2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "common/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
45 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
49 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
50 const fs_reg
*src
, unsigned sources
)
52 memset(this, 0, sizeof(*this));
54 this->src
= new fs_reg
[MAX2(sources
, 3)];
55 for (unsigned i
= 0; i
< sources
; i
++)
56 this->src
[i
] = src
[i
];
58 this->opcode
= opcode
;
60 this->sources
= sources
;
61 this->exec_size
= exec_size
;
64 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
66 assert(this->exec_size
!= 0);
68 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
70 /* This will be the case for almost all instructions. */
77 this->size_written
= dst
.component_size(exec_size
);
80 this->size_written
= 0;
84 unreachable("Invalid destination register file");
87 this->writes_accumulator
= false;
92 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
95 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
97 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
100 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
102 init(opcode
, exec_size
, dst
, NULL
, 0);
105 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
108 const fs_reg src
[1] = { src0
};
109 init(opcode
, exec_size
, dst
, src
, 1);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
113 const fs_reg
&src0
, const fs_reg
&src1
)
115 const fs_reg src
[2] = { src0
, src1
};
116 init(opcode
, exec_size
, dst
, src
, 2);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
122 const fs_reg src
[3] = { src0
, src1
, src2
};
123 init(opcode
, exec_size
, dst
, src
, 3);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
127 const fs_reg src
[], unsigned sources
)
129 init(opcode
, exec_width
, dst
, src
, sources
);
132 fs_inst::fs_inst(const fs_inst
&that
)
134 memcpy(this, &that
, sizeof(that
));
136 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
138 for (unsigned i
= 0; i
< that
.sources
; i
++)
139 this->src
[i
] = that
.src
[i
];
148 fs_inst::resize_sources(uint8_t num_sources
)
150 if (this->sources
!= num_sources
) {
151 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
153 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
154 src
[i
] = this->src
[i
];
158 this->sources
= num_sources
;
163 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
165 const fs_reg
&surf_index
,
166 const fs_reg
&varying_offset
,
167 uint32_t const_offset
)
169 /* We have our constant surface use a pitch of 4 bytes, so our index can
170 * be any component of a vector, and then we load 4 contiguous
171 * components starting from that.
173 * We break down the const_offset to a portion added to the variable offset
174 * and a portion done using fs_reg::offset, which means that if you have
175 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
176 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
177 * later notice that those loads are all the same and eliminate the
180 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
181 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
183 /* The pull load message will load a vec4 (16 bytes). If we are loading
184 * a double this means we are only loading 2 elements worth of data.
185 * We also want to use a 32-bit data type for the dst of the load operation
186 * so other parts of the driver don't get confused about the size of the
189 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
190 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
191 vec4_result
, surf_index
, vec4_offset
);
192 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
194 if (type_sz(dst
.type
) == 8) {
195 shuffle_32bit_load_result_to_64bit_data(
196 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
199 vec4_result
.type
= dst
.type
;
200 bld
.MOV(dst
, offset(vec4_result
, bld
,
201 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
205 * A helper for MOV generation for fixing up broken hardware SEND dependency
209 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
211 /* The caller always wants uncompressed to emit the minimal extra
212 * dependencies, and to avoid having to deal with aligning its regs to 2.
214 const fs_builder ubld
= bld
.annotate("send dependency resolve")
217 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
221 fs_inst::equals(fs_inst
*inst
) const
223 return (opcode
== inst
->opcode
&&
224 dst
.equals(inst
->dst
) &&
225 src
[0].equals(inst
->src
[0]) &&
226 src
[1].equals(inst
->src
[1]) &&
227 src
[2].equals(inst
->src
[2]) &&
228 saturate
== inst
->saturate
&&
229 predicate
== inst
->predicate
&&
230 conditional_mod
== inst
->conditional_mod
&&
231 mlen
== inst
->mlen
&&
232 base_mrf
== inst
->base_mrf
&&
233 target
== inst
->target
&&
235 header_size
== inst
->header_size
&&
236 shadow_compare
== inst
->shadow_compare
&&
237 exec_size
== inst
->exec_size
&&
238 offset
== inst
->offset
);
242 fs_inst::is_send_from_grf() const
245 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
246 case SHADER_OPCODE_SHADER_TIME_ADD
:
247 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
248 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
249 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
250 case SHADER_OPCODE_UNTYPED_ATOMIC
:
251 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
252 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
253 case SHADER_OPCODE_TYPED_ATOMIC
:
254 case SHADER_OPCODE_TYPED_SURFACE_READ
:
255 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
256 case SHADER_OPCODE_URB_WRITE_SIMD8
:
257 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
258 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
259 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
260 case SHADER_OPCODE_URB_READ_SIMD8
:
261 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
263 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
264 return src
[1].file
== VGRF
;
265 case FS_OPCODE_FB_WRITE
:
266 case FS_OPCODE_FB_READ
:
267 return src
[0].file
== VGRF
;
270 return src
[0].file
== VGRF
;
277 * Returns true if this instruction's sources and destinations cannot
278 * safely be the same register.
280 * In most cases, a register can be written over safely by the same
281 * instruction that is its last use. For a single instruction, the
282 * sources are dereferenced before writing of the destination starts
285 * However, there are a few cases where this can be problematic:
287 * - Virtual opcodes that translate to multiple instructions in the
288 * code generator: if src == dst and one instruction writes the
289 * destination before a later instruction reads the source, then
290 * src will have been clobbered.
292 * - SIMD16 compressed instructions with certain regioning (see below).
294 * The register allocator uses this information to set up conflicts between
295 * GRF sources and the destination.
298 fs_inst::has_source_and_destination_hazard() const
301 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
302 /* Multiple partial writes to the destination */
305 /* The SIMD16 compressed instruction
307 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
309 * is actually decoded in hardware as:
311 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
312 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
314 * Which is safe. However, if we have uniform accesses
315 * happening, we get into trouble:
317 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
318 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
320 * Now our destination for the first instruction overwrote the
321 * second instruction's src0, and we get garbage for those 8
322 * pixels. There's a similar issue for the pre-gen6
323 * pixel_x/pixel_y, which are registers of 16-bit values and thus
324 * would get stomped by the first decode as well.
326 if (exec_size
== 16) {
327 for (int i
= 0; i
< sources
; i
++) {
328 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
329 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
330 src
[i
].type
== BRW_REGISTER_TYPE_W
||
331 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
332 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
342 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
344 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
347 fs_reg reg
= this->src
[0];
348 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
351 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
354 for (int i
= 0; i
< this->sources
; i
++) {
355 reg
.type
= this->src
[i
].type
;
356 if (!this->src
[i
].equals(reg
))
359 if (i
< this->header_size
) {
360 reg
.offset
+= REG_SIZE
;
362 reg
= horiz_offset(reg
, this->exec_size
);
370 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
372 if (devinfo
->gen
== 6 && is_math())
375 if (is_send_from_grf())
378 if (!backend_instruction::can_do_source_mods())
385 fs_inst::can_change_types() const
387 return dst
.type
== src
[0].type
&&
388 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
389 (opcode
== BRW_OPCODE_MOV
||
390 (opcode
== BRW_OPCODE_SEL
&&
391 dst
.type
== src
[1].type
&&
392 predicate
!= BRW_PREDICATE_NONE
&&
393 !src
[1].abs
&& !src
[1].negate
));
399 memset(this, 0, sizeof(*this));
400 type
= BRW_REGISTER_TYPE_UD
;
404 /** Generic unset register constructor. */
408 this->file
= BAD_FILE
;
411 fs_reg::fs_reg(struct ::brw_reg reg
) :
416 if (this->file
== IMM
&&
417 (this->type
!= BRW_REGISTER_TYPE_V
&&
418 this->type
!= BRW_REGISTER_TYPE_UV
&&
419 this->type
!= BRW_REGISTER_TYPE_VF
)) {
425 fs_reg::equals(const fs_reg
&r
) const
427 return (this->backend_reg::equals(r
) &&
432 fs_reg::is_contiguous() const
438 fs_reg::component_size(unsigned width
) const
440 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
443 return MAX2(width
* stride
, 1) * type_sz(type
);
447 type_size_scalar(const struct glsl_type
*type
)
449 unsigned int size
, i
;
451 switch (type
->base_type
) {
454 case GLSL_TYPE_FLOAT
:
456 return type
->components();
457 case GLSL_TYPE_DOUBLE
:
458 case GLSL_TYPE_UINT64
:
459 case GLSL_TYPE_INT64
:
460 return type
->components() * 2;
461 case GLSL_TYPE_ARRAY
:
462 return type_size_scalar(type
->fields
.array
) * type
->length
;
463 case GLSL_TYPE_STRUCT
:
465 for (i
= 0; i
< type
->length
; i
++) {
466 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
469 case GLSL_TYPE_SAMPLER
:
470 /* Samplers take up no register space, since they're baked in at
474 case GLSL_TYPE_ATOMIC_UINT
:
476 case GLSL_TYPE_SUBROUTINE
:
478 case GLSL_TYPE_IMAGE
:
479 return BRW_IMAGE_PARAM_SIZE
;
481 case GLSL_TYPE_ERROR
:
482 case GLSL_TYPE_INTERFACE
:
483 case GLSL_TYPE_FUNCTION
:
484 unreachable("not reached");
491 * Create a MOV to read the timestamp register.
493 * The caller is responsible for emitting the MOV. The return value is
494 * the destination of the MOV, with extra parameters set.
497 fs_visitor::get_timestamp(const fs_builder
&bld
)
499 assert(devinfo
->gen
>= 7);
501 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
504 BRW_REGISTER_TYPE_UD
));
506 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
508 /* We want to read the 3 fields we care about even if it's not enabled in
511 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
517 fs_visitor::emit_shader_time_begin()
519 /* We want only the low 32 bits of the timestamp. Since it's running
520 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
521 * which is plenty of time for our purposes. It is identical across the
522 * EUs, but since it's tracking GPU core speed it will increment at a
523 * varying rate as render P-states change.
525 shader_start_time
= component(
526 get_timestamp(bld
.annotate("shader time start")), 0);
530 fs_visitor::emit_shader_time_end()
532 /* Insert our code just before the final SEND with EOT. */
533 exec_node
*end
= this->instructions
.get_tail();
534 assert(end
&& ((fs_inst
*) end
)->eot
);
535 const fs_builder ibld
= bld
.annotate("shader time end")
536 .exec_all().at(NULL
, end
);
537 const fs_reg timestamp
= get_timestamp(ibld
);
539 /* We only use the low 32 bits of the timestamp - see
540 * emit_shader_time_begin()).
542 * We could also check if render P-states have changed (or anything
543 * else that might disrupt timing) by setting smear to 2 and checking if
544 * that field is != 0.
546 const fs_reg shader_end_time
= component(timestamp
, 0);
548 /* Check that there weren't any timestamp reset events (assuming these
549 * were the only two timestamp reads that happened).
551 const fs_reg reset
= component(timestamp
, 2);
552 set_condmod(BRW_CONDITIONAL_Z
,
553 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
554 ibld
.IF(BRW_PREDICATE_NORMAL
);
556 fs_reg start
= shader_start_time
;
558 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
559 BRW_REGISTER_TYPE_UD
),
561 const fs_builder cbld
= ibld
.group(1, 0);
562 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
564 /* If there were no instructions between the two timestamp gets, the diff
565 * is 2 cycles. Remove that overhead, so I can forget about that when
566 * trying to determine the time taken for single instructions.
568 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
569 SHADER_TIME_ADD(cbld
, 0, diff
);
570 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
571 ibld
.emit(BRW_OPCODE_ELSE
);
572 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
573 ibld
.emit(BRW_OPCODE_ENDIF
);
577 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
578 int shader_time_subindex
,
581 int index
= shader_time_index
* 3 + shader_time_subindex
;
582 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
585 if (dispatch_width
== 8)
586 payload
= vgrf(glsl_type::uvec2_type
);
588 payload
= vgrf(glsl_type::uint_type
);
590 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
594 fs_visitor::vfail(const char *format
, va_list va
)
603 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
604 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
606 this->fail_msg
= msg
;
609 fprintf(stderr
, "%s", msg
);
614 fs_visitor::fail(const char *format
, ...)
618 va_start(va
, format
);
624 * Mark this program as impossible to compile with dispatch width greater
627 * During the SIMD8 compile (which happens first), we can detect and flag
628 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
629 * SIMD16+ compile altogether.
631 * During a compile of dispatch width greater than n (if one happens anyway),
632 * this just calls fail().
635 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
637 if (dispatch_width
> n
) {
640 max_dispatch_width
= n
;
641 compiler
->shader_perf_log(log_data
,
642 "Shader dispatch width limited to SIMD%d: %s",
648 * Returns true if the instruction has a flag that means it won't
649 * update an entire destination register.
651 * For example, dead code elimination and live variable analysis want to know
652 * when a write to a variable screens off any preceding values that were in
656 fs_inst::is_partial_write() const
658 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
659 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
660 !this->dst
.is_contiguous() ||
661 this->dst
.offset
% REG_SIZE
!= 0);
665 fs_inst::components_read(unsigned i
) const
667 /* Return zero if the source is not present. */
668 if (src
[i
].file
== BAD_FILE
)
672 case FS_OPCODE_LINTERP
:
678 case FS_OPCODE_PIXEL_X
:
679 case FS_OPCODE_PIXEL_Y
:
683 case FS_OPCODE_FB_WRITE_LOGICAL
:
684 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
685 /* First/second FB write color. */
687 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
691 case SHADER_OPCODE_TEX_LOGICAL
:
692 case SHADER_OPCODE_TXD_LOGICAL
:
693 case SHADER_OPCODE_TXF_LOGICAL
:
694 case SHADER_OPCODE_TXL_LOGICAL
:
695 case SHADER_OPCODE_TXS_LOGICAL
:
696 case FS_OPCODE_TXB_LOGICAL
:
697 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
698 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
699 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
700 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
701 case SHADER_OPCODE_LOD_LOGICAL
:
702 case SHADER_OPCODE_TG4_LOGICAL
:
703 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
704 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
705 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
706 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
707 /* Texture coordinates. */
708 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
709 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
710 /* Texture derivatives. */
711 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
712 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
713 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
714 /* Texture offset. */
715 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
718 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
723 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
724 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
725 assert(src
[3].file
== IMM
);
726 /* Surface coordinates. */
729 /* Surface operation source (ignored for reads). */
735 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
736 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
737 assert(src
[3].file
== IMM
&&
739 /* Surface coordinates. */
742 /* Surface operation source. */
748 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
749 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
750 assert(src
[3].file
== IMM
&&
752 const unsigned op
= src
[4].ud
;
753 /* Surface coordinates. */
756 /* Surface operation source. */
757 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
759 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
760 op
== BRW_AOP_PREDEC
))
772 fs_inst::size_read(int arg
) const
775 case FS_OPCODE_FB_WRITE
:
776 case FS_OPCODE_FB_READ
:
777 case SHADER_OPCODE_URB_WRITE_SIMD8
:
778 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
779 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
780 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
781 case SHADER_OPCODE_URB_READ_SIMD8
:
782 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
783 case SHADER_OPCODE_UNTYPED_ATOMIC
:
784 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
785 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
786 case SHADER_OPCODE_TYPED_ATOMIC
:
787 case SHADER_OPCODE_TYPED_SURFACE_READ
:
788 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
789 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
791 return mlen
* REG_SIZE
;
794 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
795 /* The payload is actually stored in src1 */
797 return mlen
* REG_SIZE
;
800 case FS_OPCODE_LINTERP
:
805 case SHADER_OPCODE_LOAD_PAYLOAD
:
806 if (arg
< this->header_size
)
810 case CS_OPCODE_CS_TERMINATE
:
811 case SHADER_OPCODE_BARRIER
:
814 case SHADER_OPCODE_MOV_INDIRECT
:
816 assert(src
[2].file
== IMM
);
822 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
823 return mlen
* REG_SIZE
;
827 switch (src
[arg
].file
) {
830 return components_read(arg
) * type_sz(src
[arg
].type
);
836 return components_read(arg
) * src
[arg
].component_size(exec_size
);
838 unreachable("MRF registers are not allowed as sources");
844 /* Return the subset of flag registers that an instruction could
845 * potentially read or write based on the execution controls and flag
846 * subregister number of the instruction.
849 flag_mask(const fs_inst
*inst
)
851 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
852 const unsigned end
= start
+ inst
->exec_size
;
853 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
859 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
863 flag_mask(const fs_reg
&r
, unsigned sz
)
866 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
867 const unsigned end
= start
+ sz
;
868 return bit_mask(end
) & ~bit_mask(start
);
876 fs_inst::flags_read(const gen_device_info
*devinfo
) const
878 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
879 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
880 /* The vertical predication modes combine corresponding bits from
881 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
883 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
884 return flag_mask(this) << shift
| flag_mask(this);
885 } else if (predicate
) {
886 return flag_mask(this);
889 for (int i
= 0; i
< sources
; i
++) {
890 mask
|= flag_mask(src
[i
], size_read(i
));
897 fs_inst::flags_written() const
899 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
900 opcode
!= BRW_OPCODE_IF
&&
901 opcode
!= BRW_OPCODE_WHILE
)) ||
902 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
903 return flag_mask(this);
905 return flag_mask(dst
, size_written
);
910 * Returns how many MRFs an FS opcode will write over.
912 * Note that this is not the 0 or 1 implied writes in an actual gen
913 * instruction -- the FS opcodes often generate MOVs in addition.
916 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
921 if (inst
->base_mrf
== -1)
924 switch (inst
->opcode
) {
925 case SHADER_OPCODE_RCP
:
926 case SHADER_OPCODE_RSQ
:
927 case SHADER_OPCODE_SQRT
:
928 case SHADER_OPCODE_EXP2
:
929 case SHADER_OPCODE_LOG2
:
930 case SHADER_OPCODE_SIN
:
931 case SHADER_OPCODE_COS
:
932 return 1 * dispatch_width
/ 8;
933 case SHADER_OPCODE_POW
:
934 case SHADER_OPCODE_INT_QUOTIENT
:
935 case SHADER_OPCODE_INT_REMAINDER
:
936 return 2 * dispatch_width
/ 8;
937 case SHADER_OPCODE_TEX
:
939 case SHADER_OPCODE_TXD
:
940 case SHADER_OPCODE_TXF
:
941 case SHADER_OPCODE_TXF_CMS
:
942 case SHADER_OPCODE_TXF_MCS
:
943 case SHADER_OPCODE_TG4
:
944 case SHADER_OPCODE_TG4_OFFSET
:
945 case SHADER_OPCODE_TXL
:
946 case SHADER_OPCODE_TXS
:
947 case SHADER_OPCODE_LOD
:
948 case SHADER_OPCODE_SAMPLEINFO
:
950 case FS_OPCODE_FB_WRITE
:
952 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
953 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
955 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
957 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
960 unreachable("not reached");
965 fs_visitor::vgrf(const glsl_type
*const type
)
967 int reg_width
= dispatch_width
/ 8;
968 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
969 brw_type_for_base_type(type
));
972 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
977 this->type
= BRW_REGISTER_TYPE_F
;
978 this->stride
= (file
== UNIFORM
? 0 : 1);
981 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
987 this->stride
= (file
== UNIFORM
? 0 : 1);
990 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
991 * This brings in those uniform definitions
994 fs_visitor::import_uniforms(fs_visitor
*v
)
996 this->push_constant_loc
= v
->push_constant_loc
;
997 this->pull_constant_loc
= v
->pull_constant_loc
;
998 this->uniforms
= v
->uniforms
;
1002 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1004 assert(stage
== MESA_SHADER_FRAGMENT
);
1006 /* gl_FragCoord.x */
1007 bld
.MOV(wpos
, this->pixel_x
);
1008 wpos
= offset(wpos
, bld
, 1);
1010 /* gl_FragCoord.y */
1011 bld
.MOV(wpos
, this->pixel_y
);
1012 wpos
= offset(wpos
, bld
, 1);
1014 /* gl_FragCoord.z */
1015 if (devinfo
->gen
>= 6) {
1016 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1018 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1019 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1020 interp_reg(VARYING_SLOT_POS
, 2));
1022 wpos
= offset(wpos
, bld
, 1);
1024 /* gl_FragCoord.w: Already set up in emit_interpolation */
1025 bld
.MOV(wpos
, this->wpos_w
);
1028 enum brw_barycentric_mode
1029 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1031 /* Barycentric modes don't make sense for flat inputs. */
1032 assert(mode
!= INTERP_MODE_FLAT
);
1036 case nir_intrinsic_load_barycentric_pixel
:
1037 case nir_intrinsic_load_barycentric_at_offset
:
1038 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1040 case nir_intrinsic_load_barycentric_centroid
:
1041 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1043 case nir_intrinsic_load_barycentric_sample
:
1044 case nir_intrinsic_load_barycentric_at_sample
:
1045 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1048 unreachable("invalid intrinsic");
1051 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1054 return (enum brw_barycentric_mode
) bary
;
1058 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1060 static enum brw_barycentric_mode
1061 centroid_to_pixel(enum brw_barycentric_mode bary
)
1063 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1064 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1065 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1069 fs_visitor::emit_frontfacing_interpolation()
1071 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1073 if (devinfo
->gen
>= 6) {
1074 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1075 * a boolean result from this (~0/true or 0/false).
1077 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1078 * this task in only one instruction:
1079 * - a negation source modifier will flip the bit; and
1080 * - a W -> D type conversion will sign extend the bit into the high
1081 * word of the destination.
1083 * An ASR 15 fills the low word of the destination.
1085 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1088 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1090 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1091 * a boolean result from this (1/true or 0/false).
1093 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1094 * the negation source modifier to flip it. Unfortunately the SHR
1095 * instruction only operates on UD (or D with an abs source modifier)
1096 * sources without negation.
1098 * Instead, use ASR (which will give ~0/true or 0/false).
1100 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1103 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1110 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1112 assert(stage
== MESA_SHADER_FRAGMENT
);
1113 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1114 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1116 if (wm_prog_data
->persample_dispatch
) {
1117 /* Convert int_sample_pos to floating point */
1118 bld
.MOV(dst
, int_sample_pos
);
1119 /* Scale to the range [0, 1] */
1120 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1123 /* From ARB_sample_shading specification:
1124 * "When rendering to a non-multisample buffer, or if multisample
1125 * rasterization is disabled, gl_SamplePosition will always be
1128 bld
.MOV(dst
, brw_imm_f(0.5f
));
1133 fs_visitor::emit_samplepos_setup()
1135 assert(devinfo
->gen
>= 6);
1137 const fs_builder abld
= bld
.annotate("compute sample position");
1138 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1140 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1141 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1143 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1144 * mode will be enabled.
1146 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1147 * R31.1:0 Position Offset X/Y for Slot[3:0]
1148 * R31.3:2 Position Offset X/Y for Slot[7:4]
1151 * The X, Y sample positions come in as bytes in thread payload. So, read
1152 * the positions using vstride=16, width=8, hstride=2.
1154 struct brw_reg sample_pos_reg
=
1155 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1156 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1158 if (dispatch_width
== 8) {
1159 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1161 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1162 abld
.half(1).MOV(half(int_sample_x
, 1),
1163 fs_reg(suboffset(sample_pos_reg
, 16)));
1165 /* Compute gl_SamplePosition.x */
1166 compute_sample_position(pos
, int_sample_x
);
1167 pos
= offset(pos
, abld
, 1);
1168 if (dispatch_width
== 8) {
1169 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1171 abld
.half(0).MOV(half(int_sample_y
, 0),
1172 fs_reg(suboffset(sample_pos_reg
, 1)));
1173 abld
.half(1).MOV(half(int_sample_y
, 1),
1174 fs_reg(suboffset(sample_pos_reg
, 17)));
1176 /* Compute gl_SamplePosition.y */
1177 compute_sample_position(pos
, int_sample_y
);
1182 fs_visitor::emit_sampleid_setup()
1184 assert(stage
== MESA_SHADER_FRAGMENT
);
1185 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1186 assert(devinfo
->gen
>= 6);
1188 const fs_builder abld
= bld
.annotate("compute sample id");
1189 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1191 if (!key
->multisample_fbo
) {
1192 /* As per GL_ARB_sample_shading specification:
1193 * "When rendering to a non-multisample buffer, or if multisample
1194 * rasterization is disabled, gl_SampleID will always be zero."
1196 abld
.MOV(*reg
, brw_imm_d(0));
1197 } else if (devinfo
->gen
>= 8) {
1198 /* Sample ID comes in as 4-bit numbers in g1.0:
1200 * 15:12 Slot 3 SampleID (only used in SIMD16)
1201 * 11:8 Slot 2 SampleID (only used in SIMD16)
1202 * 7:4 Slot 1 SampleID
1203 * 3:0 Slot 0 SampleID
1205 * Each slot corresponds to four channels, so we want to replicate each
1206 * half-byte value to 4 channels in a row:
1208 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1209 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1211 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1212 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1214 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1215 * channels to read the first byte (7:0), and the second group of 8
1216 * channels to read the second byte (15:8). Then, we shift right by
1217 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1218 * values into place. Finally, we AND with 0xf to keep the low nibble.
1220 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1221 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1223 * TODO: These payload bits exist on Gen7 too, but they appear to always
1224 * be zero, so this code fails to work. We should find out why.
1226 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1228 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1229 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1230 brw_imm_v(0x44440000));
1231 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1233 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1234 BRW_REGISTER_TYPE_D
), 0);
1235 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1237 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1238 * 8x multisampling, subspan 0 will represent sample N (where N
1239 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1240 * 7. We can find the value of N by looking at R0.0 bits 7:6
1241 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1242 * (since samples are always delivered in pairs). That is, we
1243 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1244 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1245 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1246 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1247 * populating a temporary variable with the sequence (0, 1, 2, 3),
1248 * and then reading from it using vstride=1, width=4, hstride=0.
1249 * These computations hold good for 4x multisampling as well.
1251 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1252 * the first four slots are sample 0 of subspan 0; the next four
1253 * are sample 1 of subspan 0; the third group is sample 0 of
1254 * subspan 1, and finally sample 1 of subspan 1.
1257 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1258 * accomodate 16x MSAA.
1260 abld
.exec_all().group(1, 0)
1261 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1263 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1265 /* This works for both SIMD8 and SIMD16 */
1266 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1268 /* This special instruction takes care of setting vstride=1,
1269 * width=4, hstride=0 of t2 during an ADD instruction.
1271 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1278 fs_visitor::emit_samplemaskin_setup()
1280 assert(stage
== MESA_SHADER_FRAGMENT
);
1281 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1282 assert(devinfo
->gen
>= 6);
1284 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1286 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1287 BRW_REGISTER_TYPE_D
));
1289 if (wm_prog_data
->persample_dispatch
) {
1290 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1291 * and a mask representing which sample is being processed by the
1292 * current shader invocation.
1294 * From the OES_sample_variables specification:
1295 * "When per-sample shading is active due to the use of a fragment input
1296 * qualified by "sample" or due to the use of the gl_SampleID or
1297 * gl_SamplePosition variables, only the bit for the current sample is
1298 * set in gl_SampleMaskIn."
1300 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1302 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1303 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1305 fs_reg one
= vgrf(glsl_type::int_type
);
1306 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1307 abld
.MOV(one
, brw_imm_d(1));
1308 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1309 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1311 /* In per-pixel mode, the coverage mask is sufficient. */
1312 *reg
= coverage_mask
;
1318 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1320 if (!src
.abs
&& !src
.negate
)
1323 fs_reg temp
= bld
.vgrf(src
.type
);
1330 fs_visitor::emit_discard_jump()
1332 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1334 /* For performance, after a discard, jump to the end of the
1335 * shader if all relevant channels have been discarded.
1337 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1338 discard_jump
->flag_subreg
= 1;
1340 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1341 discard_jump
->predicate_inverse
= true;
1345 fs_visitor::emit_gs_thread_end()
1347 assert(stage
== MESA_SHADER_GEOMETRY
);
1349 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1351 if (gs_compile
->control_data_header_size_bits
> 0) {
1352 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1355 const fs_builder abld
= bld
.annotate("thread end");
1358 if (gs_prog_data
->static_vertex_count
!= -1) {
1359 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1360 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1361 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1362 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1363 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1366 /* Delete now dead instructions. */
1367 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1373 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1377 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1378 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1379 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1382 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1383 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1384 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1385 sources
[1] = this->final_gs_vertex_count
;
1386 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1387 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1395 fs_visitor::assign_curb_setup()
1397 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1399 unsigned ubo_push_length
= 0;
1400 unsigned ubo_push_start
[4];
1401 for (int i
= 0; i
< 4; i
++) {
1402 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1403 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1406 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1408 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1409 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1410 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1411 if (inst
->src
[i
].file
== UNIFORM
) {
1412 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1414 if (inst
->src
[i
].nr
>= UBO_START
) {
1415 /* constant_nr is in 32-bit units, the rest are in bytes */
1416 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1417 inst
->src
[i
].offset
/ 4;
1418 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1419 constant_nr
= push_constant_loc
[uniform_nr
];
1421 /* Section 5.11 of the OpenGL 4.1 spec says:
1422 * "Out-of-bounds reads return undefined values, which include
1423 * values from other variables of the active program or zero."
1424 * Just return the first push constant.
1429 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1432 brw_reg
.abs
= inst
->src
[i
].abs
;
1433 brw_reg
.negate
= inst
->src
[i
].negate
;
1435 assert(inst
->src
[i
].stride
== 0);
1436 inst
->src
[i
] = byte_offset(
1437 retype(brw_reg
, inst
->src
[i
].type
),
1438 inst
->src
[i
].offset
% 4);
1443 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1444 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1448 fs_visitor::calculate_urb_setup()
1450 assert(stage
== MESA_SHADER_FRAGMENT
);
1451 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1452 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1454 memset(prog_data
->urb_setup
, -1,
1455 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1458 /* Figure out where each of the incoming setup attributes lands. */
1459 if (devinfo
->gen
>= 6) {
1460 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1461 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1462 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1463 * first 16 varying inputs, so we can put them wherever we want.
1464 * Just put them in order.
1466 * This is useful because it means that (a) inputs not used by the
1467 * fragment shader won't take up valuable register space, and (b) we
1468 * won't have to recompile the fragment shader if it gets paired with
1469 * a different vertex (or geometry) shader.
1471 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1472 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1473 BITFIELD64_BIT(i
)) {
1474 prog_data
->urb_setup
[i
] = urb_next
++;
1478 /* We have enough input varyings that the SF/SBE pipeline stage can't
1479 * arbitrarily rearrange them to suit our whim; we have to put them
1480 * in an order that matches the output of the previous pipeline stage
1481 * (geometry or vertex shader).
1483 struct brw_vue_map prev_stage_vue_map
;
1484 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1485 key
->input_slots_valid
,
1486 nir
->info
.separate_shader
);
1489 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1490 &prev_stage_vue_map
);
1492 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1493 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1495 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1496 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1497 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1498 BITFIELD64_BIT(varying
))) {
1499 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1502 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1505 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1506 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1507 /* Point size is packed into the header, not as a general attribute */
1508 if (i
== VARYING_SLOT_PSIZ
)
1511 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1512 /* The back color slot is skipped when the front color is
1513 * also written to. In addition, some slots can be
1514 * written in the vertex shader and not read in the
1515 * fragment shader. So the register number must always be
1516 * incremented, mapped or not.
1518 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1519 prog_data
->urb_setup
[i
] = urb_next
;
1525 * It's a FS only attribute, and we did interpolation for this attribute
1526 * in SF thread. So, count it here, too.
1528 * See compile_sf_prog() for more info.
1530 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1531 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1534 prog_data
->num_varying_inputs
= urb_next
;
1538 fs_visitor::assign_urb_setup()
1540 assert(stage
== MESA_SHADER_FRAGMENT
);
1541 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1543 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1545 /* Offset all the urb_setup[] index by the actual position of the
1546 * setup regs, now that the location of the constants has been chosen.
1548 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1549 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1550 assert(inst
->src
[1].file
== FIXED_GRF
);
1551 inst
->src
[1].nr
+= urb_start
;
1554 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1555 assert(inst
->src
[0].file
== FIXED_GRF
);
1556 inst
->src
[0].nr
+= urb_start
;
1560 /* Each attribute is 4 setup channels, each of which is half a reg. */
1561 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1565 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1567 for (int i
= 0; i
< inst
->sources
; i
++) {
1568 if (inst
->src
[i
].file
== ATTR
) {
1569 int grf
= payload
.num_regs
+
1570 prog_data
->curb_read_length
+
1572 inst
->src
[i
].offset
/ REG_SIZE
;
1574 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1576 * VertStride must be used to cross GRF register boundaries. This
1577 * rule implies that elements within a 'Width' cannot cross GRF
1580 * So, for registers that are large enough, we have to split the exec
1581 * size in two and trust the compression state to sort it out.
1583 unsigned total_size
= inst
->exec_size
*
1584 inst
->src
[i
].stride
*
1585 type_sz(inst
->src
[i
].type
);
1587 assert(total_size
<= 2 * REG_SIZE
);
1588 const unsigned exec_size
=
1589 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1591 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1592 struct brw_reg reg
=
1593 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1594 inst
->src
[i
].offset
% REG_SIZE
),
1595 exec_size
* inst
->src
[i
].stride
,
1596 width
, inst
->src
[i
].stride
);
1597 reg
.abs
= inst
->src
[i
].abs
;
1598 reg
.negate
= inst
->src
[i
].negate
;
1606 fs_visitor::assign_vs_urb_setup()
1608 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1610 assert(stage
== MESA_SHADER_VERTEX
);
1612 /* Each attribute is 4 regs. */
1613 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1615 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1617 /* Rewrite all ATTR file references to the hw grf that they land in. */
1618 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1619 convert_attr_sources_to_hw_regs(inst
);
1624 fs_visitor::assign_tcs_single_patch_urb_setup()
1626 assert(stage
== MESA_SHADER_TESS_CTRL
);
1628 /* Rewrite all ATTR file references to HW_REGs. */
1629 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1630 convert_attr_sources_to_hw_regs(inst
);
1635 fs_visitor::assign_tes_urb_setup()
1637 assert(stage
== MESA_SHADER_TESS_EVAL
);
1639 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1641 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1643 /* Rewrite all ATTR file references to HW_REGs. */
1644 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1645 convert_attr_sources_to_hw_regs(inst
);
1650 fs_visitor::assign_gs_urb_setup()
1652 assert(stage
== MESA_SHADER_GEOMETRY
);
1654 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1656 first_non_payload_grf
+=
1657 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1659 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1660 /* Rewrite all ATTR file references to GRFs. */
1661 convert_attr_sources_to_hw_regs(inst
);
1667 * Split large virtual GRFs into separate components if we can.
1669 * This is mostly duplicated with what brw_fs_vector_splitting does,
1670 * but that's really conservative because it's afraid of doing
1671 * splitting that doesn't result in real progress after the rest of
1672 * the optimization phases, which would cause infinite looping in
1673 * optimization. We can do it once here, safely. This also has the
1674 * opportunity to split interpolated values, or maybe even uniforms,
1675 * which we don't have at the IR level.
1677 * We want to split, because virtual GRFs are what we register
1678 * allocate and spill (due to contiguousness requirements for some
1679 * instructions), and they're what we naturally generate in the
1680 * codegen process, but most virtual GRFs don't actually need to be
1681 * contiguous sets of GRFs. If we split, we'll end up with reduced
1682 * live intervals and better dead code elimination and coalescing.
1685 fs_visitor::split_virtual_grfs()
1687 /* Compact the register file so we eliminate dead vgrfs. This
1688 * only defines split points for live registers, so if we have
1689 * too large dead registers they will hit assertions later.
1691 compact_virtual_grfs();
1693 int num_vars
= this->alloc
.count
;
1695 /* Count the total number of registers */
1697 int vgrf_to_reg
[num_vars
];
1698 for (int i
= 0; i
< num_vars
; i
++) {
1699 vgrf_to_reg
[i
] = reg_count
;
1700 reg_count
+= alloc
.sizes
[i
];
1703 /* An array of "split points". For each register slot, this indicates
1704 * if this slot can be separated from the previous slot. Every time an
1705 * instruction uses multiple elements of a register (as a source or
1706 * destination), we mark the used slots as inseparable. Then we go
1707 * through and split the registers into the smallest pieces we can.
1709 bool split_points
[reg_count
];
1710 memset(split_points
, 0, sizeof(split_points
));
1712 /* Mark all used registers as fully splittable */
1713 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1714 if (inst
->dst
.file
== VGRF
) {
1715 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1716 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1717 split_points
[reg
+ j
] = true;
1720 for (int i
= 0; i
< inst
->sources
; i
++) {
1721 if (inst
->src
[i
].file
== VGRF
) {
1722 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1723 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1724 split_points
[reg
+ j
] = true;
1729 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1730 if (inst
->dst
.file
== VGRF
) {
1731 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1732 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1733 split_points
[reg
+ j
] = false;
1735 for (int i
= 0; i
< inst
->sources
; i
++) {
1736 if (inst
->src
[i
].file
== VGRF
) {
1737 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1738 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1739 split_points
[reg
+ j
] = false;
1744 int new_virtual_grf
[reg_count
];
1745 int new_reg_offset
[reg_count
];
1748 for (int i
= 0; i
< num_vars
; i
++) {
1749 /* The first one should always be 0 as a quick sanity check. */
1750 assert(split_points
[reg
] == false);
1753 new_reg_offset
[reg
] = 0;
1758 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1759 /* If this is a split point, reset the offset to 0 and allocate a
1760 * new virtual GRF for the previous offset many registers
1762 if (split_points
[reg
]) {
1763 assert(offset
<= MAX_VGRF_SIZE
);
1764 int grf
= alloc
.allocate(offset
);
1765 for (int k
= reg
- offset
; k
< reg
; k
++)
1766 new_virtual_grf
[k
] = grf
;
1769 new_reg_offset
[reg
] = offset
;
1774 /* The last one gets the original register number */
1775 assert(offset
<= MAX_VGRF_SIZE
);
1776 alloc
.sizes
[i
] = offset
;
1777 for (int k
= reg
- offset
; k
< reg
; k
++)
1778 new_virtual_grf
[k
] = i
;
1780 assert(reg
== reg_count
);
1782 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1783 if (inst
->dst
.file
== VGRF
) {
1784 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1785 inst
->dst
.nr
= new_virtual_grf
[reg
];
1786 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1787 inst
->dst
.offset
% REG_SIZE
;
1788 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1790 for (int i
= 0; i
< inst
->sources
; i
++) {
1791 if (inst
->src
[i
].file
== VGRF
) {
1792 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1793 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1794 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1795 inst
->src
[i
].offset
% REG_SIZE
;
1796 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1800 invalidate_live_intervals();
1804 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1806 * During code generation, we create tons of temporary variables, many of
1807 * which get immediately killed and are never used again. Yet, in later
1808 * optimization and analysis passes, such as compute_live_intervals, we need
1809 * to loop over all the virtual GRFs. Compacting them can save a lot of
1813 fs_visitor::compact_virtual_grfs()
1815 bool progress
= false;
1816 int remap_table
[this->alloc
.count
];
1817 memset(remap_table
, -1, sizeof(remap_table
));
1819 /* Mark which virtual GRFs are used. */
1820 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1821 if (inst
->dst
.file
== VGRF
)
1822 remap_table
[inst
->dst
.nr
] = 0;
1824 for (int i
= 0; i
< inst
->sources
; i
++) {
1825 if (inst
->src
[i
].file
== VGRF
)
1826 remap_table
[inst
->src
[i
].nr
] = 0;
1830 /* Compact the GRF arrays. */
1832 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1833 if (remap_table
[i
] == -1) {
1834 /* We just found an unused register. This means that we are
1835 * actually going to compact something.
1839 remap_table
[i
] = new_index
;
1840 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1841 invalidate_live_intervals();
1846 this->alloc
.count
= new_index
;
1848 /* Patch all the instructions to use the newly renumbered registers */
1849 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1850 if (inst
->dst
.file
== VGRF
)
1851 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1853 for (int i
= 0; i
< inst
->sources
; i
++) {
1854 if (inst
->src
[i
].file
== VGRF
)
1855 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1859 /* Patch all the references to delta_xy, since they're used in register
1860 * allocation. If they're unused, switch them to BAD_FILE so we don't
1861 * think some random VGRF is delta_xy.
1863 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1864 if (delta_xy
[i
].file
== VGRF
) {
1865 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1866 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1868 delta_xy
[i
].file
= BAD_FILE
;
1877 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
,
1878 unsigned *max_chunk_bitsize
,
1879 bool contiguous
, unsigned bitsize
,
1880 const unsigned target_bitsize
,
1881 int *push_constant_loc
, int *pull_constant_loc
,
1882 unsigned *num_push_constants
,
1883 unsigned *num_pull_constants
,
1884 const unsigned max_push_components
,
1885 const unsigned max_chunk_size
,
1886 bool allow_pull_constants
,
1887 struct brw_stage_prog_data
*stage_prog_data
)
1889 /* This is the first live uniform in the chunk */
1890 if (*chunk_start
< 0)
1891 *chunk_start
= uniform
;
1893 /* Keep track of the maximum bit size access in contiguous uniforms */
1894 *max_chunk_bitsize
= MAX2(*max_chunk_bitsize
, bitsize
);
1896 /* If this element does not need to be contiguous with the next, we
1897 * split at this point and everything between chunk_start and u forms a
1901 /* If bitsize doesn't match the target one, skip it */
1902 if (*max_chunk_bitsize
!= target_bitsize
) {
1903 /* FIXME: right now we only support 32 and 64-bit accesses */
1904 assert(*max_chunk_bitsize
== 4 || *max_chunk_bitsize
== 8);
1905 *max_chunk_bitsize
= 0;
1910 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1912 /* Decide whether we should push or pull this parameter. In the
1913 * Vulkan driver, push constants are explicitly exposed via the API
1914 * so we push everything. In GL, we only push small arrays.
1916 if (!allow_pull_constants
||
1917 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1918 chunk_size
<= max_chunk_size
)) {
1919 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1920 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1921 push_constant_loc
[j
] = (*num_push_constants
)++;
1923 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1924 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1927 *max_chunk_bitsize
= 0;
1933 get_thread_local_id_param_index(const brw_stage_prog_data
*prog_data
)
1935 if (prog_data
->nr_params
== 0)
1938 /* The local thread id is always the last parameter in the list */
1939 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
1940 if (last_param
== BRW_PARAM_BUILTIN_THREAD_LOCAL_ID
)
1941 return prog_data
->nr_params
- 1;
1947 * Assign UNIFORM file registers to either push constants or pull constants.
1949 * We allow a fragment shader to have more than the specified minimum
1950 * maximum number of fragment shader uniform components (64). If
1951 * there are too many of these, they'd fill up all of register space.
1952 * So, this will push some of them out to the pull constant buffer and
1953 * update the program to load them.
1956 fs_visitor::assign_constant_locations()
1958 /* Only the first compile gets to decide on locations. */
1959 if (dispatch_width
!= min_dispatch_width
)
1962 bool is_live
[uniforms
];
1963 memset(is_live
, 0, sizeof(is_live
));
1964 unsigned bitsize_access
[uniforms
];
1965 memset(bitsize_access
, 0, sizeof(bitsize_access
));
1967 /* For each uniform slot, a value of true indicates that the given slot and
1968 * the next slot must remain contiguous. This is used to keep us from
1969 * splitting arrays apart.
1971 bool contiguous
[uniforms
];
1972 memset(contiguous
, 0, sizeof(contiguous
));
1974 /* First, we walk through the instructions and do two things:
1976 * 1) Figure out which uniforms are live.
1978 * 2) Mark any indirectly used ranges of registers as contiguous.
1980 * Note that we don't move constant-indexed accesses to arrays. No
1981 * testing has been done of the performance impact of this choice.
1983 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1984 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1985 if (inst
->src
[i
].file
!= UNIFORM
)
1988 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1990 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1991 assert(inst
->src
[2].ud
% 4 == 0);
1992 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1993 assert(last
< uniforms
);
1995 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1997 contiguous
[j
] = true;
1998 bitsize_access
[j
] = MAX2(bitsize_access
[j
], type_sz(inst
->src
[i
].type
));
2000 is_live
[last
] = true;
2001 bitsize_access
[last
] = MAX2(bitsize_access
[last
], type_sz(inst
->src
[i
].type
));
2003 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2004 int regs_read
= inst
->components_read(i
) *
2005 type_sz(inst
->src
[i
].type
) / 4;
2006 for (int j
= 0; j
< regs_read
; j
++) {
2007 is_live
[constant_nr
+ j
] = true;
2008 bitsize_access
[constant_nr
+ j
] =
2009 MAX2(bitsize_access
[constant_nr
+ j
], type_sz(inst
->src
[i
].type
));
2016 int thread_local_id_index
= get_thread_local_id_param_index(stage_prog_data
);
2018 /* Only allow 16 registers (128 uniform components) as push constants.
2020 * Just demote the end of the list. We could probably do better
2021 * here, demoting things that are rarely used in the program first.
2023 * If changing this value, note the limitation about total_regs in
2026 unsigned int max_push_components
= 16 * 8;
2027 if (thread_local_id_index
>= 0)
2028 max_push_components
--; /* Save a slot for the thread ID */
2030 /* We push small arrays, but no bigger than 16 floats. This is big enough
2031 * for a vec4 but hopefully not large enough to push out other stuff. We
2032 * should probably use a better heuristic at some point.
2034 const unsigned int max_chunk_size
= 16;
2036 unsigned int num_push_constants
= 0;
2037 unsigned int num_pull_constants
= 0;
2039 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2040 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2042 /* Default to -1 meaning no location */
2043 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2044 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2046 int chunk_start
= -1;
2047 unsigned max_chunk_bitsize
= 0;
2049 /* First push 64-bit uniforms to ensure they are properly aligned */
2050 const unsigned uniform_64_bit_size
= type_sz(BRW_REGISTER_TYPE_DF
);
2051 for (unsigned u
= 0; u
< uniforms
; u
++) {
2055 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2056 contiguous
[u
], bitsize_access
[u
],
2057 uniform_64_bit_size
,
2058 push_constant_loc
, pull_constant_loc
,
2059 &num_push_constants
, &num_pull_constants
,
2060 max_push_components
, max_chunk_size
,
2061 compiler
->supports_pull_constants
,
2066 /* Then push the rest of uniforms */
2067 const unsigned uniform_32_bit_size
= type_sz(BRW_REGISTER_TYPE_F
);
2068 for (unsigned u
= 0; u
< uniforms
; u
++) {
2072 /* Skip thread_local_id_index to put it in the last push register. */
2073 if (thread_local_id_index
== (int)u
)
2076 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2077 contiguous
[u
], bitsize_access
[u
],
2078 uniform_32_bit_size
,
2079 push_constant_loc
, pull_constant_loc
,
2080 &num_push_constants
, &num_pull_constants
,
2081 max_push_components
, max_chunk_size
,
2082 compiler
->supports_pull_constants
,
2086 /* Add the CS local thread ID uniform at the end of the push constants */
2087 if (thread_local_id_index
>= 0)
2088 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2090 /* As the uniforms are going to be reordered, stash the old array and
2091 * create two new arrays for push/pull params.
2093 uint32_t *param
= stage_prog_data
->param
;
2094 stage_prog_data
->nr_params
= num_push_constants
;
2095 if (num_push_constants
) {
2096 stage_prog_data
->param
= ralloc_array(mem_ctx
, uint32_t,
2097 num_push_constants
);
2099 stage_prog_data
->param
= NULL
;
2101 assert(stage_prog_data
->nr_pull_params
== 0);
2102 assert(stage_prog_data
->pull_param
== NULL
);
2103 if (num_pull_constants
> 0) {
2104 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2105 stage_prog_data
->pull_param
= ralloc_array(mem_ctx
, uint32_t,
2106 num_pull_constants
);
2109 /* Now that we know how many regular uniforms we'll push, reduce the
2110 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2112 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2113 for (int i
= 0; i
< 4; i
++) {
2114 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2116 if (push_length
+ range
->length
> 64)
2117 range
->length
= 64 - push_length
;
2119 push_length
+= range
->length
;
2121 assert(push_length
<= 64);
2123 /* Up until now, the param[] array has been indexed by reg + offset
2124 * of UNIFORM registers. Move pull constants into pull_param[] and
2125 * condense param[] to only contain the uniforms we chose to push.
2127 * NOTE: Because we are condensing the params[] array, we know that
2128 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2129 * having to make a copy.
2131 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2132 uint32_t value
= param
[i
];
2133 if (pull_constant_loc
[i
] != -1) {
2134 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2135 } else if (push_constant_loc
[i
] != -1) {
2136 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2143 fs_visitor::get_pull_locs(const fs_reg
&src
,
2144 unsigned *out_surf_index
,
2145 unsigned *out_pull_index
)
2147 assert(src
.file
== UNIFORM
);
2149 if (src
.nr
>= UBO_START
) {
2150 const struct brw_ubo_range
*range
=
2151 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2153 /* If this access is in our (reduced) range, use the push data. */
2154 if (src
.offset
/ 32 < range
->length
)
2157 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2158 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2162 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2164 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2165 /* A regular uniform push constant */
2166 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2167 *out_pull_index
= pull_constant_loc
[location
];
2175 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2176 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2179 fs_visitor::lower_constant_loads()
2181 unsigned index
, pull_index
;
2183 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2184 /* Set up the annotation tracking for new generated instructions. */
2185 const fs_builder
ibld(this, block
, inst
);
2187 for (int i
= 0; i
< inst
->sources
; i
++) {
2188 if (inst
->src
[i
].file
!= UNIFORM
)
2191 /* We'll handle this case later */
2192 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2195 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2198 assert(inst
->src
[i
].stride
== 0);
2200 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2201 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2202 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2203 const unsigned base
= pull_index
* 4;
2205 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2206 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2208 /* Rewrite the instruction to use the temporary VGRF. */
2209 inst
->src
[i
].file
= VGRF
;
2210 inst
->src
[i
].nr
= dst
.nr
;
2211 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2212 inst
->src
[i
].offset
% 4;
2214 brw_mark_surface_used(prog_data
, index
);
2217 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2218 inst
->src
[0].file
== UNIFORM
) {
2220 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2223 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2227 inst
->remove(block
);
2229 brw_mark_surface_used(prog_data
, index
);
2232 invalidate_live_intervals();
2236 fs_visitor::opt_algebraic()
2238 bool progress
= false;
2240 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2241 switch (inst
->opcode
) {
2242 case BRW_OPCODE_MOV
:
2243 if (inst
->src
[0].file
!= IMM
)
2246 if (inst
->saturate
) {
2247 if (inst
->dst
.type
!= inst
->src
[0].type
)
2248 assert(!"unimplemented: saturate mixed types");
2250 if (brw_saturate_immediate(inst
->dst
.type
,
2251 &inst
->src
[0].as_brw_reg())) {
2252 inst
->saturate
= false;
2258 case BRW_OPCODE_MUL
:
2259 if (inst
->src
[1].file
!= IMM
)
2263 if (inst
->src
[1].is_one()) {
2264 inst
->opcode
= BRW_OPCODE_MOV
;
2265 inst
->src
[1] = reg_undef
;
2271 if (inst
->src
[1].is_negative_one()) {
2272 inst
->opcode
= BRW_OPCODE_MOV
;
2273 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2274 inst
->src
[1] = reg_undef
;
2280 if (inst
->src
[1].is_zero()) {
2281 inst
->opcode
= BRW_OPCODE_MOV
;
2282 inst
->src
[0] = inst
->src
[1];
2283 inst
->src
[1] = reg_undef
;
2288 if (inst
->src
[0].file
== IMM
) {
2289 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2290 inst
->opcode
= BRW_OPCODE_MOV
;
2291 inst
->src
[0].f
*= inst
->src
[1].f
;
2292 inst
->src
[1] = reg_undef
;
2297 case BRW_OPCODE_ADD
:
2298 if (inst
->src
[1].file
!= IMM
)
2302 if (inst
->src
[1].is_zero()) {
2303 inst
->opcode
= BRW_OPCODE_MOV
;
2304 inst
->src
[1] = reg_undef
;
2309 if (inst
->src
[0].file
== IMM
) {
2310 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2311 inst
->opcode
= BRW_OPCODE_MOV
;
2312 inst
->src
[0].f
+= inst
->src
[1].f
;
2313 inst
->src
[1] = reg_undef
;
2319 if (inst
->src
[0].equals(inst
->src
[1])) {
2320 inst
->opcode
= BRW_OPCODE_MOV
;
2321 inst
->src
[1] = reg_undef
;
2326 case BRW_OPCODE_LRP
:
2327 if (inst
->src
[1].equals(inst
->src
[2])) {
2328 inst
->opcode
= BRW_OPCODE_MOV
;
2329 inst
->src
[0] = inst
->src
[1];
2330 inst
->src
[1] = reg_undef
;
2331 inst
->src
[2] = reg_undef
;
2336 case BRW_OPCODE_CMP
:
2337 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2339 inst
->src
[0].negate
&&
2340 inst
->src
[1].is_zero()) {
2341 inst
->src
[0].abs
= false;
2342 inst
->src
[0].negate
= false;
2343 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2348 case BRW_OPCODE_SEL
:
2349 if (inst
->src
[0].equals(inst
->src
[1])) {
2350 inst
->opcode
= BRW_OPCODE_MOV
;
2351 inst
->src
[1] = reg_undef
;
2352 inst
->predicate
= BRW_PREDICATE_NONE
;
2353 inst
->predicate_inverse
= false;
2355 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2356 switch (inst
->conditional_mod
) {
2357 case BRW_CONDITIONAL_LE
:
2358 case BRW_CONDITIONAL_L
:
2359 switch (inst
->src
[1].type
) {
2360 case BRW_REGISTER_TYPE_F
:
2361 if (inst
->src
[1].f
>= 1.0f
) {
2362 inst
->opcode
= BRW_OPCODE_MOV
;
2363 inst
->src
[1] = reg_undef
;
2364 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2372 case BRW_CONDITIONAL_GE
:
2373 case BRW_CONDITIONAL_G
:
2374 switch (inst
->src
[1].type
) {
2375 case BRW_REGISTER_TYPE_F
:
2376 if (inst
->src
[1].f
<= 0.0f
) {
2377 inst
->opcode
= BRW_OPCODE_MOV
;
2378 inst
->src
[1] = reg_undef
;
2379 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2391 case BRW_OPCODE_MAD
:
2392 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2393 inst
->opcode
= BRW_OPCODE_MOV
;
2394 inst
->src
[1] = reg_undef
;
2395 inst
->src
[2] = reg_undef
;
2397 } else if (inst
->src
[0].is_zero()) {
2398 inst
->opcode
= BRW_OPCODE_MUL
;
2399 inst
->src
[0] = inst
->src
[2];
2400 inst
->src
[2] = reg_undef
;
2402 } else if (inst
->src
[1].is_one()) {
2403 inst
->opcode
= BRW_OPCODE_ADD
;
2404 inst
->src
[1] = inst
->src
[2];
2405 inst
->src
[2] = reg_undef
;
2407 } else if (inst
->src
[2].is_one()) {
2408 inst
->opcode
= BRW_OPCODE_ADD
;
2409 inst
->src
[2] = reg_undef
;
2411 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2412 inst
->opcode
= BRW_OPCODE_ADD
;
2413 inst
->src
[1].f
*= inst
->src
[2].f
;
2414 inst
->src
[2] = reg_undef
;
2418 case SHADER_OPCODE_BROADCAST
:
2419 if (is_uniform(inst
->src
[0])) {
2420 inst
->opcode
= BRW_OPCODE_MOV
;
2422 inst
->force_writemask_all
= true;
2424 } else if (inst
->src
[1].file
== IMM
) {
2425 inst
->opcode
= BRW_OPCODE_MOV
;
2426 inst
->src
[0] = component(inst
->src
[0],
2429 inst
->force_writemask_all
= true;
2438 /* Swap if src[0] is immediate. */
2439 if (progress
&& inst
->is_commutative()) {
2440 if (inst
->src
[0].file
== IMM
) {
2441 fs_reg tmp
= inst
->src
[1];
2442 inst
->src
[1] = inst
->src
[0];
2451 * Optimize sample messages that have constant zero values for the trailing
2452 * texture coordinates. We can just reduce the message length for these
2453 * instructions instead of reserving a register for it. Trailing parameters
2454 * that aren't sent default to zero anyway. This will cause the dead code
2455 * eliminator to remove the MOV instruction that would otherwise be emitted to
2456 * set up the zero value.
2459 fs_visitor::opt_zero_samples()
2461 /* Gen4 infers the texturing opcode based on the message length so we can't
2464 if (devinfo
->gen
< 5)
2467 bool progress
= false;
2469 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2470 if (!inst
->is_tex())
2473 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2475 if (load_payload
->is_head_sentinel() ||
2476 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2479 /* We don't want to remove the message header or the first parameter.
2480 * Removing the first parameter is not allowed, see the Haswell PRM
2481 * volume 7, page 149:
2483 * "Parameter 0 is required except for the sampleinfo message, which
2484 * has no parameter 0"
2486 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2487 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2488 (inst
->exec_size
/ 8) +
2489 inst
->header_size
- 1].is_zero()) {
2490 inst
->mlen
-= inst
->exec_size
/ 8;
2496 invalidate_live_intervals();
2502 * Optimize sample messages which are followed by the final RT write.
2504 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2505 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2506 * final texturing results copied to the framebuffer write payload and modify
2507 * them to write to the framebuffer directly.
2510 fs_visitor::opt_sampler_eot()
2512 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2514 if (stage
!= MESA_SHADER_FRAGMENT
)
2517 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2520 /* FINISHME: It should be possible to implement this optimization when there
2521 * are multiple drawbuffers.
2523 if (key
->nr_color_regions
!= 1)
2526 /* Requires emitting a bunch of saturating MOV instructions during logical
2527 * send lowering to clamp the color payload, which the sampler unit isn't
2528 * going to do for us.
2530 if (key
->clamp_fragment_color
)
2533 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2534 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2535 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2536 assert(fb_write
->eot
);
2537 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2539 /* There wasn't one; nothing to do. */
2540 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2543 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2545 /* 3D Sampler » Messages » Message Format
2547 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2548 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2550 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2551 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2552 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2553 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2554 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2555 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2556 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2557 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2560 /* XXX - This shouldn't be necessary. */
2561 if (tex_inst
->prev
->is_head_sentinel())
2564 /* Check that the FB write sources are fully initialized by the single
2565 * texturing instruction.
2567 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2568 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2569 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2570 fb_write
->size_read(i
) != tex_inst
->size_written
)
2572 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2573 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2578 assert(!tex_inst
->eot
); /* We can't get here twice */
2579 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2581 const fs_builder
ibld(this, block
, tex_inst
);
2583 tex_inst
->offset
|= fb_write
->target
<< 24;
2584 tex_inst
->eot
= true;
2585 tex_inst
->dst
= ibld
.null_reg_ud();
2586 tex_inst
->size_written
= 0;
2587 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2589 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2590 * flag and submit a header together with the sampler message as required
2593 invalidate_live_intervals();
2598 fs_visitor::opt_register_renaming()
2600 bool progress
= false;
2603 int remap
[alloc
.count
];
2604 memset(remap
, -1, sizeof(int) * alloc
.count
);
2606 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2607 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2609 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2610 inst
->opcode
== BRW_OPCODE_WHILE
) {
2614 /* Rewrite instruction sources. */
2615 for (int i
= 0; i
< inst
->sources
; i
++) {
2616 if (inst
->src
[i
].file
== VGRF
&&
2617 remap
[inst
->src
[i
].nr
] != -1 &&
2618 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2619 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2624 const int dst
= inst
->dst
.nr
;
2627 inst
->dst
.file
== VGRF
&&
2628 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2629 !inst
->is_partial_write()) {
2630 if (remap
[dst
] == -1) {
2633 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2634 inst
->dst
.nr
= remap
[dst
];
2637 } else if (inst
->dst
.file
== VGRF
&&
2639 remap
[dst
] != dst
) {
2640 inst
->dst
.nr
= remap
[dst
];
2646 invalidate_live_intervals();
2648 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2649 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2650 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2659 * Remove redundant or useless discard jumps.
2661 * For example, we can eliminate jumps in the following sequence:
2663 * discard-jump (redundant with the next jump)
2664 * discard-jump (useless; jumps to the next instruction)
2668 fs_visitor::opt_redundant_discard_jumps()
2670 bool progress
= false;
2672 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2674 fs_inst
*placeholder_halt
= NULL
;
2675 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2676 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2677 placeholder_halt
= inst
;
2682 if (!placeholder_halt
)
2685 /* Delete any HALTs immediately before the placeholder halt. */
2686 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2687 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2688 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2689 prev
->remove(last_bblock
);
2694 invalidate_live_intervals();
2700 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2701 * from \p r.offset which overlaps the region starting at \p s.offset and
2702 * spanning \p ds bytes.
2704 static inline unsigned
2705 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2707 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2708 const int shift
= rel_offset
/ REG_SIZE
;
2709 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2710 assert(reg_space(r
) == reg_space(s
) &&
2711 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2712 return ((1 << n
) - 1) << shift
;
2716 fs_visitor::compute_to_mrf()
2718 bool progress
= false;
2721 /* No MRFs on Gen >= 7. */
2722 if (devinfo
->gen
>= 7)
2725 calculate_live_intervals();
2727 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2731 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2732 inst
->is_partial_write() ||
2733 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2734 inst
->dst
.type
!= inst
->src
[0].type
||
2735 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2736 !inst
->src
[0].is_contiguous() ||
2737 inst
->src
[0].offset
% REG_SIZE
!= 0)
2740 /* Can't compute-to-MRF this GRF if someone else was going to
2743 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2746 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2747 * things that computed the value of all GRFs of the source region. The
2748 * regs_left bitset keeps track of the registers we haven't yet found a
2749 * generating instruction for.
2751 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2753 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2754 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2755 inst
->src
[0], inst
->size_read(0))) {
2756 /* Found the last thing to write our reg we want to turn
2757 * into a compute-to-MRF.
2760 /* If this one instruction didn't populate all the
2761 * channels, bail. We might be able to rewrite everything
2762 * that writes that reg, but it would require smarter
2765 if (scan_inst
->is_partial_write())
2768 /* Handling things not fully contained in the source of the copy
2769 * would need us to understand coalescing out more than one MOV at
2772 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
2773 inst
->src
[0], inst
->size_read(0)))
2776 /* SEND instructions can't have MRF as a destination. */
2777 if (scan_inst
->mlen
)
2780 if (devinfo
->gen
== 6) {
2781 /* gen6 math instructions must have the destination be
2782 * GRF, so no compute-to-MRF for them.
2784 if (scan_inst
->is_math()) {
2789 /* Clear the bits for any registers this instruction overwrites. */
2790 regs_left
&= ~mask_relative_to(
2791 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2796 /* We don't handle control flow here. Most computation of
2797 * values that end up in MRFs are shortly before the MRF
2800 if (block
->start() == scan_inst
)
2803 /* You can't read from an MRF, so if someone else reads our
2804 * MRF's source GRF that we wanted to rewrite, that stops us.
2806 bool interfered
= false;
2807 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2808 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2809 inst
->src
[0], inst
->size_read(0))) {
2816 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2817 inst
->dst
, inst
->size_written
)) {
2818 /* If somebody else writes our MRF here, we can't
2819 * compute-to-MRF before that.
2824 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2825 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2826 inst
->dst
, inst
->size_written
)) {
2827 /* Found a SEND instruction, which means that there are
2828 * live values in MRFs from base_mrf to base_mrf +
2829 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2839 /* Found all generating instructions of our MRF's source value, so it
2840 * should be safe to rewrite them to point to the MRF directly.
2842 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2844 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2845 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2846 inst
->src
[0], inst
->size_read(0))) {
2847 /* Clear the bits for any registers this instruction overwrites. */
2848 regs_left
&= ~mask_relative_to(
2849 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2851 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
2852 reg_offset(inst
->src
[0]);
2854 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2855 /* Apply the same address transformation done by the hardware
2856 * for COMPR4 MRF writes.
2858 assert(rel_offset
< 2 * REG_SIZE
);
2859 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
2861 /* Clear the COMPR4 bit if the generating instruction is not
2864 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2865 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2868 /* Calculate the MRF number the result of this instruction is
2869 * ultimately written to.
2871 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
2874 scan_inst
->dst
.file
= MRF
;
2875 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
2876 scan_inst
->saturate
|= inst
->saturate
;
2883 inst
->remove(block
);
2888 invalidate_live_intervals();
2894 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2895 * flow. We could probably do better here with some form of divergence
2899 fs_visitor::eliminate_find_live_channel()
2901 bool progress
= false;
2904 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
2905 /* The optimization below assumes that channel zero is live on thread
2906 * dispatch, which may not be the case if the fixed function dispatches
2912 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2913 switch (inst
->opcode
) {
2919 case BRW_OPCODE_ENDIF
:
2920 case BRW_OPCODE_WHILE
:
2924 case FS_OPCODE_DISCARD_JUMP
:
2925 /* This can potentially make control flow non-uniform until the end
2930 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2932 inst
->opcode
= BRW_OPCODE_MOV
;
2933 inst
->src
[0] = brw_imm_ud(0u);
2935 inst
->force_writemask_all
= true;
2949 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2950 * instructions to FS_OPCODE_REP_FB_WRITE.
2953 fs_visitor::emit_repclear_shader()
2955 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2957 int color_mrf
= base_mrf
+ 2;
2961 mov
= bld
.exec_all().group(4, 0)
2962 .MOV(brw_message_reg(color_mrf
),
2963 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2965 struct brw_reg reg
=
2966 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2967 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2968 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2970 mov
= bld
.exec_all().group(4, 0)
2971 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2975 if (key
->nr_color_regions
== 1) {
2976 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2977 write
->saturate
= key
->clamp_fragment_color
;
2978 write
->base_mrf
= color_mrf
;
2980 write
->header_size
= 0;
2983 assume(key
->nr_color_regions
> 0);
2984 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2985 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2986 write
->saturate
= key
->clamp_fragment_color
;
2987 write
->base_mrf
= base_mrf
;
2989 write
->header_size
= 2;
2997 assign_constant_locations();
2998 assign_curb_setup();
3000 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3002 assert(mov
->src
[0].file
== FIXED_GRF
);
3003 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3008 * Walks through basic blocks, looking for repeated MRF writes and
3009 * removing the later ones.
3012 fs_visitor::remove_duplicate_mrf_writes()
3014 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3015 bool progress
= false;
3017 /* Need to update the MRF tracking for compressed instructions. */
3018 if (dispatch_width
>= 16)
3021 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3023 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3024 if (inst
->is_control_flow()) {
3025 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3028 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3029 inst
->dst
.file
== MRF
) {
3030 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3031 if (prev_inst
&& inst
->equals(prev_inst
)) {
3032 inst
->remove(block
);
3038 /* Clear out the last-write records for MRFs that were overwritten. */
3039 if (inst
->dst
.file
== MRF
) {
3040 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3043 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3044 /* Found a SEND instruction, which will include two or fewer
3045 * implied MRF writes. We could do better here.
3047 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3048 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3052 /* Clear out any MRF move records whose sources got overwritten. */
3053 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3054 if (last_mrf_move
[i
] &&
3055 regions_overlap(inst
->dst
, inst
->size_written
,
3056 last_mrf_move
[i
]->src
[0],
3057 last_mrf_move
[i
]->size_read(0))) {
3058 last_mrf_move
[i
] = NULL
;
3062 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3063 inst
->dst
.file
== MRF
&&
3064 inst
->src
[0].file
!= ARF
&&
3065 !inst
->is_partial_write()) {
3066 last_mrf_move
[inst
->dst
.nr
] = inst
;
3071 invalidate_live_intervals();
3077 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3079 /* Clear the flag for registers that actually got read (as expected). */
3080 for (int i
= 0; i
< inst
->sources
; i
++) {
3082 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3083 grf
= inst
->src
[i
].nr
;
3088 if (grf
>= first_grf
&&
3089 grf
< first_grf
+ grf_len
) {
3090 deps
[grf
- first_grf
] = false;
3091 if (inst
->exec_size
== 16)
3092 deps
[grf
- first_grf
+ 1] = false;
3098 * Implements this workaround for the original 965:
3100 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3101 * check for post destination dependencies on this instruction, software
3102 * must ensure that there is no destination hazard for the case of ‘write
3103 * followed by a posted write’ shown in the following example.
3106 * 2. send r3.xy <rest of send instruction>
3109 * Due to no post-destination dependency check on the ‘send’, the above
3110 * code sequence could have two instructions (1 and 2) in flight at the
3111 * same time that both consider ‘r3’ as the target of their final writes.
3114 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3117 int write_len
= regs_written(inst
);
3118 int first_write_grf
= inst
->dst
.nr
;
3119 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3120 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3122 memset(needs_dep
, false, sizeof(needs_dep
));
3123 memset(needs_dep
, true, write_len
);
3125 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3127 /* Walk backwards looking for writes to registers we're writing which
3128 * aren't read since being written. If we hit the start of the program,
3129 * we assume that there are no outstanding dependencies on entry to the
3132 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3133 /* If we hit control flow, assume that there *are* outstanding
3134 * dependencies, and force their cleanup before our instruction.
3136 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3137 for (int i
= 0; i
< write_len
; i
++) {
3139 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3140 first_write_grf
+ i
);
3145 /* We insert our reads as late as possible on the assumption that any
3146 * instruction but a MOV that might have left us an outstanding
3147 * dependency has more latency than a MOV.
3149 if (scan_inst
->dst
.file
== VGRF
) {
3150 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3151 int reg
= scan_inst
->dst
.nr
+ i
;
3153 if (reg
>= first_write_grf
&&
3154 reg
< first_write_grf
+ write_len
&&
3155 needs_dep
[reg
- first_write_grf
]) {
3156 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3157 needs_dep
[reg
- first_write_grf
] = false;
3158 if (scan_inst
->exec_size
== 16)
3159 needs_dep
[reg
- first_write_grf
+ 1] = false;
3164 /* Clear the flag for registers that actually got read (as expected). */
3165 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3167 /* Continue the loop only if we haven't resolved all the dependencies */
3169 for (i
= 0; i
< write_len
; i
++) {
3179 * Implements this workaround for the original 965:
3181 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3182 * used as a destination register until after it has been sourced by an
3183 * instruction with a different destination register.
3186 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3188 int write_len
= regs_written(inst
);
3189 int first_write_grf
= inst
->dst
.nr
;
3190 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3191 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3193 memset(needs_dep
, false, sizeof(needs_dep
));
3194 memset(needs_dep
, true, write_len
);
3195 /* Walk forwards looking for writes to registers we're writing which aren't
3196 * read before being written.
3198 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3199 /* If we hit control flow, force resolve all remaining dependencies. */
3200 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3201 for (int i
= 0; i
< write_len
; i
++) {
3203 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3204 first_write_grf
+ i
);
3209 /* Clear the flag for registers that actually got read (as expected). */
3210 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3212 /* We insert our reads as late as possible since they're reading the
3213 * result of a SEND, which has massive latency.
3215 if (scan_inst
->dst
.file
== VGRF
&&
3216 scan_inst
->dst
.nr
>= first_write_grf
&&
3217 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3218 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3219 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3221 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3224 /* Continue the loop only if we haven't resolved all the dependencies */
3226 for (i
= 0; i
< write_len
; i
++) {
3236 fs_visitor::insert_gen4_send_dependency_workarounds()
3238 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3241 bool progress
= false;
3243 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3244 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3245 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3246 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3252 invalidate_live_intervals();
3256 * Turns the generic expression-style uniform pull constant load instruction
3257 * into a hardware-specific series of instructions for loading a pull
3260 * The expression style allows the CSE pass before this to optimize out
3261 * repeated loads from the same offset, and gives the pre-register-allocation
3262 * scheduling full flexibility, while the conversion to native instructions
3263 * allows the post-register-allocation scheduler the best information
3266 * Note that execution masking for setting up pull constant loads is special:
3267 * the channels that need to be written are unrelated to the current execution
3268 * mask, since a later instruction will use one of the result channels as a
3269 * source operand for all 8 or 16 of its channels.
3272 fs_visitor::lower_uniform_pull_constant_loads()
3274 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3275 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3278 if (devinfo
->gen
>= 7) {
3279 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3280 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3282 ubld
.group(8, 0).MOV(payload
,
3283 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3284 ubld
.group(1, 0).MOV(component(payload
, 2),
3285 brw_imm_ud(inst
->src
[1].ud
/ 16));
3287 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3288 inst
->src
[1] = payload
;
3289 inst
->header_size
= 1;
3292 invalidate_live_intervals();
3294 /* Before register allocation, we didn't tell the scheduler about the
3295 * MRF we use. We know it's safe to use this MRF because nothing
3296 * else does except for register spill/unspill, which generates and
3297 * uses its MRF within a single IR instruction.
3299 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3306 fs_visitor::lower_load_payload()
3308 bool progress
= false;
3310 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3311 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3314 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3315 assert(inst
->saturate
== false);
3316 fs_reg dst
= inst
->dst
;
3318 /* Get rid of COMPR4. We'll add it back in if we need it */
3319 if (dst
.file
== MRF
)
3320 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3322 const fs_builder
ibld(this, block
, inst
);
3323 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3325 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3326 if (inst
->src
[i
].file
!= BAD_FILE
) {
3327 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3328 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3329 hbld
.MOV(mov_dst
, mov_src
);
3331 dst
= offset(dst
, hbld
, 1);
3334 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3335 inst
->exec_size
> 8) {
3336 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3337 * a straightforward copy. Instead, the result of the
3338 * LOAD_PAYLOAD is treated as interleaved and the first four
3339 * non-header sources are unpacked as:
3350 * This is used for gen <= 5 fb writes.
3352 assert(inst
->exec_size
== 16);
3353 assert(inst
->header_size
+ 4 <= inst
->sources
);
3354 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3355 if (inst
->src
[i
].file
!= BAD_FILE
) {
3356 if (devinfo
->has_compr4
) {
3357 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3358 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3359 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3361 /* Platform doesn't have COMPR4. We have to fake it */
3362 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3363 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3365 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3372 /* The loop above only ever incremented us through the first set
3373 * of 4 registers. However, thanks to the magic of COMPR4, we
3374 * actually wrote to the first 8 registers, so we need to take
3375 * that into account now.
3379 /* The COMPR4 code took care of the first 4 sources. We'll let
3380 * the regular path handle any remaining sources. Yes, we are
3381 * modifying the instruction but we're about to delete it so
3382 * this really doesn't hurt anything.
3384 inst
->header_size
+= 4;
3387 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3388 if (inst
->src
[i
].file
!= BAD_FILE
)
3389 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3390 dst
= offset(dst
, ibld
, 1);
3393 inst
->remove(block
);
3398 invalidate_live_intervals();
3404 fs_visitor::lower_integer_multiplication()
3406 bool progress
= false;
3408 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3409 const fs_builder
ibld(this, block
, inst
);
3411 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3412 if (inst
->dst
.is_accumulator() ||
3413 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3414 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3417 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3418 * operation directly, but CHV/BXT cannot.
3420 if (devinfo
->gen
>= 8 &&
3421 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
))
3424 if (inst
->src
[1].file
== IMM
&&
3425 inst
->src
[1].ud
< (1 << 16)) {
3426 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3427 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3430 * If multiplying by an immediate value that fits in 16-bits, do a
3431 * single MUL instruction with that value in the proper location.
3433 if (devinfo
->gen
< 7) {
3434 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3436 ibld
.MOV(imm
, inst
->src
[1]);
3437 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3439 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3440 ibld
.MUL(inst
->dst
, inst
->src
[0],
3441 ud
? brw_imm_uw(inst
->src
[1].ud
)
3442 : brw_imm_w(inst
->src
[1].d
));
3445 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3446 * do 32-bit integer multiplication in one instruction, but instead
3447 * must do a sequence (which actually calculates a 64-bit result):
3449 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3450 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3451 * mov(8) g2<1>D acc0<8,8,1>D
3453 * But on Gen > 6, the ability to use second accumulator register
3454 * (acc1) for non-float data types was removed, preventing a simple
3455 * implementation in SIMD16. A 16-channel result can be calculated by
3456 * executing the three instructions twice in SIMD8, once with quarter
3457 * control of 1Q for the first eight channels and again with 2Q for
3458 * the second eight channels.
3460 * Which accumulator register is implicitly accessed (by AccWrEnable
3461 * for instance) is determined by the quarter control. Unfortunately
3462 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3463 * implicit accumulator access by an instruction with 2Q will access
3464 * acc1 regardless of whether the data type is usable in acc1.
3466 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3467 * integer data types.
3469 * Since we only want the low 32-bits of the result, we can do two
3470 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3471 * adjust the high result and add them (like the mach is doing):
3473 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3474 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3475 * shl(8) g9<1>D g8<8,8,1>D 16D
3476 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3478 * We avoid the shl instruction by realizing that we only want to add
3479 * the low 16-bits of the "high" result to the high 16-bits of the
3480 * "low" result and using proper regioning on the add:
3482 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3483 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3484 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3486 * Since it does not use the (single) accumulator register, we can
3487 * schedule multi-component multiplications much better.
3490 fs_reg orig_dst
= inst
->dst
;
3491 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3492 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3495 fs_reg low
= inst
->dst
;
3496 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3499 if (devinfo
->gen
>= 7) {
3500 if (inst
->src
[1].file
== IMM
) {
3501 ibld
.MUL(low
, inst
->src
[0],
3502 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3503 ibld
.MUL(high
, inst
->src
[0],
3504 brw_imm_uw(inst
->src
[1].ud
>> 16));
3506 ibld
.MUL(low
, inst
->src
[0],
3507 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3508 ibld
.MUL(high
, inst
->src
[0],
3509 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3512 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3514 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3518 ibld
.ADD(subscript(inst
->dst
, BRW_REGISTER_TYPE_UW
, 1),
3519 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3520 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3522 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3523 set_condmod(inst
->conditional_mod
,
3524 ibld
.MOV(orig_dst
, inst
->dst
));
3528 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3529 /* Should have been lowered to 8-wide. */
3530 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3531 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3533 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3534 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3536 if (devinfo
->gen
>= 8) {
3537 /* Until Gen8, integer multiplies read 32-bits from one source,
3538 * and 16-bits from the other, and relying on the MACH instruction
3539 * to generate the high bits of the result.
3541 * On Gen8, the multiply instruction does a full 32x32-bit
3542 * multiply, but in order to do a 64-bit multiply we can simulate
3543 * the previous behavior and then use a MACH instruction.
3545 * FINISHME: Don't use source modifiers on src1.
3547 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3548 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3549 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3550 mul
->src
[1].stride
*= 2;
3552 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3554 /* Among other things the quarter control bits influence which
3555 * accumulator register is used by the hardware for instructions
3556 * that access the accumulator implicitly (e.g. MACH). A
3557 * second-half instruction would normally map to acc1, which
3558 * doesn't exist on Gen7 and up (the hardware does emulate it for
3559 * floating-point instructions *only* by taking advantage of the
3560 * extra precision of acc0 not normally used for floating point
3563 * HSW and up are careful enough not to try to access an
3564 * accumulator register that doesn't exist, but on earlier Gen7
3565 * hardware we need to make sure that the quarter control bits are
3566 * zero to avoid non-deterministic behaviour and emit an extra MOV
3567 * to get the result masked correctly according to the current
3571 mach
->force_writemask_all
= true;
3572 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3573 ibld
.MOV(inst
->dst
, mach
->dst
);
3579 inst
->remove(block
);
3584 invalidate_live_intervals();
3590 fs_visitor::lower_minmax()
3592 assert(devinfo
->gen
< 6);
3594 bool progress
= false;
3596 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3597 const fs_builder
ibld(this, block
, inst
);
3599 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3600 inst
->predicate
== BRW_PREDICATE_NONE
) {
3601 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3602 * the original SEL.L/GE instruction
3604 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3605 inst
->conditional_mod
);
3606 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3607 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3614 invalidate_live_intervals();
3620 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3621 fs_reg
*dst
, fs_reg color
, unsigned components
)
3623 if (key
->clamp_fragment_color
) {
3624 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3625 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3627 for (unsigned i
= 0; i
< components
; i
++)
3629 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3634 for (unsigned i
= 0; i
< components
; i
++)
3635 dst
[i
] = offset(color
, bld
, i
);
3639 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3640 const struct brw_wm_prog_data
*prog_data
,
3641 const brw_wm_prog_key
*key
,
3642 const fs_visitor::thread_payload
&payload
)
3644 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3645 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3646 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3647 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3648 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3649 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3650 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3651 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3652 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3653 const unsigned components
=
3654 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3656 /* We can potentially have a message length of up to 15, so we have to set
3657 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3660 int header_size
= 2, payload_header_size
;
3661 unsigned length
= 0;
3663 /* From the Sandy Bridge PRM, volume 4, page 198:
3665 * "Dispatched Pixel Enables. One bit per pixel indicating
3666 * which pixels were originally enabled when the thread was
3667 * dispatched. This field is only required for the end-of-
3668 * thread message and on all dual-source messages."
3670 if (devinfo
->gen
>= 6 &&
3671 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3672 color1
.file
== BAD_FILE
&&
3673 key
->nr_color_regions
== 1) {
3677 if (header_size
!= 0) {
3678 assert(header_size
== 2);
3679 /* Allocate 2 registers for a header */
3683 if (payload
.aa_dest_stencil_reg
) {
3684 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3685 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3686 .MOV(sources
[length
],
3687 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3691 if (sample_mask
.file
!= BAD_FILE
) {
3692 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3693 BRW_REGISTER_TYPE_UD
);
3695 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3696 * relevant. Since it's unsigned single words one vgrf is always
3697 * 16-wide, but only the lower or higher 8 channels will be used by the
3698 * hardware when doing a SIMD8 write depending on whether we have
3699 * selected the subspans for the first or second half respectively.
3701 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3702 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3703 sample_mask
.stride
*= 2;
3705 bld
.exec_all().annotate("FB write oMask")
3706 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3712 payload_header_size
= length
;
3714 if (src0_alpha
.file
!= BAD_FILE
) {
3715 /* FIXME: This is being passed at the wrong location in the payload and
3716 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3717 * It's supposed to be immediately before oMask but there seems to be no
3718 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3719 * requires header sources to form a contiguous segment at the beginning
3720 * of the message and src0_alpha has per-channel semantics.
3722 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3724 } else if (key
->replicate_alpha
&& inst
->target
!= 0) {
3725 /* Handle the case when fragment shader doesn't write to draw buffer
3726 * zero. No need to call setup_color_payload() for src0_alpha because
3727 * alpha value will be undefined.
3732 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3735 if (color1
.file
!= BAD_FILE
) {
3736 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3740 if (src_depth
.file
!= BAD_FILE
) {
3741 sources
[length
] = src_depth
;
3745 if (dst_depth
.file
!= BAD_FILE
) {
3746 sources
[length
] = dst_depth
;
3750 if (src_stencil
.file
!= BAD_FILE
) {
3751 assert(devinfo
->gen
>= 9);
3752 assert(bld
.dispatch_width() != 16);
3754 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3755 * available on gen9+. As such it's impossible to have both enabled at the
3756 * same time and therefore length cannot overrun the array.
3758 assert(length
< 15);
3760 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3761 bld
.exec_all().annotate("FB write OS")
3762 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3763 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3768 if (devinfo
->gen
>= 7) {
3769 /* Send from the GRF */
3770 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3771 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3772 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3773 load
->dst
= payload
;
3775 inst
->src
[0] = payload
;
3776 inst
->resize_sources(1);
3778 /* Send from the MRF */
3779 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3780 sources
, length
, payload_header_size
);
3782 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3783 * will do this for us if we just give it a COMPR4 destination.
3785 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3786 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3788 inst
->resize_sources(0);
3792 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3793 inst
->mlen
= regs_written(load
);
3794 inst
->header_size
= header_size
;
3798 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3800 const fs_builder
&ubld
= bld
.exec_all();
3801 const unsigned length
= 2;
3802 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3805 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3807 inst
->resize_sources(1);
3808 inst
->src
[0] = header
;
3809 inst
->opcode
= FS_OPCODE_FB_READ
;
3810 inst
->mlen
= length
;
3811 inst
->header_size
= length
;
3815 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3816 const fs_reg
&coordinate
,
3817 const fs_reg
&shadow_c
,
3818 const fs_reg
&lod
, const fs_reg
&lod2
,
3819 const fs_reg
&surface
,
3820 const fs_reg
&sampler
,
3821 unsigned coord_components
,
3822 unsigned grad_components
)
3824 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3825 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3826 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3827 fs_reg msg_end
= msg_begin
;
3830 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3832 for (unsigned i
= 0; i
< coord_components
; i
++)
3833 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3834 offset(coordinate
, bld
, i
));
3836 msg_end
= offset(msg_end
, bld
, coord_components
);
3838 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3839 * require all three components to be present and zero if they are unused.
3841 if (coord_components
> 0 &&
3842 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3843 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3844 for (unsigned i
= coord_components
; i
< 3; i
++)
3845 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3847 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3850 if (op
== SHADER_OPCODE_TXD
) {
3851 /* TXD unsupported in SIMD16 mode. */
3852 assert(bld
.dispatch_width() == 8);
3854 /* the slots for u and v are always present, but r is optional */
3855 if (coord_components
< 2)
3856 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3859 * dPdx = dudx, dvdx, drdx
3860 * dPdy = dudy, dvdy, drdy
3862 * 1-arg: Does not exist.
3864 * 2-arg: dudx dvdx dudy dvdy
3865 * dPdx.x dPdx.y dPdy.x dPdy.y
3868 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3869 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3870 * m5 m6 m7 m8 m9 m10
3872 for (unsigned i
= 0; i
< grad_components
; i
++)
3873 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3875 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3877 for (unsigned i
= 0; i
< grad_components
; i
++)
3878 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3880 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3884 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
3885 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
3887 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3888 bld
.dispatch_width() == 16);
3890 const brw_reg_type type
=
3891 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3892 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3893 bld
.MOV(retype(msg_end
, type
), lod
);
3894 msg_end
= offset(msg_end
, bld
, 1);
3897 if (shadow_c
.file
!= BAD_FILE
) {
3898 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3899 /* There's no plain shadow compare message, so we use shadow
3900 * compare with a bias of 0.0.
3902 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3903 msg_end
= offset(msg_end
, bld
, 1);
3906 bld
.MOV(msg_end
, shadow_c
);
3907 msg_end
= offset(msg_end
, bld
, 1);
3911 inst
->src
[0] = reg_undef
;
3912 inst
->src
[1] = surface
;
3913 inst
->src
[2] = sampler
;
3914 inst
->resize_sources(3);
3915 inst
->base_mrf
= msg_begin
.nr
;
3916 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3917 inst
->header_size
= 1;
3921 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3922 const fs_reg
&coordinate
,
3923 const fs_reg
&shadow_c
,
3924 const fs_reg
&lod
, const fs_reg
&lod2
,
3925 const fs_reg
&sample_index
,
3926 const fs_reg
&surface
,
3927 const fs_reg
&sampler
,
3928 unsigned coord_components
,
3929 unsigned grad_components
)
3931 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3932 fs_reg msg_coords
= message
;
3933 unsigned header_size
= 0;
3935 if (inst
->offset
!= 0) {
3936 /* The offsets set up by the visitor are in the m1 header, so we can't
3943 for (unsigned i
= 0; i
< coord_components
; i
++)
3944 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3945 offset(coordinate
, bld
, i
));
3947 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3948 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3950 if (shadow_c
.file
!= BAD_FILE
) {
3951 fs_reg msg_shadow
= msg_lod
;
3952 bld
.MOV(msg_shadow
, shadow_c
);
3953 msg_lod
= offset(msg_shadow
, bld
, 1);
3958 case SHADER_OPCODE_TXL
:
3960 bld
.MOV(msg_lod
, lod
);
3961 msg_end
= offset(msg_lod
, bld
, 1);
3963 case SHADER_OPCODE_TXD
:
3966 * dPdx = dudx, dvdx, drdx
3967 * dPdy = dudy, dvdy, drdy
3969 * Load up these values:
3970 * - dudx dudy dvdx dvdy drdx drdy
3971 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3974 for (unsigned i
= 0; i
< grad_components
; i
++) {
3975 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3976 msg_end
= offset(msg_end
, bld
, 1);
3978 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3979 msg_end
= offset(msg_end
, bld
, 1);
3982 case SHADER_OPCODE_TXS
:
3983 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3984 bld
.MOV(msg_lod
, lod
);
3985 msg_end
= offset(msg_lod
, bld
, 1);
3987 case SHADER_OPCODE_TXF
:
3988 msg_lod
= offset(msg_coords
, bld
, 3);
3989 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3990 msg_end
= offset(msg_lod
, bld
, 1);
3992 case SHADER_OPCODE_TXF_CMS
:
3993 msg_lod
= offset(msg_coords
, bld
, 3);
3995 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3997 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3998 msg_end
= offset(msg_lod
, bld
, 2);
4005 inst
->src
[0] = reg_undef
;
4006 inst
->src
[1] = surface
;
4007 inst
->src
[2] = sampler
;
4008 inst
->resize_sources(3);
4009 inst
->base_mrf
= message
.nr
;
4010 inst
->mlen
= msg_end
.nr
- message
.nr
;
4011 inst
->header_size
= header_size
;
4013 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4014 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4018 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4020 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4023 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4027 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4028 const fs_reg
&coordinate
,
4029 const fs_reg
&shadow_c
,
4030 fs_reg lod
, const fs_reg
&lod2
,
4031 const fs_reg
&sample_index
,
4033 const fs_reg
&surface
,
4034 const fs_reg
&sampler
,
4035 const fs_reg
&tg4_offset
,
4036 unsigned coord_components
,
4037 unsigned grad_components
)
4039 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4040 unsigned reg_width
= bld
.dispatch_width() / 8;
4041 unsigned header_size
= 0, length
= 0;
4042 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4043 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4044 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4046 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4047 inst
->offset
!= 0 || inst
->eot
||
4048 op
== SHADER_OPCODE_SAMPLEINFO
||
4049 is_high_sampler(devinfo
, sampler
)) {
4050 /* For general texture offsets (no txf workaround), we need a header to
4051 * put them in. Note that we're only reserving space for it in the
4052 * message payload as it will be initialized implicitly by the
4055 * TG4 needs to place its channel select in the header, for interaction
4056 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4057 * larger sampler numbers we need to offset the Sampler State Pointer in
4061 sources
[0] = fs_reg();
4064 /* If we're requesting fewer than four channels worth of response,
4065 * and we have an explicit header, we need to set up the sampler
4066 * writemask. It's reversed from normal: 1 means "don't write".
4068 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4069 assert(regs_written(inst
) % reg_width
== 0);
4070 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4071 inst
->offset
|= mask
<< 12;
4075 if (shadow_c
.file
!= BAD_FILE
) {
4076 bld
.MOV(sources
[length
], shadow_c
);
4080 bool coordinate_done
= false;
4082 /* Set up the LOD info */
4085 case SHADER_OPCODE_TXL
:
4086 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4087 op
= SHADER_OPCODE_TXL_LZ
;
4090 bld
.MOV(sources
[length
], lod
);
4093 case SHADER_OPCODE_TXD
:
4094 /* TXD should have been lowered in SIMD16 mode. */
4095 assert(bld
.dispatch_width() == 8);
4097 /* Load dPdx and the coordinate together:
4098 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4100 for (unsigned i
= 0; i
< coord_components
; i
++) {
4101 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4103 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4104 * only derivatives for (u, v, r).
4106 if (i
< grad_components
) {
4107 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4108 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4112 coordinate_done
= true;
4114 case SHADER_OPCODE_TXS
:
4115 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4118 case SHADER_OPCODE_TXF
:
4119 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4120 * On Gen9 they are u, v, lod, r
4122 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4124 if (devinfo
->gen
>= 9) {
4125 if (coord_components
>= 2) {
4126 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4127 offset(coordinate
, bld
, 1));
4129 sources
[length
] = brw_imm_d(0);
4134 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4135 op
= SHADER_OPCODE_TXF_LZ
;
4137 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4141 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4142 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4143 offset(coordinate
, bld
, i
));
4145 coordinate_done
= true;
4148 case SHADER_OPCODE_TXF_CMS
:
4149 case SHADER_OPCODE_TXF_CMS_W
:
4150 case SHADER_OPCODE_TXF_UMS
:
4151 case SHADER_OPCODE_TXF_MCS
:
4152 if (op
== SHADER_OPCODE_TXF_UMS
||
4153 op
== SHADER_OPCODE_TXF_CMS
||
4154 op
== SHADER_OPCODE_TXF_CMS_W
) {
4155 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4159 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4160 /* Data from the multisample control surface. */
4161 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4164 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4167 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4168 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4171 offset(mcs
, bld
, 1));
4176 /* There is no offsetting for this message; just copy in the integer
4177 * texture coordinates.
4179 for (unsigned i
= 0; i
< coord_components
; i
++)
4180 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4181 offset(coordinate
, bld
, i
));
4183 coordinate_done
= true;
4185 case SHADER_OPCODE_TG4_OFFSET
:
4186 /* More crazy intermixing */
4187 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4188 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4190 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4191 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4192 offset(tg4_offset
, bld
, i
));
4194 if (coord_components
== 3) /* r if present */
4195 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4197 coordinate_done
= true;
4203 /* Set up the coordinate (except for cases where it was done above) */
4204 if (!coordinate_done
) {
4205 for (unsigned i
= 0; i
< coord_components
; i
++)
4206 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4211 mlen
= length
* reg_width
- header_size
;
4213 mlen
= length
* reg_width
;
4215 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4216 BRW_REGISTER_TYPE_F
);
4217 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4219 /* Generate the SEND. */
4221 inst
->src
[0] = src_payload
;
4222 inst
->src
[1] = surface
;
4223 inst
->src
[2] = sampler
;
4224 inst
->resize_sources(3);
4226 inst
->header_size
= header_size
;
4228 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4229 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4233 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4235 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4236 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4237 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4238 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4239 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4240 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4241 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4242 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4243 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4244 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
4245 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4246 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4247 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4248 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4250 if (devinfo
->gen
>= 7) {
4251 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4252 shadow_c
, lod
, lod2
, sample_index
,
4253 mcs
, surface
, sampler
, tg4_offset
,
4254 coord_components
, grad_components
);
4255 } else if (devinfo
->gen
>= 5) {
4256 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4257 shadow_c
, lod
, lod2
, sample_index
,
4259 coord_components
, grad_components
);
4261 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4262 shadow_c
, lod
, lod2
,
4264 coord_components
, grad_components
);
4269 * Initialize the header present in some typed and untyped surface
4273 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4275 fs_builder ubld
= bld
.exec_all().group(8, 0);
4276 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4277 ubld
.MOV(dst
, brw_imm_d(0));
4278 ubld
.MOV(component(dst
, 7), sample_mask
);
4283 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4284 const fs_reg
&sample_mask
)
4286 /* Get the logical send arguments. */
4287 const fs_reg
&addr
= inst
->src
[0];
4288 const fs_reg
&src
= inst
->src
[1];
4289 const fs_reg
&surface
= inst
->src
[2];
4290 const UNUSED fs_reg
&dims
= inst
->src
[3];
4291 const fs_reg
&arg
= inst
->src
[4];
4293 /* Calculate the total number of components of the payload. */
4294 const unsigned addr_sz
= inst
->components_read(0);
4295 const unsigned src_sz
= inst
->components_read(1);
4296 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4297 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4299 /* Allocate space for the payload. */
4300 fs_reg
*const components
= new fs_reg
[sz
];
4301 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4304 /* Construct the payload. */
4306 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4308 for (unsigned i
= 0; i
< addr_sz
; i
++)
4309 components
[n
++] = offset(addr
, bld
, i
);
4311 for (unsigned i
= 0; i
< src_sz
; i
++)
4312 components
[n
++] = offset(src
, bld
, i
);
4314 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4316 /* Update the original instruction. */
4318 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4319 inst
->header_size
= header_sz
;
4321 inst
->src
[0] = payload
;
4322 inst
->src
[1] = surface
;
4324 inst
->resize_sources(3);
4326 delete[] components
;
4330 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4332 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4334 if (devinfo
->gen
>= 7) {
4335 /* We are switching the instruction from an ALU-like instruction to a
4336 * send-from-grf instruction. Since sends can't handle strides or
4337 * source modifiers, we have to make a copy of the offset source.
4339 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4340 bld
.MOV(tmp
, inst
->src
[1]);
4343 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4346 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4347 BRW_REGISTER_TYPE_UD
);
4349 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4351 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4352 inst
->resize_sources(1);
4353 inst
->base_mrf
= payload
.nr
;
4354 inst
->header_size
= 1;
4355 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4360 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4362 assert(bld
.shader
->devinfo
->gen
< 6);
4365 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4367 if (inst
->sources
> 1) {
4368 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4369 * "Message Payload":
4371 * "Operand0[7]. For the INT DIV functions, this operand is the
4374 * "Operand1[7]. For the INT DIV functions, this operand is the
4377 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4378 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4379 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4381 inst
->resize_sources(1);
4382 inst
->src
[0] = src0
;
4384 assert(inst
->exec_size
== 8);
4385 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4390 fs_visitor::lower_logical_sends()
4392 bool progress
= false;
4394 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4395 const fs_builder
ibld(this, block
, inst
);
4397 switch (inst
->opcode
) {
4398 case FS_OPCODE_FB_WRITE_LOGICAL
:
4399 assert(stage
== MESA_SHADER_FRAGMENT
);
4400 lower_fb_write_logical_send(ibld
, inst
,
4401 brw_wm_prog_data(prog_data
),
4402 (const brw_wm_prog_key
*)key
,
4406 case FS_OPCODE_FB_READ_LOGICAL
:
4407 lower_fb_read_logical_send(ibld
, inst
);
4410 case SHADER_OPCODE_TEX_LOGICAL
:
4411 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4414 case SHADER_OPCODE_TXD_LOGICAL
:
4415 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4418 case SHADER_OPCODE_TXF_LOGICAL
:
4419 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4422 case SHADER_OPCODE_TXL_LOGICAL
:
4423 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4426 case SHADER_OPCODE_TXS_LOGICAL
:
4427 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4430 case FS_OPCODE_TXB_LOGICAL
:
4431 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4434 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4435 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4438 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4439 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4442 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4443 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4446 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4447 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4450 case SHADER_OPCODE_LOD_LOGICAL
:
4451 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4454 case SHADER_OPCODE_TG4_LOGICAL
:
4455 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4458 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4459 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4462 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4463 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4466 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4467 lower_surface_logical_send(ibld
, inst
,
4468 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4472 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4473 lower_surface_logical_send(ibld
, inst
,
4474 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4475 ibld
.sample_mask_reg());
4478 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4479 lower_surface_logical_send(ibld
, inst
,
4480 SHADER_OPCODE_UNTYPED_ATOMIC
,
4481 ibld
.sample_mask_reg());
4484 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4485 lower_surface_logical_send(ibld
, inst
,
4486 SHADER_OPCODE_TYPED_SURFACE_READ
,
4490 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4491 lower_surface_logical_send(ibld
, inst
,
4492 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4493 ibld
.sample_mask_reg());
4496 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4497 lower_surface_logical_send(ibld
, inst
,
4498 SHADER_OPCODE_TYPED_ATOMIC
,
4499 ibld
.sample_mask_reg());
4502 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4503 lower_varying_pull_constant_logical_send(ibld
, inst
);
4506 case SHADER_OPCODE_RCP
:
4507 case SHADER_OPCODE_RSQ
:
4508 case SHADER_OPCODE_SQRT
:
4509 case SHADER_OPCODE_EXP2
:
4510 case SHADER_OPCODE_LOG2
:
4511 case SHADER_OPCODE_SIN
:
4512 case SHADER_OPCODE_COS
:
4513 case SHADER_OPCODE_POW
:
4514 case SHADER_OPCODE_INT_QUOTIENT
:
4515 case SHADER_OPCODE_INT_REMAINDER
:
4516 /* The math opcodes are overloaded for the send-like and
4517 * expression-like instructions which seems kind of icky. Gen6+ has
4518 * a native (but rather quirky) MATH instruction so we don't need to
4519 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4520 * logical instructions (which we can easily recognize because they
4521 * have mlen = 0) into send-like virtual instructions.
4523 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4524 lower_math_logical_send(ibld
, inst
);
4539 invalidate_live_intervals();
4545 * Get the closest allowed SIMD width for instruction \p inst accounting for
4546 * some common regioning and execution control restrictions that apply to FPU
4547 * instructions. These restrictions don't necessarily have any relevance to
4548 * instructions not executed by the FPU pipeline like extended math, control
4549 * flow or send message instructions.
4551 * For virtual opcodes it's really up to the instruction -- In some cases
4552 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4553 * instructions) it may simplify virtual instruction lowering if we can
4554 * enforce FPU-like regioning restrictions already on the virtual instruction,
4555 * in other cases (e.g. virtual send-like instructions) this may be
4556 * excessively restrictive.
4559 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4560 const fs_inst
*inst
)
4562 /* Maximum execution size representable in the instruction controls. */
4563 unsigned max_width
= MIN2(32, inst
->exec_size
);
4565 /* According to the PRMs:
4566 * "A. In Direct Addressing mode, a source cannot span more than 2
4567 * adjacent GRF registers.
4568 * B. A destination cannot span more than 2 adjacent GRF registers."
4570 * Look for the source or destination with the largest register region
4571 * which is the one that is going to limit the overall execution size of
4572 * the instruction due to this rule.
4574 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4576 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4577 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4579 /* Calculate the maximum execution size of the instruction based on the
4580 * factor by which it goes over the hardware limit of 2 GRFs.
4583 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4585 /* According to the IVB PRMs:
4586 * "When destination spans two registers, the source MUST span two
4587 * registers. The exception to the above rule:
4589 * - When source is scalar, the source registers are not incremented.
4590 * - When source is packed integer Word and destination is packed
4591 * integer DWord, the source register is not incremented but the
4592 * source sub register is incremented."
4594 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4595 * restrictions. The code below intentionally doesn't check whether the
4596 * destination type is integer because empirically the hardware doesn't
4597 * seem to care what the actual type is as long as it's dword-aligned.
4599 if (devinfo
->gen
< 8) {
4600 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4601 /* IVB implements DF scalars as <0;2,1> regions. */
4602 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
4603 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
4604 const bool is_packed_word_exception
=
4605 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4606 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
4608 if (inst
->size_written
> REG_SIZE
&&
4609 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
4610 !is_scalar_exception
&& !is_packed_word_exception
) {
4611 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4612 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4617 /* From the IVB PRMs:
4618 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4619 * are applied for both halves of the SIMD32 instruction. If different
4620 * execution mask channels are required, split the instruction into two
4621 * SIMD16 instructions."
4623 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4624 * 32-wide control flow support in hardware and will behave similarly.
4626 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4627 max_width
= MIN2(max_width
, 16);
4629 /* From the IVB PRMs (applies to HSW too):
4630 * "Instructions with condition modifiers must not use SIMD32."
4632 * From the BDW PRMs (applies to later hardware too):
4633 * "Ternary instruction with condition modifiers must not use SIMD32."
4635 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4636 max_width
= MIN2(max_width
, 16);
4638 /* From the IVB PRMs (applies to other devices that don't have the
4639 * gen_device_info::supports_simd16_3src flag set):
4640 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4641 * SIMD8 is not allowed for DF operations."
4643 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4644 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4646 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4647 * the 8-bit quarter of the execution mask signals specified in the
4648 * instruction control fields) for the second compressed half of any
4649 * single-precision instruction (for double-precision instructions
4650 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4651 * the EU will apply the wrong execution controls for the second
4652 * sequential GRF write if the number of channels per GRF is not exactly
4653 * eight in single-precision mode (or four in double-float mode).
4655 * In this situation we calculate the maximum size of the split
4656 * instructions so they only ever write to a single register.
4658 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4659 !inst
->force_writemask_all
) {
4660 const unsigned channels_per_grf
= inst
->exec_size
/
4661 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4662 const unsigned exec_type_size
= get_exec_type_size(inst
);
4663 assert(exec_type_size
);
4665 /* The hardware shifts exactly 8 channels per compressed half of the
4666 * instruction in single-precision mode and exactly 4 in double-precision.
4668 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4669 max_width
= MIN2(max_width
, channels_per_grf
);
4671 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
4672 * because HW applies the same channel enable signals to both halves of
4673 * the compressed instruction which will be just wrong under
4674 * non-uniform control flow.
4676 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4677 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
4678 max_width
= MIN2(max_width
, 4);
4681 /* Only power-of-two execution sizes are representable in the instruction
4684 return 1 << _mesa_logbase2(max_width
);
4688 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4689 * various payload size restrictions that apply to sampler message
4692 * This is only intended to provide a maximum theoretical bound for the
4693 * execution size of the message based on the number of argument components
4694 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4695 * variant of the message can be used, though some messages may have
4696 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4697 * the message length to determine the exact SIMD width and argument count,
4698 * which makes a number of sampler message combinations impossible to
4702 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4703 const fs_inst
*inst
)
4705 /* Calculate the number of coordinate components that have to be present
4706 * assuming that additional arguments follow the texel coordinates in the
4707 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4708 * need to pad to four or three components depending on the message,
4709 * pre-ILK we need to pad to at most three components.
4711 const unsigned req_coord_components
=
4712 (devinfo
->gen
>= 7 ||
4713 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4714 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4715 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4718 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4719 * variant of the TXL or TXF message.
4721 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4722 (inst
->opcode
== SHADER_OPCODE_TXL
||
4723 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4724 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4726 /* Calculate the total number of argument components that need to be passed
4727 * to the sampler unit.
4729 const unsigned num_payload_components
=
4730 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4731 req_coord_components
) +
4732 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4733 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4734 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4735 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4736 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4737 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
4738 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4740 /* SIMD16 messages with more than five arguments exceed the maximum message
4741 * size supported by the sampler, regardless of whether a header is
4744 return MIN2(inst
->exec_size
,
4745 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4749 * Get the closest native SIMD width supported by the hardware for instruction
4750 * \p inst. The instruction will be left untouched by
4751 * fs_visitor::lower_simd_width() if the returned value is equal to the
4752 * original execution size.
4755 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4756 const fs_inst
*inst
)
4758 switch (inst
->opcode
) {
4759 case BRW_OPCODE_MOV
:
4760 case BRW_OPCODE_SEL
:
4761 case BRW_OPCODE_NOT
:
4762 case BRW_OPCODE_AND
:
4764 case BRW_OPCODE_XOR
:
4765 case BRW_OPCODE_SHR
:
4766 case BRW_OPCODE_SHL
:
4767 case BRW_OPCODE_ASR
:
4768 case BRW_OPCODE_CMPN
:
4769 case BRW_OPCODE_CSEL
:
4770 case BRW_OPCODE_F32TO16
:
4771 case BRW_OPCODE_F16TO32
:
4772 case BRW_OPCODE_BFREV
:
4773 case BRW_OPCODE_BFE
:
4774 case BRW_OPCODE_ADD
:
4775 case BRW_OPCODE_MUL
:
4776 case BRW_OPCODE_AVG
:
4777 case BRW_OPCODE_FRC
:
4778 case BRW_OPCODE_RNDU
:
4779 case BRW_OPCODE_RNDD
:
4780 case BRW_OPCODE_RNDE
:
4781 case BRW_OPCODE_RNDZ
:
4782 case BRW_OPCODE_LZD
:
4783 case BRW_OPCODE_FBH
:
4784 case BRW_OPCODE_FBL
:
4785 case BRW_OPCODE_CBIT
:
4786 case BRW_OPCODE_SAD2
:
4787 case BRW_OPCODE_MAD
:
4788 case BRW_OPCODE_LRP
:
4789 case FS_OPCODE_PACK
:
4790 return get_fpu_lowered_simd_width(devinfo
, inst
);
4792 case BRW_OPCODE_CMP
: {
4793 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4794 * when the destination is a GRF the dependency-clear bit on the flag
4795 * register is cleared early.
4797 * Suggested workarounds are to disable coissuing CMP instructions
4798 * or to split CMP(16) instructions into two CMP(8) instructions.
4800 * We choose to split into CMP(8) instructions since disabling
4801 * coissuing would affect CMP instructions not otherwise affected by
4804 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4805 !inst
->dst
.is_null() ? 8 : ~0);
4806 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4808 case BRW_OPCODE_BFI1
:
4809 case BRW_OPCODE_BFI2
:
4810 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4812 * "Force BFI instructions to be executed always in SIMD8."
4814 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4815 get_fpu_lowered_simd_width(devinfo
, inst
));
4818 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4819 return inst
->exec_size
;
4821 case SHADER_OPCODE_RCP
:
4822 case SHADER_OPCODE_RSQ
:
4823 case SHADER_OPCODE_SQRT
:
4824 case SHADER_OPCODE_EXP2
:
4825 case SHADER_OPCODE_LOG2
:
4826 case SHADER_OPCODE_SIN
:
4827 case SHADER_OPCODE_COS
:
4828 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4831 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4832 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4833 MIN2(8, inst
->exec_size
));
4835 case SHADER_OPCODE_POW
:
4836 /* SIMD16 is only allowed on Gen7+. */
4837 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4838 MIN2(8, inst
->exec_size
));
4840 case SHADER_OPCODE_INT_QUOTIENT
:
4841 case SHADER_OPCODE_INT_REMAINDER
:
4842 /* Integer division is limited to SIMD8 on all generations. */
4843 return MIN2(8, inst
->exec_size
);
4845 case FS_OPCODE_LINTERP
:
4846 case FS_OPCODE_GET_BUFFER_SIZE
:
4847 case FS_OPCODE_DDX_COARSE
:
4848 case FS_OPCODE_DDX_FINE
:
4849 case FS_OPCODE_DDY_COARSE
:
4850 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4851 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4852 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4853 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4854 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4855 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4856 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4857 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4858 return MIN2(16, inst
->exec_size
);
4860 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4861 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4862 * message used to implement varying pull constant loads, so expand it
4863 * to SIMD16. An alternative with longer message payload length but
4864 * shorter return payload would be to use the SIMD8 sampler message that
4865 * takes (header, u, v, r) as parameters instead of (header, u).
4867 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4869 case FS_OPCODE_DDY_FINE
:
4870 /* The implementation of this virtual opcode may require emitting
4871 * compressed Align16 instructions, which are severely limited on some
4874 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4875 * Region Restrictions):
4877 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4878 * and SIMD8 is not allowed for DF operations."
4880 * In this context, "DW operations" means "operations acting on 32-bit
4881 * values", so it includes operations on floats.
4883 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4884 * (Instruction Compression -> Rules and Restrictions):
4886 * "A compressed instruction must be in Align1 access mode. Align16
4887 * mode instructions cannot be compressed."
4889 * Similar text exists in the g45 PRM.
4891 * Empirically, compressed align16 instructions using odd register
4892 * numbers don't appear to work on Sandybridge either.
4894 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4895 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4896 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4898 case SHADER_OPCODE_MULH
:
4899 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4900 * is 8-wide on Gen7+.
4902 return (devinfo
->gen
>= 7 ? 8 :
4903 get_fpu_lowered_simd_width(devinfo
, inst
));
4905 case FS_OPCODE_FB_WRITE_LOGICAL
:
4906 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4909 assert(devinfo
->gen
!= 6 ||
4910 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4911 inst
->exec_size
== 8);
4912 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4913 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4914 8 : MIN2(16, inst
->exec_size
));
4916 case FS_OPCODE_FB_READ_LOGICAL
:
4917 return MIN2(16, inst
->exec_size
);
4919 case SHADER_OPCODE_TEX_LOGICAL
:
4920 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4921 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4922 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4923 case SHADER_OPCODE_LOD_LOGICAL
:
4924 case SHADER_OPCODE_TG4_LOGICAL
:
4925 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4926 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4927 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4928 return get_sampler_lowered_simd_width(devinfo
, inst
);
4930 case SHADER_OPCODE_TXD_LOGICAL
:
4931 /* TXD is unsupported in SIMD16 mode. */
4934 case SHADER_OPCODE_TXL_LOGICAL
:
4935 case FS_OPCODE_TXB_LOGICAL
:
4936 /* Only one execution size is representable pre-ILK depending on whether
4937 * the shadow reference argument is present.
4939 if (devinfo
->gen
== 4)
4940 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4942 return get_sampler_lowered_simd_width(devinfo
, inst
);
4944 case SHADER_OPCODE_TXF_LOGICAL
:
4945 case SHADER_OPCODE_TXS_LOGICAL
:
4946 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4947 * messages. Use SIMD16 instead.
4949 if (devinfo
->gen
== 4)
4952 return get_sampler_lowered_simd_width(devinfo
, inst
);
4954 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4955 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4956 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4959 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4960 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4961 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4962 return MIN2(16, inst
->exec_size
);
4964 case SHADER_OPCODE_URB_READ_SIMD8
:
4965 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4966 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4967 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4968 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4969 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4970 return MIN2(8, inst
->exec_size
);
4972 case SHADER_OPCODE_MOV_INDIRECT
: {
4973 /* From IVB and HSW PRMs:
4975 * "2.When the destination requires two registers and the sources are
4976 * indirect, the sources must use 1x1 regioning mode.
4978 * In case of DF instructions in HSW/IVB, the exec_size is limited by
4979 * the EU decompression logic not handling VxH indirect addressing
4982 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
4983 /* Prior to Broadwell, we only have 8 address subregisters. */
4984 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4985 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4989 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4990 const unsigned reg_count
=
4991 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
4993 if (reg_count
> 2) {
4994 /* Only LOAD_PAYLOAD instructions with per-channel destination region
4995 * can be easily lowered (which excludes headers and heterogeneous
4998 assert(!inst
->header_size
);
4999 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5000 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5001 inst
->src
[i
].file
== BAD_FILE
);
5003 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5005 return inst
->exec_size
;
5009 return inst
->exec_size
;
5014 * Return true if splitting out the group of channels of instruction \p inst
5015 * given by lbld.group() requires allocating a temporary for the i-th source
5016 * of the lowered instruction.
5019 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5021 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5022 (inst
->components_read(i
) == 1 &&
5023 lbld
.dispatch_width() <= inst
->exec_size
)) ||
5024 (inst
->flags_written() &
5025 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
5029 * Extract the data that would be consumed by the channel group given by
5030 * lbld.group() from the i-th source region of instruction \p inst and return
5031 * it as result in packed form. If any copy instructions are required they
5032 * will be emitted before the given \p inst in \p block.
5035 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
5038 /* Specified channel group from the source region. */
5039 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5041 if (needs_src_copy(lbld
, inst
, i
)) {
5042 /* Builder of the right width to perform the copy avoiding uninitialized
5043 * data if the lowered execution size is greater than the original
5044 * execution size of the instruction.
5046 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5047 inst
->exec_size
), 0);
5048 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5050 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5051 cbld
.at(block
, inst
)
5052 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5056 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5057 /* The source is invariant for all dispatch_width-wide groups of the
5060 return inst
->src
[i
];
5063 /* We can just point the lowered instruction at the right channel group
5064 * from the original region.
5071 * Return true if splitting out the group of channels of instruction \p inst
5072 * given by lbld.group() requires allocating a temporary for the destination
5073 * of the lowered instruction and copying the data back to the original
5074 * destination region.
5077 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5079 /* If the instruction writes more than one component we'll have to shuffle
5080 * the results of multiple lowered instructions in order to make sure that
5081 * they end up arranged correctly in the original destination region.
5083 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5086 /* If the lowered execution size is larger than the original the result of
5087 * the instruction won't fit in the original destination, so we'll have to
5088 * allocate a temporary in any case.
5090 if (lbld
.dispatch_width() > inst
->exec_size
)
5093 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5094 /* If we already made a copy of the source for other reasons there won't
5095 * be any overlap with the destination.
5097 if (needs_src_copy(lbld
, inst
, i
))
5100 /* In order to keep the logic simple we emit a copy whenever the
5101 * destination region doesn't exactly match an overlapping source, which
5102 * may point at the source and destination not being aligned group by
5103 * group which could cause one of the lowered instructions to overwrite
5104 * the data read from the same source by other lowered instructions.
5106 if (regions_overlap(inst
->dst
, inst
->size_written
,
5107 inst
->src
[i
], inst
->size_read(i
)) &&
5108 !inst
->dst
.equals(inst
->src
[i
]))
5116 * Insert data from a packed temporary into the channel group given by
5117 * lbld.group() of the destination region of instruction \p inst and return
5118 * the temporary as result. If any copy instructions are required they will
5119 * be emitted around the given \p inst in \p block.
5122 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5124 /* Builder of the right width to perform the copy avoiding uninitialized
5125 * data if the lowered execution size is greater than the original
5126 * execution size of the instruction.
5128 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5129 inst
->exec_size
), 0);
5131 /* Specified channel group from the destination region. */
5132 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5133 const unsigned dst_size
= inst
->size_written
/
5134 inst
->dst
.component_size(inst
->exec_size
);
5136 if (needs_dst_copy(lbld
, inst
)) {
5137 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5139 if (inst
->predicate
) {
5140 /* Handle predication by copying the original contents of
5141 * the destination into the temporary before emitting the
5142 * lowered instruction.
5144 for (unsigned k
= 0; k
< dst_size
; ++k
)
5145 cbld
.at(block
, inst
)
5146 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5149 for (unsigned k
= 0; k
< dst_size
; ++k
)
5150 cbld
.at(block
, inst
->next
)
5151 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5156 /* No need to allocate a temporary for the lowered instruction, just
5157 * take the right group of channels from the original region.
5164 fs_visitor::lower_simd_width()
5166 bool progress
= false;
5168 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5169 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5171 if (lower_width
!= inst
->exec_size
) {
5172 /* Builder matching the original instruction. We may also need to
5173 * emit an instruction of width larger than the original, set the
5174 * execution size of the builder to the highest of both for now so
5175 * we're sure that both cases can be handled.
5177 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5178 const fs_builder ibld
= bld
.at(block
, inst
)
5179 .exec_all(inst
->force_writemask_all
)
5180 .group(max_width
, inst
->group
/ max_width
);
5182 /* Split the copies in chunks of the execution width of either the
5183 * original or the lowered instruction, whichever is lower.
5185 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5186 const unsigned dst_size
= inst
->size_written
/
5187 inst
->dst
.component_size(inst
->exec_size
);
5189 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5191 for (unsigned i
= 0; i
< n
; i
++) {
5192 /* Emit a copy of the original instruction with the lowered width.
5193 * If the EOT flag was set throw it away except for the last
5194 * instruction to avoid killing the thread prematurely.
5196 fs_inst split_inst
= *inst
;
5197 split_inst
.exec_size
= lower_width
;
5198 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5200 /* Select the correct channel enables for the i-th group, then
5201 * transform the sources and destination and emit the lowered
5204 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5206 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5207 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5209 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5210 split_inst
.size_written
=
5211 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5213 lbld
.emit(split_inst
);
5216 inst
->remove(block
);
5222 invalidate_live_intervals();
5228 fs_visitor::dump_instructions()
5230 dump_instructions(NULL
);
5234 fs_visitor::dump_instructions(const char *name
)
5236 FILE *file
= stderr
;
5237 if (name
&& geteuid() != 0) {
5238 file
= fopen(name
, "w");
5244 calculate_register_pressure();
5245 int ip
= 0, max_pressure
= 0;
5246 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5247 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5248 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5249 dump_instruction(inst
, file
);
5252 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5255 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5256 fprintf(file
, "%4d: ", ip
++);
5257 dump_instruction(inst
, file
);
5261 if (file
!= stderr
) {
5267 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5269 dump_instruction(be_inst
, stderr
);
5273 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5275 fs_inst
*inst
= (fs_inst
*)be_inst
;
5277 if (inst
->predicate
) {
5278 fprintf(file
, "(%cf0.%d) ",
5279 inst
->predicate_inverse
? '-' : '+',
5283 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5285 fprintf(file
, ".sat");
5286 if (inst
->conditional_mod
) {
5287 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5288 if (!inst
->predicate
&&
5289 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5290 inst
->opcode
!= BRW_OPCODE_IF
&&
5291 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5292 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5295 fprintf(file
, "(%d) ", inst
->exec_size
);
5298 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5302 fprintf(file
, "(EOT) ");
5305 switch (inst
->dst
.file
) {
5307 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5310 fprintf(file
, "g%d", inst
->dst
.nr
);
5313 fprintf(file
, "m%d", inst
->dst
.nr
);
5316 fprintf(file
, "(null)");
5319 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5322 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5325 switch (inst
->dst
.nr
) {
5327 fprintf(file
, "null");
5329 case BRW_ARF_ADDRESS
:
5330 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5332 case BRW_ARF_ACCUMULATOR
:
5333 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5336 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5339 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5344 unreachable("not reached");
5347 if (inst
->dst
.offset
||
5348 (inst
->dst
.file
== VGRF
&&
5349 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5350 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5351 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5352 inst
->dst
.offset
% reg_size
);
5355 if (inst
->dst
.stride
!= 1)
5356 fprintf(file
, "<%u>", inst
->dst
.stride
);
5357 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
5359 for (int i
= 0; i
< inst
->sources
; i
++) {
5360 if (inst
->src
[i
].negate
)
5362 if (inst
->src
[i
].abs
)
5364 switch (inst
->src
[i
].file
) {
5366 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5369 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5372 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5375 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5378 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5381 fprintf(file
, "(null)");
5384 switch (inst
->src
[i
].type
) {
5385 case BRW_REGISTER_TYPE_F
:
5386 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5388 case BRW_REGISTER_TYPE_DF
:
5389 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5391 case BRW_REGISTER_TYPE_W
:
5392 case BRW_REGISTER_TYPE_D
:
5393 fprintf(file
, "%dd", inst
->src
[i
].d
);
5395 case BRW_REGISTER_TYPE_UW
:
5396 case BRW_REGISTER_TYPE_UD
:
5397 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5399 case BRW_REGISTER_TYPE_VF
:
5400 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5401 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5402 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5403 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5404 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5407 fprintf(file
, "???");
5412 switch (inst
->src
[i
].nr
) {
5414 fprintf(file
, "null");
5416 case BRW_ARF_ADDRESS
:
5417 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5419 case BRW_ARF_ACCUMULATOR
:
5420 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5423 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5426 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5432 if (inst
->src
[i
].offset
||
5433 (inst
->src
[i
].file
== VGRF
&&
5434 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5435 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5436 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5437 inst
->src
[i
].offset
% reg_size
);
5440 if (inst
->src
[i
].abs
)
5443 if (inst
->src
[i
].file
!= IMM
) {
5445 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5446 unsigned hstride
= inst
->src
[i
].hstride
;
5447 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5449 stride
= inst
->src
[i
].stride
;
5452 fprintf(file
, "<%u>", stride
);
5454 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
5457 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5458 fprintf(file
, ", ");
5463 if (inst
->force_writemask_all
)
5464 fprintf(file
, "NoMask ");
5466 if (inst
->exec_size
!= dispatch_width
)
5467 fprintf(file
, "group%d ", inst
->group
);
5469 fprintf(file
, "\n");
5473 * Possibly returns an instruction that set up @param reg.
5475 * Sometimes we want to take the result of some expression/variable
5476 * dereference tree and rewrite the instruction generating the result
5477 * of the tree. When processing the tree, we know that the
5478 * instructions generated are all writing temporaries that are dead
5479 * outside of this tree. So, if we have some instructions that write
5480 * a temporary, we're free to point that temp write somewhere else.
5482 * Note that this doesn't guarantee that the instruction generated
5483 * only reg -- it might be the size=4 destination of a texture instruction.
5486 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5491 end
->is_partial_write() ||
5492 !reg
.equals(end
->dst
)) {
5500 fs_visitor::setup_fs_payload_gen6()
5502 assert(stage
== MESA_SHADER_FRAGMENT
);
5503 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
5505 assert(devinfo
->gen
>= 6);
5507 /* R0-1: masks, pixel X/Y coordinates. */
5508 payload
.num_regs
= 2;
5509 /* R2: only for 32-pixel dispatch.*/
5511 /* R3-26: barycentric interpolation coordinates. These appear in the
5512 * same order that they appear in the brw_barycentric_mode
5513 * enum. Each set of coordinates occupies 2 registers if dispatch width
5514 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5515 * appear if they were enabled using the "Barycentric Interpolation
5516 * Mode" bits in WM_STATE.
5518 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5519 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
5520 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5521 payload
.num_regs
+= 2;
5522 if (dispatch_width
== 16) {
5523 payload
.num_regs
+= 2;
5528 /* R27: interpolated depth if uses source depth */
5529 prog_data
->uses_src_depth
=
5530 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5531 if (prog_data
->uses_src_depth
) {
5532 payload
.source_depth_reg
= payload
.num_regs
;
5534 if (dispatch_width
== 16) {
5535 /* R28: interpolated depth if not SIMD8. */
5540 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5541 prog_data
->uses_src_w
=
5542 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5543 if (prog_data
->uses_src_w
) {
5544 payload
.source_w_reg
= payload
.num_regs
;
5546 if (dispatch_width
== 16) {
5547 /* R30: interpolated W if not SIMD8. */
5552 /* R31: MSAA position offsets. */
5553 if (prog_data
->persample_dispatch
&&
5554 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5555 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5557 * "MSDISPMODE_PERSAMPLE is required in order to select
5560 * So we can only really get sample positions if we are doing real
5561 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5562 * persample dispatch, we hard-code it to 0.5.
5564 prog_data
->uses_pos_offset
= true;
5565 payload
.sample_pos_reg
= payload
.num_regs
;
5569 /* R32: MSAA input coverage mask */
5570 prog_data
->uses_sample_mask
=
5571 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5572 if (prog_data
->uses_sample_mask
) {
5573 assert(devinfo
->gen
>= 7);
5574 payload
.sample_mask_in_reg
= payload
.num_regs
;
5576 if (dispatch_width
== 16) {
5577 /* R33: input coverage mask if not SIMD8. */
5582 /* R34-: bary for 32-pixel. */
5583 /* R58-59: interp W for 32-pixel. */
5585 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5586 source_depth_to_render_target
= true;
5591 fs_visitor::setup_vs_payload()
5593 /* R0: thread header, R1: urb handles */
5594 payload
.num_regs
= 2;
5598 fs_visitor::setup_gs_payload()
5600 assert(stage
== MESA_SHADER_GEOMETRY
);
5602 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
5603 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
5605 /* R0: thread header, R1: output URB handles */
5606 payload
.num_regs
= 2;
5608 if (gs_prog_data
->include_primitive_id
) {
5609 /* R2: Primitive ID 0..7 */
5613 /* Always enable VUE handles so we can safely use pull model if needed.
5615 * The push model for a GS uses a ton of register space even for trivial
5616 * scenarios with just a few inputs, so just make things easier and a bit
5617 * safer by always having pull model available.
5619 gs_prog_data
->base
.include_vue_handles
= true;
5621 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5622 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5624 /* Use a maximum of 24 registers for push-model inputs. */
5625 const unsigned max_push_components
= 24;
5627 /* If pushing our inputs would take too many registers, reduce the URB read
5628 * length (which is in HWords, or 8 registers), and resort to pulling.
5630 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5631 * have to multiply by VerticesIn to obtain the total storage requirement.
5633 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5634 max_push_components
) {
5635 vue_prog_data
->urb_read_length
=
5636 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5641 fs_visitor::setup_cs_payload()
5643 assert(devinfo
->gen
>= 7);
5644 payload
.num_regs
= 1;
5648 fs_visitor::calculate_register_pressure()
5650 invalidate_live_intervals();
5651 calculate_live_intervals();
5653 unsigned num_instructions
= 0;
5654 foreach_block(block
, cfg
)
5655 num_instructions
+= block
->instructions
.length();
5657 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5659 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5660 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5661 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5666 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5668 * The needs_unlit_centroid_workaround ends up producing one of these per
5669 * channel of centroid input, so it's good to clean them up.
5671 * An assumption here is that nothing ever modifies the dispatched pixels
5672 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5673 * dictates that anyway.
5676 fs_visitor::opt_drop_redundant_mov_to_flags()
5678 bool flag_mov_found
[2] = {false};
5679 bool progress
= false;
5681 /* Instructions removed by this pass can only be added if this were true */
5682 if (!devinfo
->needs_unlit_centroid_workaround
)
5685 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5686 if (inst
->is_control_flow()) {
5687 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5688 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5689 if (!flag_mov_found
[inst
->flag_subreg
]) {
5690 flag_mov_found
[inst
->flag_subreg
] = true;
5692 inst
->remove(block
);
5695 } else if (inst
->flags_written()) {
5696 flag_mov_found
[inst
->flag_subreg
] = false;
5704 fs_visitor::optimize()
5706 /* Start by validating the shader we currently have. */
5709 /* bld is the common builder object pointing at the end of the program we
5710 * used to translate it into i965 IR. For the optimization and lowering
5711 * passes coming next, any code added after the end of the program without
5712 * having explicitly called fs_builder::at() clearly points at a mistake.
5713 * Ideally optimization passes wouldn't be part of the visitor so they
5714 * wouldn't have access to bld at all, but they do, so just in case some
5715 * pass forgets to ask for a location explicitly set it to NULL here to
5716 * make it trip. The dispatch width is initialized to a bogus value to
5717 * make sure that optimizations set the execution controls explicitly to
5718 * match the code they are manipulating instead of relying on the defaults.
5720 bld
= fs_builder(this, 64);
5722 assign_constant_locations();
5723 lower_constant_loads();
5727 split_virtual_grfs();
5730 #define OPT(pass, args...) ({ \
5732 bool this_progress = pass(args); \
5734 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5735 char filename[64]; \
5736 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5737 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5739 backend_shader::dump_instructions(filename); \
5744 progress = progress || this_progress; \
5748 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5750 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5751 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5753 backend_shader::dump_instructions(filename
);
5756 bool progress
= false;
5760 OPT(opt_drop_redundant_mov_to_flags
);
5767 OPT(remove_duplicate_mrf_writes
);
5771 OPT(opt_copy_propagation
);
5772 OPT(opt_predicated_break
, this);
5773 OPT(opt_cmod_propagation
);
5774 OPT(dead_code_eliminate
);
5775 OPT(opt_peephole_sel
);
5776 OPT(dead_control_flow_eliminate
, this);
5777 OPT(opt_register_renaming
);
5778 OPT(opt_saturate_propagation
);
5779 OPT(register_coalesce
);
5780 OPT(compute_to_mrf
);
5781 OPT(eliminate_find_live_channel
);
5783 OPT(compact_virtual_grfs
);
5789 if (OPT(lower_pack
)) {
5790 OPT(register_coalesce
);
5791 OPT(dead_code_eliminate
);
5794 OPT(lower_simd_width
);
5796 /* After SIMD lowering just in case we had to unroll the EOT send. */
5797 OPT(opt_sampler_eot
);
5799 OPT(lower_logical_sends
);
5802 OPT(opt_copy_propagation
);
5803 /* Only run after logical send lowering because it's easier to implement
5804 * in terms of physical sends.
5806 if (OPT(opt_zero_samples
))
5807 OPT(opt_copy_propagation
);
5808 /* Run after logical send lowering to give it a chance to CSE the
5809 * LOAD_PAYLOAD instructions created to construct the payloads of
5810 * e.g. texturing messages in cases where it wasn't possible to CSE the
5811 * whole logical instruction.
5814 OPT(register_coalesce
);
5815 OPT(compute_to_mrf
);
5816 OPT(dead_code_eliminate
);
5817 OPT(remove_duplicate_mrf_writes
);
5818 OPT(opt_peephole_sel
);
5821 OPT(opt_redundant_discard_jumps
);
5823 if (OPT(lower_load_payload
)) {
5824 split_virtual_grfs();
5825 OPT(register_coalesce
);
5826 OPT(compute_to_mrf
);
5827 OPT(dead_code_eliminate
);
5830 OPT(opt_combine_constants
);
5831 OPT(lower_integer_multiplication
);
5833 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5834 OPT(opt_cmod_propagation
);
5836 OPT(opt_copy_propagation
);
5837 OPT(dead_code_eliminate
);
5840 if (OPT(lower_conversions
)) {
5841 OPT(opt_copy_propagation
);
5842 OPT(dead_code_eliminate
);
5843 OPT(lower_simd_width
);
5846 lower_uniform_pull_constant_loads();
5852 * Three source instruction must have a GRF/MRF destination register.
5853 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5856 fs_visitor::fixup_3src_null_dest()
5858 bool progress
= false;
5860 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5861 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5862 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5869 invalidate_live_intervals();
5873 fs_visitor::allocate_registers(bool allow_spilling
)
5875 bool allocated_without_spills
;
5877 static const enum instruction_scheduler_mode pre_modes
[] = {
5879 SCHEDULE_PRE_NON_LIFO
,
5883 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5885 /* Try each scheduling heuristic to see if it can successfully register
5886 * allocate without spilling. They should be ordered by decreasing
5887 * performance but increasing likelihood of allocating.
5889 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5890 schedule_instructions(pre_modes
[i
]);
5893 assign_regs_trivial();
5894 allocated_without_spills
= true;
5896 allocated_without_spills
= assign_regs(false, spill_all
);
5898 if (allocated_without_spills
)
5902 if (!allocated_without_spills
) {
5903 if (!allow_spilling
)
5904 fail("Failure to register allocate and spilling is not allowed.");
5906 /* We assume that any spilling is worse than just dropping back to
5907 * SIMD8. There's probably actually some intermediate point where
5908 * SIMD16 with a couple of spills is still better.
5910 if (dispatch_width
> min_dispatch_width
) {
5911 fail("Failure to register allocate. Reduce number of "
5912 "live scalar values to avoid this.");
5914 compiler
->shader_perf_log(log_data
,
5915 "%s shader triggered register spilling. "
5916 "Try reducing the number of live scalar "
5917 "values to improve performance.\n",
5921 /* Since we're out of heuristics, just go spill registers until we
5922 * get an allocation.
5924 while (!assign_regs(true, spill_all
)) {
5930 /* This must come after all optimization and register allocation, since
5931 * it inserts dead code that happens to have side effects, and it does
5932 * so based on the actual physical registers in use.
5934 insert_gen4_send_dependency_workarounds();
5939 schedule_instructions(SCHEDULE_POST
);
5941 if (last_scratch
> 0) {
5942 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
5944 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5946 if (stage
== MESA_SHADER_COMPUTE
) {
5947 if (devinfo
->is_haswell
) {
5948 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5949 * field documentation, Haswell supports a minimum of 2kB of
5950 * scratch space for compute shaders, unlike every other stage
5953 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5954 } else if (devinfo
->gen
<= 7) {
5955 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5956 * field documentation, platforms prior to Haswell measure scratch
5957 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5959 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5960 max_scratch_size
= 12 * 1024;
5964 /* We currently only support up to 2MB of scratch space. If we
5965 * need to support more eventually, the documentation suggests
5966 * that we could allocate a larger buffer, and partition it out
5967 * ourselves. We'd just have to undo the hardware's address
5968 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5969 * and then add FFTID * (Larger Per Thread Scratch Space).
5971 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5972 * Thread Group Tracking > Local Memory/Scratch Space.
5974 assert(prog_data
->total_scratch
< max_scratch_size
);
5979 fs_visitor::run_vs()
5981 assert(stage
== MESA_SHADER_VERTEX
);
5985 if (shader_time_index
>= 0)
5986 emit_shader_time_begin();
5993 compute_clip_distance();
5997 if (shader_time_index
>= 0)
5998 emit_shader_time_end();
6004 assign_curb_setup();
6005 assign_vs_urb_setup();
6007 fixup_3src_null_dest();
6008 allocate_registers(true);
6014 fs_visitor::run_tcs_single_patch()
6016 assert(stage
== MESA_SHADER_TESS_CTRL
);
6018 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
6020 /* r1-r4 contain the ICP handles. */
6021 payload
.num_regs
= 5;
6023 if (shader_time_index
>= 0)
6024 emit_shader_time_begin();
6026 /* Initialize gl_InvocationID */
6027 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6028 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6029 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6030 bld
.MOV(channels_ud
, channels_uw
);
6032 if (tcs_prog_data
->instances
== 1) {
6033 invocation_id
= channels_ud
;
6035 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6037 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6038 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6039 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6040 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6041 brw_imm_ud(INTEL_MASK(23, 17)));
6042 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6044 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6047 /* Fix the disptach mask */
6048 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6049 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6050 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
6051 bld
.IF(BRW_PREDICATE_NORMAL
);
6056 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6057 bld
.emit(BRW_OPCODE_ENDIF
);
6060 /* Emit EOT write; set TR DS Cache bit */
6062 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6063 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6064 fs_reg(brw_imm_ud(0)),
6066 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6067 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6069 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6070 bld
.null_reg_ud(), payload
);
6074 if (shader_time_index
>= 0)
6075 emit_shader_time_end();
6084 assign_curb_setup();
6085 assign_tcs_single_patch_urb_setup();
6087 fixup_3src_null_dest();
6088 allocate_registers(true);
6094 fs_visitor::run_tes()
6096 assert(stage
== MESA_SHADER_TESS_EVAL
);
6098 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6099 payload
.num_regs
= 5;
6101 if (shader_time_index
>= 0)
6102 emit_shader_time_begin();
6111 if (shader_time_index
>= 0)
6112 emit_shader_time_end();
6118 assign_curb_setup();
6119 assign_tes_urb_setup();
6121 fixup_3src_null_dest();
6122 allocate_registers(true);
6128 fs_visitor::run_gs()
6130 assert(stage
== MESA_SHADER_GEOMETRY
);
6134 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6136 if (gs_compile
->control_data_header_size_bits
> 0) {
6137 /* Create a VGRF to store accumulated control data bits. */
6138 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6140 /* If we're outputting more than 32 control data bits, then EmitVertex()
6141 * will set control_data_bits to 0 after emitting the first vertex.
6142 * Otherwise, we need to initialize it to 0 here.
6144 if (gs_compile
->control_data_header_size_bits
<= 32) {
6145 const fs_builder abld
= bld
.annotate("initialize control data bits");
6146 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6150 if (shader_time_index
>= 0)
6151 emit_shader_time_begin();
6155 emit_gs_thread_end();
6157 if (shader_time_index
>= 0)
6158 emit_shader_time_end();
6167 assign_curb_setup();
6168 assign_gs_urb_setup();
6170 fixup_3src_null_dest();
6171 allocate_registers(true);
6176 /* From the SKL PRM, Volume 16, Workarounds:
6178 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
6179 * only header phases (R0-R2)
6181 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
6182 * have been header only.
6184 * Instead of enabling push constants one can alternatively enable one of the
6185 * inputs. Here one simply chooses "layer" which shouldn't impose much
6189 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
6191 if (wm_prog_data
->num_varying_inputs
)
6194 if (wm_prog_data
->base
.curb_read_length
)
6197 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
6198 wm_prog_data
->num_varying_inputs
= 1;
6202 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6204 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6205 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6207 assert(stage
== MESA_SHADER_FRAGMENT
);
6209 if (devinfo
->gen
>= 6)
6210 setup_fs_payload_gen6();
6212 setup_fs_payload_gen4();
6216 } else if (do_rep_send
) {
6217 assert(dispatch_width
== 16);
6218 emit_repclear_shader();
6220 if (shader_time_index
>= 0)
6221 emit_shader_time_begin();
6223 calculate_urb_setup();
6224 if (nir
->info
.inputs_read
> 0 ||
6225 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6226 if (devinfo
->gen
< 6)
6227 emit_interpolation_setup_gen4();
6229 emit_interpolation_setup_gen6();
6232 /* We handle discards by keeping track of the still-live pixels in f0.1.
6233 * Initialize it with the dispatched pixels.
6235 if (wm_prog_data
->uses_kill
) {
6236 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6237 discard_init
->flag_subreg
= 1;
6240 /* Generate FS IR for main(). (the visitor only descends into
6241 * functions called "main").
6248 if (wm_prog_data
->uses_kill
)
6249 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6251 if (wm_key
->alpha_test_func
)
6256 if (shader_time_index
>= 0)
6257 emit_shader_time_end();
6263 assign_curb_setup();
6265 if (devinfo
->gen
>= 9)
6266 gen9_ps_header_only_workaround(wm_prog_data
);
6270 fixup_3src_null_dest();
6271 allocate_registers(allow_spilling
);
6281 fs_visitor::run_cs()
6283 assert(stage
== MESA_SHADER_COMPUTE
);
6287 if (shader_time_index
>= 0)
6288 emit_shader_time_begin();
6290 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6291 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6292 const fs_builder abld
= bld
.exec_all().group(1, 0);
6293 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6294 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6302 emit_cs_terminate();
6304 if (shader_time_index
>= 0)
6305 emit_shader_time_end();
6311 assign_curb_setup();
6313 fixup_3src_null_dest();
6314 allocate_registers(true);
6323 * Return a bitfield where bit n is set if barycentric interpolation mode n
6324 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6326 * We examine the load_barycentric intrinsics rather than looking at input
6327 * variables so that we catch interpolateAtCentroid() messages too, which
6328 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6331 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6332 const nir_shader
*shader
)
6334 unsigned barycentric_interp_modes
= 0;
6336 nir_foreach_function(f
, shader
) {
6340 nir_foreach_block(block
, f
->impl
) {
6341 nir_foreach_instr(instr
, block
) {
6342 if (instr
->type
!= nir_instr_type_intrinsic
)
6345 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6346 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6349 /* Ignore WPOS; it doesn't require interpolation. */
6350 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6353 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6354 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6355 nir_intrinsic_interp_mode(intrin
);
6356 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6357 enum brw_barycentric_mode bary
=
6358 brw_barycentric_mode(interp
, bary_op
);
6360 barycentric_interp_modes
|= 1 << bary
;
6362 if (devinfo
->needs_unlit_centroid_workaround
&&
6363 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6364 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6369 return barycentric_interp_modes
;
6373 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6374 const nir_shader
*shader
)
6376 prog_data
->flat_inputs
= 0;
6378 nir_foreach_variable(var
, &shader
->inputs
) {
6379 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6381 if (input_index
< 0)
6385 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6386 prog_data
->flat_inputs
|= (1 << input_index
);
6391 computed_depth_mode(const nir_shader
*shader
)
6393 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6394 switch (shader
->info
.fs
.depth_layout
) {
6395 case FRAG_DEPTH_LAYOUT_NONE
:
6396 case FRAG_DEPTH_LAYOUT_ANY
:
6397 return BRW_PSCDEPTH_ON
;
6398 case FRAG_DEPTH_LAYOUT_GREATER
:
6399 return BRW_PSCDEPTH_ON_GE
;
6400 case FRAG_DEPTH_LAYOUT_LESS
:
6401 return BRW_PSCDEPTH_ON_LE
;
6402 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6403 return BRW_PSCDEPTH_OFF
;
6406 return BRW_PSCDEPTH_OFF
;
6410 * Move load_interpolated_input with simple (payload-based) barycentric modes
6411 * to the top of the program so we don't emit multiple PLNs for the same input.
6413 * This works around CSE not being able to handle non-dominating cases
6419 * interpolate the same exact input
6422 * This should be replaced by global value numbering someday.
6425 move_interpolation_to_top(nir_shader
*nir
)
6427 bool progress
= false;
6429 nir_foreach_function(f
, nir
) {
6433 nir_block
*top
= nir_start_block(f
->impl
);
6434 exec_node
*cursor_node
= NULL
;
6436 nir_foreach_block(block
, f
->impl
) {
6440 nir_foreach_instr_safe(instr
, block
) {
6441 if (instr
->type
!= nir_instr_type_intrinsic
)
6444 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6445 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6447 nir_intrinsic_instr
*bary_intrinsic
=
6448 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6449 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6451 /* Leave interpolateAtSample/Offset() where they are. */
6452 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6453 op
== nir_intrinsic_load_barycentric_at_offset
)
6456 nir_instr
*move
[3] = {
6457 &bary_intrinsic
->instr
,
6458 intrin
->src
[1].ssa
->parent_instr
,
6462 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6463 if (move
[i
]->block
!= top
) {
6464 move
[i
]->block
= top
;
6465 exec_node_remove(&move
[i
]->node
);
6467 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6469 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6471 cursor_node
= &move
[i
]->node
;
6477 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6478 ((unsigned) nir_metadata_block_index
|
6479 (unsigned) nir_metadata_dominance
));
6486 * Demote per-sample barycentric intrinsics to centroid.
6488 * Useful when rendering to a non-multisampled buffer.
6491 demote_sample_qualifiers(nir_shader
*nir
)
6493 bool progress
= true;
6495 nir_foreach_function(f
, nir
) {
6500 nir_builder_init(&b
, f
->impl
);
6502 nir_foreach_block(block
, f
->impl
) {
6503 nir_foreach_instr_safe(instr
, block
) {
6504 if (instr
->type
!= nir_instr_type_intrinsic
)
6507 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6508 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6509 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6512 b
.cursor
= nir_before_instr(instr
);
6513 nir_ssa_def
*centroid
=
6514 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6515 nir_intrinsic_interp_mode(intrin
));
6516 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6517 nir_src_for_ssa(centroid
));
6518 nir_instr_remove(instr
);
6523 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6524 ((unsigned) nir_metadata_block_index
|
6525 (unsigned) nir_metadata_dominance
));
6532 * Pre-gen6, the register file of the EUs was shared between threads,
6533 * and each thread used some subset allocated on a 16-register block
6534 * granularity. The unit states wanted these block counts.
6537 brw_register_blocks(int reg_count
)
6539 return ALIGN(reg_count
, 16) / 16 - 1;
6543 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6545 const struct brw_wm_prog_key
*key
,
6546 struct brw_wm_prog_data
*prog_data
,
6547 const nir_shader
*src_shader
,
6548 struct gl_program
*prog
,
6549 int shader_time_index8
, int shader_time_index16
,
6550 bool allow_spilling
,
6551 bool use_rep_send
, struct brw_vue_map
*vue_map
,
6554 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
6556 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6557 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6558 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
6559 brw_nir_lower_fs_outputs(shader
);
6561 if (devinfo
->gen
< 6) {
6562 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
, devinfo
);
6565 if (!key
->multisample_fbo
)
6566 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6567 NIR_PASS_V(shader
, move_interpolation_to_top
);
6568 shader
= brw_postprocess_nir(shader
, compiler
, true);
6570 /* key->alpha_test_func means simulating alpha testing via discards,
6571 * so the shader definitely kills pixels.
6573 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
6574 key
->alpha_test_func
;
6575 prog_data
->uses_omask
= key
->multisample_fbo
&&
6576 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6577 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6578 prog_data
->computed_stencil
=
6579 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6581 prog_data
->persample_dispatch
=
6582 key
->multisample_fbo
&&
6583 (key
->persample_interp
||
6584 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6585 SYSTEM_BIT_SAMPLE_POS
)) ||
6586 shader
->info
.fs
.uses_sample_qualifier
||
6587 shader
->info
.outputs_read
);
6589 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
6591 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6592 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
6593 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
6595 prog_data
->barycentric_interp_modes
=
6596 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6598 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6599 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6600 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6602 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6603 &prog_data
->base
, prog
, shader
, 8,
6604 shader_time_index8
);
6605 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6607 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6610 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6612 simd8_grf_start
= v8
.payload
.num_regs
;
6613 simd8_grf_used
= v8
.grf_used
;
6616 if (v8
.max_dispatch_width
>= 16 &&
6617 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6618 /* Try a SIMD16 compile */
6619 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6620 &prog_data
->base
, prog
, shader
, 16,
6621 shader_time_index16
);
6622 v16
.import_uniforms(&v8
);
6623 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6624 compiler
->shader_perf_log(log_data
,
6625 "SIMD16 shader failed to compile: %s",
6628 simd16_cfg
= v16
.cfg
;
6629 simd16_grf_start
= v16
.payload
.num_regs
;
6630 simd16_grf_used
= v16
.grf_used
;
6634 /* When the caller requests a repclear shader, they want SIMD16-only */
6638 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6639 * at the top to select the shader. We've never implemented that.
6640 * Instead, we just give them exactly one shader and we pick the widest one
6643 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6646 if (prog_data
->persample_dispatch
) {
6647 /* Starting with SandyBridge (where we first get MSAA), the different
6648 * pixel dispatch combinations are grouped into classifications A
6649 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6650 * generations, the only configurations supporting persample dispatch
6651 * are are this in which only one dispatch width is enabled.
6653 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6654 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6656 if (compiler
->devinfo
->gen
== 6 &&
6657 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6659 } else if (simd16_cfg
) {
6664 /* We have to compute the flat inputs after the visitor is finished running
6665 * because it relies on prog_data->urb_setup which is computed in
6666 * fs_visitor::calculate_urb_setup().
6668 brw_compute_flat_inputs(prog_data
, shader
);
6670 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6671 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6672 MESA_SHADER_FRAGMENT
);
6674 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6675 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6676 shader
->info
.label
?
6677 shader
->info
.label
: "unnamed",
6678 shader
->info
.name
));
6682 prog_data
->dispatch_8
= true;
6683 g
.generate_code(simd8_cfg
, 8);
6684 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6685 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6688 prog_data
->dispatch_16
= true;
6689 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6690 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6691 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6693 } else if (simd16_cfg
) {
6694 prog_data
->dispatch_16
= true;
6695 g
.generate_code(simd16_cfg
, 16);
6696 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6697 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6700 return g
.get_assembly(&prog_data
->base
.program_size
);
6704 fs_visitor::emit_cs_work_group_id_setup()
6706 assert(stage
== MESA_SHADER_COMPUTE
);
6708 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6710 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6711 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6712 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6714 bld
.MOV(*reg
, r0_1
);
6715 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6716 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6722 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6724 block
->dwords
= dwords
;
6725 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6726 block
->size
= block
->regs
* 32;
6730 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6731 struct brw_cs_prog_data
*cs_prog_data
)
6733 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
6734 int thread_local_id_index
= get_thread_local_id_param_index(prog_data
);
6735 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6737 /* The thread ID should be stored in the last param dword */
6738 assert(thread_local_id_index
== -1 ||
6739 thread_local_id_index
== (int)prog_data
->nr_params
- 1);
6741 unsigned cross_thread_dwords
, per_thread_dwords
;
6742 if (!cross_thread_supported
) {
6743 cross_thread_dwords
= 0u;
6744 per_thread_dwords
= prog_data
->nr_params
;
6745 } else if (thread_local_id_index
>= 0) {
6746 /* Fill all but the last register with cross-thread payload */
6747 cross_thread_dwords
= 8 * (thread_local_id_index
/ 8);
6748 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6749 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6751 /* Fill all data using cross-thread payload */
6752 cross_thread_dwords
= prog_data
->nr_params
;
6753 per_thread_dwords
= 0u;
6756 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6757 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6759 unsigned total_dwords
=
6760 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6761 cs_prog_data
->push
.cross_thread
.size
) / 4;
6762 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6764 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6765 cs_prog_data
->push
.per_thread
.size
== 0);
6766 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6767 cs_prog_data
->push
.per_thread
.dwords
==
6768 prog_data
->nr_params
);
6772 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6774 cs_prog_data
->simd_size
= size
;
6775 unsigned group_size
= cs_prog_data
->local_size
[0] *
6776 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6777 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6781 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6783 const struct brw_cs_prog_key
*key
,
6784 struct brw_cs_prog_data
*prog_data
,
6785 const nir_shader
*src_shader
,
6786 int shader_time_index
,
6789 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6790 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6792 brw_nir_lower_cs_intrinsics(shader
, prog_data
);
6793 shader
= brw_postprocess_nir(shader
, compiler
, true);
6795 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6796 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6797 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6798 unsigned local_workgroup_size
=
6799 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6800 shader
->info
.cs
.local_size
[2];
6802 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6803 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6806 const char *fail_msg
= NULL
;
6808 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6810 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6811 NULL
, /* Never used in core profile */
6812 shader
, 8, shader_time_index
);
6813 if (simd_required
<= 8) {
6815 fail_msg
= v8
.fail_msg
;
6818 cs_set_simd_size(prog_data
, 8);
6819 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6820 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6824 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6825 NULL
, /* Never used in core profile */
6826 shader
, 16, shader_time_index
);
6827 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6828 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6829 simd_required
<= 16) {
6830 /* Try a SIMD16 compile */
6831 if (simd_required
<= 8)
6832 v16
.import_uniforms(&v8
);
6833 if (!v16
.run_cs()) {
6834 compiler
->shader_perf_log(log_data
,
6835 "SIMD16 shader failed to compile: %s",
6839 "Couldn't generate SIMD16 program and not "
6840 "enough threads for SIMD8";
6844 cs_set_simd_size(prog_data
, 16);
6845 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6846 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6850 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6851 NULL
, /* Never used in core profile */
6852 shader
, 32, shader_time_index
);
6853 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6854 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6855 /* Try a SIMD32 compile */
6856 if (simd_required
<= 8)
6857 v32
.import_uniforms(&v8
);
6858 else if (simd_required
<= 16)
6859 v32
.import_uniforms(&v16
);
6861 if (!v32
.run_cs()) {
6862 compiler
->shader_perf_log(log_data
,
6863 "SIMD32 shader failed to compile: %s",
6867 "Couldn't generate SIMD32 program and not "
6868 "enough threads for SIMD16";
6872 cs_set_simd_size(prog_data
, 32);
6873 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6877 if (unlikely(cfg
== NULL
)) {
6880 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6885 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6886 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6887 MESA_SHADER_COMPUTE
);
6888 if (INTEL_DEBUG
& DEBUG_CS
) {
6889 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6890 shader
->info
.label
? shader
->info
.label
:
6893 g
.enable_debug(name
);
6896 g
.generate_code(cfg
, prog_data
->simd_size
);
6898 return g
.get_assembly(&prog_data
->base
.program_size
);
6902 * Test the dispatch mask packing assumptions of
6903 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
6904 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
6905 * executed with an unexpected dispatch mask.
6908 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
6910 const gl_shader_stage stage
= bld
.shader
->stage
;
6912 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
6913 bld
.shader
->stage_prog_data
)) {
6914 const fs_builder ubld
= bld
.exec_all().group(1, 0);
6915 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
6916 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
6919 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
6920 ubld
.AND(tmp
, mask
, tmp
);
6922 /* This will loop forever if the dispatch mask doesn't have the expected
6923 * form '2^n-1', in which case tmp will be non-zero.
6925 bld
.emit(BRW_OPCODE_DO
);
6926 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
6927 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));