2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "common/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
45 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
49 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
50 const fs_reg
*src
, unsigned sources
)
52 memset(this, 0, sizeof(*this));
54 this->src
= new fs_reg
[MAX2(sources
, 3)];
55 for (unsigned i
= 0; i
< sources
; i
++)
56 this->src
[i
] = src
[i
];
58 this->opcode
= opcode
;
60 this->sources
= sources
;
61 this->exec_size
= exec_size
;
64 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
66 assert(this->exec_size
!= 0);
68 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
70 /* This will be the case for almost all instructions. */
77 this->size_written
= dst
.component_size(exec_size
);
80 this->size_written
= 0;
84 unreachable("Invalid destination register file");
87 this->writes_accumulator
= false;
92 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
95 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
97 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
100 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
102 init(opcode
, exec_size
, dst
, NULL
, 0);
105 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
108 const fs_reg src
[1] = { src0
};
109 init(opcode
, exec_size
, dst
, src
, 1);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
113 const fs_reg
&src0
, const fs_reg
&src1
)
115 const fs_reg src
[2] = { src0
, src1
};
116 init(opcode
, exec_size
, dst
, src
, 2);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
122 const fs_reg src
[3] = { src0
, src1
, src2
};
123 init(opcode
, exec_size
, dst
, src
, 3);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
127 const fs_reg src
[], unsigned sources
)
129 init(opcode
, exec_width
, dst
, src
, sources
);
132 fs_inst::fs_inst(const fs_inst
&that
)
134 memcpy(this, &that
, sizeof(that
));
136 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
138 for (unsigned i
= 0; i
< that
.sources
; i
++)
139 this->src
[i
] = that
.src
[i
];
148 fs_inst::resize_sources(uint8_t num_sources
)
150 if (this->sources
!= num_sources
) {
151 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
153 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
154 src
[i
] = this->src
[i
];
158 this->sources
= num_sources
;
163 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
165 const fs_reg
&surf_index
,
166 const fs_reg
&varying_offset
,
167 uint32_t const_offset
)
169 /* We have our constant surface use a pitch of 4 bytes, so our index can
170 * be any component of a vector, and then we load 4 contiguous
171 * components starting from that.
173 * We break down the const_offset to a portion added to the variable offset
174 * and a portion done using fs_reg::offset, which means that if you have
175 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
176 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
177 * later notice that those loads are all the same and eliminate the
180 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
181 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
183 /* The pull load message will load a vec4 (16 bytes). If we are loading
184 * a double this means we are only loading 2 elements worth of data.
185 * We also want to use a 32-bit data type for the dst of the load operation
186 * so other parts of the driver don't get confused about the size of the
189 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
190 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
191 vec4_result
, surf_index
, vec4_offset
);
192 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
194 fs_reg dw
= offset(vec4_result
, bld
, (const_offset
& 0xf) / 4);
195 switch (type_sz(dst
.type
)) {
197 shuffle_32bit_load_result_to_16bit_data(bld
, dst
, dw
, 0, 1);
198 bld
.MOV(dst
, subscript(dw
, dst
.type
, (const_offset
/ 2) & 1));
201 bld
.MOV(dst
, retype(dw
, dst
.type
));
204 shuffle_32bit_load_result_to_64bit_data(bld
, dst
, dw
, 1);
207 unreachable("Unsupported bit_size");
212 * A helper for MOV generation for fixing up broken hardware SEND dependency
216 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
218 /* The caller always wants uncompressed to emit the minimal extra
219 * dependencies, and to avoid having to deal with aligning its regs to 2.
221 const fs_builder ubld
= bld
.annotate("send dependency resolve")
224 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
228 fs_inst::equals(fs_inst
*inst
) const
230 return (opcode
== inst
->opcode
&&
231 dst
.equals(inst
->dst
) &&
232 src
[0].equals(inst
->src
[0]) &&
233 src
[1].equals(inst
->src
[1]) &&
234 src
[2].equals(inst
->src
[2]) &&
235 saturate
== inst
->saturate
&&
236 predicate
== inst
->predicate
&&
237 conditional_mod
== inst
->conditional_mod
&&
238 mlen
== inst
->mlen
&&
239 base_mrf
== inst
->base_mrf
&&
240 target
== inst
->target
&&
242 header_size
== inst
->header_size
&&
243 shadow_compare
== inst
->shadow_compare
&&
244 exec_size
== inst
->exec_size
&&
245 offset
== inst
->offset
);
249 fs_inst::is_send_from_grf() const
252 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
253 case SHADER_OPCODE_SHADER_TIME_ADD
:
254 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
255 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
256 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
257 case SHADER_OPCODE_UNTYPED_ATOMIC
:
258 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
259 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
260 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
261 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
262 case SHADER_OPCODE_TYPED_ATOMIC
:
263 case SHADER_OPCODE_TYPED_SURFACE_READ
:
264 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
265 case SHADER_OPCODE_URB_WRITE_SIMD8
:
266 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
267 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
268 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
269 case SHADER_OPCODE_URB_READ_SIMD8
:
270 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
272 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
273 return src
[1].file
== VGRF
;
274 case FS_OPCODE_FB_WRITE
:
275 case FS_OPCODE_FB_READ
:
276 return src
[0].file
== VGRF
;
279 return src
[0].file
== VGRF
;
286 * Returns true if this instruction's sources and destinations cannot
287 * safely be the same register.
289 * In most cases, a register can be written over safely by the same
290 * instruction that is its last use. For a single instruction, the
291 * sources are dereferenced before writing of the destination starts
294 * However, there are a few cases where this can be problematic:
296 * - Virtual opcodes that translate to multiple instructions in the
297 * code generator: if src == dst and one instruction writes the
298 * destination before a later instruction reads the source, then
299 * src will have been clobbered.
301 * - SIMD16 compressed instructions with certain regioning (see below).
303 * The register allocator uses this information to set up conflicts between
304 * GRF sources and the destination.
307 fs_inst::has_source_and_destination_hazard() const
310 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
311 /* Multiple partial writes to the destination */
313 case SHADER_OPCODE_SHUFFLE
:
314 /* This instruction returns an arbitrary channel from the source and
315 * gets split into smaller instructions in the generator. It's possible
316 * that one of the instructions will read from a channel corresponding
317 * to an earlier instruction.
319 case SHADER_OPCODE_SEL_EXEC
:
320 /* This is implemented as
322 * mov(16) g4<1>D 0D { align1 WE_all 1H };
323 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
325 * Because the source is only read in the second instruction, the first
326 * may stomp all over it.
330 /* The SIMD16 compressed instruction
332 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
334 * is actually decoded in hardware as:
336 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
337 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
339 * Which is safe. However, if we have uniform accesses
340 * happening, we get into trouble:
342 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
343 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
345 * Now our destination for the first instruction overwrote the
346 * second instruction's src0, and we get garbage for those 8
347 * pixels. There's a similar issue for the pre-gen6
348 * pixel_x/pixel_y, which are registers of 16-bit values and thus
349 * would get stomped by the first decode as well.
351 if (exec_size
== 16) {
352 for (int i
= 0; i
< sources
; i
++) {
353 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
354 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
355 src
[i
].type
== BRW_REGISTER_TYPE_W
||
356 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
357 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
367 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
369 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
372 fs_reg reg
= this->src
[0];
373 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
376 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
379 for (int i
= 0; i
< this->sources
; i
++) {
380 reg
.type
= this->src
[i
].type
;
381 if (!this->src
[i
].equals(reg
))
384 if (i
< this->header_size
) {
385 reg
.offset
+= REG_SIZE
;
387 reg
= horiz_offset(reg
, this->exec_size
);
395 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
397 if (devinfo
->gen
== 6 && is_math())
400 if (is_send_from_grf())
403 if (!backend_instruction::can_do_source_mods())
410 fs_inst::can_change_types() const
412 return dst
.type
== src
[0].type
&&
413 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
414 (opcode
== BRW_OPCODE_MOV
||
415 (opcode
== BRW_OPCODE_SEL
&&
416 dst
.type
== src
[1].type
&&
417 predicate
!= BRW_PREDICATE_NONE
&&
418 !src
[1].abs
&& !src
[1].negate
));
424 memset(this, 0, sizeof(*this));
425 type
= BRW_REGISTER_TYPE_UD
;
429 /** Generic unset register constructor. */
433 this->file
= BAD_FILE
;
436 fs_reg::fs_reg(struct ::brw_reg reg
) :
441 if (this->file
== IMM
&&
442 (this->type
!= BRW_REGISTER_TYPE_V
&&
443 this->type
!= BRW_REGISTER_TYPE_UV
&&
444 this->type
!= BRW_REGISTER_TYPE_VF
)) {
450 fs_reg::equals(const fs_reg
&r
) const
452 return (this->backend_reg::equals(r
) &&
457 fs_reg::is_contiguous() const
463 fs_reg::component_size(unsigned width
) const
465 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
468 return MAX2(width
* stride
, 1) * type_sz(type
);
472 type_size_scalar(const struct glsl_type
*type
)
474 unsigned int size
, i
;
476 switch (type
->base_type
) {
479 case GLSL_TYPE_FLOAT
:
481 return type
->components();
482 case GLSL_TYPE_UINT16
:
483 case GLSL_TYPE_INT16
:
484 case GLSL_TYPE_FLOAT16
:
485 return DIV_ROUND_UP(type
->components(), 2);
486 case GLSL_TYPE_DOUBLE
:
487 case GLSL_TYPE_UINT64
:
488 case GLSL_TYPE_INT64
:
489 return type
->components() * 2;
490 case GLSL_TYPE_ARRAY
:
491 return type_size_scalar(type
->fields
.array
) * type
->length
;
492 case GLSL_TYPE_STRUCT
:
494 for (i
= 0; i
< type
->length
; i
++) {
495 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
498 case GLSL_TYPE_SAMPLER
:
499 /* Samplers take up no register space, since they're baked in at
503 case GLSL_TYPE_ATOMIC_UINT
:
505 case GLSL_TYPE_SUBROUTINE
:
507 case GLSL_TYPE_IMAGE
:
508 return BRW_IMAGE_PARAM_SIZE
;
510 case GLSL_TYPE_ERROR
:
511 case GLSL_TYPE_INTERFACE
:
512 case GLSL_TYPE_FUNCTION
:
513 unreachable("not reached");
520 * Create a MOV to read the timestamp register.
522 * The caller is responsible for emitting the MOV. The return value is
523 * the destination of the MOV, with extra parameters set.
526 fs_visitor::get_timestamp(const fs_builder
&bld
)
528 assert(devinfo
->gen
>= 7);
530 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
533 BRW_REGISTER_TYPE_UD
));
535 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
537 /* We want to read the 3 fields we care about even if it's not enabled in
540 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
546 fs_visitor::emit_shader_time_begin()
548 /* We want only the low 32 bits of the timestamp. Since it's running
549 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
550 * which is plenty of time for our purposes. It is identical across the
551 * EUs, but since it's tracking GPU core speed it will increment at a
552 * varying rate as render P-states change.
554 shader_start_time
= component(
555 get_timestamp(bld
.annotate("shader time start")), 0);
559 fs_visitor::emit_shader_time_end()
561 /* Insert our code just before the final SEND with EOT. */
562 exec_node
*end
= this->instructions
.get_tail();
563 assert(end
&& ((fs_inst
*) end
)->eot
);
564 const fs_builder ibld
= bld
.annotate("shader time end")
565 .exec_all().at(NULL
, end
);
566 const fs_reg timestamp
= get_timestamp(ibld
);
568 /* We only use the low 32 bits of the timestamp - see
569 * emit_shader_time_begin()).
571 * We could also check if render P-states have changed (or anything
572 * else that might disrupt timing) by setting smear to 2 and checking if
573 * that field is != 0.
575 const fs_reg shader_end_time
= component(timestamp
, 0);
577 /* Check that there weren't any timestamp reset events (assuming these
578 * were the only two timestamp reads that happened).
580 const fs_reg reset
= component(timestamp
, 2);
581 set_condmod(BRW_CONDITIONAL_Z
,
582 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
583 ibld
.IF(BRW_PREDICATE_NORMAL
);
585 fs_reg start
= shader_start_time
;
587 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
588 BRW_REGISTER_TYPE_UD
),
590 const fs_builder cbld
= ibld
.group(1, 0);
591 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
593 /* If there were no instructions between the two timestamp gets, the diff
594 * is 2 cycles. Remove that overhead, so I can forget about that when
595 * trying to determine the time taken for single instructions.
597 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
598 SHADER_TIME_ADD(cbld
, 0, diff
);
599 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
600 ibld
.emit(BRW_OPCODE_ELSE
);
601 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
602 ibld
.emit(BRW_OPCODE_ENDIF
);
606 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
607 int shader_time_subindex
,
610 int index
= shader_time_index
* 3 + shader_time_subindex
;
611 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
614 if (dispatch_width
== 8)
615 payload
= vgrf(glsl_type::uvec2_type
);
617 payload
= vgrf(glsl_type::uint_type
);
619 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
623 fs_visitor::vfail(const char *format
, va_list va
)
632 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
633 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
635 this->fail_msg
= msg
;
638 fprintf(stderr
, "%s", msg
);
643 fs_visitor::fail(const char *format
, ...)
647 va_start(va
, format
);
653 * Mark this program as impossible to compile with dispatch width greater
656 * During the SIMD8 compile (which happens first), we can detect and flag
657 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
658 * SIMD16+ compile altogether.
660 * During a compile of dispatch width greater than n (if one happens anyway),
661 * this just calls fail().
664 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
666 if (dispatch_width
> n
) {
669 max_dispatch_width
= n
;
670 compiler
->shader_perf_log(log_data
,
671 "Shader dispatch width limited to SIMD%d: %s",
677 * Returns true if the instruction has a flag that means it won't
678 * update an entire destination register.
680 * For example, dead code elimination and live variable analysis want to know
681 * when a write to a variable screens off any preceding values that were in
685 fs_inst::is_partial_write() const
687 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
688 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
689 !this->dst
.is_contiguous() ||
690 this->dst
.offset
% REG_SIZE
!= 0);
694 fs_inst::components_read(unsigned i
) const
696 /* Return zero if the source is not present. */
697 if (src
[i
].file
== BAD_FILE
)
701 case FS_OPCODE_LINTERP
:
707 case FS_OPCODE_PIXEL_X
:
708 case FS_OPCODE_PIXEL_Y
:
712 case FS_OPCODE_FB_WRITE_LOGICAL
:
713 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
714 /* First/second FB write color. */
716 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
720 case SHADER_OPCODE_TEX_LOGICAL
:
721 case SHADER_OPCODE_TXD_LOGICAL
:
722 case SHADER_OPCODE_TXF_LOGICAL
:
723 case SHADER_OPCODE_TXL_LOGICAL
:
724 case SHADER_OPCODE_TXS_LOGICAL
:
725 case FS_OPCODE_TXB_LOGICAL
:
726 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
727 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
728 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
729 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
730 case SHADER_OPCODE_LOD_LOGICAL
:
731 case SHADER_OPCODE_TG4_LOGICAL
:
732 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
733 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
734 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
735 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
736 /* Texture coordinates. */
737 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
738 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
739 /* Texture derivatives. */
740 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
741 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
742 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
743 /* Texture offset. */
744 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
747 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
752 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
753 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
754 assert(src
[3].file
== IMM
);
755 /* Surface coordinates. */
758 /* Surface operation source (ignored for reads). */
764 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
765 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
766 assert(src
[3].file
== IMM
&&
768 /* Surface coordinates. */
771 /* Surface operation source. */
777 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
778 /* Scattered logical opcodes use the following params:
779 * src[0] Surface coordinates
780 * src[1] Surface operation source (ignored for reads)
782 * src[3] IMM with always 1 dimension.
783 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
785 assert(src
[3].file
== IMM
&&
787 return i
== 1 ? 0 : 1;
789 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
790 assert(src
[3].file
== IMM
&&
794 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
795 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
796 assert(src
[3].file
== IMM
&&
798 const unsigned op
= src
[4].ud
;
799 /* Surface coordinates. */
802 /* Surface operation source. */
803 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
805 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
806 op
== BRW_AOP_PREDEC
))
818 fs_inst::size_read(int arg
) const
821 case FS_OPCODE_FB_WRITE
:
822 case FS_OPCODE_FB_READ
:
823 case SHADER_OPCODE_URB_WRITE_SIMD8
:
824 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
825 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
826 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
827 case SHADER_OPCODE_URB_READ_SIMD8
:
828 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
829 case SHADER_OPCODE_UNTYPED_ATOMIC
:
830 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
831 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
832 case SHADER_OPCODE_TYPED_ATOMIC
:
833 case SHADER_OPCODE_TYPED_SURFACE_READ
:
834 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
835 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
836 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
837 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
839 return mlen
* REG_SIZE
;
842 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
843 /* The payload is actually stored in src1 */
845 return mlen
* REG_SIZE
;
848 case FS_OPCODE_LINTERP
:
853 case SHADER_OPCODE_LOAD_PAYLOAD
:
854 if (arg
< this->header_size
)
858 case CS_OPCODE_CS_TERMINATE
:
859 case SHADER_OPCODE_BARRIER
:
862 case SHADER_OPCODE_MOV_INDIRECT
:
864 assert(src
[2].file
== IMM
);
870 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
871 return mlen
* REG_SIZE
;
875 switch (src
[arg
].file
) {
878 return components_read(arg
) * type_sz(src
[arg
].type
);
884 return components_read(arg
) * src
[arg
].component_size(exec_size
);
886 unreachable("MRF registers are not allowed as sources");
892 /* Return the subset of flag registers that an instruction could
893 * potentially read or write based on the execution controls and flag
894 * subregister number of the instruction.
897 flag_mask(const fs_inst
*inst
)
899 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
900 const unsigned end
= start
+ inst
->exec_size
;
901 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
907 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
911 flag_mask(const fs_reg
&r
, unsigned sz
)
914 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
915 const unsigned end
= start
+ sz
;
916 return bit_mask(end
) & ~bit_mask(start
);
924 fs_inst::flags_read(const gen_device_info
*devinfo
) const
926 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
927 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
928 /* The vertical predication modes combine corresponding bits from
929 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
931 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
932 return flag_mask(this) << shift
| flag_mask(this);
933 } else if (predicate
) {
934 return flag_mask(this);
937 for (int i
= 0; i
< sources
; i
++) {
938 mask
|= flag_mask(src
[i
], size_read(i
));
945 fs_inst::flags_written() const
947 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
948 opcode
!= BRW_OPCODE_CSEL
&&
949 opcode
!= BRW_OPCODE_IF
&&
950 opcode
!= BRW_OPCODE_WHILE
)) ||
951 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
||
952 opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
) {
953 return flag_mask(this);
955 return flag_mask(dst
, size_written
);
960 * Returns how many MRFs an FS opcode will write over.
962 * Note that this is not the 0 or 1 implied writes in an actual gen
963 * instruction -- the FS opcodes often generate MOVs in addition.
966 fs_visitor::implied_mrf_writes(fs_inst
*inst
) const
971 if (inst
->base_mrf
== -1)
974 switch (inst
->opcode
) {
975 case SHADER_OPCODE_RCP
:
976 case SHADER_OPCODE_RSQ
:
977 case SHADER_OPCODE_SQRT
:
978 case SHADER_OPCODE_EXP2
:
979 case SHADER_OPCODE_LOG2
:
980 case SHADER_OPCODE_SIN
:
981 case SHADER_OPCODE_COS
:
982 return 1 * dispatch_width
/ 8;
983 case SHADER_OPCODE_POW
:
984 case SHADER_OPCODE_INT_QUOTIENT
:
985 case SHADER_OPCODE_INT_REMAINDER
:
986 return 2 * dispatch_width
/ 8;
987 case SHADER_OPCODE_TEX
:
989 case SHADER_OPCODE_TXD
:
990 case SHADER_OPCODE_TXF
:
991 case SHADER_OPCODE_TXF_CMS
:
992 case SHADER_OPCODE_TXF_MCS
:
993 case SHADER_OPCODE_TG4
:
994 case SHADER_OPCODE_TG4_OFFSET
:
995 case SHADER_OPCODE_TXL
:
996 case SHADER_OPCODE_TXS
:
997 case SHADER_OPCODE_LOD
:
998 case SHADER_OPCODE_SAMPLEINFO
:
1000 case FS_OPCODE_FB_WRITE
:
1002 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1003 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1005 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1007 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1010 unreachable("not reached");
1015 fs_visitor::vgrf(const glsl_type
*const type
)
1017 int reg_width
= dispatch_width
/ 8;
1018 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1019 brw_type_for_base_type(type
));
1022 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1027 this->type
= BRW_REGISTER_TYPE_F
;
1028 this->stride
= (file
== UNIFORM
? 0 : 1);
1031 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1037 this->stride
= (file
== UNIFORM
? 0 : 1);
1040 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1041 * This brings in those uniform definitions
1044 fs_visitor::import_uniforms(fs_visitor
*v
)
1046 this->push_constant_loc
= v
->push_constant_loc
;
1047 this->pull_constant_loc
= v
->pull_constant_loc
;
1048 this->uniforms
= v
->uniforms
;
1049 this->subgroup_id
= v
->subgroup_id
;
1053 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1055 assert(stage
== MESA_SHADER_FRAGMENT
);
1057 /* gl_FragCoord.x */
1058 bld
.MOV(wpos
, this->pixel_x
);
1059 wpos
= offset(wpos
, bld
, 1);
1061 /* gl_FragCoord.y */
1062 bld
.MOV(wpos
, this->pixel_y
);
1063 wpos
= offset(wpos
, bld
, 1);
1065 /* gl_FragCoord.z */
1066 if (devinfo
->gen
>= 6) {
1067 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1069 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1070 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1071 interp_reg(VARYING_SLOT_POS
, 2));
1073 wpos
= offset(wpos
, bld
, 1);
1075 /* gl_FragCoord.w: Already set up in emit_interpolation */
1076 bld
.MOV(wpos
, this->wpos_w
);
1079 enum brw_barycentric_mode
1080 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1082 /* Barycentric modes don't make sense for flat inputs. */
1083 assert(mode
!= INTERP_MODE_FLAT
);
1087 case nir_intrinsic_load_barycentric_pixel
:
1088 case nir_intrinsic_load_barycentric_at_offset
:
1089 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1091 case nir_intrinsic_load_barycentric_centroid
:
1092 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1094 case nir_intrinsic_load_barycentric_sample
:
1095 case nir_intrinsic_load_barycentric_at_sample
:
1096 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1099 unreachable("invalid intrinsic");
1102 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1105 return (enum brw_barycentric_mode
) bary
;
1109 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1111 static enum brw_barycentric_mode
1112 centroid_to_pixel(enum brw_barycentric_mode bary
)
1114 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1115 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1116 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1120 fs_visitor::emit_frontfacing_interpolation()
1122 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1124 if (devinfo
->gen
>= 6) {
1125 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1126 * a boolean result from this (~0/true or 0/false).
1128 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1129 * this task in only one instruction:
1130 * - a negation source modifier will flip the bit; and
1131 * - a W -> D type conversion will sign extend the bit into the high
1132 * word of the destination.
1134 * An ASR 15 fills the low word of the destination.
1136 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1139 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1141 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1142 * a boolean result from this (1/true or 0/false).
1144 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1145 * the negation source modifier to flip it. Unfortunately the SHR
1146 * instruction only operates on UD (or D with an abs source modifier)
1147 * sources without negation.
1149 * Instead, use ASR (which will give ~0/true or 0/false).
1151 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1154 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1161 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1163 assert(stage
== MESA_SHADER_FRAGMENT
);
1164 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1165 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1167 if (wm_prog_data
->persample_dispatch
) {
1168 /* Convert int_sample_pos to floating point */
1169 bld
.MOV(dst
, int_sample_pos
);
1170 /* Scale to the range [0, 1] */
1171 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1174 /* From ARB_sample_shading specification:
1175 * "When rendering to a non-multisample buffer, or if multisample
1176 * rasterization is disabled, gl_SamplePosition will always be
1179 bld
.MOV(dst
, brw_imm_f(0.5f
));
1184 fs_visitor::emit_samplepos_setup()
1186 assert(devinfo
->gen
>= 6);
1188 const fs_builder abld
= bld
.annotate("compute sample position");
1189 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1191 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1192 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1194 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1195 * mode will be enabled.
1197 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1198 * R31.1:0 Position Offset X/Y for Slot[3:0]
1199 * R31.3:2 Position Offset X/Y for Slot[7:4]
1202 * The X, Y sample positions come in as bytes in thread payload. So, read
1203 * the positions using vstride=16, width=8, hstride=2.
1205 struct brw_reg sample_pos_reg
=
1206 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1207 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1209 if (dispatch_width
== 8) {
1210 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1212 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1213 abld
.half(1).MOV(half(int_sample_x
, 1),
1214 fs_reg(suboffset(sample_pos_reg
, 16)));
1216 /* Compute gl_SamplePosition.x */
1217 compute_sample_position(pos
, int_sample_x
);
1218 pos
= offset(pos
, abld
, 1);
1219 if (dispatch_width
== 8) {
1220 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1222 abld
.half(0).MOV(half(int_sample_y
, 0),
1223 fs_reg(suboffset(sample_pos_reg
, 1)));
1224 abld
.half(1).MOV(half(int_sample_y
, 1),
1225 fs_reg(suboffset(sample_pos_reg
, 17)));
1227 /* Compute gl_SamplePosition.y */
1228 compute_sample_position(pos
, int_sample_y
);
1233 fs_visitor::emit_sampleid_setup()
1235 assert(stage
== MESA_SHADER_FRAGMENT
);
1236 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1237 assert(devinfo
->gen
>= 6);
1239 const fs_builder abld
= bld
.annotate("compute sample id");
1240 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1242 if (!key
->multisample_fbo
) {
1243 /* As per GL_ARB_sample_shading specification:
1244 * "When rendering to a non-multisample buffer, or if multisample
1245 * rasterization is disabled, gl_SampleID will always be zero."
1247 abld
.MOV(*reg
, brw_imm_d(0));
1248 } else if (devinfo
->gen
>= 8) {
1249 /* Sample ID comes in as 4-bit numbers in g1.0:
1251 * 15:12 Slot 3 SampleID (only used in SIMD16)
1252 * 11:8 Slot 2 SampleID (only used in SIMD16)
1253 * 7:4 Slot 1 SampleID
1254 * 3:0 Slot 0 SampleID
1256 * Each slot corresponds to four channels, so we want to replicate each
1257 * half-byte value to 4 channels in a row:
1259 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1260 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1262 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1263 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1265 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1266 * channels to read the first byte (7:0), and the second group of 8
1267 * channels to read the second byte (15:8). Then, we shift right by
1268 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1269 * values into place. Finally, we AND with 0xf to keep the low nibble.
1271 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1272 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1274 * TODO: These payload bits exist on Gen7 too, but they appear to always
1275 * be zero, so this code fails to work. We should find out why.
1277 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UW
);
1279 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1280 BRW_REGISTER_TYPE_UB
), 1, 8, 0)),
1281 brw_imm_v(0x44440000));
1282 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1284 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1285 BRW_REGISTER_TYPE_UD
), 0);
1286 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UW
);
1288 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1289 * 8x multisampling, subspan 0 will represent sample N (where N
1290 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1291 * 7. We can find the value of N by looking at R0.0 bits 7:6
1292 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1293 * (since samples are always delivered in pairs). That is, we
1294 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1295 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1296 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1297 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1298 * populating a temporary variable with the sequence (0, 1, 2, 3),
1299 * and then reading from it using vstride=1, width=4, hstride=0.
1300 * These computations hold good for 4x multisampling as well.
1302 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1303 * the first four slots are sample 0 of subspan 0; the next four
1304 * are sample 1 of subspan 0; the third group is sample 0 of
1305 * subspan 1, and finally sample 1 of subspan 1.
1308 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1309 * accomodate 16x MSAA.
1311 abld
.exec_all().group(1, 0)
1312 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1314 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1316 /* This works for both SIMD8 and SIMD16 */
1317 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1319 /* This special instruction takes care of setting vstride=1,
1320 * width=4, hstride=0 of t2 during an ADD instruction.
1322 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1329 fs_visitor::emit_samplemaskin_setup()
1331 assert(stage
== MESA_SHADER_FRAGMENT
);
1332 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1333 assert(devinfo
->gen
>= 6);
1335 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1337 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1338 BRW_REGISTER_TYPE_D
));
1340 if (wm_prog_data
->persample_dispatch
) {
1341 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1342 * and a mask representing which sample is being processed by the
1343 * current shader invocation.
1345 * From the OES_sample_variables specification:
1346 * "When per-sample shading is active due to the use of a fragment input
1347 * qualified by "sample" or due to the use of the gl_SampleID or
1348 * gl_SamplePosition variables, only the bit for the current sample is
1349 * set in gl_SampleMaskIn."
1351 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1353 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1354 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1356 fs_reg one
= vgrf(glsl_type::int_type
);
1357 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1358 abld
.MOV(one
, brw_imm_d(1));
1359 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1360 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1362 /* In per-pixel mode, the coverage mask is sufficient. */
1363 *reg
= coverage_mask
;
1369 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1371 if (!src
.abs
&& !src
.negate
)
1374 fs_reg temp
= bld
.vgrf(src
.type
);
1381 fs_visitor::emit_discard_jump()
1383 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1385 /* For performance, after a discard, jump to the end of the
1386 * shader if all relevant channels have been discarded.
1388 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1389 discard_jump
->flag_subreg
= 1;
1391 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1392 discard_jump
->predicate_inverse
= true;
1396 fs_visitor::emit_gs_thread_end()
1398 assert(stage
== MESA_SHADER_GEOMETRY
);
1400 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1402 if (gs_compile
->control_data_header_size_bits
> 0) {
1403 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1406 const fs_builder abld
= bld
.annotate("thread end");
1409 if (gs_prog_data
->static_vertex_count
!= -1) {
1410 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1411 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1412 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1413 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1414 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1417 /* Delete now dead instructions. */
1418 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1424 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1428 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1429 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1430 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1433 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1434 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1435 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1436 sources
[1] = this->final_gs_vertex_count
;
1437 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1438 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1446 fs_visitor::assign_curb_setup()
1448 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1450 unsigned ubo_push_length
= 0;
1451 unsigned ubo_push_start
[4];
1452 for (int i
= 0; i
< 4; i
++) {
1453 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1454 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1457 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1459 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1460 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1461 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1462 if (inst
->src
[i
].file
== UNIFORM
) {
1463 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1465 if (inst
->src
[i
].nr
>= UBO_START
) {
1466 /* constant_nr is in 32-bit units, the rest are in bytes */
1467 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1468 inst
->src
[i
].offset
/ 4;
1469 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1470 constant_nr
= push_constant_loc
[uniform_nr
];
1472 /* Section 5.11 of the OpenGL 4.1 spec says:
1473 * "Out-of-bounds reads return undefined values, which include
1474 * values from other variables of the active program or zero."
1475 * Just return the first push constant.
1480 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1483 brw_reg
.abs
= inst
->src
[i
].abs
;
1484 brw_reg
.negate
= inst
->src
[i
].negate
;
1486 assert(inst
->src
[i
].stride
== 0);
1487 inst
->src
[i
] = byte_offset(
1488 retype(brw_reg
, inst
->src
[i
].type
),
1489 inst
->src
[i
].offset
% 4);
1494 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1495 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1499 fs_visitor::calculate_urb_setup()
1501 assert(stage
== MESA_SHADER_FRAGMENT
);
1502 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1503 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1505 memset(prog_data
->urb_setup
, -1,
1506 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1509 /* Figure out where each of the incoming setup attributes lands. */
1510 if (devinfo
->gen
>= 6) {
1511 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1512 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1513 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1514 * first 16 varying inputs, so we can put them wherever we want.
1515 * Just put them in order.
1517 * This is useful because it means that (a) inputs not used by the
1518 * fragment shader won't take up valuable register space, and (b) we
1519 * won't have to recompile the fragment shader if it gets paired with
1520 * a different vertex (or geometry) shader.
1522 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1523 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1524 BITFIELD64_BIT(i
)) {
1525 prog_data
->urb_setup
[i
] = urb_next
++;
1529 /* We have enough input varyings that the SF/SBE pipeline stage can't
1530 * arbitrarily rearrange them to suit our whim; we have to put them
1531 * in an order that matches the output of the previous pipeline stage
1532 * (geometry or vertex shader).
1534 struct brw_vue_map prev_stage_vue_map
;
1535 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1536 key
->input_slots_valid
,
1537 nir
->info
.separate_shader
);
1540 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1541 &prev_stage_vue_map
);
1543 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1544 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1546 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1547 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1548 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1549 BITFIELD64_BIT(varying
))) {
1550 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1553 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1556 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1557 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1558 /* Point size is packed into the header, not as a general attribute */
1559 if (i
== VARYING_SLOT_PSIZ
)
1562 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1563 /* The back color slot is skipped when the front color is
1564 * also written to. In addition, some slots can be
1565 * written in the vertex shader and not read in the
1566 * fragment shader. So the register number must always be
1567 * incremented, mapped or not.
1569 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1570 prog_data
->urb_setup
[i
] = urb_next
;
1576 * It's a FS only attribute, and we did interpolation for this attribute
1577 * in SF thread. So, count it here, too.
1579 * See compile_sf_prog() for more info.
1581 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1582 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1585 prog_data
->num_varying_inputs
= urb_next
;
1589 fs_visitor::assign_urb_setup()
1591 assert(stage
== MESA_SHADER_FRAGMENT
);
1592 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1594 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1596 /* Offset all the urb_setup[] index by the actual position of the
1597 * setup regs, now that the location of the constants has been chosen.
1599 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1600 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1601 assert(inst
->src
[1].file
== FIXED_GRF
);
1602 inst
->src
[1].nr
+= urb_start
;
1605 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1606 assert(inst
->src
[0].file
== FIXED_GRF
);
1607 inst
->src
[0].nr
+= urb_start
;
1611 /* Each attribute is 4 setup channels, each of which is half a reg. */
1612 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1616 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1618 for (int i
= 0; i
< inst
->sources
; i
++) {
1619 if (inst
->src
[i
].file
== ATTR
) {
1620 int grf
= payload
.num_regs
+
1621 prog_data
->curb_read_length
+
1623 inst
->src
[i
].offset
/ REG_SIZE
;
1625 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1627 * VertStride must be used to cross GRF register boundaries. This
1628 * rule implies that elements within a 'Width' cannot cross GRF
1631 * So, for registers that are large enough, we have to split the exec
1632 * size in two and trust the compression state to sort it out.
1634 unsigned total_size
= inst
->exec_size
*
1635 inst
->src
[i
].stride
*
1636 type_sz(inst
->src
[i
].type
);
1638 assert(total_size
<= 2 * REG_SIZE
);
1639 const unsigned exec_size
=
1640 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1642 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1643 struct brw_reg reg
=
1644 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1645 inst
->src
[i
].offset
% REG_SIZE
),
1646 exec_size
* inst
->src
[i
].stride
,
1647 width
, inst
->src
[i
].stride
);
1648 reg
.abs
= inst
->src
[i
].abs
;
1649 reg
.negate
= inst
->src
[i
].negate
;
1657 fs_visitor::assign_vs_urb_setup()
1659 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1661 assert(stage
== MESA_SHADER_VERTEX
);
1663 /* Each attribute is 4 regs. */
1664 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1666 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1668 /* Rewrite all ATTR file references to the hw grf that they land in. */
1669 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1670 convert_attr_sources_to_hw_regs(inst
);
1675 fs_visitor::assign_tcs_single_patch_urb_setup()
1677 assert(stage
== MESA_SHADER_TESS_CTRL
);
1679 /* Rewrite all ATTR file references to HW_REGs. */
1680 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1681 convert_attr_sources_to_hw_regs(inst
);
1686 fs_visitor::assign_tes_urb_setup()
1688 assert(stage
== MESA_SHADER_TESS_EVAL
);
1690 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1692 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1694 /* Rewrite all ATTR file references to HW_REGs. */
1695 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1696 convert_attr_sources_to_hw_regs(inst
);
1701 fs_visitor::assign_gs_urb_setup()
1703 assert(stage
== MESA_SHADER_GEOMETRY
);
1705 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1707 first_non_payload_grf
+=
1708 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1710 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1711 /* Rewrite all ATTR file references to GRFs. */
1712 convert_attr_sources_to_hw_regs(inst
);
1718 * Split large virtual GRFs into separate components if we can.
1720 * This is mostly duplicated with what brw_fs_vector_splitting does,
1721 * but that's really conservative because it's afraid of doing
1722 * splitting that doesn't result in real progress after the rest of
1723 * the optimization phases, which would cause infinite looping in
1724 * optimization. We can do it once here, safely. This also has the
1725 * opportunity to split interpolated values, or maybe even uniforms,
1726 * which we don't have at the IR level.
1728 * We want to split, because virtual GRFs are what we register
1729 * allocate and spill (due to contiguousness requirements for some
1730 * instructions), and they're what we naturally generate in the
1731 * codegen process, but most virtual GRFs don't actually need to be
1732 * contiguous sets of GRFs. If we split, we'll end up with reduced
1733 * live intervals and better dead code elimination and coalescing.
1736 fs_visitor::split_virtual_grfs()
1738 /* Compact the register file so we eliminate dead vgrfs. This
1739 * only defines split points for live registers, so if we have
1740 * too large dead registers they will hit assertions later.
1742 compact_virtual_grfs();
1744 int num_vars
= this->alloc
.count
;
1746 /* Count the total number of registers */
1748 int vgrf_to_reg
[num_vars
];
1749 for (int i
= 0; i
< num_vars
; i
++) {
1750 vgrf_to_reg
[i
] = reg_count
;
1751 reg_count
+= alloc
.sizes
[i
];
1754 /* An array of "split points". For each register slot, this indicates
1755 * if this slot can be separated from the previous slot. Every time an
1756 * instruction uses multiple elements of a register (as a source or
1757 * destination), we mark the used slots as inseparable. Then we go
1758 * through and split the registers into the smallest pieces we can.
1760 bool split_points
[reg_count
];
1761 memset(split_points
, 0, sizeof(split_points
));
1763 /* Mark all used registers as fully splittable */
1764 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1765 if (inst
->dst
.file
== VGRF
) {
1766 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1767 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1768 split_points
[reg
+ j
] = true;
1771 for (int i
= 0; i
< inst
->sources
; i
++) {
1772 if (inst
->src
[i
].file
== VGRF
) {
1773 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1774 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1775 split_points
[reg
+ j
] = true;
1780 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1781 if (inst
->dst
.file
== VGRF
) {
1782 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1783 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1784 split_points
[reg
+ j
] = false;
1786 for (int i
= 0; i
< inst
->sources
; i
++) {
1787 if (inst
->src
[i
].file
== VGRF
) {
1788 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1789 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1790 split_points
[reg
+ j
] = false;
1795 int new_virtual_grf
[reg_count
];
1796 int new_reg_offset
[reg_count
];
1799 for (int i
= 0; i
< num_vars
; i
++) {
1800 /* The first one should always be 0 as a quick sanity check. */
1801 assert(split_points
[reg
] == false);
1804 new_reg_offset
[reg
] = 0;
1809 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1810 /* If this is a split point, reset the offset to 0 and allocate a
1811 * new virtual GRF for the previous offset many registers
1813 if (split_points
[reg
]) {
1814 assert(offset
<= MAX_VGRF_SIZE
);
1815 int grf
= alloc
.allocate(offset
);
1816 for (int k
= reg
- offset
; k
< reg
; k
++)
1817 new_virtual_grf
[k
] = grf
;
1820 new_reg_offset
[reg
] = offset
;
1825 /* The last one gets the original register number */
1826 assert(offset
<= MAX_VGRF_SIZE
);
1827 alloc
.sizes
[i
] = offset
;
1828 for (int k
= reg
- offset
; k
< reg
; k
++)
1829 new_virtual_grf
[k
] = i
;
1831 assert(reg
== reg_count
);
1833 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1834 if (inst
->dst
.file
== VGRF
) {
1835 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1836 inst
->dst
.nr
= new_virtual_grf
[reg
];
1837 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1838 inst
->dst
.offset
% REG_SIZE
;
1839 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1841 for (int i
= 0; i
< inst
->sources
; i
++) {
1842 if (inst
->src
[i
].file
== VGRF
) {
1843 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1844 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1845 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1846 inst
->src
[i
].offset
% REG_SIZE
;
1847 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1851 invalidate_live_intervals();
1855 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1857 * During code generation, we create tons of temporary variables, many of
1858 * which get immediately killed and are never used again. Yet, in later
1859 * optimization and analysis passes, such as compute_live_intervals, we need
1860 * to loop over all the virtual GRFs. Compacting them can save a lot of
1864 fs_visitor::compact_virtual_grfs()
1866 bool progress
= false;
1867 int remap_table
[this->alloc
.count
];
1868 memset(remap_table
, -1, sizeof(remap_table
));
1870 /* Mark which virtual GRFs are used. */
1871 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1872 if (inst
->dst
.file
== VGRF
)
1873 remap_table
[inst
->dst
.nr
] = 0;
1875 for (int i
= 0; i
< inst
->sources
; i
++) {
1876 if (inst
->src
[i
].file
== VGRF
)
1877 remap_table
[inst
->src
[i
].nr
] = 0;
1881 /* Compact the GRF arrays. */
1883 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1884 if (remap_table
[i
] == -1) {
1885 /* We just found an unused register. This means that we are
1886 * actually going to compact something.
1890 remap_table
[i
] = new_index
;
1891 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1892 invalidate_live_intervals();
1897 this->alloc
.count
= new_index
;
1899 /* Patch all the instructions to use the newly renumbered registers */
1900 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1901 if (inst
->dst
.file
== VGRF
)
1902 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1904 for (int i
= 0; i
< inst
->sources
; i
++) {
1905 if (inst
->src
[i
].file
== VGRF
)
1906 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1910 /* Patch all the references to delta_xy, since they're used in register
1911 * allocation. If they're unused, switch them to BAD_FILE so we don't
1912 * think some random VGRF is delta_xy.
1914 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1915 if (delta_xy
[i
].file
== VGRF
) {
1916 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1917 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1919 delta_xy
[i
].file
= BAD_FILE
;
1928 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
1930 if (prog_data
->nr_params
== 0)
1933 /* The local thread id is always the last parameter in the list */
1934 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
1935 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
1936 return prog_data
->nr_params
- 1;
1942 * Struct for handling complex alignments.
1944 * A complex alignment is stored as multiplier and an offset. A value is
1945 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
1946 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
1949 * N | cplx_align_apply({8, 2}, N)
1950 * ----+-----------------------------
1964 #define CPLX_ALIGN_MAX_MUL 8
1967 cplx_align_assert_sane(struct cplx_align a
)
1969 assert(a
.mul
> 0 && util_is_power_of_two(a
.mul
));
1970 assert(a
.offset
< a
.mul
);
1974 * Combines two alignments to produce a least multiple of sorts.
1976 * The returned alignment is the smallest (in terms of multiplier) such that
1977 * anything aligned to both a and b will be aligned to the new alignment.
1978 * This function will assert-fail if a and b are not compatible, i.e. if the
1979 * offset parameters are such that no common alignment is possible.
1981 static struct cplx_align
1982 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
1984 cplx_align_assert_sane(a
);
1985 cplx_align_assert_sane(b
);
1987 /* Assert that the alignments agree. */
1988 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
1990 return a
.mul
> b
.mul
? a
: b
;
1994 * Apply a complex alignment
1996 * This function will return the smallest number greater than or equal to
1997 * offset that is aligned to align.
2000 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2002 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2005 #define UNIFORM_SLOT_SIZE 4
2007 struct uniform_slot_info
{
2008 /** True if the given uniform slot is live */
2011 /** True if this slot and the next slot must remain contiguous */
2012 unsigned contiguous
:1;
2014 struct cplx_align align
;
2018 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2019 unsigned num_slots
, unsigned alignment
)
2021 assert(alignment
> 0 && util_is_power_of_two(alignment
));
2022 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2024 /* We can't align a slot to anything less than the slot size */
2025 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2027 struct cplx_align align
= {alignment
, 0};
2028 cplx_align_assert_sane(align
);
2030 for (unsigned i
= 0; i
< num_slots
; i
++) {
2031 slots
[i
].is_live
= true;
2032 if (i
< num_slots
- 1)
2033 slots
[i
].contiguous
= true;
2035 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2036 if (slots
[i
].align
.mul
== 0) {
2037 slots
[i
].align
= align
;
2039 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2045 * Assign UNIFORM file registers to either push constants or pull constants.
2047 * We allow a fragment shader to have more than the specified minimum
2048 * maximum number of fragment shader uniform components (64). If
2049 * there are too many of these, they'd fill up all of register space.
2050 * So, this will push some of them out to the pull constant buffer and
2051 * update the program to load them.
2054 fs_visitor::assign_constant_locations()
2056 /* Only the first compile gets to decide on locations. */
2057 if (push_constant_loc
) {
2058 assert(pull_constant_loc
);
2062 struct uniform_slot_info slots
[uniforms
];
2063 memset(slots
, 0, sizeof(slots
));
2065 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2066 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2067 if (inst
->src
[i
].file
!= UNIFORM
)
2070 /* NIR tightly packs things so the uniform number might not be
2071 * aligned (if we have a double right after a float, for instance).
2072 * This is fine because the process of re-arranging them will ensure
2073 * that things are properly aligned. The offset into that uniform,
2074 * however, must be aligned.
2076 * In Vulkan, we have explicit offsets but everything is crammed
2077 * into a single "variable" so inst->src[i].nr will always be 0.
2078 * Everything will be properly aligned relative to that one base.
2080 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2082 unsigned u
= inst
->src
[i
].nr
+
2083 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2088 unsigned slots_read
;
2089 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2090 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2092 unsigned bytes_read
= inst
->components_read(i
) *
2093 type_sz(inst
->src
[i
].type
);
2094 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2097 assert(u
+ slots_read
<= uniforms
);
2098 mark_uniform_slots_read(&slots
[u
], slots_read
,
2099 type_sz(inst
->src
[i
].type
));
2103 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2105 /* Only allow 16 registers (128 uniform components) as push constants.
2107 * Just demote the end of the list. We could probably do better
2108 * here, demoting things that are rarely used in the program first.
2110 * If changing this value, note the limitation about total_regs in
2113 unsigned int max_push_components
= 16 * 8;
2114 if (subgroup_id_index
>= 0)
2115 max_push_components
--; /* Save a slot for the thread ID */
2117 /* We push small arrays, but no bigger than 16 floats. This is big enough
2118 * for a vec4 but hopefully not large enough to push out other stuff. We
2119 * should probably use a better heuristic at some point.
2121 const unsigned int max_chunk_size
= 16;
2123 unsigned int num_push_constants
= 0;
2124 unsigned int num_pull_constants
= 0;
2126 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2127 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2129 /* Default to -1 meaning no location */
2130 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2131 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2133 int chunk_start
= -1;
2134 struct cplx_align align
;
2135 for (unsigned u
= 0; u
< uniforms
; u
++) {
2136 if (!slots
[u
].is_live
) {
2137 assert(chunk_start
== -1);
2141 /* Skip subgroup_id_index to put it in the last push register. */
2142 if (subgroup_id_index
== (int)u
)
2145 if (chunk_start
== -1) {
2147 align
= slots
[u
].align
;
2149 /* Offset into the chunk */
2150 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2152 /* Shift the slot alignment down by the chunk offset so it is
2153 * comparable with the base chunk alignment.
2155 struct cplx_align slot_align
= slots
[u
].align
;
2157 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2159 align
= cplx_align_combine(align
, slot_align
);
2162 /* Sanity check the alignment */
2163 cplx_align_assert_sane(align
);
2165 if (slots
[u
].contiguous
)
2168 /* Adjust the alignment to be in terms of slots, not bytes */
2169 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2170 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2171 align
.mul
/= UNIFORM_SLOT_SIZE
;
2172 align
.offset
/= UNIFORM_SLOT_SIZE
;
2174 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2175 unsigned chunk_size
= u
- chunk_start
+ 1;
2176 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2177 (chunk_size
< max_chunk_size
&&
2178 push_start_align
+ chunk_size
<= max_push_components
)) {
2179 /* Align up the number of push constants */
2180 num_push_constants
= push_start_align
;
2181 for (unsigned i
= 0; i
< chunk_size
; i
++)
2182 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2184 /* We need to pull this one */
2185 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2186 for (unsigned i
= 0; i
< chunk_size
; i
++)
2187 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2190 /* Reset the chunk and start again */
2194 /* Add the CS local thread ID uniform at the end of the push constants */
2195 if (subgroup_id_index
>= 0)
2196 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2198 /* As the uniforms are going to be reordered, stash the old array and
2199 * create two new arrays for push/pull params.
2201 uint32_t *param
= stage_prog_data
->param
;
2202 stage_prog_data
->nr_params
= num_push_constants
;
2203 if (num_push_constants
) {
2204 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2205 num_push_constants
);
2207 stage_prog_data
->param
= NULL
;
2209 assert(stage_prog_data
->nr_pull_params
== 0);
2210 assert(stage_prog_data
->pull_param
== NULL
);
2211 if (num_pull_constants
> 0) {
2212 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2213 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2214 num_pull_constants
);
2217 /* Now that we know how many regular uniforms we'll push, reduce the
2218 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2220 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2221 for (int i
= 0; i
< 4; i
++) {
2222 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2224 if (push_length
+ range
->length
> 64)
2225 range
->length
= 64 - push_length
;
2227 push_length
+= range
->length
;
2229 assert(push_length
<= 64);
2231 /* Up until now, the param[] array has been indexed by reg + offset
2232 * of UNIFORM registers. Move pull constants into pull_param[] and
2233 * condense param[] to only contain the uniforms we chose to push.
2235 * NOTE: Because we are condensing the params[] array, we know that
2236 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2237 * having to make a copy.
2239 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2240 uint32_t value
= param
[i
];
2241 if (pull_constant_loc
[i
] != -1) {
2242 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2243 } else if (push_constant_loc
[i
] != -1) {
2244 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2251 fs_visitor::get_pull_locs(const fs_reg
&src
,
2252 unsigned *out_surf_index
,
2253 unsigned *out_pull_index
)
2255 assert(src
.file
== UNIFORM
);
2257 if (src
.nr
>= UBO_START
) {
2258 const struct brw_ubo_range
*range
=
2259 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2261 /* If this access is in our (reduced) range, use the push data. */
2262 if (src
.offset
/ 32 < range
->length
)
2265 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2266 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2270 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2272 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2273 /* A regular uniform push constant */
2274 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2275 *out_pull_index
= pull_constant_loc
[location
];
2283 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2284 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2287 fs_visitor::lower_constant_loads()
2289 unsigned index
, pull_index
;
2291 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2292 /* Set up the annotation tracking for new generated instructions. */
2293 const fs_builder
ibld(this, block
, inst
);
2295 for (int i
= 0; i
< inst
->sources
; i
++) {
2296 if (inst
->src
[i
].file
!= UNIFORM
)
2299 /* We'll handle this case later */
2300 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2303 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2306 assert(inst
->src
[i
].stride
== 0);
2308 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2309 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2310 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2311 const unsigned base
= pull_index
* 4;
2313 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2314 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2316 /* Rewrite the instruction to use the temporary VGRF. */
2317 inst
->src
[i
].file
= VGRF
;
2318 inst
->src
[i
].nr
= dst
.nr
;
2319 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2320 inst
->src
[i
].offset
% 4;
2322 brw_mark_surface_used(prog_data
, index
);
2325 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2326 inst
->src
[0].file
== UNIFORM
) {
2328 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2331 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2335 inst
->remove(block
);
2337 brw_mark_surface_used(prog_data
, index
);
2340 invalidate_live_intervals();
2344 fs_visitor::opt_algebraic()
2346 bool progress
= false;
2348 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2349 switch (inst
->opcode
) {
2350 case BRW_OPCODE_MOV
:
2351 if (inst
->src
[0].file
!= IMM
)
2354 if (inst
->saturate
) {
2355 if (inst
->dst
.type
!= inst
->src
[0].type
)
2356 assert(!"unimplemented: saturate mixed types");
2358 if (brw_saturate_immediate(inst
->dst
.type
,
2359 &inst
->src
[0].as_brw_reg())) {
2360 inst
->saturate
= false;
2366 case BRW_OPCODE_MUL
:
2367 if (inst
->src
[1].file
!= IMM
)
2371 if (inst
->src
[1].is_one()) {
2372 inst
->opcode
= BRW_OPCODE_MOV
;
2373 inst
->src
[1] = reg_undef
;
2379 if (inst
->src
[1].is_negative_one()) {
2380 inst
->opcode
= BRW_OPCODE_MOV
;
2381 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2382 inst
->src
[1] = reg_undef
;
2388 if (inst
->src
[1].is_zero()) {
2389 inst
->opcode
= BRW_OPCODE_MOV
;
2390 inst
->src
[0] = inst
->src
[1];
2391 inst
->src
[1] = reg_undef
;
2396 if (inst
->src
[0].file
== IMM
) {
2397 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2398 inst
->opcode
= BRW_OPCODE_MOV
;
2399 inst
->src
[0].f
*= inst
->src
[1].f
;
2400 inst
->src
[1] = reg_undef
;
2405 case BRW_OPCODE_ADD
:
2406 if (inst
->src
[1].file
!= IMM
)
2410 if (inst
->src
[1].is_zero()) {
2411 inst
->opcode
= BRW_OPCODE_MOV
;
2412 inst
->src
[1] = reg_undef
;
2417 if (inst
->src
[0].file
== IMM
) {
2418 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2419 inst
->opcode
= BRW_OPCODE_MOV
;
2420 inst
->src
[0].f
+= inst
->src
[1].f
;
2421 inst
->src
[1] = reg_undef
;
2427 if (inst
->src
[0].equals(inst
->src
[1])) {
2428 inst
->opcode
= BRW_OPCODE_MOV
;
2429 inst
->src
[1] = reg_undef
;
2434 case BRW_OPCODE_LRP
:
2435 if (inst
->src
[1].equals(inst
->src
[2])) {
2436 inst
->opcode
= BRW_OPCODE_MOV
;
2437 inst
->src
[0] = inst
->src
[1];
2438 inst
->src
[1] = reg_undef
;
2439 inst
->src
[2] = reg_undef
;
2444 case BRW_OPCODE_CMP
:
2445 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2447 inst
->src
[0].negate
&&
2448 inst
->src
[1].is_zero()) {
2449 inst
->src
[0].abs
= false;
2450 inst
->src
[0].negate
= false;
2451 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2456 case BRW_OPCODE_SEL
:
2457 if (inst
->src
[0].equals(inst
->src
[1])) {
2458 inst
->opcode
= BRW_OPCODE_MOV
;
2459 inst
->src
[1] = reg_undef
;
2460 inst
->predicate
= BRW_PREDICATE_NONE
;
2461 inst
->predicate_inverse
= false;
2463 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2464 switch (inst
->conditional_mod
) {
2465 case BRW_CONDITIONAL_LE
:
2466 case BRW_CONDITIONAL_L
:
2467 switch (inst
->src
[1].type
) {
2468 case BRW_REGISTER_TYPE_F
:
2469 if (inst
->src
[1].f
>= 1.0f
) {
2470 inst
->opcode
= BRW_OPCODE_MOV
;
2471 inst
->src
[1] = reg_undef
;
2472 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2480 case BRW_CONDITIONAL_GE
:
2481 case BRW_CONDITIONAL_G
:
2482 switch (inst
->src
[1].type
) {
2483 case BRW_REGISTER_TYPE_F
:
2484 if (inst
->src
[1].f
<= 0.0f
) {
2485 inst
->opcode
= BRW_OPCODE_MOV
;
2486 inst
->src
[1] = reg_undef
;
2487 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2499 case BRW_OPCODE_MAD
:
2500 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2501 inst
->opcode
= BRW_OPCODE_MOV
;
2502 inst
->src
[1] = reg_undef
;
2503 inst
->src
[2] = reg_undef
;
2505 } else if (inst
->src
[0].is_zero()) {
2506 inst
->opcode
= BRW_OPCODE_MUL
;
2507 inst
->src
[0] = inst
->src
[2];
2508 inst
->src
[2] = reg_undef
;
2510 } else if (inst
->src
[1].is_one()) {
2511 inst
->opcode
= BRW_OPCODE_ADD
;
2512 inst
->src
[1] = inst
->src
[2];
2513 inst
->src
[2] = reg_undef
;
2515 } else if (inst
->src
[2].is_one()) {
2516 inst
->opcode
= BRW_OPCODE_ADD
;
2517 inst
->src
[2] = reg_undef
;
2519 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2520 inst
->opcode
= BRW_OPCODE_ADD
;
2521 inst
->src
[1].f
*= inst
->src
[2].f
;
2522 inst
->src
[2] = reg_undef
;
2526 case SHADER_OPCODE_BROADCAST
:
2527 if (is_uniform(inst
->src
[0])) {
2528 inst
->opcode
= BRW_OPCODE_MOV
;
2530 inst
->force_writemask_all
= true;
2532 } else if (inst
->src
[1].file
== IMM
) {
2533 inst
->opcode
= BRW_OPCODE_MOV
;
2534 /* It's possible that the selected component will be too large and
2535 * overflow the register. This can happen if someone does a
2536 * readInvocation() from GLSL or SPIR-V and provides an OOB
2537 * invocationIndex. If this happens and we some how manage
2538 * to constant fold it in and get here, then component() may cause
2539 * us to start reading outside of the VGRF which will lead to an
2540 * assert later. Instead, just let it wrap around if it goes over
2543 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2544 inst
->src
[0] = component(inst
->src
[0], comp
);
2546 inst
->force_writemask_all
= true;
2551 case SHADER_OPCODE_SHUFFLE
:
2552 if (is_uniform(inst
->src
[0])) {
2553 inst
->opcode
= BRW_OPCODE_MOV
;
2556 } else if (inst
->src
[1].file
== IMM
) {
2557 inst
->opcode
= BRW_OPCODE_MOV
;
2558 inst
->src
[0] = component(inst
->src
[0],
2569 /* Swap if src[0] is immediate. */
2570 if (progress
&& inst
->is_commutative()) {
2571 if (inst
->src
[0].file
== IMM
) {
2572 fs_reg tmp
= inst
->src
[1];
2573 inst
->src
[1] = inst
->src
[0];
2582 * Optimize sample messages that have constant zero values for the trailing
2583 * texture coordinates. We can just reduce the message length for these
2584 * instructions instead of reserving a register for it. Trailing parameters
2585 * that aren't sent default to zero anyway. This will cause the dead code
2586 * eliminator to remove the MOV instruction that would otherwise be emitted to
2587 * set up the zero value.
2590 fs_visitor::opt_zero_samples()
2592 /* Gen4 infers the texturing opcode based on the message length so we can't
2595 if (devinfo
->gen
< 5)
2598 bool progress
= false;
2600 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2601 if (!inst
->is_tex())
2604 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2606 if (load_payload
->is_head_sentinel() ||
2607 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2610 /* We don't want to remove the message header or the first parameter.
2611 * Removing the first parameter is not allowed, see the Haswell PRM
2612 * volume 7, page 149:
2614 * "Parameter 0 is required except for the sampleinfo message, which
2615 * has no parameter 0"
2617 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2618 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2619 (inst
->exec_size
/ 8) +
2620 inst
->header_size
- 1].is_zero()) {
2621 inst
->mlen
-= inst
->exec_size
/ 8;
2627 invalidate_live_intervals();
2633 * Optimize sample messages which are followed by the final RT write.
2635 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2636 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2637 * final texturing results copied to the framebuffer write payload and modify
2638 * them to write to the framebuffer directly.
2641 fs_visitor::opt_sampler_eot()
2643 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2645 if (stage
!= MESA_SHADER_FRAGMENT
)
2648 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2651 /* FINISHME: It should be possible to implement this optimization when there
2652 * are multiple drawbuffers.
2654 if (key
->nr_color_regions
!= 1)
2657 /* Requires emitting a bunch of saturating MOV instructions during logical
2658 * send lowering to clamp the color payload, which the sampler unit isn't
2659 * going to do for us.
2661 if (key
->clamp_fragment_color
)
2664 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2665 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2666 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2667 assert(fb_write
->eot
);
2668 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2670 /* There wasn't one; nothing to do. */
2671 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2674 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2676 /* 3D Sampler » Messages » Message Format
2678 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2679 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2681 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2682 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2683 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2684 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2685 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2686 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2687 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2688 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2691 /* XXX - This shouldn't be necessary. */
2692 if (tex_inst
->prev
->is_head_sentinel())
2695 /* Check that the FB write sources are fully initialized by the single
2696 * texturing instruction.
2698 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2699 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2700 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2701 fb_write
->size_read(i
) != tex_inst
->size_written
)
2703 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2704 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2709 assert(!tex_inst
->eot
); /* We can't get here twice */
2710 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2712 const fs_builder
ibld(this, block
, tex_inst
);
2714 tex_inst
->offset
|= fb_write
->target
<< 24;
2715 tex_inst
->eot
= true;
2716 tex_inst
->dst
= ibld
.null_reg_ud();
2717 tex_inst
->size_written
= 0;
2718 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2720 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2721 * flag and submit a header together with the sampler message as required
2724 invalidate_live_intervals();
2729 fs_visitor::opt_register_renaming()
2731 bool progress
= false;
2734 int remap
[alloc
.count
];
2735 memset(remap
, -1, sizeof(int) * alloc
.count
);
2737 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2738 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2740 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2741 inst
->opcode
== BRW_OPCODE_WHILE
) {
2745 /* Rewrite instruction sources. */
2746 for (int i
= 0; i
< inst
->sources
; i
++) {
2747 if (inst
->src
[i
].file
== VGRF
&&
2748 remap
[inst
->src
[i
].nr
] != -1 &&
2749 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2750 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2755 const int dst
= inst
->dst
.nr
;
2758 inst
->dst
.file
== VGRF
&&
2759 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2760 !inst
->is_partial_write()) {
2761 if (remap
[dst
] == -1) {
2764 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2765 inst
->dst
.nr
= remap
[dst
];
2768 } else if (inst
->dst
.file
== VGRF
&&
2770 remap
[dst
] != dst
) {
2771 inst
->dst
.nr
= remap
[dst
];
2777 invalidate_live_intervals();
2779 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2780 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2781 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2790 * Remove redundant or useless discard jumps.
2792 * For example, we can eliminate jumps in the following sequence:
2794 * discard-jump (redundant with the next jump)
2795 * discard-jump (useless; jumps to the next instruction)
2799 fs_visitor::opt_redundant_discard_jumps()
2801 bool progress
= false;
2803 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2805 fs_inst
*placeholder_halt
= NULL
;
2806 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2807 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2808 placeholder_halt
= inst
;
2813 if (!placeholder_halt
)
2816 /* Delete any HALTs immediately before the placeholder halt. */
2817 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2818 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2819 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2820 prev
->remove(last_bblock
);
2825 invalidate_live_intervals();
2831 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2832 * from \p r.offset which overlaps the region starting at \p s.offset and
2833 * spanning \p ds bytes.
2835 static inline unsigned
2836 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2838 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2839 const int shift
= rel_offset
/ REG_SIZE
;
2840 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2841 assert(reg_space(r
) == reg_space(s
) &&
2842 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2843 return ((1 << n
) - 1) << shift
;
2847 fs_visitor::opt_peephole_csel()
2849 if (devinfo
->gen
< 8)
2852 bool progress
= false;
2854 foreach_block_reverse(block
, cfg
) {
2855 int ip
= block
->end_ip
+ 1;
2857 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
2860 if (inst
->opcode
!= BRW_OPCODE_SEL
||
2861 inst
->predicate
!= BRW_PREDICATE_NORMAL
||
2862 (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
&&
2863 inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
2864 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
2867 /* Because it is a 3-src instruction, CSEL cannot have an immediate
2868 * value as a source, but we can sometimes handle zero.
2870 if ((inst
->src
[0].file
!= VGRF
&& inst
->src
[0].file
!= ATTR
&&
2871 inst
->src
[0].file
!= UNIFORM
) ||
2872 (inst
->src
[1].file
!= VGRF
&& inst
->src
[1].file
!= ATTR
&&
2873 inst
->src
[1].file
!= UNIFORM
&& !inst
->src
[1].is_zero()))
2876 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2877 if (!scan_inst
->flags_written())
2880 if ((scan_inst
->opcode
!= BRW_OPCODE_CMP
&&
2881 scan_inst
->opcode
!= BRW_OPCODE_MOV
) ||
2882 scan_inst
->predicate
!= BRW_PREDICATE_NONE
||
2883 (scan_inst
->src
[0].file
!= VGRF
&&
2884 scan_inst
->src
[0].file
!= ATTR
&&
2885 scan_inst
->src
[0].file
!= UNIFORM
) ||
2886 scan_inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2889 if (scan_inst
->opcode
== BRW_OPCODE_CMP
&& !scan_inst
->src
[1].is_zero())
2892 const brw::fs_builder
ibld(this, block
, inst
);
2894 const enum brw_conditional_mod cond
=
2895 inst
->predicate_inverse
2896 ? brw_negate_cmod(scan_inst
->conditional_mod
)
2897 : scan_inst
->conditional_mod
;
2899 fs_inst
*csel_inst
= NULL
;
2901 if (inst
->src
[1].file
!= IMM
) {
2902 csel_inst
= ibld
.CSEL(inst
->dst
,
2907 } else if (cond
== BRW_CONDITIONAL_NZ
) {
2908 /* Consider the sequence
2910 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
2911 * (+f0) sel g124<1>UD g2<8,8,1>UD 0x00000000UD
2913 * The sel will pick the immediate value 0 if r0 is ±0.0.
2914 * Therefore, this sequence is equivalent:
2916 * cmp.nz.f0 null<1>F g3<8,8,1>F 0F
2917 * (+f0) sel g124<1>F g2<8,8,1>F (abs)g3<8,8,1>F
2919 * The abs is ensures that the result is 0UD when g3 is -0.0F.
2920 * By normal cmp-sel merging, this is also equivalent:
2922 * csel.nz g124<1>F g2<4,4,1>F (abs)g3<4,4,1>F g3<4,4,1>F
2924 csel_inst
= ibld
.CSEL(inst
->dst
,
2930 csel_inst
->src
[1].abs
= true;
2933 if (csel_inst
!= NULL
) {
2935 inst
->remove(block
);
2947 fs_visitor::compute_to_mrf()
2949 bool progress
= false;
2952 /* No MRFs on Gen >= 7. */
2953 if (devinfo
->gen
>= 7)
2956 calculate_live_intervals();
2958 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2962 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2963 inst
->is_partial_write() ||
2964 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2965 inst
->dst
.type
!= inst
->src
[0].type
||
2966 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2967 !inst
->src
[0].is_contiguous() ||
2968 inst
->src
[0].offset
% REG_SIZE
!= 0)
2971 /* Can't compute-to-MRF this GRF if someone else was going to
2974 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2977 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2978 * things that computed the value of all GRFs of the source region. The
2979 * regs_left bitset keeps track of the registers we haven't yet found a
2980 * generating instruction for.
2982 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2984 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2985 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2986 inst
->src
[0], inst
->size_read(0))) {
2987 /* Found the last thing to write our reg we want to turn
2988 * into a compute-to-MRF.
2991 /* If this one instruction didn't populate all the
2992 * channels, bail. We might be able to rewrite everything
2993 * that writes that reg, but it would require smarter
2996 if (scan_inst
->is_partial_write())
2999 /* Handling things not fully contained in the source of the copy
3000 * would need us to understand coalescing out more than one MOV at
3003 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3004 inst
->src
[0], inst
->size_read(0)))
3007 /* SEND instructions can't have MRF as a destination. */
3008 if (scan_inst
->mlen
)
3011 if (devinfo
->gen
== 6) {
3012 /* gen6 math instructions must have the destination be
3013 * GRF, so no compute-to-MRF for them.
3015 if (scan_inst
->is_math()) {
3020 /* Clear the bits for any registers this instruction overwrites. */
3021 regs_left
&= ~mask_relative_to(
3022 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3027 /* We don't handle control flow here. Most computation of
3028 * values that end up in MRFs are shortly before the MRF
3031 if (block
->start() == scan_inst
)
3034 /* You can't read from an MRF, so if someone else reads our
3035 * MRF's source GRF that we wanted to rewrite, that stops us.
3037 bool interfered
= false;
3038 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3039 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3040 inst
->src
[0], inst
->size_read(0))) {
3047 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3048 inst
->dst
, inst
->size_written
)) {
3049 /* If somebody else writes our MRF here, we can't
3050 * compute-to-MRF before that.
3055 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3056 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3057 inst
->dst
, inst
->size_written
)) {
3058 /* Found a SEND instruction, which means that there are
3059 * live values in MRFs from base_mrf to base_mrf +
3060 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3070 /* Found all generating instructions of our MRF's source value, so it
3071 * should be safe to rewrite them to point to the MRF directly.
3073 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3075 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3076 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3077 inst
->src
[0], inst
->size_read(0))) {
3078 /* Clear the bits for any registers this instruction overwrites. */
3079 regs_left
&= ~mask_relative_to(
3080 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3082 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3083 reg_offset(inst
->src
[0]);
3085 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3086 /* Apply the same address transformation done by the hardware
3087 * for COMPR4 MRF writes.
3089 assert(rel_offset
< 2 * REG_SIZE
);
3090 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3092 /* Clear the COMPR4 bit if the generating instruction is not
3095 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3096 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3099 /* Calculate the MRF number the result of this instruction is
3100 * ultimately written to.
3102 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3105 scan_inst
->dst
.file
= MRF
;
3106 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3107 scan_inst
->saturate
|= inst
->saturate
;
3114 inst
->remove(block
);
3119 invalidate_live_intervals();
3125 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3126 * flow. We could probably do better here with some form of divergence
3130 fs_visitor::eliminate_find_live_channel()
3132 bool progress
= false;
3135 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3136 /* The optimization below assumes that channel zero is live on thread
3137 * dispatch, which may not be the case if the fixed function dispatches
3143 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3144 switch (inst
->opcode
) {
3150 case BRW_OPCODE_ENDIF
:
3151 case BRW_OPCODE_WHILE
:
3155 case FS_OPCODE_DISCARD_JUMP
:
3156 /* This can potentially make control flow non-uniform until the end
3161 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3163 inst
->opcode
= BRW_OPCODE_MOV
;
3164 inst
->src
[0] = brw_imm_ud(0u);
3166 inst
->force_writemask_all
= true;
3180 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3181 * instructions to FS_OPCODE_REP_FB_WRITE.
3184 fs_visitor::emit_repclear_shader()
3186 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3188 int color_mrf
= base_mrf
+ 2;
3192 mov
= bld
.exec_all().group(4, 0)
3193 .MOV(brw_message_reg(color_mrf
),
3194 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3196 struct brw_reg reg
=
3197 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3198 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3199 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3201 mov
= bld
.exec_all().group(4, 0)
3202 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3205 fs_inst
*write
= NULL
;
3206 if (key
->nr_color_regions
== 1) {
3207 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3208 write
->saturate
= key
->clamp_fragment_color
;
3209 write
->base_mrf
= color_mrf
;
3211 write
->header_size
= 0;
3214 assume(key
->nr_color_regions
> 0);
3215 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3216 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3217 write
->saturate
= key
->clamp_fragment_color
;
3218 write
->base_mrf
= base_mrf
;
3220 write
->header_size
= 2;
3228 assign_constant_locations();
3229 assign_curb_setup();
3231 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3233 assert(mov
->src
[0].file
== FIXED_GRF
);
3234 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3239 * Walks through basic blocks, looking for repeated MRF writes and
3240 * removing the later ones.
3243 fs_visitor::remove_duplicate_mrf_writes()
3245 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3246 bool progress
= false;
3248 /* Need to update the MRF tracking for compressed instructions. */
3249 if (dispatch_width
>= 16)
3252 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3254 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3255 if (inst
->is_control_flow()) {
3256 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3259 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3260 inst
->dst
.file
== MRF
) {
3261 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3262 if (prev_inst
&& inst
->equals(prev_inst
)) {
3263 inst
->remove(block
);
3269 /* Clear out the last-write records for MRFs that were overwritten. */
3270 if (inst
->dst
.file
== MRF
) {
3271 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3274 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3275 /* Found a SEND instruction, which will include two or fewer
3276 * implied MRF writes. We could do better here.
3278 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3279 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3283 /* Clear out any MRF move records whose sources got overwritten. */
3284 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3285 if (last_mrf_move
[i
] &&
3286 regions_overlap(inst
->dst
, inst
->size_written
,
3287 last_mrf_move
[i
]->src
[0],
3288 last_mrf_move
[i
]->size_read(0))) {
3289 last_mrf_move
[i
] = NULL
;
3293 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3294 inst
->dst
.file
== MRF
&&
3295 inst
->src
[0].file
!= ARF
&&
3296 !inst
->is_partial_write()) {
3297 last_mrf_move
[inst
->dst
.nr
] = inst
;
3302 invalidate_live_intervals();
3308 * Rounding modes for conversion instructions are included for each
3309 * conversion, but right now it is a state. So once it is set,
3310 * we don't need to call it again for subsequent calls.
3312 * This is useful for vector/matrices conversions, as setting the
3313 * mode once is enough for the full vector/matrix
3316 fs_visitor::remove_extra_rounding_modes()
3318 bool progress
= false;
3320 foreach_block (block
, cfg
) {
3321 brw_rnd_mode prev_mode
= BRW_RND_MODE_UNSPECIFIED
;
3323 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3324 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3325 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3326 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3327 if (mode
== prev_mode
) {
3328 inst
->remove(block
);
3338 invalidate_live_intervals();
3344 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3346 /* Clear the flag for registers that actually got read (as expected). */
3347 for (int i
= 0; i
< inst
->sources
; i
++) {
3349 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3350 grf
= inst
->src
[i
].nr
;
3355 if (grf
>= first_grf
&&
3356 grf
< first_grf
+ grf_len
) {
3357 deps
[grf
- first_grf
] = false;
3358 if (inst
->exec_size
== 16)
3359 deps
[grf
- first_grf
+ 1] = false;
3365 * Implements this workaround for the original 965:
3367 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3368 * check for post destination dependencies on this instruction, software
3369 * must ensure that there is no destination hazard for the case of ‘write
3370 * followed by a posted write’ shown in the following example.
3373 * 2. send r3.xy <rest of send instruction>
3376 * Due to no post-destination dependency check on the ‘send’, the above
3377 * code sequence could have two instructions (1 and 2) in flight at the
3378 * same time that both consider ‘r3’ as the target of their final writes.
3381 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3384 int write_len
= regs_written(inst
);
3385 int first_write_grf
= inst
->dst
.nr
;
3386 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3387 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3389 memset(needs_dep
, false, sizeof(needs_dep
));
3390 memset(needs_dep
, true, write_len
);
3392 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3394 /* Walk backwards looking for writes to registers we're writing which
3395 * aren't read since being written. If we hit the start of the program,
3396 * we assume that there are no outstanding dependencies on entry to the
3399 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3400 /* If we hit control flow, assume that there *are* outstanding
3401 * dependencies, and force their cleanup before our instruction.
3403 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3404 for (int i
= 0; i
< write_len
; i
++) {
3406 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3407 first_write_grf
+ i
);
3412 /* We insert our reads as late as possible on the assumption that any
3413 * instruction but a MOV that might have left us an outstanding
3414 * dependency has more latency than a MOV.
3416 if (scan_inst
->dst
.file
== VGRF
) {
3417 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3418 int reg
= scan_inst
->dst
.nr
+ i
;
3420 if (reg
>= first_write_grf
&&
3421 reg
< first_write_grf
+ write_len
&&
3422 needs_dep
[reg
- first_write_grf
]) {
3423 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3424 needs_dep
[reg
- first_write_grf
] = false;
3425 if (scan_inst
->exec_size
== 16)
3426 needs_dep
[reg
- first_write_grf
+ 1] = false;
3431 /* Clear the flag for registers that actually got read (as expected). */
3432 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3434 /* Continue the loop only if we haven't resolved all the dependencies */
3436 for (i
= 0; i
< write_len
; i
++) {
3446 * Implements this workaround for the original 965:
3448 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3449 * used as a destination register until after it has been sourced by an
3450 * instruction with a different destination register.
3453 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3455 int write_len
= regs_written(inst
);
3456 int first_write_grf
= inst
->dst
.nr
;
3457 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3458 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3460 memset(needs_dep
, false, sizeof(needs_dep
));
3461 memset(needs_dep
, true, write_len
);
3462 /* Walk forwards looking for writes to registers we're writing which aren't
3463 * read before being written.
3465 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3466 /* If we hit control flow, force resolve all remaining dependencies. */
3467 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3468 for (int i
= 0; i
< write_len
; i
++) {
3470 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3471 first_write_grf
+ i
);
3476 /* Clear the flag for registers that actually got read (as expected). */
3477 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3479 /* We insert our reads as late as possible since they're reading the
3480 * result of a SEND, which has massive latency.
3482 if (scan_inst
->dst
.file
== VGRF
&&
3483 scan_inst
->dst
.nr
>= first_write_grf
&&
3484 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3485 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3486 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3488 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3491 /* Continue the loop only if we haven't resolved all the dependencies */
3493 for (i
= 0; i
< write_len
; i
++) {
3503 fs_visitor::insert_gen4_send_dependency_workarounds()
3505 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3508 bool progress
= false;
3510 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3511 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3512 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3513 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3519 invalidate_live_intervals();
3523 * Turns the generic expression-style uniform pull constant load instruction
3524 * into a hardware-specific series of instructions for loading a pull
3527 * The expression style allows the CSE pass before this to optimize out
3528 * repeated loads from the same offset, and gives the pre-register-allocation
3529 * scheduling full flexibility, while the conversion to native instructions
3530 * allows the post-register-allocation scheduler the best information
3533 * Note that execution masking for setting up pull constant loads is special:
3534 * the channels that need to be written are unrelated to the current execution
3535 * mask, since a later instruction will use one of the result channels as a
3536 * source operand for all 8 or 16 of its channels.
3539 fs_visitor::lower_uniform_pull_constant_loads()
3541 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3542 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3545 if (devinfo
->gen
>= 7) {
3546 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3547 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3549 ubld
.group(8, 0).MOV(payload
,
3550 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3551 ubld
.group(1, 0).MOV(component(payload
, 2),
3552 brw_imm_ud(inst
->src
[1].ud
/ 16));
3554 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3555 inst
->src
[1] = payload
;
3556 inst
->header_size
= 1;
3559 invalidate_live_intervals();
3561 /* Before register allocation, we didn't tell the scheduler about the
3562 * MRF we use. We know it's safe to use this MRF because nothing
3563 * else does except for register spill/unspill, which generates and
3564 * uses its MRF within a single IR instruction.
3566 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3573 fs_visitor::lower_load_payload()
3575 bool progress
= false;
3577 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3578 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3581 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3582 assert(inst
->saturate
== false);
3583 fs_reg dst
= inst
->dst
;
3585 /* Get rid of COMPR4. We'll add it back in if we need it */
3586 if (dst
.file
== MRF
)
3587 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3589 const fs_builder
ibld(this, block
, inst
);
3590 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3592 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3593 if (inst
->src
[i
].file
!= BAD_FILE
) {
3594 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3595 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3596 hbld
.MOV(mov_dst
, mov_src
);
3598 dst
= offset(dst
, hbld
, 1);
3601 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3602 inst
->exec_size
> 8) {
3603 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3604 * a straightforward copy. Instead, the result of the
3605 * LOAD_PAYLOAD is treated as interleaved and the first four
3606 * non-header sources are unpacked as:
3617 * This is used for gen <= 5 fb writes.
3619 assert(inst
->exec_size
== 16);
3620 assert(inst
->header_size
+ 4 <= inst
->sources
);
3621 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3622 if (inst
->src
[i
].file
!= BAD_FILE
) {
3623 if (devinfo
->has_compr4
) {
3624 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3625 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3626 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3628 /* Platform doesn't have COMPR4. We have to fake it */
3629 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3630 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3632 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3639 /* The loop above only ever incremented us through the first set
3640 * of 4 registers. However, thanks to the magic of COMPR4, we
3641 * actually wrote to the first 8 registers, so we need to take
3642 * that into account now.
3646 /* The COMPR4 code took care of the first 4 sources. We'll let
3647 * the regular path handle any remaining sources. Yes, we are
3648 * modifying the instruction but we're about to delete it so
3649 * this really doesn't hurt anything.
3651 inst
->header_size
+= 4;
3654 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3655 if (inst
->src
[i
].file
!= BAD_FILE
)
3656 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3657 dst
= offset(dst
, ibld
, 1);
3660 inst
->remove(block
);
3665 invalidate_live_intervals();
3671 fs_visitor::lower_integer_multiplication()
3673 bool progress
= false;
3675 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3676 const fs_builder
ibld(this, block
, inst
);
3678 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3679 if (inst
->dst
.is_accumulator() ||
3680 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3681 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3684 if (devinfo
->has_integer_dword_mul
)
3687 if (inst
->src
[1].file
== IMM
&&
3688 inst
->src
[1].ud
< (1 << 16)) {
3689 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3690 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3693 * If multiplying by an immediate value that fits in 16-bits, do a
3694 * single MUL instruction with that value in the proper location.
3696 if (devinfo
->gen
< 7) {
3697 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3699 ibld
.MOV(imm
, inst
->src
[1]);
3700 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3702 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3703 ibld
.MUL(inst
->dst
, inst
->src
[0],
3704 ud
? brw_imm_uw(inst
->src
[1].ud
)
3705 : brw_imm_w(inst
->src
[1].d
));
3708 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3709 * do 32-bit integer multiplication in one instruction, but instead
3710 * must do a sequence (which actually calculates a 64-bit result):
3712 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3713 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3714 * mov(8) g2<1>D acc0<8,8,1>D
3716 * But on Gen > 6, the ability to use second accumulator register
3717 * (acc1) for non-float data types was removed, preventing a simple
3718 * implementation in SIMD16. A 16-channel result can be calculated by
3719 * executing the three instructions twice in SIMD8, once with quarter
3720 * control of 1Q for the first eight channels and again with 2Q for
3721 * the second eight channels.
3723 * Which accumulator register is implicitly accessed (by AccWrEnable
3724 * for instance) is determined by the quarter control. Unfortunately
3725 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3726 * implicit accumulator access by an instruction with 2Q will access
3727 * acc1 regardless of whether the data type is usable in acc1.
3729 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3730 * integer data types.
3732 * Since we only want the low 32-bits of the result, we can do two
3733 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3734 * adjust the high result and add them (like the mach is doing):
3736 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3737 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3738 * shl(8) g9<1>D g8<8,8,1>D 16D
3739 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3741 * We avoid the shl instruction by realizing that we only want to add
3742 * the low 16-bits of the "high" result to the high 16-bits of the
3743 * "low" result and using proper regioning on the add:
3745 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3746 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3747 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3749 * Since it does not use the (single) accumulator register, we can
3750 * schedule multi-component multiplications much better.
3753 bool needs_mov
= false;
3754 fs_reg orig_dst
= inst
->dst
;
3755 fs_reg low
= inst
->dst
;
3756 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3757 regions_overlap(inst
->dst
, inst
->size_written
,
3758 inst
->src
[0], inst
->size_read(0)) ||
3759 regions_overlap(inst
->dst
, inst
->size_written
,
3760 inst
->src
[1], inst
->size_read(1))) {
3762 /* Get a new VGRF but keep the same stride as inst->dst */
3763 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
3765 low
.stride
= inst
->dst
.stride
;
3766 low
.offset
= inst
->dst
.offset
% REG_SIZE
;
3769 /* Get a new VGRF but keep the same stride as inst->dst */
3770 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)),
3772 high
.stride
= inst
->dst
.stride
;
3773 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
3775 if (devinfo
->gen
>= 7) {
3776 if (inst
->src
[1].file
== IMM
) {
3777 ibld
.MUL(low
, inst
->src
[0],
3778 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3779 ibld
.MUL(high
, inst
->src
[0],
3780 brw_imm_uw(inst
->src
[1].ud
>> 16));
3782 ibld
.MUL(low
, inst
->src
[0],
3783 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3784 ibld
.MUL(high
, inst
->src
[0],
3785 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3788 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3790 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3794 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3795 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3796 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3798 if (needs_mov
|| inst
->conditional_mod
) {
3799 set_condmod(inst
->conditional_mod
,
3800 ibld
.MOV(orig_dst
, low
));
3804 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3805 /* Should have been lowered to 8-wide. */
3806 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3807 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3809 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3810 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3812 if (devinfo
->gen
>= 8) {
3813 /* Until Gen8, integer multiplies read 32-bits from one source,
3814 * and 16-bits from the other, and relying on the MACH instruction
3815 * to generate the high bits of the result.
3817 * On Gen8, the multiply instruction does a full 32x32-bit
3818 * multiply, but in order to do a 64-bit multiply we can simulate
3819 * the previous behavior and then use a MACH instruction.
3821 * FINISHME: Don't use source modifiers on src1.
3823 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3824 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3825 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3826 mul
->src
[1].stride
*= 2;
3828 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3830 /* Among other things the quarter control bits influence which
3831 * accumulator register is used by the hardware for instructions
3832 * that access the accumulator implicitly (e.g. MACH). A
3833 * second-half instruction would normally map to acc1, which
3834 * doesn't exist on Gen7 and up (the hardware does emulate it for
3835 * floating-point instructions *only* by taking advantage of the
3836 * extra precision of acc0 not normally used for floating point
3839 * HSW and up are careful enough not to try to access an
3840 * accumulator register that doesn't exist, but on earlier Gen7
3841 * hardware we need to make sure that the quarter control bits are
3842 * zero to avoid non-deterministic behaviour and emit an extra MOV
3843 * to get the result masked correctly according to the current
3847 mach
->force_writemask_all
= true;
3848 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3849 ibld
.MOV(inst
->dst
, mach
->dst
);
3855 inst
->remove(block
);
3860 invalidate_live_intervals();
3866 fs_visitor::lower_minmax()
3868 assert(devinfo
->gen
< 6);
3870 bool progress
= false;
3872 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3873 const fs_builder
ibld(this, block
, inst
);
3875 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3876 inst
->predicate
== BRW_PREDICATE_NONE
) {
3877 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3878 * the original SEL.L/GE instruction
3880 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3881 inst
->conditional_mod
);
3882 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3883 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3890 invalidate_live_intervals();
3896 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3897 fs_reg
*dst
, fs_reg color
, unsigned components
)
3899 if (key
->clamp_fragment_color
) {
3900 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3901 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3903 for (unsigned i
= 0; i
< components
; i
++)
3905 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3910 for (unsigned i
= 0; i
< components
; i
++)
3911 dst
[i
] = offset(color
, bld
, i
);
3915 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3916 const struct brw_wm_prog_data
*prog_data
,
3917 const brw_wm_prog_key
*key
,
3918 const fs_visitor::thread_payload
&payload
)
3920 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3921 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3922 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3923 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3924 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3925 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3926 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3927 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3928 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3929 const unsigned components
=
3930 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3932 /* We can potentially have a message length of up to 15, so we have to set
3933 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3936 int header_size
= 2, payload_header_size
;
3937 unsigned length
= 0;
3939 /* From the Sandy Bridge PRM, volume 4, page 198:
3941 * "Dispatched Pixel Enables. One bit per pixel indicating
3942 * which pixels were originally enabled when the thread was
3943 * dispatched. This field is only required for the end-of-
3944 * thread message and on all dual-source messages."
3946 if (devinfo
->gen
>= 6 &&
3947 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3948 color1
.file
== BAD_FILE
&&
3949 key
->nr_color_regions
== 1) {
3953 if (header_size
!= 0) {
3954 assert(header_size
== 2);
3955 /* Allocate 2 registers for a header */
3959 if (payload
.aa_dest_stencil_reg
) {
3960 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3961 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3962 .MOV(sources
[length
],
3963 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3967 if (sample_mask
.file
!= BAD_FILE
) {
3968 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3969 BRW_REGISTER_TYPE_UD
);
3971 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3972 * relevant. Since it's unsigned single words one vgrf is always
3973 * 16-wide, but only the lower or higher 8 channels will be used by the
3974 * hardware when doing a SIMD8 write depending on whether we have
3975 * selected the subspans for the first or second half respectively.
3977 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3978 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3979 sample_mask
.stride
*= 2;
3981 bld
.exec_all().annotate("FB write oMask")
3982 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3988 payload_header_size
= length
;
3990 if (src0_alpha
.file
!= BAD_FILE
) {
3991 /* FIXME: This is being passed at the wrong location in the payload and
3992 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3993 * It's supposed to be immediately before oMask but there seems to be no
3994 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3995 * requires header sources to form a contiguous segment at the beginning
3996 * of the message and src0_alpha has per-channel semantics.
3998 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
4000 } else if (key
->replicate_alpha
&& inst
->target
!= 0) {
4001 /* Handle the case when fragment shader doesn't write to draw buffer
4002 * zero. No need to call setup_color_payload() for src0_alpha because
4003 * alpha value will be undefined.
4008 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4011 if (color1
.file
!= BAD_FILE
) {
4012 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4016 if (src_depth
.file
!= BAD_FILE
) {
4017 sources
[length
] = src_depth
;
4021 if (dst_depth
.file
!= BAD_FILE
) {
4022 sources
[length
] = dst_depth
;
4026 if (src_stencil
.file
!= BAD_FILE
) {
4027 assert(devinfo
->gen
>= 9);
4028 assert(bld
.dispatch_width() != 16);
4030 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4031 * available on gen9+. As such it's impossible to have both enabled at the
4032 * same time and therefore length cannot overrun the array.
4034 assert(length
< 15);
4036 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4037 bld
.exec_all().annotate("FB write OS")
4038 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4039 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4044 if (devinfo
->gen
>= 7) {
4045 /* Send from the GRF */
4046 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4047 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4048 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4049 load
->dst
= payload
;
4051 inst
->src
[0] = payload
;
4052 inst
->resize_sources(1);
4054 /* Send from the MRF */
4055 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4056 sources
, length
, payload_header_size
);
4058 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4059 * will do this for us if we just give it a COMPR4 destination.
4061 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4062 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4064 inst
->resize_sources(0);
4068 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4069 inst
->mlen
= regs_written(load
);
4070 inst
->header_size
= header_size
;
4074 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4076 const fs_builder
&ubld
= bld
.exec_all();
4077 const unsigned length
= 2;
4078 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
4081 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4083 inst
->resize_sources(1);
4084 inst
->src
[0] = header
;
4085 inst
->opcode
= FS_OPCODE_FB_READ
;
4086 inst
->mlen
= length
;
4087 inst
->header_size
= length
;
4091 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4092 const fs_reg
&coordinate
,
4093 const fs_reg
&shadow_c
,
4094 const fs_reg
&lod
, const fs_reg
&lod2
,
4095 const fs_reg
&surface
,
4096 const fs_reg
&sampler
,
4097 unsigned coord_components
,
4098 unsigned grad_components
)
4100 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4101 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4102 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4103 fs_reg msg_end
= msg_begin
;
4106 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4108 for (unsigned i
= 0; i
< coord_components
; i
++)
4109 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4110 offset(coordinate
, bld
, i
));
4112 msg_end
= offset(msg_end
, bld
, coord_components
);
4114 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4115 * require all three components to be present and zero if they are unused.
4117 if (coord_components
> 0 &&
4118 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4119 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4120 for (unsigned i
= coord_components
; i
< 3; i
++)
4121 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4123 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4126 if (op
== SHADER_OPCODE_TXD
) {
4127 /* TXD unsupported in SIMD16 mode. */
4128 assert(bld
.dispatch_width() == 8);
4130 /* the slots for u and v are always present, but r is optional */
4131 if (coord_components
< 2)
4132 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4135 * dPdx = dudx, dvdx, drdx
4136 * dPdy = dudy, dvdy, drdy
4138 * 1-arg: Does not exist.
4140 * 2-arg: dudx dvdx dudy dvdy
4141 * dPdx.x dPdx.y dPdy.x dPdy.y
4144 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4145 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4146 * m5 m6 m7 m8 m9 m10
4148 for (unsigned i
= 0; i
< grad_components
; i
++)
4149 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4151 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4153 for (unsigned i
= 0; i
< grad_components
; i
++)
4154 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4156 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4160 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4161 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4163 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4164 bld
.dispatch_width() == 16);
4166 const brw_reg_type type
=
4167 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4168 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4169 bld
.MOV(retype(msg_end
, type
), lod
);
4170 msg_end
= offset(msg_end
, bld
, 1);
4173 if (shadow_c
.file
!= BAD_FILE
) {
4174 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4175 /* There's no plain shadow compare message, so we use shadow
4176 * compare with a bias of 0.0.
4178 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4179 msg_end
= offset(msg_end
, bld
, 1);
4182 bld
.MOV(msg_end
, shadow_c
);
4183 msg_end
= offset(msg_end
, bld
, 1);
4187 inst
->src
[0] = reg_undef
;
4188 inst
->src
[1] = surface
;
4189 inst
->src
[2] = sampler
;
4190 inst
->resize_sources(3);
4191 inst
->base_mrf
= msg_begin
.nr
;
4192 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4193 inst
->header_size
= 1;
4197 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4198 const fs_reg
&coordinate
,
4199 const fs_reg
&shadow_c
,
4200 const fs_reg
&lod
, const fs_reg
&lod2
,
4201 const fs_reg
&sample_index
,
4202 const fs_reg
&surface
,
4203 const fs_reg
&sampler
,
4204 unsigned coord_components
,
4205 unsigned grad_components
)
4207 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4208 fs_reg msg_coords
= message
;
4209 unsigned header_size
= 0;
4211 if (inst
->offset
!= 0) {
4212 /* The offsets set up by the visitor are in the m1 header, so we can't
4219 for (unsigned i
= 0; i
< coord_components
; i
++)
4220 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4221 offset(coordinate
, bld
, i
));
4223 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4224 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4226 if (shadow_c
.file
!= BAD_FILE
) {
4227 fs_reg msg_shadow
= msg_lod
;
4228 bld
.MOV(msg_shadow
, shadow_c
);
4229 msg_lod
= offset(msg_shadow
, bld
, 1);
4234 case SHADER_OPCODE_TXL
:
4236 bld
.MOV(msg_lod
, lod
);
4237 msg_end
= offset(msg_lod
, bld
, 1);
4239 case SHADER_OPCODE_TXD
:
4242 * dPdx = dudx, dvdx, drdx
4243 * dPdy = dudy, dvdy, drdy
4245 * Load up these values:
4246 * - dudx dudy dvdx dvdy drdx drdy
4247 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4250 for (unsigned i
= 0; i
< grad_components
; i
++) {
4251 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4252 msg_end
= offset(msg_end
, bld
, 1);
4254 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4255 msg_end
= offset(msg_end
, bld
, 1);
4258 case SHADER_OPCODE_TXS
:
4259 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4260 bld
.MOV(msg_lod
, lod
);
4261 msg_end
= offset(msg_lod
, bld
, 1);
4263 case SHADER_OPCODE_TXF
:
4264 msg_lod
= offset(msg_coords
, bld
, 3);
4265 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4266 msg_end
= offset(msg_lod
, bld
, 1);
4268 case SHADER_OPCODE_TXF_CMS
:
4269 msg_lod
= offset(msg_coords
, bld
, 3);
4271 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4273 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4274 msg_end
= offset(msg_lod
, bld
, 2);
4281 inst
->src
[0] = reg_undef
;
4282 inst
->src
[1] = surface
;
4283 inst
->src
[2] = sampler
;
4284 inst
->resize_sources(3);
4285 inst
->base_mrf
= message
.nr
;
4286 inst
->mlen
= msg_end
.nr
- message
.nr
;
4287 inst
->header_size
= header_size
;
4289 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4290 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4294 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4296 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4299 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4303 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4304 const fs_reg
&coordinate
,
4305 const fs_reg
&shadow_c
,
4306 fs_reg lod
, const fs_reg
&lod2
,
4307 const fs_reg
&sample_index
,
4309 const fs_reg
&surface
,
4310 const fs_reg
&sampler
,
4311 const fs_reg
&tg4_offset
,
4312 unsigned coord_components
,
4313 unsigned grad_components
)
4315 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4316 unsigned reg_width
= bld
.dispatch_width() / 8;
4317 unsigned header_size
= 0, length
= 0;
4318 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4319 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4320 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4322 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4323 inst
->offset
!= 0 || inst
->eot
||
4324 op
== SHADER_OPCODE_SAMPLEINFO
||
4325 is_high_sampler(devinfo
, sampler
)) {
4326 /* For general texture offsets (no txf workaround), we need a header to
4329 * TG4 needs to place its channel select in the header, for interaction
4330 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4331 * larger sampler numbers we need to offset the Sampler State Pointer in
4334 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4338 /* If we're requesting fewer than four channels worth of response,
4339 * and we have an explicit header, we need to set up the sampler
4340 * writemask. It's reversed from normal: 1 means "don't write".
4342 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4343 assert(regs_written(inst
) % reg_width
== 0);
4344 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4345 inst
->offset
|= mask
<< 12;
4348 /* Build the actual header */
4349 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4350 const fs_builder ubld1
= ubld
.group(1, 0);
4351 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4353 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4354 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4355 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4356 /* The vertex and fragment stages have g0.2 set to 0, so
4357 * header0.2 is 0 when g0 is copied. Other stages may not, so we
4358 * must set it to 0 to avoid setting undesirable bits in the
4361 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
4364 if (is_high_sampler(devinfo
, sampler
)) {
4365 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
4366 assert(sampler
.ud
>= 16);
4367 const int sampler_state_size
= 16; /* 16 bytes */
4369 ubld1
.ADD(component(header
, 3),
4370 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4371 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
4373 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
4374 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
4375 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
4376 ubld1
.ADD(component(header
, 3),
4377 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4383 if (shadow_c
.file
!= BAD_FILE
) {
4384 bld
.MOV(sources
[length
], shadow_c
);
4388 bool coordinate_done
= false;
4390 /* Set up the LOD info */
4393 case SHADER_OPCODE_TXL
:
4394 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4395 op
= SHADER_OPCODE_TXL_LZ
;
4398 bld
.MOV(sources
[length
], lod
);
4401 case SHADER_OPCODE_TXD
:
4402 /* TXD should have been lowered in SIMD16 mode. */
4403 assert(bld
.dispatch_width() == 8);
4405 /* Load dPdx and the coordinate together:
4406 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4408 for (unsigned i
= 0; i
< coord_components
; i
++) {
4409 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4411 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4412 * only derivatives for (u, v, r).
4414 if (i
< grad_components
) {
4415 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4416 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4420 coordinate_done
= true;
4422 case SHADER_OPCODE_TXS
:
4423 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4426 case SHADER_OPCODE_TXF
:
4427 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4428 * On Gen9 they are u, v, lod, r
4430 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4432 if (devinfo
->gen
>= 9) {
4433 if (coord_components
>= 2) {
4434 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4435 offset(coordinate
, bld
, 1));
4437 sources
[length
] = brw_imm_d(0);
4442 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4443 op
= SHADER_OPCODE_TXF_LZ
;
4445 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4449 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4450 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4451 offset(coordinate
, bld
, i
));
4453 coordinate_done
= true;
4456 case SHADER_OPCODE_TXF_CMS
:
4457 case SHADER_OPCODE_TXF_CMS_W
:
4458 case SHADER_OPCODE_TXF_UMS
:
4459 case SHADER_OPCODE_TXF_MCS
:
4460 if (op
== SHADER_OPCODE_TXF_UMS
||
4461 op
== SHADER_OPCODE_TXF_CMS
||
4462 op
== SHADER_OPCODE_TXF_CMS_W
) {
4463 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4467 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4468 /* Data from the multisample control surface. */
4469 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4472 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4475 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4476 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4479 offset(mcs
, bld
, 1));
4484 /* There is no offsetting for this message; just copy in the integer
4485 * texture coordinates.
4487 for (unsigned i
= 0; i
< coord_components
; i
++)
4488 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4489 offset(coordinate
, bld
, i
));
4491 coordinate_done
= true;
4493 case SHADER_OPCODE_TG4_OFFSET
:
4494 /* More crazy intermixing */
4495 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4496 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4498 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4499 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4500 offset(tg4_offset
, bld
, i
));
4502 if (coord_components
== 3) /* r if present */
4503 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4505 coordinate_done
= true;
4511 /* Set up the coordinate (except for cases where it was done above) */
4512 if (!coordinate_done
) {
4513 for (unsigned i
= 0; i
< coord_components
; i
++)
4514 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4519 mlen
= length
* reg_width
- header_size
;
4521 mlen
= length
* reg_width
;
4523 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4524 BRW_REGISTER_TYPE_F
);
4525 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4527 /* Generate the SEND. */
4529 inst
->src
[0] = src_payload
;
4530 inst
->src
[1] = surface
;
4531 inst
->src
[2] = sampler
;
4532 inst
->resize_sources(3);
4534 inst
->header_size
= header_size
;
4536 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4537 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4541 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4543 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4544 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4545 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4546 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4547 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4548 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4549 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4550 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4551 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4552 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
4553 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4554 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4555 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4556 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4558 if (devinfo
->gen
>= 7) {
4559 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4560 shadow_c
, lod
, lod2
, sample_index
,
4561 mcs
, surface
, sampler
, tg4_offset
,
4562 coord_components
, grad_components
);
4563 } else if (devinfo
->gen
>= 5) {
4564 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4565 shadow_c
, lod
, lod2
, sample_index
,
4567 coord_components
, grad_components
);
4569 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4570 shadow_c
, lod
, lod2
,
4572 coord_components
, grad_components
);
4577 * Initialize the header present in some typed and untyped surface
4581 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4583 fs_builder ubld
= bld
.exec_all().group(8, 0);
4584 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4585 ubld
.MOV(dst
, brw_imm_d(0));
4586 ubld
.group(1, 0).MOV(component(dst
, 7), sample_mask
);
4591 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4592 const fs_reg
&sample_mask
)
4594 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4596 /* Get the logical send arguments. */
4597 const fs_reg
&addr
= inst
->src
[0];
4598 const fs_reg
&src
= inst
->src
[1];
4599 const fs_reg
&surface
= inst
->src
[2];
4600 const UNUSED fs_reg
&dims
= inst
->src
[3];
4601 const fs_reg
&arg
= inst
->src
[4];
4603 /* Calculate the total number of components of the payload. */
4604 const unsigned addr_sz
= inst
->components_read(0);
4605 const unsigned src_sz
= inst
->components_read(1);
4606 /* From the BDW PRM Volume 7, page 147:
4608 * "For the Data Cache Data Port*, the header must be present for the
4609 * following message types: [...] Typed read/write/atomics"
4611 * Earlier generations have a similar wording. Because of this restriction
4612 * we don't attempt to implement sample masks via predication for such
4613 * messages prior to Gen9, since we have to provide a header anyway. On
4614 * Gen11+ the header has been removed so we can only use predication.
4616 const unsigned header_sz
= devinfo
->gen
< 9 &&
4617 (op
== SHADER_OPCODE_TYPED_SURFACE_READ
||
4618 op
== SHADER_OPCODE_TYPED_SURFACE_WRITE
||
4619 op
== SHADER_OPCODE_TYPED_ATOMIC
) ? 1 : 0;
4620 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4622 /* Allocate space for the payload. */
4623 fs_reg
*const components
= new fs_reg
[sz
];
4624 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4627 /* Construct the payload. */
4629 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4631 for (unsigned i
= 0; i
< addr_sz
; i
++)
4632 components
[n
++] = offset(addr
, bld
, i
);
4634 for (unsigned i
= 0; i
< src_sz
; i
++)
4635 components
[n
++] = offset(src
, bld
, i
);
4637 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4639 /* Predicate the instruction on the sample mask if no header is
4642 if (!header_sz
&& sample_mask
.file
!= BAD_FILE
&&
4643 sample_mask
.file
!= IMM
) {
4644 const fs_builder ubld
= bld
.group(1, 0).exec_all();
4645 if (inst
->predicate
) {
4646 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
4647 assert(!inst
->predicate_inverse
);
4648 assert(inst
->flag_subreg
< 2);
4649 /* Combine the sample mask with the existing predicate by using a
4650 * vertical predication mode.
4652 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
4653 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
+ 2),
4657 inst
->flag_subreg
= 2;
4658 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4659 inst
->predicate_inverse
= false;
4660 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
4665 /* Update the original instruction. */
4667 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4668 inst
->header_size
= header_sz
;
4670 inst
->src
[0] = payload
;
4671 inst
->src
[1] = surface
;
4673 inst
->resize_sources(3);
4675 delete[] components
;
4679 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4681 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4683 if (devinfo
->gen
>= 7) {
4684 /* We are switching the instruction from an ALU-like instruction to a
4685 * send-from-grf instruction. Since sends can't handle strides or
4686 * source modifiers, we have to make a copy of the offset source.
4688 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4689 bld
.MOV(tmp
, inst
->src
[1]);
4692 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4695 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4696 BRW_REGISTER_TYPE_UD
);
4698 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4700 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4701 inst
->resize_sources(1);
4702 inst
->base_mrf
= payload
.nr
;
4703 inst
->header_size
= 1;
4704 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4709 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4711 assert(bld
.shader
->devinfo
->gen
< 6);
4714 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4716 if (inst
->sources
> 1) {
4717 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4718 * "Message Payload":
4720 * "Operand0[7]. For the INT DIV functions, this operand is the
4723 * "Operand1[7]. For the INT DIV functions, this operand is the
4726 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4727 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4728 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4730 inst
->resize_sources(1);
4731 inst
->src
[0] = src0
;
4733 assert(inst
->exec_size
== 8);
4734 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4739 fs_visitor::lower_logical_sends()
4741 bool progress
= false;
4743 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4744 const fs_builder
ibld(this, block
, inst
);
4746 switch (inst
->opcode
) {
4747 case FS_OPCODE_FB_WRITE_LOGICAL
:
4748 assert(stage
== MESA_SHADER_FRAGMENT
);
4749 lower_fb_write_logical_send(ibld
, inst
,
4750 brw_wm_prog_data(prog_data
),
4751 (const brw_wm_prog_key
*)key
,
4755 case FS_OPCODE_FB_READ_LOGICAL
:
4756 lower_fb_read_logical_send(ibld
, inst
);
4759 case SHADER_OPCODE_TEX_LOGICAL
:
4760 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4763 case SHADER_OPCODE_TXD_LOGICAL
:
4764 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4767 case SHADER_OPCODE_TXF_LOGICAL
:
4768 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4771 case SHADER_OPCODE_TXL_LOGICAL
:
4772 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4775 case SHADER_OPCODE_TXS_LOGICAL
:
4776 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4779 case FS_OPCODE_TXB_LOGICAL
:
4780 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4783 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4784 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4787 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4788 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4791 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4792 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4795 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4796 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4799 case SHADER_OPCODE_LOD_LOGICAL
:
4800 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4803 case SHADER_OPCODE_TG4_LOGICAL
:
4804 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4807 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4808 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4811 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4812 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4815 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4816 lower_surface_logical_send(ibld
, inst
,
4817 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4821 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4822 lower_surface_logical_send(ibld
, inst
,
4823 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4824 ibld
.sample_mask_reg());
4827 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
4828 lower_surface_logical_send(ibld
, inst
,
4829 SHADER_OPCODE_BYTE_SCATTERED_READ
,
4833 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
4834 lower_surface_logical_send(ibld
, inst
,
4835 SHADER_OPCODE_BYTE_SCATTERED_WRITE
,
4836 ibld
.sample_mask_reg());
4839 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4840 lower_surface_logical_send(ibld
, inst
,
4841 SHADER_OPCODE_UNTYPED_ATOMIC
,
4842 ibld
.sample_mask_reg());
4845 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4846 lower_surface_logical_send(ibld
, inst
,
4847 SHADER_OPCODE_TYPED_SURFACE_READ
,
4851 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4852 lower_surface_logical_send(ibld
, inst
,
4853 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4854 ibld
.sample_mask_reg());
4857 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4858 lower_surface_logical_send(ibld
, inst
,
4859 SHADER_OPCODE_TYPED_ATOMIC
,
4860 ibld
.sample_mask_reg());
4863 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4864 lower_varying_pull_constant_logical_send(ibld
, inst
);
4867 case SHADER_OPCODE_RCP
:
4868 case SHADER_OPCODE_RSQ
:
4869 case SHADER_OPCODE_SQRT
:
4870 case SHADER_OPCODE_EXP2
:
4871 case SHADER_OPCODE_LOG2
:
4872 case SHADER_OPCODE_SIN
:
4873 case SHADER_OPCODE_COS
:
4874 case SHADER_OPCODE_POW
:
4875 case SHADER_OPCODE_INT_QUOTIENT
:
4876 case SHADER_OPCODE_INT_REMAINDER
:
4877 /* The math opcodes are overloaded for the send-like and
4878 * expression-like instructions which seems kind of icky. Gen6+ has
4879 * a native (but rather quirky) MATH instruction so we don't need to
4880 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4881 * logical instructions (which we can easily recognize because they
4882 * have mlen = 0) into send-like virtual instructions.
4884 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4885 lower_math_logical_send(ibld
, inst
);
4900 invalidate_live_intervals();
4906 * Get the closest allowed SIMD width for instruction \p inst accounting for
4907 * some common regioning and execution control restrictions that apply to FPU
4908 * instructions. These restrictions don't necessarily have any relevance to
4909 * instructions not executed by the FPU pipeline like extended math, control
4910 * flow or send message instructions.
4912 * For virtual opcodes it's really up to the instruction -- In some cases
4913 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4914 * instructions) it may simplify virtual instruction lowering if we can
4915 * enforce FPU-like regioning restrictions already on the virtual instruction,
4916 * in other cases (e.g. virtual send-like instructions) this may be
4917 * excessively restrictive.
4920 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4921 const fs_inst
*inst
)
4923 /* Maximum execution size representable in the instruction controls. */
4924 unsigned max_width
= MIN2(32, inst
->exec_size
);
4926 /* According to the PRMs:
4927 * "A. In Direct Addressing mode, a source cannot span more than 2
4928 * adjacent GRF registers.
4929 * B. A destination cannot span more than 2 adjacent GRF registers."
4931 * Look for the source or destination with the largest register region
4932 * which is the one that is going to limit the overall execution size of
4933 * the instruction due to this rule.
4935 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4937 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4938 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4940 /* Calculate the maximum execution size of the instruction based on the
4941 * factor by which it goes over the hardware limit of 2 GRFs.
4944 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4946 /* According to the IVB PRMs:
4947 * "When destination spans two registers, the source MUST span two
4948 * registers. The exception to the above rule:
4950 * - When source is scalar, the source registers are not incremented.
4951 * - When source is packed integer Word and destination is packed
4952 * integer DWord, the source register is not incremented but the
4953 * source sub register is incremented."
4955 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4956 * restrictions. The code below intentionally doesn't check whether the
4957 * destination type is integer because empirically the hardware doesn't
4958 * seem to care what the actual type is as long as it's dword-aligned.
4960 if (devinfo
->gen
< 8) {
4961 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4962 /* IVB implements DF scalars as <0;2,1> regions. */
4963 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
4964 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
4965 const bool is_packed_word_exception
=
4966 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4967 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
4969 if (inst
->size_written
> REG_SIZE
&&
4970 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
4971 !is_scalar_exception
&& !is_packed_word_exception
) {
4972 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4973 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4978 /* From the IVB PRMs:
4979 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4980 * are applied for both halves of the SIMD32 instruction. If different
4981 * execution mask channels are required, split the instruction into two
4982 * SIMD16 instructions."
4984 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4985 * 32-wide control flow support in hardware and will behave similarly.
4987 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4988 max_width
= MIN2(max_width
, 16);
4990 /* From the IVB PRMs (applies to HSW too):
4991 * "Instructions with condition modifiers must not use SIMD32."
4993 * From the BDW PRMs (applies to later hardware too):
4994 * "Ternary instruction with condition modifiers must not use SIMD32."
4996 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4997 max_width
= MIN2(max_width
, 16);
4999 /* From the IVB PRMs (applies to other devices that don't have the
5000 * gen_device_info::supports_simd16_3src flag set):
5001 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
5002 * SIMD8 is not allowed for DF operations."
5004 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
5005 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
5007 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
5008 * the 8-bit quarter of the execution mask signals specified in the
5009 * instruction control fields) for the second compressed half of any
5010 * single-precision instruction (for double-precision instructions
5011 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
5012 * the EU will apply the wrong execution controls for the second
5013 * sequential GRF write if the number of channels per GRF is not exactly
5014 * eight in single-precision mode (or four in double-float mode).
5016 * In this situation we calculate the maximum size of the split
5017 * instructions so they only ever write to a single register.
5019 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
5020 !inst
->force_writemask_all
) {
5021 const unsigned channels_per_grf
= inst
->exec_size
/
5022 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
5023 const unsigned exec_type_size
= get_exec_type_size(inst
);
5024 assert(exec_type_size
);
5026 /* The hardware shifts exactly 8 channels per compressed half of the
5027 * instruction in single-precision mode and exactly 4 in double-precision.
5029 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
5030 max_width
= MIN2(max_width
, channels_per_grf
);
5032 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
5033 * because HW applies the same channel enable signals to both halves of
5034 * the compressed instruction which will be just wrong under
5035 * non-uniform control flow.
5037 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
5038 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
5039 max_width
= MIN2(max_width
, 4);
5042 /* Only power-of-two execution sizes are representable in the instruction
5045 return 1 << _mesa_logbase2(max_width
);
5049 * Get the maximum allowed SIMD width for instruction \p inst accounting for
5050 * various payload size restrictions that apply to sampler message
5053 * This is only intended to provide a maximum theoretical bound for the
5054 * execution size of the message based on the number of argument components
5055 * alone, which in most cases will determine whether the SIMD8 or SIMD16
5056 * variant of the message can be used, though some messages may have
5057 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
5058 * the message length to determine the exact SIMD width and argument count,
5059 * which makes a number of sampler message combinations impossible to
5063 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
5064 const fs_inst
*inst
)
5066 /* Calculate the number of coordinate components that have to be present
5067 * assuming that additional arguments follow the texel coordinates in the
5068 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
5069 * need to pad to four or three components depending on the message,
5070 * pre-ILK we need to pad to at most three components.
5072 const unsigned req_coord_components
=
5073 (devinfo
->gen
>= 7 ||
5074 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
5075 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
5076 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
5079 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
5080 * variant of the TXL or TXF message.
5082 const bool implicit_lod
= devinfo
->gen
>= 9 &&
5083 (inst
->opcode
== SHADER_OPCODE_TXL
||
5084 inst
->opcode
== SHADER_OPCODE_TXF
) &&
5085 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
5087 /* Calculate the total number of argument components that need to be passed
5088 * to the sampler unit.
5090 const unsigned num_payload_components
=
5091 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
5092 req_coord_components
) +
5093 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
5094 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
5095 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
5096 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
5097 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
5098 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
5099 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
5101 /* SIMD16 messages with more than five arguments exceed the maximum message
5102 * size supported by the sampler, regardless of whether a header is
5105 return MIN2(inst
->exec_size
,
5106 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
5110 * Get the closest native SIMD width supported by the hardware for instruction
5111 * \p inst. The instruction will be left untouched by
5112 * fs_visitor::lower_simd_width() if the returned value is equal to the
5113 * original execution size.
5116 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
5117 const fs_inst
*inst
)
5119 switch (inst
->opcode
) {
5120 case BRW_OPCODE_MOV
:
5121 case BRW_OPCODE_SEL
:
5122 case BRW_OPCODE_NOT
:
5123 case BRW_OPCODE_AND
:
5125 case BRW_OPCODE_XOR
:
5126 case BRW_OPCODE_SHR
:
5127 case BRW_OPCODE_SHL
:
5128 case BRW_OPCODE_ASR
:
5129 case BRW_OPCODE_CMPN
:
5130 case BRW_OPCODE_CSEL
:
5131 case BRW_OPCODE_F32TO16
:
5132 case BRW_OPCODE_F16TO32
:
5133 case BRW_OPCODE_BFREV
:
5134 case BRW_OPCODE_BFE
:
5135 case BRW_OPCODE_ADD
:
5136 case BRW_OPCODE_MUL
:
5137 case BRW_OPCODE_AVG
:
5138 case BRW_OPCODE_FRC
:
5139 case BRW_OPCODE_RNDU
:
5140 case BRW_OPCODE_RNDD
:
5141 case BRW_OPCODE_RNDE
:
5142 case BRW_OPCODE_RNDZ
:
5143 case BRW_OPCODE_LZD
:
5144 case BRW_OPCODE_FBH
:
5145 case BRW_OPCODE_FBL
:
5146 case BRW_OPCODE_CBIT
:
5147 case BRW_OPCODE_SAD2
:
5148 case BRW_OPCODE_MAD
:
5149 case BRW_OPCODE_LRP
:
5150 case FS_OPCODE_PACK
:
5151 case SHADER_OPCODE_SEL_EXEC
:
5152 case SHADER_OPCODE_CLUSTER_BROADCAST
:
5153 return get_fpu_lowered_simd_width(devinfo
, inst
);
5155 case BRW_OPCODE_CMP
: {
5156 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
5157 * when the destination is a GRF the dependency-clear bit on the flag
5158 * register is cleared early.
5160 * Suggested workarounds are to disable coissuing CMP instructions
5161 * or to split CMP(16) instructions into two CMP(8) instructions.
5163 * We choose to split into CMP(8) instructions since disabling
5164 * coissuing would affect CMP instructions not otherwise affected by
5167 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
5168 !inst
->dst
.is_null() ? 8 : ~0);
5169 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
5171 case BRW_OPCODE_BFI1
:
5172 case BRW_OPCODE_BFI2
:
5173 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
5175 * "Force BFI instructions to be executed always in SIMD8."
5177 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
5178 get_fpu_lowered_simd_width(devinfo
, inst
));
5181 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
5182 return inst
->exec_size
;
5184 case SHADER_OPCODE_RCP
:
5185 case SHADER_OPCODE_RSQ
:
5186 case SHADER_OPCODE_SQRT
:
5187 case SHADER_OPCODE_EXP2
:
5188 case SHADER_OPCODE_LOG2
:
5189 case SHADER_OPCODE_SIN
:
5190 case SHADER_OPCODE_COS
:
5191 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
5194 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
5195 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
5196 MIN2(8, inst
->exec_size
));
5198 case SHADER_OPCODE_POW
:
5199 /* SIMD16 is only allowed on Gen7+. */
5200 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
5201 MIN2(8, inst
->exec_size
));
5203 case SHADER_OPCODE_INT_QUOTIENT
:
5204 case SHADER_OPCODE_INT_REMAINDER
:
5205 /* Integer division is limited to SIMD8 on all generations. */
5206 return MIN2(8, inst
->exec_size
);
5208 case FS_OPCODE_LINTERP
:
5209 case SHADER_OPCODE_GET_BUFFER_SIZE
:
5210 case FS_OPCODE_DDX_COARSE
:
5211 case FS_OPCODE_DDX_FINE
:
5212 case FS_OPCODE_DDY_COARSE
:
5213 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
5214 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
5215 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
5216 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
5217 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
5218 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
5219 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
5220 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
5221 return MIN2(16, inst
->exec_size
);
5223 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5224 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
5225 * message used to implement varying pull constant loads, so expand it
5226 * to SIMD16. An alternative with longer message payload length but
5227 * shorter return payload would be to use the SIMD8 sampler message that
5228 * takes (header, u, v, r) as parameters instead of (header, u).
5230 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
5232 case FS_OPCODE_DDY_FINE
:
5233 /* The implementation of this virtual opcode may require emitting
5234 * compressed Align16 instructions, which are severely limited on some
5237 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
5238 * Region Restrictions):
5240 * "In Align16 access mode, SIMD16 is not allowed for DW operations
5241 * and SIMD8 is not allowed for DF operations."
5243 * In this context, "DW operations" means "operations acting on 32-bit
5244 * values", so it includes operations on floats.
5246 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
5247 * (Instruction Compression -> Rules and Restrictions):
5249 * "A compressed instruction must be in Align1 access mode. Align16
5250 * mode instructions cannot be compressed."
5252 * Similar text exists in the g45 PRM.
5254 * Empirically, compressed align16 instructions using odd register
5255 * numbers don't appear to work on Sandybridge either.
5257 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
5258 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
5259 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
5261 case SHADER_OPCODE_MULH
:
5262 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
5263 * is 8-wide on Gen7+.
5265 return (devinfo
->gen
>= 7 ? 8 :
5266 get_fpu_lowered_simd_width(devinfo
, inst
));
5268 case FS_OPCODE_FB_WRITE_LOGICAL
:
5269 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
5272 assert(devinfo
->gen
!= 6 ||
5273 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
5274 inst
->exec_size
== 8);
5275 /* Dual-source FB writes are unsupported in SIMD16 mode. */
5276 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
5277 8 : MIN2(16, inst
->exec_size
));
5279 case FS_OPCODE_FB_READ_LOGICAL
:
5280 return MIN2(16, inst
->exec_size
);
5282 case SHADER_OPCODE_TEX_LOGICAL
:
5283 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5284 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5285 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5286 case SHADER_OPCODE_LOD_LOGICAL
:
5287 case SHADER_OPCODE_TG4_LOGICAL
:
5288 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5289 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5290 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5291 return get_sampler_lowered_simd_width(devinfo
, inst
);
5293 case SHADER_OPCODE_TXD_LOGICAL
:
5294 /* TXD is unsupported in SIMD16 mode. */
5297 case SHADER_OPCODE_TXL_LOGICAL
:
5298 case FS_OPCODE_TXB_LOGICAL
:
5299 /* Only one execution size is representable pre-ILK depending on whether
5300 * the shadow reference argument is present.
5302 if (devinfo
->gen
== 4)
5303 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
5305 return get_sampler_lowered_simd_width(devinfo
, inst
);
5307 case SHADER_OPCODE_TXF_LOGICAL
:
5308 case SHADER_OPCODE_TXS_LOGICAL
:
5309 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
5310 * messages. Use SIMD16 instead.
5312 if (devinfo
->gen
== 4)
5315 return get_sampler_lowered_simd_width(devinfo
, inst
);
5317 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5318 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5319 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5322 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5323 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5324 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5325 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5326 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5327 return MIN2(16, inst
->exec_size
);
5329 case SHADER_OPCODE_URB_READ_SIMD8
:
5330 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
5331 case SHADER_OPCODE_URB_WRITE_SIMD8
:
5332 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
5333 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
5334 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
5335 return MIN2(8, inst
->exec_size
);
5337 case SHADER_OPCODE_QUAD_SWIZZLE
:
5340 case SHADER_OPCODE_MOV_INDIRECT
: {
5341 /* From IVB and HSW PRMs:
5343 * "2.When the destination requires two registers and the sources are
5344 * indirect, the sources must use 1x1 regioning mode.
5346 * In case of DF instructions in HSW/IVB, the exec_size is limited by
5347 * the EU decompression logic not handling VxH indirect addressing
5350 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
5351 /* Prior to Broadwell, we only have 8 address subregisters. */
5352 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
5353 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
5357 case SHADER_OPCODE_LOAD_PAYLOAD
: {
5358 const unsigned reg_count
=
5359 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5361 if (reg_count
> 2) {
5362 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5363 * can be easily lowered (which excludes headers and heterogeneous
5366 assert(!inst
->header_size
);
5367 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5368 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5369 inst
->src
[i
].file
== BAD_FILE
);
5371 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5373 return inst
->exec_size
;
5377 return inst
->exec_size
;
5382 * Return true if splitting out the group of channels of instruction \p inst
5383 * given by lbld.group() requires allocating a temporary for the i-th source
5384 * of the lowered instruction.
5387 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5389 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5390 (inst
->components_read(i
) == 1 &&
5391 lbld
.dispatch_width() <= inst
->exec_size
)) ||
5392 (inst
->flags_written() &
5393 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
5397 * Extract the data that would be consumed by the channel group given by
5398 * lbld.group() from the i-th source region of instruction \p inst and return
5399 * it as result in packed form.
5402 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
5404 /* Specified channel group from the source region. */
5405 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5407 if (needs_src_copy(lbld
, inst
, i
)) {
5408 /* Builder of the right width to perform the copy avoiding uninitialized
5409 * data if the lowered execution size is greater than the original
5410 * execution size of the instruction.
5412 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5413 inst
->exec_size
), 0);
5414 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5416 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5417 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5421 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5422 /* The source is invariant for all dispatch_width-wide groups of the
5425 return inst
->src
[i
];
5428 /* We can just point the lowered instruction at the right channel group
5429 * from the original region.
5436 * Return true if splitting out the group of channels of instruction \p inst
5437 * given by lbld.group() requires allocating a temporary for the destination
5438 * of the lowered instruction and copying the data back to the original
5439 * destination region.
5442 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5444 /* If the instruction writes more than one component we'll have to shuffle
5445 * the results of multiple lowered instructions in order to make sure that
5446 * they end up arranged correctly in the original destination region.
5448 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5451 /* If the lowered execution size is larger than the original the result of
5452 * the instruction won't fit in the original destination, so we'll have to
5453 * allocate a temporary in any case.
5455 if (lbld
.dispatch_width() > inst
->exec_size
)
5458 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5459 /* If we already made a copy of the source for other reasons there won't
5460 * be any overlap with the destination.
5462 if (needs_src_copy(lbld
, inst
, i
))
5465 /* In order to keep the logic simple we emit a copy whenever the
5466 * destination region doesn't exactly match an overlapping source, which
5467 * may point at the source and destination not being aligned group by
5468 * group which could cause one of the lowered instructions to overwrite
5469 * the data read from the same source by other lowered instructions.
5471 if (regions_overlap(inst
->dst
, inst
->size_written
,
5472 inst
->src
[i
], inst
->size_read(i
)) &&
5473 !inst
->dst
.equals(inst
->src
[i
]))
5481 * Insert data from a packed temporary into the channel group given by
5482 * lbld.group() of the destination region of instruction \p inst and return
5483 * the temporary as result. Any copy instructions that are required for
5484 * unzipping the previous value (in the case of partial writes) will be
5485 * inserted using \p lbld_before and any copy instructions required for
5486 * zipping up the destination of \p inst will be inserted using \p lbld_after.
5489 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
5492 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
5493 assert(lbld_before
.group() == lbld_after
.group());
5495 /* Specified channel group from the destination region. */
5496 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group());
5497 const unsigned dst_size
= inst
->size_written
/
5498 inst
->dst
.component_size(inst
->exec_size
);
5500 if (needs_dst_copy(lbld_after
, inst
)) {
5501 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
5503 if (inst
->predicate
) {
5504 /* Handle predication by copying the original contents of
5505 * the destination into the temporary before emitting the
5506 * lowered instruction.
5508 const fs_builder gbld_before
=
5509 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
5510 inst
->exec_size
), 0);
5511 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5512 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
5513 offset(dst
, inst
->exec_size
, k
));
5517 const fs_builder gbld_after
=
5518 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
5519 inst
->exec_size
), 0);
5520 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5521 /* Use a builder of the right width to perform the copy avoiding
5522 * uninitialized data if the lowered execution size is greater than
5523 * the original execution size of the instruction.
5525 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
5526 offset(tmp
, lbld_after
, k
));
5532 /* No need to allocate a temporary for the lowered instruction, just
5533 * take the right group of channels from the original region.
5540 fs_visitor::lower_simd_width()
5542 bool progress
= false;
5544 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5545 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5547 if (lower_width
!= inst
->exec_size
) {
5548 /* Builder matching the original instruction. We may also need to
5549 * emit an instruction of width larger than the original, set the
5550 * execution size of the builder to the highest of both for now so
5551 * we're sure that both cases can be handled.
5553 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5554 const fs_builder ibld
= bld
.at(block
, inst
)
5555 .exec_all(inst
->force_writemask_all
)
5556 .group(max_width
, inst
->group
/ max_width
);
5558 /* Split the copies in chunks of the execution width of either the
5559 * original or the lowered instruction, whichever is lower.
5561 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5562 const unsigned dst_size
= inst
->size_written
/
5563 inst
->dst
.component_size(inst
->exec_size
);
5565 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5567 /* Inserting the zip, unzip, and duplicated instructions in all of
5568 * the right spots is somewhat tricky. All of the unzip and any
5569 * instructions from the zip which unzip the destination prior to
5570 * writing need to happen before all of the per-group instructions
5571 * and the zip instructions need to happen after. In order to sort
5572 * this all out, we insert the unzip instructions before \p inst,
5573 * insert the per-group instructions after \p inst (i.e. before
5574 * inst->next), and insert the zip instructions before the
5575 * instruction after \p inst. Since we are inserting instructions
5576 * after \p inst, inst->next is a moving target and we need to save
5577 * it off here so that we insert the zip instructions in the right
5580 exec_node
*const after_inst
= inst
->next
;
5581 for (unsigned i
= 0; i
< n
; i
++) {
5582 /* Emit a copy of the original instruction with the lowered width.
5583 * If the EOT flag was set throw it away except for the last
5584 * instruction to avoid killing the thread prematurely.
5586 fs_inst split_inst
= *inst
;
5587 split_inst
.exec_size
= lower_width
;
5588 split_inst
.eot
= inst
->eot
&& i
== 0;
5590 /* Select the correct channel enables for the i-th group, then
5591 * transform the sources and destination and emit the lowered
5594 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5596 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5597 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
5599 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
5600 lbld
.at(block
, after_inst
), inst
);
5601 split_inst
.size_written
=
5602 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5604 lbld
.at(block
, inst
->next
).emit(split_inst
);
5607 inst
->remove(block
);
5613 invalidate_live_intervals();
5619 fs_visitor::dump_instructions()
5621 dump_instructions(NULL
);
5625 fs_visitor::dump_instructions(const char *name
)
5627 FILE *file
= stderr
;
5628 if (name
&& geteuid() != 0) {
5629 file
= fopen(name
, "w");
5635 calculate_register_pressure();
5636 int ip
= 0, max_pressure
= 0;
5637 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5638 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5639 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5640 dump_instruction(inst
, file
);
5643 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5646 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5647 fprintf(file
, "%4d: ", ip
++);
5648 dump_instruction(inst
, file
);
5652 if (file
!= stderr
) {
5658 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5660 dump_instruction(be_inst
, stderr
);
5664 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5666 fs_inst
*inst
= (fs_inst
*)be_inst
;
5668 if (inst
->predicate
) {
5669 fprintf(file
, "(%cf%d.%d) ",
5670 inst
->predicate_inverse
? '-' : '+',
5671 inst
->flag_subreg
/ 2,
5672 inst
->flag_subreg
% 2);
5675 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5677 fprintf(file
, ".sat");
5678 if (inst
->conditional_mod
) {
5679 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5680 if (!inst
->predicate
&&
5681 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5682 inst
->opcode
!= BRW_OPCODE_CSEL
&&
5683 inst
->opcode
!= BRW_OPCODE_IF
&&
5684 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5685 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
5686 inst
->flag_subreg
% 2);
5689 fprintf(file
, "(%d) ", inst
->exec_size
);
5692 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5696 fprintf(file
, "(EOT) ");
5699 switch (inst
->dst
.file
) {
5701 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5704 fprintf(file
, "g%d", inst
->dst
.nr
);
5707 fprintf(file
, "m%d", inst
->dst
.nr
);
5710 fprintf(file
, "(null)");
5713 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5716 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5719 switch (inst
->dst
.nr
) {
5721 fprintf(file
, "null");
5723 case BRW_ARF_ADDRESS
:
5724 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5726 case BRW_ARF_ACCUMULATOR
:
5727 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5730 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5733 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5738 unreachable("not reached");
5741 if (inst
->dst
.offset
||
5742 (inst
->dst
.file
== VGRF
&&
5743 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5744 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5745 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5746 inst
->dst
.offset
% reg_size
);
5749 if (inst
->dst
.stride
!= 1)
5750 fprintf(file
, "<%u>", inst
->dst
.stride
);
5751 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
5753 for (int i
= 0; i
< inst
->sources
; i
++) {
5754 if (inst
->src
[i
].negate
)
5756 if (inst
->src
[i
].abs
)
5758 switch (inst
->src
[i
].file
) {
5760 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5763 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5766 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5769 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5772 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5775 fprintf(file
, "(null)");
5778 switch (inst
->src
[i
].type
) {
5779 case BRW_REGISTER_TYPE_F
:
5780 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5782 case BRW_REGISTER_TYPE_DF
:
5783 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5785 case BRW_REGISTER_TYPE_W
:
5786 case BRW_REGISTER_TYPE_D
:
5787 fprintf(file
, "%dd", inst
->src
[i
].d
);
5789 case BRW_REGISTER_TYPE_UW
:
5790 case BRW_REGISTER_TYPE_UD
:
5791 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5793 case BRW_REGISTER_TYPE_VF
:
5794 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5795 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5796 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5797 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5798 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5801 fprintf(file
, "???");
5806 switch (inst
->src
[i
].nr
) {
5808 fprintf(file
, "null");
5810 case BRW_ARF_ADDRESS
:
5811 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5813 case BRW_ARF_ACCUMULATOR
:
5814 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5817 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5820 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5826 if (inst
->src
[i
].offset
||
5827 (inst
->src
[i
].file
== VGRF
&&
5828 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5829 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5830 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5831 inst
->src
[i
].offset
% reg_size
);
5834 if (inst
->src
[i
].abs
)
5837 if (inst
->src
[i
].file
!= IMM
) {
5839 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5840 unsigned hstride
= inst
->src
[i
].hstride
;
5841 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5843 stride
= inst
->src
[i
].stride
;
5846 fprintf(file
, "<%u>", stride
);
5848 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
5851 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5852 fprintf(file
, ", ");
5857 if (inst
->force_writemask_all
)
5858 fprintf(file
, "NoMask ");
5860 if (inst
->exec_size
!= dispatch_width
)
5861 fprintf(file
, "group%d ", inst
->group
);
5863 fprintf(file
, "\n");
5867 * Possibly returns an instruction that set up @param reg.
5869 * Sometimes we want to take the result of some expression/variable
5870 * dereference tree and rewrite the instruction generating the result
5871 * of the tree. When processing the tree, we know that the
5872 * instructions generated are all writing temporaries that are dead
5873 * outside of this tree. So, if we have some instructions that write
5874 * a temporary, we're free to point that temp write somewhere else.
5876 * Note that this doesn't guarantee that the instruction generated
5877 * only reg -- it might be the size=4 destination of a texture instruction.
5880 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5885 end
->is_partial_write() ||
5886 !reg
.equals(end
->dst
)) {
5894 fs_visitor::setup_fs_payload_gen6()
5896 assert(stage
== MESA_SHADER_FRAGMENT
);
5897 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
5899 assert(devinfo
->gen
>= 6);
5901 /* R0-1: masks, pixel X/Y coordinates. */
5902 payload
.num_regs
= 2;
5903 /* R2: only for 32-pixel dispatch.*/
5905 /* R3-26: barycentric interpolation coordinates. These appear in the
5906 * same order that they appear in the brw_barycentric_mode
5907 * enum. Each set of coordinates occupies 2 registers if dispatch width
5908 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5909 * appear if they were enabled using the "Barycentric Interpolation
5910 * Mode" bits in WM_STATE.
5912 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5913 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
5914 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5915 payload
.num_regs
+= 2;
5916 if (dispatch_width
== 16) {
5917 payload
.num_regs
+= 2;
5922 /* R27: interpolated depth if uses source depth */
5923 prog_data
->uses_src_depth
=
5924 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5925 if (prog_data
->uses_src_depth
) {
5926 payload
.source_depth_reg
= payload
.num_regs
;
5928 if (dispatch_width
== 16) {
5929 /* R28: interpolated depth if not SIMD8. */
5934 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5935 prog_data
->uses_src_w
=
5936 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5937 if (prog_data
->uses_src_w
) {
5938 payload
.source_w_reg
= payload
.num_regs
;
5940 if (dispatch_width
== 16) {
5941 /* R30: interpolated W if not SIMD8. */
5946 /* R31: MSAA position offsets. */
5947 if (prog_data
->persample_dispatch
&&
5948 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5949 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5951 * "MSDISPMODE_PERSAMPLE is required in order to select
5954 * So we can only really get sample positions if we are doing real
5955 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5956 * persample dispatch, we hard-code it to 0.5.
5958 prog_data
->uses_pos_offset
= true;
5959 payload
.sample_pos_reg
= payload
.num_regs
;
5963 /* R32: MSAA input coverage mask */
5964 prog_data
->uses_sample_mask
=
5965 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5966 if (prog_data
->uses_sample_mask
) {
5967 assert(devinfo
->gen
>= 7);
5968 payload
.sample_mask_in_reg
= payload
.num_regs
;
5970 if (dispatch_width
== 16) {
5971 /* R33: input coverage mask if not SIMD8. */
5976 /* R34-: bary for 32-pixel. */
5977 /* R58-59: interp W for 32-pixel. */
5979 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5980 source_depth_to_render_target
= true;
5985 fs_visitor::setup_vs_payload()
5987 /* R0: thread header, R1: urb handles */
5988 payload
.num_regs
= 2;
5992 fs_visitor::setup_gs_payload()
5994 assert(stage
== MESA_SHADER_GEOMETRY
);
5996 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
5997 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
5999 /* R0: thread header, R1: output URB handles */
6000 payload
.num_regs
= 2;
6002 if (gs_prog_data
->include_primitive_id
) {
6003 /* R2: Primitive ID 0..7 */
6007 /* Always enable VUE handles so we can safely use pull model if needed.
6009 * The push model for a GS uses a ton of register space even for trivial
6010 * scenarios with just a few inputs, so just make things easier and a bit
6011 * safer by always having pull model available.
6013 gs_prog_data
->base
.include_vue_handles
= true;
6015 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
6016 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
6018 /* Use a maximum of 24 registers for push-model inputs. */
6019 const unsigned max_push_components
= 24;
6021 /* If pushing our inputs would take too many registers, reduce the URB read
6022 * length (which is in HWords, or 8 registers), and resort to pulling.
6024 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
6025 * have to multiply by VerticesIn to obtain the total storage requirement.
6027 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
6028 max_push_components
) {
6029 vue_prog_data
->urb_read_length
=
6030 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
6035 fs_visitor::setup_cs_payload()
6037 assert(devinfo
->gen
>= 7);
6038 payload
.num_regs
= 1;
6042 fs_visitor::calculate_register_pressure()
6044 invalidate_live_intervals();
6045 calculate_live_intervals();
6047 unsigned num_instructions
= 0;
6048 foreach_block(block
, cfg
)
6049 num_instructions
+= block
->instructions
.length();
6051 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
6053 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
6054 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
6055 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
6060 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
6062 * The needs_unlit_centroid_workaround ends up producing one of these per
6063 * channel of centroid input, so it's good to clean them up.
6065 * An assumption here is that nothing ever modifies the dispatched pixels
6066 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
6067 * dictates that anyway.
6070 fs_visitor::opt_drop_redundant_mov_to_flags()
6072 bool flag_mov_found
[4] = {false};
6073 bool progress
= false;
6075 /* Instructions removed by this pass can only be added if this were true */
6076 if (!devinfo
->needs_unlit_centroid_workaround
)
6079 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6080 if (inst
->is_control_flow()) {
6081 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
6082 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
6083 if (!flag_mov_found
[inst
->flag_subreg
]) {
6084 flag_mov_found
[inst
->flag_subreg
] = true;
6086 inst
->remove(block
);
6089 } else if (inst
->flags_written()) {
6090 flag_mov_found
[inst
->flag_subreg
] = false;
6098 fs_visitor::optimize()
6100 /* Start by validating the shader we currently have. */
6103 /* bld is the common builder object pointing at the end of the program we
6104 * used to translate it into i965 IR. For the optimization and lowering
6105 * passes coming next, any code added after the end of the program without
6106 * having explicitly called fs_builder::at() clearly points at a mistake.
6107 * Ideally optimization passes wouldn't be part of the visitor so they
6108 * wouldn't have access to bld at all, but they do, so just in case some
6109 * pass forgets to ask for a location explicitly set it to NULL here to
6110 * make it trip. The dispatch width is initialized to a bogus value to
6111 * make sure that optimizations set the execution controls explicitly to
6112 * match the code they are manipulating instead of relying on the defaults.
6114 bld
= fs_builder(this, 64);
6116 assign_constant_locations();
6117 lower_constant_loads();
6121 split_virtual_grfs();
6124 #define OPT(pass, args...) ({ \
6126 bool this_progress = pass(args); \
6128 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
6129 char filename[64]; \
6130 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
6131 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
6133 backend_shader::dump_instructions(filename); \
6138 progress = progress || this_progress; \
6142 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
6144 snprintf(filename
, 64, "%s%d-%s-00-00-start",
6145 stage_abbrev
, dispatch_width
, nir
->info
.name
);
6147 backend_shader::dump_instructions(filename
);
6150 bool progress
= false;
6154 OPT(opt_drop_redundant_mov_to_flags
);
6155 OPT(remove_extra_rounding_modes
);
6162 OPT(remove_duplicate_mrf_writes
);
6166 OPT(opt_copy_propagation
);
6167 OPT(opt_predicated_break
, this);
6168 OPT(opt_cmod_propagation
);
6169 OPT(dead_code_eliminate
);
6170 OPT(opt_peephole_sel
);
6171 OPT(dead_control_flow_eliminate
, this);
6172 OPT(opt_register_renaming
);
6173 OPT(opt_saturate_propagation
);
6174 OPT(register_coalesce
);
6175 OPT(compute_to_mrf
);
6176 OPT(eliminate_find_live_channel
);
6178 OPT(compact_virtual_grfs
);
6181 /* Do this after cmod propagation has had every possible opportunity to
6182 * propagate results into SEL instructions.
6184 if (OPT(opt_peephole_csel
))
6185 OPT(dead_code_eliminate
);
6190 if (OPT(lower_pack
)) {
6191 OPT(register_coalesce
);
6192 OPT(dead_code_eliminate
);
6195 OPT(lower_simd_width
);
6197 /* After SIMD lowering just in case we had to unroll the EOT send. */
6198 OPT(opt_sampler_eot
);
6200 OPT(lower_logical_sends
);
6203 OPT(opt_copy_propagation
);
6204 /* Only run after logical send lowering because it's easier to implement
6205 * in terms of physical sends.
6207 if (OPT(opt_zero_samples
))
6208 OPT(opt_copy_propagation
);
6209 /* Run after logical send lowering to give it a chance to CSE the
6210 * LOAD_PAYLOAD instructions created to construct the payloads of
6211 * e.g. texturing messages in cases where it wasn't possible to CSE the
6212 * whole logical instruction.
6215 OPT(register_coalesce
);
6216 OPT(compute_to_mrf
);
6217 OPT(dead_code_eliminate
);
6218 OPT(remove_duplicate_mrf_writes
);
6219 OPT(opt_peephole_sel
);
6222 OPT(opt_redundant_discard_jumps
);
6224 if (OPT(lower_load_payload
)) {
6225 split_virtual_grfs();
6226 OPT(register_coalesce
);
6227 OPT(compute_to_mrf
);
6228 OPT(dead_code_eliminate
);
6231 OPT(opt_combine_constants
);
6232 OPT(lower_integer_multiplication
);
6234 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
6235 OPT(opt_cmod_propagation
);
6237 OPT(opt_copy_propagation
);
6238 OPT(dead_code_eliminate
);
6241 if (OPT(lower_conversions
)) {
6242 OPT(opt_copy_propagation
);
6243 OPT(dead_code_eliminate
);
6244 OPT(lower_simd_width
);
6247 lower_uniform_pull_constant_loads();
6253 * Three source instruction must have a GRF/MRF destination register.
6254 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
6257 fs_visitor::fixup_3src_null_dest()
6259 bool progress
= false;
6261 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
6262 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
6263 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
6270 invalidate_live_intervals();
6274 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
6276 bool allocated_without_spills
;
6278 static const enum instruction_scheduler_mode pre_modes
[] = {
6280 SCHEDULE_PRE_NON_LIFO
,
6284 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
6286 /* Try each scheduling heuristic to see if it can successfully register
6287 * allocate without spilling. They should be ordered by decreasing
6288 * performance but increasing likelihood of allocating.
6290 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
6291 schedule_instructions(pre_modes
[i
]);
6294 assign_regs_trivial();
6295 allocated_without_spills
= true;
6297 allocated_without_spills
= assign_regs(false, spill_all
);
6299 if (allocated_without_spills
)
6303 if (!allocated_without_spills
) {
6304 if (!allow_spilling
)
6305 fail("Failure to register allocate and spilling is not allowed.");
6307 /* We assume that any spilling is worse than just dropping back to
6308 * SIMD8. There's probably actually some intermediate point where
6309 * SIMD16 with a couple of spills is still better.
6311 if (dispatch_width
> min_dispatch_width
) {
6312 fail("Failure to register allocate. Reduce number of "
6313 "live scalar values to avoid this.");
6315 compiler
->shader_perf_log(log_data
,
6316 "%s shader triggered register spilling. "
6317 "Try reducing the number of live scalar "
6318 "values to improve performance.\n",
6322 /* Since we're out of heuristics, just go spill registers until we
6323 * get an allocation.
6325 while (!assign_regs(true, spill_all
)) {
6331 /* This must come after all optimization and register allocation, since
6332 * it inserts dead code that happens to have side effects, and it does
6333 * so based on the actual physical registers in use.
6335 insert_gen4_send_dependency_workarounds();
6340 opt_bank_conflicts();
6342 schedule_instructions(SCHEDULE_POST
);
6344 if (last_scratch
> 0) {
6345 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
6347 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
6349 if (stage
== MESA_SHADER_COMPUTE
) {
6350 if (devinfo
->is_haswell
) {
6351 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
6352 * field documentation, Haswell supports a minimum of 2kB of
6353 * scratch space for compute shaders, unlike every other stage
6356 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
6357 } else if (devinfo
->gen
<= 7) {
6358 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
6359 * field documentation, platforms prior to Haswell measure scratch
6360 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
6362 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
6363 max_scratch_size
= 12 * 1024;
6367 /* We currently only support up to 2MB of scratch space. If we
6368 * need to support more eventually, the documentation suggests
6369 * that we could allocate a larger buffer, and partition it out
6370 * ourselves. We'd just have to undo the hardware's address
6371 * calculation by subtracting (FFTID * Per Thread Scratch Space)
6372 * and then add FFTID * (Larger Per Thread Scratch Space).
6374 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
6375 * Thread Group Tracking > Local Memory/Scratch Space.
6377 assert(prog_data
->total_scratch
< max_scratch_size
);
6382 fs_visitor::run_vs()
6384 assert(stage
== MESA_SHADER_VERTEX
);
6388 if (shader_time_index
>= 0)
6389 emit_shader_time_begin();
6396 compute_clip_distance();
6400 if (shader_time_index
>= 0)
6401 emit_shader_time_end();
6407 assign_curb_setup();
6408 assign_vs_urb_setup();
6410 fixup_3src_null_dest();
6411 allocate_registers(8, true);
6417 fs_visitor::run_tcs_single_patch()
6419 assert(stage
== MESA_SHADER_TESS_CTRL
);
6421 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
6423 /* r1-r4 contain the ICP handles. */
6424 payload
.num_regs
= 5;
6426 if (shader_time_index
>= 0)
6427 emit_shader_time_begin();
6429 /* Initialize gl_InvocationID */
6430 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6431 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6432 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6433 bld
.MOV(channels_ud
, channels_uw
);
6435 if (tcs_prog_data
->instances
== 1) {
6436 invocation_id
= channels_ud
;
6438 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6440 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6441 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6442 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6443 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6444 brw_imm_ud(INTEL_MASK(23, 17)));
6445 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6447 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6450 /* Fix the disptach mask */
6451 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6452 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6453 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
6454 bld
.IF(BRW_PREDICATE_NORMAL
);
6459 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6460 bld
.emit(BRW_OPCODE_ENDIF
);
6463 /* Emit EOT write; set TR DS Cache bit */
6465 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6466 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6467 fs_reg(brw_imm_ud(0)),
6469 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6470 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6472 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6473 bld
.null_reg_ud(), payload
);
6477 if (shader_time_index
>= 0)
6478 emit_shader_time_end();
6487 assign_curb_setup();
6488 assign_tcs_single_patch_urb_setup();
6490 fixup_3src_null_dest();
6491 allocate_registers(8, true);
6497 fs_visitor::run_tes()
6499 assert(stage
== MESA_SHADER_TESS_EVAL
);
6501 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6502 payload
.num_regs
= 5;
6504 if (shader_time_index
>= 0)
6505 emit_shader_time_begin();
6514 if (shader_time_index
>= 0)
6515 emit_shader_time_end();
6521 assign_curb_setup();
6522 assign_tes_urb_setup();
6524 fixup_3src_null_dest();
6525 allocate_registers(8, true);
6531 fs_visitor::run_gs()
6533 assert(stage
== MESA_SHADER_GEOMETRY
);
6537 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6539 if (gs_compile
->control_data_header_size_bits
> 0) {
6540 /* Create a VGRF to store accumulated control data bits. */
6541 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6543 /* If we're outputting more than 32 control data bits, then EmitVertex()
6544 * will set control_data_bits to 0 after emitting the first vertex.
6545 * Otherwise, we need to initialize it to 0 here.
6547 if (gs_compile
->control_data_header_size_bits
<= 32) {
6548 const fs_builder abld
= bld
.annotate("initialize control data bits");
6549 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6553 if (shader_time_index
>= 0)
6554 emit_shader_time_begin();
6558 emit_gs_thread_end();
6560 if (shader_time_index
>= 0)
6561 emit_shader_time_end();
6570 assign_curb_setup();
6571 assign_gs_urb_setup();
6573 fixup_3src_null_dest();
6574 allocate_registers(8, true);
6579 /* From the SKL PRM, Volume 16, Workarounds:
6581 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
6582 * only header phases (R0-R2)
6584 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
6585 * have been header only.
6587 * Instead of enabling push constants one can alternatively enable one of the
6588 * inputs. Here one simply chooses "layer" which shouldn't impose much
6592 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
6594 if (wm_prog_data
->num_varying_inputs
)
6597 if (wm_prog_data
->base
.curb_read_length
)
6600 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
6601 wm_prog_data
->num_varying_inputs
= 1;
6605 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6607 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6608 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6610 assert(stage
== MESA_SHADER_FRAGMENT
);
6612 if (devinfo
->gen
>= 6)
6613 setup_fs_payload_gen6();
6615 setup_fs_payload_gen4();
6619 } else if (do_rep_send
) {
6620 assert(dispatch_width
== 16);
6621 emit_repclear_shader();
6623 if (shader_time_index
>= 0)
6624 emit_shader_time_begin();
6626 calculate_urb_setup();
6627 if (nir
->info
.inputs_read
> 0 ||
6628 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6629 if (devinfo
->gen
< 6)
6630 emit_interpolation_setup_gen4();
6632 emit_interpolation_setup_gen6();
6635 /* We handle discards by keeping track of the still-live pixels in f0.1.
6636 * Initialize it with the dispatched pixels.
6638 if (wm_prog_data
->uses_kill
) {
6639 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6640 discard_init
->flag_subreg
= 1;
6643 /* Generate FS IR for main(). (the visitor only descends into
6644 * functions called "main").
6651 if (wm_prog_data
->uses_kill
)
6652 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6654 if (wm_key
->alpha_test_func
)
6659 if (shader_time_index
>= 0)
6660 emit_shader_time_end();
6666 assign_curb_setup();
6668 if (devinfo
->gen
>= 9)
6669 gen9_ps_header_only_workaround(wm_prog_data
);
6673 fixup_3src_null_dest();
6674 allocate_registers(8, allow_spilling
);
6684 fs_visitor::run_cs(unsigned min_dispatch_width
)
6686 assert(stage
== MESA_SHADER_COMPUTE
);
6687 assert(dispatch_width
>= min_dispatch_width
);
6691 if (shader_time_index
>= 0)
6692 emit_shader_time_begin();
6694 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6695 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6696 const fs_builder abld
= bld
.exec_all().group(1, 0);
6697 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6698 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6706 emit_cs_terminate();
6708 if (shader_time_index
>= 0)
6709 emit_shader_time_end();
6715 assign_curb_setup();
6717 fixup_3src_null_dest();
6718 allocate_registers(min_dispatch_width
, true);
6727 * Return a bitfield where bit n is set if barycentric interpolation mode n
6728 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6730 * We examine the load_barycentric intrinsics rather than looking at input
6731 * variables so that we catch interpolateAtCentroid() messages too, which
6732 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6735 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6736 const nir_shader
*shader
)
6738 unsigned barycentric_interp_modes
= 0;
6740 nir_foreach_function(f
, shader
) {
6744 nir_foreach_block(block
, f
->impl
) {
6745 nir_foreach_instr(instr
, block
) {
6746 if (instr
->type
!= nir_instr_type_intrinsic
)
6749 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6750 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6753 /* Ignore WPOS; it doesn't require interpolation. */
6754 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6757 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6758 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6759 nir_intrinsic_interp_mode(intrin
);
6760 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6761 enum brw_barycentric_mode bary
=
6762 brw_barycentric_mode(interp
, bary_op
);
6764 barycentric_interp_modes
|= 1 << bary
;
6766 if (devinfo
->needs_unlit_centroid_workaround
&&
6767 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6768 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6773 return barycentric_interp_modes
;
6777 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6778 const nir_shader
*shader
)
6780 prog_data
->flat_inputs
= 0;
6782 nir_foreach_variable(var
, &shader
->inputs
) {
6783 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6785 if (input_index
< 0)
6789 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6790 prog_data
->flat_inputs
|= (1 << input_index
);
6795 computed_depth_mode(const nir_shader
*shader
)
6797 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6798 switch (shader
->info
.fs
.depth_layout
) {
6799 case FRAG_DEPTH_LAYOUT_NONE
:
6800 case FRAG_DEPTH_LAYOUT_ANY
:
6801 return BRW_PSCDEPTH_ON
;
6802 case FRAG_DEPTH_LAYOUT_GREATER
:
6803 return BRW_PSCDEPTH_ON_GE
;
6804 case FRAG_DEPTH_LAYOUT_LESS
:
6805 return BRW_PSCDEPTH_ON_LE
;
6806 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6807 return BRW_PSCDEPTH_OFF
;
6810 return BRW_PSCDEPTH_OFF
;
6814 * Move load_interpolated_input with simple (payload-based) barycentric modes
6815 * to the top of the program so we don't emit multiple PLNs for the same input.
6817 * This works around CSE not being able to handle non-dominating cases
6823 * interpolate the same exact input
6826 * This should be replaced by global value numbering someday.
6829 move_interpolation_to_top(nir_shader
*nir
)
6831 bool progress
= false;
6833 nir_foreach_function(f
, nir
) {
6837 nir_block
*top
= nir_start_block(f
->impl
);
6838 exec_node
*cursor_node
= NULL
;
6840 nir_foreach_block(block
, f
->impl
) {
6844 nir_foreach_instr_safe(instr
, block
) {
6845 if (instr
->type
!= nir_instr_type_intrinsic
)
6848 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6849 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6851 nir_intrinsic_instr
*bary_intrinsic
=
6852 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6853 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6855 /* Leave interpolateAtSample/Offset() where they are. */
6856 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6857 op
== nir_intrinsic_load_barycentric_at_offset
)
6860 nir_instr
*move
[3] = {
6861 &bary_intrinsic
->instr
,
6862 intrin
->src
[1].ssa
->parent_instr
,
6866 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6867 if (move
[i
]->block
!= top
) {
6868 move
[i
]->block
= top
;
6869 exec_node_remove(&move
[i
]->node
);
6871 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6873 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6875 cursor_node
= &move
[i
]->node
;
6881 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6882 ((unsigned) nir_metadata_block_index
|
6883 (unsigned) nir_metadata_dominance
));
6890 * Demote per-sample barycentric intrinsics to centroid.
6892 * Useful when rendering to a non-multisampled buffer.
6895 demote_sample_qualifiers(nir_shader
*nir
)
6897 bool progress
= true;
6899 nir_foreach_function(f
, nir
) {
6904 nir_builder_init(&b
, f
->impl
);
6906 nir_foreach_block(block
, f
->impl
) {
6907 nir_foreach_instr_safe(instr
, block
) {
6908 if (instr
->type
!= nir_instr_type_intrinsic
)
6911 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6912 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6913 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6916 b
.cursor
= nir_before_instr(instr
);
6917 nir_ssa_def
*centroid
=
6918 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6919 nir_intrinsic_interp_mode(intrin
));
6920 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6921 nir_src_for_ssa(centroid
));
6922 nir_instr_remove(instr
);
6927 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6928 ((unsigned) nir_metadata_block_index
|
6929 (unsigned) nir_metadata_dominance
));
6936 * Pre-gen6, the register file of the EUs was shared between threads,
6937 * and each thread used some subset allocated on a 16-register block
6938 * granularity. The unit states wanted these block counts.
6941 brw_register_blocks(int reg_count
)
6943 return ALIGN(reg_count
, 16) / 16 - 1;
6947 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6949 const struct brw_wm_prog_key
*key
,
6950 struct brw_wm_prog_data
*prog_data
,
6951 const nir_shader
*src_shader
,
6952 struct gl_program
*prog
,
6953 int shader_time_index8
, int shader_time_index16
,
6954 bool allow_spilling
,
6955 bool use_rep_send
, struct brw_vue_map
*vue_map
,
6958 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
6960 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6961 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6962 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
6963 brw_nir_lower_fs_outputs(shader
);
6965 if (devinfo
->gen
< 6) {
6966 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
, devinfo
);
6969 if (!key
->multisample_fbo
)
6970 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6971 NIR_PASS_V(shader
, move_interpolation_to_top
);
6972 shader
= brw_postprocess_nir(shader
, compiler
, true);
6974 /* key->alpha_test_func means simulating alpha testing via discards,
6975 * so the shader definitely kills pixels.
6977 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
6978 key
->alpha_test_func
;
6979 prog_data
->uses_omask
= key
->multisample_fbo
&&
6980 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6981 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6982 prog_data
->computed_stencil
=
6983 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6985 prog_data
->persample_dispatch
=
6986 key
->multisample_fbo
&&
6987 (key
->persample_interp
||
6988 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6989 SYSTEM_BIT_SAMPLE_POS
)) ||
6990 shader
->info
.fs
.uses_sample_qualifier
||
6991 shader
->info
.outputs_read
);
6993 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
6995 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6996 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
6997 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
6999 prog_data
->barycentric_interp_modes
=
7000 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
7002 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
7003 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
7004 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
7006 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
7007 &prog_data
->base
, prog
, shader
, 8,
7008 shader_time_index8
);
7009 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
7011 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
7014 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
7016 simd8_grf_start
= v8
.payload
.num_regs
;
7017 simd8_grf_used
= v8
.grf_used
;
7020 if (v8
.max_dispatch_width
>= 16 &&
7021 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
7022 /* Try a SIMD16 compile */
7023 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
7024 &prog_data
->base
, prog
, shader
, 16,
7025 shader_time_index16
);
7026 v16
.import_uniforms(&v8
);
7027 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
7028 compiler
->shader_perf_log(log_data
,
7029 "SIMD16 shader failed to compile: %s",
7032 simd16_cfg
= v16
.cfg
;
7033 simd16_grf_start
= v16
.payload
.num_regs
;
7034 simd16_grf_used
= v16
.grf_used
;
7038 /* When the caller requests a repclear shader, they want SIMD16-only */
7042 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
7043 * at the top to select the shader. We've never implemented that.
7044 * Instead, we just give them exactly one shader and we pick the widest one
7047 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
7050 if (prog_data
->persample_dispatch
) {
7051 /* Starting with SandyBridge (where we first get MSAA), the different
7052 * pixel dispatch combinations are grouped into classifications A
7053 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
7054 * generations, the only configurations supporting persample dispatch
7055 * are are this in which only one dispatch width is enabled.
7057 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
7058 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
7060 if (compiler
->devinfo
->gen
== 6 &&
7061 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
7063 } else if (simd16_cfg
) {
7068 /* We have to compute the flat inputs after the visitor is finished running
7069 * because it relies on prog_data->urb_setup which is computed in
7070 * fs_visitor::calculate_urb_setup().
7072 brw_compute_flat_inputs(prog_data
, shader
);
7074 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
7075 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
7076 MESA_SHADER_FRAGMENT
);
7078 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
7079 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
7080 shader
->info
.label
?
7081 shader
->info
.label
: "unnamed",
7082 shader
->info
.name
));
7086 prog_data
->dispatch_8
= true;
7087 g
.generate_code(simd8_cfg
, 8);
7088 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
7089 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
7092 prog_data
->dispatch_16
= true;
7093 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
7094 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
7095 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
7097 } else if (simd16_cfg
) {
7098 prog_data
->dispatch_16
= true;
7099 g
.generate_code(simd16_cfg
, 16);
7100 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
7101 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
7104 return g
.get_assembly();
7108 fs_visitor::emit_cs_work_group_id_setup()
7110 assert(stage
== MESA_SHADER_COMPUTE
);
7112 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
7114 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
7115 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
7116 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
7118 bld
.MOV(*reg
, r0_1
);
7119 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
7120 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
7126 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
7128 block
->dwords
= dwords
;
7129 block
->regs
= DIV_ROUND_UP(dwords
, 8);
7130 block
->size
= block
->regs
* 32;
7134 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
7135 struct brw_cs_prog_data
*cs_prog_data
)
7137 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
7138 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
7139 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
7141 /* The thread ID should be stored in the last param dword */
7142 assert(subgroup_id_index
== -1 ||
7143 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
7145 unsigned cross_thread_dwords
, per_thread_dwords
;
7146 if (!cross_thread_supported
) {
7147 cross_thread_dwords
= 0u;
7148 per_thread_dwords
= prog_data
->nr_params
;
7149 } else if (subgroup_id_index
>= 0) {
7150 /* Fill all but the last register with cross-thread payload */
7151 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
7152 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
7153 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
7155 /* Fill all data using cross-thread payload */
7156 cross_thread_dwords
= prog_data
->nr_params
;
7157 per_thread_dwords
= 0u;
7160 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
7161 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
7163 unsigned total_dwords
=
7164 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
7165 cs_prog_data
->push
.cross_thread
.size
) / 4;
7166 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
7168 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
7169 cs_prog_data
->push
.per_thread
.size
== 0);
7170 assert(cs_prog_data
->push
.cross_thread
.dwords
+
7171 cs_prog_data
->push
.per_thread
.dwords
==
7172 prog_data
->nr_params
);
7176 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
7178 cs_prog_data
->simd_size
= size
;
7179 unsigned group_size
= cs_prog_data
->local_size
[0] *
7180 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
7181 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
7185 compile_cs_to_nir(const struct brw_compiler
*compiler
,
7187 const struct brw_cs_prog_key
*key
,
7188 struct brw_cs_prog_data
*prog_data
,
7189 const nir_shader
*src_shader
,
7190 unsigned dispatch_width
)
7192 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
7193 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
7194 brw_nir_lower_cs_intrinsics(shader
, dispatch_width
);
7195 return brw_postprocess_nir(shader
, compiler
, true);
7199 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
7201 const struct brw_cs_prog_key
*key
,
7202 struct brw_cs_prog_data
*prog_data
,
7203 const nir_shader
*src_shader
,
7204 int shader_time_index
,
7207 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
7208 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
7209 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
7210 unsigned local_workgroup_size
=
7211 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
7212 src_shader
->info
.cs
.local_size
[2];
7214 unsigned min_dispatch_width
=
7215 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
7216 min_dispatch_width
= MAX2(8, min_dispatch_width
);
7217 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
7218 assert(min_dispatch_width
<= 32);
7220 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
7222 const char *fail_msg
= NULL
;
7223 unsigned promoted_constants
;
7225 /* Now the main event: Visit the shader IR and generate our CS IR for it.
7227 if (min_dispatch_width
<= 8) {
7228 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
7229 prog_data
, src_shader
, 8);
7230 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
7231 NULL
, /* Never used in core profile */
7232 nir8
, 8, shader_time_index
);
7233 if (!v8
->run_cs(min_dispatch_width
)) {
7234 fail_msg
= v8
->fail_msg
;
7236 /* We should always be able to do SIMD32 for compute shaders */
7237 assert(v8
->max_dispatch_width
>= 32);
7240 cs_set_simd_size(prog_data
, 8);
7241 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7242 promoted_constants
= v8
->promoted_constants
;
7246 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
7247 !fail_msg
&& min_dispatch_width
<= 16) {
7248 /* Try a SIMD16 compile */
7249 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
7250 prog_data
, src_shader
, 16);
7251 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
7252 NULL
, /* Never used in core profile */
7253 nir16
, 16, shader_time_index
);
7255 v16
->import_uniforms(v8
);
7257 if (!v16
->run_cs(min_dispatch_width
)) {
7258 compiler
->shader_perf_log(log_data
,
7259 "SIMD16 shader failed to compile: %s",
7263 "Couldn't generate SIMD16 program and not "
7264 "enough threads for SIMD8";
7267 /* We should always be able to do SIMD32 for compute shaders */
7268 assert(v16
->max_dispatch_width
>= 32);
7271 cs_set_simd_size(prog_data
, 16);
7272 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7273 promoted_constants
= v16
->promoted_constants
;
7277 /* We should always be able to do SIMD32 for compute shaders */
7278 assert(!v16
|| v16
->max_dispatch_width
>= 32);
7280 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
7281 /* Try a SIMD32 compile */
7282 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
7283 prog_data
, src_shader
, 32);
7284 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
7285 NULL
, /* Never used in core profile */
7286 nir32
, 32, shader_time_index
);
7288 v32
->import_uniforms(v8
);
7290 v32
->import_uniforms(v16
);
7292 if (!v32
->run_cs(min_dispatch_width
)) {
7293 compiler
->shader_perf_log(log_data
,
7294 "SIMD32 shader failed to compile: %s",
7298 "Couldn't generate SIMD32 program and not "
7299 "enough threads for SIMD16";
7303 cs_set_simd_size(prog_data
, 32);
7304 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7305 promoted_constants
= v32
->promoted_constants
;
7309 const unsigned *ret
= NULL
;
7310 if (unlikely(cfg
== NULL
)) {
7313 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
7315 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
7316 promoted_constants
, false, MESA_SHADER_COMPUTE
);
7317 if (INTEL_DEBUG
& DEBUG_CS
) {
7318 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
7319 src_shader
->info
.label
?
7320 src_shader
->info
.label
: "unnamed",
7321 src_shader
->info
.name
);
7322 g
.enable_debug(name
);
7325 g
.generate_code(cfg
, prog_data
->simd_size
);
7327 ret
= g
.get_assembly();
7338 * Test the dispatch mask packing assumptions of
7339 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
7340 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
7341 * executed with an unexpected dispatch mask.
7344 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
7346 const gl_shader_stage stage
= bld
.shader
->stage
;
7348 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
7349 bld
.shader
->stage_prog_data
)) {
7350 const fs_builder ubld
= bld
.exec_all().group(1, 0);
7351 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
7352 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
7355 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
7356 ubld
.AND(tmp
, mask
, tmp
);
7358 /* This will loop forever if the dispatch mask doesn't have the expected
7359 * form '2^n-1', in which case tmp will be non-zero.
7361 bld
.emit(BRW_OPCODE_DO
);
7362 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
7363 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));