2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
34 #include "brw_fs_live_variables.h"
36 #include "brw_vec4_gs_visitor.h"
38 #include "brw_dead_control_flow.h"
39 #include "dev/gen_debug.h"
40 #include "compiler/glsl_types.h"
41 #include "compiler/nir/nir_builder.h"
42 #include "program/prog_parameter.h"
43 #include "util/u_math.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset((void*)this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->size_written
= dst
.component_size(exec_size
);
82 this->size_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy((void*)this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable offset
176 * and a portion done using fs_reg::offset, which means that if you have
177 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
178 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
179 * later notice that those loads are all the same and eliminate the
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
196 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
197 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
201 * A helper for MOV generation for fixing up broken hardware SEND dependency
205 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
207 /* The caller always wants uncompressed to emit the minimal extra
208 * dependencies, and to avoid having to deal with aligning its regs to 2.
210 const fs_builder ubld
= bld
.annotate("send dependency resolve")
213 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
217 fs_inst::is_send_from_grf() const
220 case SHADER_OPCODE_SEND
:
221 case SHADER_OPCODE_SHADER_TIME_ADD
:
222 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
223 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
224 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
225 case SHADER_OPCODE_URB_WRITE_SIMD8
:
226 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
227 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
228 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
229 case SHADER_OPCODE_URB_READ_SIMD8
:
230 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
231 case SHADER_OPCODE_INTERLOCK
:
232 case SHADER_OPCODE_MEMORY_FENCE
:
233 case SHADER_OPCODE_BARRIER
:
235 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
236 return src
[1].file
== VGRF
;
237 case FS_OPCODE_FB_WRITE
:
238 case FS_OPCODE_FB_READ
:
239 return src
[0].file
== VGRF
;
242 return src
[0].file
== VGRF
;
249 fs_inst::is_control_source(unsigned arg
) const
252 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
253 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
254 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
257 case SHADER_OPCODE_BROADCAST
:
258 case SHADER_OPCODE_SHUFFLE
:
259 case SHADER_OPCODE_QUAD_SWIZZLE
:
260 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
261 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
262 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
263 case SHADER_OPCODE_GET_BUFFER_SIZE
:
266 case SHADER_OPCODE_MOV_INDIRECT
:
267 case SHADER_OPCODE_CLUSTER_BROADCAST
:
268 case SHADER_OPCODE_TEX
:
270 case SHADER_OPCODE_TXD
:
271 case SHADER_OPCODE_TXF
:
272 case SHADER_OPCODE_TXF_LZ
:
273 case SHADER_OPCODE_TXF_CMS
:
274 case SHADER_OPCODE_TXF_CMS_W
:
275 case SHADER_OPCODE_TXF_UMS
:
276 case SHADER_OPCODE_TXF_MCS
:
277 case SHADER_OPCODE_TXL
:
278 case SHADER_OPCODE_TXL_LZ
:
279 case SHADER_OPCODE_TXS
:
280 case SHADER_OPCODE_LOD
:
281 case SHADER_OPCODE_TG4
:
282 case SHADER_OPCODE_TG4_OFFSET
:
283 case SHADER_OPCODE_SAMPLEINFO
:
284 return arg
== 1 || arg
== 2;
286 case SHADER_OPCODE_SEND
:
287 return arg
== 0 || arg
== 1;
295 fs_inst::is_payload(unsigned arg
) const
298 case FS_OPCODE_FB_WRITE
:
299 case FS_OPCODE_FB_READ
:
300 case SHADER_OPCODE_URB_WRITE_SIMD8
:
301 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
302 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
303 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
304 case SHADER_OPCODE_URB_READ_SIMD8
:
305 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
306 case VEC4_OPCODE_UNTYPED_ATOMIC
:
307 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
308 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
309 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
310 case SHADER_OPCODE_SHADER_TIME_ADD
:
311 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
312 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
313 case SHADER_OPCODE_INTERLOCK
:
314 case SHADER_OPCODE_MEMORY_FENCE
:
315 case SHADER_OPCODE_BARRIER
:
318 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
321 case SHADER_OPCODE_SEND
:
322 return arg
== 2 || arg
== 3;
333 * Returns true if this instruction's sources and destinations cannot
334 * safely be the same register.
336 * In most cases, a register can be written over safely by the same
337 * instruction that is its last use. For a single instruction, the
338 * sources are dereferenced before writing of the destination starts
341 * However, there are a few cases where this can be problematic:
343 * - Virtual opcodes that translate to multiple instructions in the
344 * code generator: if src == dst and one instruction writes the
345 * destination before a later instruction reads the source, then
346 * src will have been clobbered.
348 * - SIMD16 compressed instructions with certain regioning (see below).
350 * The register allocator uses this information to set up conflicts between
351 * GRF sources and the destination.
354 fs_inst::has_source_and_destination_hazard() const
357 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
358 /* Multiple partial writes to the destination */
360 case SHADER_OPCODE_SHUFFLE
:
361 /* This instruction returns an arbitrary channel from the source and
362 * gets split into smaller instructions in the generator. It's possible
363 * that one of the instructions will read from a channel corresponding
364 * to an earlier instruction.
366 case SHADER_OPCODE_SEL_EXEC
:
367 /* This is implemented as
369 * mov(16) g4<1>D 0D { align1 WE_all 1H };
370 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
372 * Because the source is only read in the second instruction, the first
373 * may stomp all over it.
376 case SHADER_OPCODE_QUAD_SWIZZLE
:
378 case BRW_SWIZZLE_XXXX
:
379 case BRW_SWIZZLE_YYYY
:
380 case BRW_SWIZZLE_ZZZZ
:
381 case BRW_SWIZZLE_WWWW
:
382 case BRW_SWIZZLE_XXZZ
:
383 case BRW_SWIZZLE_YYWW
:
384 case BRW_SWIZZLE_XYXY
:
385 case BRW_SWIZZLE_ZWZW
:
386 /* These can be implemented as a single Align1 region on all
387 * platforms, so there's never a hazard between source and
388 * destination. C.f. fs_generator::generate_quad_swizzle().
392 return !is_uniform(src
[0]);
395 /* The SIMD16 compressed instruction
397 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
399 * is actually decoded in hardware as:
401 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
402 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
404 * Which is safe. However, if we have uniform accesses
405 * happening, we get into trouble:
407 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
408 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
410 * Now our destination for the first instruction overwrote the
411 * second instruction's src0, and we get garbage for those 8
412 * pixels. There's a similar issue for the pre-gen6
413 * pixel_x/pixel_y, which are registers of 16-bit values and thus
414 * would get stomped by the first decode as well.
416 if (exec_size
== 16) {
417 for (int i
= 0; i
< sources
; i
++) {
418 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
419 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
420 src
[i
].type
== BRW_REGISTER_TYPE_W
||
421 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
422 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
432 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
) const
434 if (devinfo
->gen
== 6 && is_math())
437 if (is_send_from_grf())
440 /* From GEN:BUG:1604601757:
442 * "When multiplying a DW and any lower precision integer, source modifier
445 if (devinfo
->gen
>= 12 && (opcode
== BRW_OPCODE_MUL
||
446 opcode
== BRW_OPCODE_MAD
)) {
447 const brw_reg_type exec_type
= get_exec_type(this);
448 const unsigned min_type_sz
= opcode
== BRW_OPCODE_MAD
?
449 MIN2(type_sz(src
[1].type
), type_sz(src
[2].type
)) :
450 MIN2(type_sz(src
[0].type
), type_sz(src
[1].type
));
452 if (brw_reg_type_is_integer(exec_type
) &&
453 type_sz(exec_type
) >= 4 &&
454 type_sz(exec_type
) != min_type_sz
)
458 if (!backend_instruction::can_do_source_mods())
465 fs_inst::can_do_cmod()
467 if (!backend_instruction::can_do_cmod())
470 /* The accumulator result appears to get used for the conditional modifier
471 * generation. When negating a UD value, there is a 33rd bit generated for
472 * the sign in the accumulator value, so now you can't check, for example,
473 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
475 for (unsigned i
= 0; i
< sources
; i
++) {
476 if (type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
484 fs_inst::can_change_types() const
486 return dst
.type
== src
[0].type
&&
487 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
488 (opcode
== BRW_OPCODE_MOV
||
489 (opcode
== BRW_OPCODE_SEL
&&
490 dst
.type
== src
[1].type
&&
491 predicate
!= BRW_PREDICATE_NONE
&&
492 !src
[1].abs
&& !src
[1].negate
));
498 memset((void*)this, 0, sizeof(*this));
499 type
= BRW_REGISTER_TYPE_UD
;
503 /** Generic unset register constructor. */
507 this->file
= BAD_FILE
;
510 fs_reg::fs_reg(struct ::brw_reg reg
) :
515 if (this->file
== IMM
&&
516 (this->type
!= BRW_REGISTER_TYPE_V
&&
517 this->type
!= BRW_REGISTER_TYPE_UV
&&
518 this->type
!= BRW_REGISTER_TYPE_VF
)) {
524 fs_reg::equals(const fs_reg
&r
) const
526 return (this->backend_reg::equals(r
) &&
531 fs_reg::negative_equals(const fs_reg
&r
) const
533 return (this->backend_reg::negative_equals(r
) &&
538 fs_reg::is_contiguous() const
543 return hstride
== BRW_HORIZONTAL_STRIDE_1
&&
544 vstride
== width
+ hstride
;
555 unreachable("Invalid register file");
559 fs_reg::component_size(unsigned width
) const
561 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
564 return MAX2(width
* stride
, 1) * type_sz(type
);
568 * Create a MOV to read the timestamp register.
571 fs_visitor::get_timestamp(const fs_builder
&bld
)
573 assert(devinfo
->gen
>= 7);
575 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
578 BRW_REGISTER_TYPE_UD
));
580 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
582 /* We want to read the 3 fields we care about even if it's not enabled in
585 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
591 fs_visitor::emit_shader_time_begin()
593 /* We want only the low 32 bits of the timestamp. Since it's running
594 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
595 * which is plenty of time for our purposes. It is identical across the
596 * EUs, but since it's tracking GPU core speed it will increment at a
597 * varying rate as render P-states change.
599 shader_start_time
= component(
600 get_timestamp(bld
.annotate("shader time start")), 0);
604 fs_visitor::emit_shader_time_end()
606 /* Insert our code just before the final SEND with EOT. */
607 exec_node
*end
= this->instructions
.get_tail();
608 assert(end
&& ((fs_inst
*) end
)->eot
);
609 const fs_builder ibld
= bld
.annotate("shader time end")
610 .exec_all().at(NULL
, end
);
611 const fs_reg timestamp
= get_timestamp(ibld
);
613 /* We only use the low 32 bits of the timestamp - see
614 * emit_shader_time_begin()).
616 * We could also check if render P-states have changed (or anything
617 * else that might disrupt timing) by setting smear to 2 and checking if
618 * that field is != 0.
620 const fs_reg shader_end_time
= component(timestamp
, 0);
622 /* Check that there weren't any timestamp reset events (assuming these
623 * were the only two timestamp reads that happened).
625 const fs_reg reset
= component(timestamp
, 2);
626 set_condmod(BRW_CONDITIONAL_Z
,
627 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
628 ibld
.IF(BRW_PREDICATE_NORMAL
);
630 fs_reg start
= shader_start_time
;
632 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
633 BRW_REGISTER_TYPE_UD
),
635 const fs_builder cbld
= ibld
.group(1, 0);
636 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
638 /* If there were no instructions between the two timestamp gets, the diff
639 * is 2 cycles. Remove that overhead, so I can forget about that when
640 * trying to determine the time taken for single instructions.
642 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
643 SHADER_TIME_ADD(cbld
, 0, diff
);
644 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
645 ibld
.emit(BRW_OPCODE_ELSE
);
646 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
647 ibld
.emit(BRW_OPCODE_ENDIF
);
651 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
652 int shader_time_subindex
,
655 int index
= shader_time_index
* 3 + shader_time_subindex
;
656 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
659 if (dispatch_width
== 8)
660 payload
= vgrf(glsl_type::uvec2_type
);
662 payload
= vgrf(glsl_type::uint_type
);
664 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
668 fs_visitor::vfail(const char *format
, va_list va
)
677 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
678 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
680 this->fail_msg
= msg
;
683 fprintf(stderr
, "%s", msg
);
688 fs_visitor::fail(const char *format
, ...)
692 va_start(va
, format
);
698 * Mark this program as impossible to compile with dispatch width greater
701 * During the SIMD8 compile (which happens first), we can detect and flag
702 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
703 * SIMD16+ compile altogether.
705 * During a compile of dispatch width greater than n (if one happens anyway),
706 * this just calls fail().
709 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
711 if (dispatch_width
> n
) {
714 max_dispatch_width
= n
;
715 compiler
->shader_perf_log(log_data
,
716 "Shader dispatch width limited to SIMD%d: %s",
722 * Returns true if the instruction has a flag that means it won't
723 * update an entire destination register.
725 * For example, dead code elimination and live variable analysis want to know
726 * when a write to a variable screens off any preceding values that were in
730 fs_inst::is_partial_write() const
732 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
733 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
734 !this->dst
.is_contiguous() ||
735 this->dst
.offset
% REG_SIZE
!= 0);
739 fs_inst::components_read(unsigned i
) const
741 /* Return zero if the source is not present. */
742 if (src
[i
].file
== BAD_FILE
)
746 case FS_OPCODE_LINTERP
:
752 case FS_OPCODE_PIXEL_X
:
753 case FS_OPCODE_PIXEL_Y
:
757 case FS_OPCODE_FB_WRITE_LOGICAL
:
758 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
759 /* First/second FB write color. */
761 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
765 case SHADER_OPCODE_TEX_LOGICAL
:
766 case SHADER_OPCODE_TXD_LOGICAL
:
767 case SHADER_OPCODE_TXF_LOGICAL
:
768 case SHADER_OPCODE_TXL_LOGICAL
:
769 case SHADER_OPCODE_TXS_LOGICAL
:
770 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
771 case FS_OPCODE_TXB_LOGICAL
:
772 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
773 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
774 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
775 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
776 case SHADER_OPCODE_LOD_LOGICAL
:
777 case SHADER_OPCODE_TG4_LOGICAL
:
778 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
779 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
780 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
781 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
782 /* Texture coordinates. */
783 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
784 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
785 /* Texture derivatives. */
786 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
787 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
788 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
789 /* Texture offset. */
790 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
793 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
798 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
799 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
800 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
);
801 /* Surface coordinates. */
802 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
803 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
804 /* Surface operation source (ignored for reads). */
805 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
810 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
811 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
812 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
813 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
814 /* Surface coordinates. */
815 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
816 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
817 /* Surface operation source. */
818 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
819 return src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
823 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
824 assert(src
[2].file
== IMM
);
827 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
828 assert(src
[2].file
== IMM
);
829 return i
== 1 ? src
[2].ud
: 1;
831 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
832 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
833 assert(src
[2].file
== IMM
);
836 const unsigned op
= src
[2].ud
;
851 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
852 assert(src
[2].file
== IMM
);
855 const unsigned op
= src
[2].ud
;
856 return op
== BRW_AOP_FCMPWR
? 2 : 1;
861 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
862 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
863 /* Scattered logical opcodes use the following params:
864 * src[0] Surface coordinates
865 * src[1] Surface operation source (ignored for reads)
867 * src[3] IMM with always 1 dimension.
868 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
870 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
871 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
872 return i
== SURFACE_LOGICAL_SRC_DATA
? 0 : 1;
874 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
875 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
876 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
877 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
880 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
881 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
882 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
883 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
884 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
885 /* Surface coordinates. */
886 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
887 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
888 /* Surface operation source. */
889 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_CMPWR
)
891 else if (i
== SURFACE_LOGICAL_SRC_DATA
&&
892 (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
|| op
== BRW_AOP_PREDEC
))
897 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
898 return (i
== 0 ? 2 : 1);
900 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
: {
901 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
902 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
903 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
904 /* Surface coordinates. */
905 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
906 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
907 /* Surface operation source. */
908 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_FCMPWR
)
920 fs_inst::size_read(int arg
) const
923 case SHADER_OPCODE_SEND
:
925 return mlen
* REG_SIZE
;
926 } else if (arg
== 3) {
927 return ex_mlen
* REG_SIZE
;
931 case FS_OPCODE_FB_WRITE
:
932 case FS_OPCODE_REP_FB_WRITE
:
935 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
937 return mlen
* REG_SIZE
;
941 case FS_OPCODE_FB_READ
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8
:
943 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
944 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
945 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
946 case SHADER_OPCODE_URB_READ_SIMD8
:
947 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
948 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
949 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
951 return mlen
* REG_SIZE
;
954 case FS_OPCODE_SET_SAMPLE_ID
:
959 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
960 /* The payload is actually stored in src1 */
962 return mlen
* REG_SIZE
;
965 case FS_OPCODE_LINTERP
:
970 case SHADER_OPCODE_LOAD_PAYLOAD
:
971 if (arg
< this->header_size
)
975 case CS_OPCODE_CS_TERMINATE
:
976 case SHADER_OPCODE_BARRIER
:
979 case SHADER_OPCODE_MOV_INDIRECT
:
981 assert(src
[2].file
== IMM
);
987 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
988 return mlen
* REG_SIZE
;
992 switch (src
[arg
].file
) {
995 return components_read(arg
) * type_sz(src
[arg
].type
);
1001 return components_read(arg
) * src
[arg
].component_size(exec_size
);
1003 unreachable("MRF registers are not allowed as sources");
1010 predicate_width(brw_predicate predicate
)
1012 switch (predicate
) {
1013 case BRW_PREDICATE_NONE
: return 1;
1014 case BRW_PREDICATE_NORMAL
: return 1;
1015 case BRW_PREDICATE_ALIGN1_ANY2H
: return 2;
1016 case BRW_PREDICATE_ALIGN1_ALL2H
: return 2;
1017 case BRW_PREDICATE_ALIGN1_ANY4H
: return 4;
1018 case BRW_PREDICATE_ALIGN1_ALL4H
: return 4;
1019 case BRW_PREDICATE_ALIGN1_ANY8H
: return 8;
1020 case BRW_PREDICATE_ALIGN1_ALL8H
: return 8;
1021 case BRW_PREDICATE_ALIGN1_ANY16H
: return 16;
1022 case BRW_PREDICATE_ALIGN1_ALL16H
: return 16;
1023 case BRW_PREDICATE_ALIGN1_ANY32H
: return 32;
1024 case BRW_PREDICATE_ALIGN1_ALL32H
: return 32;
1025 default: unreachable("Unsupported predicate");
1029 /* Return the subset of flag registers that an instruction could
1030 * potentially read or write based on the execution controls and flag
1031 * subregister number of the instruction.
1034 flag_mask(const fs_inst
*inst
, unsigned width
)
1036 assert(util_is_power_of_two_nonzero(width
));
1037 const unsigned start
= (inst
->flag_subreg
* 16 + inst
->group
) &
1039 const unsigned end
= start
+ ALIGN(inst
->exec_size
, width
);
1040 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
1044 bit_mask(unsigned n
)
1046 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
1050 flag_mask(const fs_reg
&r
, unsigned sz
)
1052 if (r
.file
== ARF
) {
1053 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
1054 const unsigned end
= start
+ sz
;
1055 return bit_mask(end
) & ~bit_mask(start
);
1063 fs_inst::flags_read(const gen_device_info
*devinfo
) const
1065 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
1066 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
1067 /* The vertical predication modes combine corresponding bits from
1068 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
1070 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
1071 return flag_mask(this, 1) << shift
| flag_mask(this, 1);
1072 } else if (predicate
) {
1073 return flag_mask(this, predicate_width(predicate
));
1076 for (int i
= 0; i
< sources
; i
++) {
1077 mask
|= flag_mask(src
[i
], size_read(i
));
1084 fs_inst::flags_written() const
1086 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1087 opcode
!= BRW_OPCODE_CSEL
&&
1088 opcode
!= BRW_OPCODE_IF
&&
1089 opcode
!= BRW_OPCODE_WHILE
)) ||
1090 opcode
== FS_OPCODE_FB_WRITE
) {
1091 return flag_mask(this, 1);
1092 } else if (opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
1093 opcode
== FS_OPCODE_LOAD_LIVE_CHANNELS
) {
1094 return flag_mask(this, 32);
1096 return flag_mask(dst
, size_written
);
1101 * Returns how many MRFs an FS opcode will write over.
1103 * Note that this is not the 0 or 1 implied writes in an actual gen
1104 * instruction -- the FS opcodes often generate MOVs in addition.
1107 fs_inst::implied_mrf_writes() const
1116 case SHADER_OPCODE_RCP
:
1117 case SHADER_OPCODE_RSQ
:
1118 case SHADER_OPCODE_SQRT
:
1119 case SHADER_OPCODE_EXP2
:
1120 case SHADER_OPCODE_LOG2
:
1121 case SHADER_OPCODE_SIN
:
1122 case SHADER_OPCODE_COS
:
1123 return 1 * exec_size
/ 8;
1124 case SHADER_OPCODE_POW
:
1125 case SHADER_OPCODE_INT_QUOTIENT
:
1126 case SHADER_OPCODE_INT_REMAINDER
:
1127 return 2 * exec_size
/ 8;
1128 case SHADER_OPCODE_TEX
:
1130 case SHADER_OPCODE_TXD
:
1131 case SHADER_OPCODE_TXF
:
1132 case SHADER_OPCODE_TXF_CMS
:
1133 case SHADER_OPCODE_TXF_MCS
:
1134 case SHADER_OPCODE_TG4
:
1135 case SHADER_OPCODE_TG4_OFFSET
:
1136 case SHADER_OPCODE_TXL
:
1137 case SHADER_OPCODE_TXS
:
1138 case SHADER_OPCODE_LOD
:
1139 case SHADER_OPCODE_SAMPLEINFO
:
1141 case FS_OPCODE_FB_WRITE
:
1142 case FS_OPCODE_REP_FB_WRITE
:
1143 return src
[0].file
== BAD_FILE
? 0 : 2;
1144 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1145 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1147 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1149 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1152 unreachable("not reached");
1157 fs_visitor::vgrf(const glsl_type
*const type
)
1159 int reg_width
= dispatch_width
/ 8;
1161 alloc
.allocate(glsl_count_dword_slots(type
, false) * reg_width
),
1162 brw_type_for_base_type(type
));
1165 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1170 this->type
= BRW_REGISTER_TYPE_F
;
1171 this->stride
= (file
== UNIFORM
? 0 : 1);
1174 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1180 this->stride
= (file
== UNIFORM
? 0 : 1);
1183 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1184 * This brings in those uniform definitions
1187 fs_visitor::import_uniforms(fs_visitor
*v
)
1189 this->push_constant_loc
= v
->push_constant_loc
;
1190 this->pull_constant_loc
= v
->pull_constant_loc
;
1191 this->uniforms
= v
->uniforms
;
1192 this->subgroup_id
= v
->subgroup_id
;
1196 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1198 assert(stage
== MESA_SHADER_FRAGMENT
);
1200 /* gl_FragCoord.x */
1201 bld
.MOV(wpos
, this->pixel_x
);
1202 wpos
= offset(wpos
, bld
, 1);
1204 /* gl_FragCoord.y */
1205 bld
.MOV(wpos
, this->pixel_y
);
1206 wpos
= offset(wpos
, bld
, 1);
1208 /* gl_FragCoord.z */
1209 if (devinfo
->gen
>= 6) {
1210 bld
.MOV(wpos
, fetch_payload_reg(bld
, payload
.source_depth_reg
));
1212 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1213 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1214 component(interp_reg(VARYING_SLOT_POS
, 2), 0));
1216 wpos
= offset(wpos
, bld
, 1);
1218 /* gl_FragCoord.w: Already set up in emit_interpolation */
1219 bld
.MOV(wpos
, this->wpos_w
);
1222 enum brw_barycentric_mode
1223 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1225 /* Barycentric modes don't make sense for flat inputs. */
1226 assert(mode
!= INTERP_MODE_FLAT
);
1230 case nir_intrinsic_load_barycentric_pixel
:
1231 case nir_intrinsic_load_barycentric_at_offset
:
1232 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1234 case nir_intrinsic_load_barycentric_centroid
:
1235 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1237 case nir_intrinsic_load_barycentric_sample
:
1238 case nir_intrinsic_load_barycentric_at_sample
:
1239 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1242 unreachable("invalid intrinsic");
1245 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1248 return (enum brw_barycentric_mode
) bary
;
1252 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1254 static enum brw_barycentric_mode
1255 centroid_to_pixel(enum brw_barycentric_mode bary
)
1257 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1258 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1259 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1263 fs_visitor::emit_frontfacing_interpolation()
1265 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1267 if (devinfo
->gen
>= 12) {
1268 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
1270 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1271 bld
.ASR(tmp
, g1
, brw_imm_d(15));
1273 } else if (devinfo
->gen
>= 6) {
1274 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1275 * a boolean result from this (~0/true or 0/false).
1277 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1278 * this task in only one instruction:
1279 * - a negation source modifier will flip the bit; and
1280 * - a W -> D type conversion will sign extend the bit into the high
1281 * word of the destination.
1283 * An ASR 15 fills the low word of the destination.
1285 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1288 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1290 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1291 * a boolean result from this (1/true or 0/false).
1293 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1294 * the negation source modifier to flip it. Unfortunately the SHR
1295 * instruction only operates on UD (or D with an abs source modifier)
1296 * sources without negation.
1298 * Instead, use ASR (which will give ~0/true or 0/false).
1300 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1303 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1310 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1312 assert(stage
== MESA_SHADER_FRAGMENT
);
1313 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1314 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1316 if (wm_prog_data
->persample_dispatch
) {
1317 /* Convert int_sample_pos to floating point */
1318 bld
.MOV(dst
, int_sample_pos
);
1319 /* Scale to the range [0, 1] */
1320 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1323 /* From ARB_sample_shading specification:
1324 * "When rendering to a non-multisample buffer, or if multisample
1325 * rasterization is disabled, gl_SamplePosition will always be
1328 bld
.MOV(dst
, brw_imm_f(0.5f
));
1333 fs_visitor::emit_samplepos_setup()
1335 assert(devinfo
->gen
>= 6);
1337 const fs_builder abld
= bld
.annotate("compute sample position");
1338 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1340 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1341 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1343 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1344 * mode will be enabled.
1346 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1347 * R31.1:0 Position Offset X/Y for Slot[3:0]
1348 * R31.3:2 Position Offset X/Y for Slot[7:4]
1351 * The X, Y sample positions come in as bytes in thread payload. So, read
1352 * the positions using vstride=16, width=8, hstride=2.
1354 const fs_reg sample_pos_reg
=
1355 fetch_payload_reg(abld
, payload
.sample_pos_reg
, BRW_REGISTER_TYPE_W
);
1357 /* Compute gl_SamplePosition.x */
1358 abld
.MOV(int_sample_x
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 0));
1359 compute_sample_position(offset(pos
, abld
, 0), int_sample_x
);
1361 /* Compute gl_SamplePosition.y */
1362 abld
.MOV(int_sample_y
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 1));
1363 compute_sample_position(offset(pos
, abld
, 1), int_sample_y
);
1368 fs_visitor::emit_sampleid_setup()
1370 assert(stage
== MESA_SHADER_FRAGMENT
);
1371 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1372 assert(devinfo
->gen
>= 6);
1374 const fs_builder abld
= bld
.annotate("compute sample id");
1375 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1377 if (!key
->multisample_fbo
) {
1378 /* As per GL_ARB_sample_shading specification:
1379 * "When rendering to a non-multisample buffer, or if multisample
1380 * rasterization is disabled, gl_SampleID will always be zero."
1382 abld
.MOV(*reg
, brw_imm_d(0));
1383 } else if (devinfo
->gen
>= 8) {
1384 /* Sample ID comes in as 4-bit numbers in g1.0:
1386 * 15:12 Slot 3 SampleID (only used in SIMD16)
1387 * 11:8 Slot 2 SampleID (only used in SIMD16)
1388 * 7:4 Slot 1 SampleID
1389 * 3:0 Slot 0 SampleID
1391 * Each slot corresponds to four channels, so we want to replicate each
1392 * half-byte value to 4 channels in a row:
1394 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1395 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1397 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1398 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1400 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1401 * channels to read the first byte (7:0), and the second group of 8
1402 * channels to read the second byte (15:8). Then, we shift right by
1403 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1404 * values into place. Finally, we AND with 0xf to keep the low nibble.
1406 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1407 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1409 * TODO: These payload bits exist on Gen7 too, but they appear to always
1410 * be zero, so this code fails to work. We should find out why.
1412 const fs_reg tmp
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1414 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
1415 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
1416 hbld
.SHR(offset(tmp
, hbld
, i
),
1417 stride(retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UB
),
1419 brw_imm_v(0x44440000));
1422 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1424 const fs_reg t1
= component(abld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
1425 const fs_reg t2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1427 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1428 * 8x multisampling, subspan 0 will represent sample N (where N
1429 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1430 * 7. We can find the value of N by looking at R0.0 bits 7:6
1431 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1432 * (since samples are always delivered in pairs). That is, we
1433 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1434 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1435 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1436 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1437 * populating a temporary variable with the sequence (0, 1, 2, 3),
1438 * and then reading from it using vstride=1, width=4, hstride=0.
1439 * These computations hold good for 4x multisampling as well.
1441 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1442 * the first four slots are sample 0 of subspan 0; the next four
1443 * are sample 1 of subspan 0; the third group is sample 0 of
1444 * subspan 1, and finally sample 1 of subspan 1.
1447 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1448 * accomodate 16x MSAA.
1450 abld
.exec_all().group(1, 0)
1451 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1453 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1455 /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1456 * can assume 4x MSAA. Disallow it on IVB+
1458 * FINISHME: One day, we could come up with a way to do this that
1459 * actually works on gen7.
1461 if (devinfo
->gen
>= 7)
1462 limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
1463 abld
.exec_all().group(8, 0).MOV(t2
, brw_imm_v(0x32103210));
1465 /* This special instruction takes care of setting vstride=1,
1466 * width=4, hstride=0 of t2 during an ADD instruction.
1468 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1475 fs_visitor::emit_samplemaskin_setup()
1477 assert(stage
== MESA_SHADER_FRAGMENT
);
1478 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1479 assert(devinfo
->gen
>= 6);
1481 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1483 fs_reg coverage_mask
=
1484 fetch_payload_reg(bld
, payload
.sample_mask_in_reg
, BRW_REGISTER_TYPE_D
);
1486 if (wm_prog_data
->persample_dispatch
) {
1487 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1488 * and a mask representing which sample is being processed by the
1489 * current shader invocation.
1491 * From the OES_sample_variables specification:
1492 * "When per-sample shading is active due to the use of a fragment input
1493 * qualified by "sample" or due to the use of the gl_SampleID or
1494 * gl_SamplePosition variables, only the bit for the current sample is
1495 * set in gl_SampleMaskIn."
1497 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1499 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1500 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1502 fs_reg one
= vgrf(glsl_type::int_type
);
1503 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1504 abld
.MOV(one
, brw_imm_d(1));
1505 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1506 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1508 /* In per-pixel mode, the coverage mask is sufficient. */
1509 *reg
= coverage_mask
;
1515 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1517 if (!src
.abs
&& !src
.negate
)
1520 fs_reg temp
= bld
.vgrf(src
.type
);
1527 fs_visitor::emit_discard_jump()
1529 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1531 /* For performance, after a discard, jump to the end of the
1532 * shader if all relevant channels have been discarded.
1534 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1535 discard_jump
->flag_subreg
= 1;
1537 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1538 discard_jump
->predicate_inverse
= true;
1542 fs_visitor::emit_gs_thread_end()
1544 assert(stage
== MESA_SHADER_GEOMETRY
);
1546 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1548 if (gs_compile
->control_data_header_size_bits
> 0) {
1549 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1552 const fs_builder abld
= bld
.annotate("thread end");
1555 if (gs_prog_data
->static_vertex_count
!= -1) {
1556 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1557 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1558 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1559 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1560 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1563 /* Delete now dead instructions. */
1564 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1570 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1574 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1575 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1576 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1579 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1580 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1581 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1582 sources
[1] = this->final_gs_vertex_count
;
1583 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1584 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1592 fs_visitor::assign_curb_setup()
1594 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1596 unsigned ubo_push_length
= 0;
1597 unsigned ubo_push_start
[4];
1598 for (int i
= 0; i
< 4; i
++) {
1599 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1600 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1603 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1605 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1606 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1607 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1608 if (inst
->src
[i
].file
== UNIFORM
) {
1609 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1611 if (inst
->src
[i
].nr
>= UBO_START
) {
1612 /* constant_nr is in 32-bit units, the rest are in bytes */
1613 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1614 inst
->src
[i
].offset
/ 4;
1615 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1616 constant_nr
= push_constant_loc
[uniform_nr
];
1618 /* Section 5.11 of the OpenGL 4.1 spec says:
1619 * "Out-of-bounds reads return undefined values, which include
1620 * values from other variables of the active program or zero."
1621 * Just return the first push constant.
1626 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1629 brw_reg
.abs
= inst
->src
[i
].abs
;
1630 brw_reg
.negate
= inst
->src
[i
].negate
;
1632 assert(inst
->src
[i
].stride
== 0);
1633 inst
->src
[i
] = byte_offset(
1634 retype(brw_reg
, inst
->src
[i
].type
),
1635 inst
->src
[i
].offset
% 4);
1640 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1641 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1645 calculate_urb_setup(const struct gen_device_info
*devinfo
,
1646 const struct brw_wm_prog_key
*key
,
1647 struct brw_wm_prog_data
*prog_data
,
1648 const nir_shader
*nir
)
1650 memset(prog_data
->urb_setup
, -1,
1651 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1654 /* Figure out where each of the incoming setup attributes lands. */
1655 if (devinfo
->gen
>= 6) {
1656 if (util_bitcount64(nir
->info
.inputs_read
&
1657 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1658 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1659 * first 16 varying inputs, so we can put them wherever we want.
1660 * Just put them in order.
1662 * This is useful because it means that (a) inputs not used by the
1663 * fragment shader won't take up valuable register space, and (b) we
1664 * won't have to recompile the fragment shader if it gets paired with
1665 * a different vertex (or geometry) shader.
1667 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1668 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1669 BITFIELD64_BIT(i
)) {
1670 prog_data
->urb_setup
[i
] = urb_next
++;
1674 /* We have enough input varyings that the SF/SBE pipeline stage can't
1675 * arbitrarily rearrange them to suit our whim; we have to put them
1676 * in an order that matches the output of the previous pipeline stage
1677 * (geometry or vertex shader).
1679 struct brw_vue_map prev_stage_vue_map
;
1680 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1681 key
->input_slots_valid
,
1682 nir
->info
.separate_shader
);
1685 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1686 &prev_stage_vue_map
);
1688 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1689 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1691 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1692 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1693 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1694 BITFIELD64_BIT(varying
))) {
1695 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1698 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1701 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1702 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1703 /* Point size is packed into the header, not as a general attribute */
1704 if (i
== VARYING_SLOT_PSIZ
)
1707 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1708 /* The back color slot is skipped when the front color is
1709 * also written to. In addition, some slots can be
1710 * written in the vertex shader and not read in the
1711 * fragment shader. So the register number must always be
1712 * incremented, mapped or not.
1714 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1715 prog_data
->urb_setup
[i
] = urb_next
;
1721 * It's a FS only attribute, and we did interpolation for this attribute
1722 * in SF thread. So, count it here, too.
1724 * See compile_sf_prog() for more info.
1726 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1727 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1730 prog_data
->num_varying_inputs
= urb_next
;
1734 fs_visitor::assign_urb_setup()
1736 assert(stage
== MESA_SHADER_FRAGMENT
);
1737 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1739 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1741 /* Offset all the urb_setup[] index by the actual position of the
1742 * setup regs, now that the location of the constants has been chosen.
1744 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1745 for (int i
= 0; i
< inst
->sources
; i
++) {
1746 if (inst
->src
[i
].file
== ATTR
) {
1747 /* ATTR regs in the FS are in units of logical scalar inputs each
1748 * of which consumes half of a GRF register.
1750 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1751 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1752 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1753 inst
->src
[i
].offset
;
1754 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1755 1 : MIN2(inst
->exec_size
, 8);
1756 struct brw_reg reg
= stride(
1757 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1759 width
* inst
->src
[i
].stride
,
1760 width
, inst
->src
[i
].stride
);
1761 reg
.abs
= inst
->src
[i
].abs
;
1762 reg
.negate
= inst
->src
[i
].negate
;
1768 /* Each attribute is 4 setup channels, each of which is half a reg. */
1769 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1773 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1775 for (int i
= 0; i
< inst
->sources
; i
++) {
1776 if (inst
->src
[i
].file
== ATTR
) {
1777 int grf
= payload
.num_regs
+
1778 prog_data
->curb_read_length
+
1780 inst
->src
[i
].offset
/ REG_SIZE
;
1782 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1784 * VertStride must be used to cross GRF register boundaries. This
1785 * rule implies that elements within a 'Width' cannot cross GRF
1788 * So, for registers that are large enough, we have to split the exec
1789 * size in two and trust the compression state to sort it out.
1791 unsigned total_size
= inst
->exec_size
*
1792 inst
->src
[i
].stride
*
1793 type_sz(inst
->src
[i
].type
);
1795 assert(total_size
<= 2 * REG_SIZE
);
1796 const unsigned exec_size
=
1797 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1799 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1800 struct brw_reg reg
=
1801 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1802 inst
->src
[i
].offset
% REG_SIZE
),
1803 exec_size
* inst
->src
[i
].stride
,
1804 width
, inst
->src
[i
].stride
);
1805 reg
.abs
= inst
->src
[i
].abs
;
1806 reg
.negate
= inst
->src
[i
].negate
;
1814 fs_visitor::assign_vs_urb_setup()
1816 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1818 assert(stage
== MESA_SHADER_VERTEX
);
1820 /* Each attribute is 4 regs. */
1821 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1823 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1825 /* Rewrite all ATTR file references to the hw grf that they land in. */
1826 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1827 convert_attr_sources_to_hw_regs(inst
);
1832 fs_visitor::assign_tcs_urb_setup()
1834 assert(stage
== MESA_SHADER_TESS_CTRL
);
1836 /* Rewrite all ATTR file references to HW_REGs. */
1837 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1838 convert_attr_sources_to_hw_regs(inst
);
1843 fs_visitor::assign_tes_urb_setup()
1845 assert(stage
== MESA_SHADER_TESS_EVAL
);
1847 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1849 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1851 /* Rewrite all ATTR file references to HW_REGs. */
1852 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1853 convert_attr_sources_to_hw_regs(inst
);
1858 fs_visitor::assign_gs_urb_setup()
1860 assert(stage
== MESA_SHADER_GEOMETRY
);
1862 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1864 first_non_payload_grf
+=
1865 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1867 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1868 /* Rewrite all ATTR file references to GRFs. */
1869 convert_attr_sources_to_hw_regs(inst
);
1875 * Split large virtual GRFs into separate components if we can.
1877 * This is mostly duplicated with what brw_fs_vector_splitting does,
1878 * but that's really conservative because it's afraid of doing
1879 * splitting that doesn't result in real progress after the rest of
1880 * the optimization phases, which would cause infinite looping in
1881 * optimization. We can do it once here, safely. This also has the
1882 * opportunity to split interpolated values, or maybe even uniforms,
1883 * which we don't have at the IR level.
1885 * We want to split, because virtual GRFs are what we register
1886 * allocate and spill (due to contiguousness requirements for some
1887 * instructions), and they're what we naturally generate in the
1888 * codegen process, but most virtual GRFs don't actually need to be
1889 * contiguous sets of GRFs. If we split, we'll end up with reduced
1890 * live intervals and better dead code elimination and coalescing.
1893 fs_visitor::split_virtual_grfs()
1895 /* Compact the register file so we eliminate dead vgrfs. This
1896 * only defines split points for live registers, so if we have
1897 * too large dead registers they will hit assertions later.
1899 compact_virtual_grfs();
1901 int num_vars
= this->alloc
.count
;
1903 /* Count the total number of registers */
1905 int vgrf_to_reg
[num_vars
];
1906 for (int i
= 0; i
< num_vars
; i
++) {
1907 vgrf_to_reg
[i
] = reg_count
;
1908 reg_count
+= alloc
.sizes
[i
];
1911 /* An array of "split points". For each register slot, this indicates
1912 * if this slot can be separated from the previous slot. Every time an
1913 * instruction uses multiple elements of a register (as a source or
1914 * destination), we mark the used slots as inseparable. Then we go
1915 * through and split the registers into the smallest pieces we can.
1917 bool *split_points
= new bool[reg_count
];
1918 memset(split_points
, 0, reg_count
* sizeof(*split_points
));
1920 /* Mark all used registers as fully splittable */
1921 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1922 if (inst
->dst
.file
== VGRF
) {
1923 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1924 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1925 split_points
[reg
+ j
] = true;
1928 for (int i
= 0; i
< inst
->sources
; i
++) {
1929 if (inst
->src
[i
].file
== VGRF
) {
1930 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1931 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1932 split_points
[reg
+ j
] = true;
1937 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1938 /* We fix up undef instructions later */
1939 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
1940 /* UNDEF instructions are currently only used to undef entire
1941 * registers. We need this invariant later when we split them.
1943 assert(inst
->dst
.file
== VGRF
);
1944 assert(inst
->dst
.offset
== 0);
1945 assert(inst
->size_written
== alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
);
1949 if (inst
->dst
.file
== VGRF
) {
1950 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1951 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1952 split_points
[reg
+ j
] = false;
1954 for (int i
= 0; i
< inst
->sources
; i
++) {
1955 if (inst
->src
[i
].file
== VGRF
) {
1956 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1957 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1958 split_points
[reg
+ j
] = false;
1963 int *new_virtual_grf
= new int[reg_count
];
1964 int *new_reg_offset
= new int[reg_count
];
1967 for (int i
= 0; i
< num_vars
; i
++) {
1968 /* The first one should always be 0 as a quick sanity check. */
1969 assert(split_points
[reg
] == false);
1972 new_reg_offset
[reg
] = 0;
1977 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1978 /* If this is a split point, reset the offset to 0 and allocate a
1979 * new virtual GRF for the previous offset many registers
1981 if (split_points
[reg
]) {
1982 assert(offset
<= MAX_VGRF_SIZE
);
1983 int grf
= alloc
.allocate(offset
);
1984 for (int k
= reg
- offset
; k
< reg
; k
++)
1985 new_virtual_grf
[k
] = grf
;
1988 new_reg_offset
[reg
] = offset
;
1993 /* The last one gets the original register number */
1994 assert(offset
<= MAX_VGRF_SIZE
);
1995 alloc
.sizes
[i
] = offset
;
1996 for (int k
= reg
- offset
; k
< reg
; k
++)
1997 new_virtual_grf
[k
] = i
;
1999 assert(reg
== reg_count
);
2001 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2002 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2003 const fs_builder
ibld(this, block
, inst
);
2004 assert(inst
->size_written
% REG_SIZE
== 0);
2005 unsigned reg_offset
= 0;
2006 while (reg_offset
< inst
->size_written
/ REG_SIZE
) {
2007 reg
= vgrf_to_reg
[inst
->dst
.nr
] + reg_offset
;
2008 ibld
.UNDEF(fs_reg(VGRF
, new_virtual_grf
[reg
], inst
->dst
.type
));
2009 reg_offset
+= alloc
.sizes
[new_virtual_grf
[reg
]];
2011 inst
->remove(block
);
2015 if (inst
->dst
.file
== VGRF
) {
2016 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2017 inst
->dst
.nr
= new_virtual_grf
[reg
];
2018 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
2019 inst
->dst
.offset
% REG_SIZE
;
2020 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2022 for (int i
= 0; i
< inst
->sources
; i
++) {
2023 if (inst
->src
[i
].file
== VGRF
) {
2024 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2025 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
2026 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
2027 inst
->src
[i
].offset
% REG_SIZE
;
2028 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2032 invalidate_live_intervals();
2034 delete[] split_points
;
2035 delete[] new_virtual_grf
;
2036 delete[] new_reg_offset
;
2040 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
2042 * During code generation, we create tons of temporary variables, many of
2043 * which get immediately killed and are never used again. Yet, in later
2044 * optimization and analysis passes, such as compute_live_intervals, we need
2045 * to loop over all the virtual GRFs. Compacting them can save a lot of
2049 fs_visitor::compact_virtual_grfs()
2051 bool progress
= false;
2052 int *remap_table
= new int[this->alloc
.count
];
2053 memset(remap_table
, -1, this->alloc
.count
* sizeof(int));
2055 /* Mark which virtual GRFs are used. */
2056 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2057 if (inst
->dst
.file
== VGRF
)
2058 remap_table
[inst
->dst
.nr
] = 0;
2060 for (int i
= 0; i
< inst
->sources
; i
++) {
2061 if (inst
->src
[i
].file
== VGRF
)
2062 remap_table
[inst
->src
[i
].nr
] = 0;
2066 /* Compact the GRF arrays. */
2068 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2069 if (remap_table
[i
] == -1) {
2070 /* We just found an unused register. This means that we are
2071 * actually going to compact something.
2075 remap_table
[i
] = new_index
;
2076 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2077 invalidate_live_intervals();
2082 this->alloc
.count
= new_index
;
2084 /* Patch all the instructions to use the newly renumbered registers */
2085 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2086 if (inst
->dst
.file
== VGRF
)
2087 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
2089 for (int i
= 0; i
< inst
->sources
; i
++) {
2090 if (inst
->src
[i
].file
== VGRF
)
2091 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
2095 /* Patch all the references to delta_xy, since they're used in register
2096 * allocation. If they're unused, switch them to BAD_FILE so we don't
2097 * think some random VGRF is delta_xy.
2099 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2100 if (delta_xy
[i
].file
== VGRF
) {
2101 if (remap_table
[delta_xy
[i
].nr
] != -1) {
2102 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2104 delta_xy
[i
].file
= BAD_FILE
;
2109 delete[] remap_table
;
2115 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
2117 if (prog_data
->nr_params
== 0)
2120 /* The local thread id is always the last parameter in the list */
2121 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
2122 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
2123 return prog_data
->nr_params
- 1;
2129 * Struct for handling complex alignments.
2131 * A complex alignment is stored as multiplier and an offset. A value is
2132 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
2133 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
2136 * N | cplx_align_apply({8, 2}, N)
2137 * ----+-----------------------------
2151 #define CPLX_ALIGN_MAX_MUL 8
2154 cplx_align_assert_sane(struct cplx_align a
)
2156 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
2157 assert(a
.offset
< a
.mul
);
2161 * Combines two alignments to produce a least multiple of sorts.
2163 * The returned alignment is the smallest (in terms of multiplier) such that
2164 * anything aligned to both a and b will be aligned to the new alignment.
2165 * This function will assert-fail if a and b are not compatible, i.e. if the
2166 * offset parameters are such that no common alignment is possible.
2168 static struct cplx_align
2169 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2171 cplx_align_assert_sane(a
);
2172 cplx_align_assert_sane(b
);
2174 /* Assert that the alignments agree. */
2175 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2177 return a
.mul
> b
.mul
? a
: b
;
2181 * Apply a complex alignment
2183 * This function will return the smallest number greater than or equal to
2184 * offset that is aligned to align.
2187 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2189 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2192 #define UNIFORM_SLOT_SIZE 4
2194 struct uniform_slot_info
{
2195 /** True if the given uniform slot is live */
2198 /** True if this slot and the next slot must remain contiguous */
2199 unsigned contiguous
:1;
2201 struct cplx_align align
;
2205 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2206 unsigned num_slots
, unsigned alignment
)
2208 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2209 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2211 /* We can't align a slot to anything less than the slot size */
2212 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2214 struct cplx_align align
= {alignment
, 0};
2215 cplx_align_assert_sane(align
);
2217 for (unsigned i
= 0; i
< num_slots
; i
++) {
2218 slots
[i
].is_live
= true;
2219 if (i
< num_slots
- 1)
2220 slots
[i
].contiguous
= true;
2222 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2223 if (slots
[i
].align
.mul
== 0) {
2224 slots
[i
].align
= align
;
2226 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2232 * Assign UNIFORM file registers to either push constants or pull constants.
2234 * We allow a fragment shader to have more than the specified minimum
2235 * maximum number of fragment shader uniform components (64). If
2236 * there are too many of these, they'd fill up all of register space.
2237 * So, this will push some of them out to the pull constant buffer and
2238 * update the program to load them.
2241 fs_visitor::assign_constant_locations()
2243 /* Only the first compile gets to decide on locations. */
2244 if (push_constant_loc
) {
2245 assert(pull_constant_loc
);
2249 if (compiler
->compact_params
) {
2250 struct uniform_slot_info slots
[uniforms
];
2251 memset(slots
, 0, sizeof(slots
));
2253 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2254 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2255 if (inst
->src
[i
].file
!= UNIFORM
)
2258 /* NIR tightly packs things so the uniform number might not be
2259 * aligned (if we have a double right after a float, for
2260 * instance). This is fine because the process of re-arranging
2261 * them will ensure that things are properly aligned. The offset
2262 * into that uniform, however, must be aligned.
2264 * In Vulkan, we have explicit offsets but everything is crammed
2265 * into a single "variable" so inst->src[i].nr will always be 0.
2266 * Everything will be properly aligned relative to that one base.
2268 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2270 unsigned u
= inst
->src
[i
].nr
+
2271 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2276 unsigned slots_read
;
2277 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2278 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2280 unsigned bytes_read
= inst
->components_read(i
) *
2281 type_sz(inst
->src
[i
].type
);
2282 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2285 assert(u
+ slots_read
<= uniforms
);
2286 mark_uniform_slots_read(&slots
[u
], slots_read
,
2287 type_sz(inst
->src
[i
].type
));
2291 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2293 /* Only allow 16 registers (128 uniform components) as push constants.
2295 * Just demote the end of the list. We could probably do better
2296 * here, demoting things that are rarely used in the program first.
2298 * If changing this value, note the limitation about total_regs in
2301 unsigned int max_push_components
= 16 * 8;
2302 if (subgroup_id_index
>= 0)
2303 max_push_components
--; /* Save a slot for the thread ID */
2305 /* We push small arrays, but no bigger than 16 floats. This is big
2306 * enough for a vec4 but hopefully not large enough to push out other
2307 * stuff. We should probably use a better heuristic at some point.
2309 const unsigned int max_chunk_size
= 16;
2311 unsigned int num_push_constants
= 0;
2312 unsigned int num_pull_constants
= 0;
2314 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2315 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2317 /* Default to -1 meaning no location */
2318 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2319 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2321 int chunk_start
= -1;
2322 struct cplx_align align
;
2323 for (unsigned u
= 0; u
< uniforms
; u
++) {
2324 if (!slots
[u
].is_live
) {
2325 assert(chunk_start
== -1);
2329 /* Skip subgroup_id_index to put it in the last push register. */
2330 if (subgroup_id_index
== (int)u
)
2333 if (chunk_start
== -1) {
2335 align
= slots
[u
].align
;
2337 /* Offset into the chunk */
2338 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2340 /* Shift the slot alignment down by the chunk offset so it is
2341 * comparable with the base chunk alignment.
2343 struct cplx_align slot_align
= slots
[u
].align
;
2345 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2347 align
= cplx_align_combine(align
, slot_align
);
2350 /* Sanity check the alignment */
2351 cplx_align_assert_sane(align
);
2353 if (slots
[u
].contiguous
)
2356 /* Adjust the alignment to be in terms of slots, not bytes */
2357 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2358 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2359 align
.mul
/= UNIFORM_SLOT_SIZE
;
2360 align
.offset
/= UNIFORM_SLOT_SIZE
;
2362 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2363 unsigned chunk_size
= u
- chunk_start
+ 1;
2364 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2365 (chunk_size
< max_chunk_size
&&
2366 push_start_align
+ chunk_size
<= max_push_components
)) {
2367 /* Align up the number of push constants */
2368 num_push_constants
= push_start_align
;
2369 for (unsigned i
= 0; i
< chunk_size
; i
++)
2370 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2372 /* We need to pull this one */
2373 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2374 for (unsigned i
= 0; i
< chunk_size
; i
++)
2375 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2378 /* Reset the chunk and start again */
2382 /* Add the CS local thread ID uniform at the end of the push constants */
2383 if (subgroup_id_index
>= 0)
2384 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2386 /* As the uniforms are going to be reordered, stash the old array and
2387 * create two new arrays for push/pull params.
2389 uint32_t *param
= stage_prog_data
->param
;
2390 stage_prog_data
->nr_params
= num_push_constants
;
2391 if (num_push_constants
) {
2392 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2393 num_push_constants
);
2395 stage_prog_data
->param
= NULL
;
2397 assert(stage_prog_data
->nr_pull_params
== 0);
2398 assert(stage_prog_data
->pull_param
== NULL
);
2399 if (num_pull_constants
> 0) {
2400 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2401 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2402 num_pull_constants
);
2405 /* Up until now, the param[] array has been indexed by reg + offset
2406 * of UNIFORM registers. Move pull constants into pull_param[] and
2407 * condense param[] to only contain the uniforms we chose to push.
2409 * NOTE: Because we are condensing the params[] array, we know that
2410 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2411 * having to make a copy.
2413 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2414 uint32_t value
= param
[i
];
2415 if (pull_constant_loc
[i
] != -1) {
2416 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2417 } else if (push_constant_loc
[i
] != -1) {
2418 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2423 /* If we don't want to compact anything, just set up dummy push/pull
2424 * arrays. All the rest of the compiler cares about are these arrays.
2426 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2427 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2429 for (unsigned u
= 0; u
< uniforms
; u
++)
2430 push_constant_loc
[u
] = u
;
2432 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2435 /* Now that we know how many regular uniforms we'll push, reduce the
2436 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2438 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2439 for (int i
= 0; i
< 4; i
++) {
2440 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2442 if (push_length
+ range
->length
> 64)
2443 range
->length
= 64 - push_length
;
2445 push_length
+= range
->length
;
2447 assert(push_length
<= 64);
2451 fs_visitor::get_pull_locs(const fs_reg
&src
,
2452 unsigned *out_surf_index
,
2453 unsigned *out_pull_index
)
2455 assert(src
.file
== UNIFORM
);
2457 if (src
.nr
>= UBO_START
) {
2458 const struct brw_ubo_range
*range
=
2459 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2461 /* If this access is in our (reduced) range, use the push data. */
2462 if (src
.offset
/ 32 < range
->length
)
2465 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2466 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2468 prog_data
->has_ubo_pull
= true;
2472 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2474 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2475 /* A regular uniform push constant */
2476 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2477 *out_pull_index
= pull_constant_loc
[location
];
2479 prog_data
->has_ubo_pull
= true;
2487 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2488 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2491 fs_visitor::lower_constant_loads()
2493 unsigned index
, pull_index
;
2495 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2496 /* Set up the annotation tracking for new generated instructions. */
2497 const fs_builder
ibld(this, block
, inst
);
2499 for (int i
= 0; i
< inst
->sources
; i
++) {
2500 if (inst
->src
[i
].file
!= UNIFORM
)
2503 /* We'll handle this case later */
2504 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2507 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2510 assert(inst
->src
[i
].stride
== 0);
2512 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2513 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2514 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2515 const unsigned base
= pull_index
* 4;
2517 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2518 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2520 /* Rewrite the instruction to use the temporary VGRF. */
2521 inst
->src
[i
].file
= VGRF
;
2522 inst
->src
[i
].nr
= dst
.nr
;
2523 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2524 inst
->src
[i
].offset
% 4;
2527 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2528 inst
->src
[0].file
== UNIFORM
) {
2530 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2533 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2537 inst
->remove(block
);
2540 invalidate_live_intervals();
2544 fs_visitor::opt_algebraic()
2546 bool progress
= false;
2548 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2549 switch (inst
->opcode
) {
2550 case BRW_OPCODE_MOV
:
2551 if (!devinfo
->has_64bit_float
&&
2552 !devinfo
->has_64bit_int
&&
2553 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2554 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2555 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2556 assert(inst
->dst
.type
== inst
->src
[0].type
);
2557 assert(!inst
->saturate
);
2558 assert(!inst
->src
[0].abs
);
2559 assert(!inst
->src
[0].negate
);
2560 const brw::fs_builder
ibld(this, block
, inst
);
2562 if (inst
->src
[0].file
== IMM
) {
2563 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2564 brw_imm_ud(inst
->src
[0].u64
>> 32));
2565 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2566 brw_imm_ud(inst
->src
[0].u64
));
2568 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2569 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1));
2570 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2571 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0));
2574 inst
->remove(block
);
2578 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2579 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2580 inst
->dst
.is_null() &&
2581 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2582 inst
->src
[0].abs
= false;
2583 inst
->src
[0].negate
= false;
2588 if (inst
->src
[0].file
!= IMM
)
2591 if (inst
->saturate
) {
2592 /* Full mixed-type saturates don't happen. However, we can end up
2595 * mov.sat(8) g21<1>DF -1F
2597 * Other mixed-size-but-same-base-type cases may also be possible.
2599 if (inst
->dst
.type
!= inst
->src
[0].type
&&
2600 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
2601 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2602 assert(!"unimplemented: saturate mixed types");
2604 if (brw_saturate_immediate(inst
->src
[0].type
,
2605 &inst
->src
[0].as_brw_reg())) {
2606 inst
->saturate
= false;
2612 case BRW_OPCODE_MUL
:
2613 if (inst
->src
[1].file
!= IMM
)
2617 if (inst
->src
[1].is_one()) {
2618 inst
->opcode
= BRW_OPCODE_MOV
;
2619 inst
->src
[1] = reg_undef
;
2625 if (inst
->src
[1].is_negative_one()) {
2626 inst
->opcode
= BRW_OPCODE_MOV
;
2627 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2628 inst
->src
[1] = reg_undef
;
2633 if (inst
->src
[0].file
== IMM
) {
2634 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2635 inst
->opcode
= BRW_OPCODE_MOV
;
2636 inst
->src
[0].f
*= inst
->src
[1].f
;
2637 inst
->src
[1] = reg_undef
;
2642 case BRW_OPCODE_ADD
:
2643 if (inst
->src
[1].file
!= IMM
)
2646 if (inst
->src
[0].file
== IMM
) {
2647 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2648 inst
->opcode
= BRW_OPCODE_MOV
;
2649 inst
->src
[0].f
+= inst
->src
[1].f
;
2650 inst
->src
[1] = reg_undef
;
2656 if (inst
->src
[0].equals(inst
->src
[1]) ||
2657 inst
->src
[1].is_zero()) {
2658 /* On Gen8+, the OR instruction can have a source modifier that
2659 * performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
2660 * or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
2662 if (inst
->src
[0].negate
) {
2663 inst
->opcode
= BRW_OPCODE_NOT
;
2664 inst
->src
[0].negate
= false;
2666 inst
->opcode
= BRW_OPCODE_MOV
;
2668 inst
->src
[1] = reg_undef
;
2673 case BRW_OPCODE_CMP
:
2674 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2675 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2676 inst
->src
[1].is_zero() &&
2677 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2678 inst
->src
[0].abs
= false;
2679 inst
->src
[0].negate
= false;
2684 case BRW_OPCODE_SEL
:
2685 if (!devinfo
->has_64bit_float
&&
2686 !devinfo
->has_64bit_int
&&
2687 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2688 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2689 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2690 assert(inst
->dst
.type
== inst
->src
[0].type
);
2691 assert(!inst
->saturate
);
2692 assert(!inst
->src
[0].abs
&& !inst
->src
[0].negate
);
2693 assert(!inst
->src
[1].abs
&& !inst
->src
[1].negate
);
2694 const brw::fs_builder
ibld(this, block
, inst
);
2696 set_predicate(inst
->predicate
,
2697 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2698 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
2699 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0)));
2700 set_predicate(inst
->predicate
,
2701 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2702 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
2703 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1)));
2705 inst
->remove(block
);
2708 if (inst
->src
[0].equals(inst
->src
[1])) {
2709 inst
->opcode
= BRW_OPCODE_MOV
;
2710 inst
->src
[1] = reg_undef
;
2711 inst
->predicate
= BRW_PREDICATE_NONE
;
2712 inst
->predicate_inverse
= false;
2714 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2715 switch (inst
->conditional_mod
) {
2716 case BRW_CONDITIONAL_LE
:
2717 case BRW_CONDITIONAL_L
:
2718 switch (inst
->src
[1].type
) {
2719 case BRW_REGISTER_TYPE_F
:
2720 if (inst
->src
[1].f
>= 1.0f
) {
2721 inst
->opcode
= BRW_OPCODE_MOV
;
2722 inst
->src
[1] = reg_undef
;
2723 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2731 case BRW_CONDITIONAL_GE
:
2732 case BRW_CONDITIONAL_G
:
2733 switch (inst
->src
[1].type
) {
2734 case BRW_REGISTER_TYPE_F
:
2735 if (inst
->src
[1].f
<= 0.0f
) {
2736 inst
->opcode
= BRW_OPCODE_MOV
;
2737 inst
->src
[1] = reg_undef
;
2738 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2750 case BRW_OPCODE_MAD
:
2751 if (inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
2752 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
2753 inst
->src
[2].type
!= BRW_REGISTER_TYPE_F
)
2755 if (inst
->src
[1].is_one()) {
2756 inst
->opcode
= BRW_OPCODE_ADD
;
2757 inst
->src
[1] = inst
->src
[2];
2758 inst
->src
[2] = reg_undef
;
2760 } else if (inst
->src
[2].is_one()) {
2761 inst
->opcode
= BRW_OPCODE_ADD
;
2762 inst
->src
[2] = reg_undef
;
2766 case SHADER_OPCODE_BROADCAST
:
2767 if (is_uniform(inst
->src
[0])) {
2768 inst
->opcode
= BRW_OPCODE_MOV
;
2770 inst
->force_writemask_all
= true;
2772 } else if (inst
->src
[1].file
== IMM
) {
2773 inst
->opcode
= BRW_OPCODE_MOV
;
2774 /* It's possible that the selected component will be too large and
2775 * overflow the register. This can happen if someone does a
2776 * readInvocation() from GLSL or SPIR-V and provides an OOB
2777 * invocationIndex. If this happens and we some how manage
2778 * to constant fold it in and get here, then component() may cause
2779 * us to start reading outside of the VGRF which will lead to an
2780 * assert later. Instead, just let it wrap around if it goes over
2783 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2784 inst
->src
[0] = component(inst
->src
[0], comp
);
2786 inst
->force_writemask_all
= true;
2791 case SHADER_OPCODE_SHUFFLE
:
2792 if (is_uniform(inst
->src
[0])) {
2793 inst
->opcode
= BRW_OPCODE_MOV
;
2796 } else if (inst
->src
[1].file
== IMM
) {
2797 inst
->opcode
= BRW_OPCODE_MOV
;
2798 inst
->src
[0] = component(inst
->src
[0],
2809 /* Swap if src[0] is immediate. */
2810 if (progress
&& inst
->is_commutative()) {
2811 if (inst
->src
[0].file
== IMM
) {
2812 fs_reg tmp
= inst
->src
[1];
2813 inst
->src
[1] = inst
->src
[0];
2822 * Optimize sample messages that have constant zero values for the trailing
2823 * texture coordinates. We can just reduce the message length for these
2824 * instructions instead of reserving a register for it. Trailing parameters
2825 * that aren't sent default to zero anyway. This will cause the dead code
2826 * eliminator to remove the MOV instruction that would otherwise be emitted to
2827 * set up the zero value.
2830 fs_visitor::opt_zero_samples()
2832 /* Gen4 infers the texturing opcode based on the message length so we can't
2835 if (devinfo
->gen
< 5)
2838 bool progress
= false;
2840 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2841 if (!inst
->is_tex())
2844 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2846 if (load_payload
->is_head_sentinel() ||
2847 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2850 /* We don't want to remove the message header or the first parameter.
2851 * Removing the first parameter is not allowed, see the Haswell PRM
2852 * volume 7, page 149:
2854 * "Parameter 0 is required except for the sampleinfo message, which
2855 * has no parameter 0"
2857 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2858 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2859 (inst
->exec_size
/ 8) +
2860 inst
->header_size
- 1].is_zero()) {
2861 inst
->mlen
-= inst
->exec_size
/ 8;
2867 invalidate_live_intervals();
2873 * Optimize sample messages which are followed by the final RT write.
2875 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2876 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2877 * final texturing results copied to the framebuffer write payload and modify
2878 * them to write to the framebuffer directly.
2881 fs_visitor::opt_sampler_eot()
2883 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2885 if (stage
!= MESA_SHADER_FRAGMENT
|| dispatch_width
> 16)
2888 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2891 /* FINISHME: It should be possible to implement this optimization when there
2892 * are multiple drawbuffers.
2894 if (key
->nr_color_regions
!= 1)
2897 /* Requires emitting a bunch of saturating MOV instructions during logical
2898 * send lowering to clamp the color payload, which the sampler unit isn't
2899 * going to do for us.
2901 if (key
->clamp_fragment_color
)
2904 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2905 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2906 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2907 assert(fb_write
->eot
);
2908 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2910 /* There wasn't one; nothing to do. */
2911 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2914 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2916 /* 3D Sampler » Messages » Message Format
2918 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2919 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2921 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2922 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2923 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2924 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2925 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2926 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2927 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2928 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2931 /* XXX - This shouldn't be necessary. */
2932 if (tex_inst
->prev
->is_head_sentinel())
2935 /* Check that the FB write sources are fully initialized by the single
2936 * texturing instruction.
2938 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2939 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2940 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2941 fb_write
->size_read(i
) != tex_inst
->size_written
)
2943 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2944 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2949 assert(!tex_inst
->eot
); /* We can't get here twice */
2950 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2952 const fs_builder
ibld(this, block
, tex_inst
);
2954 tex_inst
->offset
|= fb_write
->target
<< 24;
2955 tex_inst
->eot
= true;
2956 tex_inst
->dst
= ibld
.null_reg_ud();
2957 tex_inst
->size_written
= 0;
2958 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2960 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2961 * flag and submit a header together with the sampler message as required
2964 invalidate_live_intervals();
2969 fs_visitor::opt_register_renaming()
2971 bool progress
= false;
2974 unsigned remap
[alloc
.count
];
2975 memset(remap
, ~0u, sizeof(unsigned) * alloc
.count
);
2977 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2978 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2980 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2981 inst
->opcode
== BRW_OPCODE_WHILE
) {
2985 /* Rewrite instruction sources. */
2986 for (int i
= 0; i
< inst
->sources
; i
++) {
2987 if (inst
->src
[i
].file
== VGRF
&&
2988 remap
[inst
->src
[i
].nr
] != ~0u &&
2989 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2990 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2995 const unsigned dst
= inst
->dst
.nr
;
2998 inst
->dst
.file
== VGRF
&&
2999 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
3000 !inst
->is_partial_write()) {
3001 if (remap
[dst
] == ~0u) {
3004 remap
[dst
] = alloc
.allocate(regs_written(inst
));
3005 inst
->dst
.nr
= remap
[dst
];
3008 } else if (inst
->dst
.file
== VGRF
&&
3009 remap
[dst
] != ~0u &&
3010 remap
[dst
] != dst
) {
3011 inst
->dst
.nr
= remap
[dst
];
3017 invalidate_live_intervals();
3019 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
3020 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != ~0u) {
3021 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
3030 * Remove redundant or useless discard jumps.
3032 * For example, we can eliminate jumps in the following sequence:
3034 * discard-jump (redundant with the next jump)
3035 * discard-jump (useless; jumps to the next instruction)
3039 fs_visitor::opt_redundant_discard_jumps()
3041 bool progress
= false;
3043 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
3045 fs_inst
*placeholder_halt
= NULL
;
3046 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
3047 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
3048 placeholder_halt
= inst
;
3053 if (!placeholder_halt
)
3056 /* Delete any HALTs immediately before the placeholder halt. */
3057 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
3058 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
3059 prev
= (fs_inst
*) placeholder_halt
->prev
) {
3060 prev
->remove(last_bblock
);
3065 invalidate_live_intervals();
3071 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
3072 * from \p r.offset which overlaps the region starting at \p s.offset and
3073 * spanning \p ds bytes.
3075 static inline unsigned
3076 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
3078 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
3079 const int shift
= rel_offset
/ REG_SIZE
;
3080 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
3081 assert(reg_space(r
) == reg_space(s
) &&
3082 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
3083 return ((1 << n
) - 1) << shift
;
3087 fs_visitor::compute_to_mrf()
3089 bool progress
= false;
3092 /* No MRFs on Gen >= 7. */
3093 if (devinfo
->gen
>= 7)
3096 calculate_live_intervals();
3098 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3102 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3103 inst
->is_partial_write() ||
3104 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
3105 inst
->dst
.type
!= inst
->src
[0].type
||
3106 inst
->src
[0].abs
|| inst
->src
[0].negate
||
3107 !inst
->src
[0].is_contiguous() ||
3108 inst
->src
[0].offset
% REG_SIZE
!= 0)
3111 /* Can't compute-to-MRF this GRF if someone else was going to
3114 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
3117 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3118 * things that computed the value of all GRFs of the source region. The
3119 * regs_left bitset keeps track of the registers we haven't yet found a
3120 * generating instruction for.
3122 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3124 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3125 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3126 inst
->src
[0], inst
->size_read(0))) {
3127 /* Found the last thing to write our reg we want to turn
3128 * into a compute-to-MRF.
3131 /* If this one instruction didn't populate all the
3132 * channels, bail. We might be able to rewrite everything
3133 * that writes that reg, but it would require smarter
3136 if (scan_inst
->is_partial_write())
3139 /* Handling things not fully contained in the source of the copy
3140 * would need us to understand coalescing out more than one MOV at
3143 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3144 inst
->src
[0], inst
->size_read(0)))
3147 /* SEND instructions can't have MRF as a destination. */
3148 if (scan_inst
->mlen
)
3151 if (devinfo
->gen
== 6) {
3152 /* gen6 math instructions must have the destination be
3153 * GRF, so no compute-to-MRF for them.
3155 if (scan_inst
->is_math()) {
3160 /* Clear the bits for any registers this instruction overwrites. */
3161 regs_left
&= ~mask_relative_to(
3162 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3167 /* We don't handle control flow here. Most computation of
3168 * values that end up in MRFs are shortly before the MRF
3171 if (block
->start() == scan_inst
)
3174 /* You can't read from an MRF, so if someone else reads our
3175 * MRF's source GRF that we wanted to rewrite, that stops us.
3177 bool interfered
= false;
3178 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3179 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3180 inst
->src
[0], inst
->size_read(0))) {
3187 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3188 inst
->dst
, inst
->size_written
)) {
3189 /* If somebody else writes our MRF here, we can't
3190 * compute-to-MRF before that.
3195 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3196 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3197 inst
->dst
, inst
->size_written
)) {
3198 /* Found a SEND instruction, which means that there are
3199 * live values in MRFs from base_mrf to base_mrf +
3200 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3210 /* Found all generating instructions of our MRF's source value, so it
3211 * should be safe to rewrite them to point to the MRF directly.
3213 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3215 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3216 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3217 inst
->src
[0], inst
->size_read(0))) {
3218 /* Clear the bits for any registers this instruction overwrites. */
3219 regs_left
&= ~mask_relative_to(
3220 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3222 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3223 reg_offset(inst
->src
[0]);
3225 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3226 /* Apply the same address transformation done by the hardware
3227 * for COMPR4 MRF writes.
3229 assert(rel_offset
< 2 * REG_SIZE
);
3230 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3232 /* Clear the COMPR4 bit if the generating instruction is not
3235 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3236 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3239 /* Calculate the MRF number the result of this instruction is
3240 * ultimately written to.
3242 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3245 scan_inst
->dst
.file
= MRF
;
3246 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3247 scan_inst
->saturate
|= inst
->saturate
;
3254 inst
->remove(block
);
3259 invalidate_live_intervals();
3265 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3266 * flow. We could probably do better here with some form of divergence
3270 fs_visitor::eliminate_find_live_channel()
3272 bool progress
= false;
3275 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3276 /* The optimization below assumes that channel zero is live on thread
3277 * dispatch, which may not be the case if the fixed function dispatches
3283 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3284 switch (inst
->opcode
) {
3290 case BRW_OPCODE_ENDIF
:
3291 case BRW_OPCODE_WHILE
:
3295 case FS_OPCODE_DISCARD_JUMP
:
3296 /* This can potentially make control flow non-uniform until the end
3301 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3303 inst
->opcode
= BRW_OPCODE_MOV
;
3304 inst
->src
[0] = brw_imm_ud(0u);
3306 inst
->force_writemask_all
= true;
3320 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3321 * instructions to FS_OPCODE_REP_FB_WRITE.
3324 fs_visitor::emit_repclear_shader()
3326 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3328 int color_mrf
= base_mrf
+ 2;
3332 mov
= bld
.exec_all().group(4, 0)
3333 .MOV(brw_message_reg(color_mrf
),
3334 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3336 struct brw_reg reg
=
3337 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3338 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3339 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3341 mov
= bld
.exec_all().group(4, 0)
3342 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3345 fs_inst
*write
= NULL
;
3346 if (key
->nr_color_regions
== 1) {
3347 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3348 write
->saturate
= key
->clamp_fragment_color
;
3349 write
->base_mrf
= color_mrf
;
3351 write
->header_size
= 0;
3354 assume(key
->nr_color_regions
> 0);
3356 struct brw_reg header
=
3357 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3358 bld
.exec_all().group(16, 0)
3359 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3361 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3363 bld
.exec_all().group(1, 0)
3364 .MOV(component(header
, 2), brw_imm_ud(i
));
3367 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3368 write
->saturate
= key
->clamp_fragment_color
;
3369 write
->base_mrf
= base_mrf
;
3371 write
->header_size
= 2;
3376 write
->last_rt
= true;
3380 assign_constant_locations();
3381 assign_curb_setup();
3383 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3385 assert(mov
->src
[0].file
== FIXED_GRF
);
3386 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3393 * Walks through basic blocks, looking for repeated MRF writes and
3394 * removing the later ones.
3397 fs_visitor::remove_duplicate_mrf_writes()
3399 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3400 bool progress
= false;
3402 /* Need to update the MRF tracking for compressed instructions. */
3403 if (dispatch_width
>= 16)
3406 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3408 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3409 if (inst
->is_control_flow()) {
3410 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3413 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3414 inst
->dst
.file
== MRF
) {
3415 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3416 if (prev_inst
&& prev_inst
->opcode
== BRW_OPCODE_MOV
&&
3417 inst
->dst
.equals(prev_inst
->dst
) &&
3418 inst
->src
[0].equals(prev_inst
->src
[0]) &&
3419 inst
->saturate
== prev_inst
->saturate
&&
3420 inst
->predicate
== prev_inst
->predicate
&&
3421 inst
->conditional_mod
== prev_inst
->conditional_mod
&&
3422 inst
->exec_size
== prev_inst
->exec_size
) {
3423 inst
->remove(block
);
3429 /* Clear out the last-write records for MRFs that were overwritten. */
3430 if (inst
->dst
.file
== MRF
) {
3431 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3434 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3435 /* Found a SEND instruction, which will include two or fewer
3436 * implied MRF writes. We could do better here.
3438 for (unsigned i
= 0; i
< inst
->implied_mrf_writes(); i
++) {
3439 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3443 /* Clear out any MRF move records whose sources got overwritten. */
3444 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3445 if (last_mrf_move
[i
] &&
3446 regions_overlap(inst
->dst
, inst
->size_written
,
3447 last_mrf_move
[i
]->src
[0],
3448 last_mrf_move
[i
]->size_read(0))) {
3449 last_mrf_move
[i
] = NULL
;
3453 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3454 inst
->dst
.file
== MRF
&&
3455 inst
->src
[0].file
!= ARF
&&
3456 !inst
->is_partial_write()) {
3457 last_mrf_move
[inst
->dst
.nr
] = inst
;
3462 invalidate_live_intervals();
3468 * Rounding modes for conversion instructions are included for each
3469 * conversion, but right now it is a state. So once it is set,
3470 * we don't need to call it again for subsequent calls.
3472 * This is useful for vector/matrices conversions, as setting the
3473 * mode once is enough for the full vector/matrix
3476 fs_visitor::remove_extra_rounding_modes()
3478 bool progress
= false;
3479 unsigned execution_mode
= this->nir
->info
.float_controls_execution_mode
;
3481 brw_rnd_mode base_mode
= BRW_RND_MODE_UNSPECIFIED
;
3482 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
|
3483 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
|
3484 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
) &
3486 base_mode
= BRW_RND_MODE_RTNE
;
3487 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
|
3488 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
|
3489 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
) &
3491 base_mode
= BRW_RND_MODE_RTZ
;
3493 foreach_block (block
, cfg
) {
3494 brw_rnd_mode prev_mode
= base_mode
;
3496 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3497 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3498 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3499 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3500 if (mode
== prev_mode
) {
3501 inst
->remove(block
);
3511 invalidate_live_intervals();
3517 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3519 /* Clear the flag for registers that actually got read (as expected). */
3520 for (int i
= 0; i
< inst
->sources
; i
++) {
3522 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3523 grf
= inst
->src
[i
].nr
;
3528 if (grf
>= first_grf
&&
3529 grf
< first_grf
+ grf_len
) {
3530 deps
[grf
- first_grf
] = false;
3531 if (inst
->exec_size
== 16)
3532 deps
[grf
- first_grf
+ 1] = false;
3538 * Implements this workaround for the original 965:
3540 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3541 * check for post destination dependencies on this instruction, software
3542 * must ensure that there is no destination hazard for the case of ‘write
3543 * followed by a posted write’ shown in the following example.
3546 * 2. send r3.xy <rest of send instruction>
3549 * Due to no post-destination dependency check on the ‘send’, the above
3550 * code sequence could have two instructions (1 and 2) in flight at the
3551 * same time that both consider ‘r3’ as the target of their final writes.
3554 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3557 int write_len
= regs_written(inst
);
3558 int first_write_grf
= inst
->dst
.nr
;
3559 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3560 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3562 memset(needs_dep
, false, sizeof(needs_dep
));
3563 memset(needs_dep
, true, write_len
);
3565 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3567 /* Walk backwards looking for writes to registers we're writing which
3568 * aren't read since being written. If we hit the start of the program,
3569 * we assume that there are no outstanding dependencies on entry to the
3572 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3573 /* If we hit control flow, assume that there *are* outstanding
3574 * dependencies, and force their cleanup before our instruction.
3576 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3577 for (int i
= 0; i
< write_len
; i
++) {
3579 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3580 first_write_grf
+ i
);
3585 /* We insert our reads as late as possible on the assumption that any
3586 * instruction but a MOV that might have left us an outstanding
3587 * dependency has more latency than a MOV.
3589 if (scan_inst
->dst
.file
== VGRF
) {
3590 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3591 int reg
= scan_inst
->dst
.nr
+ i
;
3593 if (reg
>= first_write_grf
&&
3594 reg
< first_write_grf
+ write_len
&&
3595 needs_dep
[reg
- first_write_grf
]) {
3596 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3597 needs_dep
[reg
- first_write_grf
] = false;
3598 if (scan_inst
->exec_size
== 16)
3599 needs_dep
[reg
- first_write_grf
+ 1] = false;
3604 /* Clear the flag for registers that actually got read (as expected). */
3605 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3607 /* Continue the loop only if we haven't resolved all the dependencies */
3609 for (i
= 0; i
< write_len
; i
++) {
3619 * Implements this workaround for the original 965:
3621 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3622 * used as a destination register until after it has been sourced by an
3623 * instruction with a different destination register.
3626 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3628 int write_len
= regs_written(inst
);
3629 unsigned first_write_grf
= inst
->dst
.nr
;
3630 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3631 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3633 memset(needs_dep
, false, sizeof(needs_dep
));
3634 memset(needs_dep
, true, write_len
);
3635 /* Walk forwards looking for writes to registers we're writing which aren't
3636 * read before being written.
3638 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3639 /* If we hit control flow, force resolve all remaining dependencies. */
3640 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3641 for (int i
= 0; i
< write_len
; i
++) {
3643 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3644 first_write_grf
+ i
);
3649 /* Clear the flag for registers that actually got read (as expected). */
3650 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3652 /* We insert our reads as late as possible since they're reading the
3653 * result of a SEND, which has massive latency.
3655 if (scan_inst
->dst
.file
== VGRF
&&
3656 scan_inst
->dst
.nr
>= first_write_grf
&&
3657 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3658 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3659 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3661 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3664 /* Continue the loop only if we haven't resolved all the dependencies */
3666 for (i
= 0; i
< write_len
; i
++) {
3676 fs_visitor::insert_gen4_send_dependency_workarounds()
3678 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3681 bool progress
= false;
3683 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3684 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3685 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3686 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3692 invalidate_live_intervals();
3696 * Turns the generic expression-style uniform pull constant load instruction
3697 * into a hardware-specific series of instructions for loading a pull
3700 * The expression style allows the CSE pass before this to optimize out
3701 * repeated loads from the same offset, and gives the pre-register-allocation
3702 * scheduling full flexibility, while the conversion to native instructions
3703 * allows the post-register-allocation scheduler the best information
3706 * Note that execution masking for setting up pull constant loads is special:
3707 * the channels that need to be written are unrelated to the current execution
3708 * mask, since a later instruction will use one of the result channels as a
3709 * source operand for all 8 or 16 of its channels.
3712 fs_visitor::lower_uniform_pull_constant_loads()
3714 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3715 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3718 if (devinfo
->gen
>= 7) {
3719 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3720 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3722 ubld
.group(8, 0).MOV(payload
,
3723 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3724 ubld
.group(1, 0).MOV(component(payload
, 2),
3725 brw_imm_ud(inst
->src
[1].ud
/ 16));
3727 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3728 inst
->src
[1] = payload
;
3729 inst
->header_size
= 1;
3732 invalidate_live_intervals();
3734 /* Before register allocation, we didn't tell the scheduler about the
3735 * MRF we use. We know it's safe to use this MRF because nothing
3736 * else does except for register spill/unspill, which generates and
3737 * uses its MRF within a single IR instruction.
3739 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3746 fs_visitor::lower_load_payload()
3748 bool progress
= false;
3750 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3751 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3754 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3755 assert(inst
->saturate
== false);
3756 fs_reg dst
= inst
->dst
;
3758 /* Get rid of COMPR4. We'll add it back in if we need it */
3759 if (dst
.file
== MRF
)
3760 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3762 const fs_builder
ibld(this, block
, inst
);
3763 const fs_builder ubld
= ibld
.exec_all();
3765 for (uint8_t i
= 0; i
< inst
->header_size
;) {
3766 /* Number of header GRFs to initialize at once with a single MOV
3770 (i
+ 1 < inst
->header_size
&& inst
->src
[i
].stride
== 1 &&
3771 inst
->src
[i
+ 1].equals(byte_offset(inst
->src
[i
], REG_SIZE
))) ?
3774 if (inst
->src
[i
].file
!= BAD_FILE
)
3775 ubld
.group(8 * n
, 0).MOV(retype(dst
, BRW_REGISTER_TYPE_UD
),
3776 retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
));
3778 dst
= byte_offset(dst
, n
* REG_SIZE
);
3782 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3783 inst
->exec_size
> 8) {
3784 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3785 * a straightforward copy. Instead, the result of the
3786 * LOAD_PAYLOAD is treated as interleaved and the first four
3787 * non-header sources are unpacked as:
3798 * This is used for gen <= 5 fb writes.
3800 assert(inst
->exec_size
== 16);
3801 assert(inst
->header_size
+ 4 <= inst
->sources
);
3802 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3803 if (inst
->src
[i
].file
!= BAD_FILE
) {
3804 if (devinfo
->has_compr4
) {
3805 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3806 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3807 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3809 /* Platform doesn't have COMPR4. We have to fake it */
3810 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3811 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3813 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3820 /* The loop above only ever incremented us through the first set
3821 * of 4 registers. However, thanks to the magic of COMPR4, we
3822 * actually wrote to the first 8 registers, so we need to take
3823 * that into account now.
3827 /* The COMPR4 code took care of the first 4 sources. We'll let
3828 * the regular path handle any remaining sources. Yes, we are
3829 * modifying the instruction but we're about to delete it so
3830 * this really doesn't hurt anything.
3832 inst
->header_size
+= 4;
3835 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3836 if (inst
->src
[i
].file
!= BAD_FILE
) {
3837 dst
.type
= inst
->src
[i
].type
;
3838 ibld
.MOV(dst
, inst
->src
[i
]);
3840 dst
.type
= BRW_REGISTER_TYPE_UD
;
3842 dst
= offset(dst
, ibld
, 1);
3845 inst
->remove(block
);
3850 invalidate_live_intervals();
3856 fs_visitor::lower_mul_dword_inst(fs_inst
*inst
, bblock_t
*block
)
3858 const fs_builder
ibld(this, block
, inst
);
3860 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3861 if (inst
->src
[1].file
== IMM
&&
3862 (( ud
&& inst
->src
[1].ud
<= UINT16_MAX
) ||
3863 (!ud
&& inst
->src
[1].d
<= INT16_MAX
&& inst
->src
[1].d
>= INT16_MIN
))) {
3864 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3865 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3868 * If multiplying by an immediate value that fits in 16-bits, do a
3869 * single MUL instruction with that value in the proper location.
3871 if (devinfo
->gen
< 7) {
3872 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8), inst
->dst
.type
);
3873 ibld
.MOV(imm
, inst
->src
[1]);
3874 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3876 ibld
.MUL(inst
->dst
, inst
->src
[0],
3877 ud
? brw_imm_uw(inst
->src
[1].ud
)
3878 : brw_imm_w(inst
->src
[1].d
));
3881 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3882 * do 32-bit integer multiplication in one instruction, but instead
3883 * must do a sequence (which actually calculates a 64-bit result):
3885 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3886 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3887 * mov(8) g2<1>D acc0<8,8,1>D
3889 * But on Gen > 6, the ability to use second accumulator register
3890 * (acc1) for non-float data types was removed, preventing a simple
3891 * implementation in SIMD16. A 16-channel result can be calculated by
3892 * executing the three instructions twice in SIMD8, once with quarter
3893 * control of 1Q for the first eight channels and again with 2Q for
3894 * the second eight channels.
3896 * Which accumulator register is implicitly accessed (by AccWrEnable
3897 * for instance) is determined by the quarter control. Unfortunately
3898 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3899 * implicit accumulator access by an instruction with 2Q will access
3900 * acc1 regardless of whether the data type is usable in acc1.
3902 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3903 * integer data types.
3905 * Since we only want the low 32-bits of the result, we can do two
3906 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3907 * adjust the high result and add them (like the mach is doing):
3909 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3910 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3911 * shl(8) g9<1>D g8<8,8,1>D 16D
3912 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3914 * We avoid the shl instruction by realizing that we only want to add
3915 * the low 16-bits of the "high" result to the high 16-bits of the
3916 * "low" result and using proper regioning on the add:
3918 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3919 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3920 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3922 * Since it does not use the (single) accumulator register, we can
3923 * schedule multi-component multiplications much better.
3926 bool needs_mov
= false;
3927 fs_reg orig_dst
= inst
->dst
;
3929 /* Get a new VGRF for the "low" 32x16-bit multiplication result if
3930 * reusing the original destination is impossible due to hardware
3931 * restrictions, source/destination overlap, or it being the null
3934 fs_reg low
= inst
->dst
;
3935 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3936 regions_overlap(inst
->dst
, inst
->size_written
,
3937 inst
->src
[0], inst
->size_read(0)) ||
3938 regions_overlap(inst
->dst
, inst
->size_written
,
3939 inst
->src
[1], inst
->size_read(1)) ||
3940 inst
->dst
.stride
>= 4) {
3942 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
3946 /* Get a new VGRF but keep the same stride as inst->dst */
3947 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)), inst
->dst
.type
);
3948 high
.stride
= inst
->dst
.stride
;
3949 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
3951 if (devinfo
->gen
>= 7) {
3952 if (inst
->src
[1].abs
)
3953 lower_src_modifiers(this, block
, inst
, 1);
3955 if (inst
->src
[1].file
== IMM
) {
3956 ibld
.MUL(low
, inst
->src
[0],
3957 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3958 ibld
.MUL(high
, inst
->src
[0],
3959 brw_imm_uw(inst
->src
[1].ud
>> 16));
3961 ibld
.MUL(low
, inst
->src
[0],
3962 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3963 ibld
.MUL(high
, inst
->src
[0],
3964 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3967 if (inst
->src
[0].abs
)
3968 lower_src_modifiers(this, block
, inst
, 0);
3970 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3972 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3976 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3977 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3978 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3980 if (needs_mov
|| inst
->conditional_mod
)
3981 set_condmod(inst
->conditional_mod
, ibld
.MOV(orig_dst
, low
));
3986 fs_visitor::lower_mul_qword_inst(fs_inst
*inst
, bblock_t
*block
)
3988 const fs_builder
ibld(this, block
, inst
);
3990 /* Considering two 64-bit integers ab and cd where each letter ab
3991 * corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd
3992 * only need to provide the YZ part of the result. -------
3994 * Only BD needs to be 64 bits. For AD and BC we only care + AD
3995 * about the lower 32 bits (since they are part of the upper + BC
3996 * 32 bits of our result). AC is not needed since it starts + AC
3997 * on the 65th bit of the result. -------
4000 unsigned int q_regs
= regs_written(inst
);
4001 unsigned int d_regs
= (q_regs
+ 1) / 2;
4003 fs_reg
bd(VGRF
, alloc
.allocate(q_regs
), BRW_REGISTER_TYPE_UQ
);
4004 fs_reg
ad(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4005 fs_reg
bc(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4007 /* Here we need the full 64 bit result for 32b * 32b. */
4008 if (devinfo
->has_integer_dword_mul
) {
4009 ibld
.MUL(bd
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4010 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4012 fs_reg
bd_high(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4013 fs_reg
bd_low(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4014 fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), BRW_REGISTER_TYPE_UD
);
4016 fs_inst
*mul
= ibld
.MUL(acc
,
4017 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4018 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4019 mul
->writes_accumulator
= true;
4021 ibld
.MACH(bd_high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4022 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4023 ibld
.MOV(bd_low
, acc
);
4025 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 0), bd_low
);
4026 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), bd_high
);
4029 ibld
.MUL(ad
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
4030 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4031 ibld
.MUL(bc
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4032 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1));
4034 ibld
.ADD(ad
, ad
, bc
);
4035 ibld
.ADD(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1),
4036 subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), ad
);
4038 ibld
.MOV(inst
->dst
, bd
);
4042 fs_visitor::lower_mulh_inst(fs_inst
*inst
, bblock_t
*block
)
4044 const fs_builder
ibld(this, block
, inst
);
4046 /* According to the BDW+ BSpec page for the "Multiply Accumulate
4047 * High" instruction:
4049 * "An added preliminary mov is required for source modification on
4051 * mov (8) r3.0<1>:d -r3<8;8,1>:d
4052 * mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
4053 * mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
4055 if (devinfo
->gen
>= 8 && (inst
->src
[1].negate
|| inst
->src
[1].abs
))
4056 lower_src_modifiers(this, block
, inst
, 1);
4058 /* Should have been lowered to 8-wide. */
4059 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
4060 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), inst
->dst
.type
);
4061 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
4062 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4064 if (devinfo
->gen
>= 8) {
4065 /* Until Gen8, integer multiplies read 32-bits from one source,
4066 * and 16-bits from the other, and relying on the MACH instruction
4067 * to generate the high bits of the result.
4069 * On Gen8, the multiply instruction does a full 32x32-bit
4070 * multiply, but in order to do a 64-bit multiply we can simulate
4071 * the previous behavior and then use a MACH instruction.
4073 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
4074 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
4075 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
4076 mul
->src
[1].stride
*= 2;
4078 if (mul
->src
[1].file
== IMM
) {
4079 mul
->src
[1] = brw_imm_uw(mul
->src
[1].ud
);
4081 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4083 /* Among other things the quarter control bits influence which
4084 * accumulator register is used by the hardware for instructions
4085 * that access the accumulator implicitly (e.g. MACH). A
4086 * second-half instruction would normally map to acc1, which
4087 * doesn't exist on Gen7 and up (the hardware does emulate it for
4088 * floating-point instructions *only* by taking advantage of the
4089 * extra precision of acc0 not normally used for floating point
4092 * HSW and up are careful enough not to try to access an
4093 * accumulator register that doesn't exist, but on earlier Gen7
4094 * hardware we need to make sure that the quarter control bits are
4095 * zero to avoid non-deterministic behaviour and emit an extra MOV
4096 * to get the result masked correctly according to the current
4100 mach
->force_writemask_all
= true;
4101 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
4102 ibld
.MOV(inst
->dst
, mach
->dst
);
4107 fs_visitor::lower_integer_multiplication()
4109 bool progress
= false;
4111 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4112 if (inst
->opcode
== BRW_OPCODE_MUL
) {
4113 /* If the instruction is already in a form that does not need lowering,
4116 if (devinfo
->gen
>= 7) {
4117 if (type_sz(inst
->src
[1].type
) < 4 && type_sz(inst
->src
[0].type
) <= 4)
4120 if (type_sz(inst
->src
[0].type
) < 4 && type_sz(inst
->src
[1].type
) <= 4)
4124 if ((inst
->dst
.type
== BRW_REGISTER_TYPE_Q
||
4125 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
) &&
4126 (inst
->src
[0].type
== BRW_REGISTER_TYPE_Q
||
4127 inst
->src
[0].type
== BRW_REGISTER_TYPE_UQ
) &&
4128 (inst
->src
[1].type
== BRW_REGISTER_TYPE_Q
||
4129 inst
->src
[1].type
== BRW_REGISTER_TYPE_UQ
)) {
4130 lower_mul_qword_inst(inst
, block
);
4131 inst
->remove(block
);
4133 } else if (!inst
->dst
.is_accumulator() &&
4134 (inst
->dst
.type
== BRW_REGISTER_TYPE_D
||
4135 inst
->dst
.type
== BRW_REGISTER_TYPE_UD
) &&
4136 !devinfo
->has_integer_dword_mul
) {
4137 lower_mul_dword_inst(inst
, block
);
4138 inst
->remove(block
);
4141 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
4142 lower_mulh_inst(inst
, block
);
4143 inst
->remove(block
);
4150 invalidate_live_intervals();
4156 fs_visitor::lower_minmax()
4158 assert(devinfo
->gen
< 6);
4160 bool progress
= false;
4162 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4163 const fs_builder
ibld(this, block
, inst
);
4165 if (inst
->opcode
== BRW_OPCODE_SEL
&&
4166 inst
->predicate
== BRW_PREDICATE_NONE
) {
4167 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
4168 * the original SEL.L/GE instruction
4170 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4171 inst
->conditional_mod
);
4172 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4173 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
4180 invalidate_live_intervals();
4186 fs_visitor::lower_sub_sat()
4188 bool progress
= false;
4190 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4191 const fs_builder
ibld(this, block
, inst
);
4193 if (inst
->opcode
== SHADER_OPCODE_USUB_SAT
||
4194 inst
->opcode
== SHADER_OPCODE_ISUB_SAT
) {
4195 /* The fundamental problem is the hardware performs source negation
4196 * at the bit width of the source. If the source is 0x80000000D, the
4197 * negation is 0x80000000D. As a result, subtractSaturate(0,
4198 * 0x80000000) will produce 0x80000000 instead of 0x7fffffff. There
4199 * are at least three ways to resolve this:
4201 * 1. Use the accumulator for the negated source. The accumulator is
4202 * 33 bits, so our source 0x80000000 is sign-extended to
4203 * 0x1800000000. The negation of which is 0x080000000. This
4204 * doesn't help for 64-bit integers (which are already bigger than
4205 * 33 bits). There are also only 8 accumulators, so SIMD16 or
4206 * SIMD32 instructions would have to be split into multiple SIMD8
4209 * 2. Use slightly different math. For any n-bit value x, we know (x
4210 * >> 1) != -(x >> 1). We can use this fact to only do
4211 * subtractions involving (x >> 1). subtractSaturate(a, b) ==
4212 * subtractSaturate(subtractSaturate(a, (b >> 1)), b - (b >> 1)).
4214 * 3. For unsigned sources, it is sufficient to replace the
4215 * subtractSaturate with (a > b) ? a - b : 0.
4217 * It may also be possible to use the SUBB instruction. This
4218 * implicitly writes the accumulator, so it could only be used in the
4219 * same situations as #1 above. It is further limited by only
4220 * allowing UD sources.
4222 if (inst
->exec_size
== 8 && inst
->src
[0].type
!= BRW_REGISTER_TYPE_Q
&&
4223 inst
->src
[0].type
!= BRW_REGISTER_TYPE_UQ
) {
4224 fs_reg
acc(ARF
, BRW_ARF_ACCUMULATOR
, inst
->src
[1].type
);
4226 ibld
.MOV(acc
, inst
->src
[1]);
4227 fs_inst
*add
= ibld
.ADD(inst
->dst
, acc
, inst
->src
[0]);
4228 add
->saturate
= true;
4229 add
->src
[0].negate
= true;
4230 } else if (inst
->opcode
== SHADER_OPCODE_ISUB_SAT
) {
4232 * dst = add.sat(add.sat(src0, -tmp), -(src1 - tmp));
4234 fs_reg tmp1
= ibld
.vgrf(inst
->src
[0].type
);
4235 fs_reg tmp2
= ibld
.vgrf(inst
->src
[0].type
);
4236 fs_reg tmp3
= ibld
.vgrf(inst
->src
[0].type
);
4239 ibld
.SHR(tmp1
, inst
->src
[1], brw_imm_d(1));
4241 add
= ibld
.ADD(tmp2
, inst
->src
[1], tmp1
);
4242 add
->src
[1].negate
= true;
4244 add
= ibld
.ADD(tmp3
, inst
->src
[0], tmp1
);
4245 add
->src
[1].negate
= true;
4246 add
->saturate
= true;
4248 add
= ibld
.ADD(inst
->dst
, tmp3
, tmp2
);
4249 add
->src
[1].negate
= true;
4250 add
->saturate
= true;
4252 /* a > b ? a - b : 0 */
4253 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4256 fs_inst
*add
= ibld
.ADD(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4257 add
->src
[1].negate
= !add
->src
[1].negate
;
4259 ibld
.SEL(inst
->dst
, inst
->dst
, brw_imm_ud(0))
4260 ->predicate
= BRW_PREDICATE_NORMAL
;
4263 inst
->remove(block
);
4269 invalidate_live_intervals();
4275 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
4276 fs_reg
*dst
, fs_reg color
, unsigned components
)
4278 if (key
->clamp_fragment_color
) {
4279 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
4280 assert(color
.type
== BRW_REGISTER_TYPE_F
);
4282 for (unsigned i
= 0; i
< components
; i
++)
4284 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
4289 for (unsigned i
= 0; i
< components
; i
++)
4290 dst
[i
] = offset(color
, bld
, i
);
4294 brw_fb_write_msg_control(const fs_inst
*inst
,
4295 const struct brw_wm_prog_data
*prog_data
)
4299 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
4300 assert(inst
->group
== 0 && inst
->exec_size
== 16);
4301 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
4302 } else if (prog_data
->dual_src_blend
) {
4303 assert(inst
->exec_size
== 8);
4305 if (inst
->group
% 16 == 0)
4306 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
4307 else if (inst
->group
% 16 == 8)
4308 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
4310 unreachable("Invalid dual-source FB write instruction group");
4312 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
4314 if (inst
->exec_size
== 16)
4315 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
4316 else if (inst
->exec_size
== 8)
4317 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
4319 unreachable("Invalid FB write execution size");
4326 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
4327 const struct brw_wm_prog_data
*prog_data
,
4328 const brw_wm_prog_key
*key
,
4329 const fs_visitor::thread_payload
&payload
)
4331 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
4332 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4333 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
4334 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
4335 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
4336 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
4337 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
4338 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
4339 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
4340 const unsigned components
=
4341 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
4343 assert(inst
->target
!= 0 || src0_alpha
.file
== BAD_FILE
);
4345 /* We can potentially have a message length of up to 15, so we have to set
4346 * base_mrf to either 0 or 1 in order to fit in m0..m15.
4349 int header_size
= 2, payload_header_size
;
4350 unsigned length
= 0;
4352 if (devinfo
->gen
< 6) {
4353 /* TODO: Support SIMD32 on gen4-5 */
4354 assert(bld
.group() < 16);
4356 /* For gen4-5, we always have a header consisting of g0 and g1. We have
4357 * an implied MOV from g0,g1 to the start of the message. The MOV from
4358 * g0 is handled by the hardware and the MOV from g1 is provided by the
4359 * generator. This is required because, on gen4-5, the generator may
4360 * generate two write messages with different message lengths in order
4361 * to handle AA data properly.
4363 * Also, since the pixel mask goes in the g0 portion of the message and
4364 * since render target writes are the last thing in the shader, we write
4365 * the pixel mask directly into g0 and it will get copied as part of the
4368 if (prog_data
->uses_kill
) {
4369 bld
.exec_all().group(1, 0)
4370 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
4371 brw_flag_reg(0, 1));
4374 assert(length
== 0);
4376 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
4377 prog_data
->uses_kill
) ||
4378 (devinfo
->gen
< 11 &&
4379 (color1
.file
!= BAD_FILE
|| key
->nr_color_regions
> 1))) {
4380 /* From the Sandy Bridge PRM, volume 4, page 198:
4382 * "Dispatched Pixel Enables. One bit per pixel indicating
4383 * which pixels were originally enabled when the thread was
4384 * dispatched. This field is only required for the end-of-
4385 * thread message and on all dual-source messages."
4387 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4389 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4390 if (bld
.group() < 16) {
4391 /* The header starts off as g0 and g1 for the first half */
4392 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4393 BRW_REGISTER_TYPE_UD
));
4395 /* The header starts off as g0 and g2 for the second half */
4396 assert(bld
.group() < 32);
4397 const fs_reg header_sources
[2] = {
4398 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4399 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4401 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4404 uint32_t g00_bits
= 0;
4406 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4409 if (src0_alpha
.file
!= BAD_FILE
)
4410 g00_bits
|= 1 << 11;
4412 /* Set computes stencil to render target */
4413 if (prog_data
->computed_stencil
)
4414 g00_bits
|= 1 << 14;
4417 /* OR extra bits into g0.0 */
4418 ubld
.group(1, 0).OR(component(header
, 0),
4419 retype(brw_vec1_grf(0, 0),
4420 BRW_REGISTER_TYPE_UD
),
4421 brw_imm_ud(g00_bits
));
4424 /* Set the render target index for choosing BLEND_STATE. */
4425 if (inst
->target
> 0) {
4426 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4429 if (prog_data
->uses_kill
) {
4430 assert(bld
.group() < 16);
4431 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4432 BRW_REGISTER_TYPE_UW
),
4433 brw_flag_reg(0, 1));
4436 assert(length
== 0);
4437 sources
[0] = header
;
4438 sources
[1] = horiz_offset(header
, 8);
4441 assert(length
== 0 || length
== 2);
4442 header_size
= length
;
4444 if (payload
.aa_dest_stencil_reg
[0]) {
4445 assert(inst
->group
< 16);
4446 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4447 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4448 .MOV(sources
[length
],
4449 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
[0], 0)));
4453 if (src0_alpha
.file
!= BAD_FILE
) {
4454 for (unsigned i
= 0; i
< bld
.dispatch_width() / 8; i
++) {
4455 const fs_builder
&ubld
= bld
.exec_all().group(8, i
)
4456 .annotate("FB write src0 alpha");
4457 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_F
);
4458 ubld
.MOV(tmp
, horiz_offset(src0_alpha
, i
* 8));
4459 setup_color_payload(ubld
, key
, &sources
[length
], tmp
, 1);
4464 if (sample_mask
.file
!= BAD_FILE
) {
4465 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4466 BRW_REGISTER_TYPE_UD
);
4468 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4469 * relevant. Since it's unsigned single words one vgrf is always
4470 * 16-wide, but only the lower or higher 8 channels will be used by the
4471 * hardware when doing a SIMD8 write depending on whether we have
4472 * selected the subspans for the first or second half respectively.
4474 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4475 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4476 sample_mask
.stride
*= 2;
4478 bld
.exec_all().annotate("FB write oMask")
4479 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4485 payload_header_size
= length
;
4487 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4490 if (color1
.file
!= BAD_FILE
) {
4491 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4495 if (src_depth
.file
!= BAD_FILE
) {
4496 sources
[length
] = src_depth
;
4500 if (dst_depth
.file
!= BAD_FILE
) {
4501 sources
[length
] = dst_depth
;
4505 if (src_stencil
.file
!= BAD_FILE
) {
4506 assert(devinfo
->gen
>= 9);
4507 assert(bld
.dispatch_width() == 8);
4509 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4510 * available on gen9+. As such it's impossible to have both enabled at the
4511 * same time and therefore length cannot overrun the array.
4513 assert(length
< 15);
4515 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4516 bld
.exec_all().annotate("FB write OS")
4517 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4518 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4523 if (devinfo
->gen
>= 7) {
4524 /* Send from the GRF */
4525 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4526 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4527 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4528 load
->dst
= payload
;
4530 uint32_t msg_ctl
= brw_fb_write_msg_control(inst
, prog_data
);
4531 uint32_t ex_desc
= 0;
4534 (inst
->group
/ 16) << 11 | /* rt slot group */
4535 brw_dp_write_desc(devinfo
, inst
->target
, msg_ctl
,
4536 GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
,
4537 inst
->last_rt
, false);
4539 if (devinfo
->gen
>= 11) {
4540 /* Set the "Render Target Index" and "Src0 Alpha Present" fields
4541 * in the extended message descriptor, in lieu of using a header.
4543 ex_desc
= inst
->target
<< 12 | (src0_alpha
.file
!= BAD_FILE
) << 15;
4545 if (key
->nr_color_regions
== 0)
4546 ex_desc
|= 1 << 20; /* Null Render Target */
4549 inst
->opcode
= SHADER_OPCODE_SEND
;
4550 inst
->resize_sources(3);
4551 inst
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4552 inst
->src
[0] = brw_imm_ud(inst
->desc
);
4553 inst
->src
[1] = brw_imm_ud(ex_desc
);
4554 inst
->src
[2] = payload
;
4555 inst
->mlen
= regs_written(load
);
4557 inst
->header_size
= header_size
;
4558 inst
->check_tdr
= true;
4559 inst
->send_has_side_effects
= true;
4561 /* Send from the MRF */
4562 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4563 sources
, length
, payload_header_size
);
4565 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4566 * will do this for us if we just give it a COMPR4 destination.
4568 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4569 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4571 if (devinfo
->gen
< 6) {
4572 /* Set up src[0] for the implied MOV from grf0-1 */
4573 inst
->resize_sources(1);
4574 inst
->src
[0] = brw_vec8_grf(0, 0);
4576 inst
->resize_sources(0);
4579 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4580 inst
->mlen
= regs_written(load
);
4581 inst
->header_size
= header_size
;
4586 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4588 const fs_builder
&ubld
= bld
.exec_all().group(8, 0);
4589 const unsigned length
= 2;
4590 const fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, length
);
4592 if (bld
.group() < 16) {
4593 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4594 BRW_REGISTER_TYPE_UD
));
4596 assert(bld
.group() < 32);
4597 const fs_reg header_sources
[] = {
4598 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4599 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
)
4601 ubld
.LOAD_PAYLOAD(header
, header_sources
, ARRAY_SIZE(header_sources
), 0);
4604 inst
->resize_sources(1);
4605 inst
->src
[0] = header
;
4606 inst
->opcode
= FS_OPCODE_FB_READ
;
4607 inst
->mlen
= length
;
4608 inst
->header_size
= length
;
4612 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4613 const fs_reg
&coordinate
,
4614 const fs_reg
&shadow_c
,
4615 const fs_reg
&lod
, const fs_reg
&lod2
,
4616 const fs_reg
&surface
,
4617 const fs_reg
&sampler
,
4618 unsigned coord_components
,
4619 unsigned grad_components
)
4621 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4622 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4623 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4624 fs_reg msg_end
= msg_begin
;
4627 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4629 for (unsigned i
= 0; i
< coord_components
; i
++)
4630 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4631 offset(coordinate
, bld
, i
));
4633 msg_end
= offset(msg_end
, bld
, coord_components
);
4635 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4636 * require all three components to be present and zero if they are unused.
4638 if (coord_components
> 0 &&
4639 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4640 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4641 for (unsigned i
= coord_components
; i
< 3; i
++)
4642 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4644 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4647 if (op
== SHADER_OPCODE_TXD
) {
4648 /* TXD unsupported in SIMD16 mode. */
4649 assert(bld
.dispatch_width() == 8);
4651 /* the slots for u and v are always present, but r is optional */
4652 if (coord_components
< 2)
4653 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4656 * dPdx = dudx, dvdx, drdx
4657 * dPdy = dudy, dvdy, drdy
4659 * 1-arg: Does not exist.
4661 * 2-arg: dudx dvdx dudy dvdy
4662 * dPdx.x dPdx.y dPdy.x dPdy.y
4665 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4666 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4667 * m5 m6 m7 m8 m9 m10
4669 for (unsigned i
= 0; i
< grad_components
; i
++)
4670 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4672 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4674 for (unsigned i
= 0; i
< grad_components
; i
++)
4675 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4677 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4681 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4682 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4684 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4685 bld
.dispatch_width() == 16);
4687 const brw_reg_type type
=
4688 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4689 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4690 bld
.MOV(retype(msg_end
, type
), lod
);
4691 msg_end
= offset(msg_end
, bld
, 1);
4694 if (shadow_c
.file
!= BAD_FILE
) {
4695 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4696 /* There's no plain shadow compare message, so we use shadow
4697 * compare with a bias of 0.0.
4699 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4700 msg_end
= offset(msg_end
, bld
, 1);
4703 bld
.MOV(msg_end
, shadow_c
);
4704 msg_end
= offset(msg_end
, bld
, 1);
4708 inst
->src
[0] = reg_undef
;
4709 inst
->src
[1] = surface
;
4710 inst
->src
[2] = sampler
;
4711 inst
->resize_sources(3);
4712 inst
->base_mrf
= msg_begin
.nr
;
4713 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4714 inst
->header_size
= 1;
4718 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4719 const fs_reg
&coordinate
,
4720 const fs_reg
&shadow_c
,
4721 const fs_reg
&lod
, const fs_reg
&lod2
,
4722 const fs_reg
&sample_index
,
4723 const fs_reg
&surface
,
4724 const fs_reg
&sampler
,
4725 unsigned coord_components
,
4726 unsigned grad_components
)
4728 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4729 fs_reg msg_coords
= message
;
4730 unsigned header_size
= 0;
4732 if (inst
->offset
!= 0) {
4733 /* The offsets set up by the visitor are in the m1 header, so we can't
4740 for (unsigned i
= 0; i
< coord_components
; i
++)
4741 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4742 offset(coordinate
, bld
, i
));
4744 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4745 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4747 if (shadow_c
.file
!= BAD_FILE
) {
4748 fs_reg msg_shadow
= msg_lod
;
4749 bld
.MOV(msg_shadow
, shadow_c
);
4750 msg_lod
= offset(msg_shadow
, bld
, 1);
4755 case SHADER_OPCODE_TXL
:
4757 bld
.MOV(msg_lod
, lod
);
4758 msg_end
= offset(msg_lod
, bld
, 1);
4760 case SHADER_OPCODE_TXD
:
4763 * dPdx = dudx, dvdx, drdx
4764 * dPdy = dudy, dvdy, drdy
4766 * Load up these values:
4767 * - dudx dudy dvdx dvdy drdx drdy
4768 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4771 for (unsigned i
= 0; i
< grad_components
; i
++) {
4772 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4773 msg_end
= offset(msg_end
, bld
, 1);
4775 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4776 msg_end
= offset(msg_end
, bld
, 1);
4779 case SHADER_OPCODE_TXS
:
4780 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4781 bld
.MOV(msg_lod
, lod
);
4782 msg_end
= offset(msg_lod
, bld
, 1);
4784 case SHADER_OPCODE_TXF
:
4785 msg_lod
= offset(msg_coords
, bld
, 3);
4786 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4787 msg_end
= offset(msg_lod
, bld
, 1);
4789 case SHADER_OPCODE_TXF_CMS
:
4790 msg_lod
= offset(msg_coords
, bld
, 3);
4792 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4794 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4795 msg_end
= offset(msg_lod
, bld
, 2);
4802 inst
->src
[0] = reg_undef
;
4803 inst
->src
[1] = surface
;
4804 inst
->src
[2] = sampler
;
4805 inst
->resize_sources(3);
4806 inst
->base_mrf
= message
.nr
;
4807 inst
->mlen
= msg_end
.nr
- message
.nr
;
4808 inst
->header_size
= header_size
;
4810 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4811 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4815 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4817 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4820 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4824 sampler_msg_type(const gen_device_info
*devinfo
,
4825 opcode opcode
, bool shadow_compare
)
4827 assert(devinfo
->gen
>= 5);
4829 case SHADER_OPCODE_TEX
:
4830 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
:
4831 GEN5_SAMPLER_MESSAGE_SAMPLE
;
4833 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
:
4834 GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
4835 case SHADER_OPCODE_TXL
:
4836 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
:
4837 GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
4838 case SHADER_OPCODE_TXL_LZ
:
4839 return shadow_compare
? GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
:
4840 GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
4841 case SHADER_OPCODE_TXS
:
4842 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4843 return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
4844 case SHADER_OPCODE_TXD
:
4845 assert(!shadow_compare
|| devinfo
->gen
>= 8 || devinfo
->is_haswell
);
4846 return shadow_compare
? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
:
4847 GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
4848 case SHADER_OPCODE_TXF
:
4849 return GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4850 case SHADER_OPCODE_TXF_LZ
:
4851 assert(devinfo
->gen
>= 9);
4852 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
4853 case SHADER_OPCODE_TXF_CMS_W
:
4854 assert(devinfo
->gen
>= 9);
4855 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
4856 case SHADER_OPCODE_TXF_CMS
:
4857 return devinfo
->gen
>= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
:
4858 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4859 case SHADER_OPCODE_TXF_UMS
:
4860 assert(devinfo
->gen
>= 7);
4861 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
4862 case SHADER_OPCODE_TXF_MCS
:
4863 assert(devinfo
->gen
>= 7);
4864 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
4865 case SHADER_OPCODE_LOD
:
4866 return GEN5_SAMPLER_MESSAGE_LOD
;
4867 case SHADER_OPCODE_TG4
:
4868 assert(devinfo
->gen
>= 7);
4869 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
:
4870 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
4872 case SHADER_OPCODE_TG4_OFFSET
:
4873 assert(devinfo
->gen
>= 7);
4874 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
:
4875 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
4876 case SHADER_OPCODE_SAMPLEINFO
:
4877 return GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
4879 unreachable("not reached");
4884 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4885 const fs_reg
&coordinate
,
4886 const fs_reg
&shadow_c
,
4887 fs_reg lod
, const fs_reg
&lod2
,
4888 const fs_reg
&min_lod
,
4889 const fs_reg
&sample_index
,
4891 const fs_reg
&surface
,
4892 const fs_reg
&sampler
,
4893 const fs_reg
&surface_handle
,
4894 const fs_reg
&sampler_handle
,
4895 const fs_reg
&tg4_offset
,
4896 unsigned coord_components
,
4897 unsigned grad_components
)
4899 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4900 const brw_stage_prog_data
*prog_data
= bld
.shader
->stage_prog_data
;
4901 unsigned reg_width
= bld
.dispatch_width() / 8;
4902 unsigned header_size
= 0, length
= 0;
4903 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4904 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4905 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4907 /* We must have exactly one of surface/sampler and surface/sampler_handle */
4908 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
4909 assert((sampler
.file
== BAD_FILE
) != (sampler_handle
.file
== BAD_FILE
));
4911 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4912 inst
->offset
!= 0 || inst
->eot
||
4913 op
== SHADER_OPCODE_SAMPLEINFO
||
4914 sampler_handle
.file
!= BAD_FILE
||
4915 is_high_sampler(devinfo
, sampler
)) {
4916 /* For general texture offsets (no txf workaround), we need a header to
4919 * TG4 needs to place its channel select in the header, for interaction
4920 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4921 * larger sampler numbers we need to offset the Sampler State Pointer in
4924 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4928 /* If we're requesting fewer than four channels worth of response,
4929 * and we have an explicit header, we need to set up the sampler
4930 * writemask. It's reversed from normal: 1 means "don't write".
4932 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4933 assert(regs_written(inst
) % reg_width
== 0);
4934 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4935 inst
->offset
|= mask
<< 12;
4938 /* Build the actual header */
4939 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4940 const fs_builder ubld1
= ubld
.group(1, 0);
4941 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4943 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4944 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4945 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4946 /* The vertex and fragment stages have g0.2 set to 0, so
4947 * header0.2 is 0 when g0 is copied. Other stages may not, so we
4948 * must set it to 0 to avoid setting undesirable bits in the
4951 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
4954 if (sampler_handle
.file
!= BAD_FILE
) {
4955 /* Bindless sampler handles aren't relative to the sampler state
4956 * pointer passed into the shader through SAMPLER_STATE_POINTERS_*.
4957 * Instead, it's an absolute pointer relative to dynamic state base
4960 * Sampler states are 16 bytes each and the pointer we give here has
4961 * to be 32-byte aligned. In order to avoid more indirect messages
4962 * than required, we assume that all bindless sampler states are
4963 * 32-byte aligned. This sacrifices a bit of general state base
4964 * address space but means we can do something more efficient in the
4967 ubld1
.MOV(component(header
, 3), sampler_handle
);
4968 } else if (is_high_sampler(devinfo
, sampler
)) {
4969 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
4970 assert(sampler
.ud
>= 16);
4971 const int sampler_state_size
= 16; /* 16 bytes */
4973 ubld1
.ADD(component(header
, 3),
4974 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4975 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
4977 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
4978 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
4979 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
4980 ubld1
.ADD(component(header
, 3),
4981 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
4987 if (shadow_c
.file
!= BAD_FILE
) {
4988 bld
.MOV(sources
[length
], shadow_c
);
4992 bool coordinate_done
= false;
4994 /* Set up the LOD info */
4997 case SHADER_OPCODE_TXL
:
4998 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4999 op
= SHADER_OPCODE_TXL_LZ
;
5002 bld
.MOV(sources
[length
], lod
);
5005 case SHADER_OPCODE_TXD
:
5006 /* TXD should have been lowered in SIMD16 mode. */
5007 assert(bld
.dispatch_width() == 8);
5009 /* Load dPdx and the coordinate together:
5010 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
5012 for (unsigned i
= 0; i
< coord_components
; i
++) {
5013 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5015 /* For cube map array, the coordinate is (u,v,r,ai) but there are
5016 * only derivatives for (u, v, r).
5018 if (i
< grad_components
) {
5019 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
5020 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
5024 coordinate_done
= true;
5026 case SHADER_OPCODE_TXS
:
5027 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
5030 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5031 /* We need an LOD; just use 0 */
5032 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
5035 case SHADER_OPCODE_TXF
:
5036 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
5037 * On Gen9 they are u, v, lod, r
5039 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
5041 if (devinfo
->gen
>= 9) {
5042 if (coord_components
>= 2) {
5043 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
5044 offset(coordinate
, bld
, 1));
5046 sources
[length
] = brw_imm_d(0);
5051 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
5052 op
= SHADER_OPCODE_TXF_LZ
;
5054 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
5058 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
5059 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5060 offset(coordinate
, bld
, i
));
5062 coordinate_done
= true;
5065 case SHADER_OPCODE_TXF_CMS
:
5066 case SHADER_OPCODE_TXF_CMS_W
:
5067 case SHADER_OPCODE_TXF_UMS
:
5068 case SHADER_OPCODE_TXF_MCS
:
5069 if (op
== SHADER_OPCODE_TXF_UMS
||
5070 op
== SHADER_OPCODE_TXF_CMS
||
5071 op
== SHADER_OPCODE_TXF_CMS_W
) {
5072 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
5076 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
5077 /* Data from the multisample control surface. */
5078 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
5081 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
5084 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
5085 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
5088 offset(mcs
, bld
, 1));
5093 /* There is no offsetting for this message; just copy in the integer
5094 * texture coordinates.
5096 for (unsigned i
= 0; i
< coord_components
; i
++)
5097 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5098 offset(coordinate
, bld
, i
));
5100 coordinate_done
= true;
5102 case SHADER_OPCODE_TG4_OFFSET
:
5103 /* More crazy intermixing */
5104 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
5105 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5107 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
5108 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5109 offset(tg4_offset
, bld
, i
));
5111 if (coord_components
== 3) /* r if present */
5112 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
5114 coordinate_done
= true;
5120 /* Set up the coordinate (except for cases where it was done above) */
5121 if (!coordinate_done
) {
5122 for (unsigned i
= 0; i
< coord_components
; i
++)
5123 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5126 if (min_lod
.file
!= BAD_FILE
) {
5127 /* Account for all of the missing coordinate sources */
5128 length
+= 4 - coord_components
;
5129 if (op
== SHADER_OPCODE_TXD
)
5130 length
+= (3 - grad_components
) * 2;
5132 bld
.MOV(sources
[length
++], min_lod
);
5137 mlen
= length
* reg_width
- header_size
;
5139 mlen
= length
* reg_width
;
5141 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
5142 BRW_REGISTER_TYPE_F
);
5143 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
5145 /* Generate the SEND. */
5146 inst
->opcode
= SHADER_OPCODE_SEND
;
5148 inst
->header_size
= header_size
;
5150 const unsigned msg_type
=
5151 sampler_msg_type(devinfo
, op
, inst
->shadow_compare
);
5152 const unsigned simd_mode
=
5153 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5154 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5156 uint32_t base_binding_table_index
;
5158 case SHADER_OPCODE_TG4
:
5159 case SHADER_OPCODE_TG4_OFFSET
:
5160 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
5162 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5163 base_binding_table_index
= prog_data
->binding_table
.image_start
;
5166 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
5170 inst
->sfid
= BRW_SFID_SAMPLER
;
5171 if (surface
.file
== IMM
&&
5172 (sampler
.file
== IMM
|| sampler_handle
.file
!= BAD_FILE
)) {
5173 inst
->desc
= brw_sampler_desc(devinfo
,
5174 surface
.ud
+ base_binding_table_index
,
5175 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5178 0 /* return_format unused on gen7+ */);
5179 inst
->src
[0] = brw_imm_ud(0);
5180 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5181 } else if (surface_handle
.file
!= BAD_FILE
) {
5182 /* Bindless surface */
5183 assert(devinfo
->gen
>= 9);
5184 inst
->desc
= brw_sampler_desc(devinfo
,
5186 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5189 0 /* return_format unused on gen7+ */);
5191 /* For bindless samplers, the entire address is included in the message
5192 * header so we can leave the portion in the message descriptor 0.
5194 if (sampler_handle
.file
!= BAD_FILE
|| sampler
.file
== IMM
) {
5195 inst
->src
[0] = brw_imm_ud(0);
5197 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5198 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5199 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5200 inst
->src
[0] = desc
;
5203 /* We assume that the driver provided the handle in the top 20 bits so
5204 * we can use the surface handle directly as the extended descriptor.
5206 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5208 /* Immediate portion of the descriptor */
5209 inst
->desc
= brw_sampler_desc(devinfo
,
5214 0 /* return_format unused on gen7+ */);
5215 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5216 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5217 if (surface
.equals(sampler
)) {
5218 /* This case is common in GL */
5219 ubld
.MUL(desc
, surface
, brw_imm_ud(0x101));
5221 if (sampler_handle
.file
!= BAD_FILE
) {
5222 ubld
.MOV(desc
, surface
);
5223 } else if (sampler
.file
== IMM
) {
5224 ubld
.OR(desc
, surface
, brw_imm_ud(sampler
.ud
<< 8));
5226 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5227 ubld
.OR(desc
, desc
, surface
);
5230 if (base_binding_table_index
)
5231 ubld
.ADD(desc
, desc
, brw_imm_ud(base_binding_table_index
));
5232 ubld
.AND(desc
, desc
, brw_imm_ud(0xfff));
5234 inst
->src
[0] = component(desc
, 0);
5235 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5238 inst
->src
[2] = src_payload
;
5239 inst
->resize_sources(3);
5242 /* EOT sampler messages don't make sense to split because it would
5243 * involve ending half of the thread early.
5245 assert(inst
->group
== 0);
5246 /* We need to use SENDC for EOT sampler messages */
5247 inst
->check_tdr
= true;
5248 inst
->send_has_side_effects
= true;
5251 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
5252 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
5256 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
5258 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5259 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
5260 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
5261 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
5262 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
5263 const fs_reg
&min_lod
= inst
->src
[TEX_LOGICAL_SRC_MIN_LOD
];
5264 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
5265 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
5266 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
5267 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
5268 const fs_reg
&surface_handle
= inst
->src
[TEX_LOGICAL_SRC_SURFACE_HANDLE
];
5269 const fs_reg
&sampler_handle
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
];
5270 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
5271 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
5272 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
5273 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
5274 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
5276 if (devinfo
->gen
>= 7) {
5277 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
5278 shadow_c
, lod
, lod2
, min_lod
,
5280 mcs
, surface
, sampler
,
5281 surface_handle
, sampler_handle
,
5283 coord_components
, grad_components
);
5284 } else if (devinfo
->gen
>= 5) {
5285 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
5286 shadow_c
, lod
, lod2
, sample_index
,
5288 coord_components
, grad_components
);
5290 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
5291 shadow_c
, lod
, lod2
,
5293 coord_components
, grad_components
);
5298 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5300 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5302 /* Get the logical send arguments. */
5303 const fs_reg
&addr
= inst
->src
[SURFACE_LOGICAL_SRC_ADDRESS
];
5304 const fs_reg
&src
= inst
->src
[SURFACE_LOGICAL_SRC_DATA
];
5305 const fs_reg
&surface
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE
];
5306 const fs_reg
&surface_handle
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
];
5307 const UNUSED fs_reg
&dims
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_DIMS
];
5308 const fs_reg
&arg
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_ARG
];
5309 assert(arg
.file
== IMM
);
5311 /* We must have exactly one of surface and surface_handle */
5312 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
5314 /* Calculate the total number of components of the payload. */
5315 const unsigned addr_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_ADDRESS
);
5316 const unsigned src_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_DATA
);
5318 const bool is_typed_access
=
5319 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
||
5320 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
||
5321 inst
->opcode
== SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
;
5323 const bool is_surface_access
= is_typed_access
||
5324 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
||
5325 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
||
5326 inst
->opcode
== SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
;
5328 const bool is_stateless
=
5329 surface
.file
== IMM
&& (surface
.ud
== BRW_BTI_STATELESS
||
5330 surface
.ud
== GEN8_BTI_STATELESS_NON_COHERENT
);
5332 const bool has_side_effects
= inst
->has_side_effects();
5333 fs_reg sample_mask
= has_side_effects
? bld
.sample_mask_reg() :
5334 fs_reg(brw_imm_d(0xffff));
5336 /* From the BDW PRM Volume 7, page 147:
5338 * "For the Data Cache Data Port*, the header must be present for the
5339 * following message types: [...] Typed read/write/atomics"
5341 * Earlier generations have a similar wording. Because of this restriction
5342 * we don't attempt to implement sample masks via predication for such
5343 * messages prior to Gen9, since we have to provide a header anyway. On
5344 * Gen11+ the header has been removed so we can only use predication.
5346 * For all stateless A32 messages, we also need a header
5349 if ((devinfo
->gen
< 9 && is_typed_access
) || is_stateless
) {
5350 fs_builder ubld
= bld
.exec_all().group(8, 0);
5351 header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5352 ubld
.MOV(header
, brw_imm_d(0));
5354 /* Both the typed and scattered byte/dword A32 messages take a buffer
5355 * base address in R0.5:[31:0] (See MH1_A32_PSM for typed messages or
5356 * MH_A32_GO for byte/dword scattered messages in the SKL PRM Vol. 2d
5357 * for more details.) This is conveniently where the HW places the
5358 * scratch surface base address.
5360 * From the SKL PRM Vol. 7 "Per-Thread Scratch Space":
5362 * "When a thread becomes 'active' it is allocated a portion of
5363 * scratch space, sized according to PerThreadScratchSpace. The
5364 * starting location of each thread’s scratch space allocation,
5365 * ScratchSpaceOffset, is passed in the thread payload in
5366 * R0.5[31:10] and is specified as a 1KB-granular offset from the
5367 * GeneralStateBaseAddress. The computation of ScratchSpaceOffset
5368 * includes the starting address of the stage’s scratch space
5369 * allocation, as programmed by ScratchSpaceBasePointer."
5371 * The base address is passed in bits R0.5[31:10] and the bottom 10
5372 * bits of R0.5 are used for other things. Therefore, we have to
5373 * mask off the bottom 10 bits so that we don't get a garbage base
5376 ubld
.group(1, 0).AND(component(header
, 5),
5377 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD
),
5378 brw_imm_ud(0xfffffc00));
5380 if (is_surface_access
)
5381 ubld
.group(1, 0).MOV(component(header
, 7), sample_mask
);
5383 const unsigned header_sz
= header
.file
!= BAD_FILE
? 1 : 0;
5385 fs_reg payload
, payload2
;
5386 unsigned mlen
, ex_mlen
= 0;
5387 if (devinfo
->gen
>= 9 &&
5388 (src
.file
== BAD_FILE
|| header
.file
== BAD_FILE
)) {
5389 /* We have split sends on gen9 and above */
5390 if (header
.file
== BAD_FILE
) {
5391 payload
= bld
.move_to_vgrf(addr
, addr_sz
);
5392 payload2
= bld
.move_to_vgrf(src
, src_sz
);
5393 mlen
= addr_sz
* (inst
->exec_size
/ 8);
5394 ex_mlen
= src_sz
* (inst
->exec_size
/ 8);
5396 assert(src
.file
== BAD_FILE
);
5398 payload2
= bld
.move_to_vgrf(addr
, addr_sz
);
5400 ex_mlen
= addr_sz
* (inst
->exec_size
/ 8);
5403 /* Allocate space for the payload. */
5404 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
5405 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
5406 fs_reg
*const components
= new fs_reg
[sz
];
5409 /* Construct the payload. */
5410 if (header
.file
!= BAD_FILE
)
5411 components
[n
++] = header
;
5413 for (unsigned i
= 0; i
< addr_sz
; i
++)
5414 components
[n
++] = offset(addr
, bld
, i
);
5416 for (unsigned i
= 0; i
< src_sz
; i
++)
5417 components
[n
++] = offset(src
, bld
, i
);
5419 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
5420 mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
5422 delete[] components
;
5425 /* Predicate the instruction on the sample mask if no header is
5428 if ((header
.file
== BAD_FILE
|| !is_surface_access
) &&
5429 sample_mask
.file
!= BAD_FILE
&& sample_mask
.file
!= IMM
) {
5430 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5431 if (inst
->predicate
) {
5432 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
5433 assert(!inst
->predicate_inverse
);
5434 assert(inst
->flag_subreg
< 2);
5435 /* Combine the sample mask with the existing predicate by using a
5436 * vertical predication mode.
5438 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
5439 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
+ 2),
5443 inst
->flag_subreg
= 2;
5444 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5445 inst
->predicate_inverse
= false;
5446 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
5452 switch (inst
->opcode
) {
5453 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5454 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5455 /* Byte scattered opcodes go through the normal data cache */
5456 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
5459 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5460 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5461 sfid
= devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
5462 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
5463 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
;
5466 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5467 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5468 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5469 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5470 /* Untyped Surface messages go through the data cache but the SFID value
5471 * changed on Haswell.
5473 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5474 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5475 GEN7_SFID_DATAPORT_DATA_CACHE
);
5478 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5479 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5480 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5481 /* Typed surface messages go through the render cache on IVB and the
5482 * data cache on HSW+.
5484 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5485 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5486 GEN6_SFID_DATAPORT_RENDER_CACHE
);
5490 unreachable("Unsupported surface opcode");
5494 switch (inst
->opcode
) {
5495 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5496 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5497 arg
.ud
, /* num_channels */
5501 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5502 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5503 arg
.ud
, /* num_channels */
5507 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5508 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5509 arg
.ud
, /* bit_size */
5513 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5514 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5515 arg
.ud
, /* bit_size */
5519 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5520 assert(arg
.ud
== 32); /* bit_size */
5521 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5525 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5526 assert(arg
.ud
== 32); /* bit_size */
5527 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5531 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5532 desc
= brw_dp_untyped_atomic_desc(devinfo
, inst
->exec_size
,
5533 arg
.ud
, /* atomic_op */
5534 !inst
->dst
.is_null());
5537 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5538 desc
= brw_dp_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5539 arg
.ud
, /* atomic_op */
5540 !inst
->dst
.is_null());
5543 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5544 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5545 arg
.ud
, /* num_channels */
5549 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5550 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5551 arg
.ud
, /* num_channels */
5555 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5556 desc
= brw_dp_typed_atomic_desc(devinfo
, inst
->exec_size
, inst
->group
,
5557 arg
.ud
, /* atomic_op */
5558 !inst
->dst
.is_null());
5562 unreachable("Unknown surface logical instruction");
5565 /* Update the original instruction. */
5566 inst
->opcode
= SHADER_OPCODE_SEND
;
5568 inst
->ex_mlen
= ex_mlen
;
5569 inst
->header_size
= header_sz
;
5570 inst
->send_has_side_effects
= has_side_effects
;
5571 inst
->send_is_volatile
= !has_side_effects
;
5573 /* Set up SFID and descriptors */
5576 if (surface
.file
== IMM
) {
5577 inst
->desc
|= surface
.ud
& 0xff;
5578 inst
->src
[0] = brw_imm_ud(0);
5579 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5580 } else if (surface_handle
.file
!= BAD_FILE
) {
5581 /* Bindless surface */
5582 assert(devinfo
->gen
>= 9);
5583 inst
->desc
|= GEN9_BTI_BINDLESS
;
5584 inst
->src
[0] = brw_imm_ud(0);
5586 /* We assume that the driver provided the handle in the top 20 bits so
5587 * we can use the surface handle directly as the extended descriptor.
5589 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5591 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5592 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5593 ubld
.AND(tmp
, surface
, brw_imm_ud(0xff));
5594 inst
->src
[0] = component(tmp
, 0);
5595 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5598 /* Finally, the payload */
5599 inst
->src
[2] = payload
;
5600 inst
->src
[3] = payload2
;
5602 inst
->resize_sources(4);
5606 lower_a64_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5608 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5610 const fs_reg
&addr
= inst
->src
[0];
5611 const fs_reg
&src
= inst
->src
[1];
5612 const unsigned src_comps
= inst
->components_read(1);
5613 assert(inst
->src
[2].file
== IMM
);
5614 const unsigned arg
= inst
->src
[2].ud
;
5615 const bool has_side_effects
= inst
->has_side_effects();
5617 /* If the surface message has side effects and we're a fragment shader, we
5618 * have to predicate with the sample mask to avoid helper invocations.
5620 if (has_side_effects
&& bld
.shader
->stage
== MESA_SHADER_FRAGMENT
) {
5621 inst
->flag_subreg
= 2;
5622 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5623 inst
->predicate_inverse
= false;
5625 fs_reg sample_mask
= bld
.sample_mask_reg();
5626 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5627 ubld
.MOV(retype(brw_flag_subreg(inst
->flag_subreg
), sample_mask
.type
),
5631 fs_reg payload
, payload2
;
5632 unsigned mlen
, ex_mlen
= 0;
5633 if (devinfo
->gen
>= 9) {
5634 /* On Skylake and above, we have SENDS */
5635 mlen
= 2 * (inst
->exec_size
/ 8);
5636 ex_mlen
= src_comps
* type_sz(src
.type
) * inst
->exec_size
/ REG_SIZE
;
5637 payload
= retype(bld
.move_to_vgrf(addr
, 1), BRW_REGISTER_TYPE_UD
);
5638 payload2
= retype(bld
.move_to_vgrf(src
, src_comps
),
5639 BRW_REGISTER_TYPE_UD
);
5641 /* Add two because the address is 64-bit */
5642 const unsigned dwords
= 2 + src_comps
;
5643 mlen
= dwords
* (inst
->exec_size
/ 8);
5649 for (unsigned i
= 0; i
< src_comps
; i
++)
5650 sources
[1 + i
] = offset(src
, bld
, i
);
5652 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, dwords
);
5653 bld
.LOAD_PAYLOAD(payload
, sources
, 1 + src_comps
, 0);
5657 switch (inst
->opcode
) {
5658 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5659 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5660 arg
, /* num_channels */
5664 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5665 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5666 arg
, /* num_channels */
5670 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5671 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5676 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5677 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5682 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5683 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 32,
5684 arg
, /* atomic_op */
5685 !inst
->dst
.is_null());
5688 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5689 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 64,
5690 arg
, /* atomic_op */
5691 !inst
->dst
.is_null());
5695 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5696 desc
= brw_dp_a64_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5697 arg
, /* atomic_op */
5698 !inst
->dst
.is_null());
5702 unreachable("Unknown A64 logical instruction");
5705 /* Update the original instruction. */
5706 inst
->opcode
= SHADER_OPCODE_SEND
;
5708 inst
->ex_mlen
= ex_mlen
;
5709 inst
->header_size
= 0;
5710 inst
->send_has_side_effects
= has_side_effects
;
5711 inst
->send_is_volatile
= !has_side_effects
;
5713 /* Set up SFID and descriptors */
5714 inst
->sfid
= HSW_SFID_DATAPORT_DATA_CACHE_1
;
5716 inst
->resize_sources(4);
5717 inst
->src
[0] = brw_imm_ud(0); /* desc */
5718 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5719 inst
->src
[2] = payload
;
5720 inst
->src
[3] = payload2
;
5724 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5726 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5728 if (devinfo
->gen
>= 7) {
5729 fs_reg index
= inst
->src
[0];
5730 /* We are switching the instruction from an ALU-like instruction to a
5731 * send-from-grf instruction. Since sends can't handle strides or
5732 * source modifiers, we have to make a copy of the offset source.
5734 fs_reg offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5735 bld
.MOV(offset
, inst
->src
[1]);
5737 const unsigned simd_mode
=
5738 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5739 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5741 inst
->opcode
= SHADER_OPCODE_SEND
;
5742 inst
->mlen
= inst
->exec_size
/ 8;
5743 inst
->resize_sources(3);
5745 inst
->sfid
= BRW_SFID_SAMPLER
;
5746 inst
->desc
= brw_sampler_desc(devinfo
, 0, 0,
5747 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
5749 if (index
.file
== IMM
) {
5750 inst
->desc
|= index
.ud
& 0xff;
5751 inst
->src
[0] = brw_imm_ud(0);
5753 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5754 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5755 ubld
.AND(tmp
, index
, brw_imm_ud(0xff));
5756 inst
->src
[0] = component(tmp
, 0);
5758 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5759 inst
->src
[2] = offset
; /* payload */
5761 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
5762 BRW_REGISTER_TYPE_UD
);
5764 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
5766 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
5767 inst
->resize_sources(1);
5768 inst
->base_mrf
= payload
.nr
;
5769 inst
->header_size
= 1;
5770 inst
->mlen
= 1 + inst
->exec_size
/ 8;
5775 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5777 assert(bld
.shader
->devinfo
->gen
< 6);
5780 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
5782 if (inst
->sources
> 1) {
5783 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
5784 * "Message Payload":
5786 * "Operand0[7]. For the INT DIV functions, this operand is the
5789 * "Operand1[7]. For the INT DIV functions, this operand is the
5792 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
5793 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
5794 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
5796 inst
->resize_sources(1);
5797 inst
->src
[0] = src0
;
5799 assert(inst
->exec_size
== 8);
5800 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
5805 fs_visitor::lower_logical_sends()
5807 bool progress
= false;
5809 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5810 const fs_builder
ibld(this, block
, inst
);
5812 switch (inst
->opcode
) {
5813 case FS_OPCODE_FB_WRITE_LOGICAL
:
5814 assert(stage
== MESA_SHADER_FRAGMENT
);
5815 lower_fb_write_logical_send(ibld
, inst
,
5816 brw_wm_prog_data(prog_data
),
5817 (const brw_wm_prog_key
*)key
,
5821 case FS_OPCODE_FB_READ_LOGICAL
:
5822 lower_fb_read_logical_send(ibld
, inst
);
5825 case SHADER_OPCODE_TEX_LOGICAL
:
5826 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
5829 case SHADER_OPCODE_TXD_LOGICAL
:
5830 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
5833 case SHADER_OPCODE_TXF_LOGICAL
:
5834 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
5837 case SHADER_OPCODE_TXL_LOGICAL
:
5838 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
5841 case SHADER_OPCODE_TXS_LOGICAL
:
5842 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
5845 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5846 lower_sampler_logical_send(ibld
, inst
,
5847 SHADER_OPCODE_IMAGE_SIZE_LOGICAL
);
5850 case FS_OPCODE_TXB_LOGICAL
:
5851 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
5854 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5855 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
5858 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5859 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
5862 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5863 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
5866 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5867 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
5870 case SHADER_OPCODE_LOD_LOGICAL
:
5871 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
5874 case SHADER_OPCODE_TG4_LOGICAL
:
5875 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
5878 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5879 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
5882 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5883 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
5886 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5887 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5888 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5889 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5890 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5891 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5892 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5893 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5894 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5895 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5896 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5897 lower_surface_logical_send(ibld
, inst
);
5900 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5901 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5902 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5903 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5904 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5905 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5906 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5907 lower_a64_logical_send(ibld
, inst
);
5910 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5911 lower_varying_pull_constant_logical_send(ibld
, inst
);
5914 case SHADER_OPCODE_RCP
:
5915 case SHADER_OPCODE_RSQ
:
5916 case SHADER_OPCODE_SQRT
:
5917 case SHADER_OPCODE_EXP2
:
5918 case SHADER_OPCODE_LOG2
:
5919 case SHADER_OPCODE_SIN
:
5920 case SHADER_OPCODE_COS
:
5921 case SHADER_OPCODE_POW
:
5922 case SHADER_OPCODE_INT_QUOTIENT
:
5923 case SHADER_OPCODE_INT_REMAINDER
:
5924 /* The math opcodes are overloaded for the send-like and
5925 * expression-like instructions which seems kind of icky. Gen6+ has
5926 * a native (but rather quirky) MATH instruction so we don't need to
5927 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
5928 * logical instructions (which we can easily recognize because they
5929 * have mlen = 0) into send-like virtual instructions.
5931 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
5932 lower_math_logical_send(ibld
, inst
);
5947 invalidate_live_intervals();
5953 is_mixed_float_with_fp32_dst(const fs_inst
*inst
)
5955 /* This opcode sometimes uses :W type on the source even if the operand is
5956 * a :HF, because in gen7 there is no support for :HF, and thus it uses :W.
5958 if (inst
->opcode
== BRW_OPCODE_F16TO32
)
5961 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
)
5964 for (int i
= 0; i
< inst
->sources
; i
++) {
5965 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_HF
)
5973 is_mixed_float_with_packed_fp16_dst(const fs_inst
*inst
)
5975 /* This opcode sometimes uses :W type on the destination even if the
5976 * destination is a :HF, because in gen7 there is no support for :HF, and
5979 if (inst
->opcode
== BRW_OPCODE_F32TO16
&&
5980 inst
->dst
.stride
== 1)
5983 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_HF
||
5984 inst
->dst
.stride
!= 1)
5987 for (int i
= 0; i
< inst
->sources
; i
++) {
5988 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_F
)
5996 * Get the closest allowed SIMD width for instruction \p inst accounting for
5997 * some common regioning and execution control restrictions that apply to FPU
5998 * instructions. These restrictions don't necessarily have any relevance to
5999 * instructions not executed by the FPU pipeline like extended math, control
6000 * flow or send message instructions.
6002 * For virtual opcodes it's really up to the instruction -- In some cases
6003 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
6004 * instructions) it may simplify virtual instruction lowering if we can
6005 * enforce FPU-like regioning restrictions already on the virtual instruction,
6006 * in other cases (e.g. virtual send-like instructions) this may be
6007 * excessively restrictive.
6010 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
6011 const fs_inst
*inst
)
6013 /* Maximum execution size representable in the instruction controls. */
6014 unsigned max_width
= MIN2(32, inst
->exec_size
);
6016 /* According to the PRMs:
6017 * "A. In Direct Addressing mode, a source cannot span more than 2
6018 * adjacent GRF registers.
6019 * B. A destination cannot span more than 2 adjacent GRF registers."
6021 * Look for the source or destination with the largest register region
6022 * which is the one that is going to limit the overall execution size of
6023 * the instruction due to this rule.
6025 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6027 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6028 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
6030 /* Calculate the maximum execution size of the instruction based on the
6031 * factor by which it goes over the hardware limit of 2 GRFs.
6034 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
6036 /* According to the IVB PRMs:
6037 * "When destination spans two registers, the source MUST span two
6038 * registers. The exception to the above rule:
6040 * - When source is scalar, the source registers are not incremented.
6041 * - When source is packed integer Word and destination is packed
6042 * integer DWord, the source register is not incremented but the
6043 * source sub register is incremented."
6045 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
6046 * restrictions. The code below intentionally doesn't check whether the
6047 * destination type is integer because empirically the hardware doesn't
6048 * seem to care what the actual type is as long as it's dword-aligned.
6050 if (devinfo
->gen
< 8) {
6051 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6052 /* IVB implements DF scalars as <0;2,1> regions. */
6053 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
6054 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
6055 const bool is_packed_word_exception
=
6056 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
6057 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
6059 /* We check size_read(i) against size_written instead of REG_SIZE
6060 * because we want to properly handle SIMD32. In SIMD32, you can end
6061 * up with writes to 4 registers and a source that reads 2 registers
6062 * and we may still need to lower all the way to SIMD8 in that case.
6064 if (inst
->size_written
> REG_SIZE
&&
6065 inst
->size_read(i
) != 0 &&
6066 inst
->size_read(i
) < inst
->size_written
&&
6067 !is_scalar_exception
&& !is_packed_word_exception
) {
6068 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6069 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6074 if (devinfo
->gen
< 6) {
6075 /* From the G45 PRM, Volume 4 Page 361:
6077 * "Operand Alignment Rule: With the exceptions listed below, a
6078 * source/destination operand in general should be aligned to even
6079 * 256-bit physical register with a region size equal to two 256-bit
6080 * physical registers."
6082 * Normally we enforce this by allocating virtual registers to the
6083 * even-aligned class. But we need to handle payload registers.
6085 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6086 if (inst
->src
[i
].file
== FIXED_GRF
&& (inst
->src
[i
].nr
& 1) &&
6087 inst
->size_read(i
) > REG_SIZE
) {
6088 max_width
= MIN2(max_width
, 8);
6093 /* From the IVB PRMs:
6094 * "When an instruction is SIMD32, the low 16 bits of the execution mask
6095 * are applied for both halves of the SIMD32 instruction. If different
6096 * execution mask channels are required, split the instruction into two
6097 * SIMD16 instructions."
6099 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
6100 * 32-wide control flow support in hardware and will behave similarly.
6102 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
6103 max_width
= MIN2(max_width
, 16);
6105 /* From the IVB PRMs (applies to HSW too):
6106 * "Instructions with condition modifiers must not use SIMD32."
6108 * From the BDW PRMs (applies to later hardware too):
6109 * "Ternary instruction with condition modifiers must not use SIMD32."
6111 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
6112 max_width
= MIN2(max_width
, 16);
6114 /* From the IVB PRMs (applies to other devices that don't have the
6115 * gen_device_info::supports_simd16_3src flag set):
6116 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
6117 * SIMD8 is not allowed for DF operations."
6119 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
6120 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6122 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
6123 * the 8-bit quarter of the execution mask signals specified in the
6124 * instruction control fields) for the second compressed half of any
6125 * single-precision instruction (for double-precision instructions
6126 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
6127 * the EU will apply the wrong execution controls for the second
6128 * sequential GRF write if the number of channels per GRF is not exactly
6129 * eight in single-precision mode (or four in double-float mode).
6131 * In this situation we calculate the maximum size of the split
6132 * instructions so they only ever write to a single register.
6134 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
6135 !inst
->force_writemask_all
) {
6136 const unsigned channels_per_grf
= inst
->exec_size
/
6137 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6138 const unsigned exec_type_size
= get_exec_type_size(inst
);
6139 assert(exec_type_size
);
6141 /* The hardware shifts exactly 8 channels per compressed half of the
6142 * instruction in single-precision mode and exactly 4 in double-precision.
6144 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
6145 max_width
= MIN2(max_width
, channels_per_grf
);
6147 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
6148 * because HW applies the same channel enable signals to both halves of
6149 * the compressed instruction which will be just wrong under
6150 * non-uniform control flow.
6152 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6153 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
6154 max_width
= MIN2(max_width
, 4);
6157 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6160 * "No SIMD16 in mixed mode when destination is f32. Instruction
6161 * execution size must be no more than 8."
6163 * FIXME: the simulator doesn't seem to complain if we don't do this and
6164 * empirical testing with existing CTS tests show that they pass just fine
6165 * without implementing this, however, since our interpretation of the PRM
6166 * is that conversion MOVs between HF and F are still mixed-float
6167 * instructions (and therefore subject to this restriction) we decided to
6168 * split them to be safe. Might be useful to do additional investigation to
6169 * lift the restriction if we can ensure that it is safe though, since these
6170 * conversions are common when half-float types are involved since many
6171 * instructions do not support HF types and conversions from/to F are
6174 if (is_mixed_float_with_fp32_dst(inst
))
6175 max_width
= MIN2(max_width
, 8);
6177 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6180 * "No SIMD16 in mixed mode when destination is packed f16 for both
6181 * Align1 and Align16."
6183 if (is_mixed_float_with_packed_fp16_dst(inst
))
6184 max_width
= MIN2(max_width
, 8);
6186 /* Only power-of-two execution sizes are representable in the instruction
6189 return 1 << _mesa_logbase2(max_width
);
6193 * Get the maximum allowed SIMD width for instruction \p inst accounting for
6194 * various payload size restrictions that apply to sampler message
6197 * This is only intended to provide a maximum theoretical bound for the
6198 * execution size of the message based on the number of argument components
6199 * alone, which in most cases will determine whether the SIMD8 or SIMD16
6200 * variant of the message can be used, though some messages may have
6201 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
6202 * the message length to determine the exact SIMD width and argument count,
6203 * which makes a number of sampler message combinations impossible to
6207 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
6208 const fs_inst
*inst
)
6210 /* If we have a min_lod parameter on anything other than a simple sample
6211 * message, it will push it over 5 arguments and we have to fall back to
6214 if (inst
->opcode
!= SHADER_OPCODE_TEX
&&
6215 inst
->components_read(TEX_LOGICAL_SRC_MIN_LOD
))
6218 /* Calculate the number of coordinate components that have to be present
6219 * assuming that additional arguments follow the texel coordinates in the
6220 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
6221 * need to pad to four or three components depending on the message,
6222 * pre-ILK we need to pad to at most three components.
6224 const unsigned req_coord_components
=
6225 (devinfo
->gen
>= 7 ||
6226 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
6227 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
6228 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
6231 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
6232 * variant of the TXL or TXF message.
6234 const bool implicit_lod
= devinfo
->gen
>= 9 &&
6235 (inst
->opcode
== SHADER_OPCODE_TXL
||
6236 inst
->opcode
== SHADER_OPCODE_TXF
) &&
6237 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
6239 /* Calculate the total number of argument components that need to be passed
6240 * to the sampler unit.
6242 const unsigned num_payload_components
=
6243 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
6244 req_coord_components
) +
6245 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
6246 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
6247 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
6248 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
6249 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
6250 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
6251 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
6253 /* SIMD16 messages with more than five arguments exceed the maximum message
6254 * size supported by the sampler, regardless of whether a header is
6257 return MIN2(inst
->exec_size
,
6258 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
6262 * Get the closest native SIMD width supported by the hardware for instruction
6263 * \p inst. The instruction will be left untouched by
6264 * fs_visitor::lower_simd_width() if the returned value is equal to the
6265 * original execution size.
6268 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
6269 const fs_inst
*inst
)
6271 switch (inst
->opcode
) {
6272 case BRW_OPCODE_MOV
:
6273 case BRW_OPCODE_SEL
:
6274 case BRW_OPCODE_NOT
:
6275 case BRW_OPCODE_AND
:
6277 case BRW_OPCODE_XOR
:
6278 case BRW_OPCODE_SHR
:
6279 case BRW_OPCODE_SHL
:
6280 case BRW_OPCODE_ASR
:
6281 case BRW_OPCODE_ROR
:
6282 case BRW_OPCODE_ROL
:
6283 case BRW_OPCODE_CMPN
:
6284 case BRW_OPCODE_CSEL
:
6285 case BRW_OPCODE_F32TO16
:
6286 case BRW_OPCODE_F16TO32
:
6287 case BRW_OPCODE_BFREV
:
6288 case BRW_OPCODE_BFE
:
6289 case BRW_OPCODE_ADD
:
6290 case BRW_OPCODE_MUL
:
6291 case BRW_OPCODE_AVG
:
6292 case BRW_OPCODE_FRC
:
6293 case BRW_OPCODE_RNDU
:
6294 case BRW_OPCODE_RNDD
:
6295 case BRW_OPCODE_RNDE
:
6296 case BRW_OPCODE_RNDZ
:
6297 case BRW_OPCODE_LZD
:
6298 case BRW_OPCODE_FBH
:
6299 case BRW_OPCODE_FBL
:
6300 case BRW_OPCODE_CBIT
:
6301 case BRW_OPCODE_SAD2
:
6302 case BRW_OPCODE_MAD
:
6303 case BRW_OPCODE_LRP
:
6304 case FS_OPCODE_PACK
:
6305 case SHADER_OPCODE_SEL_EXEC
:
6306 case SHADER_OPCODE_CLUSTER_BROADCAST
:
6307 return get_fpu_lowered_simd_width(devinfo
, inst
);
6309 case BRW_OPCODE_CMP
: {
6310 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
6311 * when the destination is a GRF the dependency-clear bit on the flag
6312 * register is cleared early.
6314 * Suggested workarounds are to disable coissuing CMP instructions
6315 * or to split CMP(16) instructions into two CMP(8) instructions.
6317 * We choose to split into CMP(8) instructions since disabling
6318 * coissuing would affect CMP instructions not otherwise affected by
6321 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6322 !inst
->dst
.is_null() ? 8 : ~0);
6323 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
6325 case BRW_OPCODE_BFI1
:
6326 case BRW_OPCODE_BFI2
:
6327 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
6329 * "Force BFI instructions to be executed always in SIMD8."
6331 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
6332 get_fpu_lowered_simd_width(devinfo
, inst
));
6335 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
6336 return inst
->exec_size
;
6338 case SHADER_OPCODE_RCP
:
6339 case SHADER_OPCODE_RSQ
:
6340 case SHADER_OPCODE_SQRT
:
6341 case SHADER_OPCODE_EXP2
:
6342 case SHADER_OPCODE_LOG2
:
6343 case SHADER_OPCODE_SIN
:
6344 case SHADER_OPCODE_COS
: {
6345 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
6346 * Gen6. Extended Math Function is limited to SIMD8 with half-float.
6348 if (devinfo
->gen
== 6 || (devinfo
->gen
== 4 && !devinfo
->is_g4x
))
6349 return MIN2(8, inst
->exec_size
);
6350 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6351 return MIN2(8, inst
->exec_size
);
6352 return MIN2(16, inst
->exec_size
);
6355 case SHADER_OPCODE_POW
: {
6356 /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
6357 * to SIMD8 with half-float
6359 if (devinfo
->gen
< 7)
6360 return MIN2(8, inst
->exec_size
);
6361 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6362 return MIN2(8, inst
->exec_size
);
6363 return MIN2(16, inst
->exec_size
);
6366 case SHADER_OPCODE_USUB_SAT
:
6367 case SHADER_OPCODE_ISUB_SAT
:
6368 return get_fpu_lowered_simd_width(devinfo
, inst
);
6370 case SHADER_OPCODE_INT_QUOTIENT
:
6371 case SHADER_OPCODE_INT_REMAINDER
:
6372 /* Integer division is limited to SIMD8 on all generations. */
6373 return MIN2(8, inst
->exec_size
);
6375 case FS_OPCODE_LINTERP
:
6376 case SHADER_OPCODE_GET_BUFFER_SIZE
:
6377 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
6378 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
6379 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6380 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6381 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
6382 return MIN2(16, inst
->exec_size
);
6384 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
6385 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
6386 * message used to implement varying pull constant loads, so expand it
6387 * to SIMD16. An alternative with longer message payload length but
6388 * shorter return payload would be to use the SIMD8 sampler message that
6389 * takes (header, u, v, r) as parameters instead of (header, u).
6391 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
6393 case FS_OPCODE_DDX_COARSE
:
6394 case FS_OPCODE_DDX_FINE
:
6395 case FS_OPCODE_DDY_COARSE
:
6396 case FS_OPCODE_DDY_FINE
:
6397 /* The implementation of this virtual opcode may require emitting
6398 * compressed Align16 instructions, which are severely limited on some
6401 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
6402 * Region Restrictions):
6404 * "In Align16 access mode, SIMD16 is not allowed for DW operations
6405 * and SIMD8 is not allowed for DF operations."
6407 * In this context, "DW operations" means "operations acting on 32-bit
6408 * values", so it includes operations on floats.
6410 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
6411 * (Instruction Compression -> Rules and Restrictions):
6413 * "A compressed instruction must be in Align1 access mode. Align16
6414 * mode instructions cannot be compressed."
6416 * Similar text exists in the g45 PRM.
6418 * Empirically, compressed align16 instructions using odd register
6419 * numbers don't appear to work on Sandybridge either.
6421 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
6422 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
6423 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
6425 case SHADER_OPCODE_MULH
:
6426 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
6427 * is 8-wide on Gen7+.
6429 return (devinfo
->gen
>= 7 ? 8 :
6430 get_fpu_lowered_simd_width(devinfo
, inst
));
6432 case FS_OPCODE_FB_WRITE_LOGICAL
:
6433 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
6436 assert(devinfo
->gen
!= 6 ||
6437 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
6438 inst
->exec_size
== 8);
6439 /* Dual-source FB writes are unsupported in SIMD16 mode. */
6440 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
6441 8 : MIN2(16, inst
->exec_size
));
6443 case FS_OPCODE_FB_READ_LOGICAL
:
6444 return MIN2(16, inst
->exec_size
);
6446 case SHADER_OPCODE_TEX_LOGICAL
:
6447 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
6448 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
6449 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
6450 case SHADER_OPCODE_LOD_LOGICAL
:
6451 case SHADER_OPCODE_TG4_LOGICAL
:
6452 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
6453 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
6454 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
6455 return get_sampler_lowered_simd_width(devinfo
, inst
);
6457 case SHADER_OPCODE_TXD_LOGICAL
:
6458 /* TXD is unsupported in SIMD16 mode. */
6461 case SHADER_OPCODE_TXL_LOGICAL
:
6462 case FS_OPCODE_TXB_LOGICAL
:
6463 /* Only one execution size is representable pre-ILK depending on whether
6464 * the shadow reference argument is present.
6466 if (devinfo
->gen
== 4)
6467 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
6469 return get_sampler_lowered_simd_width(devinfo
, inst
);
6471 case SHADER_OPCODE_TXF_LOGICAL
:
6472 case SHADER_OPCODE_TXS_LOGICAL
:
6473 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
6474 * messages. Use SIMD16 instead.
6476 if (devinfo
->gen
== 4)
6479 return get_sampler_lowered_simd_width(devinfo
, inst
);
6481 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
6482 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
6483 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
6486 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
6487 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6488 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
6489 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
6490 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
6491 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
6492 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
6493 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
6494 return MIN2(16, inst
->exec_size
);
6496 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
6497 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
6498 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
6499 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
6500 return devinfo
->gen
<= 8 ? 8 : MIN2(16, inst
->exec_size
);
6502 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
6503 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
6504 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6507 case SHADER_OPCODE_URB_READ_SIMD8
:
6508 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
6509 case SHADER_OPCODE_URB_WRITE_SIMD8
:
6510 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
6511 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
6512 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
6513 return MIN2(8, inst
->exec_size
);
6515 case SHADER_OPCODE_QUAD_SWIZZLE
: {
6516 const unsigned swiz
= inst
->src
[1].ud
;
6517 return (is_uniform(inst
->src
[0]) ?
6518 get_fpu_lowered_simd_width(devinfo
, inst
) :
6519 devinfo
->gen
< 11 && type_sz(inst
->src
[0].type
) == 4 ? 8 :
6520 swiz
== BRW_SWIZZLE_XYXY
|| swiz
== BRW_SWIZZLE_ZWZW
? 4 :
6521 get_fpu_lowered_simd_width(devinfo
, inst
));
6523 case SHADER_OPCODE_MOV_INDIRECT
: {
6524 /* From IVB and HSW PRMs:
6526 * "2.When the destination requires two registers and the sources are
6527 * indirect, the sources must use 1x1 regioning mode.
6529 * In case of DF instructions in HSW/IVB, the exec_size is limited by
6530 * the EU decompression logic not handling VxH indirect addressing
6533 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
6534 /* Prior to Broadwell, we only have 8 address subregisters. */
6535 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
6536 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
6540 case SHADER_OPCODE_LOAD_PAYLOAD
: {
6541 const unsigned reg_count
=
6542 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
6544 if (reg_count
> 2) {
6545 /* Only LOAD_PAYLOAD instructions with per-channel destination region
6546 * can be easily lowered (which excludes headers and heterogeneous
6549 assert(!inst
->header_size
);
6550 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6551 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
6552 inst
->src
[i
].file
== BAD_FILE
);
6554 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
6556 return inst
->exec_size
;
6560 return inst
->exec_size
;
6565 * Return true if splitting out the group of channels of instruction \p inst
6566 * given by lbld.group() requires allocating a temporary for the i-th source
6567 * of the lowered instruction.
6570 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
6572 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
6573 (inst
->components_read(i
) == 1 &&
6574 lbld
.dispatch_width() <= inst
->exec_size
)) ||
6575 (inst
->flags_written() &
6576 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
6580 * Extract the data that would be consumed by the channel group given by
6581 * lbld.group() from the i-th source region of instruction \p inst and return
6582 * it as result in packed form.
6585 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
6587 assert(lbld
.group() >= inst
->group
);
6589 /* Specified channel group from the source region. */
6590 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group() - inst
->group
);
6592 if (needs_src_copy(lbld
, inst
, i
)) {
6593 /* Builder of the right width to perform the copy avoiding uninitialized
6594 * data if the lowered execution size is greater than the original
6595 * execution size of the instruction.
6597 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
6598 inst
->exec_size
), 0);
6599 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
6601 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
6602 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
6606 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
6607 /* The source is invariant for all dispatch_width-wide groups of the
6610 return inst
->src
[i
];
6613 /* We can just point the lowered instruction at the right channel group
6614 * from the original region.
6621 * Return true if splitting out the group of channels of instruction \p inst
6622 * given by lbld.group() requires allocating a temporary for the destination
6623 * of the lowered instruction and copying the data back to the original
6624 * destination region.
6627 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
6629 /* If the instruction writes more than one component we'll have to shuffle
6630 * the results of multiple lowered instructions in order to make sure that
6631 * they end up arranged correctly in the original destination region.
6633 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
6636 /* If the lowered execution size is larger than the original the result of
6637 * the instruction won't fit in the original destination, so we'll have to
6638 * allocate a temporary in any case.
6640 if (lbld
.dispatch_width() > inst
->exec_size
)
6643 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6644 /* If we already made a copy of the source for other reasons there won't
6645 * be any overlap with the destination.
6647 if (needs_src_copy(lbld
, inst
, i
))
6650 /* In order to keep the logic simple we emit a copy whenever the
6651 * destination region doesn't exactly match an overlapping source, which
6652 * may point at the source and destination not being aligned group by
6653 * group which could cause one of the lowered instructions to overwrite
6654 * the data read from the same source by other lowered instructions.
6656 if (regions_overlap(inst
->dst
, inst
->size_written
,
6657 inst
->src
[i
], inst
->size_read(i
)) &&
6658 !inst
->dst
.equals(inst
->src
[i
]))
6666 * Insert data from a packed temporary into the channel group given by
6667 * lbld.group() of the destination region of instruction \p inst and return
6668 * the temporary as result. Any copy instructions that are required for
6669 * unzipping the previous value (in the case of partial writes) will be
6670 * inserted using \p lbld_before and any copy instructions required for
6671 * zipping up the destination of \p inst will be inserted using \p lbld_after.
6674 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
6677 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
6678 assert(lbld_before
.group() == lbld_after
.group());
6679 assert(lbld_after
.group() >= inst
->group
);
6681 /* Specified channel group from the destination region. */
6682 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group() - inst
->group
);
6683 const unsigned dst_size
= inst
->size_written
/
6684 inst
->dst
.component_size(inst
->exec_size
);
6686 if (needs_dst_copy(lbld_after
, inst
)) {
6687 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
6689 if (inst
->predicate
) {
6690 /* Handle predication by copying the original contents of
6691 * the destination into the temporary before emitting the
6692 * lowered instruction.
6694 const fs_builder gbld_before
=
6695 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
6696 inst
->exec_size
), 0);
6697 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6698 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
6699 offset(dst
, inst
->exec_size
, k
));
6703 const fs_builder gbld_after
=
6704 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
6705 inst
->exec_size
), 0);
6706 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6707 /* Use a builder of the right width to perform the copy avoiding
6708 * uninitialized data if the lowered execution size is greater than
6709 * the original execution size of the instruction.
6711 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
6712 offset(tmp
, lbld_after
, k
));
6718 /* No need to allocate a temporary for the lowered instruction, just
6719 * take the right group of channels from the original region.
6726 fs_visitor::lower_simd_width()
6728 bool progress
= false;
6730 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6731 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
6733 if (lower_width
!= inst
->exec_size
) {
6734 /* Builder matching the original instruction. We may also need to
6735 * emit an instruction of width larger than the original, set the
6736 * execution size of the builder to the highest of both for now so
6737 * we're sure that both cases can be handled.
6739 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
6740 const fs_builder ibld
= bld
.at(block
, inst
)
6741 .exec_all(inst
->force_writemask_all
)
6742 .group(max_width
, inst
->group
/ max_width
);
6744 /* Split the copies in chunks of the execution width of either the
6745 * original or the lowered instruction, whichever is lower.
6747 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
6748 const unsigned dst_size
= inst
->size_written
/
6749 inst
->dst
.component_size(inst
->exec_size
);
6751 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
6753 /* Inserting the zip, unzip, and duplicated instructions in all of
6754 * the right spots is somewhat tricky. All of the unzip and any
6755 * instructions from the zip which unzip the destination prior to
6756 * writing need to happen before all of the per-group instructions
6757 * and the zip instructions need to happen after. In order to sort
6758 * this all out, we insert the unzip instructions before \p inst,
6759 * insert the per-group instructions after \p inst (i.e. before
6760 * inst->next), and insert the zip instructions before the
6761 * instruction after \p inst. Since we are inserting instructions
6762 * after \p inst, inst->next is a moving target and we need to save
6763 * it off here so that we insert the zip instructions in the right
6766 * Since we're inserting split instructions after after_inst, the
6767 * instructions will end up in the reverse order that we insert them.
6768 * However, certain render target writes require that the low group
6769 * instructions come before the high group. From the Ivy Bridge PRM
6770 * Vol. 4, Pt. 1, Section 3.9.11:
6772 * "If multiple SIMD8 Dual Source messages are delivered by the
6773 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
6774 * issued before the SIMD8_DUALSRC_HI message with the same Slot
6775 * Group Select setting."
6777 * And, from Section 3.9.11.1 of the same PRM:
6779 * "When SIMD32 or SIMD16 PS threads send render target writes
6780 * with multiple SIMD8 and SIMD16 messages, the following must
6783 * All the slots (as described above) must have a corresponding
6784 * render target write irrespective of the slot's validity. A slot
6785 * is considered valid when at least one sample is enabled. For
6786 * example, a SIMD16 PS thread must send two SIMD8 render target
6787 * writes to cover all the slots.
6789 * PS thread must send SIMD render target write messages with
6790 * increasing slot numbers. For example, SIMD16 thread has
6791 * Slot[15:0] and if two SIMD8 render target writes are used, the
6792 * first SIMD8 render target write must send Slot[7:0] and the
6793 * next one must send Slot[15:8]."
6795 * In order to make low group instructions come before high group
6796 * instructions (this is required for some render target writes), we
6797 * split from the highest group to lowest.
6799 exec_node
*const after_inst
= inst
->next
;
6800 for (int i
= n
- 1; i
>= 0; i
--) {
6801 /* Emit a copy of the original instruction with the lowered width.
6802 * If the EOT flag was set throw it away except for the last
6803 * instruction to avoid killing the thread prematurely.
6805 fs_inst split_inst
= *inst
;
6806 split_inst
.exec_size
= lower_width
;
6807 split_inst
.eot
= inst
->eot
&& i
== int(n
- 1);
6809 /* Select the correct channel enables for the i-th group, then
6810 * transform the sources and destination and emit the lowered
6813 const fs_builder lbld
= ibld
.group(lower_width
, i
);
6815 for (unsigned j
= 0; j
< inst
->sources
; j
++)
6816 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
6818 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
6819 lbld
.at(block
, after_inst
), inst
);
6820 split_inst
.size_written
=
6821 split_inst
.dst
.component_size(lower_width
) * dst_size
;
6823 lbld
.at(block
, inst
->next
).emit(split_inst
);
6826 inst
->remove(block
);
6832 invalidate_live_intervals();
6838 * Transform barycentric vectors into the interleaved form expected by the PLN
6839 * instruction and returned by the Gen7+ PI shared function.
6841 * For channels 0-15 in SIMD16 mode they are expected to be laid out as
6842 * follows in the register file:
6849 * There is no need to handle SIMD32 here -- This is expected to be run after
6850 * SIMD lowering, since SIMD lowering relies on vectors having the standard
6854 fs_visitor::lower_barycentrics()
6856 const bool has_interleaved_layout
= devinfo
->has_pln
|| devinfo
->gen
>= 7;
6857 bool progress
= false;
6859 if (stage
!= MESA_SHADER_FRAGMENT
|| !has_interleaved_layout
)
6862 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6863 if (inst
->exec_size
< 16)
6866 const fs_builder
ibld(this, block
, inst
);
6867 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
6869 switch (inst
->opcode
) {
6870 case FS_OPCODE_LINTERP
: {
6871 assert(inst
->exec_size
== 16);
6872 const fs_reg tmp
= ibld
.vgrf(inst
->src
[0].type
, 2);
6875 for (unsigned i
= 0; i
< ARRAY_SIZE(srcs
); i
++)
6876 srcs
[i
] = horiz_offset(offset(inst
->src
[0], ibld
, i
% 2),
6879 ubld
.LOAD_PAYLOAD(tmp
, srcs
, ARRAY_SIZE(srcs
), ARRAY_SIZE(srcs
));
6885 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6886 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6887 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
: {
6888 assert(inst
->exec_size
== 16);
6889 const fs_reg tmp
= ibld
.vgrf(inst
->dst
.type
, 2);
6891 for (unsigned i
= 0; i
< 2; i
++) {
6892 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
6893 fs_inst
*mov
= ibld
.at(block
, inst
->next
).group(8, g
)
6894 .MOV(horiz_offset(offset(inst
->dst
, ibld
, i
),
6896 offset(tmp
, ubld
, 2 * g
+ i
));
6897 mov
->predicate
= inst
->predicate
;
6898 mov
->predicate_inverse
= inst
->predicate_inverse
;
6899 mov
->flag_subreg
= inst
->flag_subreg
;
6913 invalidate_live_intervals();
6919 fs_visitor::dump_instructions()
6921 dump_instructions(NULL
);
6925 fs_visitor::dump_instructions(const char *name
)
6927 FILE *file
= stderr
;
6928 if (name
&& geteuid() != 0) {
6929 file
= fopen(name
, "w");
6935 calculate_register_pressure();
6936 int ip
= 0, max_pressure
= 0;
6937 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
6938 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
6939 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
6940 dump_instruction(inst
, file
);
6943 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
6946 foreach_in_list(backend_instruction
, inst
, &instructions
) {
6947 fprintf(file
, "%4d: ", ip
++);
6948 dump_instruction(inst
, file
);
6952 if (file
!= stderr
) {
6958 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
6960 dump_instruction(be_inst
, stderr
);
6964 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
6966 fs_inst
*inst
= (fs_inst
*)be_inst
;
6968 if (inst
->predicate
) {
6969 fprintf(file
, "(%cf%d.%d) ",
6970 inst
->predicate_inverse
? '-' : '+',
6971 inst
->flag_subreg
/ 2,
6972 inst
->flag_subreg
% 2);
6975 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
6977 fprintf(file
, ".sat");
6978 if (inst
->conditional_mod
) {
6979 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
6980 if (!inst
->predicate
&&
6981 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
6982 inst
->opcode
!= BRW_OPCODE_CSEL
&&
6983 inst
->opcode
!= BRW_OPCODE_IF
&&
6984 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
6985 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
6986 inst
->flag_subreg
% 2);
6989 fprintf(file
, "(%d) ", inst
->exec_size
);
6992 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
6995 if (inst
->ex_mlen
) {
6996 fprintf(file
, "(ex_mlen: %d) ", inst
->ex_mlen
);
7000 fprintf(file
, "(EOT) ");
7003 switch (inst
->dst
.file
) {
7005 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
7008 fprintf(file
, "g%d", inst
->dst
.nr
);
7011 fprintf(file
, "m%d", inst
->dst
.nr
);
7014 fprintf(file
, "(null)");
7017 fprintf(file
, "***u%d***", inst
->dst
.nr
);
7020 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
7023 switch (inst
->dst
.nr
) {
7025 fprintf(file
, "null");
7027 case BRW_ARF_ADDRESS
:
7028 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
7030 case BRW_ARF_ACCUMULATOR
:
7031 fprintf(file
, "acc%d", inst
->dst
.subnr
);
7034 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7037 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7042 unreachable("not reached");
7045 if (inst
->dst
.offset
||
7046 (inst
->dst
.file
== VGRF
&&
7047 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
7048 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
7049 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
7050 inst
->dst
.offset
% reg_size
);
7053 if (inst
->dst
.stride
!= 1)
7054 fprintf(file
, "<%u>", inst
->dst
.stride
);
7055 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
7057 for (int i
= 0; i
< inst
->sources
; i
++) {
7058 if (inst
->src
[i
].negate
)
7060 if (inst
->src
[i
].abs
)
7062 switch (inst
->src
[i
].file
) {
7064 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
7067 fprintf(file
, "g%d", inst
->src
[i
].nr
);
7070 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
7073 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
7076 fprintf(file
, "u%d", inst
->src
[i
].nr
);
7079 fprintf(file
, "(null)");
7082 switch (inst
->src
[i
].type
) {
7083 case BRW_REGISTER_TYPE_F
:
7084 fprintf(file
, "%-gf", inst
->src
[i
].f
);
7086 case BRW_REGISTER_TYPE_DF
:
7087 fprintf(file
, "%fdf", inst
->src
[i
].df
);
7089 case BRW_REGISTER_TYPE_W
:
7090 case BRW_REGISTER_TYPE_D
:
7091 fprintf(file
, "%dd", inst
->src
[i
].d
);
7093 case BRW_REGISTER_TYPE_UW
:
7094 case BRW_REGISTER_TYPE_UD
:
7095 fprintf(file
, "%uu", inst
->src
[i
].ud
);
7097 case BRW_REGISTER_TYPE_Q
:
7098 fprintf(file
, "%" PRId64
"q", inst
->src
[i
].d64
);
7100 case BRW_REGISTER_TYPE_UQ
:
7101 fprintf(file
, "%" PRIu64
"uq", inst
->src
[i
].u64
);
7103 case BRW_REGISTER_TYPE_VF
:
7104 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
7105 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
7106 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
7107 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
7108 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
7110 case BRW_REGISTER_TYPE_V
:
7111 case BRW_REGISTER_TYPE_UV
:
7112 fprintf(file
, "%08x%s", inst
->src
[i
].ud
,
7113 inst
->src
[i
].type
== BRW_REGISTER_TYPE_V
? "V" : "UV");
7116 fprintf(file
, "???");
7121 switch (inst
->src
[i
].nr
) {
7123 fprintf(file
, "null");
7125 case BRW_ARF_ADDRESS
:
7126 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
7128 case BRW_ARF_ACCUMULATOR
:
7129 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
7132 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7135 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7141 if (inst
->src
[i
].offset
||
7142 (inst
->src
[i
].file
== VGRF
&&
7143 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
7144 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
7145 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
7146 inst
->src
[i
].offset
% reg_size
);
7149 if (inst
->src
[i
].abs
)
7152 if (inst
->src
[i
].file
!= IMM
) {
7154 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
7155 unsigned hstride
= inst
->src
[i
].hstride
;
7156 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
7158 stride
= inst
->src
[i
].stride
;
7161 fprintf(file
, "<%u>", stride
);
7163 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
7166 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
7167 fprintf(file
, ", ");
7172 if (inst
->force_writemask_all
)
7173 fprintf(file
, "NoMask ");
7175 if (inst
->exec_size
!= dispatch_width
)
7176 fprintf(file
, "group%d ", inst
->group
);
7178 fprintf(file
, "\n");
7182 fs_visitor::setup_fs_payload_gen6()
7184 assert(stage
== MESA_SHADER_FRAGMENT
);
7185 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
7186 const unsigned payload_width
= MIN2(16, dispatch_width
);
7187 assert(dispatch_width
% payload_width
== 0);
7188 assert(devinfo
->gen
>= 6);
7190 prog_data
->uses_src_depth
= prog_data
->uses_src_w
=
7191 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) != 0;
7193 prog_data
->uses_sample_mask
=
7194 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
7196 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
7198 * "MSDISPMODE_PERSAMPLE is required in order to select
7201 * So we can only really get sample positions if we are doing real
7202 * per-sample dispatch. If we need gl_SamplePosition and we don't have
7203 * persample dispatch, we hard-code it to 0.5.
7205 prog_data
->uses_pos_offset
= prog_data
->persample_dispatch
&&
7206 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
7208 /* R0: PS thread payload header. */
7211 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7212 /* R1: masks, pixel X/Y coordinates. */
7213 payload
.subspan_coord_reg
[j
] = payload
.num_regs
++;
7216 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7217 /* R3-26: barycentric interpolation coordinates. These appear in the
7218 * same order that they appear in the brw_barycentric_mode enum. Each
7219 * set of coordinates occupies 2 registers if dispatch width == 8 and 4
7220 * registers if dispatch width == 16. Coordinates only appear if they
7221 * were enabled using the "Barycentric Interpolation Mode" bits in
7224 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
7225 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
7226 payload
.barycentric_coord_reg
[i
][j
] = payload
.num_regs
;
7227 payload
.num_regs
+= payload_width
/ 4;
7231 /* R27-28: interpolated depth if uses source depth */
7232 if (prog_data
->uses_src_depth
) {
7233 payload
.source_depth_reg
[j
] = payload
.num_regs
;
7234 payload
.num_regs
+= payload_width
/ 8;
7237 /* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
7238 if (prog_data
->uses_src_w
) {
7239 payload
.source_w_reg
[j
] = payload
.num_regs
;
7240 payload
.num_regs
+= payload_width
/ 8;
7243 /* R31: MSAA position offsets. */
7244 if (prog_data
->uses_pos_offset
) {
7245 payload
.sample_pos_reg
[j
] = payload
.num_regs
;
7249 /* R32-33: MSAA input coverage mask */
7250 if (prog_data
->uses_sample_mask
) {
7251 assert(devinfo
->gen
>= 7);
7252 payload
.sample_mask_in_reg
[j
] = payload
.num_regs
;
7253 payload
.num_regs
+= payload_width
/ 8;
7257 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
7258 source_depth_to_render_target
= true;
7263 fs_visitor::setup_vs_payload()
7265 /* R0: thread header, R1: urb handles */
7266 payload
.num_regs
= 2;
7270 fs_visitor::setup_gs_payload()
7272 assert(stage
== MESA_SHADER_GEOMETRY
);
7274 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
7275 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7277 /* R0: thread header, R1: output URB handles */
7278 payload
.num_regs
= 2;
7280 if (gs_prog_data
->include_primitive_id
) {
7281 /* R2: Primitive ID 0..7 */
7285 /* Always enable VUE handles so we can safely use pull model if needed.
7287 * The push model for a GS uses a ton of register space even for trivial
7288 * scenarios with just a few inputs, so just make things easier and a bit
7289 * safer by always having pull model available.
7291 gs_prog_data
->base
.include_vue_handles
= true;
7293 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
7294 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
7296 /* Use a maximum of 24 registers for push-model inputs. */
7297 const unsigned max_push_components
= 24;
7299 /* If pushing our inputs would take too many registers, reduce the URB read
7300 * length (which is in HWords, or 8 registers), and resort to pulling.
7302 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
7303 * have to multiply by VerticesIn to obtain the total storage requirement.
7305 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
7306 max_push_components
) {
7307 vue_prog_data
->urb_read_length
=
7308 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
7313 fs_visitor::setup_cs_payload()
7315 assert(devinfo
->gen
>= 7);
7316 payload
.num_regs
= 1;
7320 fs_visitor::calculate_register_pressure()
7322 invalidate_live_intervals();
7323 calculate_live_intervals();
7325 unsigned num_instructions
= 0;
7326 foreach_block(block
, cfg
)
7327 num_instructions
+= block
->instructions
.length();
7329 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
7331 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
7332 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
7333 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
7338 fs_visitor::optimize()
7340 /* Start by validating the shader we currently have. */
7343 /* bld is the common builder object pointing at the end of the program we
7344 * used to translate it into i965 IR. For the optimization and lowering
7345 * passes coming next, any code added after the end of the program without
7346 * having explicitly called fs_builder::at() clearly points at a mistake.
7347 * Ideally optimization passes wouldn't be part of the visitor so they
7348 * wouldn't have access to bld at all, but they do, so just in case some
7349 * pass forgets to ask for a location explicitly set it to NULL here to
7350 * make it trip. The dispatch width is initialized to a bogus value to
7351 * make sure that optimizations set the execution controls explicitly to
7352 * match the code they are manipulating instead of relying on the defaults.
7354 bld
= fs_builder(this, 64);
7356 assign_constant_locations();
7357 lower_constant_loads();
7361 split_virtual_grfs();
7364 #define OPT(pass, args...) ({ \
7366 bool this_progress = pass(args); \
7368 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
7369 char filename[64]; \
7370 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
7371 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
7373 backend_shader::dump_instructions(filename); \
7378 progress = progress || this_progress; \
7382 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
7384 snprintf(filename
, 64, "%s%d-%s-00-00-start",
7385 stage_abbrev
, dispatch_width
, nir
->info
.name
);
7387 backend_shader::dump_instructions(filename
);
7390 bool progress
= false;
7394 /* Before anything else, eliminate dead code. The results of some NIR
7395 * instructions may effectively be calculated twice. Once when the
7396 * instruction is encountered, and again when the user of that result is
7397 * encountered. Wipe those away before algebraic optimizations and
7398 * especially copy propagation can mix things up.
7400 OPT(dead_code_eliminate
);
7402 OPT(remove_extra_rounding_modes
);
7409 OPT(remove_duplicate_mrf_writes
);
7413 OPT(opt_copy_propagation
);
7414 OPT(opt_predicated_break
, this);
7415 OPT(opt_cmod_propagation
);
7416 OPT(dead_code_eliminate
);
7417 OPT(opt_peephole_sel
);
7418 OPT(dead_control_flow_eliminate
, this);
7419 OPT(opt_register_renaming
);
7420 OPT(opt_saturate_propagation
);
7421 OPT(register_coalesce
);
7422 OPT(compute_to_mrf
);
7423 OPT(eliminate_find_live_channel
);
7425 OPT(compact_virtual_grfs
);
7431 if (OPT(lower_pack
)) {
7432 OPT(register_coalesce
);
7433 OPT(dead_code_eliminate
);
7436 OPT(lower_simd_width
);
7437 OPT(lower_barycentrics
);
7439 /* After SIMD lowering just in case we had to unroll the EOT send. */
7440 OPT(opt_sampler_eot
);
7442 OPT(lower_logical_sends
);
7444 /* After logical SEND lowering. */
7445 OPT(fixup_nomask_control_flow
);
7448 OPT(opt_copy_propagation
);
7449 /* Only run after logical send lowering because it's easier to implement
7450 * in terms of physical sends.
7452 if (OPT(opt_zero_samples
))
7453 OPT(opt_copy_propagation
);
7454 /* Run after logical send lowering to give it a chance to CSE the
7455 * LOAD_PAYLOAD instructions created to construct the payloads of
7456 * e.g. texturing messages in cases where it wasn't possible to CSE the
7457 * whole logical instruction.
7460 OPT(register_coalesce
);
7461 OPT(compute_to_mrf
);
7462 OPT(dead_code_eliminate
);
7463 OPT(remove_duplicate_mrf_writes
);
7464 OPT(opt_peephole_sel
);
7467 OPT(opt_redundant_discard_jumps
);
7469 if (OPT(lower_load_payload
)) {
7470 split_virtual_grfs();
7472 /* Lower 64 bit MOVs generated by payload lowering. */
7473 if (!devinfo
->has_64bit_float
&& !devinfo
->has_64bit_int
)
7476 OPT(register_coalesce
);
7477 OPT(lower_simd_width
);
7478 OPT(compute_to_mrf
);
7479 OPT(dead_code_eliminate
);
7482 OPT(opt_combine_constants
);
7483 OPT(lower_integer_multiplication
);
7486 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
7487 OPT(opt_cmod_propagation
);
7489 OPT(opt_copy_propagation
);
7490 OPT(dead_code_eliminate
);
7493 if (OPT(lower_regioning
)) {
7494 OPT(opt_copy_propagation
);
7495 OPT(dead_code_eliminate
);
7496 OPT(lower_simd_width
);
7499 OPT(fixup_sends_duplicate_payload
);
7501 lower_uniform_pull_constant_loads();
7507 * From the Skylake PRM Vol. 2a docs for sends:
7509 * "It is required that the second block of GRFs does not overlap with the
7512 * There are plenty of cases where we may accidentally violate this due to
7513 * having, for instance, both sources be the constant 0. This little pass
7514 * just adds a new vgrf for the second payload and copies it over.
7517 fs_visitor::fixup_sends_duplicate_payload()
7519 bool progress
= false;
7521 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7522 if (inst
->opcode
== SHADER_OPCODE_SEND
&& inst
->ex_mlen
> 0 &&
7523 regions_overlap(inst
->src
[2], inst
->mlen
* REG_SIZE
,
7524 inst
->src
[3], inst
->ex_mlen
* REG_SIZE
)) {
7525 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(inst
->ex_mlen
),
7526 BRW_REGISTER_TYPE_UD
);
7527 /* Sadly, we've lost all notion of channels and bit sizes at this
7528 * point. Just WE_all it.
7530 const fs_builder ibld
= bld
.at(block
, inst
).exec_all().group(16, 0);
7531 fs_reg copy_src
= retype(inst
->src
[3], BRW_REGISTER_TYPE_UD
);
7532 fs_reg copy_dst
= tmp
;
7533 for (unsigned i
= 0; i
< inst
->ex_mlen
; i
+= 2) {
7534 if (inst
->ex_mlen
== i
+ 1) {
7535 /* Only one register left; do SIMD8 */
7536 ibld
.group(8, 0).MOV(copy_dst
, copy_src
);
7538 ibld
.MOV(copy_dst
, copy_src
);
7540 copy_src
= offset(copy_src
, ibld
, 1);
7541 copy_dst
= offset(copy_dst
, ibld
, 1);
7549 invalidate_live_intervals();
7555 * Three source instruction must have a GRF/MRF destination register.
7556 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
7559 fs_visitor::fixup_3src_null_dest()
7561 bool progress
= false;
7563 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7564 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
7565 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
7572 invalidate_live_intervals();
7576 * Find the first instruction in the program that might start a region of
7577 * divergent control flow due to a HALT jump. There is no
7578 * find_halt_control_flow_region_end(), the region of divergence extends until
7579 * the only FS_OPCODE_PLACEHOLDER_HALT in the program.
7581 static const fs_inst
*
7582 find_halt_control_flow_region_start(const fs_visitor
*v
)
7584 if (brw_wm_prog_data(v
->prog_data
)->uses_kill
) {
7585 foreach_block_and_inst(block
, fs_inst
, inst
, v
->cfg
) {
7586 if (inst
->opcode
== FS_OPCODE_DISCARD_JUMP
||
7587 inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
)
7596 * Work around the Gen12 hardware bug filed as GEN:BUG:1407528679. EU fusion
7597 * can cause a BB to be executed with all channels disabled, which will lead
7598 * to the execution of any NoMask instructions in it, even though any
7599 * execution-masked instructions will be correctly shot down. This may break
7600 * assumptions of some NoMask SEND messages whose descriptor depends on data
7601 * generated by live invocations of the shader.
7603 * This avoids the problem by predicating certain instructions on an ANY
7604 * horizontal predicate that makes sure that their execution is omitted when
7605 * all channels of the program are disabled.
7608 fs_visitor::fixup_nomask_control_flow()
7610 if (devinfo
->gen
!= 12)
7613 const brw_predicate pred
= dispatch_width
> 16 ? BRW_PREDICATE_ALIGN1_ANY32H
:
7614 dispatch_width
> 8 ? BRW_PREDICATE_ALIGN1_ANY16H
:
7615 BRW_PREDICATE_ALIGN1_ANY8H
;
7616 const fs_inst
*halt_start
= find_halt_control_flow_region_start(this);
7618 bool progress
= false;
7620 calculate_live_intervals();
7622 /* Scan the program backwards in order to be able to easily determine
7623 * whether the flag register is live at any point.
7625 foreach_block_reverse_safe(block
, cfg
) {
7626 BITSET_WORD flag_liveout
= live_intervals
->block_data
[block
->num
]
7628 STATIC_ASSERT(ARRAY_SIZE(live_intervals
->block_data
[0].flag_liveout
) == 1);
7630 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
7631 if (!inst
->predicate
&& inst
->exec_size
>= 8)
7632 flag_liveout
&= ~inst
->flags_written();
7634 switch (inst
->opcode
) {
7637 /* Note that this doesn't handle FS_OPCODE_DISCARD_JUMP since only
7638 * the first one in the program closes the region of divergent
7639 * control flow due to any HALT instructions -- Instead this is
7640 * handled with the halt_start check below.
7645 case BRW_OPCODE_WHILE
:
7646 case BRW_OPCODE_ENDIF
:
7647 case FS_OPCODE_PLACEHOLDER_HALT
:
7652 /* Note that the vast majority of NoMask SEND instructions in the
7653 * program are harmless while executed in a block with all
7654 * channels disabled, since any instructions with side effects we
7655 * could hit here should be execution-masked.
7657 * The main concern is NoMask SEND instructions where the message
7658 * descriptor or header depends on data generated by live
7659 * invocations of the shader (RESINFO and
7660 * FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD with a dynamically
7661 * computed surface index seem to be the only examples right now
7662 * where this could easily lead to GPU hangs). Unfortunately we
7663 * have no straightforward way to detect that currently, so just
7664 * predicate any NoMask SEND instructions we find under control
7667 * If this proves to have a measurable performance impact it can
7668 * be easily extended with a whitelist of messages we know we can
7669 * safely omit the predication for.
7671 if (depth
&& inst
->force_writemask_all
&&
7672 is_send(inst
) && !inst
->predicate
) {
7673 /* We need to load the execution mask into the flag register by
7674 * using a builder with channel group matching the whole shader
7675 * (rather than the default which is derived from the original
7676 * instruction), in order to avoid getting a right-shifted
7679 const fs_builder ubld
= fs_builder(this, block
, inst
)
7680 .exec_all().group(dispatch_width
, 0);
7681 const fs_reg flag
= retype(brw_flag_reg(0, 0),
7682 BRW_REGISTER_TYPE_UD
);
7684 /* Due to the lack of flag register allocation we need to save
7685 * and restore the flag register if it's live.
7687 const bool save_flag
= flag_liveout
&
7688 flag_mask(flag
, dispatch_width
/ 8);
7689 const fs_reg tmp
= ubld
.group(1, 0).vgrf(flag
.type
);
7692 ubld
.group(1, 0).MOV(tmp
, flag
);
7694 ubld
.emit(FS_OPCODE_LOAD_LIVE_CHANNELS
);
7696 set_predicate(pred
, inst
);
7697 inst
->flag_subreg
= 0;
7700 ubld
.group(1, 0).at(block
, inst
->next
).MOV(flag
, tmp
);
7707 if (inst
== halt_start
)
7710 flag_liveout
|= inst
->flags_read(devinfo
);
7715 invalidate_live_intervals();
7721 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
7725 static const enum instruction_scheduler_mode pre_modes
[] = {
7727 SCHEDULE_PRE_NON_LIFO
,
7731 static const char *scheduler_mode_name
[] = {
7737 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
7739 /* Try each scheduling heuristic to see if it can successfully register
7740 * allocate without spilling. They should be ordered by decreasing
7741 * performance but increasing likelihood of allocating.
7743 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
7744 schedule_instructions(pre_modes
[i
]);
7745 this->shader_stats
.scheduler_mode
= scheduler_mode_name
[i
];
7748 assign_regs_trivial();
7753 /* We only allow spilling for the last schedule mode and only if the
7754 * allow_spilling parameter and dispatch width work out ok.
7756 bool can_spill
= allow_spilling
&&
7757 (i
== ARRAY_SIZE(pre_modes
) - 1) &&
7758 dispatch_width
== min_dispatch_width
;
7760 /* We should only spill registers on the last scheduling. */
7761 assert(!spilled_any_registers
);
7763 allocated
= assign_regs(can_spill
, spill_all
);
7769 if (!allow_spilling
)
7770 fail("Failure to register allocate and spilling is not allowed.");
7772 /* We assume that any spilling is worse than just dropping back to
7773 * SIMD8. There's probably actually some intermediate point where
7774 * SIMD16 with a couple of spills is still better.
7776 if (dispatch_width
> min_dispatch_width
) {
7777 fail("Failure to register allocate. Reduce number of "
7778 "live scalar values to avoid this.");
7781 /* If we failed to allocate, we must have a reason */
7783 } else if (spilled_any_registers
) {
7784 compiler
->shader_perf_log(log_data
,
7785 "%s shader triggered register spilling. "
7786 "Try reducing the number of live scalar "
7787 "values to improve performance.\n",
7791 /* This must come after all optimization and register allocation, since
7792 * it inserts dead code that happens to have side effects, and it does
7793 * so based on the actual physical registers in use.
7795 insert_gen4_send_dependency_workarounds();
7800 opt_bank_conflicts();
7802 schedule_instructions(SCHEDULE_POST
);
7804 if (last_scratch
> 0) {
7805 ASSERTED
unsigned max_scratch_size
= 2 * 1024 * 1024;
7807 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
7809 if (stage
== MESA_SHADER_COMPUTE
) {
7810 if (devinfo
->is_haswell
) {
7811 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7812 * field documentation, Haswell supports a minimum of 2kB of
7813 * scratch space for compute shaders, unlike every other stage
7816 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
7817 } else if (devinfo
->gen
<= 7) {
7818 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7819 * field documentation, platforms prior to Haswell measure scratch
7820 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
7822 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
7823 max_scratch_size
= 12 * 1024;
7827 /* We currently only support up to 2MB of scratch space. If we
7828 * need to support more eventually, the documentation suggests
7829 * that we could allocate a larger buffer, and partition it out
7830 * ourselves. We'd just have to undo the hardware's address
7831 * calculation by subtracting (FFTID * Per Thread Scratch Space)
7832 * and then add FFTID * (Larger Per Thread Scratch Space).
7834 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
7835 * Thread Group Tracking > Local Memory/Scratch Space.
7837 assert(prog_data
->total_scratch
< max_scratch_size
);
7844 fs_visitor::run_vs()
7846 assert(stage
== MESA_SHADER_VERTEX
);
7850 if (shader_time_index
>= 0)
7851 emit_shader_time_begin();
7860 if (shader_time_index
>= 0)
7861 emit_shader_time_end();
7867 assign_curb_setup();
7868 assign_vs_urb_setup();
7870 fixup_3src_null_dest();
7871 allocate_registers(8, true);
7877 fs_visitor::set_tcs_invocation_id()
7879 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7880 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
7882 const unsigned instance_id_mask
=
7883 devinfo
->gen
>= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
7884 const unsigned instance_id_shift
=
7885 devinfo
->gen
>= 11 ? 16 : 17;
7887 /* Get instance number from g0.2 bits 22:16 or 23:17 */
7888 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7889 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
7890 brw_imm_ud(instance_id_mask
));
7892 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7894 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
) {
7895 /* gl_InvocationID is just the thread number */
7896 bld
.SHR(invocation_id
, t
, brw_imm_ud(instance_id_shift
));
7900 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
);
7902 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
7903 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7904 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
7905 bld
.MOV(channels_ud
, channels_uw
);
7907 if (tcs_prog_data
->instances
== 1) {
7908 invocation_id
= channels_ud
;
7910 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7911 bld
.SHR(instance_times_8
, t
, brw_imm_ud(instance_id_shift
- 3));
7912 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
7917 fs_visitor::run_tcs()
7919 assert(stage
== MESA_SHADER_TESS_CTRL
);
7921 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7922 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7923 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
7925 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
||
7926 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7928 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
7929 /* r1-r4 contain the ICP handles. */
7930 payload
.num_regs
= 5;
7932 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7933 assert(tcs_key
->input_vertices
> 0);
7934 /* r1 contains output handles, r2 may contain primitive ID, then the
7935 * ICP handles occupy the next 1-32 registers.
7937 payload
.num_regs
= 2 + tcs_prog_data
->include_primitive_id
+
7938 tcs_key
->input_vertices
;
7941 if (shader_time_index
>= 0)
7942 emit_shader_time_begin();
7944 /* Initialize gl_InvocationID */
7945 set_tcs_invocation_id();
7947 const bool fix_dispatch_mask
=
7948 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
&&
7949 (nir
->info
.tess
.tcs_vertices_out
% 8) != 0;
7951 /* Fix the disptach mask */
7952 if (fix_dispatch_mask
) {
7953 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
7954 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
7955 bld
.IF(BRW_PREDICATE_NORMAL
);
7960 if (fix_dispatch_mask
) {
7961 bld
.emit(BRW_OPCODE_ENDIF
);
7964 /* Emit EOT write; set TR DS Cache bit */
7966 fs_reg(get_tcs_output_urb_handle()),
7967 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
7968 fs_reg(brw_imm_ud(0)),
7970 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
7971 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
7973 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
7974 bld
.null_reg_ud(), payload
);
7978 if (shader_time_index
>= 0)
7979 emit_shader_time_end();
7988 assign_curb_setup();
7989 assign_tcs_urb_setup();
7991 fixup_3src_null_dest();
7992 allocate_registers(8, true);
7998 fs_visitor::run_tes()
8000 assert(stage
== MESA_SHADER_TESS_EVAL
);
8002 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
8003 payload
.num_regs
= 5;
8005 if (shader_time_index
>= 0)
8006 emit_shader_time_begin();
8015 if (shader_time_index
>= 0)
8016 emit_shader_time_end();
8022 assign_curb_setup();
8023 assign_tes_urb_setup();
8025 fixup_3src_null_dest();
8026 allocate_registers(8, true);
8032 fs_visitor::run_gs()
8034 assert(stage
== MESA_SHADER_GEOMETRY
);
8038 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
8040 if (gs_compile
->control_data_header_size_bits
> 0) {
8041 /* Create a VGRF to store accumulated control data bits. */
8042 this->control_data_bits
= vgrf(glsl_type::uint_type
);
8044 /* If we're outputting more than 32 control data bits, then EmitVertex()
8045 * will set control_data_bits to 0 after emitting the first vertex.
8046 * Otherwise, we need to initialize it to 0 here.
8048 if (gs_compile
->control_data_header_size_bits
<= 32) {
8049 const fs_builder abld
= bld
.annotate("initialize control data bits");
8050 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
8054 if (shader_time_index
>= 0)
8055 emit_shader_time_begin();
8059 emit_gs_thread_end();
8061 if (shader_time_index
>= 0)
8062 emit_shader_time_end();
8071 assign_curb_setup();
8072 assign_gs_urb_setup();
8074 fixup_3src_null_dest();
8075 allocate_registers(8, true);
8080 /* From the SKL PRM, Volume 16, Workarounds:
8082 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
8083 * only header phases (R0-R2)
8085 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
8086 * have been header only.
8088 * Instead of enabling push constants one can alternatively enable one of the
8089 * inputs. Here one simply chooses "layer" which shouldn't impose much
8093 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
8095 if (wm_prog_data
->num_varying_inputs
)
8098 if (wm_prog_data
->base
.curb_read_length
)
8101 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
8102 wm_prog_data
->num_varying_inputs
= 1;
8106 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
8108 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
8109 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
8111 assert(stage
== MESA_SHADER_FRAGMENT
);
8113 if (devinfo
->gen
>= 6)
8114 setup_fs_payload_gen6();
8116 setup_fs_payload_gen4();
8120 } else if (do_rep_send
) {
8121 assert(dispatch_width
== 16);
8122 emit_repclear_shader();
8124 if (shader_time_index
>= 0)
8125 emit_shader_time_begin();
8127 if (nir
->info
.inputs_read
> 0 ||
8128 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) ||
8129 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
8130 if (devinfo
->gen
< 6)
8131 emit_interpolation_setup_gen4();
8133 emit_interpolation_setup_gen6();
8136 /* We handle discards by keeping track of the still-live pixels in f0.1.
8137 * Initialize it with the dispatched pixels.
8139 if (wm_prog_data
->uses_kill
) {
8140 const fs_reg dispatch_mask
=
8141 devinfo
->gen
>= 6 ? brw_vec1_grf(1, 7) : brw_vec1_grf(0, 0);
8142 bld
.exec_all().group(1, 0)
8143 .MOV(retype(brw_flag_reg(0, 1), BRW_REGISTER_TYPE_UW
),
8144 retype(dispatch_mask
, BRW_REGISTER_TYPE_UW
));
8152 if (wm_prog_data
->uses_kill
)
8153 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
8155 if (wm_key
->alpha_test_func
)
8160 if (shader_time_index
>= 0)
8161 emit_shader_time_end();
8167 assign_curb_setup();
8169 if (devinfo
->gen
>= 9)
8170 gen9_ps_header_only_workaround(wm_prog_data
);
8174 fixup_3src_null_dest();
8175 allocate_registers(8, allow_spilling
);
8185 fs_visitor::run_cs(unsigned min_dispatch_width
)
8187 assert(stage
== MESA_SHADER_COMPUTE
);
8188 assert(dispatch_width
>= min_dispatch_width
);
8192 if (shader_time_index
>= 0)
8193 emit_shader_time_begin();
8195 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
8196 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
8197 const fs_builder abld
= bld
.exec_all().group(1, 0);
8198 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
8199 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
8207 emit_cs_terminate();
8209 if (shader_time_index
>= 0)
8210 emit_shader_time_end();
8216 assign_curb_setup();
8218 fixup_3src_null_dest();
8219 allocate_registers(min_dispatch_width
, true);
8228 is_used_in_not_interp_frag_coord(nir_ssa_def
*def
)
8230 nir_foreach_use(src
, def
) {
8231 if (src
->parent_instr
->type
!= nir_instr_type_intrinsic
)
8234 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(src
->parent_instr
);
8235 if (intrin
->intrinsic
!= nir_intrinsic_load_frag_coord
)
8239 nir_foreach_if_use(src
, def
)
8246 * Return a bitfield where bit n is set if barycentric interpolation mode n
8247 * (see enum brw_barycentric_mode) is needed by the fragment shader.
8249 * We examine the load_barycentric intrinsics rather than looking at input
8250 * variables so that we catch interpolateAtCentroid() messages too, which
8251 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
8254 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
8255 const nir_shader
*shader
)
8257 unsigned barycentric_interp_modes
= 0;
8259 nir_foreach_function(f
, shader
) {
8263 nir_foreach_block(block
, f
->impl
) {
8264 nir_foreach_instr(instr
, block
) {
8265 if (instr
->type
!= nir_instr_type_intrinsic
)
8268 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8269 switch (intrin
->intrinsic
) {
8270 case nir_intrinsic_load_barycentric_pixel
:
8271 case nir_intrinsic_load_barycentric_centroid
:
8272 case nir_intrinsic_load_barycentric_sample
:
8278 /* Ignore WPOS; it doesn't require interpolation. */
8279 assert(intrin
->dest
.is_ssa
);
8280 if (!is_used_in_not_interp_frag_coord(&intrin
->dest
.ssa
))
8283 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
8284 nir_intrinsic_interp_mode(intrin
);
8285 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
8286 enum brw_barycentric_mode bary
=
8287 brw_barycentric_mode(interp
, bary_op
);
8289 barycentric_interp_modes
|= 1 << bary
;
8291 if (devinfo
->needs_unlit_centroid_workaround
&&
8292 bary_op
== nir_intrinsic_load_barycentric_centroid
)
8293 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
8298 return barycentric_interp_modes
;
8302 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
8303 const nir_shader
*shader
)
8305 prog_data
->flat_inputs
= 0;
8307 nir_foreach_variable(var
, &shader
->inputs
) {
8308 unsigned slots
= glsl_count_attribute_slots(var
->type
, false);
8309 for (unsigned s
= 0; s
< slots
; s
++) {
8310 int input_index
= prog_data
->urb_setup
[var
->data
.location
+ s
];
8312 if (input_index
< 0)
8316 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
8317 prog_data
->flat_inputs
|= 1 << input_index
;
8323 computed_depth_mode(const nir_shader
*shader
)
8325 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
8326 switch (shader
->info
.fs
.depth_layout
) {
8327 case FRAG_DEPTH_LAYOUT_NONE
:
8328 case FRAG_DEPTH_LAYOUT_ANY
:
8329 return BRW_PSCDEPTH_ON
;
8330 case FRAG_DEPTH_LAYOUT_GREATER
:
8331 return BRW_PSCDEPTH_ON_GE
;
8332 case FRAG_DEPTH_LAYOUT_LESS
:
8333 return BRW_PSCDEPTH_ON_LE
;
8334 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
8335 return BRW_PSCDEPTH_OFF
;
8338 return BRW_PSCDEPTH_OFF
;
8342 * Move load_interpolated_input with simple (payload-based) barycentric modes
8343 * to the top of the program so we don't emit multiple PLNs for the same input.
8345 * This works around CSE not being able to handle non-dominating cases
8351 * interpolate the same exact input
8354 * This should be replaced by global value numbering someday.
8357 move_interpolation_to_top(nir_shader
*nir
)
8359 bool progress
= false;
8361 nir_foreach_function(f
, nir
) {
8365 nir_block
*top
= nir_start_block(f
->impl
);
8366 exec_node
*cursor_node
= NULL
;
8368 nir_foreach_block(block
, f
->impl
) {
8372 nir_foreach_instr_safe(instr
, block
) {
8373 if (instr
->type
!= nir_instr_type_intrinsic
)
8376 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8377 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
8379 nir_intrinsic_instr
*bary_intrinsic
=
8380 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
8381 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
8383 /* Leave interpolateAtSample/Offset() where they are. */
8384 if (op
== nir_intrinsic_load_barycentric_at_sample
||
8385 op
== nir_intrinsic_load_barycentric_at_offset
)
8388 nir_instr
*move
[3] = {
8389 &bary_intrinsic
->instr
,
8390 intrin
->src
[1].ssa
->parent_instr
,
8394 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
8395 if (move
[i
]->block
!= top
) {
8396 move
[i
]->block
= top
;
8397 exec_node_remove(&move
[i
]->node
);
8399 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
8401 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
8403 cursor_node
= &move
[i
]->node
;
8409 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8410 ((unsigned) nir_metadata_block_index
|
8411 (unsigned) nir_metadata_dominance
));
8418 * Demote per-sample barycentric intrinsics to centroid.
8420 * Useful when rendering to a non-multisampled buffer.
8423 demote_sample_qualifiers(nir_shader
*nir
)
8425 bool progress
= true;
8427 nir_foreach_function(f
, nir
) {
8432 nir_builder_init(&b
, f
->impl
);
8434 nir_foreach_block(block
, f
->impl
) {
8435 nir_foreach_instr_safe(instr
, block
) {
8436 if (instr
->type
!= nir_instr_type_intrinsic
)
8439 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8440 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
8441 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
8444 b
.cursor
= nir_before_instr(instr
);
8445 nir_ssa_def
*centroid
=
8446 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
8447 nir_intrinsic_interp_mode(intrin
));
8448 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
8449 nir_src_for_ssa(centroid
));
8450 nir_instr_remove(instr
);
8455 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8456 ((unsigned) nir_metadata_block_index
|
8457 (unsigned) nir_metadata_dominance
));
8464 * Pre-gen6, the register file of the EUs was shared between threads,
8465 * and each thread used some subset allocated on a 16-register block
8466 * granularity. The unit states wanted these block counts.
8469 brw_register_blocks(int reg_count
)
8471 return ALIGN(reg_count
, 16) / 16 - 1;
8475 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
8477 const struct brw_wm_prog_key
*key
,
8478 struct brw_wm_prog_data
*prog_data
,
8480 int shader_time_index8
, int shader_time_index16
,
8481 int shader_time_index32
, bool allow_spilling
,
8482 bool use_rep_send
, struct brw_vue_map
*vue_map
,
8483 struct brw_compile_stats
*stats
,
8486 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
8488 unsigned max_subgroup_size
= unlikely(INTEL_DEBUG
& DEBUG_DO32
) ? 32 : 16;
8490 brw_nir_apply_key(shader
, compiler
, &key
->base
, max_subgroup_size
, true);
8491 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
8492 brw_nir_lower_fs_outputs(shader
);
8494 if (devinfo
->gen
< 6)
8495 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
);
8497 /* From the SKL PRM, Volume 7, "Alpha Coverage":
8498 * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
8499 * hardware, regardless of the state setting for this feature."
8501 if (devinfo
->gen
> 6 && key
->alpha_to_coverage
) {
8502 /* Run constant fold optimization in order to get the correct source
8503 * offset to determine render target 0 store instruction in
8504 * emit_alpha_to_coverage pass.
8506 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8507 NIR_PASS_V(shader
, brw_nir_lower_alpha_to_coverage
);
8510 if (!key
->multisample_fbo
)
8511 NIR_PASS_V(shader
, demote_sample_qualifiers
);
8512 NIR_PASS_V(shader
, move_interpolation_to_top
);
8513 brw_postprocess_nir(shader
, compiler
, true);
8515 /* key->alpha_test_func means simulating alpha testing via discards,
8516 * so the shader definitely kills pixels.
8518 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
8519 key
->alpha_test_func
;
8520 prog_data
->uses_omask
= key
->multisample_fbo
&&
8521 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
8522 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
8523 prog_data
->computed_stencil
=
8524 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
8526 prog_data
->persample_dispatch
=
8527 key
->multisample_fbo
&&
8528 (key
->persample_interp
||
8529 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
8530 SYSTEM_BIT_SAMPLE_POS
)) ||
8531 shader
->info
.fs
.uses_sample_qualifier
||
8532 shader
->info
.outputs_read
);
8534 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
8536 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
8537 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
8538 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
8540 prog_data
->barycentric_interp_modes
=
8541 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
8543 calculate_urb_setup(devinfo
, key
, prog_data
, shader
);
8544 brw_compute_flat_inputs(prog_data
, shader
);
8546 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
, *simd32_cfg
= NULL
;
8548 fs_visitor
v8(compiler
, log_data
, mem_ctx
, &key
->base
,
8549 &prog_data
->base
, shader
, 8,
8550 shader_time_index8
);
8551 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
8553 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
8556 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
8558 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
8559 prog_data
->reg_blocks_8
= brw_register_blocks(v8
.grf_used
);
8562 /* Limit dispatch width to simd8 with dual source blending on gen8.
8563 * See: https://gitlab.freedesktop.org/mesa/mesa/issues/1917
8565 if (devinfo
->gen
== 8 && prog_data
->dual_src_blend
&&
8566 !(INTEL_DEBUG
& DEBUG_NO8
)) {
8567 assert(!use_rep_send
);
8568 v8
.limit_dispatch_width(8, "gen8 workaround: "
8569 "using SIMD8 when dual src blending.\n");
8572 if (v8
.max_dispatch_width
>= 16 &&
8573 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
8574 /* Try a SIMD16 compile */
8575 fs_visitor
v16(compiler
, log_data
, mem_ctx
, &key
->base
,
8576 &prog_data
->base
, shader
, 16,
8577 shader_time_index16
);
8578 v16
.import_uniforms(&v8
);
8579 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
8580 compiler
->shader_perf_log(log_data
,
8581 "SIMD16 shader failed to compile: %s",
8584 simd16_cfg
= v16
.cfg
;
8585 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
8586 prog_data
->reg_blocks_16
= brw_register_blocks(v16
.grf_used
);
8590 /* Currently, the compiler only supports SIMD32 on SNB+ */
8591 if (v8
.max_dispatch_width
>= 32 && !use_rep_send
&&
8592 compiler
->devinfo
->gen
>= 6 &&
8593 unlikely(INTEL_DEBUG
& DEBUG_DO32
)) {
8594 /* Try a SIMD32 compile */
8595 fs_visitor
v32(compiler
, log_data
, mem_ctx
, &key
->base
,
8596 &prog_data
->base
, shader
, 32,
8597 shader_time_index32
);
8598 v32
.import_uniforms(&v8
);
8599 if (!v32
.run_fs(allow_spilling
, false)) {
8600 compiler
->shader_perf_log(log_data
,
8601 "SIMD32 shader failed to compile: %s",
8604 simd32_cfg
= v32
.cfg
;
8605 prog_data
->dispatch_grf_start_reg_32
= v32
.payload
.num_regs
;
8606 prog_data
->reg_blocks_32
= brw_register_blocks(v32
.grf_used
);
8610 /* When the caller requests a repclear shader, they want SIMD16-only */
8614 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
8615 * at the top to select the shader. We've never implemented that.
8616 * Instead, we just give them exactly one shader and we pick the widest one
8619 if (compiler
->devinfo
->gen
< 5) {
8620 if (simd32_cfg
|| simd16_cfg
)
8626 /* If computed depth is enabled SNB only allows SIMD8. */
8627 if (compiler
->devinfo
->gen
== 6 &&
8628 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
)
8629 assert(simd16_cfg
== NULL
&& simd32_cfg
== NULL
);
8631 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
8632 /* Iron lake and earlier only have one Dispatch GRF start field. Make
8633 * the data available in the base prog data struct for convenience.
8636 prog_data
->base
.dispatch_grf_start_reg
=
8637 prog_data
->dispatch_grf_start_reg_16
;
8638 } else if (simd32_cfg
) {
8639 prog_data
->base
.dispatch_grf_start_reg
=
8640 prog_data
->dispatch_grf_start_reg_32
;
8644 if (prog_data
->persample_dispatch
) {
8645 /* Starting with SandyBridge (where we first get MSAA), the different
8646 * pixel dispatch combinations are grouped into classifications A
8647 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
8648 * generations, the only configurations supporting persample dispatch
8649 * are are this in which only one dispatch width is enabled.
8651 if (simd32_cfg
|| simd16_cfg
)
8657 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8658 v8
.shader_stats
, v8
.runtime_check_aads_emit
,
8659 MESA_SHADER_FRAGMENT
);
8661 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
8662 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
8663 shader
->info
.label
?
8664 shader
->info
.label
: "unnamed",
8665 shader
->info
.name
));
8669 prog_data
->dispatch_8
= true;
8670 g
.generate_code(simd8_cfg
, 8, stats
);
8671 stats
= stats
? stats
+ 1 : NULL
;
8675 prog_data
->dispatch_16
= true;
8676 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16, stats
);
8677 stats
= stats
? stats
+ 1 : NULL
;
8681 prog_data
->dispatch_32
= true;
8682 prog_data
->prog_offset_32
= g
.generate_code(simd32_cfg
, 32, stats
);
8683 stats
= stats
? stats
+ 1 : NULL
;
8686 return g
.get_assembly();
8690 fs_visitor::emit_cs_work_group_id_setup()
8692 assert(stage
== MESA_SHADER_COMPUTE
);
8694 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
8696 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
8697 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
8698 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
8700 bld
.MOV(*reg
, r0_1
);
8701 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
8702 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
8708 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
8710 block
->dwords
= dwords
;
8711 block
->regs
= DIV_ROUND_UP(dwords
, 8);
8712 block
->size
= block
->regs
* 32;
8716 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
8717 struct brw_cs_prog_data
*cs_prog_data
)
8719 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
8720 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
8721 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
8723 /* The thread ID should be stored in the last param dword */
8724 assert(subgroup_id_index
== -1 ||
8725 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
8727 unsigned cross_thread_dwords
, per_thread_dwords
;
8728 if (!cross_thread_supported
) {
8729 cross_thread_dwords
= 0u;
8730 per_thread_dwords
= prog_data
->nr_params
;
8731 } else if (subgroup_id_index
>= 0) {
8732 /* Fill all but the last register with cross-thread payload */
8733 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
8734 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
8735 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
8737 /* Fill all data using cross-thread payload */
8738 cross_thread_dwords
= prog_data
->nr_params
;
8739 per_thread_dwords
= 0u;
8742 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
8743 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
8745 unsigned total_dwords
=
8746 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
8747 cs_prog_data
->push
.cross_thread
.size
) / 4;
8748 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
8750 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
8751 cs_prog_data
->push
.per_thread
.size
== 0);
8752 assert(cs_prog_data
->push
.cross_thread
.dwords
+
8753 cs_prog_data
->push
.per_thread
.dwords
==
8754 prog_data
->nr_params
);
8758 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
8760 cs_prog_data
->simd_size
= size
;
8761 unsigned group_size
= cs_prog_data
->local_size
[0] *
8762 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
8763 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
8767 compile_cs_to_nir(const struct brw_compiler
*compiler
,
8769 const struct brw_cs_prog_key
*key
,
8770 const nir_shader
*src_shader
,
8771 unsigned dispatch_width
)
8773 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
8774 brw_nir_apply_key(shader
, compiler
, &key
->base
, dispatch_width
, true);
8776 NIR_PASS_V(shader
, brw_nir_lower_cs_intrinsics
, dispatch_width
);
8778 /* Clean up after the local index and ID calculations. */
8779 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8780 NIR_PASS_V(shader
, nir_opt_dce
);
8782 brw_postprocess_nir(shader
, compiler
, true);
8788 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
8790 const struct brw_cs_prog_key
*key
,
8791 struct brw_cs_prog_data
*prog_data
,
8792 const nir_shader
*src_shader
,
8793 int shader_time_index
,
8794 struct brw_compile_stats
*stats
,
8797 prog_data
->base
.total_shared
= src_shader
->info
.cs
.shared_size
;
8798 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
8799 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
8800 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
8801 prog_data
->slm_size
= src_shader
->num_shared
;
8802 unsigned local_workgroup_size
=
8803 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
8804 src_shader
->info
.cs
.local_size
[2];
8806 unsigned min_dispatch_width
=
8807 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
8808 min_dispatch_width
= MAX2(8, min_dispatch_width
);
8809 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
8810 assert(min_dispatch_width
<= 32);
8811 unsigned max_dispatch_width
= 32;
8813 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
8814 fs_visitor
*v
= NULL
;
8815 const char *fail_msg
= NULL
;
8817 if ((int)key
->base
.subgroup_size_type
>= (int)BRW_SUBGROUP_SIZE_REQUIRE_8
) {
8818 /* These enum values are expressly chosen to be equal to the subgroup
8819 * size that they require.
8821 const unsigned required_dispatch_width
=
8822 (unsigned)key
->base
.subgroup_size_type
;
8823 assert(required_dispatch_width
== 8 ||
8824 required_dispatch_width
== 16 ||
8825 required_dispatch_width
== 32);
8826 if (required_dispatch_width
< min_dispatch_width
||
8827 required_dispatch_width
> max_dispatch_width
) {
8828 fail_msg
= "Cannot satisfy explicit subgroup size";
8830 min_dispatch_width
= max_dispatch_width
= required_dispatch_width
;
8834 /* Now the main event: Visit the shader IR and generate our CS IR for it.
8836 if (!fail_msg
&& min_dispatch_width
<= 8 && max_dispatch_width
>= 8) {
8837 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8839 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8841 nir8
, 8, shader_time_index
);
8842 if (!v8
->run_cs(min_dispatch_width
)) {
8843 fail_msg
= v8
->fail_msg
;
8845 /* We should always be able to do SIMD32 for compute shaders */
8846 assert(v8
->max_dispatch_width
>= 32);
8849 cs_set_simd_size(prog_data
, 8);
8850 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8854 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
8855 !fail_msg
&& min_dispatch_width
<= 16 && max_dispatch_width
>= 16) {
8856 /* Try a SIMD16 compile */
8857 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8859 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8861 nir16
, 16, shader_time_index
);
8863 v16
->import_uniforms(v8
);
8865 if (!v16
->run_cs(min_dispatch_width
)) {
8866 compiler
->shader_perf_log(log_data
,
8867 "SIMD16 shader failed to compile: %s",
8871 "Couldn't generate SIMD16 program and not "
8872 "enough threads for SIMD8";
8875 /* We should always be able to do SIMD32 for compute shaders */
8876 assert(v16
->max_dispatch_width
>= 32);
8879 cs_set_simd_size(prog_data
, 16);
8880 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8884 /* We should always be able to do SIMD32 for compute shaders */
8885 assert(!v16
|| v16
->max_dispatch_width
>= 32);
8887 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
)) &&
8888 max_dispatch_width
>= 32) {
8889 /* Try a SIMD32 compile */
8890 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8892 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8894 nir32
, 32, shader_time_index
);
8896 v32
->import_uniforms(v8
);
8898 v32
->import_uniforms(v16
);
8900 if (!v32
->run_cs(min_dispatch_width
)) {
8901 compiler
->shader_perf_log(log_data
,
8902 "SIMD32 shader failed to compile: %s",
8906 "Couldn't generate SIMD32 program and not "
8907 "enough threads for SIMD16";
8911 cs_set_simd_size(prog_data
, 32);
8912 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8916 const unsigned *ret
= NULL
;
8917 if (unlikely(v
== NULL
)) {
8920 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
8922 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8923 v
->shader_stats
, v
->runtime_check_aads_emit
,
8924 MESA_SHADER_COMPUTE
);
8925 if (INTEL_DEBUG
& DEBUG_CS
) {
8926 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
8927 src_shader
->info
.label
?
8928 src_shader
->info
.label
: "unnamed",
8929 src_shader
->info
.name
);
8930 g
.enable_debug(name
);
8933 g
.generate_code(v
->cfg
, prog_data
->simd_size
, stats
);
8935 ret
= g
.get_assembly();
8946 * Test the dispatch mask packing assumptions of
8947 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
8948 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
8949 * executed with an unexpected dispatch mask.
8952 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
8954 const gl_shader_stage stage
= bld
.shader
->stage
;
8956 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
8957 bld
.shader
->stage_prog_data
)) {
8958 const fs_builder ubld
= bld
.exec_all().group(1, 0);
8959 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
8960 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
8963 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
8964 ubld
.AND(tmp
, mask
, tmp
);
8966 /* This will loop forever if the dispatch mask doesn't have the expected
8967 * form '2^n-1', in which case tmp will be non-zero.
8969 bld
.emit(BRW_OPCODE_DO
);
8970 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
8971 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));
8976 fs_visitor::workgroup_size() const
8978 assert(stage
== MESA_SHADER_COMPUTE
);
8979 const struct brw_cs_prog_data
*cs
= brw_cs_prog_data(prog_data
);
8980 return cs
->local_size
[0] * cs
->local_size
[1] * cs
->local_size
[2];