2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "common/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
45 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
49 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
50 const fs_reg
*src
, unsigned sources
)
52 memset(this, 0, sizeof(*this));
54 this->src
= new fs_reg
[MAX2(sources
, 3)];
55 for (unsigned i
= 0; i
< sources
; i
++)
56 this->src
[i
] = src
[i
];
58 this->opcode
= opcode
;
60 this->sources
= sources
;
61 this->exec_size
= exec_size
;
64 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
66 assert(this->exec_size
!= 0);
68 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
70 /* This will be the case for almost all instructions. */
77 this->size_written
= dst
.component_size(exec_size
);
80 this->size_written
= 0;
84 unreachable("Invalid destination register file");
87 this->writes_accumulator
= false;
92 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
95 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
97 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
100 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
102 init(opcode
, exec_size
, dst
, NULL
, 0);
105 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
108 const fs_reg src
[1] = { src0
};
109 init(opcode
, exec_size
, dst
, src
, 1);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
113 const fs_reg
&src0
, const fs_reg
&src1
)
115 const fs_reg src
[2] = { src0
, src1
};
116 init(opcode
, exec_size
, dst
, src
, 2);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
122 const fs_reg src
[3] = { src0
, src1
, src2
};
123 init(opcode
, exec_size
, dst
, src
, 3);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
127 const fs_reg src
[], unsigned sources
)
129 init(opcode
, exec_width
, dst
, src
, sources
);
132 fs_inst::fs_inst(const fs_inst
&that
)
134 memcpy(this, &that
, sizeof(that
));
136 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
138 for (unsigned i
= 0; i
< that
.sources
; i
++)
139 this->src
[i
] = that
.src
[i
];
148 fs_inst::resize_sources(uint8_t num_sources
)
150 if (this->sources
!= num_sources
) {
151 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
153 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
154 src
[i
] = this->src
[i
];
158 this->sources
= num_sources
;
163 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
165 const fs_reg
&surf_index
,
166 const fs_reg
&varying_offset
,
167 uint32_t const_offset
)
169 /* We have our constant surface use a pitch of 4 bytes, so our index can
170 * be any component of a vector, and then we load 4 contiguous
171 * components starting from that.
173 * We break down the const_offset to a portion added to the variable offset
174 * and a portion done using fs_reg::offset, which means that if you have
175 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
176 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
177 * later notice that those loads are all the same and eliminate the
180 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
181 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
183 /* The pull load message will load a vec4 (16 bytes). If we are loading
184 * a double this means we are only loading 2 elements worth of data.
185 * We also want to use a 32-bit data type for the dst of the load operation
186 * so other parts of the driver don't get confused about the size of the
189 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
190 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
191 vec4_result
, surf_index
, vec4_offset
);
192 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
194 if (type_sz(dst
.type
) == 8) {
195 shuffle_32bit_load_result_to_64bit_data(
196 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
199 vec4_result
.type
= dst
.type
;
200 bld
.MOV(dst
, offset(vec4_result
, bld
,
201 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
205 * A helper for MOV generation for fixing up broken hardware SEND dependency
209 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
211 /* The caller always wants uncompressed to emit the minimal extra
212 * dependencies, and to avoid having to deal with aligning its regs to 2.
214 const fs_builder ubld
= bld
.annotate("send dependency resolve")
217 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
221 fs_inst::equals(fs_inst
*inst
) const
223 return (opcode
== inst
->opcode
&&
224 dst
.equals(inst
->dst
) &&
225 src
[0].equals(inst
->src
[0]) &&
226 src
[1].equals(inst
->src
[1]) &&
227 src
[2].equals(inst
->src
[2]) &&
228 saturate
== inst
->saturate
&&
229 predicate
== inst
->predicate
&&
230 conditional_mod
== inst
->conditional_mod
&&
231 mlen
== inst
->mlen
&&
232 base_mrf
== inst
->base_mrf
&&
233 target
== inst
->target
&&
235 header_size
== inst
->header_size
&&
236 shadow_compare
== inst
->shadow_compare
&&
237 exec_size
== inst
->exec_size
&&
238 offset
== inst
->offset
);
242 fs_inst::is_send_from_grf() const
245 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
246 case SHADER_OPCODE_SHADER_TIME_ADD
:
247 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
248 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
249 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
250 case SHADER_OPCODE_UNTYPED_ATOMIC
:
251 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
252 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
253 case SHADER_OPCODE_TYPED_ATOMIC
:
254 case SHADER_OPCODE_TYPED_SURFACE_READ
:
255 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
256 case SHADER_OPCODE_URB_WRITE_SIMD8
:
257 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
258 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
259 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
260 case SHADER_OPCODE_URB_READ_SIMD8
:
261 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
263 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
264 return src
[1].file
== VGRF
;
265 case FS_OPCODE_FB_WRITE
:
266 case FS_OPCODE_FB_READ
:
267 return src
[0].file
== VGRF
;
270 return src
[0].file
== VGRF
;
277 * Returns true if this instruction's sources and destinations cannot
278 * safely be the same register.
280 * In most cases, a register can be written over safely by the same
281 * instruction that is its last use. For a single instruction, the
282 * sources are dereferenced before writing of the destination starts
285 * However, there are a few cases where this can be problematic:
287 * - Virtual opcodes that translate to multiple instructions in the
288 * code generator: if src == dst and one instruction writes the
289 * destination before a later instruction reads the source, then
290 * src will have been clobbered.
292 * - SIMD16 compressed instructions with certain regioning (see below).
294 * The register allocator uses this information to set up conflicts between
295 * GRF sources and the destination.
298 fs_inst::has_source_and_destination_hazard() const
301 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
302 /* Multiple partial writes to the destination */
305 /* The SIMD16 compressed instruction
307 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
309 * is actually decoded in hardware as:
311 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
312 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
314 * Which is safe. However, if we have uniform accesses
315 * happening, we get into trouble:
317 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
318 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
320 * Now our destination for the first instruction overwrote the
321 * second instruction's src0, and we get garbage for those 8
322 * pixels. There's a similar issue for the pre-gen6
323 * pixel_x/pixel_y, which are registers of 16-bit values and thus
324 * would get stomped by the first decode as well.
326 if (exec_size
== 16) {
327 for (int i
= 0; i
< sources
; i
++) {
328 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
329 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
330 src
[i
].type
== BRW_REGISTER_TYPE_W
||
331 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
332 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
342 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
344 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
347 fs_reg reg
= this->src
[0];
348 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
351 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
354 for (int i
= 0; i
< this->sources
; i
++) {
355 reg
.type
= this->src
[i
].type
;
356 if (!this->src
[i
].equals(reg
))
359 if (i
< this->header_size
) {
360 reg
.offset
+= REG_SIZE
;
362 reg
= horiz_offset(reg
, this->exec_size
);
370 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
372 if (devinfo
->gen
== 6 && is_math())
375 if (is_send_from_grf())
378 if (!backend_instruction::can_do_source_mods())
385 fs_inst::can_change_types() const
387 return dst
.type
== src
[0].type
&&
388 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
389 (opcode
== BRW_OPCODE_MOV
||
390 (opcode
== BRW_OPCODE_SEL
&&
391 dst
.type
== src
[1].type
&&
392 predicate
!= BRW_PREDICATE_NONE
&&
393 !src
[1].abs
&& !src
[1].negate
));
399 memset(this, 0, sizeof(*this));
400 type
= BRW_REGISTER_TYPE_UD
;
404 /** Generic unset register constructor. */
408 this->file
= BAD_FILE
;
411 fs_reg::fs_reg(struct ::brw_reg reg
) :
416 if (this->file
== IMM
&&
417 (this->type
!= BRW_REGISTER_TYPE_V
&&
418 this->type
!= BRW_REGISTER_TYPE_UV
&&
419 this->type
!= BRW_REGISTER_TYPE_VF
)) {
425 fs_reg::equals(const fs_reg
&r
) const
427 return (this->backend_reg::equals(r
) &&
432 fs_reg::is_contiguous() const
438 fs_reg::component_size(unsigned width
) const
440 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
443 return MAX2(width
* stride
, 1) * type_sz(type
);
447 type_size_scalar(const struct glsl_type
*type
)
449 unsigned int size
, i
;
451 switch (type
->base_type
) {
454 case GLSL_TYPE_FLOAT
:
456 return type
->components();
457 case GLSL_TYPE_DOUBLE
:
458 case GLSL_TYPE_UINT64
:
459 case GLSL_TYPE_INT64
:
460 return type
->components() * 2;
461 case GLSL_TYPE_ARRAY
:
462 return type_size_scalar(type
->fields
.array
) * type
->length
;
463 case GLSL_TYPE_STRUCT
:
465 for (i
= 0; i
< type
->length
; i
++) {
466 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
469 case GLSL_TYPE_SAMPLER
:
470 /* Samplers take up no register space, since they're baked in at
474 case GLSL_TYPE_ATOMIC_UINT
:
476 case GLSL_TYPE_SUBROUTINE
:
478 case GLSL_TYPE_IMAGE
:
479 return BRW_IMAGE_PARAM_SIZE
;
481 case GLSL_TYPE_ERROR
:
482 case GLSL_TYPE_INTERFACE
:
483 case GLSL_TYPE_FUNCTION
:
484 unreachable("not reached");
491 * Create a MOV to read the timestamp register.
493 * The caller is responsible for emitting the MOV. The return value is
494 * the destination of the MOV, with extra parameters set.
497 fs_visitor::get_timestamp(const fs_builder
&bld
)
499 assert(devinfo
->gen
>= 7);
501 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
504 BRW_REGISTER_TYPE_UD
));
506 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
508 /* We want to read the 3 fields we care about even if it's not enabled in
511 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
517 fs_visitor::emit_shader_time_begin()
519 /* We want only the low 32 bits of the timestamp. Since it's running
520 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
521 * which is plenty of time for our purposes. It is identical across the
522 * EUs, but since it's tracking GPU core speed it will increment at a
523 * varying rate as render P-states change.
525 shader_start_time
= component(
526 get_timestamp(bld
.annotate("shader time start")), 0);
530 fs_visitor::emit_shader_time_end()
532 /* Insert our code just before the final SEND with EOT. */
533 exec_node
*end
= this->instructions
.get_tail();
534 assert(end
&& ((fs_inst
*) end
)->eot
);
535 const fs_builder ibld
= bld
.annotate("shader time end")
536 .exec_all().at(NULL
, end
);
537 const fs_reg timestamp
= get_timestamp(ibld
);
539 /* We only use the low 32 bits of the timestamp - see
540 * emit_shader_time_begin()).
542 * We could also check if render P-states have changed (or anything
543 * else that might disrupt timing) by setting smear to 2 and checking if
544 * that field is != 0.
546 const fs_reg shader_end_time
= component(timestamp
, 0);
548 /* Check that there weren't any timestamp reset events (assuming these
549 * were the only two timestamp reads that happened).
551 const fs_reg reset
= component(timestamp
, 2);
552 set_condmod(BRW_CONDITIONAL_Z
,
553 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
554 ibld
.IF(BRW_PREDICATE_NORMAL
);
556 fs_reg start
= shader_start_time
;
558 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
559 BRW_REGISTER_TYPE_UD
),
561 const fs_builder cbld
= ibld
.group(1, 0);
562 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
564 /* If there were no instructions between the two timestamp gets, the diff
565 * is 2 cycles. Remove that overhead, so I can forget about that when
566 * trying to determine the time taken for single instructions.
568 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
569 SHADER_TIME_ADD(cbld
, 0, diff
);
570 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
571 ibld
.emit(BRW_OPCODE_ELSE
);
572 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
573 ibld
.emit(BRW_OPCODE_ENDIF
);
577 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
578 int shader_time_subindex
,
581 int index
= shader_time_index
* 3 + shader_time_subindex
;
582 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
585 if (dispatch_width
== 8)
586 payload
= vgrf(glsl_type::uvec2_type
);
588 payload
= vgrf(glsl_type::uint_type
);
590 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
594 fs_visitor::vfail(const char *format
, va_list va
)
603 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
604 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
606 this->fail_msg
= msg
;
609 fprintf(stderr
, "%s", msg
);
614 fs_visitor::fail(const char *format
, ...)
618 va_start(va
, format
);
624 * Mark this program as impossible to compile with dispatch width greater
627 * During the SIMD8 compile (which happens first), we can detect and flag
628 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
629 * SIMD16+ compile altogether.
631 * During a compile of dispatch width greater than n (if one happens anyway),
632 * this just calls fail().
635 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
637 if (dispatch_width
> n
) {
640 max_dispatch_width
= n
;
641 compiler
->shader_perf_log(log_data
,
642 "Shader dispatch width limited to SIMD%d: %s",
648 * Returns true if the instruction has a flag that means it won't
649 * update an entire destination register.
651 * For example, dead code elimination and live variable analysis want to know
652 * when a write to a variable screens off any preceding values that were in
656 fs_inst::is_partial_write() const
658 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
659 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
660 !this->dst
.is_contiguous() ||
661 this->dst
.offset
% REG_SIZE
!= 0);
665 fs_inst::components_read(unsigned i
) const
667 /* Return zero if the source is not present. */
668 if (src
[i
].file
== BAD_FILE
)
672 case FS_OPCODE_LINTERP
:
678 case FS_OPCODE_PIXEL_X
:
679 case FS_OPCODE_PIXEL_Y
:
683 case FS_OPCODE_FB_WRITE_LOGICAL
:
684 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
685 /* First/second FB write color. */
687 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
691 case SHADER_OPCODE_TEX_LOGICAL
:
692 case SHADER_OPCODE_TXD_LOGICAL
:
693 case SHADER_OPCODE_TXF_LOGICAL
:
694 case SHADER_OPCODE_TXL_LOGICAL
:
695 case SHADER_OPCODE_TXS_LOGICAL
:
696 case FS_OPCODE_TXB_LOGICAL
:
697 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
698 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
699 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
700 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
701 case SHADER_OPCODE_LOD_LOGICAL
:
702 case SHADER_OPCODE_TG4_LOGICAL
:
703 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
704 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
705 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
706 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
707 /* Texture coordinates. */
708 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
709 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
710 /* Texture derivatives. */
711 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
712 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
713 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
714 /* Texture offset. */
715 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
718 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
723 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
724 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
725 assert(src
[3].file
== IMM
);
726 /* Surface coordinates. */
729 /* Surface operation source (ignored for reads). */
735 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
736 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
737 assert(src
[3].file
== IMM
&&
739 /* Surface coordinates. */
742 /* Surface operation source. */
748 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
749 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
750 assert(src
[3].file
== IMM
&&
752 const unsigned op
= src
[4].ud
;
753 /* Surface coordinates. */
756 /* Surface operation source. */
757 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
759 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
760 op
== BRW_AOP_PREDEC
))
772 fs_inst::size_read(int arg
) const
775 case FS_OPCODE_FB_WRITE
:
776 case FS_OPCODE_FB_READ
:
777 case SHADER_OPCODE_URB_WRITE_SIMD8
:
778 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
779 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
780 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
781 case SHADER_OPCODE_URB_READ_SIMD8
:
782 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
783 case SHADER_OPCODE_UNTYPED_ATOMIC
:
784 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
785 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
786 case SHADER_OPCODE_TYPED_ATOMIC
:
787 case SHADER_OPCODE_TYPED_SURFACE_READ
:
788 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
789 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
791 return mlen
* REG_SIZE
;
794 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
795 /* The payload is actually stored in src1 */
797 return mlen
* REG_SIZE
;
800 case FS_OPCODE_LINTERP
:
805 case SHADER_OPCODE_LOAD_PAYLOAD
:
806 if (arg
< this->header_size
)
810 case CS_OPCODE_CS_TERMINATE
:
811 case SHADER_OPCODE_BARRIER
:
814 case SHADER_OPCODE_MOV_INDIRECT
:
816 assert(src
[2].file
== IMM
);
822 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
823 return mlen
* REG_SIZE
;
827 switch (src
[arg
].file
) {
830 return components_read(arg
) * type_sz(src
[arg
].type
);
836 return components_read(arg
) * src
[arg
].component_size(exec_size
);
838 unreachable("MRF registers are not allowed as sources");
844 /* Return the subset of flag registers that an instruction could
845 * potentially read or write based on the execution controls and flag
846 * subregister number of the instruction.
849 flag_mask(const fs_inst
*inst
)
851 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
852 const unsigned end
= start
+ inst
->exec_size
;
853 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
859 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
863 flag_mask(const fs_reg
&r
, unsigned sz
)
866 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
867 const unsigned end
= start
+ sz
;
868 return bit_mask(end
) & ~bit_mask(start
);
876 fs_inst::flags_read(const gen_device_info
*devinfo
) const
878 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
879 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
880 /* The vertical predication modes combine corresponding bits from
881 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
883 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
884 return flag_mask(this) << shift
| flag_mask(this);
885 } else if (predicate
) {
886 return flag_mask(this);
889 for (int i
= 0; i
< sources
; i
++) {
890 mask
|= flag_mask(src
[i
], size_read(i
));
897 fs_inst::flags_written() const
899 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
900 opcode
!= BRW_OPCODE_IF
&&
901 opcode
!= BRW_OPCODE_WHILE
)) ||
902 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
903 return flag_mask(this);
905 return flag_mask(dst
, size_written
);
910 * Returns how many MRFs an FS opcode will write over.
912 * Note that this is not the 0 or 1 implied writes in an actual gen
913 * instruction -- the FS opcodes often generate MOVs in addition.
916 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
921 if (inst
->base_mrf
== -1)
924 switch (inst
->opcode
) {
925 case SHADER_OPCODE_RCP
:
926 case SHADER_OPCODE_RSQ
:
927 case SHADER_OPCODE_SQRT
:
928 case SHADER_OPCODE_EXP2
:
929 case SHADER_OPCODE_LOG2
:
930 case SHADER_OPCODE_SIN
:
931 case SHADER_OPCODE_COS
:
932 return 1 * dispatch_width
/ 8;
933 case SHADER_OPCODE_POW
:
934 case SHADER_OPCODE_INT_QUOTIENT
:
935 case SHADER_OPCODE_INT_REMAINDER
:
936 return 2 * dispatch_width
/ 8;
937 case SHADER_OPCODE_TEX
:
939 case SHADER_OPCODE_TXD
:
940 case SHADER_OPCODE_TXF
:
941 case SHADER_OPCODE_TXF_CMS
:
942 case SHADER_OPCODE_TXF_MCS
:
943 case SHADER_OPCODE_TG4
:
944 case SHADER_OPCODE_TG4_OFFSET
:
945 case SHADER_OPCODE_TXL
:
946 case SHADER_OPCODE_TXS
:
947 case SHADER_OPCODE_LOD
:
948 case SHADER_OPCODE_SAMPLEINFO
:
950 case FS_OPCODE_FB_WRITE
:
952 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
953 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
955 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
957 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
960 unreachable("not reached");
965 fs_visitor::vgrf(const glsl_type
*const type
)
967 int reg_width
= dispatch_width
/ 8;
968 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
969 brw_type_for_base_type(type
));
972 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
977 this->type
= BRW_REGISTER_TYPE_F
;
978 this->stride
= (file
== UNIFORM
? 0 : 1);
981 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
987 this->stride
= (file
== UNIFORM
? 0 : 1);
990 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
991 * This brings in those uniform definitions
994 fs_visitor::import_uniforms(fs_visitor
*v
)
996 this->push_constant_loc
= v
->push_constant_loc
;
997 this->pull_constant_loc
= v
->pull_constant_loc
;
998 this->uniforms
= v
->uniforms
;
999 this->thread_local_id
= v
->thread_local_id
;
1003 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1005 assert(stage
== MESA_SHADER_FRAGMENT
);
1007 /* gl_FragCoord.x */
1008 bld
.MOV(wpos
, this->pixel_x
);
1009 wpos
= offset(wpos
, bld
, 1);
1011 /* gl_FragCoord.y */
1012 bld
.MOV(wpos
, this->pixel_y
);
1013 wpos
= offset(wpos
, bld
, 1);
1015 /* gl_FragCoord.z */
1016 if (devinfo
->gen
>= 6) {
1017 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1019 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1020 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1021 interp_reg(VARYING_SLOT_POS
, 2));
1023 wpos
= offset(wpos
, bld
, 1);
1025 /* gl_FragCoord.w: Already set up in emit_interpolation */
1026 bld
.MOV(wpos
, this->wpos_w
);
1029 enum brw_barycentric_mode
1030 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1032 /* Barycentric modes don't make sense for flat inputs. */
1033 assert(mode
!= INTERP_MODE_FLAT
);
1037 case nir_intrinsic_load_barycentric_pixel
:
1038 case nir_intrinsic_load_barycentric_at_offset
:
1039 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1041 case nir_intrinsic_load_barycentric_centroid
:
1042 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1044 case nir_intrinsic_load_barycentric_sample
:
1045 case nir_intrinsic_load_barycentric_at_sample
:
1046 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1049 unreachable("invalid intrinsic");
1052 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1055 return (enum brw_barycentric_mode
) bary
;
1059 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1061 static enum brw_barycentric_mode
1062 centroid_to_pixel(enum brw_barycentric_mode bary
)
1064 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1065 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1066 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1070 fs_visitor::emit_frontfacing_interpolation()
1072 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1074 if (devinfo
->gen
>= 6) {
1075 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1076 * a boolean result from this (~0/true or 0/false).
1078 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1079 * this task in only one instruction:
1080 * - a negation source modifier will flip the bit; and
1081 * - a W -> D type conversion will sign extend the bit into the high
1082 * word of the destination.
1084 * An ASR 15 fills the low word of the destination.
1086 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1089 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1091 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1092 * a boolean result from this (1/true or 0/false).
1094 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1095 * the negation source modifier to flip it. Unfortunately the SHR
1096 * instruction only operates on UD (or D with an abs source modifier)
1097 * sources without negation.
1099 * Instead, use ASR (which will give ~0/true or 0/false).
1101 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1104 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1111 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1113 assert(stage
== MESA_SHADER_FRAGMENT
);
1114 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1115 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1117 if (wm_prog_data
->persample_dispatch
) {
1118 /* Convert int_sample_pos to floating point */
1119 bld
.MOV(dst
, int_sample_pos
);
1120 /* Scale to the range [0, 1] */
1121 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1124 /* From ARB_sample_shading specification:
1125 * "When rendering to a non-multisample buffer, or if multisample
1126 * rasterization is disabled, gl_SamplePosition will always be
1129 bld
.MOV(dst
, brw_imm_f(0.5f
));
1134 fs_visitor::emit_samplepos_setup()
1136 assert(devinfo
->gen
>= 6);
1138 const fs_builder abld
= bld
.annotate("compute sample position");
1139 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1141 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1142 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1144 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1145 * mode will be enabled.
1147 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1148 * R31.1:0 Position Offset X/Y for Slot[3:0]
1149 * R31.3:2 Position Offset X/Y for Slot[7:4]
1152 * The X, Y sample positions come in as bytes in thread payload. So, read
1153 * the positions using vstride=16, width=8, hstride=2.
1155 struct brw_reg sample_pos_reg
=
1156 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1157 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1159 if (dispatch_width
== 8) {
1160 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1162 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1163 abld
.half(1).MOV(half(int_sample_x
, 1),
1164 fs_reg(suboffset(sample_pos_reg
, 16)));
1166 /* Compute gl_SamplePosition.x */
1167 compute_sample_position(pos
, int_sample_x
);
1168 pos
= offset(pos
, abld
, 1);
1169 if (dispatch_width
== 8) {
1170 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1172 abld
.half(0).MOV(half(int_sample_y
, 0),
1173 fs_reg(suboffset(sample_pos_reg
, 1)));
1174 abld
.half(1).MOV(half(int_sample_y
, 1),
1175 fs_reg(suboffset(sample_pos_reg
, 17)));
1177 /* Compute gl_SamplePosition.y */
1178 compute_sample_position(pos
, int_sample_y
);
1183 fs_visitor::emit_sampleid_setup()
1185 assert(stage
== MESA_SHADER_FRAGMENT
);
1186 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1187 assert(devinfo
->gen
>= 6);
1189 const fs_builder abld
= bld
.annotate("compute sample id");
1190 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1192 if (!key
->multisample_fbo
) {
1193 /* As per GL_ARB_sample_shading specification:
1194 * "When rendering to a non-multisample buffer, or if multisample
1195 * rasterization is disabled, gl_SampleID will always be zero."
1197 abld
.MOV(*reg
, brw_imm_d(0));
1198 } else if (devinfo
->gen
>= 8) {
1199 /* Sample ID comes in as 4-bit numbers in g1.0:
1201 * 15:12 Slot 3 SampleID (only used in SIMD16)
1202 * 11:8 Slot 2 SampleID (only used in SIMD16)
1203 * 7:4 Slot 1 SampleID
1204 * 3:0 Slot 0 SampleID
1206 * Each slot corresponds to four channels, so we want to replicate each
1207 * half-byte value to 4 channels in a row:
1209 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1210 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1212 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1213 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1215 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1216 * channels to read the first byte (7:0), and the second group of 8
1217 * channels to read the second byte (15:8). Then, we shift right by
1218 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1219 * values into place. Finally, we AND with 0xf to keep the low nibble.
1221 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1222 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1224 * TODO: These payload bits exist on Gen7 too, but they appear to always
1225 * be zero, so this code fails to work. We should find out why.
1227 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1229 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1230 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1231 brw_imm_v(0x44440000));
1232 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1234 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1235 BRW_REGISTER_TYPE_D
), 0);
1236 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1238 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1239 * 8x multisampling, subspan 0 will represent sample N (where N
1240 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1241 * 7. We can find the value of N by looking at R0.0 bits 7:6
1242 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1243 * (since samples are always delivered in pairs). That is, we
1244 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1245 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1246 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1247 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1248 * populating a temporary variable with the sequence (0, 1, 2, 3),
1249 * and then reading from it using vstride=1, width=4, hstride=0.
1250 * These computations hold good for 4x multisampling as well.
1252 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1253 * the first four slots are sample 0 of subspan 0; the next four
1254 * are sample 1 of subspan 0; the third group is sample 0 of
1255 * subspan 1, and finally sample 1 of subspan 1.
1258 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1259 * accomodate 16x MSAA.
1261 abld
.exec_all().group(1, 0)
1262 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1264 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1266 /* This works for both SIMD8 and SIMD16 */
1267 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1269 /* This special instruction takes care of setting vstride=1,
1270 * width=4, hstride=0 of t2 during an ADD instruction.
1272 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1279 fs_visitor::emit_samplemaskin_setup()
1281 assert(stage
== MESA_SHADER_FRAGMENT
);
1282 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1283 assert(devinfo
->gen
>= 6);
1285 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1287 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1288 BRW_REGISTER_TYPE_D
));
1290 if (wm_prog_data
->persample_dispatch
) {
1291 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1292 * and a mask representing which sample is being processed by the
1293 * current shader invocation.
1295 * From the OES_sample_variables specification:
1296 * "When per-sample shading is active due to the use of a fragment input
1297 * qualified by "sample" or due to the use of the gl_SampleID or
1298 * gl_SamplePosition variables, only the bit for the current sample is
1299 * set in gl_SampleMaskIn."
1301 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1303 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1304 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1306 fs_reg one
= vgrf(glsl_type::int_type
);
1307 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1308 abld
.MOV(one
, brw_imm_d(1));
1309 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1310 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1312 /* In per-pixel mode, the coverage mask is sufficient. */
1313 *reg
= coverage_mask
;
1319 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1321 if (!src
.abs
&& !src
.negate
)
1324 fs_reg temp
= bld
.vgrf(src
.type
);
1331 fs_visitor::emit_discard_jump()
1333 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1335 /* For performance, after a discard, jump to the end of the
1336 * shader if all relevant channels have been discarded.
1338 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1339 discard_jump
->flag_subreg
= 1;
1341 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1342 discard_jump
->predicate_inverse
= true;
1346 fs_visitor::emit_gs_thread_end()
1348 assert(stage
== MESA_SHADER_GEOMETRY
);
1350 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1352 if (gs_compile
->control_data_header_size_bits
> 0) {
1353 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1356 const fs_builder abld
= bld
.annotate("thread end");
1359 if (gs_prog_data
->static_vertex_count
!= -1) {
1360 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1361 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1362 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1363 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1364 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1367 /* Delete now dead instructions. */
1368 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1374 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1378 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1379 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1380 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1383 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1384 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1385 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1386 sources
[1] = this->final_gs_vertex_count
;
1387 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1388 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1396 fs_visitor::assign_curb_setup()
1398 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1400 unsigned ubo_push_length
= 0;
1401 unsigned ubo_push_start
[4];
1402 for (int i
= 0; i
< 4; i
++) {
1403 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1404 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1407 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1409 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1410 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1411 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1412 if (inst
->src
[i
].file
== UNIFORM
) {
1413 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1415 if (inst
->src
[i
].nr
>= UBO_START
) {
1416 /* constant_nr is in 32-bit units, the rest are in bytes */
1417 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1418 inst
->src
[i
].offset
/ 4;
1419 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1420 constant_nr
= push_constant_loc
[uniform_nr
];
1422 /* Section 5.11 of the OpenGL 4.1 spec says:
1423 * "Out-of-bounds reads return undefined values, which include
1424 * values from other variables of the active program or zero."
1425 * Just return the first push constant.
1430 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1433 brw_reg
.abs
= inst
->src
[i
].abs
;
1434 brw_reg
.negate
= inst
->src
[i
].negate
;
1436 assert(inst
->src
[i
].stride
== 0);
1437 inst
->src
[i
] = byte_offset(
1438 retype(brw_reg
, inst
->src
[i
].type
),
1439 inst
->src
[i
].offset
% 4);
1444 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1445 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1449 fs_visitor::calculate_urb_setup()
1451 assert(stage
== MESA_SHADER_FRAGMENT
);
1452 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1453 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1455 memset(prog_data
->urb_setup
, -1,
1456 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1459 /* Figure out where each of the incoming setup attributes lands. */
1460 if (devinfo
->gen
>= 6) {
1461 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1462 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1463 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1464 * first 16 varying inputs, so we can put them wherever we want.
1465 * Just put them in order.
1467 * This is useful because it means that (a) inputs not used by the
1468 * fragment shader won't take up valuable register space, and (b) we
1469 * won't have to recompile the fragment shader if it gets paired with
1470 * a different vertex (or geometry) shader.
1472 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1473 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1474 BITFIELD64_BIT(i
)) {
1475 prog_data
->urb_setup
[i
] = urb_next
++;
1479 /* We have enough input varyings that the SF/SBE pipeline stage can't
1480 * arbitrarily rearrange them to suit our whim; we have to put them
1481 * in an order that matches the output of the previous pipeline stage
1482 * (geometry or vertex shader).
1484 struct brw_vue_map prev_stage_vue_map
;
1485 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1486 key
->input_slots_valid
,
1487 nir
->info
.separate_shader
);
1490 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1491 &prev_stage_vue_map
);
1493 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1494 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1496 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1497 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1498 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1499 BITFIELD64_BIT(varying
))) {
1500 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1503 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1506 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1507 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1508 /* Point size is packed into the header, not as a general attribute */
1509 if (i
== VARYING_SLOT_PSIZ
)
1512 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1513 /* The back color slot is skipped when the front color is
1514 * also written to. In addition, some slots can be
1515 * written in the vertex shader and not read in the
1516 * fragment shader. So the register number must always be
1517 * incremented, mapped or not.
1519 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1520 prog_data
->urb_setup
[i
] = urb_next
;
1526 * It's a FS only attribute, and we did interpolation for this attribute
1527 * in SF thread. So, count it here, too.
1529 * See compile_sf_prog() for more info.
1531 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1532 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1535 prog_data
->num_varying_inputs
= urb_next
;
1539 fs_visitor::assign_urb_setup()
1541 assert(stage
== MESA_SHADER_FRAGMENT
);
1542 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1544 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1546 /* Offset all the urb_setup[] index by the actual position of the
1547 * setup regs, now that the location of the constants has been chosen.
1549 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1550 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1551 assert(inst
->src
[1].file
== FIXED_GRF
);
1552 inst
->src
[1].nr
+= urb_start
;
1555 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1556 assert(inst
->src
[0].file
== FIXED_GRF
);
1557 inst
->src
[0].nr
+= urb_start
;
1561 /* Each attribute is 4 setup channels, each of which is half a reg. */
1562 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1566 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1568 for (int i
= 0; i
< inst
->sources
; i
++) {
1569 if (inst
->src
[i
].file
== ATTR
) {
1570 int grf
= payload
.num_regs
+
1571 prog_data
->curb_read_length
+
1573 inst
->src
[i
].offset
/ REG_SIZE
;
1575 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1577 * VertStride must be used to cross GRF register boundaries. This
1578 * rule implies that elements within a 'Width' cannot cross GRF
1581 * So, for registers that are large enough, we have to split the exec
1582 * size in two and trust the compression state to sort it out.
1584 unsigned total_size
= inst
->exec_size
*
1585 inst
->src
[i
].stride
*
1586 type_sz(inst
->src
[i
].type
);
1588 assert(total_size
<= 2 * REG_SIZE
);
1589 const unsigned exec_size
=
1590 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1592 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1593 struct brw_reg reg
=
1594 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1595 inst
->src
[i
].offset
% REG_SIZE
),
1596 exec_size
* inst
->src
[i
].stride
,
1597 width
, inst
->src
[i
].stride
);
1598 reg
.abs
= inst
->src
[i
].abs
;
1599 reg
.negate
= inst
->src
[i
].negate
;
1607 fs_visitor::assign_vs_urb_setup()
1609 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1611 assert(stage
== MESA_SHADER_VERTEX
);
1613 /* Each attribute is 4 regs. */
1614 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1616 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1618 /* Rewrite all ATTR file references to the hw grf that they land in. */
1619 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1620 convert_attr_sources_to_hw_regs(inst
);
1625 fs_visitor::assign_tcs_single_patch_urb_setup()
1627 assert(stage
== MESA_SHADER_TESS_CTRL
);
1629 /* Rewrite all ATTR file references to HW_REGs. */
1630 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1631 convert_attr_sources_to_hw_regs(inst
);
1636 fs_visitor::assign_tes_urb_setup()
1638 assert(stage
== MESA_SHADER_TESS_EVAL
);
1640 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1642 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1644 /* Rewrite all ATTR file references to HW_REGs. */
1645 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1646 convert_attr_sources_to_hw_regs(inst
);
1651 fs_visitor::assign_gs_urb_setup()
1653 assert(stage
== MESA_SHADER_GEOMETRY
);
1655 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1657 first_non_payload_grf
+=
1658 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1660 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1661 /* Rewrite all ATTR file references to GRFs. */
1662 convert_attr_sources_to_hw_regs(inst
);
1668 * Split large virtual GRFs into separate components if we can.
1670 * This is mostly duplicated with what brw_fs_vector_splitting does,
1671 * but that's really conservative because it's afraid of doing
1672 * splitting that doesn't result in real progress after the rest of
1673 * the optimization phases, which would cause infinite looping in
1674 * optimization. We can do it once here, safely. This also has the
1675 * opportunity to split interpolated values, or maybe even uniforms,
1676 * which we don't have at the IR level.
1678 * We want to split, because virtual GRFs are what we register
1679 * allocate and spill (due to contiguousness requirements for some
1680 * instructions), and they're what we naturally generate in the
1681 * codegen process, but most virtual GRFs don't actually need to be
1682 * contiguous sets of GRFs. If we split, we'll end up with reduced
1683 * live intervals and better dead code elimination and coalescing.
1686 fs_visitor::split_virtual_grfs()
1688 /* Compact the register file so we eliminate dead vgrfs. This
1689 * only defines split points for live registers, so if we have
1690 * too large dead registers they will hit assertions later.
1692 compact_virtual_grfs();
1694 int num_vars
= this->alloc
.count
;
1696 /* Count the total number of registers */
1698 int vgrf_to_reg
[num_vars
];
1699 for (int i
= 0; i
< num_vars
; i
++) {
1700 vgrf_to_reg
[i
] = reg_count
;
1701 reg_count
+= alloc
.sizes
[i
];
1704 /* An array of "split points". For each register slot, this indicates
1705 * if this slot can be separated from the previous slot. Every time an
1706 * instruction uses multiple elements of a register (as a source or
1707 * destination), we mark the used slots as inseparable. Then we go
1708 * through and split the registers into the smallest pieces we can.
1710 bool split_points
[reg_count
];
1711 memset(split_points
, 0, sizeof(split_points
));
1713 /* Mark all used registers as fully splittable */
1714 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1715 if (inst
->dst
.file
== VGRF
) {
1716 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1717 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1718 split_points
[reg
+ j
] = true;
1721 for (int i
= 0; i
< inst
->sources
; i
++) {
1722 if (inst
->src
[i
].file
== VGRF
) {
1723 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1724 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1725 split_points
[reg
+ j
] = true;
1730 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1731 if (inst
->dst
.file
== VGRF
) {
1732 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1733 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1734 split_points
[reg
+ j
] = false;
1736 for (int i
= 0; i
< inst
->sources
; i
++) {
1737 if (inst
->src
[i
].file
== VGRF
) {
1738 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1739 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1740 split_points
[reg
+ j
] = false;
1745 int new_virtual_grf
[reg_count
];
1746 int new_reg_offset
[reg_count
];
1749 for (int i
= 0; i
< num_vars
; i
++) {
1750 /* The first one should always be 0 as a quick sanity check. */
1751 assert(split_points
[reg
] == false);
1754 new_reg_offset
[reg
] = 0;
1759 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1760 /* If this is a split point, reset the offset to 0 and allocate a
1761 * new virtual GRF for the previous offset many registers
1763 if (split_points
[reg
]) {
1764 assert(offset
<= MAX_VGRF_SIZE
);
1765 int grf
= alloc
.allocate(offset
);
1766 for (int k
= reg
- offset
; k
< reg
; k
++)
1767 new_virtual_grf
[k
] = grf
;
1770 new_reg_offset
[reg
] = offset
;
1775 /* The last one gets the original register number */
1776 assert(offset
<= MAX_VGRF_SIZE
);
1777 alloc
.sizes
[i
] = offset
;
1778 for (int k
= reg
- offset
; k
< reg
; k
++)
1779 new_virtual_grf
[k
] = i
;
1781 assert(reg
== reg_count
);
1783 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1784 if (inst
->dst
.file
== VGRF
) {
1785 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1786 inst
->dst
.nr
= new_virtual_grf
[reg
];
1787 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1788 inst
->dst
.offset
% REG_SIZE
;
1789 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1791 for (int i
= 0; i
< inst
->sources
; i
++) {
1792 if (inst
->src
[i
].file
== VGRF
) {
1793 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1794 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1795 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1796 inst
->src
[i
].offset
% REG_SIZE
;
1797 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1801 invalidate_live_intervals();
1805 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1807 * During code generation, we create tons of temporary variables, many of
1808 * which get immediately killed and are never used again. Yet, in later
1809 * optimization and analysis passes, such as compute_live_intervals, we need
1810 * to loop over all the virtual GRFs. Compacting them can save a lot of
1814 fs_visitor::compact_virtual_grfs()
1816 bool progress
= false;
1817 int remap_table
[this->alloc
.count
];
1818 memset(remap_table
, -1, sizeof(remap_table
));
1820 /* Mark which virtual GRFs are used. */
1821 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1822 if (inst
->dst
.file
== VGRF
)
1823 remap_table
[inst
->dst
.nr
] = 0;
1825 for (int i
= 0; i
< inst
->sources
; i
++) {
1826 if (inst
->src
[i
].file
== VGRF
)
1827 remap_table
[inst
->src
[i
].nr
] = 0;
1831 /* Compact the GRF arrays. */
1833 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1834 if (remap_table
[i
] == -1) {
1835 /* We just found an unused register. This means that we are
1836 * actually going to compact something.
1840 remap_table
[i
] = new_index
;
1841 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1842 invalidate_live_intervals();
1847 this->alloc
.count
= new_index
;
1849 /* Patch all the instructions to use the newly renumbered registers */
1850 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1851 if (inst
->dst
.file
== VGRF
)
1852 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1854 for (int i
= 0; i
< inst
->sources
; i
++) {
1855 if (inst
->src
[i
].file
== VGRF
)
1856 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1860 /* Patch all the references to delta_xy, since they're used in register
1861 * allocation. If they're unused, switch them to BAD_FILE so we don't
1862 * think some random VGRF is delta_xy.
1864 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1865 if (delta_xy
[i
].file
== VGRF
) {
1866 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1867 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1869 delta_xy
[i
].file
= BAD_FILE
;
1878 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
,
1879 unsigned *max_chunk_bitsize
,
1880 bool contiguous
, unsigned bitsize
,
1881 const unsigned target_bitsize
,
1882 int *push_constant_loc
, int *pull_constant_loc
,
1883 unsigned *num_push_constants
,
1884 unsigned *num_pull_constants
,
1885 const unsigned max_push_components
,
1886 const unsigned max_chunk_size
,
1887 bool allow_pull_constants
,
1888 struct brw_stage_prog_data
*stage_prog_data
)
1890 /* This is the first live uniform in the chunk */
1891 if (*chunk_start
< 0)
1892 *chunk_start
= uniform
;
1894 /* Keep track of the maximum bit size access in contiguous uniforms */
1895 *max_chunk_bitsize
= MAX2(*max_chunk_bitsize
, bitsize
);
1897 /* If this element does not need to be contiguous with the next, we
1898 * split at this point and everything between chunk_start and u forms a
1902 /* If bitsize doesn't match the target one, skip it */
1903 if (*max_chunk_bitsize
!= target_bitsize
) {
1904 /* FIXME: right now we only support 32 and 64-bit accesses */
1905 assert(*max_chunk_bitsize
== 4 || *max_chunk_bitsize
== 8);
1906 *max_chunk_bitsize
= 0;
1911 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1913 /* Decide whether we should push or pull this parameter. In the
1914 * Vulkan driver, push constants are explicitly exposed via the API
1915 * so we push everything. In GL, we only push small arrays.
1917 if (!allow_pull_constants
||
1918 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1919 chunk_size
<= max_chunk_size
)) {
1920 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1921 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1922 push_constant_loc
[j
] = (*num_push_constants
)++;
1924 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1925 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1928 *max_chunk_bitsize
= 0;
1934 get_thread_local_id_param_index(const brw_stage_prog_data
*prog_data
)
1936 if (prog_data
->nr_params
== 0)
1939 /* The local thread id is always the last parameter in the list */
1940 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
1941 if (last_param
== BRW_PARAM_BUILTIN_THREAD_LOCAL_ID
)
1942 return prog_data
->nr_params
- 1;
1948 * Assign UNIFORM file registers to either push constants or pull constants.
1950 * We allow a fragment shader to have more than the specified minimum
1951 * maximum number of fragment shader uniform components (64). If
1952 * there are too many of these, they'd fill up all of register space.
1953 * So, this will push some of them out to the pull constant buffer and
1954 * update the program to load them.
1957 fs_visitor::assign_constant_locations()
1959 /* Only the first compile gets to decide on locations. */
1960 if (push_constant_loc
) {
1961 assert(pull_constant_loc
);
1965 bool is_live
[uniforms
];
1966 memset(is_live
, 0, sizeof(is_live
));
1967 unsigned bitsize_access
[uniforms
];
1968 memset(bitsize_access
, 0, sizeof(bitsize_access
));
1970 /* For each uniform slot, a value of true indicates that the given slot and
1971 * the next slot must remain contiguous. This is used to keep us from
1972 * splitting arrays and 64-bit values apart.
1974 bool contiguous
[uniforms
];
1975 memset(contiguous
, 0, sizeof(contiguous
));
1977 /* First, we walk through the instructions and do two things:
1979 * 1) Figure out which uniforms are live.
1981 * 2) Mark any indirectly used ranges of registers as contiguous.
1983 * Note that we don't move constant-indexed accesses to arrays. No
1984 * testing has been done of the performance impact of this choice.
1986 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1987 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1988 if (inst
->src
[i
].file
!= UNIFORM
)
1991 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1993 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1994 assert(inst
->src
[2].ud
% 4 == 0);
1995 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1996 assert(last
< uniforms
);
1998 for (unsigned j
= constant_nr
; j
< last
; j
++) {
2000 contiguous
[j
] = true;
2001 bitsize_access
[j
] = MAX2(bitsize_access
[j
], type_sz(inst
->src
[i
].type
));
2003 is_live
[last
] = true;
2004 bitsize_access
[last
] = MAX2(bitsize_access
[last
], type_sz(inst
->src
[i
].type
));
2006 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2007 int regs_read
= inst
->components_read(i
) *
2008 type_sz(inst
->src
[i
].type
) / 4;
2009 assert(regs_read
<= 2);
2011 contiguous
[constant_nr
] = true;
2012 for (int j
= 0; j
< regs_read
; j
++) {
2013 is_live
[constant_nr
+ j
] = true;
2014 bitsize_access
[constant_nr
+ j
] =
2015 MAX2(bitsize_access
[constant_nr
+ j
], type_sz(inst
->src
[i
].type
));
2022 int thread_local_id_index
= get_thread_local_id_param_index(stage_prog_data
);
2024 /* Only allow 16 registers (128 uniform components) as push constants.
2026 * Just demote the end of the list. We could probably do better
2027 * here, demoting things that are rarely used in the program first.
2029 * If changing this value, note the limitation about total_regs in
2032 unsigned int max_push_components
= 16 * 8;
2033 if (thread_local_id_index
>= 0)
2034 max_push_components
--; /* Save a slot for the thread ID */
2036 /* We push small arrays, but no bigger than 16 floats. This is big enough
2037 * for a vec4 but hopefully not large enough to push out other stuff. We
2038 * should probably use a better heuristic at some point.
2040 const unsigned int max_chunk_size
= 16;
2042 unsigned int num_push_constants
= 0;
2043 unsigned int num_pull_constants
= 0;
2045 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2046 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2048 /* Default to -1 meaning no location */
2049 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2050 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2052 int chunk_start
= -1;
2053 unsigned max_chunk_bitsize
= 0;
2055 /* First push 64-bit uniforms to ensure they are properly aligned */
2056 const unsigned uniform_64_bit_size
= type_sz(BRW_REGISTER_TYPE_DF
);
2057 for (unsigned u
= 0; u
< uniforms
; u
++) {
2061 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2062 contiguous
[u
], bitsize_access
[u
],
2063 uniform_64_bit_size
,
2064 push_constant_loc
, pull_constant_loc
,
2065 &num_push_constants
, &num_pull_constants
,
2066 max_push_components
, max_chunk_size
,
2067 compiler
->supports_pull_constants
,
2072 /* Then push the rest of uniforms */
2073 const unsigned uniform_32_bit_size
= type_sz(BRW_REGISTER_TYPE_F
);
2074 for (unsigned u
= 0; u
< uniforms
; u
++) {
2078 /* Skip thread_local_id_index to put it in the last push register. */
2079 if (thread_local_id_index
== (int)u
)
2082 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2083 contiguous
[u
], bitsize_access
[u
],
2084 uniform_32_bit_size
,
2085 push_constant_loc
, pull_constant_loc
,
2086 &num_push_constants
, &num_pull_constants
,
2087 max_push_components
, max_chunk_size
,
2088 compiler
->supports_pull_constants
,
2092 /* Add the CS local thread ID uniform at the end of the push constants */
2093 if (thread_local_id_index
>= 0)
2094 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2096 /* As the uniforms are going to be reordered, stash the old array and
2097 * create two new arrays for push/pull params.
2099 uint32_t *param
= stage_prog_data
->param
;
2100 stage_prog_data
->nr_params
= num_push_constants
;
2101 if (num_push_constants
) {
2102 stage_prog_data
->param
= ralloc_array(mem_ctx
, uint32_t,
2103 num_push_constants
);
2105 stage_prog_data
->param
= NULL
;
2107 assert(stage_prog_data
->nr_pull_params
== 0);
2108 assert(stage_prog_data
->pull_param
== NULL
);
2109 if (num_pull_constants
> 0) {
2110 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2111 stage_prog_data
->pull_param
= ralloc_array(mem_ctx
, uint32_t,
2112 num_pull_constants
);
2115 /* Now that we know how many regular uniforms we'll push, reduce the
2116 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2118 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2119 for (int i
= 0; i
< 4; i
++) {
2120 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2122 if (push_length
+ range
->length
> 64)
2123 range
->length
= 64 - push_length
;
2125 push_length
+= range
->length
;
2127 assert(push_length
<= 64);
2129 /* Up until now, the param[] array has been indexed by reg + offset
2130 * of UNIFORM registers. Move pull constants into pull_param[] and
2131 * condense param[] to only contain the uniforms we chose to push.
2133 * NOTE: Because we are condensing the params[] array, we know that
2134 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2135 * having to make a copy.
2137 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2138 uint32_t value
= param
[i
];
2139 if (pull_constant_loc
[i
] != -1) {
2140 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2141 } else if (push_constant_loc
[i
] != -1) {
2142 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2149 fs_visitor::get_pull_locs(const fs_reg
&src
,
2150 unsigned *out_surf_index
,
2151 unsigned *out_pull_index
)
2153 assert(src
.file
== UNIFORM
);
2155 if (src
.nr
>= UBO_START
) {
2156 const struct brw_ubo_range
*range
=
2157 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2159 /* If this access is in our (reduced) range, use the push data. */
2160 if (src
.offset
/ 32 < range
->length
)
2163 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2164 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2168 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2170 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2171 /* A regular uniform push constant */
2172 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2173 *out_pull_index
= pull_constant_loc
[location
];
2181 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2182 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2185 fs_visitor::lower_constant_loads()
2187 unsigned index
, pull_index
;
2189 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2190 /* Set up the annotation tracking for new generated instructions. */
2191 const fs_builder
ibld(this, block
, inst
);
2193 for (int i
= 0; i
< inst
->sources
; i
++) {
2194 if (inst
->src
[i
].file
!= UNIFORM
)
2197 /* We'll handle this case later */
2198 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2201 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2204 assert(inst
->src
[i
].stride
== 0);
2206 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2207 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2208 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2209 const unsigned base
= pull_index
* 4;
2211 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2212 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2214 /* Rewrite the instruction to use the temporary VGRF. */
2215 inst
->src
[i
].file
= VGRF
;
2216 inst
->src
[i
].nr
= dst
.nr
;
2217 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2218 inst
->src
[i
].offset
% 4;
2220 brw_mark_surface_used(prog_data
, index
);
2223 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2224 inst
->src
[0].file
== UNIFORM
) {
2226 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2229 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2233 inst
->remove(block
);
2235 brw_mark_surface_used(prog_data
, index
);
2238 invalidate_live_intervals();
2242 fs_visitor::opt_algebraic()
2244 bool progress
= false;
2246 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2247 switch (inst
->opcode
) {
2248 case BRW_OPCODE_MOV
:
2249 if (inst
->src
[0].file
!= IMM
)
2252 if (inst
->saturate
) {
2253 if (inst
->dst
.type
!= inst
->src
[0].type
)
2254 assert(!"unimplemented: saturate mixed types");
2256 if (brw_saturate_immediate(inst
->dst
.type
,
2257 &inst
->src
[0].as_brw_reg())) {
2258 inst
->saturate
= false;
2264 case BRW_OPCODE_MUL
:
2265 if (inst
->src
[1].file
!= IMM
)
2269 if (inst
->src
[1].is_one()) {
2270 inst
->opcode
= BRW_OPCODE_MOV
;
2271 inst
->src
[1] = reg_undef
;
2277 if (inst
->src
[1].is_negative_one()) {
2278 inst
->opcode
= BRW_OPCODE_MOV
;
2279 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2280 inst
->src
[1] = reg_undef
;
2286 if (inst
->src
[1].is_zero()) {
2287 inst
->opcode
= BRW_OPCODE_MOV
;
2288 inst
->src
[0] = inst
->src
[1];
2289 inst
->src
[1] = reg_undef
;
2294 if (inst
->src
[0].file
== IMM
) {
2295 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2296 inst
->opcode
= BRW_OPCODE_MOV
;
2297 inst
->src
[0].f
*= inst
->src
[1].f
;
2298 inst
->src
[1] = reg_undef
;
2303 case BRW_OPCODE_ADD
:
2304 if (inst
->src
[1].file
!= IMM
)
2308 if (inst
->src
[1].is_zero()) {
2309 inst
->opcode
= BRW_OPCODE_MOV
;
2310 inst
->src
[1] = reg_undef
;
2315 if (inst
->src
[0].file
== IMM
) {
2316 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2317 inst
->opcode
= BRW_OPCODE_MOV
;
2318 inst
->src
[0].f
+= inst
->src
[1].f
;
2319 inst
->src
[1] = reg_undef
;
2325 if (inst
->src
[0].equals(inst
->src
[1])) {
2326 inst
->opcode
= BRW_OPCODE_MOV
;
2327 inst
->src
[1] = reg_undef
;
2332 case BRW_OPCODE_LRP
:
2333 if (inst
->src
[1].equals(inst
->src
[2])) {
2334 inst
->opcode
= BRW_OPCODE_MOV
;
2335 inst
->src
[0] = inst
->src
[1];
2336 inst
->src
[1] = reg_undef
;
2337 inst
->src
[2] = reg_undef
;
2342 case BRW_OPCODE_CMP
:
2343 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2345 inst
->src
[0].negate
&&
2346 inst
->src
[1].is_zero()) {
2347 inst
->src
[0].abs
= false;
2348 inst
->src
[0].negate
= false;
2349 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2354 case BRW_OPCODE_SEL
:
2355 if (inst
->src
[0].equals(inst
->src
[1])) {
2356 inst
->opcode
= BRW_OPCODE_MOV
;
2357 inst
->src
[1] = reg_undef
;
2358 inst
->predicate
= BRW_PREDICATE_NONE
;
2359 inst
->predicate_inverse
= false;
2361 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2362 switch (inst
->conditional_mod
) {
2363 case BRW_CONDITIONAL_LE
:
2364 case BRW_CONDITIONAL_L
:
2365 switch (inst
->src
[1].type
) {
2366 case BRW_REGISTER_TYPE_F
:
2367 if (inst
->src
[1].f
>= 1.0f
) {
2368 inst
->opcode
= BRW_OPCODE_MOV
;
2369 inst
->src
[1] = reg_undef
;
2370 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2378 case BRW_CONDITIONAL_GE
:
2379 case BRW_CONDITIONAL_G
:
2380 switch (inst
->src
[1].type
) {
2381 case BRW_REGISTER_TYPE_F
:
2382 if (inst
->src
[1].f
<= 0.0f
) {
2383 inst
->opcode
= BRW_OPCODE_MOV
;
2384 inst
->src
[1] = reg_undef
;
2385 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2397 case BRW_OPCODE_MAD
:
2398 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2399 inst
->opcode
= BRW_OPCODE_MOV
;
2400 inst
->src
[1] = reg_undef
;
2401 inst
->src
[2] = reg_undef
;
2403 } else if (inst
->src
[0].is_zero()) {
2404 inst
->opcode
= BRW_OPCODE_MUL
;
2405 inst
->src
[0] = inst
->src
[2];
2406 inst
->src
[2] = reg_undef
;
2408 } else if (inst
->src
[1].is_one()) {
2409 inst
->opcode
= BRW_OPCODE_ADD
;
2410 inst
->src
[1] = inst
->src
[2];
2411 inst
->src
[2] = reg_undef
;
2413 } else if (inst
->src
[2].is_one()) {
2414 inst
->opcode
= BRW_OPCODE_ADD
;
2415 inst
->src
[2] = reg_undef
;
2417 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2418 inst
->opcode
= BRW_OPCODE_ADD
;
2419 inst
->src
[1].f
*= inst
->src
[2].f
;
2420 inst
->src
[2] = reg_undef
;
2424 case SHADER_OPCODE_BROADCAST
:
2425 if (is_uniform(inst
->src
[0])) {
2426 inst
->opcode
= BRW_OPCODE_MOV
;
2428 inst
->force_writemask_all
= true;
2430 } else if (inst
->src
[1].file
== IMM
) {
2431 inst
->opcode
= BRW_OPCODE_MOV
;
2432 /* It's possible that the selected component will be too large and
2433 * overflow the register. This can happen if someone does a
2434 * readInvocation() from GLSL or SPIR-V and provides an OOB
2435 * invocationIndex. If this happens and we some how manage
2436 * to constant fold it in and get here, then component() may cause
2437 * us to start reading outside of the VGRF which will lead to an
2438 * assert later. Instead, just let it wrap around if it goes over
2441 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2442 inst
->src
[0] = component(inst
->src
[0], comp
);
2444 inst
->force_writemask_all
= true;
2453 /* Swap if src[0] is immediate. */
2454 if (progress
&& inst
->is_commutative()) {
2455 if (inst
->src
[0].file
== IMM
) {
2456 fs_reg tmp
= inst
->src
[1];
2457 inst
->src
[1] = inst
->src
[0];
2466 * Optimize sample messages that have constant zero values for the trailing
2467 * texture coordinates. We can just reduce the message length for these
2468 * instructions instead of reserving a register for it. Trailing parameters
2469 * that aren't sent default to zero anyway. This will cause the dead code
2470 * eliminator to remove the MOV instruction that would otherwise be emitted to
2471 * set up the zero value.
2474 fs_visitor::opt_zero_samples()
2476 /* Gen4 infers the texturing opcode based on the message length so we can't
2479 if (devinfo
->gen
< 5)
2482 bool progress
= false;
2484 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2485 if (!inst
->is_tex())
2488 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2490 if (load_payload
->is_head_sentinel() ||
2491 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2494 /* We don't want to remove the message header or the first parameter.
2495 * Removing the first parameter is not allowed, see the Haswell PRM
2496 * volume 7, page 149:
2498 * "Parameter 0 is required except for the sampleinfo message, which
2499 * has no parameter 0"
2501 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2502 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2503 (inst
->exec_size
/ 8) +
2504 inst
->header_size
- 1].is_zero()) {
2505 inst
->mlen
-= inst
->exec_size
/ 8;
2511 invalidate_live_intervals();
2517 * Optimize sample messages which are followed by the final RT write.
2519 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2520 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2521 * final texturing results copied to the framebuffer write payload and modify
2522 * them to write to the framebuffer directly.
2525 fs_visitor::opt_sampler_eot()
2527 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2529 if (stage
!= MESA_SHADER_FRAGMENT
)
2532 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2535 /* FINISHME: It should be possible to implement this optimization when there
2536 * are multiple drawbuffers.
2538 if (key
->nr_color_regions
!= 1)
2541 /* Requires emitting a bunch of saturating MOV instructions during logical
2542 * send lowering to clamp the color payload, which the sampler unit isn't
2543 * going to do for us.
2545 if (key
->clamp_fragment_color
)
2548 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2549 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2550 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2551 assert(fb_write
->eot
);
2552 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2554 /* There wasn't one; nothing to do. */
2555 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2558 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2560 /* 3D Sampler » Messages » Message Format
2562 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2563 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2565 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2566 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2567 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2568 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2569 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2570 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2571 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2572 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2575 /* XXX - This shouldn't be necessary. */
2576 if (tex_inst
->prev
->is_head_sentinel())
2579 /* Check that the FB write sources are fully initialized by the single
2580 * texturing instruction.
2582 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2583 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2584 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2585 fb_write
->size_read(i
) != tex_inst
->size_written
)
2587 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2588 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2593 assert(!tex_inst
->eot
); /* We can't get here twice */
2594 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2596 const fs_builder
ibld(this, block
, tex_inst
);
2598 tex_inst
->offset
|= fb_write
->target
<< 24;
2599 tex_inst
->eot
= true;
2600 tex_inst
->dst
= ibld
.null_reg_ud();
2601 tex_inst
->size_written
= 0;
2602 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2604 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2605 * flag and submit a header together with the sampler message as required
2608 invalidate_live_intervals();
2613 fs_visitor::opt_register_renaming()
2615 bool progress
= false;
2618 int remap
[alloc
.count
];
2619 memset(remap
, -1, sizeof(int) * alloc
.count
);
2621 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2622 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2624 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2625 inst
->opcode
== BRW_OPCODE_WHILE
) {
2629 /* Rewrite instruction sources. */
2630 for (int i
= 0; i
< inst
->sources
; i
++) {
2631 if (inst
->src
[i
].file
== VGRF
&&
2632 remap
[inst
->src
[i
].nr
] != -1 &&
2633 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2634 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2639 const int dst
= inst
->dst
.nr
;
2642 inst
->dst
.file
== VGRF
&&
2643 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2644 !inst
->is_partial_write()) {
2645 if (remap
[dst
] == -1) {
2648 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2649 inst
->dst
.nr
= remap
[dst
];
2652 } else if (inst
->dst
.file
== VGRF
&&
2654 remap
[dst
] != dst
) {
2655 inst
->dst
.nr
= remap
[dst
];
2661 invalidate_live_intervals();
2663 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2664 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2665 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2674 * Remove redundant or useless discard jumps.
2676 * For example, we can eliminate jumps in the following sequence:
2678 * discard-jump (redundant with the next jump)
2679 * discard-jump (useless; jumps to the next instruction)
2683 fs_visitor::opt_redundant_discard_jumps()
2685 bool progress
= false;
2687 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2689 fs_inst
*placeholder_halt
= NULL
;
2690 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2691 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2692 placeholder_halt
= inst
;
2697 if (!placeholder_halt
)
2700 /* Delete any HALTs immediately before the placeholder halt. */
2701 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2702 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2703 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2704 prev
->remove(last_bblock
);
2709 invalidate_live_intervals();
2715 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2716 * from \p r.offset which overlaps the region starting at \p s.offset and
2717 * spanning \p ds bytes.
2719 static inline unsigned
2720 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2722 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2723 const int shift
= rel_offset
/ REG_SIZE
;
2724 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2725 assert(reg_space(r
) == reg_space(s
) &&
2726 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2727 return ((1 << n
) - 1) << shift
;
2731 fs_visitor::compute_to_mrf()
2733 bool progress
= false;
2736 /* No MRFs on Gen >= 7. */
2737 if (devinfo
->gen
>= 7)
2740 calculate_live_intervals();
2742 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2746 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2747 inst
->is_partial_write() ||
2748 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2749 inst
->dst
.type
!= inst
->src
[0].type
||
2750 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2751 !inst
->src
[0].is_contiguous() ||
2752 inst
->src
[0].offset
% REG_SIZE
!= 0)
2755 /* Can't compute-to-MRF this GRF if someone else was going to
2758 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2761 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2762 * things that computed the value of all GRFs of the source region. The
2763 * regs_left bitset keeps track of the registers we haven't yet found a
2764 * generating instruction for.
2766 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2768 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2769 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2770 inst
->src
[0], inst
->size_read(0))) {
2771 /* Found the last thing to write our reg we want to turn
2772 * into a compute-to-MRF.
2775 /* If this one instruction didn't populate all the
2776 * channels, bail. We might be able to rewrite everything
2777 * that writes that reg, but it would require smarter
2780 if (scan_inst
->is_partial_write())
2783 /* Handling things not fully contained in the source of the copy
2784 * would need us to understand coalescing out more than one MOV at
2787 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
2788 inst
->src
[0], inst
->size_read(0)))
2791 /* SEND instructions can't have MRF as a destination. */
2792 if (scan_inst
->mlen
)
2795 if (devinfo
->gen
== 6) {
2796 /* gen6 math instructions must have the destination be
2797 * GRF, so no compute-to-MRF for them.
2799 if (scan_inst
->is_math()) {
2804 /* Clear the bits for any registers this instruction overwrites. */
2805 regs_left
&= ~mask_relative_to(
2806 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2811 /* We don't handle control flow here. Most computation of
2812 * values that end up in MRFs are shortly before the MRF
2815 if (block
->start() == scan_inst
)
2818 /* You can't read from an MRF, so if someone else reads our
2819 * MRF's source GRF that we wanted to rewrite, that stops us.
2821 bool interfered
= false;
2822 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2823 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2824 inst
->src
[0], inst
->size_read(0))) {
2831 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2832 inst
->dst
, inst
->size_written
)) {
2833 /* If somebody else writes our MRF here, we can't
2834 * compute-to-MRF before that.
2839 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2840 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2841 inst
->dst
, inst
->size_written
)) {
2842 /* Found a SEND instruction, which means that there are
2843 * live values in MRFs from base_mrf to base_mrf +
2844 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2854 /* Found all generating instructions of our MRF's source value, so it
2855 * should be safe to rewrite them to point to the MRF directly.
2857 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2859 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2860 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2861 inst
->src
[0], inst
->size_read(0))) {
2862 /* Clear the bits for any registers this instruction overwrites. */
2863 regs_left
&= ~mask_relative_to(
2864 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2866 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
2867 reg_offset(inst
->src
[0]);
2869 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2870 /* Apply the same address transformation done by the hardware
2871 * for COMPR4 MRF writes.
2873 assert(rel_offset
< 2 * REG_SIZE
);
2874 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
2876 /* Clear the COMPR4 bit if the generating instruction is not
2879 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2880 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2883 /* Calculate the MRF number the result of this instruction is
2884 * ultimately written to.
2886 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
2889 scan_inst
->dst
.file
= MRF
;
2890 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
2891 scan_inst
->saturate
|= inst
->saturate
;
2898 inst
->remove(block
);
2903 invalidate_live_intervals();
2909 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2910 * flow. We could probably do better here with some form of divergence
2914 fs_visitor::eliminate_find_live_channel()
2916 bool progress
= false;
2919 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
2920 /* The optimization below assumes that channel zero is live on thread
2921 * dispatch, which may not be the case if the fixed function dispatches
2927 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2928 switch (inst
->opcode
) {
2934 case BRW_OPCODE_ENDIF
:
2935 case BRW_OPCODE_WHILE
:
2939 case FS_OPCODE_DISCARD_JUMP
:
2940 /* This can potentially make control flow non-uniform until the end
2945 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2947 inst
->opcode
= BRW_OPCODE_MOV
;
2948 inst
->src
[0] = brw_imm_ud(0u);
2950 inst
->force_writemask_all
= true;
2964 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2965 * instructions to FS_OPCODE_REP_FB_WRITE.
2968 fs_visitor::emit_repclear_shader()
2970 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2972 int color_mrf
= base_mrf
+ 2;
2976 mov
= bld
.exec_all().group(4, 0)
2977 .MOV(brw_message_reg(color_mrf
),
2978 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2980 struct brw_reg reg
=
2981 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2982 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2983 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2985 mov
= bld
.exec_all().group(4, 0)
2986 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2990 if (key
->nr_color_regions
== 1) {
2991 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2992 write
->saturate
= key
->clamp_fragment_color
;
2993 write
->base_mrf
= color_mrf
;
2995 write
->header_size
= 0;
2998 assume(key
->nr_color_regions
> 0);
2999 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3000 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3001 write
->saturate
= key
->clamp_fragment_color
;
3002 write
->base_mrf
= base_mrf
;
3004 write
->header_size
= 2;
3012 assign_constant_locations();
3013 assign_curb_setup();
3015 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3017 assert(mov
->src
[0].file
== FIXED_GRF
);
3018 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3023 * Walks through basic blocks, looking for repeated MRF writes and
3024 * removing the later ones.
3027 fs_visitor::remove_duplicate_mrf_writes()
3029 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3030 bool progress
= false;
3032 /* Need to update the MRF tracking for compressed instructions. */
3033 if (dispatch_width
>= 16)
3036 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3038 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3039 if (inst
->is_control_flow()) {
3040 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3043 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3044 inst
->dst
.file
== MRF
) {
3045 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3046 if (prev_inst
&& inst
->equals(prev_inst
)) {
3047 inst
->remove(block
);
3053 /* Clear out the last-write records for MRFs that were overwritten. */
3054 if (inst
->dst
.file
== MRF
) {
3055 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3058 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3059 /* Found a SEND instruction, which will include two or fewer
3060 * implied MRF writes. We could do better here.
3062 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3063 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3067 /* Clear out any MRF move records whose sources got overwritten. */
3068 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3069 if (last_mrf_move
[i
] &&
3070 regions_overlap(inst
->dst
, inst
->size_written
,
3071 last_mrf_move
[i
]->src
[0],
3072 last_mrf_move
[i
]->size_read(0))) {
3073 last_mrf_move
[i
] = NULL
;
3077 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3078 inst
->dst
.file
== MRF
&&
3079 inst
->src
[0].file
!= ARF
&&
3080 !inst
->is_partial_write()) {
3081 last_mrf_move
[inst
->dst
.nr
] = inst
;
3086 invalidate_live_intervals();
3092 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3094 /* Clear the flag for registers that actually got read (as expected). */
3095 for (int i
= 0; i
< inst
->sources
; i
++) {
3097 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3098 grf
= inst
->src
[i
].nr
;
3103 if (grf
>= first_grf
&&
3104 grf
< first_grf
+ grf_len
) {
3105 deps
[grf
- first_grf
] = false;
3106 if (inst
->exec_size
== 16)
3107 deps
[grf
- first_grf
+ 1] = false;
3113 * Implements this workaround for the original 965:
3115 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3116 * check for post destination dependencies on this instruction, software
3117 * must ensure that there is no destination hazard for the case of ‘write
3118 * followed by a posted write’ shown in the following example.
3121 * 2. send r3.xy <rest of send instruction>
3124 * Due to no post-destination dependency check on the ‘send’, the above
3125 * code sequence could have two instructions (1 and 2) in flight at the
3126 * same time that both consider ‘r3’ as the target of their final writes.
3129 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3132 int write_len
= regs_written(inst
);
3133 int first_write_grf
= inst
->dst
.nr
;
3134 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3135 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3137 memset(needs_dep
, false, sizeof(needs_dep
));
3138 memset(needs_dep
, true, write_len
);
3140 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3142 /* Walk backwards looking for writes to registers we're writing which
3143 * aren't read since being written. If we hit the start of the program,
3144 * we assume that there are no outstanding dependencies on entry to the
3147 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3148 /* If we hit control flow, assume that there *are* outstanding
3149 * dependencies, and force their cleanup before our instruction.
3151 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3152 for (int i
= 0; i
< write_len
; i
++) {
3154 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3155 first_write_grf
+ i
);
3160 /* We insert our reads as late as possible on the assumption that any
3161 * instruction but a MOV that might have left us an outstanding
3162 * dependency has more latency than a MOV.
3164 if (scan_inst
->dst
.file
== VGRF
) {
3165 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3166 int reg
= scan_inst
->dst
.nr
+ i
;
3168 if (reg
>= first_write_grf
&&
3169 reg
< first_write_grf
+ write_len
&&
3170 needs_dep
[reg
- first_write_grf
]) {
3171 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3172 needs_dep
[reg
- first_write_grf
] = false;
3173 if (scan_inst
->exec_size
== 16)
3174 needs_dep
[reg
- first_write_grf
+ 1] = false;
3179 /* Clear the flag for registers that actually got read (as expected). */
3180 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3182 /* Continue the loop only if we haven't resolved all the dependencies */
3184 for (i
= 0; i
< write_len
; i
++) {
3194 * Implements this workaround for the original 965:
3196 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3197 * used as a destination register until after it has been sourced by an
3198 * instruction with a different destination register.
3201 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3203 int write_len
= regs_written(inst
);
3204 int first_write_grf
= inst
->dst
.nr
;
3205 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3206 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3208 memset(needs_dep
, false, sizeof(needs_dep
));
3209 memset(needs_dep
, true, write_len
);
3210 /* Walk forwards looking for writes to registers we're writing which aren't
3211 * read before being written.
3213 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3214 /* If we hit control flow, force resolve all remaining dependencies. */
3215 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3216 for (int i
= 0; i
< write_len
; i
++) {
3218 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3219 first_write_grf
+ i
);
3224 /* Clear the flag for registers that actually got read (as expected). */
3225 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3227 /* We insert our reads as late as possible since they're reading the
3228 * result of a SEND, which has massive latency.
3230 if (scan_inst
->dst
.file
== VGRF
&&
3231 scan_inst
->dst
.nr
>= first_write_grf
&&
3232 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3233 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3234 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3236 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3239 /* Continue the loop only if we haven't resolved all the dependencies */
3241 for (i
= 0; i
< write_len
; i
++) {
3251 fs_visitor::insert_gen4_send_dependency_workarounds()
3253 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3256 bool progress
= false;
3258 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3259 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3260 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3261 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3267 invalidate_live_intervals();
3271 * Turns the generic expression-style uniform pull constant load instruction
3272 * into a hardware-specific series of instructions for loading a pull
3275 * The expression style allows the CSE pass before this to optimize out
3276 * repeated loads from the same offset, and gives the pre-register-allocation
3277 * scheduling full flexibility, while the conversion to native instructions
3278 * allows the post-register-allocation scheduler the best information
3281 * Note that execution masking for setting up pull constant loads is special:
3282 * the channels that need to be written are unrelated to the current execution
3283 * mask, since a later instruction will use one of the result channels as a
3284 * source operand for all 8 or 16 of its channels.
3287 fs_visitor::lower_uniform_pull_constant_loads()
3289 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3290 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3293 if (devinfo
->gen
>= 7) {
3294 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3295 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3297 ubld
.group(8, 0).MOV(payload
,
3298 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3299 ubld
.group(1, 0).MOV(component(payload
, 2),
3300 brw_imm_ud(inst
->src
[1].ud
/ 16));
3302 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3303 inst
->src
[1] = payload
;
3304 inst
->header_size
= 1;
3307 invalidate_live_intervals();
3309 /* Before register allocation, we didn't tell the scheduler about the
3310 * MRF we use. We know it's safe to use this MRF because nothing
3311 * else does except for register spill/unspill, which generates and
3312 * uses its MRF within a single IR instruction.
3314 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3321 fs_visitor::lower_load_payload()
3323 bool progress
= false;
3325 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3326 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3329 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3330 assert(inst
->saturate
== false);
3331 fs_reg dst
= inst
->dst
;
3333 /* Get rid of COMPR4. We'll add it back in if we need it */
3334 if (dst
.file
== MRF
)
3335 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3337 const fs_builder
ibld(this, block
, inst
);
3338 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3340 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3341 if (inst
->src
[i
].file
!= BAD_FILE
) {
3342 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3343 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3344 hbld
.MOV(mov_dst
, mov_src
);
3346 dst
= offset(dst
, hbld
, 1);
3349 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3350 inst
->exec_size
> 8) {
3351 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3352 * a straightforward copy. Instead, the result of the
3353 * LOAD_PAYLOAD is treated as interleaved and the first four
3354 * non-header sources are unpacked as:
3365 * This is used for gen <= 5 fb writes.
3367 assert(inst
->exec_size
== 16);
3368 assert(inst
->header_size
+ 4 <= inst
->sources
);
3369 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3370 if (inst
->src
[i
].file
!= BAD_FILE
) {
3371 if (devinfo
->has_compr4
) {
3372 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3373 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3374 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3376 /* Platform doesn't have COMPR4. We have to fake it */
3377 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3378 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3380 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3387 /* The loop above only ever incremented us through the first set
3388 * of 4 registers. However, thanks to the magic of COMPR4, we
3389 * actually wrote to the first 8 registers, so we need to take
3390 * that into account now.
3394 /* The COMPR4 code took care of the first 4 sources. We'll let
3395 * the regular path handle any remaining sources. Yes, we are
3396 * modifying the instruction but we're about to delete it so
3397 * this really doesn't hurt anything.
3399 inst
->header_size
+= 4;
3402 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3403 if (inst
->src
[i
].file
!= BAD_FILE
)
3404 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3405 dst
= offset(dst
, ibld
, 1);
3408 inst
->remove(block
);
3413 invalidate_live_intervals();
3419 fs_visitor::lower_integer_multiplication()
3421 bool progress
= false;
3423 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3424 const fs_builder
ibld(this, block
, inst
);
3426 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3427 if (inst
->dst
.is_accumulator() ||
3428 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3429 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3432 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3433 * operation directly, but CHV/BXT cannot.
3435 if (devinfo
->gen
>= 8 &&
3436 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
))
3439 if (inst
->src
[1].file
== IMM
&&
3440 inst
->src
[1].ud
< (1 << 16)) {
3441 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3442 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3445 * If multiplying by an immediate value that fits in 16-bits, do a
3446 * single MUL instruction with that value in the proper location.
3448 if (devinfo
->gen
< 7) {
3449 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3451 ibld
.MOV(imm
, inst
->src
[1]);
3452 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3454 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3455 ibld
.MUL(inst
->dst
, inst
->src
[0],
3456 ud
? brw_imm_uw(inst
->src
[1].ud
)
3457 : brw_imm_w(inst
->src
[1].d
));
3460 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3461 * do 32-bit integer multiplication in one instruction, but instead
3462 * must do a sequence (which actually calculates a 64-bit result):
3464 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3465 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3466 * mov(8) g2<1>D acc0<8,8,1>D
3468 * But on Gen > 6, the ability to use second accumulator register
3469 * (acc1) for non-float data types was removed, preventing a simple
3470 * implementation in SIMD16. A 16-channel result can be calculated by
3471 * executing the three instructions twice in SIMD8, once with quarter
3472 * control of 1Q for the first eight channels and again with 2Q for
3473 * the second eight channels.
3475 * Which accumulator register is implicitly accessed (by AccWrEnable
3476 * for instance) is determined by the quarter control. Unfortunately
3477 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3478 * implicit accumulator access by an instruction with 2Q will access
3479 * acc1 regardless of whether the data type is usable in acc1.
3481 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3482 * integer data types.
3484 * Since we only want the low 32-bits of the result, we can do two
3485 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3486 * adjust the high result and add them (like the mach is doing):
3488 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3489 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3490 * shl(8) g9<1>D g8<8,8,1>D 16D
3491 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3493 * We avoid the shl instruction by realizing that we only want to add
3494 * the low 16-bits of the "high" result to the high 16-bits of the
3495 * "low" result and using proper regioning on the add:
3497 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3498 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3499 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3501 * Since it does not use the (single) accumulator register, we can
3502 * schedule multi-component multiplications much better.
3505 bool needs_mov
= false;
3506 fs_reg orig_dst
= inst
->dst
;
3507 fs_reg low
= inst
->dst
;
3508 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3509 regions_overlap(inst
->dst
, inst
->size_written
,
3510 inst
->src
[0], inst
->size_read(0)) ||
3511 regions_overlap(inst
->dst
, inst
->size_written
,
3512 inst
->src
[1], inst
->size_read(1))) {
3514 low
.nr
= alloc
.allocate(regs_written(inst
));
3515 low
.offset
= low
.offset
% REG_SIZE
;
3518 fs_reg high
= inst
->dst
;
3519 high
.nr
= alloc
.allocate(regs_written(inst
));
3520 high
.offset
= high
.offset
% REG_SIZE
;
3522 if (devinfo
->gen
>= 7) {
3523 if (inst
->src
[1].file
== IMM
) {
3524 ibld
.MUL(low
, inst
->src
[0],
3525 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3526 ibld
.MUL(high
, inst
->src
[0],
3527 brw_imm_uw(inst
->src
[1].ud
>> 16));
3529 ibld
.MUL(low
, inst
->src
[0],
3530 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3531 ibld
.MUL(high
, inst
->src
[0],
3532 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3535 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3537 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3541 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3542 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3543 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3545 if (needs_mov
|| inst
->conditional_mod
) {
3546 set_condmod(inst
->conditional_mod
,
3547 ibld
.MOV(orig_dst
, low
));
3551 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3552 /* Should have been lowered to 8-wide. */
3553 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3554 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3556 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3557 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3559 if (devinfo
->gen
>= 8) {
3560 /* Until Gen8, integer multiplies read 32-bits from one source,
3561 * and 16-bits from the other, and relying on the MACH instruction
3562 * to generate the high bits of the result.
3564 * On Gen8, the multiply instruction does a full 32x32-bit
3565 * multiply, but in order to do a 64-bit multiply we can simulate
3566 * the previous behavior and then use a MACH instruction.
3568 * FINISHME: Don't use source modifiers on src1.
3570 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3571 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3572 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3573 mul
->src
[1].stride
*= 2;
3575 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3577 /* Among other things the quarter control bits influence which
3578 * accumulator register is used by the hardware for instructions
3579 * that access the accumulator implicitly (e.g. MACH). A
3580 * second-half instruction would normally map to acc1, which
3581 * doesn't exist on Gen7 and up (the hardware does emulate it for
3582 * floating-point instructions *only* by taking advantage of the
3583 * extra precision of acc0 not normally used for floating point
3586 * HSW and up are careful enough not to try to access an
3587 * accumulator register that doesn't exist, but on earlier Gen7
3588 * hardware we need to make sure that the quarter control bits are
3589 * zero to avoid non-deterministic behaviour and emit an extra MOV
3590 * to get the result masked correctly according to the current
3594 mach
->force_writemask_all
= true;
3595 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3596 ibld
.MOV(inst
->dst
, mach
->dst
);
3602 inst
->remove(block
);
3607 invalidate_live_intervals();
3613 fs_visitor::lower_minmax()
3615 assert(devinfo
->gen
< 6);
3617 bool progress
= false;
3619 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3620 const fs_builder
ibld(this, block
, inst
);
3622 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3623 inst
->predicate
== BRW_PREDICATE_NONE
) {
3624 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3625 * the original SEL.L/GE instruction
3627 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3628 inst
->conditional_mod
);
3629 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3630 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3637 invalidate_live_intervals();
3643 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3644 fs_reg
*dst
, fs_reg color
, unsigned components
)
3646 if (key
->clamp_fragment_color
) {
3647 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3648 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3650 for (unsigned i
= 0; i
< components
; i
++)
3652 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3657 for (unsigned i
= 0; i
< components
; i
++)
3658 dst
[i
] = offset(color
, bld
, i
);
3662 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3663 const struct brw_wm_prog_data
*prog_data
,
3664 const brw_wm_prog_key
*key
,
3665 const fs_visitor::thread_payload
&payload
)
3667 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3668 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3669 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3670 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3671 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3672 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3673 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3674 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3675 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3676 const unsigned components
=
3677 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3679 /* We can potentially have a message length of up to 15, so we have to set
3680 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3683 int header_size
= 2, payload_header_size
;
3684 unsigned length
= 0;
3686 /* From the Sandy Bridge PRM, volume 4, page 198:
3688 * "Dispatched Pixel Enables. One bit per pixel indicating
3689 * which pixels were originally enabled when the thread was
3690 * dispatched. This field is only required for the end-of-
3691 * thread message and on all dual-source messages."
3693 if (devinfo
->gen
>= 6 &&
3694 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3695 color1
.file
== BAD_FILE
&&
3696 key
->nr_color_regions
== 1) {
3700 if (header_size
!= 0) {
3701 assert(header_size
== 2);
3702 /* Allocate 2 registers for a header */
3706 if (payload
.aa_dest_stencil_reg
) {
3707 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3708 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3709 .MOV(sources
[length
],
3710 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3714 if (sample_mask
.file
!= BAD_FILE
) {
3715 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3716 BRW_REGISTER_TYPE_UD
);
3718 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3719 * relevant. Since it's unsigned single words one vgrf is always
3720 * 16-wide, but only the lower or higher 8 channels will be used by the
3721 * hardware when doing a SIMD8 write depending on whether we have
3722 * selected the subspans for the first or second half respectively.
3724 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3725 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3726 sample_mask
.stride
*= 2;
3728 bld
.exec_all().annotate("FB write oMask")
3729 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3735 payload_header_size
= length
;
3737 if (src0_alpha
.file
!= BAD_FILE
) {
3738 /* FIXME: This is being passed at the wrong location in the payload and
3739 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3740 * It's supposed to be immediately before oMask but there seems to be no
3741 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3742 * requires header sources to form a contiguous segment at the beginning
3743 * of the message and src0_alpha has per-channel semantics.
3745 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3747 } else if (key
->replicate_alpha
&& inst
->target
!= 0) {
3748 /* Handle the case when fragment shader doesn't write to draw buffer
3749 * zero. No need to call setup_color_payload() for src0_alpha because
3750 * alpha value will be undefined.
3755 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3758 if (color1
.file
!= BAD_FILE
) {
3759 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3763 if (src_depth
.file
!= BAD_FILE
) {
3764 sources
[length
] = src_depth
;
3768 if (dst_depth
.file
!= BAD_FILE
) {
3769 sources
[length
] = dst_depth
;
3773 if (src_stencil
.file
!= BAD_FILE
) {
3774 assert(devinfo
->gen
>= 9);
3775 assert(bld
.dispatch_width() != 16);
3777 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3778 * available on gen9+. As such it's impossible to have both enabled at the
3779 * same time and therefore length cannot overrun the array.
3781 assert(length
< 15);
3783 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3784 bld
.exec_all().annotate("FB write OS")
3785 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3786 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3791 if (devinfo
->gen
>= 7) {
3792 /* Send from the GRF */
3793 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3794 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3795 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3796 load
->dst
= payload
;
3798 inst
->src
[0] = payload
;
3799 inst
->resize_sources(1);
3801 /* Send from the MRF */
3802 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3803 sources
, length
, payload_header_size
);
3805 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3806 * will do this for us if we just give it a COMPR4 destination.
3808 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3809 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3811 inst
->resize_sources(0);
3815 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3816 inst
->mlen
= regs_written(load
);
3817 inst
->header_size
= header_size
;
3821 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3823 const fs_builder
&ubld
= bld
.exec_all();
3824 const unsigned length
= 2;
3825 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3828 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3830 inst
->resize_sources(1);
3831 inst
->src
[0] = header
;
3832 inst
->opcode
= FS_OPCODE_FB_READ
;
3833 inst
->mlen
= length
;
3834 inst
->header_size
= length
;
3838 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3839 const fs_reg
&coordinate
,
3840 const fs_reg
&shadow_c
,
3841 const fs_reg
&lod
, const fs_reg
&lod2
,
3842 const fs_reg
&surface
,
3843 const fs_reg
&sampler
,
3844 unsigned coord_components
,
3845 unsigned grad_components
)
3847 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3848 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3849 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3850 fs_reg msg_end
= msg_begin
;
3853 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3855 for (unsigned i
= 0; i
< coord_components
; i
++)
3856 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3857 offset(coordinate
, bld
, i
));
3859 msg_end
= offset(msg_end
, bld
, coord_components
);
3861 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3862 * require all three components to be present and zero if they are unused.
3864 if (coord_components
> 0 &&
3865 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3866 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3867 for (unsigned i
= coord_components
; i
< 3; i
++)
3868 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3870 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3873 if (op
== SHADER_OPCODE_TXD
) {
3874 /* TXD unsupported in SIMD16 mode. */
3875 assert(bld
.dispatch_width() == 8);
3877 /* the slots for u and v are always present, but r is optional */
3878 if (coord_components
< 2)
3879 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3882 * dPdx = dudx, dvdx, drdx
3883 * dPdy = dudy, dvdy, drdy
3885 * 1-arg: Does not exist.
3887 * 2-arg: dudx dvdx dudy dvdy
3888 * dPdx.x dPdx.y dPdy.x dPdy.y
3891 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3892 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3893 * m5 m6 m7 m8 m9 m10
3895 for (unsigned i
= 0; i
< grad_components
; i
++)
3896 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3898 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3900 for (unsigned i
= 0; i
< grad_components
; i
++)
3901 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3903 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3907 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
3908 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
3910 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3911 bld
.dispatch_width() == 16);
3913 const brw_reg_type type
=
3914 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3915 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3916 bld
.MOV(retype(msg_end
, type
), lod
);
3917 msg_end
= offset(msg_end
, bld
, 1);
3920 if (shadow_c
.file
!= BAD_FILE
) {
3921 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3922 /* There's no plain shadow compare message, so we use shadow
3923 * compare with a bias of 0.0.
3925 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3926 msg_end
= offset(msg_end
, bld
, 1);
3929 bld
.MOV(msg_end
, shadow_c
);
3930 msg_end
= offset(msg_end
, bld
, 1);
3934 inst
->src
[0] = reg_undef
;
3935 inst
->src
[1] = surface
;
3936 inst
->src
[2] = sampler
;
3937 inst
->resize_sources(3);
3938 inst
->base_mrf
= msg_begin
.nr
;
3939 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3940 inst
->header_size
= 1;
3944 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3945 const fs_reg
&coordinate
,
3946 const fs_reg
&shadow_c
,
3947 const fs_reg
&lod
, const fs_reg
&lod2
,
3948 const fs_reg
&sample_index
,
3949 const fs_reg
&surface
,
3950 const fs_reg
&sampler
,
3951 unsigned coord_components
,
3952 unsigned grad_components
)
3954 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3955 fs_reg msg_coords
= message
;
3956 unsigned header_size
= 0;
3958 if (inst
->offset
!= 0) {
3959 /* The offsets set up by the visitor are in the m1 header, so we can't
3966 for (unsigned i
= 0; i
< coord_components
; i
++)
3967 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3968 offset(coordinate
, bld
, i
));
3970 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3971 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3973 if (shadow_c
.file
!= BAD_FILE
) {
3974 fs_reg msg_shadow
= msg_lod
;
3975 bld
.MOV(msg_shadow
, shadow_c
);
3976 msg_lod
= offset(msg_shadow
, bld
, 1);
3981 case SHADER_OPCODE_TXL
:
3983 bld
.MOV(msg_lod
, lod
);
3984 msg_end
= offset(msg_lod
, bld
, 1);
3986 case SHADER_OPCODE_TXD
:
3989 * dPdx = dudx, dvdx, drdx
3990 * dPdy = dudy, dvdy, drdy
3992 * Load up these values:
3993 * - dudx dudy dvdx dvdy drdx drdy
3994 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3997 for (unsigned i
= 0; i
< grad_components
; i
++) {
3998 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3999 msg_end
= offset(msg_end
, bld
, 1);
4001 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4002 msg_end
= offset(msg_end
, bld
, 1);
4005 case SHADER_OPCODE_TXS
:
4006 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4007 bld
.MOV(msg_lod
, lod
);
4008 msg_end
= offset(msg_lod
, bld
, 1);
4010 case SHADER_OPCODE_TXF
:
4011 msg_lod
= offset(msg_coords
, bld
, 3);
4012 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4013 msg_end
= offset(msg_lod
, bld
, 1);
4015 case SHADER_OPCODE_TXF_CMS
:
4016 msg_lod
= offset(msg_coords
, bld
, 3);
4018 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4020 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4021 msg_end
= offset(msg_lod
, bld
, 2);
4028 inst
->src
[0] = reg_undef
;
4029 inst
->src
[1] = surface
;
4030 inst
->src
[2] = sampler
;
4031 inst
->resize_sources(3);
4032 inst
->base_mrf
= message
.nr
;
4033 inst
->mlen
= msg_end
.nr
- message
.nr
;
4034 inst
->header_size
= header_size
;
4036 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4037 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4041 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4043 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4046 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4050 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4051 const fs_reg
&coordinate
,
4052 const fs_reg
&shadow_c
,
4053 fs_reg lod
, const fs_reg
&lod2
,
4054 const fs_reg
&sample_index
,
4056 const fs_reg
&surface
,
4057 const fs_reg
&sampler
,
4058 const fs_reg
&tg4_offset
,
4059 unsigned coord_components
,
4060 unsigned grad_components
)
4062 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4063 unsigned reg_width
= bld
.dispatch_width() / 8;
4064 unsigned header_size
= 0, length
= 0;
4065 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4066 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4067 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4069 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4070 inst
->offset
!= 0 || inst
->eot
||
4071 op
== SHADER_OPCODE_SAMPLEINFO
||
4072 is_high_sampler(devinfo
, sampler
)) {
4073 /* For general texture offsets (no txf workaround), we need a header to
4074 * put them in. Note that we're only reserving space for it in the
4075 * message payload as it will be initialized implicitly by the
4078 * TG4 needs to place its channel select in the header, for interaction
4079 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4080 * larger sampler numbers we need to offset the Sampler State Pointer in
4084 sources
[0] = fs_reg();
4087 /* If we're requesting fewer than four channels worth of response,
4088 * and we have an explicit header, we need to set up the sampler
4089 * writemask. It's reversed from normal: 1 means "don't write".
4091 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4092 assert(regs_written(inst
) % reg_width
== 0);
4093 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4094 inst
->offset
|= mask
<< 12;
4098 if (shadow_c
.file
!= BAD_FILE
) {
4099 bld
.MOV(sources
[length
], shadow_c
);
4103 bool coordinate_done
= false;
4105 /* Set up the LOD info */
4108 case SHADER_OPCODE_TXL
:
4109 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4110 op
= SHADER_OPCODE_TXL_LZ
;
4113 bld
.MOV(sources
[length
], lod
);
4116 case SHADER_OPCODE_TXD
:
4117 /* TXD should have been lowered in SIMD16 mode. */
4118 assert(bld
.dispatch_width() == 8);
4120 /* Load dPdx and the coordinate together:
4121 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4123 for (unsigned i
= 0; i
< coord_components
; i
++) {
4124 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4126 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4127 * only derivatives for (u, v, r).
4129 if (i
< grad_components
) {
4130 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4131 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4135 coordinate_done
= true;
4137 case SHADER_OPCODE_TXS
:
4138 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4141 case SHADER_OPCODE_TXF
:
4142 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4143 * On Gen9 they are u, v, lod, r
4145 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4147 if (devinfo
->gen
>= 9) {
4148 if (coord_components
>= 2) {
4149 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4150 offset(coordinate
, bld
, 1));
4152 sources
[length
] = brw_imm_d(0);
4157 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4158 op
= SHADER_OPCODE_TXF_LZ
;
4160 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4164 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4165 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4166 offset(coordinate
, bld
, i
));
4168 coordinate_done
= true;
4171 case SHADER_OPCODE_TXF_CMS
:
4172 case SHADER_OPCODE_TXF_CMS_W
:
4173 case SHADER_OPCODE_TXF_UMS
:
4174 case SHADER_OPCODE_TXF_MCS
:
4175 if (op
== SHADER_OPCODE_TXF_UMS
||
4176 op
== SHADER_OPCODE_TXF_CMS
||
4177 op
== SHADER_OPCODE_TXF_CMS_W
) {
4178 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4182 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4183 /* Data from the multisample control surface. */
4184 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4187 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4190 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4191 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4194 offset(mcs
, bld
, 1));
4199 /* There is no offsetting for this message; just copy in the integer
4200 * texture coordinates.
4202 for (unsigned i
= 0; i
< coord_components
; i
++)
4203 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4204 offset(coordinate
, bld
, i
));
4206 coordinate_done
= true;
4208 case SHADER_OPCODE_TG4_OFFSET
:
4209 /* More crazy intermixing */
4210 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4211 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4213 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4214 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4215 offset(tg4_offset
, bld
, i
));
4217 if (coord_components
== 3) /* r if present */
4218 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4220 coordinate_done
= true;
4226 /* Set up the coordinate (except for cases where it was done above) */
4227 if (!coordinate_done
) {
4228 for (unsigned i
= 0; i
< coord_components
; i
++)
4229 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4234 mlen
= length
* reg_width
- header_size
;
4236 mlen
= length
* reg_width
;
4238 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4239 BRW_REGISTER_TYPE_F
);
4240 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4242 /* Generate the SEND. */
4244 inst
->src
[0] = src_payload
;
4245 inst
->src
[1] = surface
;
4246 inst
->src
[2] = sampler
;
4247 inst
->resize_sources(3);
4249 inst
->header_size
= header_size
;
4251 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4252 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4256 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4258 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4259 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4260 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4261 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4262 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4263 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4264 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4265 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4266 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4267 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
4268 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4269 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4270 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4271 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4273 if (devinfo
->gen
>= 7) {
4274 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4275 shadow_c
, lod
, lod2
, sample_index
,
4276 mcs
, surface
, sampler
, tg4_offset
,
4277 coord_components
, grad_components
);
4278 } else if (devinfo
->gen
>= 5) {
4279 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4280 shadow_c
, lod
, lod2
, sample_index
,
4282 coord_components
, grad_components
);
4284 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4285 shadow_c
, lod
, lod2
,
4287 coord_components
, grad_components
);
4292 * Initialize the header present in some typed and untyped surface
4296 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4298 fs_builder ubld
= bld
.exec_all().group(8, 0);
4299 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4300 ubld
.MOV(dst
, brw_imm_d(0));
4301 ubld
.MOV(component(dst
, 7), sample_mask
);
4306 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4307 const fs_reg
&sample_mask
)
4309 /* Get the logical send arguments. */
4310 const fs_reg
&addr
= inst
->src
[0];
4311 const fs_reg
&src
= inst
->src
[1];
4312 const fs_reg
&surface
= inst
->src
[2];
4313 const UNUSED fs_reg
&dims
= inst
->src
[3];
4314 const fs_reg
&arg
= inst
->src
[4];
4316 /* Calculate the total number of components of the payload. */
4317 const unsigned addr_sz
= inst
->components_read(0);
4318 const unsigned src_sz
= inst
->components_read(1);
4319 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4320 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4322 /* Allocate space for the payload. */
4323 fs_reg
*const components
= new fs_reg
[sz
];
4324 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4327 /* Construct the payload. */
4329 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4331 for (unsigned i
= 0; i
< addr_sz
; i
++)
4332 components
[n
++] = offset(addr
, bld
, i
);
4334 for (unsigned i
= 0; i
< src_sz
; i
++)
4335 components
[n
++] = offset(src
, bld
, i
);
4337 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4339 /* Update the original instruction. */
4341 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4342 inst
->header_size
= header_sz
;
4344 inst
->src
[0] = payload
;
4345 inst
->src
[1] = surface
;
4347 inst
->resize_sources(3);
4349 delete[] components
;
4353 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4355 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4357 if (devinfo
->gen
>= 7) {
4358 /* We are switching the instruction from an ALU-like instruction to a
4359 * send-from-grf instruction. Since sends can't handle strides or
4360 * source modifiers, we have to make a copy of the offset source.
4362 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4363 bld
.MOV(tmp
, inst
->src
[1]);
4366 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4369 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4370 BRW_REGISTER_TYPE_UD
);
4372 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4374 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4375 inst
->resize_sources(1);
4376 inst
->base_mrf
= payload
.nr
;
4377 inst
->header_size
= 1;
4378 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4383 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4385 assert(bld
.shader
->devinfo
->gen
< 6);
4388 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4390 if (inst
->sources
> 1) {
4391 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4392 * "Message Payload":
4394 * "Operand0[7]. For the INT DIV functions, this operand is the
4397 * "Operand1[7]. For the INT DIV functions, this operand is the
4400 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4401 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4402 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4404 inst
->resize_sources(1);
4405 inst
->src
[0] = src0
;
4407 assert(inst
->exec_size
== 8);
4408 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4413 fs_visitor::lower_logical_sends()
4415 bool progress
= false;
4417 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4418 const fs_builder
ibld(this, block
, inst
);
4420 switch (inst
->opcode
) {
4421 case FS_OPCODE_FB_WRITE_LOGICAL
:
4422 assert(stage
== MESA_SHADER_FRAGMENT
);
4423 lower_fb_write_logical_send(ibld
, inst
,
4424 brw_wm_prog_data(prog_data
),
4425 (const brw_wm_prog_key
*)key
,
4429 case FS_OPCODE_FB_READ_LOGICAL
:
4430 lower_fb_read_logical_send(ibld
, inst
);
4433 case SHADER_OPCODE_TEX_LOGICAL
:
4434 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4437 case SHADER_OPCODE_TXD_LOGICAL
:
4438 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4441 case SHADER_OPCODE_TXF_LOGICAL
:
4442 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4445 case SHADER_OPCODE_TXL_LOGICAL
:
4446 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4449 case SHADER_OPCODE_TXS_LOGICAL
:
4450 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4453 case FS_OPCODE_TXB_LOGICAL
:
4454 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4457 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4458 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4461 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4462 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4465 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4466 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4469 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4470 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4473 case SHADER_OPCODE_LOD_LOGICAL
:
4474 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4477 case SHADER_OPCODE_TG4_LOGICAL
:
4478 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4481 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4482 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4485 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4486 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4489 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4490 lower_surface_logical_send(ibld
, inst
,
4491 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4495 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4496 lower_surface_logical_send(ibld
, inst
,
4497 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4498 ibld
.sample_mask_reg());
4501 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4502 lower_surface_logical_send(ibld
, inst
,
4503 SHADER_OPCODE_UNTYPED_ATOMIC
,
4504 ibld
.sample_mask_reg());
4507 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4508 lower_surface_logical_send(ibld
, inst
,
4509 SHADER_OPCODE_TYPED_SURFACE_READ
,
4513 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4514 lower_surface_logical_send(ibld
, inst
,
4515 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4516 ibld
.sample_mask_reg());
4519 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4520 lower_surface_logical_send(ibld
, inst
,
4521 SHADER_OPCODE_TYPED_ATOMIC
,
4522 ibld
.sample_mask_reg());
4525 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4526 lower_varying_pull_constant_logical_send(ibld
, inst
);
4529 case SHADER_OPCODE_RCP
:
4530 case SHADER_OPCODE_RSQ
:
4531 case SHADER_OPCODE_SQRT
:
4532 case SHADER_OPCODE_EXP2
:
4533 case SHADER_OPCODE_LOG2
:
4534 case SHADER_OPCODE_SIN
:
4535 case SHADER_OPCODE_COS
:
4536 case SHADER_OPCODE_POW
:
4537 case SHADER_OPCODE_INT_QUOTIENT
:
4538 case SHADER_OPCODE_INT_REMAINDER
:
4539 /* The math opcodes are overloaded for the send-like and
4540 * expression-like instructions which seems kind of icky. Gen6+ has
4541 * a native (but rather quirky) MATH instruction so we don't need to
4542 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4543 * logical instructions (which we can easily recognize because they
4544 * have mlen = 0) into send-like virtual instructions.
4546 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4547 lower_math_logical_send(ibld
, inst
);
4562 invalidate_live_intervals();
4568 * Get the closest allowed SIMD width for instruction \p inst accounting for
4569 * some common regioning and execution control restrictions that apply to FPU
4570 * instructions. These restrictions don't necessarily have any relevance to
4571 * instructions not executed by the FPU pipeline like extended math, control
4572 * flow or send message instructions.
4574 * For virtual opcodes it's really up to the instruction -- In some cases
4575 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4576 * instructions) it may simplify virtual instruction lowering if we can
4577 * enforce FPU-like regioning restrictions already on the virtual instruction,
4578 * in other cases (e.g. virtual send-like instructions) this may be
4579 * excessively restrictive.
4582 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4583 const fs_inst
*inst
)
4585 /* Maximum execution size representable in the instruction controls. */
4586 unsigned max_width
= MIN2(32, inst
->exec_size
);
4588 /* According to the PRMs:
4589 * "A. In Direct Addressing mode, a source cannot span more than 2
4590 * adjacent GRF registers.
4591 * B. A destination cannot span more than 2 adjacent GRF registers."
4593 * Look for the source or destination with the largest register region
4594 * which is the one that is going to limit the overall execution size of
4595 * the instruction due to this rule.
4597 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4599 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4600 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4602 /* Calculate the maximum execution size of the instruction based on the
4603 * factor by which it goes over the hardware limit of 2 GRFs.
4606 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4608 /* According to the IVB PRMs:
4609 * "When destination spans two registers, the source MUST span two
4610 * registers. The exception to the above rule:
4612 * - When source is scalar, the source registers are not incremented.
4613 * - When source is packed integer Word and destination is packed
4614 * integer DWord, the source register is not incremented but the
4615 * source sub register is incremented."
4617 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4618 * restrictions. The code below intentionally doesn't check whether the
4619 * destination type is integer because empirically the hardware doesn't
4620 * seem to care what the actual type is as long as it's dword-aligned.
4622 if (devinfo
->gen
< 8) {
4623 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4624 /* IVB implements DF scalars as <0;2,1> regions. */
4625 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
4626 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
4627 const bool is_packed_word_exception
=
4628 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4629 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
4631 if (inst
->size_written
> REG_SIZE
&&
4632 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
4633 !is_scalar_exception
&& !is_packed_word_exception
) {
4634 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4635 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4640 /* From the IVB PRMs:
4641 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4642 * are applied for both halves of the SIMD32 instruction. If different
4643 * execution mask channels are required, split the instruction into two
4644 * SIMD16 instructions."
4646 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4647 * 32-wide control flow support in hardware and will behave similarly.
4649 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4650 max_width
= MIN2(max_width
, 16);
4652 /* From the IVB PRMs (applies to HSW too):
4653 * "Instructions with condition modifiers must not use SIMD32."
4655 * From the BDW PRMs (applies to later hardware too):
4656 * "Ternary instruction with condition modifiers must not use SIMD32."
4658 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4659 max_width
= MIN2(max_width
, 16);
4661 /* From the IVB PRMs (applies to other devices that don't have the
4662 * gen_device_info::supports_simd16_3src flag set):
4663 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4664 * SIMD8 is not allowed for DF operations."
4666 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4667 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4669 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4670 * the 8-bit quarter of the execution mask signals specified in the
4671 * instruction control fields) for the second compressed half of any
4672 * single-precision instruction (for double-precision instructions
4673 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4674 * the EU will apply the wrong execution controls for the second
4675 * sequential GRF write if the number of channels per GRF is not exactly
4676 * eight in single-precision mode (or four in double-float mode).
4678 * In this situation we calculate the maximum size of the split
4679 * instructions so they only ever write to a single register.
4681 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4682 !inst
->force_writemask_all
) {
4683 const unsigned channels_per_grf
= inst
->exec_size
/
4684 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4685 const unsigned exec_type_size
= get_exec_type_size(inst
);
4686 assert(exec_type_size
);
4688 /* The hardware shifts exactly 8 channels per compressed half of the
4689 * instruction in single-precision mode and exactly 4 in double-precision.
4691 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4692 max_width
= MIN2(max_width
, channels_per_grf
);
4694 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
4695 * because HW applies the same channel enable signals to both halves of
4696 * the compressed instruction which will be just wrong under
4697 * non-uniform control flow.
4699 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4700 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
4701 max_width
= MIN2(max_width
, 4);
4704 /* Only power-of-two execution sizes are representable in the instruction
4707 return 1 << _mesa_logbase2(max_width
);
4711 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4712 * various payload size restrictions that apply to sampler message
4715 * This is only intended to provide a maximum theoretical bound for the
4716 * execution size of the message based on the number of argument components
4717 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4718 * variant of the message can be used, though some messages may have
4719 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4720 * the message length to determine the exact SIMD width and argument count,
4721 * which makes a number of sampler message combinations impossible to
4725 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4726 const fs_inst
*inst
)
4728 /* Calculate the number of coordinate components that have to be present
4729 * assuming that additional arguments follow the texel coordinates in the
4730 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4731 * need to pad to four or three components depending on the message,
4732 * pre-ILK we need to pad to at most three components.
4734 const unsigned req_coord_components
=
4735 (devinfo
->gen
>= 7 ||
4736 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4737 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4738 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4741 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4742 * variant of the TXL or TXF message.
4744 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4745 (inst
->opcode
== SHADER_OPCODE_TXL
||
4746 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4747 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4749 /* Calculate the total number of argument components that need to be passed
4750 * to the sampler unit.
4752 const unsigned num_payload_components
=
4753 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4754 req_coord_components
) +
4755 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4756 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4757 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4758 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4759 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4760 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
4761 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4763 /* SIMD16 messages with more than five arguments exceed the maximum message
4764 * size supported by the sampler, regardless of whether a header is
4767 return MIN2(inst
->exec_size
,
4768 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4772 * Get the closest native SIMD width supported by the hardware for instruction
4773 * \p inst. The instruction will be left untouched by
4774 * fs_visitor::lower_simd_width() if the returned value is equal to the
4775 * original execution size.
4778 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4779 const fs_inst
*inst
)
4781 switch (inst
->opcode
) {
4782 case BRW_OPCODE_MOV
:
4783 case BRW_OPCODE_SEL
:
4784 case BRW_OPCODE_NOT
:
4785 case BRW_OPCODE_AND
:
4787 case BRW_OPCODE_XOR
:
4788 case BRW_OPCODE_SHR
:
4789 case BRW_OPCODE_SHL
:
4790 case BRW_OPCODE_ASR
:
4791 case BRW_OPCODE_CMPN
:
4792 case BRW_OPCODE_CSEL
:
4793 case BRW_OPCODE_F32TO16
:
4794 case BRW_OPCODE_F16TO32
:
4795 case BRW_OPCODE_BFREV
:
4796 case BRW_OPCODE_BFE
:
4797 case BRW_OPCODE_ADD
:
4798 case BRW_OPCODE_MUL
:
4799 case BRW_OPCODE_AVG
:
4800 case BRW_OPCODE_FRC
:
4801 case BRW_OPCODE_RNDU
:
4802 case BRW_OPCODE_RNDD
:
4803 case BRW_OPCODE_RNDE
:
4804 case BRW_OPCODE_RNDZ
:
4805 case BRW_OPCODE_LZD
:
4806 case BRW_OPCODE_FBH
:
4807 case BRW_OPCODE_FBL
:
4808 case BRW_OPCODE_CBIT
:
4809 case BRW_OPCODE_SAD2
:
4810 case BRW_OPCODE_MAD
:
4811 case BRW_OPCODE_LRP
:
4812 case FS_OPCODE_PACK
:
4813 return get_fpu_lowered_simd_width(devinfo
, inst
);
4815 case BRW_OPCODE_CMP
: {
4816 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4817 * when the destination is a GRF the dependency-clear bit on the flag
4818 * register is cleared early.
4820 * Suggested workarounds are to disable coissuing CMP instructions
4821 * or to split CMP(16) instructions into two CMP(8) instructions.
4823 * We choose to split into CMP(8) instructions since disabling
4824 * coissuing would affect CMP instructions not otherwise affected by
4827 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4828 !inst
->dst
.is_null() ? 8 : ~0);
4829 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4831 case BRW_OPCODE_BFI1
:
4832 case BRW_OPCODE_BFI2
:
4833 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4835 * "Force BFI instructions to be executed always in SIMD8."
4837 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4838 get_fpu_lowered_simd_width(devinfo
, inst
));
4841 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4842 return inst
->exec_size
;
4844 case SHADER_OPCODE_RCP
:
4845 case SHADER_OPCODE_RSQ
:
4846 case SHADER_OPCODE_SQRT
:
4847 case SHADER_OPCODE_EXP2
:
4848 case SHADER_OPCODE_LOG2
:
4849 case SHADER_OPCODE_SIN
:
4850 case SHADER_OPCODE_COS
:
4851 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4854 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4855 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4856 MIN2(8, inst
->exec_size
));
4858 case SHADER_OPCODE_POW
:
4859 /* SIMD16 is only allowed on Gen7+. */
4860 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4861 MIN2(8, inst
->exec_size
));
4863 case SHADER_OPCODE_INT_QUOTIENT
:
4864 case SHADER_OPCODE_INT_REMAINDER
:
4865 /* Integer division is limited to SIMD8 on all generations. */
4866 return MIN2(8, inst
->exec_size
);
4868 case FS_OPCODE_LINTERP
:
4869 case FS_OPCODE_GET_BUFFER_SIZE
:
4870 case FS_OPCODE_DDX_COARSE
:
4871 case FS_OPCODE_DDX_FINE
:
4872 case FS_OPCODE_DDY_COARSE
:
4873 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4874 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4875 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4876 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4877 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4878 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4879 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4880 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4881 return MIN2(16, inst
->exec_size
);
4883 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4884 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4885 * message used to implement varying pull constant loads, so expand it
4886 * to SIMD16. An alternative with longer message payload length but
4887 * shorter return payload would be to use the SIMD8 sampler message that
4888 * takes (header, u, v, r) as parameters instead of (header, u).
4890 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4892 case FS_OPCODE_DDY_FINE
:
4893 /* The implementation of this virtual opcode may require emitting
4894 * compressed Align16 instructions, which are severely limited on some
4897 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4898 * Region Restrictions):
4900 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4901 * and SIMD8 is not allowed for DF operations."
4903 * In this context, "DW operations" means "operations acting on 32-bit
4904 * values", so it includes operations on floats.
4906 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4907 * (Instruction Compression -> Rules and Restrictions):
4909 * "A compressed instruction must be in Align1 access mode. Align16
4910 * mode instructions cannot be compressed."
4912 * Similar text exists in the g45 PRM.
4914 * Empirically, compressed align16 instructions using odd register
4915 * numbers don't appear to work on Sandybridge either.
4917 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4918 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4919 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4921 case SHADER_OPCODE_MULH
:
4922 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4923 * is 8-wide on Gen7+.
4925 return (devinfo
->gen
>= 7 ? 8 :
4926 get_fpu_lowered_simd_width(devinfo
, inst
));
4928 case FS_OPCODE_FB_WRITE_LOGICAL
:
4929 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4932 assert(devinfo
->gen
!= 6 ||
4933 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4934 inst
->exec_size
== 8);
4935 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4936 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4937 8 : MIN2(16, inst
->exec_size
));
4939 case FS_OPCODE_FB_READ_LOGICAL
:
4940 return MIN2(16, inst
->exec_size
);
4942 case SHADER_OPCODE_TEX_LOGICAL
:
4943 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4944 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4945 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4946 case SHADER_OPCODE_LOD_LOGICAL
:
4947 case SHADER_OPCODE_TG4_LOGICAL
:
4948 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4949 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4950 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4951 return get_sampler_lowered_simd_width(devinfo
, inst
);
4953 case SHADER_OPCODE_TXD_LOGICAL
:
4954 /* TXD is unsupported in SIMD16 mode. */
4957 case SHADER_OPCODE_TXL_LOGICAL
:
4958 case FS_OPCODE_TXB_LOGICAL
:
4959 /* Only one execution size is representable pre-ILK depending on whether
4960 * the shadow reference argument is present.
4962 if (devinfo
->gen
== 4)
4963 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4965 return get_sampler_lowered_simd_width(devinfo
, inst
);
4967 case SHADER_OPCODE_TXF_LOGICAL
:
4968 case SHADER_OPCODE_TXS_LOGICAL
:
4969 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4970 * messages. Use SIMD16 instead.
4972 if (devinfo
->gen
== 4)
4975 return get_sampler_lowered_simd_width(devinfo
, inst
);
4977 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4978 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4979 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4982 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4983 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4984 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4985 return MIN2(16, inst
->exec_size
);
4987 case SHADER_OPCODE_URB_READ_SIMD8
:
4988 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4989 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4990 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4991 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4992 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4993 return MIN2(8, inst
->exec_size
);
4995 case SHADER_OPCODE_MOV_INDIRECT
: {
4996 /* From IVB and HSW PRMs:
4998 * "2.When the destination requires two registers and the sources are
4999 * indirect, the sources must use 1x1 regioning mode.
5001 * In case of DF instructions in HSW/IVB, the exec_size is limited by
5002 * the EU decompression logic not handling VxH indirect addressing
5005 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
5006 /* Prior to Broadwell, we only have 8 address subregisters. */
5007 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
5008 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
5012 case SHADER_OPCODE_LOAD_PAYLOAD
: {
5013 const unsigned reg_count
=
5014 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5016 if (reg_count
> 2) {
5017 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5018 * can be easily lowered (which excludes headers and heterogeneous
5021 assert(!inst
->header_size
);
5022 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5023 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5024 inst
->src
[i
].file
== BAD_FILE
);
5026 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5028 return inst
->exec_size
;
5032 return inst
->exec_size
;
5037 * Return true if splitting out the group of channels of instruction \p inst
5038 * given by lbld.group() requires allocating a temporary for the i-th source
5039 * of the lowered instruction.
5042 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5044 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5045 (inst
->components_read(i
) == 1 &&
5046 lbld
.dispatch_width() <= inst
->exec_size
)) ||
5047 (inst
->flags_written() &
5048 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
5052 * Extract the data that would be consumed by the channel group given by
5053 * lbld.group() from the i-th source region of instruction \p inst and return
5054 * it as result in packed form.
5057 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
5059 /* Specified channel group from the source region. */
5060 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5062 if (needs_src_copy(lbld
, inst
, i
)) {
5063 /* Builder of the right width to perform the copy avoiding uninitialized
5064 * data if the lowered execution size is greater than the original
5065 * execution size of the instruction.
5067 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5068 inst
->exec_size
), 0);
5069 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5071 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5072 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5076 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5077 /* The source is invariant for all dispatch_width-wide groups of the
5080 return inst
->src
[i
];
5083 /* We can just point the lowered instruction at the right channel group
5084 * from the original region.
5091 * Return true if splitting out the group of channels of instruction \p inst
5092 * given by lbld.group() requires allocating a temporary for the destination
5093 * of the lowered instruction and copying the data back to the original
5094 * destination region.
5097 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5099 /* If the instruction writes more than one component we'll have to shuffle
5100 * the results of multiple lowered instructions in order to make sure that
5101 * they end up arranged correctly in the original destination region.
5103 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5106 /* If the lowered execution size is larger than the original the result of
5107 * the instruction won't fit in the original destination, so we'll have to
5108 * allocate a temporary in any case.
5110 if (lbld
.dispatch_width() > inst
->exec_size
)
5113 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5114 /* If we already made a copy of the source for other reasons there won't
5115 * be any overlap with the destination.
5117 if (needs_src_copy(lbld
, inst
, i
))
5120 /* In order to keep the logic simple we emit a copy whenever the
5121 * destination region doesn't exactly match an overlapping source, which
5122 * may point at the source and destination not being aligned group by
5123 * group which could cause one of the lowered instructions to overwrite
5124 * the data read from the same source by other lowered instructions.
5126 if (regions_overlap(inst
->dst
, inst
->size_written
,
5127 inst
->src
[i
], inst
->size_read(i
)) &&
5128 !inst
->dst
.equals(inst
->src
[i
]))
5136 * Insert data from a packed temporary into the channel group given by
5137 * lbld.group() of the destination region of instruction \p inst and return
5138 * the temporary as result. Any copy instructions that are required for
5139 * unzipping the previous value (in the case of partial writes) will be
5140 * inserted using \p lbld_before and any copy instructions required for
5141 * zipping up the destination of \p inst will be inserted using \p lbld_after.
5144 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
5147 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
5148 assert(lbld_before
.group() == lbld_after
.group());
5150 /* Specified channel group from the destination region. */
5151 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group());
5152 const unsigned dst_size
= inst
->size_written
/
5153 inst
->dst
.component_size(inst
->exec_size
);
5155 if (needs_dst_copy(lbld_after
, inst
)) {
5156 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
5158 if (inst
->predicate
) {
5159 /* Handle predication by copying the original contents of
5160 * the destination into the temporary before emitting the
5161 * lowered instruction.
5163 const fs_builder gbld_before
=
5164 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
5165 inst
->exec_size
), 0);
5166 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5167 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
5168 offset(dst
, inst
->exec_size
, k
));
5172 const fs_builder gbld_after
=
5173 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
5174 inst
->exec_size
), 0);
5175 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5176 /* Use a builder of the right width to perform the copy avoiding
5177 * uninitialized data if the lowered execution size is greater than
5178 * the original execution size of the instruction.
5180 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
5181 offset(tmp
, lbld_after
, k
));
5187 /* No need to allocate a temporary for the lowered instruction, just
5188 * take the right group of channels from the original region.
5195 fs_visitor::lower_simd_width()
5197 bool progress
= false;
5199 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5200 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5202 if (lower_width
!= inst
->exec_size
) {
5203 /* Builder matching the original instruction. We may also need to
5204 * emit an instruction of width larger than the original, set the
5205 * execution size of the builder to the highest of both for now so
5206 * we're sure that both cases can be handled.
5208 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5209 const fs_builder ibld
= bld
.at(block
, inst
)
5210 .exec_all(inst
->force_writemask_all
)
5211 .group(max_width
, inst
->group
/ max_width
);
5213 /* Split the copies in chunks of the execution width of either the
5214 * original or the lowered instruction, whichever is lower.
5216 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5217 const unsigned dst_size
= inst
->size_written
/
5218 inst
->dst
.component_size(inst
->exec_size
);
5220 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5222 /* Inserting the zip, unzip, and duplicated instructions in all of
5223 * the right spots is somewhat tricky. All of the unzip and any
5224 * instructions from the zip which unzip the destination prior to
5225 * writing need to happen before all of the per-group instructions
5226 * and the zip instructions need to happen after. In order to sort
5227 * this all out, we insert the unzip instructions before \p inst,
5228 * insert the per-group instructions after \p inst (i.e. before
5229 * inst->next), and insert the zip instructions before the
5230 * instruction after \p inst. Since we are inserting instructions
5231 * after \p inst, inst->next is a moving target and we need to save
5232 * it off here so that we insert the zip instructions in the right
5235 exec_node
*const after_inst
= inst
->next
;
5236 for (unsigned i
= 0; i
< n
; i
++) {
5237 /* Emit a copy of the original instruction with the lowered width.
5238 * If the EOT flag was set throw it away except for the last
5239 * instruction to avoid killing the thread prematurely.
5241 fs_inst split_inst
= *inst
;
5242 split_inst
.exec_size
= lower_width
;
5243 split_inst
.eot
= inst
->eot
&& i
== 0;
5245 /* Select the correct channel enables for the i-th group, then
5246 * transform the sources and destination and emit the lowered
5249 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5251 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5252 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
5254 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
5255 lbld
.at(block
, after_inst
), inst
);
5256 split_inst
.size_written
=
5257 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5259 lbld
.at(block
, inst
->next
).emit(split_inst
);
5262 inst
->remove(block
);
5268 invalidate_live_intervals();
5274 fs_visitor::dump_instructions()
5276 dump_instructions(NULL
);
5280 fs_visitor::dump_instructions(const char *name
)
5282 FILE *file
= stderr
;
5283 if (name
&& geteuid() != 0) {
5284 file
= fopen(name
, "w");
5290 calculate_register_pressure();
5291 int ip
= 0, max_pressure
= 0;
5292 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5293 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5294 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5295 dump_instruction(inst
, file
);
5298 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5301 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5302 fprintf(file
, "%4d: ", ip
++);
5303 dump_instruction(inst
, file
);
5307 if (file
!= stderr
) {
5313 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5315 dump_instruction(be_inst
, stderr
);
5319 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5321 fs_inst
*inst
= (fs_inst
*)be_inst
;
5323 if (inst
->predicate
) {
5324 fprintf(file
, "(%cf0.%d) ",
5325 inst
->predicate_inverse
? '-' : '+',
5329 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5331 fprintf(file
, ".sat");
5332 if (inst
->conditional_mod
) {
5333 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5334 if (!inst
->predicate
&&
5335 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5336 inst
->opcode
!= BRW_OPCODE_IF
&&
5337 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5338 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5341 fprintf(file
, "(%d) ", inst
->exec_size
);
5344 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5348 fprintf(file
, "(EOT) ");
5351 switch (inst
->dst
.file
) {
5353 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5356 fprintf(file
, "g%d", inst
->dst
.nr
);
5359 fprintf(file
, "m%d", inst
->dst
.nr
);
5362 fprintf(file
, "(null)");
5365 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5368 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5371 switch (inst
->dst
.nr
) {
5373 fprintf(file
, "null");
5375 case BRW_ARF_ADDRESS
:
5376 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5378 case BRW_ARF_ACCUMULATOR
:
5379 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5382 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5385 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5390 unreachable("not reached");
5393 if (inst
->dst
.offset
||
5394 (inst
->dst
.file
== VGRF
&&
5395 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5396 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5397 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5398 inst
->dst
.offset
% reg_size
);
5401 if (inst
->dst
.stride
!= 1)
5402 fprintf(file
, "<%u>", inst
->dst
.stride
);
5403 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
5405 for (int i
= 0; i
< inst
->sources
; i
++) {
5406 if (inst
->src
[i
].negate
)
5408 if (inst
->src
[i
].abs
)
5410 switch (inst
->src
[i
].file
) {
5412 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5415 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5418 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5421 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5424 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5427 fprintf(file
, "(null)");
5430 switch (inst
->src
[i
].type
) {
5431 case BRW_REGISTER_TYPE_F
:
5432 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5434 case BRW_REGISTER_TYPE_DF
:
5435 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5437 case BRW_REGISTER_TYPE_W
:
5438 case BRW_REGISTER_TYPE_D
:
5439 fprintf(file
, "%dd", inst
->src
[i
].d
);
5441 case BRW_REGISTER_TYPE_UW
:
5442 case BRW_REGISTER_TYPE_UD
:
5443 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5445 case BRW_REGISTER_TYPE_VF
:
5446 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5447 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5448 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5449 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5450 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5453 fprintf(file
, "???");
5458 switch (inst
->src
[i
].nr
) {
5460 fprintf(file
, "null");
5462 case BRW_ARF_ADDRESS
:
5463 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5465 case BRW_ARF_ACCUMULATOR
:
5466 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5469 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5472 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5478 if (inst
->src
[i
].offset
||
5479 (inst
->src
[i
].file
== VGRF
&&
5480 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5481 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5482 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5483 inst
->src
[i
].offset
% reg_size
);
5486 if (inst
->src
[i
].abs
)
5489 if (inst
->src
[i
].file
!= IMM
) {
5491 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5492 unsigned hstride
= inst
->src
[i
].hstride
;
5493 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5495 stride
= inst
->src
[i
].stride
;
5498 fprintf(file
, "<%u>", stride
);
5500 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
5503 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5504 fprintf(file
, ", ");
5509 if (inst
->force_writemask_all
)
5510 fprintf(file
, "NoMask ");
5512 if (inst
->exec_size
!= dispatch_width
)
5513 fprintf(file
, "group%d ", inst
->group
);
5515 fprintf(file
, "\n");
5519 * Possibly returns an instruction that set up @param reg.
5521 * Sometimes we want to take the result of some expression/variable
5522 * dereference tree and rewrite the instruction generating the result
5523 * of the tree. When processing the tree, we know that the
5524 * instructions generated are all writing temporaries that are dead
5525 * outside of this tree. So, if we have some instructions that write
5526 * a temporary, we're free to point that temp write somewhere else.
5528 * Note that this doesn't guarantee that the instruction generated
5529 * only reg -- it might be the size=4 destination of a texture instruction.
5532 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5537 end
->is_partial_write() ||
5538 !reg
.equals(end
->dst
)) {
5546 fs_visitor::setup_fs_payload_gen6()
5548 assert(stage
== MESA_SHADER_FRAGMENT
);
5549 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
5551 assert(devinfo
->gen
>= 6);
5553 /* R0-1: masks, pixel X/Y coordinates. */
5554 payload
.num_regs
= 2;
5555 /* R2: only for 32-pixel dispatch.*/
5557 /* R3-26: barycentric interpolation coordinates. These appear in the
5558 * same order that they appear in the brw_barycentric_mode
5559 * enum. Each set of coordinates occupies 2 registers if dispatch width
5560 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5561 * appear if they were enabled using the "Barycentric Interpolation
5562 * Mode" bits in WM_STATE.
5564 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5565 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
5566 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5567 payload
.num_regs
+= 2;
5568 if (dispatch_width
== 16) {
5569 payload
.num_regs
+= 2;
5574 /* R27: interpolated depth if uses source depth */
5575 prog_data
->uses_src_depth
=
5576 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5577 if (prog_data
->uses_src_depth
) {
5578 payload
.source_depth_reg
= payload
.num_regs
;
5580 if (dispatch_width
== 16) {
5581 /* R28: interpolated depth if not SIMD8. */
5586 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5587 prog_data
->uses_src_w
=
5588 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5589 if (prog_data
->uses_src_w
) {
5590 payload
.source_w_reg
= payload
.num_regs
;
5592 if (dispatch_width
== 16) {
5593 /* R30: interpolated W if not SIMD8. */
5598 /* R31: MSAA position offsets. */
5599 if (prog_data
->persample_dispatch
&&
5600 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5601 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5603 * "MSDISPMODE_PERSAMPLE is required in order to select
5606 * So we can only really get sample positions if we are doing real
5607 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5608 * persample dispatch, we hard-code it to 0.5.
5610 prog_data
->uses_pos_offset
= true;
5611 payload
.sample_pos_reg
= payload
.num_regs
;
5615 /* R32: MSAA input coverage mask */
5616 prog_data
->uses_sample_mask
=
5617 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5618 if (prog_data
->uses_sample_mask
) {
5619 assert(devinfo
->gen
>= 7);
5620 payload
.sample_mask_in_reg
= payload
.num_regs
;
5622 if (dispatch_width
== 16) {
5623 /* R33: input coverage mask if not SIMD8. */
5628 /* R34-: bary for 32-pixel. */
5629 /* R58-59: interp W for 32-pixel. */
5631 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5632 source_depth_to_render_target
= true;
5637 fs_visitor::setup_vs_payload()
5639 /* R0: thread header, R1: urb handles */
5640 payload
.num_regs
= 2;
5644 fs_visitor::setup_gs_payload()
5646 assert(stage
== MESA_SHADER_GEOMETRY
);
5648 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
5649 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
5651 /* R0: thread header, R1: output URB handles */
5652 payload
.num_regs
= 2;
5654 if (gs_prog_data
->include_primitive_id
) {
5655 /* R2: Primitive ID 0..7 */
5659 /* Always enable VUE handles so we can safely use pull model if needed.
5661 * The push model for a GS uses a ton of register space even for trivial
5662 * scenarios with just a few inputs, so just make things easier and a bit
5663 * safer by always having pull model available.
5665 gs_prog_data
->base
.include_vue_handles
= true;
5667 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5668 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5670 /* Use a maximum of 24 registers for push-model inputs. */
5671 const unsigned max_push_components
= 24;
5673 /* If pushing our inputs would take too many registers, reduce the URB read
5674 * length (which is in HWords, or 8 registers), and resort to pulling.
5676 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5677 * have to multiply by VerticesIn to obtain the total storage requirement.
5679 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5680 max_push_components
) {
5681 vue_prog_data
->urb_read_length
=
5682 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5687 fs_visitor::setup_cs_payload()
5689 assert(devinfo
->gen
>= 7);
5690 payload
.num_regs
= 1;
5694 fs_visitor::calculate_register_pressure()
5696 invalidate_live_intervals();
5697 calculate_live_intervals();
5699 unsigned num_instructions
= 0;
5700 foreach_block(block
, cfg
)
5701 num_instructions
+= block
->instructions
.length();
5703 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5705 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5706 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5707 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5712 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5714 * The needs_unlit_centroid_workaround ends up producing one of these per
5715 * channel of centroid input, so it's good to clean them up.
5717 * An assumption here is that nothing ever modifies the dispatched pixels
5718 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5719 * dictates that anyway.
5722 fs_visitor::opt_drop_redundant_mov_to_flags()
5724 bool flag_mov_found
[2] = {false};
5725 bool progress
= false;
5727 /* Instructions removed by this pass can only be added if this were true */
5728 if (!devinfo
->needs_unlit_centroid_workaround
)
5731 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5732 if (inst
->is_control_flow()) {
5733 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5734 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5735 if (!flag_mov_found
[inst
->flag_subreg
]) {
5736 flag_mov_found
[inst
->flag_subreg
] = true;
5738 inst
->remove(block
);
5741 } else if (inst
->flags_written()) {
5742 flag_mov_found
[inst
->flag_subreg
] = false;
5750 fs_visitor::optimize()
5752 /* Start by validating the shader we currently have. */
5755 /* bld is the common builder object pointing at the end of the program we
5756 * used to translate it into i965 IR. For the optimization and lowering
5757 * passes coming next, any code added after the end of the program without
5758 * having explicitly called fs_builder::at() clearly points at a mistake.
5759 * Ideally optimization passes wouldn't be part of the visitor so they
5760 * wouldn't have access to bld at all, but they do, so just in case some
5761 * pass forgets to ask for a location explicitly set it to NULL here to
5762 * make it trip. The dispatch width is initialized to a bogus value to
5763 * make sure that optimizations set the execution controls explicitly to
5764 * match the code they are manipulating instead of relying on the defaults.
5766 bld
= fs_builder(this, 64);
5768 assign_constant_locations();
5769 lower_constant_loads();
5773 split_virtual_grfs();
5776 #define OPT(pass, args...) ({ \
5778 bool this_progress = pass(args); \
5780 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5781 char filename[64]; \
5782 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5783 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5785 backend_shader::dump_instructions(filename); \
5790 progress = progress || this_progress; \
5794 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5796 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5797 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5799 backend_shader::dump_instructions(filename
);
5802 bool progress
= false;
5806 OPT(opt_drop_redundant_mov_to_flags
);
5813 OPT(remove_duplicate_mrf_writes
);
5817 OPT(opt_copy_propagation
);
5818 OPT(opt_predicated_break
, this);
5819 OPT(opt_cmod_propagation
);
5820 OPT(dead_code_eliminate
);
5821 OPT(opt_peephole_sel
);
5822 OPT(dead_control_flow_eliminate
, this);
5823 OPT(opt_register_renaming
);
5824 OPT(opt_saturate_propagation
);
5825 OPT(register_coalesce
);
5826 OPT(compute_to_mrf
);
5827 OPT(eliminate_find_live_channel
);
5829 OPT(compact_virtual_grfs
);
5835 if (OPT(lower_pack
)) {
5836 OPT(register_coalesce
);
5837 OPT(dead_code_eliminate
);
5840 OPT(lower_simd_width
);
5842 /* After SIMD lowering just in case we had to unroll the EOT send. */
5843 OPT(opt_sampler_eot
);
5845 OPT(lower_logical_sends
);
5848 OPT(opt_copy_propagation
);
5849 /* Only run after logical send lowering because it's easier to implement
5850 * in terms of physical sends.
5852 if (OPT(opt_zero_samples
))
5853 OPT(opt_copy_propagation
);
5854 /* Run after logical send lowering to give it a chance to CSE the
5855 * LOAD_PAYLOAD instructions created to construct the payloads of
5856 * e.g. texturing messages in cases where it wasn't possible to CSE the
5857 * whole logical instruction.
5860 OPT(register_coalesce
);
5861 OPT(compute_to_mrf
);
5862 OPT(dead_code_eliminate
);
5863 OPT(remove_duplicate_mrf_writes
);
5864 OPT(opt_peephole_sel
);
5867 OPT(opt_redundant_discard_jumps
);
5869 if (OPT(lower_load_payload
)) {
5870 split_virtual_grfs();
5871 OPT(register_coalesce
);
5872 OPT(compute_to_mrf
);
5873 OPT(dead_code_eliminate
);
5876 OPT(opt_combine_constants
);
5877 OPT(lower_integer_multiplication
);
5879 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5880 OPT(opt_cmod_propagation
);
5882 OPT(opt_copy_propagation
);
5883 OPT(dead_code_eliminate
);
5886 if (OPT(lower_conversions
)) {
5887 OPT(opt_copy_propagation
);
5888 OPT(dead_code_eliminate
);
5889 OPT(lower_simd_width
);
5892 lower_uniform_pull_constant_loads();
5898 * Three source instruction must have a GRF/MRF destination register.
5899 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5902 fs_visitor::fixup_3src_null_dest()
5904 bool progress
= false;
5906 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5907 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5908 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5915 invalidate_live_intervals();
5919 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
5921 bool allocated_without_spills
;
5923 static const enum instruction_scheduler_mode pre_modes
[] = {
5925 SCHEDULE_PRE_NON_LIFO
,
5929 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5931 /* Try each scheduling heuristic to see if it can successfully register
5932 * allocate without spilling. They should be ordered by decreasing
5933 * performance but increasing likelihood of allocating.
5935 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5936 schedule_instructions(pre_modes
[i
]);
5939 assign_regs_trivial();
5940 allocated_without_spills
= true;
5942 allocated_without_spills
= assign_regs(false, spill_all
);
5944 if (allocated_without_spills
)
5948 if (!allocated_without_spills
) {
5949 if (!allow_spilling
)
5950 fail("Failure to register allocate and spilling is not allowed.");
5952 /* We assume that any spilling is worse than just dropping back to
5953 * SIMD8. There's probably actually some intermediate point where
5954 * SIMD16 with a couple of spills is still better.
5956 if (dispatch_width
> min_dispatch_width
) {
5957 fail("Failure to register allocate. Reduce number of "
5958 "live scalar values to avoid this.");
5960 compiler
->shader_perf_log(log_data
,
5961 "%s shader triggered register spilling. "
5962 "Try reducing the number of live scalar "
5963 "values to improve performance.\n",
5967 /* Since we're out of heuristics, just go spill registers until we
5968 * get an allocation.
5970 while (!assign_regs(true, spill_all
)) {
5976 /* This must come after all optimization and register allocation, since
5977 * it inserts dead code that happens to have side effects, and it does
5978 * so based on the actual physical registers in use.
5980 insert_gen4_send_dependency_workarounds();
5985 schedule_instructions(SCHEDULE_POST
);
5987 if (last_scratch
> 0) {
5988 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
5990 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5992 if (stage
== MESA_SHADER_COMPUTE
) {
5993 if (devinfo
->is_haswell
) {
5994 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5995 * field documentation, Haswell supports a minimum of 2kB of
5996 * scratch space for compute shaders, unlike every other stage
5999 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
6000 } else if (devinfo
->gen
<= 7) {
6001 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
6002 * field documentation, platforms prior to Haswell measure scratch
6003 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
6005 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
6006 max_scratch_size
= 12 * 1024;
6010 /* We currently only support up to 2MB of scratch space. If we
6011 * need to support more eventually, the documentation suggests
6012 * that we could allocate a larger buffer, and partition it out
6013 * ourselves. We'd just have to undo the hardware's address
6014 * calculation by subtracting (FFTID * Per Thread Scratch Space)
6015 * and then add FFTID * (Larger Per Thread Scratch Space).
6017 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
6018 * Thread Group Tracking > Local Memory/Scratch Space.
6020 assert(prog_data
->total_scratch
< max_scratch_size
);
6025 fs_visitor::run_vs()
6027 assert(stage
== MESA_SHADER_VERTEX
);
6031 if (shader_time_index
>= 0)
6032 emit_shader_time_begin();
6039 compute_clip_distance();
6043 if (shader_time_index
>= 0)
6044 emit_shader_time_end();
6050 assign_curb_setup();
6051 assign_vs_urb_setup();
6053 fixup_3src_null_dest();
6054 allocate_registers(8, true);
6060 fs_visitor::run_tcs_single_patch()
6062 assert(stage
== MESA_SHADER_TESS_CTRL
);
6064 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
6066 /* r1-r4 contain the ICP handles. */
6067 payload
.num_regs
= 5;
6069 if (shader_time_index
>= 0)
6070 emit_shader_time_begin();
6072 /* Initialize gl_InvocationID */
6073 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6074 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6075 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6076 bld
.MOV(channels_ud
, channels_uw
);
6078 if (tcs_prog_data
->instances
== 1) {
6079 invocation_id
= channels_ud
;
6081 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6083 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6084 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6085 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6086 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6087 brw_imm_ud(INTEL_MASK(23, 17)));
6088 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6090 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6093 /* Fix the disptach mask */
6094 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6095 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6096 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
6097 bld
.IF(BRW_PREDICATE_NORMAL
);
6102 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6103 bld
.emit(BRW_OPCODE_ENDIF
);
6106 /* Emit EOT write; set TR DS Cache bit */
6108 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6109 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6110 fs_reg(brw_imm_ud(0)),
6112 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6113 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6115 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6116 bld
.null_reg_ud(), payload
);
6120 if (shader_time_index
>= 0)
6121 emit_shader_time_end();
6130 assign_curb_setup();
6131 assign_tcs_single_patch_urb_setup();
6133 fixup_3src_null_dest();
6134 allocate_registers(8, true);
6140 fs_visitor::run_tes()
6142 assert(stage
== MESA_SHADER_TESS_EVAL
);
6144 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6145 payload
.num_regs
= 5;
6147 if (shader_time_index
>= 0)
6148 emit_shader_time_begin();
6157 if (shader_time_index
>= 0)
6158 emit_shader_time_end();
6164 assign_curb_setup();
6165 assign_tes_urb_setup();
6167 fixup_3src_null_dest();
6168 allocate_registers(8, true);
6174 fs_visitor::run_gs()
6176 assert(stage
== MESA_SHADER_GEOMETRY
);
6180 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6182 if (gs_compile
->control_data_header_size_bits
> 0) {
6183 /* Create a VGRF to store accumulated control data bits. */
6184 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6186 /* If we're outputting more than 32 control data bits, then EmitVertex()
6187 * will set control_data_bits to 0 after emitting the first vertex.
6188 * Otherwise, we need to initialize it to 0 here.
6190 if (gs_compile
->control_data_header_size_bits
<= 32) {
6191 const fs_builder abld
= bld
.annotate("initialize control data bits");
6192 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6196 if (shader_time_index
>= 0)
6197 emit_shader_time_begin();
6201 emit_gs_thread_end();
6203 if (shader_time_index
>= 0)
6204 emit_shader_time_end();
6213 assign_curb_setup();
6214 assign_gs_urb_setup();
6216 fixup_3src_null_dest();
6217 allocate_registers(8, true);
6222 /* From the SKL PRM, Volume 16, Workarounds:
6224 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
6225 * only header phases (R0-R2)
6227 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
6228 * have been header only.
6230 * Instead of enabling push constants one can alternatively enable one of the
6231 * inputs. Here one simply chooses "layer" which shouldn't impose much
6235 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
6237 if (wm_prog_data
->num_varying_inputs
)
6240 if (wm_prog_data
->base
.curb_read_length
)
6243 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
6244 wm_prog_data
->num_varying_inputs
= 1;
6248 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6250 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6251 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6253 assert(stage
== MESA_SHADER_FRAGMENT
);
6255 if (devinfo
->gen
>= 6)
6256 setup_fs_payload_gen6();
6258 setup_fs_payload_gen4();
6262 } else if (do_rep_send
) {
6263 assert(dispatch_width
== 16);
6264 emit_repclear_shader();
6266 if (shader_time_index
>= 0)
6267 emit_shader_time_begin();
6269 calculate_urb_setup();
6270 if (nir
->info
.inputs_read
> 0 ||
6271 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6272 if (devinfo
->gen
< 6)
6273 emit_interpolation_setup_gen4();
6275 emit_interpolation_setup_gen6();
6278 /* We handle discards by keeping track of the still-live pixels in f0.1.
6279 * Initialize it with the dispatched pixels.
6281 if (wm_prog_data
->uses_kill
) {
6282 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6283 discard_init
->flag_subreg
= 1;
6286 /* Generate FS IR for main(). (the visitor only descends into
6287 * functions called "main").
6294 if (wm_prog_data
->uses_kill
)
6295 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6297 if (wm_key
->alpha_test_func
)
6302 if (shader_time_index
>= 0)
6303 emit_shader_time_end();
6309 assign_curb_setup();
6311 if (devinfo
->gen
>= 9)
6312 gen9_ps_header_only_workaround(wm_prog_data
);
6316 fixup_3src_null_dest();
6317 allocate_registers(8, allow_spilling
);
6327 fs_visitor::run_cs(unsigned min_dispatch_width
)
6329 assert(stage
== MESA_SHADER_COMPUTE
);
6330 assert(dispatch_width
>= min_dispatch_width
);
6334 if (shader_time_index
>= 0)
6335 emit_shader_time_begin();
6337 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6338 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6339 const fs_builder abld
= bld
.exec_all().group(1, 0);
6340 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6341 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6349 emit_cs_terminate();
6351 if (shader_time_index
>= 0)
6352 emit_shader_time_end();
6358 assign_curb_setup();
6360 fixup_3src_null_dest();
6361 allocate_registers(min_dispatch_width
, true);
6370 * Return a bitfield where bit n is set if barycentric interpolation mode n
6371 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6373 * We examine the load_barycentric intrinsics rather than looking at input
6374 * variables so that we catch interpolateAtCentroid() messages too, which
6375 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6378 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6379 const nir_shader
*shader
)
6381 unsigned barycentric_interp_modes
= 0;
6383 nir_foreach_function(f
, shader
) {
6387 nir_foreach_block(block
, f
->impl
) {
6388 nir_foreach_instr(instr
, block
) {
6389 if (instr
->type
!= nir_instr_type_intrinsic
)
6392 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6393 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6396 /* Ignore WPOS; it doesn't require interpolation. */
6397 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6400 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6401 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6402 nir_intrinsic_interp_mode(intrin
);
6403 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6404 enum brw_barycentric_mode bary
=
6405 brw_barycentric_mode(interp
, bary_op
);
6407 barycentric_interp_modes
|= 1 << bary
;
6409 if (devinfo
->needs_unlit_centroid_workaround
&&
6410 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6411 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6416 return barycentric_interp_modes
;
6420 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6421 const nir_shader
*shader
)
6423 prog_data
->flat_inputs
= 0;
6425 nir_foreach_variable(var
, &shader
->inputs
) {
6426 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6428 if (input_index
< 0)
6432 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6433 prog_data
->flat_inputs
|= (1 << input_index
);
6438 computed_depth_mode(const nir_shader
*shader
)
6440 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6441 switch (shader
->info
.fs
.depth_layout
) {
6442 case FRAG_DEPTH_LAYOUT_NONE
:
6443 case FRAG_DEPTH_LAYOUT_ANY
:
6444 return BRW_PSCDEPTH_ON
;
6445 case FRAG_DEPTH_LAYOUT_GREATER
:
6446 return BRW_PSCDEPTH_ON_GE
;
6447 case FRAG_DEPTH_LAYOUT_LESS
:
6448 return BRW_PSCDEPTH_ON_LE
;
6449 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6450 return BRW_PSCDEPTH_OFF
;
6453 return BRW_PSCDEPTH_OFF
;
6457 * Move load_interpolated_input with simple (payload-based) barycentric modes
6458 * to the top of the program so we don't emit multiple PLNs for the same input.
6460 * This works around CSE not being able to handle non-dominating cases
6466 * interpolate the same exact input
6469 * This should be replaced by global value numbering someday.
6472 move_interpolation_to_top(nir_shader
*nir
)
6474 bool progress
= false;
6476 nir_foreach_function(f
, nir
) {
6480 nir_block
*top
= nir_start_block(f
->impl
);
6481 exec_node
*cursor_node
= NULL
;
6483 nir_foreach_block(block
, f
->impl
) {
6487 nir_foreach_instr_safe(instr
, block
) {
6488 if (instr
->type
!= nir_instr_type_intrinsic
)
6491 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6492 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6494 nir_intrinsic_instr
*bary_intrinsic
=
6495 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6496 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6498 /* Leave interpolateAtSample/Offset() where they are. */
6499 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6500 op
== nir_intrinsic_load_barycentric_at_offset
)
6503 nir_instr
*move
[3] = {
6504 &bary_intrinsic
->instr
,
6505 intrin
->src
[1].ssa
->parent_instr
,
6509 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6510 if (move
[i
]->block
!= top
) {
6511 move
[i
]->block
= top
;
6512 exec_node_remove(&move
[i
]->node
);
6514 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6516 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6518 cursor_node
= &move
[i
]->node
;
6524 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6525 ((unsigned) nir_metadata_block_index
|
6526 (unsigned) nir_metadata_dominance
));
6533 * Demote per-sample barycentric intrinsics to centroid.
6535 * Useful when rendering to a non-multisampled buffer.
6538 demote_sample_qualifiers(nir_shader
*nir
)
6540 bool progress
= true;
6542 nir_foreach_function(f
, nir
) {
6547 nir_builder_init(&b
, f
->impl
);
6549 nir_foreach_block(block
, f
->impl
) {
6550 nir_foreach_instr_safe(instr
, block
) {
6551 if (instr
->type
!= nir_instr_type_intrinsic
)
6554 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6555 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6556 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6559 b
.cursor
= nir_before_instr(instr
);
6560 nir_ssa_def
*centroid
=
6561 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6562 nir_intrinsic_interp_mode(intrin
));
6563 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6564 nir_src_for_ssa(centroid
));
6565 nir_instr_remove(instr
);
6570 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6571 ((unsigned) nir_metadata_block_index
|
6572 (unsigned) nir_metadata_dominance
));
6579 * Pre-gen6, the register file of the EUs was shared between threads,
6580 * and each thread used some subset allocated on a 16-register block
6581 * granularity. The unit states wanted these block counts.
6584 brw_register_blocks(int reg_count
)
6586 return ALIGN(reg_count
, 16) / 16 - 1;
6590 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6592 const struct brw_wm_prog_key
*key
,
6593 struct brw_wm_prog_data
*prog_data
,
6594 const nir_shader
*src_shader
,
6595 struct gl_program
*prog
,
6596 int shader_time_index8
, int shader_time_index16
,
6597 bool allow_spilling
,
6598 bool use_rep_send
, struct brw_vue_map
*vue_map
,
6601 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
6603 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6604 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6605 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
6606 brw_nir_lower_fs_outputs(shader
);
6608 if (devinfo
->gen
< 6) {
6609 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
, devinfo
);
6612 if (!key
->multisample_fbo
)
6613 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6614 NIR_PASS_V(shader
, move_interpolation_to_top
);
6615 shader
= brw_postprocess_nir(shader
, compiler
, true);
6617 /* key->alpha_test_func means simulating alpha testing via discards,
6618 * so the shader definitely kills pixels.
6620 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
6621 key
->alpha_test_func
;
6622 prog_data
->uses_omask
= key
->multisample_fbo
&&
6623 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6624 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6625 prog_data
->computed_stencil
=
6626 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6628 prog_data
->persample_dispatch
=
6629 key
->multisample_fbo
&&
6630 (key
->persample_interp
||
6631 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6632 SYSTEM_BIT_SAMPLE_POS
)) ||
6633 shader
->info
.fs
.uses_sample_qualifier
||
6634 shader
->info
.outputs_read
);
6636 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
6638 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6639 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
6640 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
6642 prog_data
->barycentric_interp_modes
=
6643 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6645 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6646 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6647 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6649 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6650 &prog_data
->base
, prog
, shader
, 8,
6651 shader_time_index8
);
6652 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6654 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6657 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6659 simd8_grf_start
= v8
.payload
.num_regs
;
6660 simd8_grf_used
= v8
.grf_used
;
6663 if (v8
.max_dispatch_width
>= 16 &&
6664 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6665 /* Try a SIMD16 compile */
6666 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6667 &prog_data
->base
, prog
, shader
, 16,
6668 shader_time_index16
);
6669 v16
.import_uniforms(&v8
);
6670 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6671 compiler
->shader_perf_log(log_data
,
6672 "SIMD16 shader failed to compile: %s",
6675 simd16_cfg
= v16
.cfg
;
6676 simd16_grf_start
= v16
.payload
.num_regs
;
6677 simd16_grf_used
= v16
.grf_used
;
6681 /* When the caller requests a repclear shader, they want SIMD16-only */
6685 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6686 * at the top to select the shader. We've never implemented that.
6687 * Instead, we just give them exactly one shader and we pick the widest one
6690 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6693 if (prog_data
->persample_dispatch
) {
6694 /* Starting with SandyBridge (where we first get MSAA), the different
6695 * pixel dispatch combinations are grouped into classifications A
6696 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6697 * generations, the only configurations supporting persample dispatch
6698 * are are this in which only one dispatch width is enabled.
6700 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6701 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6703 if (compiler
->devinfo
->gen
== 6 &&
6704 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6706 } else if (simd16_cfg
) {
6711 /* We have to compute the flat inputs after the visitor is finished running
6712 * because it relies on prog_data->urb_setup which is computed in
6713 * fs_visitor::calculate_urb_setup().
6715 brw_compute_flat_inputs(prog_data
, shader
);
6717 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6718 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6719 MESA_SHADER_FRAGMENT
);
6721 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6722 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6723 shader
->info
.label
?
6724 shader
->info
.label
: "unnamed",
6725 shader
->info
.name
));
6729 prog_data
->dispatch_8
= true;
6730 g
.generate_code(simd8_cfg
, 8);
6731 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6732 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6735 prog_data
->dispatch_16
= true;
6736 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6737 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6738 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6740 } else if (simd16_cfg
) {
6741 prog_data
->dispatch_16
= true;
6742 g
.generate_code(simd16_cfg
, 16);
6743 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6744 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6747 return g
.get_assembly(&prog_data
->base
.program_size
);
6751 fs_visitor::emit_cs_work_group_id_setup()
6753 assert(stage
== MESA_SHADER_COMPUTE
);
6755 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6757 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6758 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6759 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6761 bld
.MOV(*reg
, r0_1
);
6762 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6763 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6769 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6771 block
->dwords
= dwords
;
6772 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6773 block
->size
= block
->regs
* 32;
6777 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6778 struct brw_cs_prog_data
*cs_prog_data
)
6780 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
6781 int thread_local_id_index
= get_thread_local_id_param_index(prog_data
);
6782 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6784 /* The thread ID should be stored in the last param dword */
6785 assert(thread_local_id_index
== -1 ||
6786 thread_local_id_index
== (int)prog_data
->nr_params
- 1);
6788 unsigned cross_thread_dwords
, per_thread_dwords
;
6789 if (!cross_thread_supported
) {
6790 cross_thread_dwords
= 0u;
6791 per_thread_dwords
= prog_data
->nr_params
;
6792 } else if (thread_local_id_index
>= 0) {
6793 /* Fill all but the last register with cross-thread payload */
6794 cross_thread_dwords
= 8 * (thread_local_id_index
/ 8);
6795 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6796 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6798 /* Fill all data using cross-thread payload */
6799 cross_thread_dwords
= prog_data
->nr_params
;
6800 per_thread_dwords
= 0u;
6803 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6804 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6806 unsigned total_dwords
=
6807 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6808 cs_prog_data
->push
.cross_thread
.size
) / 4;
6809 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6811 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6812 cs_prog_data
->push
.per_thread
.size
== 0);
6813 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6814 cs_prog_data
->push
.per_thread
.dwords
==
6815 prog_data
->nr_params
);
6819 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6821 cs_prog_data
->simd_size
= size
;
6822 unsigned group_size
= cs_prog_data
->local_size
[0] *
6823 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6824 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6828 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6830 const struct brw_cs_prog_key
*key
,
6831 struct brw_cs_prog_data
*prog_data
,
6832 const nir_shader
*src_shader
,
6833 int shader_time_index
,
6836 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6837 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6838 brw_nir_lower_cs_intrinsics(shader
);
6839 shader
= brw_postprocess_nir(shader
, compiler
, true);
6841 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6842 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6843 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6844 unsigned local_workgroup_size
=
6845 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6846 shader
->info
.cs
.local_size
[2];
6848 unsigned min_dispatch_width
=
6849 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
6850 min_dispatch_width
= MAX2(8, min_dispatch_width
);
6851 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
6852 assert(min_dispatch_width
<= 32);
6855 const char *fail_msg
= NULL
;
6857 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6859 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6860 NULL
, /* Never used in core profile */
6861 shader
, 8, shader_time_index
);
6862 if (min_dispatch_width
<= 8) {
6863 if (!v8
.run_cs(min_dispatch_width
)) {
6864 fail_msg
= v8
.fail_msg
;
6866 /* We should always be able to do SIMD32 for compute shaders */
6867 assert(v8
.max_dispatch_width
>= 32);
6870 cs_set_simd_size(prog_data
, 8);
6871 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6875 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6876 NULL
, /* Never used in core profile */
6877 shader
, 16, shader_time_index
);
6878 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6879 !fail_msg
&& min_dispatch_width
<= 16) {
6880 /* Try a SIMD16 compile */
6881 if (min_dispatch_width
<= 8)
6882 v16
.import_uniforms(&v8
);
6883 if (!v16
.run_cs(min_dispatch_width
)) {
6884 compiler
->shader_perf_log(log_data
,
6885 "SIMD16 shader failed to compile: %s",
6889 "Couldn't generate SIMD16 program and not "
6890 "enough threads for SIMD8";
6893 /* We should always be able to do SIMD32 for compute shaders */
6894 assert(v16
.max_dispatch_width
>= 32);
6897 cs_set_simd_size(prog_data
, 16);
6898 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6902 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6903 NULL
, /* Never used in core profile */
6904 shader
, 32, shader_time_index
);
6905 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6906 /* Try a SIMD32 compile */
6907 if (min_dispatch_width
<= 8)
6908 v32
.import_uniforms(&v8
);
6909 else if (min_dispatch_width
<= 16)
6910 v32
.import_uniforms(&v16
);
6912 if (!v32
.run_cs(min_dispatch_width
)) {
6913 compiler
->shader_perf_log(log_data
,
6914 "SIMD32 shader failed to compile: %s",
6918 "Couldn't generate SIMD32 program and not "
6919 "enough threads for SIMD16";
6923 cs_set_simd_size(prog_data
, 32);
6924 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6928 if (unlikely(cfg
== NULL
)) {
6931 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6936 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6937 v8
.promoted_constants
, false, MESA_SHADER_COMPUTE
);
6938 if (INTEL_DEBUG
& DEBUG_CS
) {
6939 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6940 shader
->info
.label
? shader
->info
.label
:
6943 g
.enable_debug(name
);
6946 g
.generate_code(cfg
, prog_data
->simd_size
);
6948 return g
.get_assembly(&prog_data
->base
.program_size
);
6952 * Test the dispatch mask packing assumptions of
6953 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
6954 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
6955 * executed with an unexpected dispatch mask.
6958 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
6960 const gl_shader_stage stage
= bld
.shader
->stage
;
6962 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
6963 bld
.shader
->stage_prog_data
)) {
6964 const fs_builder ubld
= bld
.exec_all().group(1, 0);
6965 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
6966 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
6969 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
6970 ubld
.AND(tmp
, mask
, tmp
);
6972 /* This will loop forever if the dispatch mask doesn't have the expected
6973 * form '2^n-1', in which case tmp will be non-zero.
6975 bld
.emit(BRW_OPCODE_DO
);
6976 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
6977 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));