2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "common/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
45 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
49 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
50 const fs_reg
*src
, unsigned sources
)
52 memset(this, 0, sizeof(*this));
54 this->src
= new fs_reg
[MAX2(sources
, 3)];
55 for (unsigned i
= 0; i
< sources
; i
++)
56 this->src
[i
] = src
[i
];
58 this->opcode
= opcode
;
60 this->sources
= sources
;
61 this->exec_size
= exec_size
;
64 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
66 assert(this->exec_size
!= 0);
68 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
70 /* This will be the case for almost all instructions. */
77 this->size_written
= dst
.component_size(exec_size
);
80 this->size_written
= 0;
84 unreachable("Invalid destination register file");
87 this->writes_accumulator
= false;
92 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
95 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
97 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
100 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
102 init(opcode
, exec_size
, dst
, NULL
, 0);
105 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
108 const fs_reg src
[1] = { src0
};
109 init(opcode
, exec_size
, dst
, src
, 1);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
113 const fs_reg
&src0
, const fs_reg
&src1
)
115 const fs_reg src
[2] = { src0
, src1
};
116 init(opcode
, exec_size
, dst
, src
, 2);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
122 const fs_reg src
[3] = { src0
, src1
, src2
};
123 init(opcode
, exec_size
, dst
, src
, 3);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
127 const fs_reg src
[], unsigned sources
)
129 init(opcode
, exec_width
, dst
, src
, sources
);
132 fs_inst::fs_inst(const fs_inst
&that
)
134 memcpy(this, &that
, sizeof(that
));
136 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
138 for (unsigned i
= 0; i
< that
.sources
; i
++)
139 this->src
[i
] = that
.src
[i
];
148 fs_inst::resize_sources(uint8_t num_sources
)
150 if (this->sources
!= num_sources
) {
151 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
153 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
154 src
[i
] = this->src
[i
];
158 this->sources
= num_sources
;
163 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
165 const fs_reg
&surf_index
,
166 const fs_reg
&varying_offset
,
167 uint32_t const_offset
)
169 /* We have our constant surface use a pitch of 4 bytes, so our index can
170 * be any component of a vector, and then we load 4 contiguous
171 * components starting from that.
173 * We break down the const_offset to a portion added to the variable offset
174 * and a portion done using fs_reg::offset, which means that if you have
175 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
176 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
177 * later notice that those loads are all the same and eliminate the
180 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
181 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
183 /* The pull load message will load a vec4 (16 bytes). If we are loading
184 * a double this means we are only loading 2 elements worth of data.
185 * We also want to use a 32-bit data type for the dst of the load operation
186 * so other parts of the driver don't get confused about the size of the
189 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
190 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
191 vec4_result
, surf_index
, vec4_offset
);
192 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
194 fs_reg dw
= offset(vec4_result
, bld
, (const_offset
& 0xf) / 4);
195 switch (type_sz(dst
.type
)) {
197 shuffle_32bit_load_result_to_16bit_data(bld
, dst
, dw
, 1);
198 bld
.MOV(dst
, subscript(dw
, dst
.type
, (const_offset
/ 2) & 1));
201 bld
.MOV(dst
, retype(dw
, dst
.type
));
204 shuffle_32bit_load_result_to_64bit_data(bld
, dst
, dw
, 1);
207 unreachable("Unsupported bit_size");
212 * A helper for MOV generation for fixing up broken hardware SEND dependency
216 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
218 /* The caller always wants uncompressed to emit the minimal extra
219 * dependencies, and to avoid having to deal with aligning its regs to 2.
221 const fs_builder ubld
= bld
.annotate("send dependency resolve")
224 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
228 fs_inst::equals(fs_inst
*inst
) const
230 return (opcode
== inst
->opcode
&&
231 dst
.equals(inst
->dst
) &&
232 src
[0].equals(inst
->src
[0]) &&
233 src
[1].equals(inst
->src
[1]) &&
234 src
[2].equals(inst
->src
[2]) &&
235 saturate
== inst
->saturate
&&
236 predicate
== inst
->predicate
&&
237 conditional_mod
== inst
->conditional_mod
&&
238 mlen
== inst
->mlen
&&
239 base_mrf
== inst
->base_mrf
&&
240 target
== inst
->target
&&
242 header_size
== inst
->header_size
&&
243 shadow_compare
== inst
->shadow_compare
&&
244 exec_size
== inst
->exec_size
&&
245 offset
== inst
->offset
);
249 fs_inst::is_send_from_grf() const
252 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
253 case SHADER_OPCODE_SHADER_TIME_ADD
:
254 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
255 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
256 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
257 case SHADER_OPCODE_UNTYPED_ATOMIC
:
258 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
259 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
260 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
261 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
262 case SHADER_OPCODE_TYPED_ATOMIC
:
263 case SHADER_OPCODE_TYPED_SURFACE_READ
:
264 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
265 case SHADER_OPCODE_URB_WRITE_SIMD8
:
266 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
267 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
268 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
269 case SHADER_OPCODE_URB_READ_SIMD8
:
270 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
272 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
273 return src
[1].file
== VGRF
;
274 case FS_OPCODE_FB_WRITE
:
275 case FS_OPCODE_FB_READ
:
276 return src
[0].file
== VGRF
;
279 return src
[0].file
== VGRF
;
286 * Returns true if this instruction's sources and destinations cannot
287 * safely be the same register.
289 * In most cases, a register can be written over safely by the same
290 * instruction that is its last use. For a single instruction, the
291 * sources are dereferenced before writing of the destination starts
294 * However, there are a few cases where this can be problematic:
296 * - Virtual opcodes that translate to multiple instructions in the
297 * code generator: if src == dst and one instruction writes the
298 * destination before a later instruction reads the source, then
299 * src will have been clobbered.
301 * - SIMD16 compressed instructions with certain regioning (see below).
303 * The register allocator uses this information to set up conflicts between
304 * GRF sources and the destination.
307 fs_inst::has_source_and_destination_hazard() const
310 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
311 /* Multiple partial writes to the destination */
314 /* The SIMD16 compressed instruction
316 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
318 * is actually decoded in hardware as:
320 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
321 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
323 * Which is safe. However, if we have uniform accesses
324 * happening, we get into trouble:
326 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
327 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
329 * Now our destination for the first instruction overwrote the
330 * second instruction's src0, and we get garbage for those 8
331 * pixels. There's a similar issue for the pre-gen6
332 * pixel_x/pixel_y, which are registers of 16-bit values and thus
333 * would get stomped by the first decode as well.
335 if (exec_size
== 16) {
336 for (int i
= 0; i
< sources
; i
++) {
337 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
338 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
339 src
[i
].type
== BRW_REGISTER_TYPE_W
||
340 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
341 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
351 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
353 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
356 fs_reg reg
= this->src
[0];
357 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
360 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
363 for (int i
= 0; i
< this->sources
; i
++) {
364 reg
.type
= this->src
[i
].type
;
365 if (!this->src
[i
].equals(reg
))
368 if (i
< this->header_size
) {
369 reg
.offset
+= REG_SIZE
;
371 reg
= horiz_offset(reg
, this->exec_size
);
379 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
381 if (devinfo
->gen
== 6 && is_math())
384 if (is_send_from_grf())
387 if (!backend_instruction::can_do_source_mods())
394 fs_inst::can_change_types() const
396 return dst
.type
== src
[0].type
&&
397 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
398 (opcode
== BRW_OPCODE_MOV
||
399 (opcode
== BRW_OPCODE_SEL
&&
400 dst
.type
== src
[1].type
&&
401 predicate
!= BRW_PREDICATE_NONE
&&
402 !src
[1].abs
&& !src
[1].negate
));
408 memset(this, 0, sizeof(*this));
409 type
= BRW_REGISTER_TYPE_UD
;
413 /** Generic unset register constructor. */
417 this->file
= BAD_FILE
;
420 fs_reg::fs_reg(struct ::brw_reg reg
) :
425 if (this->file
== IMM
&&
426 (this->type
!= BRW_REGISTER_TYPE_V
&&
427 this->type
!= BRW_REGISTER_TYPE_UV
&&
428 this->type
!= BRW_REGISTER_TYPE_VF
)) {
434 fs_reg::equals(const fs_reg
&r
) const
436 return (this->backend_reg::equals(r
) &&
441 fs_reg::is_contiguous() const
447 fs_reg::component_size(unsigned width
) const
449 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
452 return MAX2(width
* stride
, 1) * type_sz(type
);
456 type_size_scalar(const struct glsl_type
*type
)
458 unsigned int size
, i
;
460 switch (type
->base_type
) {
463 case GLSL_TYPE_FLOAT
:
465 return type
->components();
466 case GLSL_TYPE_UINT16
:
467 case GLSL_TYPE_INT16
:
468 case GLSL_TYPE_FLOAT16
:
469 return DIV_ROUND_UP(type
->components(), 2);
470 case GLSL_TYPE_DOUBLE
:
471 case GLSL_TYPE_UINT64
:
472 case GLSL_TYPE_INT64
:
473 return type
->components() * 2;
474 case GLSL_TYPE_ARRAY
:
475 return type_size_scalar(type
->fields
.array
) * type
->length
;
476 case GLSL_TYPE_STRUCT
:
478 for (i
= 0; i
< type
->length
; i
++) {
479 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
482 case GLSL_TYPE_SAMPLER
:
483 /* Samplers take up no register space, since they're baked in at
487 case GLSL_TYPE_ATOMIC_UINT
:
489 case GLSL_TYPE_SUBROUTINE
:
491 case GLSL_TYPE_IMAGE
:
492 return BRW_IMAGE_PARAM_SIZE
;
494 case GLSL_TYPE_ERROR
:
495 case GLSL_TYPE_INTERFACE
:
496 case GLSL_TYPE_FUNCTION
:
497 unreachable("not reached");
504 * Create a MOV to read the timestamp register.
506 * The caller is responsible for emitting the MOV. The return value is
507 * the destination of the MOV, with extra parameters set.
510 fs_visitor::get_timestamp(const fs_builder
&bld
)
512 assert(devinfo
->gen
>= 7);
514 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
517 BRW_REGISTER_TYPE_UD
));
519 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
521 /* We want to read the 3 fields we care about even if it's not enabled in
524 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
530 fs_visitor::emit_shader_time_begin()
532 /* We want only the low 32 bits of the timestamp. Since it's running
533 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
534 * which is plenty of time for our purposes. It is identical across the
535 * EUs, but since it's tracking GPU core speed it will increment at a
536 * varying rate as render P-states change.
538 shader_start_time
= component(
539 get_timestamp(bld
.annotate("shader time start")), 0);
543 fs_visitor::emit_shader_time_end()
545 /* Insert our code just before the final SEND with EOT. */
546 exec_node
*end
= this->instructions
.get_tail();
547 assert(end
&& ((fs_inst
*) end
)->eot
);
548 const fs_builder ibld
= bld
.annotate("shader time end")
549 .exec_all().at(NULL
, end
);
550 const fs_reg timestamp
= get_timestamp(ibld
);
552 /* We only use the low 32 bits of the timestamp - see
553 * emit_shader_time_begin()).
555 * We could also check if render P-states have changed (or anything
556 * else that might disrupt timing) by setting smear to 2 and checking if
557 * that field is != 0.
559 const fs_reg shader_end_time
= component(timestamp
, 0);
561 /* Check that there weren't any timestamp reset events (assuming these
562 * were the only two timestamp reads that happened).
564 const fs_reg reset
= component(timestamp
, 2);
565 set_condmod(BRW_CONDITIONAL_Z
,
566 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
567 ibld
.IF(BRW_PREDICATE_NORMAL
);
569 fs_reg start
= shader_start_time
;
571 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
572 BRW_REGISTER_TYPE_UD
),
574 const fs_builder cbld
= ibld
.group(1, 0);
575 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
577 /* If there were no instructions between the two timestamp gets, the diff
578 * is 2 cycles. Remove that overhead, so I can forget about that when
579 * trying to determine the time taken for single instructions.
581 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
582 SHADER_TIME_ADD(cbld
, 0, diff
);
583 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
584 ibld
.emit(BRW_OPCODE_ELSE
);
585 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
586 ibld
.emit(BRW_OPCODE_ENDIF
);
590 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
591 int shader_time_subindex
,
594 int index
= shader_time_index
* 3 + shader_time_subindex
;
595 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
598 if (dispatch_width
== 8)
599 payload
= vgrf(glsl_type::uvec2_type
);
601 payload
= vgrf(glsl_type::uint_type
);
603 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
607 fs_visitor::vfail(const char *format
, va_list va
)
616 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
617 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
619 this->fail_msg
= msg
;
622 fprintf(stderr
, "%s", msg
);
627 fs_visitor::fail(const char *format
, ...)
631 va_start(va
, format
);
637 * Mark this program as impossible to compile with dispatch width greater
640 * During the SIMD8 compile (which happens first), we can detect and flag
641 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
642 * SIMD16+ compile altogether.
644 * During a compile of dispatch width greater than n (if one happens anyway),
645 * this just calls fail().
648 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
650 if (dispatch_width
> n
) {
653 max_dispatch_width
= n
;
654 compiler
->shader_perf_log(log_data
,
655 "Shader dispatch width limited to SIMD%d: %s",
661 * Returns true if the instruction has a flag that means it won't
662 * update an entire destination register.
664 * For example, dead code elimination and live variable analysis want to know
665 * when a write to a variable screens off any preceding values that were in
669 fs_inst::is_partial_write() const
671 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
672 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
673 !this->dst
.is_contiguous() ||
674 this->dst
.offset
% REG_SIZE
!= 0);
678 fs_inst::components_read(unsigned i
) const
680 /* Return zero if the source is not present. */
681 if (src
[i
].file
== BAD_FILE
)
685 case FS_OPCODE_LINTERP
:
691 case FS_OPCODE_PIXEL_X
:
692 case FS_OPCODE_PIXEL_Y
:
696 case FS_OPCODE_FB_WRITE_LOGICAL
:
697 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
698 /* First/second FB write color. */
700 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
704 case SHADER_OPCODE_TEX_LOGICAL
:
705 case SHADER_OPCODE_TXD_LOGICAL
:
706 case SHADER_OPCODE_TXF_LOGICAL
:
707 case SHADER_OPCODE_TXL_LOGICAL
:
708 case SHADER_OPCODE_TXS_LOGICAL
:
709 case FS_OPCODE_TXB_LOGICAL
:
710 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
711 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
712 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
713 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
714 case SHADER_OPCODE_LOD_LOGICAL
:
715 case SHADER_OPCODE_TG4_LOGICAL
:
716 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
717 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
718 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
719 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
720 /* Texture coordinates. */
721 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
722 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
723 /* Texture derivatives. */
724 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
725 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
726 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
727 /* Texture offset. */
728 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
731 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
736 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
737 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
738 assert(src
[3].file
== IMM
);
739 /* Surface coordinates. */
742 /* Surface operation source (ignored for reads). */
748 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
749 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
750 assert(src
[3].file
== IMM
&&
752 /* Surface coordinates. */
755 /* Surface operation source. */
761 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
762 /* Scattered logical opcodes use the following params:
763 * src[0] Surface coordinates
764 * src[1] Surface operation source (ignored for reads)
766 * src[3] IMM with always 1 dimension.
767 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
769 assert(src
[3].file
== IMM
&&
771 return i
== 1 ? 0 : 1;
773 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
774 assert(src
[3].file
== IMM
&&
778 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
779 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
780 assert(src
[3].file
== IMM
&&
782 const unsigned op
= src
[4].ud
;
783 /* Surface coordinates. */
786 /* Surface operation source. */
787 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
789 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
790 op
== BRW_AOP_PREDEC
))
802 fs_inst::size_read(int arg
) const
805 case FS_OPCODE_FB_WRITE
:
806 case FS_OPCODE_FB_READ
:
807 case SHADER_OPCODE_URB_WRITE_SIMD8
:
808 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
809 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
810 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
811 case SHADER_OPCODE_URB_READ_SIMD8
:
812 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
813 case SHADER_OPCODE_UNTYPED_ATOMIC
:
814 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
815 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
816 case SHADER_OPCODE_TYPED_ATOMIC
:
817 case SHADER_OPCODE_TYPED_SURFACE_READ
:
818 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
819 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
820 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
821 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
823 return mlen
* REG_SIZE
;
826 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
827 /* The payload is actually stored in src1 */
829 return mlen
* REG_SIZE
;
832 case FS_OPCODE_LINTERP
:
837 case SHADER_OPCODE_LOAD_PAYLOAD
:
838 if (arg
< this->header_size
)
842 case CS_OPCODE_CS_TERMINATE
:
843 case SHADER_OPCODE_BARRIER
:
846 case SHADER_OPCODE_MOV_INDIRECT
:
848 assert(src
[2].file
== IMM
);
854 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
855 return mlen
* REG_SIZE
;
859 switch (src
[arg
].file
) {
862 return components_read(arg
) * type_sz(src
[arg
].type
);
868 return components_read(arg
) * src
[arg
].component_size(exec_size
);
870 unreachable("MRF registers are not allowed as sources");
876 /* Return the subset of flag registers that an instruction could
877 * potentially read or write based on the execution controls and flag
878 * subregister number of the instruction.
881 flag_mask(const fs_inst
*inst
)
883 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
884 const unsigned end
= start
+ inst
->exec_size
;
885 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
891 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
895 flag_mask(const fs_reg
&r
, unsigned sz
)
898 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
899 const unsigned end
= start
+ sz
;
900 return bit_mask(end
) & ~bit_mask(start
);
908 fs_inst::flags_read(const gen_device_info
*devinfo
) const
910 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
911 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
912 /* The vertical predication modes combine corresponding bits from
913 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
915 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
916 return flag_mask(this) << shift
| flag_mask(this);
917 } else if (predicate
) {
918 return flag_mask(this);
921 for (int i
= 0; i
< sources
; i
++) {
922 mask
|= flag_mask(src
[i
], size_read(i
));
929 fs_inst::flags_written() const
931 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
932 opcode
!= BRW_OPCODE_IF
&&
933 opcode
!= BRW_OPCODE_WHILE
)) ||
934 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
935 return flag_mask(this);
937 return flag_mask(dst
, size_written
);
942 * Returns how many MRFs an FS opcode will write over.
944 * Note that this is not the 0 or 1 implied writes in an actual gen
945 * instruction -- the FS opcodes often generate MOVs in addition.
948 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
953 if (inst
->base_mrf
== -1)
956 switch (inst
->opcode
) {
957 case SHADER_OPCODE_RCP
:
958 case SHADER_OPCODE_RSQ
:
959 case SHADER_OPCODE_SQRT
:
960 case SHADER_OPCODE_EXP2
:
961 case SHADER_OPCODE_LOG2
:
962 case SHADER_OPCODE_SIN
:
963 case SHADER_OPCODE_COS
:
964 return 1 * dispatch_width
/ 8;
965 case SHADER_OPCODE_POW
:
966 case SHADER_OPCODE_INT_QUOTIENT
:
967 case SHADER_OPCODE_INT_REMAINDER
:
968 return 2 * dispatch_width
/ 8;
969 case SHADER_OPCODE_TEX
:
971 case SHADER_OPCODE_TXD
:
972 case SHADER_OPCODE_TXF
:
973 case SHADER_OPCODE_TXF_CMS
:
974 case SHADER_OPCODE_TXF_MCS
:
975 case SHADER_OPCODE_TG4
:
976 case SHADER_OPCODE_TG4_OFFSET
:
977 case SHADER_OPCODE_TXL
:
978 case SHADER_OPCODE_TXS
:
979 case SHADER_OPCODE_LOD
:
980 case SHADER_OPCODE_SAMPLEINFO
:
982 case FS_OPCODE_FB_WRITE
:
984 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
985 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
987 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
989 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
992 unreachable("not reached");
997 fs_visitor::vgrf(const glsl_type
*const type
)
999 int reg_width
= dispatch_width
/ 8;
1000 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1001 brw_type_for_base_type(type
));
1004 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1009 this->type
= BRW_REGISTER_TYPE_F
;
1010 this->stride
= (file
== UNIFORM
? 0 : 1);
1013 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1019 this->stride
= (file
== UNIFORM
? 0 : 1);
1022 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1023 * This brings in those uniform definitions
1026 fs_visitor::import_uniforms(fs_visitor
*v
)
1028 this->push_constant_loc
= v
->push_constant_loc
;
1029 this->pull_constant_loc
= v
->pull_constant_loc
;
1030 this->uniforms
= v
->uniforms
;
1031 this->subgroup_id
= v
->subgroup_id
;
1035 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1037 assert(stage
== MESA_SHADER_FRAGMENT
);
1039 /* gl_FragCoord.x */
1040 bld
.MOV(wpos
, this->pixel_x
);
1041 wpos
= offset(wpos
, bld
, 1);
1043 /* gl_FragCoord.y */
1044 bld
.MOV(wpos
, this->pixel_y
);
1045 wpos
= offset(wpos
, bld
, 1);
1047 /* gl_FragCoord.z */
1048 if (devinfo
->gen
>= 6) {
1049 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1051 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1052 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1053 interp_reg(VARYING_SLOT_POS
, 2));
1055 wpos
= offset(wpos
, bld
, 1);
1057 /* gl_FragCoord.w: Already set up in emit_interpolation */
1058 bld
.MOV(wpos
, this->wpos_w
);
1061 enum brw_barycentric_mode
1062 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1064 /* Barycentric modes don't make sense for flat inputs. */
1065 assert(mode
!= INTERP_MODE_FLAT
);
1069 case nir_intrinsic_load_barycentric_pixel
:
1070 case nir_intrinsic_load_barycentric_at_offset
:
1071 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1073 case nir_intrinsic_load_barycentric_centroid
:
1074 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1076 case nir_intrinsic_load_barycentric_sample
:
1077 case nir_intrinsic_load_barycentric_at_sample
:
1078 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1081 unreachable("invalid intrinsic");
1084 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1087 return (enum brw_barycentric_mode
) bary
;
1091 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1093 static enum brw_barycentric_mode
1094 centroid_to_pixel(enum brw_barycentric_mode bary
)
1096 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1097 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1098 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1102 fs_visitor::emit_frontfacing_interpolation()
1104 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1106 if (devinfo
->gen
>= 6) {
1107 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1108 * a boolean result from this (~0/true or 0/false).
1110 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1111 * this task in only one instruction:
1112 * - a negation source modifier will flip the bit; and
1113 * - a W -> D type conversion will sign extend the bit into the high
1114 * word of the destination.
1116 * An ASR 15 fills the low word of the destination.
1118 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1121 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1123 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1124 * a boolean result from this (1/true or 0/false).
1126 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1127 * the negation source modifier to flip it. Unfortunately the SHR
1128 * instruction only operates on UD (or D with an abs source modifier)
1129 * sources without negation.
1131 * Instead, use ASR (which will give ~0/true or 0/false).
1133 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1136 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1143 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1145 assert(stage
== MESA_SHADER_FRAGMENT
);
1146 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1147 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1149 if (wm_prog_data
->persample_dispatch
) {
1150 /* Convert int_sample_pos to floating point */
1151 bld
.MOV(dst
, int_sample_pos
);
1152 /* Scale to the range [0, 1] */
1153 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1156 /* From ARB_sample_shading specification:
1157 * "When rendering to a non-multisample buffer, or if multisample
1158 * rasterization is disabled, gl_SamplePosition will always be
1161 bld
.MOV(dst
, brw_imm_f(0.5f
));
1166 fs_visitor::emit_samplepos_setup()
1168 assert(devinfo
->gen
>= 6);
1170 const fs_builder abld
= bld
.annotate("compute sample position");
1171 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1173 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1174 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1176 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1177 * mode will be enabled.
1179 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1180 * R31.1:0 Position Offset X/Y for Slot[3:0]
1181 * R31.3:2 Position Offset X/Y for Slot[7:4]
1184 * The X, Y sample positions come in as bytes in thread payload. So, read
1185 * the positions using vstride=16, width=8, hstride=2.
1187 struct brw_reg sample_pos_reg
=
1188 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1189 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1191 if (dispatch_width
== 8) {
1192 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1194 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1195 abld
.half(1).MOV(half(int_sample_x
, 1),
1196 fs_reg(suboffset(sample_pos_reg
, 16)));
1198 /* Compute gl_SamplePosition.x */
1199 compute_sample_position(pos
, int_sample_x
);
1200 pos
= offset(pos
, abld
, 1);
1201 if (dispatch_width
== 8) {
1202 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1204 abld
.half(0).MOV(half(int_sample_y
, 0),
1205 fs_reg(suboffset(sample_pos_reg
, 1)));
1206 abld
.half(1).MOV(half(int_sample_y
, 1),
1207 fs_reg(suboffset(sample_pos_reg
, 17)));
1209 /* Compute gl_SamplePosition.y */
1210 compute_sample_position(pos
, int_sample_y
);
1215 fs_visitor::emit_sampleid_setup()
1217 assert(stage
== MESA_SHADER_FRAGMENT
);
1218 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1219 assert(devinfo
->gen
>= 6);
1221 const fs_builder abld
= bld
.annotate("compute sample id");
1222 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1224 if (!key
->multisample_fbo
) {
1225 /* As per GL_ARB_sample_shading specification:
1226 * "When rendering to a non-multisample buffer, or if multisample
1227 * rasterization is disabled, gl_SampleID will always be zero."
1229 abld
.MOV(*reg
, brw_imm_d(0));
1230 } else if (devinfo
->gen
>= 8) {
1231 /* Sample ID comes in as 4-bit numbers in g1.0:
1233 * 15:12 Slot 3 SampleID (only used in SIMD16)
1234 * 11:8 Slot 2 SampleID (only used in SIMD16)
1235 * 7:4 Slot 1 SampleID
1236 * 3:0 Slot 0 SampleID
1238 * Each slot corresponds to four channels, so we want to replicate each
1239 * half-byte value to 4 channels in a row:
1241 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1242 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1244 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1245 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1247 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1248 * channels to read the first byte (7:0), and the second group of 8
1249 * channels to read the second byte (15:8). Then, we shift right by
1250 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1251 * values into place. Finally, we AND with 0xf to keep the low nibble.
1253 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1254 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1256 * TODO: These payload bits exist on Gen7 too, but they appear to always
1257 * be zero, so this code fails to work. We should find out why.
1259 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1261 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1262 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1263 brw_imm_v(0x44440000));
1264 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1266 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1267 BRW_REGISTER_TYPE_D
), 0);
1268 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1270 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1271 * 8x multisampling, subspan 0 will represent sample N (where N
1272 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1273 * 7. We can find the value of N by looking at R0.0 bits 7:6
1274 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1275 * (since samples are always delivered in pairs). That is, we
1276 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1277 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1278 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1279 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1280 * populating a temporary variable with the sequence (0, 1, 2, 3),
1281 * and then reading from it using vstride=1, width=4, hstride=0.
1282 * These computations hold good for 4x multisampling as well.
1284 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1285 * the first four slots are sample 0 of subspan 0; the next four
1286 * are sample 1 of subspan 0; the third group is sample 0 of
1287 * subspan 1, and finally sample 1 of subspan 1.
1290 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1291 * accomodate 16x MSAA.
1293 abld
.exec_all().group(1, 0)
1294 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1296 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1298 /* This works for both SIMD8 and SIMD16 */
1299 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1301 /* This special instruction takes care of setting vstride=1,
1302 * width=4, hstride=0 of t2 during an ADD instruction.
1304 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1311 fs_visitor::emit_samplemaskin_setup()
1313 assert(stage
== MESA_SHADER_FRAGMENT
);
1314 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1315 assert(devinfo
->gen
>= 6);
1317 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1319 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1320 BRW_REGISTER_TYPE_D
));
1322 if (wm_prog_data
->persample_dispatch
) {
1323 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1324 * and a mask representing which sample is being processed by the
1325 * current shader invocation.
1327 * From the OES_sample_variables specification:
1328 * "When per-sample shading is active due to the use of a fragment input
1329 * qualified by "sample" or due to the use of the gl_SampleID or
1330 * gl_SamplePosition variables, only the bit for the current sample is
1331 * set in gl_SampleMaskIn."
1333 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1335 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1336 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1338 fs_reg one
= vgrf(glsl_type::int_type
);
1339 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1340 abld
.MOV(one
, brw_imm_d(1));
1341 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1342 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1344 /* In per-pixel mode, the coverage mask is sufficient. */
1345 *reg
= coverage_mask
;
1351 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1353 if (!src
.abs
&& !src
.negate
)
1356 fs_reg temp
= bld
.vgrf(src
.type
);
1363 fs_visitor::emit_discard_jump()
1365 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1367 /* For performance, after a discard, jump to the end of the
1368 * shader if all relevant channels have been discarded.
1370 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1371 discard_jump
->flag_subreg
= 1;
1373 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1374 discard_jump
->predicate_inverse
= true;
1378 fs_visitor::emit_gs_thread_end()
1380 assert(stage
== MESA_SHADER_GEOMETRY
);
1382 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1384 if (gs_compile
->control_data_header_size_bits
> 0) {
1385 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1388 const fs_builder abld
= bld
.annotate("thread end");
1391 if (gs_prog_data
->static_vertex_count
!= -1) {
1392 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1393 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1394 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1395 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1396 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1399 /* Delete now dead instructions. */
1400 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1406 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1410 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1411 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1412 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1415 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1416 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1417 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1418 sources
[1] = this->final_gs_vertex_count
;
1419 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1420 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1428 fs_visitor::assign_curb_setup()
1430 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1432 unsigned ubo_push_length
= 0;
1433 unsigned ubo_push_start
[4];
1434 for (int i
= 0; i
< 4; i
++) {
1435 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1436 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1439 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1441 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1442 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1443 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1444 if (inst
->src
[i
].file
== UNIFORM
) {
1445 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1447 if (inst
->src
[i
].nr
>= UBO_START
) {
1448 /* constant_nr is in 32-bit units, the rest are in bytes */
1449 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1450 inst
->src
[i
].offset
/ 4;
1451 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1452 constant_nr
= push_constant_loc
[uniform_nr
];
1454 /* Section 5.11 of the OpenGL 4.1 spec says:
1455 * "Out-of-bounds reads return undefined values, which include
1456 * values from other variables of the active program or zero."
1457 * Just return the first push constant.
1462 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1465 brw_reg
.abs
= inst
->src
[i
].abs
;
1466 brw_reg
.negate
= inst
->src
[i
].negate
;
1468 assert(inst
->src
[i
].stride
== 0);
1469 inst
->src
[i
] = byte_offset(
1470 retype(brw_reg
, inst
->src
[i
].type
),
1471 inst
->src
[i
].offset
% 4);
1476 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1477 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1481 fs_visitor::calculate_urb_setup()
1483 assert(stage
== MESA_SHADER_FRAGMENT
);
1484 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1485 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1487 memset(prog_data
->urb_setup
, -1,
1488 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1491 /* Figure out where each of the incoming setup attributes lands. */
1492 if (devinfo
->gen
>= 6) {
1493 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1494 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1495 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1496 * first 16 varying inputs, so we can put them wherever we want.
1497 * Just put them in order.
1499 * This is useful because it means that (a) inputs not used by the
1500 * fragment shader won't take up valuable register space, and (b) we
1501 * won't have to recompile the fragment shader if it gets paired with
1502 * a different vertex (or geometry) shader.
1504 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1505 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1506 BITFIELD64_BIT(i
)) {
1507 prog_data
->urb_setup
[i
] = urb_next
++;
1511 /* We have enough input varyings that the SF/SBE pipeline stage can't
1512 * arbitrarily rearrange them to suit our whim; we have to put them
1513 * in an order that matches the output of the previous pipeline stage
1514 * (geometry or vertex shader).
1516 struct brw_vue_map prev_stage_vue_map
;
1517 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1518 key
->input_slots_valid
,
1519 nir
->info
.separate_shader
);
1522 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1523 &prev_stage_vue_map
);
1525 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1526 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1528 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1529 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1530 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1531 BITFIELD64_BIT(varying
))) {
1532 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1535 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1538 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1539 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1540 /* Point size is packed into the header, not as a general attribute */
1541 if (i
== VARYING_SLOT_PSIZ
)
1544 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1545 /* The back color slot is skipped when the front color is
1546 * also written to. In addition, some slots can be
1547 * written in the vertex shader and not read in the
1548 * fragment shader. So the register number must always be
1549 * incremented, mapped or not.
1551 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1552 prog_data
->urb_setup
[i
] = urb_next
;
1558 * It's a FS only attribute, and we did interpolation for this attribute
1559 * in SF thread. So, count it here, too.
1561 * See compile_sf_prog() for more info.
1563 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1564 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1567 prog_data
->num_varying_inputs
= urb_next
;
1571 fs_visitor::assign_urb_setup()
1573 assert(stage
== MESA_SHADER_FRAGMENT
);
1574 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1576 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1578 /* Offset all the urb_setup[] index by the actual position of the
1579 * setup regs, now that the location of the constants has been chosen.
1581 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1582 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1583 assert(inst
->src
[1].file
== FIXED_GRF
);
1584 inst
->src
[1].nr
+= urb_start
;
1587 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1588 assert(inst
->src
[0].file
== FIXED_GRF
);
1589 inst
->src
[0].nr
+= urb_start
;
1593 /* Each attribute is 4 setup channels, each of which is half a reg. */
1594 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1598 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1600 for (int i
= 0; i
< inst
->sources
; i
++) {
1601 if (inst
->src
[i
].file
== ATTR
) {
1602 int grf
= payload
.num_regs
+
1603 prog_data
->curb_read_length
+
1605 inst
->src
[i
].offset
/ REG_SIZE
;
1607 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1609 * VertStride must be used to cross GRF register boundaries. This
1610 * rule implies that elements within a 'Width' cannot cross GRF
1613 * So, for registers that are large enough, we have to split the exec
1614 * size in two and trust the compression state to sort it out.
1616 unsigned total_size
= inst
->exec_size
*
1617 inst
->src
[i
].stride
*
1618 type_sz(inst
->src
[i
].type
);
1620 assert(total_size
<= 2 * REG_SIZE
);
1621 const unsigned exec_size
=
1622 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1624 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1625 struct brw_reg reg
=
1626 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1627 inst
->src
[i
].offset
% REG_SIZE
),
1628 exec_size
* inst
->src
[i
].stride
,
1629 width
, inst
->src
[i
].stride
);
1630 reg
.abs
= inst
->src
[i
].abs
;
1631 reg
.negate
= inst
->src
[i
].negate
;
1639 fs_visitor::assign_vs_urb_setup()
1641 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1643 assert(stage
== MESA_SHADER_VERTEX
);
1645 /* Each attribute is 4 regs. */
1646 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1648 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1650 /* Rewrite all ATTR file references to the hw grf that they land in. */
1651 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1652 convert_attr_sources_to_hw_regs(inst
);
1657 fs_visitor::assign_tcs_single_patch_urb_setup()
1659 assert(stage
== MESA_SHADER_TESS_CTRL
);
1661 /* Rewrite all ATTR file references to HW_REGs. */
1662 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1663 convert_attr_sources_to_hw_regs(inst
);
1668 fs_visitor::assign_tes_urb_setup()
1670 assert(stage
== MESA_SHADER_TESS_EVAL
);
1672 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1674 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1676 /* Rewrite all ATTR file references to HW_REGs. */
1677 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1678 convert_attr_sources_to_hw_regs(inst
);
1683 fs_visitor::assign_gs_urb_setup()
1685 assert(stage
== MESA_SHADER_GEOMETRY
);
1687 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1689 first_non_payload_grf
+=
1690 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1692 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1693 /* Rewrite all ATTR file references to GRFs. */
1694 convert_attr_sources_to_hw_regs(inst
);
1700 * Split large virtual GRFs into separate components if we can.
1702 * This is mostly duplicated with what brw_fs_vector_splitting does,
1703 * but that's really conservative because it's afraid of doing
1704 * splitting that doesn't result in real progress after the rest of
1705 * the optimization phases, which would cause infinite looping in
1706 * optimization. We can do it once here, safely. This also has the
1707 * opportunity to split interpolated values, or maybe even uniforms,
1708 * which we don't have at the IR level.
1710 * We want to split, because virtual GRFs are what we register
1711 * allocate and spill (due to contiguousness requirements for some
1712 * instructions), and they're what we naturally generate in the
1713 * codegen process, but most virtual GRFs don't actually need to be
1714 * contiguous sets of GRFs. If we split, we'll end up with reduced
1715 * live intervals and better dead code elimination and coalescing.
1718 fs_visitor::split_virtual_grfs()
1720 /* Compact the register file so we eliminate dead vgrfs. This
1721 * only defines split points for live registers, so if we have
1722 * too large dead registers they will hit assertions later.
1724 compact_virtual_grfs();
1726 int num_vars
= this->alloc
.count
;
1728 /* Count the total number of registers */
1730 int vgrf_to_reg
[num_vars
];
1731 for (int i
= 0; i
< num_vars
; i
++) {
1732 vgrf_to_reg
[i
] = reg_count
;
1733 reg_count
+= alloc
.sizes
[i
];
1736 /* An array of "split points". For each register slot, this indicates
1737 * if this slot can be separated from the previous slot. Every time an
1738 * instruction uses multiple elements of a register (as a source or
1739 * destination), we mark the used slots as inseparable. Then we go
1740 * through and split the registers into the smallest pieces we can.
1742 bool split_points
[reg_count
];
1743 memset(split_points
, 0, sizeof(split_points
));
1745 /* Mark all used registers as fully splittable */
1746 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1747 if (inst
->dst
.file
== VGRF
) {
1748 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1749 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1750 split_points
[reg
+ j
] = true;
1753 for (int i
= 0; i
< inst
->sources
; i
++) {
1754 if (inst
->src
[i
].file
== VGRF
) {
1755 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1756 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1757 split_points
[reg
+ j
] = true;
1762 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1763 if (inst
->dst
.file
== VGRF
) {
1764 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1765 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1766 split_points
[reg
+ j
] = false;
1768 for (int i
= 0; i
< inst
->sources
; i
++) {
1769 if (inst
->src
[i
].file
== VGRF
) {
1770 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1771 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1772 split_points
[reg
+ j
] = false;
1777 int new_virtual_grf
[reg_count
];
1778 int new_reg_offset
[reg_count
];
1781 for (int i
= 0; i
< num_vars
; i
++) {
1782 /* The first one should always be 0 as a quick sanity check. */
1783 assert(split_points
[reg
] == false);
1786 new_reg_offset
[reg
] = 0;
1791 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1792 /* If this is a split point, reset the offset to 0 and allocate a
1793 * new virtual GRF for the previous offset many registers
1795 if (split_points
[reg
]) {
1796 assert(offset
<= MAX_VGRF_SIZE
);
1797 int grf
= alloc
.allocate(offset
);
1798 for (int k
= reg
- offset
; k
< reg
; k
++)
1799 new_virtual_grf
[k
] = grf
;
1802 new_reg_offset
[reg
] = offset
;
1807 /* The last one gets the original register number */
1808 assert(offset
<= MAX_VGRF_SIZE
);
1809 alloc
.sizes
[i
] = offset
;
1810 for (int k
= reg
- offset
; k
< reg
; k
++)
1811 new_virtual_grf
[k
] = i
;
1813 assert(reg
== reg_count
);
1815 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1816 if (inst
->dst
.file
== VGRF
) {
1817 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1818 inst
->dst
.nr
= new_virtual_grf
[reg
];
1819 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1820 inst
->dst
.offset
% REG_SIZE
;
1821 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1823 for (int i
= 0; i
< inst
->sources
; i
++) {
1824 if (inst
->src
[i
].file
== VGRF
) {
1825 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1826 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1827 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1828 inst
->src
[i
].offset
% REG_SIZE
;
1829 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1833 invalidate_live_intervals();
1837 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1839 * During code generation, we create tons of temporary variables, many of
1840 * which get immediately killed and are never used again. Yet, in later
1841 * optimization and analysis passes, such as compute_live_intervals, we need
1842 * to loop over all the virtual GRFs. Compacting them can save a lot of
1846 fs_visitor::compact_virtual_grfs()
1848 bool progress
= false;
1849 int remap_table
[this->alloc
.count
];
1850 memset(remap_table
, -1, sizeof(remap_table
));
1852 /* Mark which virtual GRFs are used. */
1853 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1854 if (inst
->dst
.file
== VGRF
)
1855 remap_table
[inst
->dst
.nr
] = 0;
1857 for (int i
= 0; i
< inst
->sources
; i
++) {
1858 if (inst
->src
[i
].file
== VGRF
)
1859 remap_table
[inst
->src
[i
].nr
] = 0;
1863 /* Compact the GRF arrays. */
1865 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1866 if (remap_table
[i
] == -1) {
1867 /* We just found an unused register. This means that we are
1868 * actually going to compact something.
1872 remap_table
[i
] = new_index
;
1873 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1874 invalidate_live_intervals();
1879 this->alloc
.count
= new_index
;
1881 /* Patch all the instructions to use the newly renumbered registers */
1882 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1883 if (inst
->dst
.file
== VGRF
)
1884 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1886 for (int i
= 0; i
< inst
->sources
; i
++) {
1887 if (inst
->src
[i
].file
== VGRF
)
1888 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1892 /* Patch all the references to delta_xy, since they're used in register
1893 * allocation. If they're unused, switch them to BAD_FILE so we don't
1894 * think some random VGRF is delta_xy.
1896 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1897 if (delta_xy
[i
].file
== VGRF
) {
1898 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1899 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1901 delta_xy
[i
].file
= BAD_FILE
;
1910 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
,
1911 unsigned *max_chunk_bitsize
,
1912 bool contiguous
, unsigned bitsize
,
1913 const unsigned target_bitsize
,
1914 int *push_constant_loc
, int *pull_constant_loc
,
1915 unsigned *num_push_constants
,
1916 unsigned *num_pull_constants
,
1917 const unsigned max_push_components
,
1918 const unsigned max_chunk_size
,
1919 bool allow_pull_constants
,
1920 struct brw_stage_prog_data
*stage_prog_data
)
1922 /* This is the first live uniform in the chunk */
1923 if (*chunk_start
< 0)
1924 *chunk_start
= uniform
;
1926 /* Keep track of the maximum bit size access in contiguous uniforms */
1927 *max_chunk_bitsize
= MAX2(*max_chunk_bitsize
, bitsize
);
1929 /* If this element does not need to be contiguous with the next, we
1930 * split at this point and everything between chunk_start and u forms a
1934 /* If bitsize doesn't match the target one, skip it */
1935 if (*max_chunk_bitsize
!= target_bitsize
) {
1936 /* FIXME: right now we only support 32 and 64-bit accesses */
1937 assert(*max_chunk_bitsize
== 4 || *max_chunk_bitsize
== 8);
1938 *max_chunk_bitsize
= 0;
1943 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1945 /* Decide whether we should push or pull this parameter. In the
1946 * Vulkan driver, push constants are explicitly exposed via the API
1947 * so we push everything. In GL, we only push small arrays.
1949 if (!allow_pull_constants
||
1950 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1951 chunk_size
<= max_chunk_size
)) {
1952 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1953 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1954 push_constant_loc
[j
] = (*num_push_constants
)++;
1956 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1957 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1960 *max_chunk_bitsize
= 0;
1966 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
1968 if (prog_data
->nr_params
== 0)
1971 /* The local thread id is always the last parameter in the list */
1972 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
1973 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
1974 return prog_data
->nr_params
- 1;
1980 * Assign UNIFORM file registers to either push constants or pull constants.
1982 * We allow a fragment shader to have more than the specified minimum
1983 * maximum number of fragment shader uniform components (64). If
1984 * there are too many of these, they'd fill up all of register space.
1985 * So, this will push some of them out to the pull constant buffer and
1986 * update the program to load them.
1989 fs_visitor::assign_constant_locations()
1991 /* Only the first compile gets to decide on locations. */
1992 if (push_constant_loc
) {
1993 assert(pull_constant_loc
);
1997 bool is_live
[uniforms
];
1998 memset(is_live
, 0, sizeof(is_live
));
1999 unsigned bitsize_access
[uniforms
];
2000 memset(bitsize_access
, 0, sizeof(bitsize_access
));
2002 /* For each uniform slot, a value of true indicates that the given slot and
2003 * the next slot must remain contiguous. This is used to keep us from
2004 * splitting arrays and 64-bit values apart.
2006 bool contiguous
[uniforms
];
2007 memset(contiguous
, 0, sizeof(contiguous
));
2009 /* First, we walk through the instructions and do two things:
2011 * 1) Figure out which uniforms are live.
2013 * 2) Mark any indirectly used ranges of registers as contiguous.
2015 * Note that we don't move constant-indexed accesses to arrays. No
2016 * testing has been done of the performance impact of this choice.
2018 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2019 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2020 if (inst
->src
[i
].file
!= UNIFORM
)
2023 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
2025 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2026 assert(inst
->src
[2].ud
% 4 == 0);
2027 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
2028 assert(last
< uniforms
);
2030 for (unsigned j
= constant_nr
; j
< last
; j
++) {
2032 contiguous
[j
] = true;
2033 bitsize_access
[j
] = MAX2(bitsize_access
[j
], type_sz(inst
->src
[i
].type
));
2035 is_live
[last
] = true;
2036 bitsize_access
[last
] = MAX2(bitsize_access
[last
], type_sz(inst
->src
[i
].type
));
2038 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2039 int regs_read
= inst
->components_read(i
) *
2040 type_sz(inst
->src
[i
].type
) / 4;
2041 assert(regs_read
<= 2);
2043 contiguous
[constant_nr
] = true;
2044 for (int j
= 0; j
< regs_read
; j
++) {
2045 is_live
[constant_nr
+ j
] = true;
2046 bitsize_access
[constant_nr
+ j
] =
2047 MAX2(bitsize_access
[constant_nr
+ j
], type_sz(inst
->src
[i
].type
));
2054 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2056 /* Only allow 16 registers (128 uniform components) as push constants.
2058 * Just demote the end of the list. We could probably do better
2059 * here, demoting things that are rarely used in the program first.
2061 * If changing this value, note the limitation about total_regs in
2064 unsigned int max_push_components
= 16 * 8;
2065 if (subgroup_id_index
>= 0)
2066 max_push_components
--; /* Save a slot for the thread ID */
2068 /* We push small arrays, but no bigger than 16 floats. This is big enough
2069 * for a vec4 but hopefully not large enough to push out other stuff. We
2070 * should probably use a better heuristic at some point.
2072 const unsigned int max_chunk_size
= 16;
2074 unsigned int num_push_constants
= 0;
2075 unsigned int num_pull_constants
= 0;
2077 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2078 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2080 /* Default to -1 meaning no location */
2081 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2082 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2084 int chunk_start
= -1;
2085 unsigned max_chunk_bitsize
= 0;
2087 /* First push 64-bit uniforms to ensure they are properly aligned */
2088 const unsigned uniform_64_bit_size
= type_sz(BRW_REGISTER_TYPE_DF
);
2089 for (unsigned u
= 0; u
< uniforms
; u
++) {
2093 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2094 contiguous
[u
], bitsize_access
[u
],
2095 uniform_64_bit_size
,
2096 push_constant_loc
, pull_constant_loc
,
2097 &num_push_constants
, &num_pull_constants
,
2098 max_push_components
, max_chunk_size
,
2099 compiler
->supports_pull_constants
,
2104 /* Then push the rest of uniforms */
2105 const unsigned uniform_32_bit_size
= type_sz(BRW_REGISTER_TYPE_F
);
2106 for (unsigned u
= 0; u
< uniforms
; u
++) {
2110 /* Skip subgroup_id_index to put it in the last push register. */
2111 if (subgroup_id_index
== (int)u
)
2114 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2115 contiguous
[u
], bitsize_access
[u
],
2116 uniform_32_bit_size
,
2117 push_constant_loc
, pull_constant_loc
,
2118 &num_push_constants
, &num_pull_constants
,
2119 max_push_components
, max_chunk_size
,
2120 compiler
->supports_pull_constants
,
2124 /* Add the CS local thread ID uniform at the end of the push constants */
2125 if (subgroup_id_index
>= 0)
2126 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2128 /* As the uniforms are going to be reordered, stash the old array and
2129 * create two new arrays for push/pull params.
2131 uint32_t *param
= stage_prog_data
->param
;
2132 stage_prog_data
->nr_params
= num_push_constants
;
2133 if (num_push_constants
) {
2134 stage_prog_data
->param
= ralloc_array(mem_ctx
, uint32_t,
2135 num_push_constants
);
2137 stage_prog_data
->param
= NULL
;
2139 assert(stage_prog_data
->nr_pull_params
== 0);
2140 assert(stage_prog_data
->pull_param
== NULL
);
2141 if (num_pull_constants
> 0) {
2142 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2143 stage_prog_data
->pull_param
= ralloc_array(mem_ctx
, uint32_t,
2144 num_pull_constants
);
2147 /* Now that we know how many regular uniforms we'll push, reduce the
2148 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2150 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2151 for (int i
= 0; i
< 4; i
++) {
2152 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2154 if (push_length
+ range
->length
> 64)
2155 range
->length
= 64 - push_length
;
2157 push_length
+= range
->length
;
2159 assert(push_length
<= 64);
2161 /* Up until now, the param[] array has been indexed by reg + offset
2162 * of UNIFORM registers. Move pull constants into pull_param[] and
2163 * condense param[] to only contain the uniforms we chose to push.
2165 * NOTE: Because we are condensing the params[] array, we know that
2166 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2167 * having to make a copy.
2169 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2170 uint32_t value
= param
[i
];
2171 if (pull_constant_loc
[i
] != -1) {
2172 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2173 } else if (push_constant_loc
[i
] != -1) {
2174 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2181 fs_visitor::get_pull_locs(const fs_reg
&src
,
2182 unsigned *out_surf_index
,
2183 unsigned *out_pull_index
)
2185 assert(src
.file
== UNIFORM
);
2187 if (src
.nr
>= UBO_START
) {
2188 const struct brw_ubo_range
*range
=
2189 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2191 /* If this access is in our (reduced) range, use the push data. */
2192 if (src
.offset
/ 32 < range
->length
)
2195 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2196 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2200 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2202 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2203 /* A regular uniform push constant */
2204 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2205 *out_pull_index
= pull_constant_loc
[location
];
2213 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2214 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2217 fs_visitor::lower_constant_loads()
2219 unsigned index
, pull_index
;
2221 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2222 /* Set up the annotation tracking for new generated instructions. */
2223 const fs_builder
ibld(this, block
, inst
);
2225 for (int i
= 0; i
< inst
->sources
; i
++) {
2226 if (inst
->src
[i
].file
!= UNIFORM
)
2229 /* We'll handle this case later */
2230 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2233 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2236 assert(inst
->src
[i
].stride
== 0);
2238 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2239 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2240 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2241 const unsigned base
= pull_index
* 4;
2243 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2244 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2246 /* Rewrite the instruction to use the temporary VGRF. */
2247 inst
->src
[i
].file
= VGRF
;
2248 inst
->src
[i
].nr
= dst
.nr
;
2249 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2250 inst
->src
[i
].offset
% 4;
2252 brw_mark_surface_used(prog_data
, index
);
2255 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2256 inst
->src
[0].file
== UNIFORM
) {
2258 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2261 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2265 inst
->remove(block
);
2267 brw_mark_surface_used(prog_data
, index
);
2270 invalidate_live_intervals();
2274 fs_visitor::opt_algebraic()
2276 bool progress
= false;
2278 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2279 switch (inst
->opcode
) {
2280 case BRW_OPCODE_MOV
:
2281 if (inst
->src
[0].file
!= IMM
)
2284 if (inst
->saturate
) {
2285 if (inst
->dst
.type
!= inst
->src
[0].type
)
2286 assert(!"unimplemented: saturate mixed types");
2288 if (brw_saturate_immediate(inst
->dst
.type
,
2289 &inst
->src
[0].as_brw_reg())) {
2290 inst
->saturate
= false;
2296 case BRW_OPCODE_MUL
:
2297 if (inst
->src
[1].file
!= IMM
)
2301 if (inst
->src
[1].is_one()) {
2302 inst
->opcode
= BRW_OPCODE_MOV
;
2303 inst
->src
[1] = reg_undef
;
2309 if (inst
->src
[1].is_negative_one()) {
2310 inst
->opcode
= BRW_OPCODE_MOV
;
2311 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2312 inst
->src
[1] = reg_undef
;
2318 if (inst
->src
[1].is_zero()) {
2319 inst
->opcode
= BRW_OPCODE_MOV
;
2320 inst
->src
[0] = inst
->src
[1];
2321 inst
->src
[1] = reg_undef
;
2326 if (inst
->src
[0].file
== IMM
) {
2327 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2328 inst
->opcode
= BRW_OPCODE_MOV
;
2329 inst
->src
[0].f
*= inst
->src
[1].f
;
2330 inst
->src
[1] = reg_undef
;
2335 case BRW_OPCODE_ADD
:
2336 if (inst
->src
[1].file
!= IMM
)
2340 if (inst
->src
[1].is_zero()) {
2341 inst
->opcode
= BRW_OPCODE_MOV
;
2342 inst
->src
[1] = reg_undef
;
2347 if (inst
->src
[0].file
== IMM
) {
2348 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2349 inst
->opcode
= BRW_OPCODE_MOV
;
2350 inst
->src
[0].f
+= inst
->src
[1].f
;
2351 inst
->src
[1] = reg_undef
;
2357 if (inst
->src
[0].equals(inst
->src
[1])) {
2358 inst
->opcode
= BRW_OPCODE_MOV
;
2359 inst
->src
[1] = reg_undef
;
2364 case BRW_OPCODE_LRP
:
2365 if (inst
->src
[1].equals(inst
->src
[2])) {
2366 inst
->opcode
= BRW_OPCODE_MOV
;
2367 inst
->src
[0] = inst
->src
[1];
2368 inst
->src
[1] = reg_undef
;
2369 inst
->src
[2] = reg_undef
;
2374 case BRW_OPCODE_CMP
:
2375 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2377 inst
->src
[0].negate
&&
2378 inst
->src
[1].is_zero()) {
2379 inst
->src
[0].abs
= false;
2380 inst
->src
[0].negate
= false;
2381 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2386 case BRW_OPCODE_SEL
:
2387 if (inst
->src
[0].equals(inst
->src
[1])) {
2388 inst
->opcode
= BRW_OPCODE_MOV
;
2389 inst
->src
[1] = reg_undef
;
2390 inst
->predicate
= BRW_PREDICATE_NONE
;
2391 inst
->predicate_inverse
= false;
2393 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2394 switch (inst
->conditional_mod
) {
2395 case BRW_CONDITIONAL_LE
:
2396 case BRW_CONDITIONAL_L
:
2397 switch (inst
->src
[1].type
) {
2398 case BRW_REGISTER_TYPE_F
:
2399 if (inst
->src
[1].f
>= 1.0f
) {
2400 inst
->opcode
= BRW_OPCODE_MOV
;
2401 inst
->src
[1] = reg_undef
;
2402 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2410 case BRW_CONDITIONAL_GE
:
2411 case BRW_CONDITIONAL_G
:
2412 switch (inst
->src
[1].type
) {
2413 case BRW_REGISTER_TYPE_F
:
2414 if (inst
->src
[1].f
<= 0.0f
) {
2415 inst
->opcode
= BRW_OPCODE_MOV
;
2416 inst
->src
[1] = reg_undef
;
2417 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2429 case BRW_OPCODE_MAD
:
2430 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2431 inst
->opcode
= BRW_OPCODE_MOV
;
2432 inst
->src
[1] = reg_undef
;
2433 inst
->src
[2] = reg_undef
;
2435 } else if (inst
->src
[0].is_zero()) {
2436 inst
->opcode
= BRW_OPCODE_MUL
;
2437 inst
->src
[0] = inst
->src
[2];
2438 inst
->src
[2] = reg_undef
;
2440 } else if (inst
->src
[1].is_one()) {
2441 inst
->opcode
= BRW_OPCODE_ADD
;
2442 inst
->src
[1] = inst
->src
[2];
2443 inst
->src
[2] = reg_undef
;
2445 } else if (inst
->src
[2].is_one()) {
2446 inst
->opcode
= BRW_OPCODE_ADD
;
2447 inst
->src
[2] = reg_undef
;
2449 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2450 inst
->opcode
= BRW_OPCODE_ADD
;
2451 inst
->src
[1].f
*= inst
->src
[2].f
;
2452 inst
->src
[2] = reg_undef
;
2456 case SHADER_OPCODE_BROADCAST
:
2457 if (is_uniform(inst
->src
[0])) {
2458 inst
->opcode
= BRW_OPCODE_MOV
;
2460 inst
->force_writemask_all
= true;
2462 } else if (inst
->src
[1].file
== IMM
) {
2463 inst
->opcode
= BRW_OPCODE_MOV
;
2464 /* It's possible that the selected component will be too large and
2465 * overflow the register. This can happen if someone does a
2466 * readInvocation() from GLSL or SPIR-V and provides an OOB
2467 * invocationIndex. If this happens and we some how manage
2468 * to constant fold it in and get here, then component() may cause
2469 * us to start reading outside of the VGRF which will lead to an
2470 * assert later. Instead, just let it wrap around if it goes over
2473 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2474 inst
->src
[0] = component(inst
->src
[0], comp
);
2476 inst
->force_writemask_all
= true;
2485 /* Swap if src[0] is immediate. */
2486 if (progress
&& inst
->is_commutative()) {
2487 if (inst
->src
[0].file
== IMM
) {
2488 fs_reg tmp
= inst
->src
[1];
2489 inst
->src
[1] = inst
->src
[0];
2498 * Optimize sample messages that have constant zero values for the trailing
2499 * texture coordinates. We can just reduce the message length for these
2500 * instructions instead of reserving a register for it. Trailing parameters
2501 * that aren't sent default to zero anyway. This will cause the dead code
2502 * eliminator to remove the MOV instruction that would otherwise be emitted to
2503 * set up the zero value.
2506 fs_visitor::opt_zero_samples()
2508 /* Gen4 infers the texturing opcode based on the message length so we can't
2511 if (devinfo
->gen
< 5)
2514 bool progress
= false;
2516 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2517 if (!inst
->is_tex())
2520 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2522 if (load_payload
->is_head_sentinel() ||
2523 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2526 /* We don't want to remove the message header or the first parameter.
2527 * Removing the first parameter is not allowed, see the Haswell PRM
2528 * volume 7, page 149:
2530 * "Parameter 0 is required except for the sampleinfo message, which
2531 * has no parameter 0"
2533 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2534 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2535 (inst
->exec_size
/ 8) +
2536 inst
->header_size
- 1].is_zero()) {
2537 inst
->mlen
-= inst
->exec_size
/ 8;
2543 invalidate_live_intervals();
2549 * Optimize sample messages which are followed by the final RT write.
2551 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2552 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2553 * final texturing results copied to the framebuffer write payload and modify
2554 * them to write to the framebuffer directly.
2557 fs_visitor::opt_sampler_eot()
2559 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2561 if (stage
!= MESA_SHADER_FRAGMENT
)
2564 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2567 /* FINISHME: It should be possible to implement this optimization when there
2568 * are multiple drawbuffers.
2570 if (key
->nr_color_regions
!= 1)
2573 /* Requires emitting a bunch of saturating MOV instructions during logical
2574 * send lowering to clamp the color payload, which the sampler unit isn't
2575 * going to do for us.
2577 if (key
->clamp_fragment_color
)
2580 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2581 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2582 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2583 assert(fb_write
->eot
);
2584 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2586 /* There wasn't one; nothing to do. */
2587 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2590 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2592 /* 3D Sampler » Messages » Message Format
2594 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2595 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2597 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2598 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2599 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2600 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2601 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2602 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2603 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2604 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2607 /* XXX - This shouldn't be necessary. */
2608 if (tex_inst
->prev
->is_head_sentinel())
2611 /* Check that the FB write sources are fully initialized by the single
2612 * texturing instruction.
2614 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2615 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2616 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2617 fb_write
->size_read(i
) != tex_inst
->size_written
)
2619 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2620 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2625 assert(!tex_inst
->eot
); /* We can't get here twice */
2626 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2628 const fs_builder
ibld(this, block
, tex_inst
);
2630 tex_inst
->offset
|= fb_write
->target
<< 24;
2631 tex_inst
->eot
= true;
2632 tex_inst
->dst
= ibld
.null_reg_ud();
2633 tex_inst
->size_written
= 0;
2634 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2636 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2637 * flag and submit a header together with the sampler message as required
2640 invalidate_live_intervals();
2645 fs_visitor::opt_register_renaming()
2647 bool progress
= false;
2650 int remap
[alloc
.count
];
2651 memset(remap
, -1, sizeof(int) * alloc
.count
);
2653 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2654 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2656 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2657 inst
->opcode
== BRW_OPCODE_WHILE
) {
2661 /* Rewrite instruction sources. */
2662 for (int i
= 0; i
< inst
->sources
; i
++) {
2663 if (inst
->src
[i
].file
== VGRF
&&
2664 remap
[inst
->src
[i
].nr
] != -1 &&
2665 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2666 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2671 const int dst
= inst
->dst
.nr
;
2674 inst
->dst
.file
== VGRF
&&
2675 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2676 !inst
->is_partial_write()) {
2677 if (remap
[dst
] == -1) {
2680 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2681 inst
->dst
.nr
= remap
[dst
];
2684 } else if (inst
->dst
.file
== VGRF
&&
2686 remap
[dst
] != dst
) {
2687 inst
->dst
.nr
= remap
[dst
];
2693 invalidate_live_intervals();
2695 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2696 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2697 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2706 * Remove redundant or useless discard jumps.
2708 * For example, we can eliminate jumps in the following sequence:
2710 * discard-jump (redundant with the next jump)
2711 * discard-jump (useless; jumps to the next instruction)
2715 fs_visitor::opt_redundant_discard_jumps()
2717 bool progress
= false;
2719 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2721 fs_inst
*placeholder_halt
= NULL
;
2722 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2723 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2724 placeholder_halt
= inst
;
2729 if (!placeholder_halt
)
2732 /* Delete any HALTs immediately before the placeholder halt. */
2733 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2734 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2735 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2736 prev
->remove(last_bblock
);
2741 invalidate_live_intervals();
2747 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2748 * from \p r.offset which overlaps the region starting at \p s.offset and
2749 * spanning \p ds bytes.
2751 static inline unsigned
2752 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2754 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2755 const int shift
= rel_offset
/ REG_SIZE
;
2756 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2757 assert(reg_space(r
) == reg_space(s
) &&
2758 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2759 return ((1 << n
) - 1) << shift
;
2763 fs_visitor::compute_to_mrf()
2765 bool progress
= false;
2768 /* No MRFs on Gen >= 7. */
2769 if (devinfo
->gen
>= 7)
2772 calculate_live_intervals();
2774 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2778 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2779 inst
->is_partial_write() ||
2780 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2781 inst
->dst
.type
!= inst
->src
[0].type
||
2782 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2783 !inst
->src
[0].is_contiguous() ||
2784 inst
->src
[0].offset
% REG_SIZE
!= 0)
2787 /* Can't compute-to-MRF this GRF if someone else was going to
2790 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2793 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2794 * things that computed the value of all GRFs of the source region. The
2795 * regs_left bitset keeps track of the registers we haven't yet found a
2796 * generating instruction for.
2798 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2800 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2801 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2802 inst
->src
[0], inst
->size_read(0))) {
2803 /* Found the last thing to write our reg we want to turn
2804 * into a compute-to-MRF.
2807 /* If this one instruction didn't populate all the
2808 * channels, bail. We might be able to rewrite everything
2809 * that writes that reg, but it would require smarter
2812 if (scan_inst
->is_partial_write())
2815 /* Handling things not fully contained in the source of the copy
2816 * would need us to understand coalescing out more than one MOV at
2819 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
2820 inst
->src
[0], inst
->size_read(0)))
2823 /* SEND instructions can't have MRF as a destination. */
2824 if (scan_inst
->mlen
)
2827 if (devinfo
->gen
== 6) {
2828 /* gen6 math instructions must have the destination be
2829 * GRF, so no compute-to-MRF for them.
2831 if (scan_inst
->is_math()) {
2836 /* Clear the bits for any registers this instruction overwrites. */
2837 regs_left
&= ~mask_relative_to(
2838 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2843 /* We don't handle control flow here. Most computation of
2844 * values that end up in MRFs are shortly before the MRF
2847 if (block
->start() == scan_inst
)
2850 /* You can't read from an MRF, so if someone else reads our
2851 * MRF's source GRF that we wanted to rewrite, that stops us.
2853 bool interfered
= false;
2854 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2855 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2856 inst
->src
[0], inst
->size_read(0))) {
2863 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2864 inst
->dst
, inst
->size_written
)) {
2865 /* If somebody else writes our MRF here, we can't
2866 * compute-to-MRF before that.
2871 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2872 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2873 inst
->dst
, inst
->size_written
)) {
2874 /* Found a SEND instruction, which means that there are
2875 * live values in MRFs from base_mrf to base_mrf +
2876 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2886 /* Found all generating instructions of our MRF's source value, so it
2887 * should be safe to rewrite them to point to the MRF directly.
2889 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2891 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2892 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2893 inst
->src
[0], inst
->size_read(0))) {
2894 /* Clear the bits for any registers this instruction overwrites. */
2895 regs_left
&= ~mask_relative_to(
2896 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2898 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
2899 reg_offset(inst
->src
[0]);
2901 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2902 /* Apply the same address transformation done by the hardware
2903 * for COMPR4 MRF writes.
2905 assert(rel_offset
< 2 * REG_SIZE
);
2906 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
2908 /* Clear the COMPR4 bit if the generating instruction is not
2911 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2912 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2915 /* Calculate the MRF number the result of this instruction is
2916 * ultimately written to.
2918 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
2921 scan_inst
->dst
.file
= MRF
;
2922 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
2923 scan_inst
->saturate
|= inst
->saturate
;
2930 inst
->remove(block
);
2935 invalidate_live_intervals();
2941 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2942 * flow. We could probably do better here with some form of divergence
2946 fs_visitor::eliminate_find_live_channel()
2948 bool progress
= false;
2951 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
2952 /* The optimization below assumes that channel zero is live on thread
2953 * dispatch, which may not be the case if the fixed function dispatches
2959 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2960 switch (inst
->opcode
) {
2966 case BRW_OPCODE_ENDIF
:
2967 case BRW_OPCODE_WHILE
:
2971 case FS_OPCODE_DISCARD_JUMP
:
2972 /* This can potentially make control flow non-uniform until the end
2977 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2979 inst
->opcode
= BRW_OPCODE_MOV
;
2980 inst
->src
[0] = brw_imm_ud(0u);
2982 inst
->force_writemask_all
= true;
2996 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2997 * instructions to FS_OPCODE_REP_FB_WRITE.
3000 fs_visitor::emit_repclear_shader()
3002 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3004 int color_mrf
= base_mrf
+ 2;
3008 mov
= bld
.exec_all().group(4, 0)
3009 .MOV(brw_message_reg(color_mrf
),
3010 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3012 struct brw_reg reg
=
3013 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3014 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3015 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3017 mov
= bld
.exec_all().group(4, 0)
3018 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3022 if (key
->nr_color_regions
== 1) {
3023 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3024 write
->saturate
= key
->clamp_fragment_color
;
3025 write
->base_mrf
= color_mrf
;
3027 write
->header_size
= 0;
3030 assume(key
->nr_color_regions
> 0);
3031 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3032 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3033 write
->saturate
= key
->clamp_fragment_color
;
3034 write
->base_mrf
= base_mrf
;
3036 write
->header_size
= 2;
3044 assign_constant_locations();
3045 assign_curb_setup();
3047 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3049 assert(mov
->src
[0].file
== FIXED_GRF
);
3050 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3055 * Walks through basic blocks, looking for repeated MRF writes and
3056 * removing the later ones.
3059 fs_visitor::remove_duplicate_mrf_writes()
3061 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3062 bool progress
= false;
3064 /* Need to update the MRF tracking for compressed instructions. */
3065 if (dispatch_width
>= 16)
3068 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3070 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3071 if (inst
->is_control_flow()) {
3072 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3075 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3076 inst
->dst
.file
== MRF
) {
3077 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3078 if (prev_inst
&& inst
->equals(prev_inst
)) {
3079 inst
->remove(block
);
3085 /* Clear out the last-write records for MRFs that were overwritten. */
3086 if (inst
->dst
.file
== MRF
) {
3087 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3090 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3091 /* Found a SEND instruction, which will include two or fewer
3092 * implied MRF writes. We could do better here.
3094 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3095 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3099 /* Clear out any MRF move records whose sources got overwritten. */
3100 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3101 if (last_mrf_move
[i
] &&
3102 regions_overlap(inst
->dst
, inst
->size_written
,
3103 last_mrf_move
[i
]->src
[0],
3104 last_mrf_move
[i
]->size_read(0))) {
3105 last_mrf_move
[i
] = NULL
;
3109 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3110 inst
->dst
.file
== MRF
&&
3111 inst
->src
[0].file
!= ARF
&&
3112 !inst
->is_partial_write()) {
3113 last_mrf_move
[inst
->dst
.nr
] = inst
;
3118 invalidate_live_intervals();
3124 * Rounding modes for conversion instructions are included for each
3125 * conversion, but right now it is a state. So once it is set,
3126 * we don't need to call it again for subsequent calls.
3128 * This is useful for vector/matrices conversions, as setting the
3129 * mode once is enough for the full vector/matrix
3132 fs_visitor::remove_extra_rounding_modes()
3134 bool progress
= false;
3136 foreach_block (block
, cfg
) {
3137 brw_rnd_mode prev_mode
= BRW_RND_MODE_UNSPECIFIED
;
3139 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3140 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3141 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3142 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3143 if (mode
== prev_mode
) {
3144 inst
->remove(block
);
3154 invalidate_live_intervals();
3160 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3162 /* Clear the flag for registers that actually got read (as expected). */
3163 for (int i
= 0; i
< inst
->sources
; i
++) {
3165 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3166 grf
= inst
->src
[i
].nr
;
3171 if (grf
>= first_grf
&&
3172 grf
< first_grf
+ grf_len
) {
3173 deps
[grf
- first_grf
] = false;
3174 if (inst
->exec_size
== 16)
3175 deps
[grf
- first_grf
+ 1] = false;
3181 * Implements this workaround for the original 965:
3183 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3184 * check for post destination dependencies on this instruction, software
3185 * must ensure that there is no destination hazard for the case of ‘write
3186 * followed by a posted write’ shown in the following example.
3189 * 2. send r3.xy <rest of send instruction>
3192 * Due to no post-destination dependency check on the ‘send’, the above
3193 * code sequence could have two instructions (1 and 2) in flight at the
3194 * same time that both consider ‘r3’ as the target of their final writes.
3197 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3200 int write_len
= regs_written(inst
);
3201 int first_write_grf
= inst
->dst
.nr
;
3202 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3203 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3205 memset(needs_dep
, false, sizeof(needs_dep
));
3206 memset(needs_dep
, true, write_len
);
3208 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3210 /* Walk backwards looking for writes to registers we're writing which
3211 * aren't read since being written. If we hit the start of the program,
3212 * we assume that there are no outstanding dependencies on entry to the
3215 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3216 /* If we hit control flow, assume that there *are* outstanding
3217 * dependencies, and force their cleanup before our instruction.
3219 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3220 for (int i
= 0; i
< write_len
; i
++) {
3222 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3223 first_write_grf
+ i
);
3228 /* We insert our reads as late as possible on the assumption that any
3229 * instruction but a MOV that might have left us an outstanding
3230 * dependency has more latency than a MOV.
3232 if (scan_inst
->dst
.file
== VGRF
) {
3233 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3234 int reg
= scan_inst
->dst
.nr
+ i
;
3236 if (reg
>= first_write_grf
&&
3237 reg
< first_write_grf
+ write_len
&&
3238 needs_dep
[reg
- first_write_grf
]) {
3239 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3240 needs_dep
[reg
- first_write_grf
] = false;
3241 if (scan_inst
->exec_size
== 16)
3242 needs_dep
[reg
- first_write_grf
+ 1] = false;
3247 /* Clear the flag for registers that actually got read (as expected). */
3248 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3250 /* Continue the loop only if we haven't resolved all the dependencies */
3252 for (i
= 0; i
< write_len
; i
++) {
3262 * Implements this workaround for the original 965:
3264 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3265 * used as a destination register until after it has been sourced by an
3266 * instruction with a different destination register.
3269 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3271 int write_len
= regs_written(inst
);
3272 int first_write_grf
= inst
->dst
.nr
;
3273 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3274 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3276 memset(needs_dep
, false, sizeof(needs_dep
));
3277 memset(needs_dep
, true, write_len
);
3278 /* Walk forwards looking for writes to registers we're writing which aren't
3279 * read before being written.
3281 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3282 /* If we hit control flow, force resolve all remaining dependencies. */
3283 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3284 for (int i
= 0; i
< write_len
; i
++) {
3286 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3287 first_write_grf
+ i
);
3292 /* Clear the flag for registers that actually got read (as expected). */
3293 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3295 /* We insert our reads as late as possible since they're reading the
3296 * result of a SEND, which has massive latency.
3298 if (scan_inst
->dst
.file
== VGRF
&&
3299 scan_inst
->dst
.nr
>= first_write_grf
&&
3300 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3301 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3302 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3304 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3307 /* Continue the loop only if we haven't resolved all the dependencies */
3309 for (i
= 0; i
< write_len
; i
++) {
3319 fs_visitor::insert_gen4_send_dependency_workarounds()
3321 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3324 bool progress
= false;
3326 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3327 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3328 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3329 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3335 invalidate_live_intervals();
3339 * Turns the generic expression-style uniform pull constant load instruction
3340 * into a hardware-specific series of instructions for loading a pull
3343 * The expression style allows the CSE pass before this to optimize out
3344 * repeated loads from the same offset, and gives the pre-register-allocation
3345 * scheduling full flexibility, while the conversion to native instructions
3346 * allows the post-register-allocation scheduler the best information
3349 * Note that execution masking for setting up pull constant loads is special:
3350 * the channels that need to be written are unrelated to the current execution
3351 * mask, since a later instruction will use one of the result channels as a
3352 * source operand for all 8 or 16 of its channels.
3355 fs_visitor::lower_uniform_pull_constant_loads()
3357 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3358 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3361 if (devinfo
->gen
>= 7) {
3362 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3363 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3365 ubld
.group(8, 0).MOV(payload
,
3366 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3367 ubld
.group(1, 0).MOV(component(payload
, 2),
3368 brw_imm_ud(inst
->src
[1].ud
/ 16));
3370 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3371 inst
->src
[1] = payload
;
3372 inst
->header_size
= 1;
3375 invalidate_live_intervals();
3377 /* Before register allocation, we didn't tell the scheduler about the
3378 * MRF we use. We know it's safe to use this MRF because nothing
3379 * else does except for register spill/unspill, which generates and
3380 * uses its MRF within a single IR instruction.
3382 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3389 fs_visitor::lower_load_payload()
3391 bool progress
= false;
3393 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3394 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3397 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3398 assert(inst
->saturate
== false);
3399 fs_reg dst
= inst
->dst
;
3401 /* Get rid of COMPR4. We'll add it back in if we need it */
3402 if (dst
.file
== MRF
)
3403 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3405 const fs_builder
ibld(this, block
, inst
);
3406 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3408 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3409 if (inst
->src
[i
].file
!= BAD_FILE
) {
3410 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3411 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3412 hbld
.MOV(mov_dst
, mov_src
);
3414 dst
= offset(dst
, hbld
, 1);
3417 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3418 inst
->exec_size
> 8) {
3419 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3420 * a straightforward copy. Instead, the result of the
3421 * LOAD_PAYLOAD is treated as interleaved and the first four
3422 * non-header sources are unpacked as:
3433 * This is used for gen <= 5 fb writes.
3435 assert(inst
->exec_size
== 16);
3436 assert(inst
->header_size
+ 4 <= inst
->sources
);
3437 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3438 if (inst
->src
[i
].file
!= BAD_FILE
) {
3439 if (devinfo
->has_compr4
) {
3440 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3441 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3442 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3444 /* Platform doesn't have COMPR4. We have to fake it */
3445 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3446 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3448 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3455 /* The loop above only ever incremented us through the first set
3456 * of 4 registers. However, thanks to the magic of COMPR4, we
3457 * actually wrote to the first 8 registers, so we need to take
3458 * that into account now.
3462 /* The COMPR4 code took care of the first 4 sources. We'll let
3463 * the regular path handle any remaining sources. Yes, we are
3464 * modifying the instruction but we're about to delete it so
3465 * this really doesn't hurt anything.
3467 inst
->header_size
+= 4;
3470 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3471 if (inst
->src
[i
].file
!= BAD_FILE
)
3472 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3473 dst
= offset(dst
, ibld
, 1);
3476 inst
->remove(block
);
3481 invalidate_live_intervals();
3487 fs_visitor::lower_integer_multiplication()
3489 bool progress
= false;
3491 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3492 const fs_builder
ibld(this, block
, inst
);
3494 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3495 if (inst
->dst
.is_accumulator() ||
3496 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3497 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3500 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3501 * operation directly, but CHV/BXT cannot.
3503 if (devinfo
->gen
>= 8 &&
3504 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
))
3507 if (inst
->src
[1].file
== IMM
&&
3508 inst
->src
[1].ud
< (1 << 16)) {
3509 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3510 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3513 * If multiplying by an immediate value that fits in 16-bits, do a
3514 * single MUL instruction with that value in the proper location.
3516 if (devinfo
->gen
< 7) {
3517 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3519 ibld
.MOV(imm
, inst
->src
[1]);
3520 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3522 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3523 ibld
.MUL(inst
->dst
, inst
->src
[0],
3524 ud
? brw_imm_uw(inst
->src
[1].ud
)
3525 : brw_imm_w(inst
->src
[1].d
));
3528 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3529 * do 32-bit integer multiplication in one instruction, but instead
3530 * must do a sequence (which actually calculates a 64-bit result):
3532 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3533 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3534 * mov(8) g2<1>D acc0<8,8,1>D
3536 * But on Gen > 6, the ability to use second accumulator register
3537 * (acc1) for non-float data types was removed, preventing a simple
3538 * implementation in SIMD16. A 16-channel result can be calculated by
3539 * executing the three instructions twice in SIMD8, once with quarter
3540 * control of 1Q for the first eight channels and again with 2Q for
3541 * the second eight channels.
3543 * Which accumulator register is implicitly accessed (by AccWrEnable
3544 * for instance) is determined by the quarter control. Unfortunately
3545 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3546 * implicit accumulator access by an instruction with 2Q will access
3547 * acc1 regardless of whether the data type is usable in acc1.
3549 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3550 * integer data types.
3552 * Since we only want the low 32-bits of the result, we can do two
3553 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3554 * adjust the high result and add them (like the mach is doing):
3556 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3557 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3558 * shl(8) g9<1>D g8<8,8,1>D 16D
3559 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3561 * We avoid the shl instruction by realizing that we only want to add
3562 * the low 16-bits of the "high" result to the high 16-bits of the
3563 * "low" result and using proper regioning on the add:
3565 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3566 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3567 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3569 * Since it does not use the (single) accumulator register, we can
3570 * schedule multi-component multiplications much better.
3573 bool needs_mov
= false;
3574 fs_reg orig_dst
= inst
->dst
;
3575 fs_reg low
= inst
->dst
;
3576 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3577 regions_overlap(inst
->dst
, inst
->size_written
,
3578 inst
->src
[0], inst
->size_read(0)) ||
3579 regions_overlap(inst
->dst
, inst
->size_written
,
3580 inst
->src
[1], inst
->size_read(1))) {
3582 low
.nr
= alloc
.allocate(regs_written(inst
));
3583 low
.offset
= low
.offset
% REG_SIZE
;
3586 fs_reg high
= inst
->dst
;
3587 high
.nr
= alloc
.allocate(regs_written(inst
));
3588 high
.offset
= high
.offset
% REG_SIZE
;
3590 if (devinfo
->gen
>= 7) {
3591 if (inst
->src
[1].file
== IMM
) {
3592 ibld
.MUL(low
, inst
->src
[0],
3593 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3594 ibld
.MUL(high
, inst
->src
[0],
3595 brw_imm_uw(inst
->src
[1].ud
>> 16));
3597 ibld
.MUL(low
, inst
->src
[0],
3598 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3599 ibld
.MUL(high
, inst
->src
[0],
3600 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3603 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3605 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3609 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3610 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3611 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3613 if (needs_mov
|| inst
->conditional_mod
) {
3614 set_condmod(inst
->conditional_mod
,
3615 ibld
.MOV(orig_dst
, low
));
3619 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3620 /* Should have been lowered to 8-wide. */
3621 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3622 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3624 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3625 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3627 if (devinfo
->gen
>= 8) {
3628 /* Until Gen8, integer multiplies read 32-bits from one source,
3629 * and 16-bits from the other, and relying on the MACH instruction
3630 * to generate the high bits of the result.
3632 * On Gen8, the multiply instruction does a full 32x32-bit
3633 * multiply, but in order to do a 64-bit multiply we can simulate
3634 * the previous behavior and then use a MACH instruction.
3636 * FINISHME: Don't use source modifiers on src1.
3638 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3639 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3640 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3641 mul
->src
[1].stride
*= 2;
3643 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3645 /* Among other things the quarter control bits influence which
3646 * accumulator register is used by the hardware for instructions
3647 * that access the accumulator implicitly (e.g. MACH). A
3648 * second-half instruction would normally map to acc1, which
3649 * doesn't exist on Gen7 and up (the hardware does emulate it for
3650 * floating-point instructions *only* by taking advantage of the
3651 * extra precision of acc0 not normally used for floating point
3654 * HSW and up are careful enough not to try to access an
3655 * accumulator register that doesn't exist, but on earlier Gen7
3656 * hardware we need to make sure that the quarter control bits are
3657 * zero to avoid non-deterministic behaviour and emit an extra MOV
3658 * to get the result masked correctly according to the current
3662 mach
->force_writemask_all
= true;
3663 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3664 ibld
.MOV(inst
->dst
, mach
->dst
);
3670 inst
->remove(block
);
3675 invalidate_live_intervals();
3681 fs_visitor::lower_minmax()
3683 assert(devinfo
->gen
< 6);
3685 bool progress
= false;
3687 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3688 const fs_builder
ibld(this, block
, inst
);
3690 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3691 inst
->predicate
== BRW_PREDICATE_NONE
) {
3692 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3693 * the original SEL.L/GE instruction
3695 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3696 inst
->conditional_mod
);
3697 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3698 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3705 invalidate_live_intervals();
3711 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3712 fs_reg
*dst
, fs_reg color
, unsigned components
)
3714 if (key
->clamp_fragment_color
) {
3715 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3716 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3718 for (unsigned i
= 0; i
< components
; i
++)
3720 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3725 for (unsigned i
= 0; i
< components
; i
++)
3726 dst
[i
] = offset(color
, bld
, i
);
3730 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3731 const struct brw_wm_prog_data
*prog_data
,
3732 const brw_wm_prog_key
*key
,
3733 const fs_visitor::thread_payload
&payload
)
3735 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3736 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3737 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3738 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3739 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3740 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3741 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3742 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3743 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3744 const unsigned components
=
3745 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3747 /* We can potentially have a message length of up to 15, so we have to set
3748 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3751 int header_size
= 2, payload_header_size
;
3752 unsigned length
= 0;
3754 /* From the Sandy Bridge PRM, volume 4, page 198:
3756 * "Dispatched Pixel Enables. One bit per pixel indicating
3757 * which pixels were originally enabled when the thread was
3758 * dispatched. This field is only required for the end-of-
3759 * thread message and on all dual-source messages."
3761 if (devinfo
->gen
>= 6 &&
3762 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3763 color1
.file
== BAD_FILE
&&
3764 key
->nr_color_regions
== 1) {
3768 if (header_size
!= 0) {
3769 assert(header_size
== 2);
3770 /* Allocate 2 registers for a header */
3774 if (payload
.aa_dest_stencil_reg
) {
3775 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3776 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3777 .MOV(sources
[length
],
3778 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3782 if (sample_mask
.file
!= BAD_FILE
) {
3783 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3784 BRW_REGISTER_TYPE_UD
);
3786 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3787 * relevant. Since it's unsigned single words one vgrf is always
3788 * 16-wide, but only the lower or higher 8 channels will be used by the
3789 * hardware when doing a SIMD8 write depending on whether we have
3790 * selected the subspans for the first or second half respectively.
3792 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3793 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3794 sample_mask
.stride
*= 2;
3796 bld
.exec_all().annotate("FB write oMask")
3797 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3803 payload_header_size
= length
;
3805 if (src0_alpha
.file
!= BAD_FILE
) {
3806 /* FIXME: This is being passed at the wrong location in the payload and
3807 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3808 * It's supposed to be immediately before oMask but there seems to be no
3809 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3810 * requires header sources to form a contiguous segment at the beginning
3811 * of the message and src0_alpha has per-channel semantics.
3813 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3815 } else if (key
->replicate_alpha
&& inst
->target
!= 0) {
3816 /* Handle the case when fragment shader doesn't write to draw buffer
3817 * zero. No need to call setup_color_payload() for src0_alpha because
3818 * alpha value will be undefined.
3823 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3826 if (color1
.file
!= BAD_FILE
) {
3827 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3831 if (src_depth
.file
!= BAD_FILE
) {
3832 sources
[length
] = src_depth
;
3836 if (dst_depth
.file
!= BAD_FILE
) {
3837 sources
[length
] = dst_depth
;
3841 if (src_stencil
.file
!= BAD_FILE
) {
3842 assert(devinfo
->gen
>= 9);
3843 assert(bld
.dispatch_width() != 16);
3845 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3846 * available on gen9+. As such it's impossible to have both enabled at the
3847 * same time and therefore length cannot overrun the array.
3849 assert(length
< 15);
3851 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3852 bld
.exec_all().annotate("FB write OS")
3853 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3854 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3859 if (devinfo
->gen
>= 7) {
3860 /* Send from the GRF */
3861 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3862 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3863 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3864 load
->dst
= payload
;
3866 inst
->src
[0] = payload
;
3867 inst
->resize_sources(1);
3869 /* Send from the MRF */
3870 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3871 sources
, length
, payload_header_size
);
3873 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3874 * will do this for us if we just give it a COMPR4 destination.
3876 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3877 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3879 inst
->resize_sources(0);
3883 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3884 inst
->mlen
= regs_written(load
);
3885 inst
->header_size
= header_size
;
3889 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3891 const fs_builder
&ubld
= bld
.exec_all();
3892 const unsigned length
= 2;
3893 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3896 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3898 inst
->resize_sources(1);
3899 inst
->src
[0] = header
;
3900 inst
->opcode
= FS_OPCODE_FB_READ
;
3901 inst
->mlen
= length
;
3902 inst
->header_size
= length
;
3906 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3907 const fs_reg
&coordinate
,
3908 const fs_reg
&shadow_c
,
3909 const fs_reg
&lod
, const fs_reg
&lod2
,
3910 const fs_reg
&surface
,
3911 const fs_reg
&sampler
,
3912 unsigned coord_components
,
3913 unsigned grad_components
)
3915 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3916 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3917 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3918 fs_reg msg_end
= msg_begin
;
3921 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3923 for (unsigned i
= 0; i
< coord_components
; i
++)
3924 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3925 offset(coordinate
, bld
, i
));
3927 msg_end
= offset(msg_end
, bld
, coord_components
);
3929 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3930 * require all three components to be present and zero if they are unused.
3932 if (coord_components
> 0 &&
3933 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3934 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3935 for (unsigned i
= coord_components
; i
< 3; i
++)
3936 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3938 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3941 if (op
== SHADER_OPCODE_TXD
) {
3942 /* TXD unsupported in SIMD16 mode. */
3943 assert(bld
.dispatch_width() == 8);
3945 /* the slots for u and v are always present, but r is optional */
3946 if (coord_components
< 2)
3947 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3950 * dPdx = dudx, dvdx, drdx
3951 * dPdy = dudy, dvdy, drdy
3953 * 1-arg: Does not exist.
3955 * 2-arg: dudx dvdx dudy dvdy
3956 * dPdx.x dPdx.y dPdy.x dPdy.y
3959 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3960 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3961 * m5 m6 m7 m8 m9 m10
3963 for (unsigned i
= 0; i
< grad_components
; i
++)
3964 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3966 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3968 for (unsigned i
= 0; i
< grad_components
; i
++)
3969 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3971 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3975 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
3976 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
3978 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3979 bld
.dispatch_width() == 16);
3981 const brw_reg_type type
=
3982 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3983 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3984 bld
.MOV(retype(msg_end
, type
), lod
);
3985 msg_end
= offset(msg_end
, bld
, 1);
3988 if (shadow_c
.file
!= BAD_FILE
) {
3989 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3990 /* There's no plain shadow compare message, so we use shadow
3991 * compare with a bias of 0.0.
3993 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3994 msg_end
= offset(msg_end
, bld
, 1);
3997 bld
.MOV(msg_end
, shadow_c
);
3998 msg_end
= offset(msg_end
, bld
, 1);
4002 inst
->src
[0] = reg_undef
;
4003 inst
->src
[1] = surface
;
4004 inst
->src
[2] = sampler
;
4005 inst
->resize_sources(3);
4006 inst
->base_mrf
= msg_begin
.nr
;
4007 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4008 inst
->header_size
= 1;
4012 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4013 const fs_reg
&coordinate
,
4014 const fs_reg
&shadow_c
,
4015 const fs_reg
&lod
, const fs_reg
&lod2
,
4016 const fs_reg
&sample_index
,
4017 const fs_reg
&surface
,
4018 const fs_reg
&sampler
,
4019 unsigned coord_components
,
4020 unsigned grad_components
)
4022 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4023 fs_reg msg_coords
= message
;
4024 unsigned header_size
= 0;
4026 if (inst
->offset
!= 0) {
4027 /* The offsets set up by the visitor are in the m1 header, so we can't
4034 for (unsigned i
= 0; i
< coord_components
; i
++)
4035 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4036 offset(coordinate
, bld
, i
));
4038 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4039 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4041 if (shadow_c
.file
!= BAD_FILE
) {
4042 fs_reg msg_shadow
= msg_lod
;
4043 bld
.MOV(msg_shadow
, shadow_c
);
4044 msg_lod
= offset(msg_shadow
, bld
, 1);
4049 case SHADER_OPCODE_TXL
:
4051 bld
.MOV(msg_lod
, lod
);
4052 msg_end
= offset(msg_lod
, bld
, 1);
4054 case SHADER_OPCODE_TXD
:
4057 * dPdx = dudx, dvdx, drdx
4058 * dPdy = dudy, dvdy, drdy
4060 * Load up these values:
4061 * - dudx dudy dvdx dvdy drdx drdy
4062 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4065 for (unsigned i
= 0; i
< grad_components
; i
++) {
4066 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4067 msg_end
= offset(msg_end
, bld
, 1);
4069 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4070 msg_end
= offset(msg_end
, bld
, 1);
4073 case SHADER_OPCODE_TXS
:
4074 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4075 bld
.MOV(msg_lod
, lod
);
4076 msg_end
= offset(msg_lod
, bld
, 1);
4078 case SHADER_OPCODE_TXF
:
4079 msg_lod
= offset(msg_coords
, bld
, 3);
4080 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4081 msg_end
= offset(msg_lod
, bld
, 1);
4083 case SHADER_OPCODE_TXF_CMS
:
4084 msg_lod
= offset(msg_coords
, bld
, 3);
4086 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4088 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4089 msg_end
= offset(msg_lod
, bld
, 2);
4096 inst
->src
[0] = reg_undef
;
4097 inst
->src
[1] = surface
;
4098 inst
->src
[2] = sampler
;
4099 inst
->resize_sources(3);
4100 inst
->base_mrf
= message
.nr
;
4101 inst
->mlen
= msg_end
.nr
- message
.nr
;
4102 inst
->header_size
= header_size
;
4104 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4105 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4109 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4111 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4114 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4118 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4119 const fs_reg
&coordinate
,
4120 const fs_reg
&shadow_c
,
4121 fs_reg lod
, const fs_reg
&lod2
,
4122 const fs_reg
&sample_index
,
4124 const fs_reg
&surface
,
4125 const fs_reg
&sampler
,
4126 const fs_reg
&tg4_offset
,
4127 unsigned coord_components
,
4128 unsigned grad_components
)
4130 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4131 unsigned reg_width
= bld
.dispatch_width() / 8;
4132 unsigned header_size
= 0, length
= 0;
4133 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4134 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4135 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4137 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4138 inst
->offset
!= 0 || inst
->eot
||
4139 op
== SHADER_OPCODE_SAMPLEINFO
||
4140 is_high_sampler(devinfo
, sampler
)) {
4141 /* For general texture offsets (no txf workaround), we need a header to
4142 * put them in. Note that we're only reserving space for it in the
4143 * message payload as it will be initialized implicitly by the
4146 * TG4 needs to place its channel select in the header, for interaction
4147 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4148 * larger sampler numbers we need to offset the Sampler State Pointer in
4152 sources
[0] = fs_reg();
4155 /* If we're requesting fewer than four channels worth of response,
4156 * and we have an explicit header, we need to set up the sampler
4157 * writemask. It's reversed from normal: 1 means "don't write".
4159 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4160 assert(regs_written(inst
) % reg_width
== 0);
4161 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4162 inst
->offset
|= mask
<< 12;
4166 if (shadow_c
.file
!= BAD_FILE
) {
4167 bld
.MOV(sources
[length
], shadow_c
);
4171 bool coordinate_done
= false;
4173 /* Set up the LOD info */
4176 case SHADER_OPCODE_TXL
:
4177 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4178 op
= SHADER_OPCODE_TXL_LZ
;
4181 bld
.MOV(sources
[length
], lod
);
4184 case SHADER_OPCODE_TXD
:
4185 /* TXD should have been lowered in SIMD16 mode. */
4186 assert(bld
.dispatch_width() == 8);
4188 /* Load dPdx and the coordinate together:
4189 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4191 for (unsigned i
= 0; i
< coord_components
; i
++) {
4192 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4194 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4195 * only derivatives for (u, v, r).
4197 if (i
< grad_components
) {
4198 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4199 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4203 coordinate_done
= true;
4205 case SHADER_OPCODE_TXS
:
4206 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4209 case SHADER_OPCODE_TXF
:
4210 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4211 * On Gen9 they are u, v, lod, r
4213 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4215 if (devinfo
->gen
>= 9) {
4216 if (coord_components
>= 2) {
4217 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4218 offset(coordinate
, bld
, 1));
4220 sources
[length
] = brw_imm_d(0);
4225 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4226 op
= SHADER_OPCODE_TXF_LZ
;
4228 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4232 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4233 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4234 offset(coordinate
, bld
, i
));
4236 coordinate_done
= true;
4239 case SHADER_OPCODE_TXF_CMS
:
4240 case SHADER_OPCODE_TXF_CMS_W
:
4241 case SHADER_OPCODE_TXF_UMS
:
4242 case SHADER_OPCODE_TXF_MCS
:
4243 if (op
== SHADER_OPCODE_TXF_UMS
||
4244 op
== SHADER_OPCODE_TXF_CMS
||
4245 op
== SHADER_OPCODE_TXF_CMS_W
) {
4246 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4250 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4251 /* Data from the multisample control surface. */
4252 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4255 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4258 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4259 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4262 offset(mcs
, bld
, 1));
4267 /* There is no offsetting for this message; just copy in the integer
4268 * texture coordinates.
4270 for (unsigned i
= 0; i
< coord_components
; i
++)
4271 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4272 offset(coordinate
, bld
, i
));
4274 coordinate_done
= true;
4276 case SHADER_OPCODE_TG4_OFFSET
:
4277 /* More crazy intermixing */
4278 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4279 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4281 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4282 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4283 offset(tg4_offset
, bld
, i
));
4285 if (coord_components
== 3) /* r if present */
4286 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4288 coordinate_done
= true;
4294 /* Set up the coordinate (except for cases where it was done above) */
4295 if (!coordinate_done
) {
4296 for (unsigned i
= 0; i
< coord_components
; i
++)
4297 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4302 mlen
= length
* reg_width
- header_size
;
4304 mlen
= length
* reg_width
;
4306 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4307 BRW_REGISTER_TYPE_F
);
4308 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4310 /* Generate the SEND. */
4312 inst
->src
[0] = src_payload
;
4313 inst
->src
[1] = surface
;
4314 inst
->src
[2] = sampler
;
4315 inst
->resize_sources(3);
4317 inst
->header_size
= header_size
;
4319 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4320 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4324 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4326 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4327 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4328 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4329 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4330 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4331 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4332 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4333 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4334 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4335 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
4336 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4337 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4338 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4339 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4341 if (devinfo
->gen
>= 7) {
4342 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4343 shadow_c
, lod
, lod2
, sample_index
,
4344 mcs
, surface
, sampler
, tg4_offset
,
4345 coord_components
, grad_components
);
4346 } else if (devinfo
->gen
>= 5) {
4347 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4348 shadow_c
, lod
, lod2
, sample_index
,
4350 coord_components
, grad_components
);
4352 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4353 shadow_c
, lod
, lod2
,
4355 coord_components
, grad_components
);
4360 * Initialize the header present in some typed and untyped surface
4364 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4366 fs_builder ubld
= bld
.exec_all().group(8, 0);
4367 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4368 ubld
.MOV(dst
, brw_imm_d(0));
4369 ubld
.group(1, 0).MOV(component(dst
, 7), sample_mask
);
4374 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4375 const fs_reg
&sample_mask
)
4377 /* Get the logical send arguments. */
4378 const fs_reg
&addr
= inst
->src
[0];
4379 const fs_reg
&src
= inst
->src
[1];
4380 const fs_reg
&surface
= inst
->src
[2];
4381 const UNUSED fs_reg
&dims
= inst
->src
[3];
4382 const fs_reg
&arg
= inst
->src
[4];
4384 /* Calculate the total number of components of the payload. */
4385 const unsigned addr_sz
= inst
->components_read(0);
4386 const unsigned src_sz
= inst
->components_read(1);
4387 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4388 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4390 /* Allocate space for the payload. */
4391 fs_reg
*const components
= new fs_reg
[sz
];
4392 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4395 /* Construct the payload. */
4397 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4399 for (unsigned i
= 0; i
< addr_sz
; i
++)
4400 components
[n
++] = offset(addr
, bld
, i
);
4402 for (unsigned i
= 0; i
< src_sz
; i
++)
4403 components
[n
++] = offset(src
, bld
, i
);
4405 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4407 /* Update the original instruction. */
4409 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4410 inst
->header_size
= header_sz
;
4412 inst
->src
[0] = payload
;
4413 inst
->src
[1] = surface
;
4415 inst
->resize_sources(3);
4417 delete[] components
;
4421 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4423 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4425 if (devinfo
->gen
>= 7) {
4426 /* We are switching the instruction from an ALU-like instruction to a
4427 * send-from-grf instruction. Since sends can't handle strides or
4428 * source modifiers, we have to make a copy of the offset source.
4430 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4431 bld
.MOV(tmp
, inst
->src
[1]);
4434 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4437 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4438 BRW_REGISTER_TYPE_UD
);
4440 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4442 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4443 inst
->resize_sources(1);
4444 inst
->base_mrf
= payload
.nr
;
4445 inst
->header_size
= 1;
4446 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4451 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4453 assert(bld
.shader
->devinfo
->gen
< 6);
4456 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4458 if (inst
->sources
> 1) {
4459 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4460 * "Message Payload":
4462 * "Operand0[7]. For the INT DIV functions, this operand is the
4465 * "Operand1[7]. For the INT DIV functions, this operand is the
4468 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4469 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4470 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4472 inst
->resize_sources(1);
4473 inst
->src
[0] = src0
;
4475 assert(inst
->exec_size
== 8);
4476 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4481 fs_visitor::lower_logical_sends()
4483 bool progress
= false;
4485 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4486 const fs_builder
ibld(this, block
, inst
);
4488 switch (inst
->opcode
) {
4489 case FS_OPCODE_FB_WRITE_LOGICAL
:
4490 assert(stage
== MESA_SHADER_FRAGMENT
);
4491 lower_fb_write_logical_send(ibld
, inst
,
4492 brw_wm_prog_data(prog_data
),
4493 (const brw_wm_prog_key
*)key
,
4497 case FS_OPCODE_FB_READ_LOGICAL
:
4498 lower_fb_read_logical_send(ibld
, inst
);
4501 case SHADER_OPCODE_TEX_LOGICAL
:
4502 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4505 case SHADER_OPCODE_TXD_LOGICAL
:
4506 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4509 case SHADER_OPCODE_TXF_LOGICAL
:
4510 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4513 case SHADER_OPCODE_TXL_LOGICAL
:
4514 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4517 case SHADER_OPCODE_TXS_LOGICAL
:
4518 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4521 case FS_OPCODE_TXB_LOGICAL
:
4522 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4525 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4526 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4529 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4530 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4533 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4534 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4537 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4538 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4541 case SHADER_OPCODE_LOD_LOGICAL
:
4542 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4545 case SHADER_OPCODE_TG4_LOGICAL
:
4546 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4549 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4550 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4553 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4554 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4557 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4558 lower_surface_logical_send(ibld
, inst
,
4559 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4563 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4564 lower_surface_logical_send(ibld
, inst
,
4565 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4566 ibld
.sample_mask_reg());
4569 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
4570 lower_surface_logical_send(ibld
, inst
,
4571 SHADER_OPCODE_BYTE_SCATTERED_READ
,
4575 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
4576 lower_surface_logical_send(ibld
, inst
,
4577 SHADER_OPCODE_BYTE_SCATTERED_WRITE
,
4578 ibld
.sample_mask_reg());
4581 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4582 lower_surface_logical_send(ibld
, inst
,
4583 SHADER_OPCODE_UNTYPED_ATOMIC
,
4584 ibld
.sample_mask_reg());
4587 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4588 lower_surface_logical_send(ibld
, inst
,
4589 SHADER_OPCODE_TYPED_SURFACE_READ
,
4593 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4594 lower_surface_logical_send(ibld
, inst
,
4595 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4596 ibld
.sample_mask_reg());
4599 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4600 lower_surface_logical_send(ibld
, inst
,
4601 SHADER_OPCODE_TYPED_ATOMIC
,
4602 ibld
.sample_mask_reg());
4605 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4606 lower_varying_pull_constant_logical_send(ibld
, inst
);
4609 case SHADER_OPCODE_RCP
:
4610 case SHADER_OPCODE_RSQ
:
4611 case SHADER_OPCODE_SQRT
:
4612 case SHADER_OPCODE_EXP2
:
4613 case SHADER_OPCODE_LOG2
:
4614 case SHADER_OPCODE_SIN
:
4615 case SHADER_OPCODE_COS
:
4616 case SHADER_OPCODE_POW
:
4617 case SHADER_OPCODE_INT_QUOTIENT
:
4618 case SHADER_OPCODE_INT_REMAINDER
:
4619 /* The math opcodes are overloaded for the send-like and
4620 * expression-like instructions which seems kind of icky. Gen6+ has
4621 * a native (but rather quirky) MATH instruction so we don't need to
4622 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4623 * logical instructions (which we can easily recognize because they
4624 * have mlen = 0) into send-like virtual instructions.
4626 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4627 lower_math_logical_send(ibld
, inst
);
4642 invalidate_live_intervals();
4648 * Get the closest allowed SIMD width for instruction \p inst accounting for
4649 * some common regioning and execution control restrictions that apply to FPU
4650 * instructions. These restrictions don't necessarily have any relevance to
4651 * instructions not executed by the FPU pipeline like extended math, control
4652 * flow or send message instructions.
4654 * For virtual opcodes it's really up to the instruction -- In some cases
4655 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4656 * instructions) it may simplify virtual instruction lowering if we can
4657 * enforce FPU-like regioning restrictions already on the virtual instruction,
4658 * in other cases (e.g. virtual send-like instructions) this may be
4659 * excessively restrictive.
4662 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4663 const fs_inst
*inst
)
4665 /* Maximum execution size representable in the instruction controls. */
4666 unsigned max_width
= MIN2(32, inst
->exec_size
);
4668 /* According to the PRMs:
4669 * "A. In Direct Addressing mode, a source cannot span more than 2
4670 * adjacent GRF registers.
4671 * B. A destination cannot span more than 2 adjacent GRF registers."
4673 * Look for the source or destination with the largest register region
4674 * which is the one that is going to limit the overall execution size of
4675 * the instruction due to this rule.
4677 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4679 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4680 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4682 /* Calculate the maximum execution size of the instruction based on the
4683 * factor by which it goes over the hardware limit of 2 GRFs.
4686 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4688 /* According to the IVB PRMs:
4689 * "When destination spans two registers, the source MUST span two
4690 * registers. The exception to the above rule:
4692 * - When source is scalar, the source registers are not incremented.
4693 * - When source is packed integer Word and destination is packed
4694 * integer DWord, the source register is not incremented but the
4695 * source sub register is incremented."
4697 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4698 * restrictions. The code below intentionally doesn't check whether the
4699 * destination type is integer because empirically the hardware doesn't
4700 * seem to care what the actual type is as long as it's dword-aligned.
4702 if (devinfo
->gen
< 8) {
4703 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4704 /* IVB implements DF scalars as <0;2,1> regions. */
4705 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
4706 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
4707 const bool is_packed_word_exception
=
4708 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4709 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
4711 if (inst
->size_written
> REG_SIZE
&&
4712 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
4713 !is_scalar_exception
&& !is_packed_word_exception
) {
4714 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4715 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4720 /* From the IVB PRMs:
4721 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4722 * are applied for both halves of the SIMD32 instruction. If different
4723 * execution mask channels are required, split the instruction into two
4724 * SIMD16 instructions."
4726 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4727 * 32-wide control flow support in hardware and will behave similarly.
4729 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4730 max_width
= MIN2(max_width
, 16);
4732 /* From the IVB PRMs (applies to HSW too):
4733 * "Instructions with condition modifiers must not use SIMD32."
4735 * From the BDW PRMs (applies to later hardware too):
4736 * "Ternary instruction with condition modifiers must not use SIMD32."
4738 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4739 max_width
= MIN2(max_width
, 16);
4741 /* From the IVB PRMs (applies to other devices that don't have the
4742 * gen_device_info::supports_simd16_3src flag set):
4743 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4744 * SIMD8 is not allowed for DF operations."
4746 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4747 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4749 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4750 * the 8-bit quarter of the execution mask signals specified in the
4751 * instruction control fields) for the second compressed half of any
4752 * single-precision instruction (for double-precision instructions
4753 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4754 * the EU will apply the wrong execution controls for the second
4755 * sequential GRF write if the number of channels per GRF is not exactly
4756 * eight in single-precision mode (or four in double-float mode).
4758 * In this situation we calculate the maximum size of the split
4759 * instructions so they only ever write to a single register.
4761 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4762 !inst
->force_writemask_all
) {
4763 const unsigned channels_per_grf
= inst
->exec_size
/
4764 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4765 const unsigned exec_type_size
= get_exec_type_size(inst
);
4766 assert(exec_type_size
);
4768 /* The hardware shifts exactly 8 channels per compressed half of the
4769 * instruction in single-precision mode and exactly 4 in double-precision.
4771 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4772 max_width
= MIN2(max_width
, channels_per_grf
);
4774 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
4775 * because HW applies the same channel enable signals to both halves of
4776 * the compressed instruction which will be just wrong under
4777 * non-uniform control flow.
4779 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4780 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
4781 max_width
= MIN2(max_width
, 4);
4784 /* Only power-of-two execution sizes are representable in the instruction
4787 return 1 << _mesa_logbase2(max_width
);
4791 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4792 * various payload size restrictions that apply to sampler message
4795 * This is only intended to provide a maximum theoretical bound for the
4796 * execution size of the message based on the number of argument components
4797 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4798 * variant of the message can be used, though some messages may have
4799 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4800 * the message length to determine the exact SIMD width and argument count,
4801 * which makes a number of sampler message combinations impossible to
4805 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4806 const fs_inst
*inst
)
4808 /* Calculate the number of coordinate components that have to be present
4809 * assuming that additional arguments follow the texel coordinates in the
4810 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4811 * need to pad to four or three components depending on the message,
4812 * pre-ILK we need to pad to at most three components.
4814 const unsigned req_coord_components
=
4815 (devinfo
->gen
>= 7 ||
4816 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4817 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4818 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4821 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4822 * variant of the TXL or TXF message.
4824 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4825 (inst
->opcode
== SHADER_OPCODE_TXL
||
4826 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4827 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4829 /* Calculate the total number of argument components that need to be passed
4830 * to the sampler unit.
4832 const unsigned num_payload_components
=
4833 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4834 req_coord_components
) +
4835 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4836 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4837 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4838 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4839 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4840 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
4841 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4843 /* SIMD16 messages with more than five arguments exceed the maximum message
4844 * size supported by the sampler, regardless of whether a header is
4847 return MIN2(inst
->exec_size
,
4848 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4852 * Get the closest native SIMD width supported by the hardware for instruction
4853 * \p inst. The instruction will be left untouched by
4854 * fs_visitor::lower_simd_width() if the returned value is equal to the
4855 * original execution size.
4858 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4859 const fs_inst
*inst
)
4861 switch (inst
->opcode
) {
4862 case BRW_OPCODE_MOV
:
4863 case BRW_OPCODE_SEL
:
4864 case BRW_OPCODE_NOT
:
4865 case BRW_OPCODE_AND
:
4867 case BRW_OPCODE_XOR
:
4868 case BRW_OPCODE_SHR
:
4869 case BRW_OPCODE_SHL
:
4870 case BRW_OPCODE_ASR
:
4871 case BRW_OPCODE_CMPN
:
4872 case BRW_OPCODE_CSEL
:
4873 case BRW_OPCODE_F32TO16
:
4874 case BRW_OPCODE_F16TO32
:
4875 case BRW_OPCODE_BFREV
:
4876 case BRW_OPCODE_BFE
:
4877 case BRW_OPCODE_ADD
:
4878 case BRW_OPCODE_MUL
:
4879 case BRW_OPCODE_AVG
:
4880 case BRW_OPCODE_FRC
:
4881 case BRW_OPCODE_RNDU
:
4882 case BRW_OPCODE_RNDD
:
4883 case BRW_OPCODE_RNDE
:
4884 case BRW_OPCODE_RNDZ
:
4885 case BRW_OPCODE_LZD
:
4886 case BRW_OPCODE_FBH
:
4887 case BRW_OPCODE_FBL
:
4888 case BRW_OPCODE_CBIT
:
4889 case BRW_OPCODE_SAD2
:
4890 case BRW_OPCODE_MAD
:
4891 case BRW_OPCODE_LRP
:
4892 case FS_OPCODE_PACK
:
4893 return get_fpu_lowered_simd_width(devinfo
, inst
);
4895 case BRW_OPCODE_CMP
: {
4896 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4897 * when the destination is a GRF the dependency-clear bit on the flag
4898 * register is cleared early.
4900 * Suggested workarounds are to disable coissuing CMP instructions
4901 * or to split CMP(16) instructions into two CMP(8) instructions.
4903 * We choose to split into CMP(8) instructions since disabling
4904 * coissuing would affect CMP instructions not otherwise affected by
4907 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4908 !inst
->dst
.is_null() ? 8 : ~0);
4909 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4911 case BRW_OPCODE_BFI1
:
4912 case BRW_OPCODE_BFI2
:
4913 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4915 * "Force BFI instructions to be executed always in SIMD8."
4917 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4918 get_fpu_lowered_simd_width(devinfo
, inst
));
4921 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4922 return inst
->exec_size
;
4924 case SHADER_OPCODE_RCP
:
4925 case SHADER_OPCODE_RSQ
:
4926 case SHADER_OPCODE_SQRT
:
4927 case SHADER_OPCODE_EXP2
:
4928 case SHADER_OPCODE_LOG2
:
4929 case SHADER_OPCODE_SIN
:
4930 case SHADER_OPCODE_COS
:
4931 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4934 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4935 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4936 MIN2(8, inst
->exec_size
));
4938 case SHADER_OPCODE_POW
:
4939 /* SIMD16 is only allowed on Gen7+. */
4940 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4941 MIN2(8, inst
->exec_size
));
4943 case SHADER_OPCODE_INT_QUOTIENT
:
4944 case SHADER_OPCODE_INT_REMAINDER
:
4945 /* Integer division is limited to SIMD8 on all generations. */
4946 return MIN2(8, inst
->exec_size
);
4948 case FS_OPCODE_LINTERP
:
4949 case FS_OPCODE_GET_BUFFER_SIZE
:
4950 case FS_OPCODE_DDX_COARSE
:
4951 case FS_OPCODE_DDX_FINE
:
4952 case FS_OPCODE_DDY_COARSE
:
4953 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4954 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4955 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4956 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4957 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4958 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4959 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4960 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4961 return MIN2(16, inst
->exec_size
);
4963 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4964 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4965 * message used to implement varying pull constant loads, so expand it
4966 * to SIMD16. An alternative with longer message payload length but
4967 * shorter return payload would be to use the SIMD8 sampler message that
4968 * takes (header, u, v, r) as parameters instead of (header, u).
4970 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4972 case FS_OPCODE_DDY_FINE
:
4973 /* The implementation of this virtual opcode may require emitting
4974 * compressed Align16 instructions, which are severely limited on some
4977 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4978 * Region Restrictions):
4980 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4981 * and SIMD8 is not allowed for DF operations."
4983 * In this context, "DW operations" means "operations acting on 32-bit
4984 * values", so it includes operations on floats.
4986 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4987 * (Instruction Compression -> Rules and Restrictions):
4989 * "A compressed instruction must be in Align1 access mode. Align16
4990 * mode instructions cannot be compressed."
4992 * Similar text exists in the g45 PRM.
4994 * Empirically, compressed align16 instructions using odd register
4995 * numbers don't appear to work on Sandybridge either.
4997 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4998 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4999 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
5001 case SHADER_OPCODE_MULH
:
5002 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
5003 * is 8-wide on Gen7+.
5005 return (devinfo
->gen
>= 7 ? 8 :
5006 get_fpu_lowered_simd_width(devinfo
, inst
));
5008 case FS_OPCODE_FB_WRITE_LOGICAL
:
5009 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
5012 assert(devinfo
->gen
!= 6 ||
5013 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
5014 inst
->exec_size
== 8);
5015 /* Dual-source FB writes are unsupported in SIMD16 mode. */
5016 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
5017 8 : MIN2(16, inst
->exec_size
));
5019 case FS_OPCODE_FB_READ_LOGICAL
:
5020 return MIN2(16, inst
->exec_size
);
5022 case SHADER_OPCODE_TEX_LOGICAL
:
5023 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5024 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5025 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5026 case SHADER_OPCODE_LOD_LOGICAL
:
5027 case SHADER_OPCODE_TG4_LOGICAL
:
5028 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5029 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5030 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5031 return get_sampler_lowered_simd_width(devinfo
, inst
);
5033 case SHADER_OPCODE_TXD_LOGICAL
:
5034 /* TXD is unsupported in SIMD16 mode. */
5037 case SHADER_OPCODE_TXL_LOGICAL
:
5038 case FS_OPCODE_TXB_LOGICAL
:
5039 /* Only one execution size is representable pre-ILK depending on whether
5040 * the shadow reference argument is present.
5042 if (devinfo
->gen
== 4)
5043 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
5045 return get_sampler_lowered_simd_width(devinfo
, inst
);
5047 case SHADER_OPCODE_TXF_LOGICAL
:
5048 case SHADER_OPCODE_TXS_LOGICAL
:
5049 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
5050 * messages. Use SIMD16 instead.
5052 if (devinfo
->gen
== 4)
5055 return get_sampler_lowered_simd_width(devinfo
, inst
);
5057 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5058 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5059 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5062 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5063 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5064 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5065 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5066 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5067 return MIN2(16, inst
->exec_size
);
5069 case SHADER_OPCODE_URB_READ_SIMD8
:
5070 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
5071 case SHADER_OPCODE_URB_WRITE_SIMD8
:
5072 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
5073 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
5074 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
5075 return MIN2(8, inst
->exec_size
);
5077 case SHADER_OPCODE_MOV_INDIRECT
: {
5078 /* From IVB and HSW PRMs:
5080 * "2.When the destination requires two registers and the sources are
5081 * indirect, the sources must use 1x1 regioning mode.
5083 * In case of DF instructions in HSW/IVB, the exec_size is limited by
5084 * the EU decompression logic not handling VxH indirect addressing
5087 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
5088 /* Prior to Broadwell, we only have 8 address subregisters. */
5089 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
5090 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
5094 case SHADER_OPCODE_LOAD_PAYLOAD
: {
5095 const unsigned reg_count
=
5096 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5098 if (reg_count
> 2) {
5099 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5100 * can be easily lowered (which excludes headers and heterogeneous
5103 assert(!inst
->header_size
);
5104 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5105 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5106 inst
->src
[i
].file
== BAD_FILE
);
5108 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5110 return inst
->exec_size
;
5114 return inst
->exec_size
;
5119 * Return true if splitting out the group of channels of instruction \p inst
5120 * given by lbld.group() requires allocating a temporary for the i-th source
5121 * of the lowered instruction.
5124 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5126 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5127 (inst
->components_read(i
) == 1 &&
5128 lbld
.dispatch_width() <= inst
->exec_size
)) ||
5129 (inst
->flags_written() &
5130 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
5134 * Extract the data that would be consumed by the channel group given by
5135 * lbld.group() from the i-th source region of instruction \p inst and return
5136 * it as result in packed form.
5139 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
5141 /* Specified channel group from the source region. */
5142 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5144 if (needs_src_copy(lbld
, inst
, i
)) {
5145 /* Builder of the right width to perform the copy avoiding uninitialized
5146 * data if the lowered execution size is greater than the original
5147 * execution size of the instruction.
5149 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5150 inst
->exec_size
), 0);
5151 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5153 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5154 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5158 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5159 /* The source is invariant for all dispatch_width-wide groups of the
5162 return inst
->src
[i
];
5165 /* We can just point the lowered instruction at the right channel group
5166 * from the original region.
5173 * Return true if splitting out the group of channels of instruction \p inst
5174 * given by lbld.group() requires allocating a temporary for the destination
5175 * of the lowered instruction and copying the data back to the original
5176 * destination region.
5179 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5181 /* If the instruction writes more than one component we'll have to shuffle
5182 * the results of multiple lowered instructions in order to make sure that
5183 * they end up arranged correctly in the original destination region.
5185 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5188 /* If the lowered execution size is larger than the original the result of
5189 * the instruction won't fit in the original destination, so we'll have to
5190 * allocate a temporary in any case.
5192 if (lbld
.dispatch_width() > inst
->exec_size
)
5195 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5196 /* If we already made a copy of the source for other reasons there won't
5197 * be any overlap with the destination.
5199 if (needs_src_copy(lbld
, inst
, i
))
5202 /* In order to keep the logic simple we emit a copy whenever the
5203 * destination region doesn't exactly match an overlapping source, which
5204 * may point at the source and destination not being aligned group by
5205 * group which could cause one of the lowered instructions to overwrite
5206 * the data read from the same source by other lowered instructions.
5208 if (regions_overlap(inst
->dst
, inst
->size_written
,
5209 inst
->src
[i
], inst
->size_read(i
)) &&
5210 !inst
->dst
.equals(inst
->src
[i
]))
5218 * Insert data from a packed temporary into the channel group given by
5219 * lbld.group() of the destination region of instruction \p inst and return
5220 * the temporary as result. Any copy instructions that are required for
5221 * unzipping the previous value (in the case of partial writes) will be
5222 * inserted using \p lbld_before and any copy instructions required for
5223 * zipping up the destination of \p inst will be inserted using \p lbld_after.
5226 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
5229 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
5230 assert(lbld_before
.group() == lbld_after
.group());
5232 /* Specified channel group from the destination region. */
5233 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group());
5234 const unsigned dst_size
= inst
->size_written
/
5235 inst
->dst
.component_size(inst
->exec_size
);
5237 if (needs_dst_copy(lbld_after
, inst
)) {
5238 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
5240 if (inst
->predicate
) {
5241 /* Handle predication by copying the original contents of
5242 * the destination into the temporary before emitting the
5243 * lowered instruction.
5245 const fs_builder gbld_before
=
5246 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
5247 inst
->exec_size
), 0);
5248 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5249 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
5250 offset(dst
, inst
->exec_size
, k
));
5254 const fs_builder gbld_after
=
5255 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
5256 inst
->exec_size
), 0);
5257 for (unsigned k
= 0; k
< dst_size
; ++k
) {
5258 /* Use a builder of the right width to perform the copy avoiding
5259 * uninitialized data if the lowered execution size is greater than
5260 * the original execution size of the instruction.
5262 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
5263 offset(tmp
, lbld_after
, k
));
5269 /* No need to allocate a temporary for the lowered instruction, just
5270 * take the right group of channels from the original region.
5277 fs_visitor::lower_simd_width()
5279 bool progress
= false;
5281 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5282 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5284 if (lower_width
!= inst
->exec_size
) {
5285 /* Builder matching the original instruction. We may also need to
5286 * emit an instruction of width larger than the original, set the
5287 * execution size of the builder to the highest of both for now so
5288 * we're sure that both cases can be handled.
5290 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5291 const fs_builder ibld
= bld
.at(block
, inst
)
5292 .exec_all(inst
->force_writemask_all
)
5293 .group(max_width
, inst
->group
/ max_width
);
5295 /* Split the copies in chunks of the execution width of either the
5296 * original or the lowered instruction, whichever is lower.
5298 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5299 const unsigned dst_size
= inst
->size_written
/
5300 inst
->dst
.component_size(inst
->exec_size
);
5302 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5304 /* Inserting the zip, unzip, and duplicated instructions in all of
5305 * the right spots is somewhat tricky. All of the unzip and any
5306 * instructions from the zip which unzip the destination prior to
5307 * writing need to happen before all of the per-group instructions
5308 * and the zip instructions need to happen after. In order to sort
5309 * this all out, we insert the unzip instructions before \p inst,
5310 * insert the per-group instructions after \p inst (i.e. before
5311 * inst->next), and insert the zip instructions before the
5312 * instruction after \p inst. Since we are inserting instructions
5313 * after \p inst, inst->next is a moving target and we need to save
5314 * it off here so that we insert the zip instructions in the right
5317 exec_node
*const after_inst
= inst
->next
;
5318 for (unsigned i
= 0; i
< n
; i
++) {
5319 /* Emit a copy of the original instruction with the lowered width.
5320 * If the EOT flag was set throw it away except for the last
5321 * instruction to avoid killing the thread prematurely.
5323 fs_inst split_inst
= *inst
;
5324 split_inst
.exec_size
= lower_width
;
5325 split_inst
.eot
= inst
->eot
&& i
== 0;
5327 /* Select the correct channel enables for the i-th group, then
5328 * transform the sources and destination and emit the lowered
5331 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5333 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5334 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
5336 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
5337 lbld
.at(block
, after_inst
), inst
);
5338 split_inst
.size_written
=
5339 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5341 lbld
.at(block
, inst
->next
).emit(split_inst
);
5344 inst
->remove(block
);
5350 invalidate_live_intervals();
5356 fs_visitor::dump_instructions()
5358 dump_instructions(NULL
);
5362 fs_visitor::dump_instructions(const char *name
)
5364 FILE *file
= stderr
;
5365 if (name
&& geteuid() != 0) {
5366 file
= fopen(name
, "w");
5372 calculate_register_pressure();
5373 int ip
= 0, max_pressure
= 0;
5374 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5375 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5376 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5377 dump_instruction(inst
, file
);
5380 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5383 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5384 fprintf(file
, "%4d: ", ip
++);
5385 dump_instruction(inst
, file
);
5389 if (file
!= stderr
) {
5395 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5397 dump_instruction(be_inst
, stderr
);
5401 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5403 fs_inst
*inst
= (fs_inst
*)be_inst
;
5405 if (inst
->predicate
) {
5406 fprintf(file
, "(%cf0.%d) ",
5407 inst
->predicate_inverse
? '-' : '+',
5411 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5413 fprintf(file
, ".sat");
5414 if (inst
->conditional_mod
) {
5415 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5416 if (!inst
->predicate
&&
5417 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5418 inst
->opcode
!= BRW_OPCODE_IF
&&
5419 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5420 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5423 fprintf(file
, "(%d) ", inst
->exec_size
);
5426 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5430 fprintf(file
, "(EOT) ");
5433 switch (inst
->dst
.file
) {
5435 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5438 fprintf(file
, "g%d", inst
->dst
.nr
);
5441 fprintf(file
, "m%d", inst
->dst
.nr
);
5444 fprintf(file
, "(null)");
5447 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5450 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5453 switch (inst
->dst
.nr
) {
5455 fprintf(file
, "null");
5457 case BRW_ARF_ADDRESS
:
5458 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5460 case BRW_ARF_ACCUMULATOR
:
5461 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5464 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5467 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5472 unreachable("not reached");
5475 if (inst
->dst
.offset
||
5476 (inst
->dst
.file
== VGRF
&&
5477 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5478 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5479 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5480 inst
->dst
.offset
% reg_size
);
5483 if (inst
->dst
.stride
!= 1)
5484 fprintf(file
, "<%u>", inst
->dst
.stride
);
5485 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
5487 for (int i
= 0; i
< inst
->sources
; i
++) {
5488 if (inst
->src
[i
].negate
)
5490 if (inst
->src
[i
].abs
)
5492 switch (inst
->src
[i
].file
) {
5494 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5497 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5500 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5503 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5506 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5509 fprintf(file
, "(null)");
5512 switch (inst
->src
[i
].type
) {
5513 case BRW_REGISTER_TYPE_F
:
5514 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5516 case BRW_REGISTER_TYPE_DF
:
5517 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5519 case BRW_REGISTER_TYPE_W
:
5520 case BRW_REGISTER_TYPE_D
:
5521 fprintf(file
, "%dd", inst
->src
[i
].d
);
5523 case BRW_REGISTER_TYPE_UW
:
5524 case BRW_REGISTER_TYPE_UD
:
5525 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5527 case BRW_REGISTER_TYPE_VF
:
5528 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5529 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5530 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5531 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5532 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5535 fprintf(file
, "???");
5540 switch (inst
->src
[i
].nr
) {
5542 fprintf(file
, "null");
5544 case BRW_ARF_ADDRESS
:
5545 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5547 case BRW_ARF_ACCUMULATOR
:
5548 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5551 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5554 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5560 if (inst
->src
[i
].offset
||
5561 (inst
->src
[i
].file
== VGRF
&&
5562 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5563 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5564 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5565 inst
->src
[i
].offset
% reg_size
);
5568 if (inst
->src
[i
].abs
)
5571 if (inst
->src
[i
].file
!= IMM
) {
5573 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5574 unsigned hstride
= inst
->src
[i
].hstride
;
5575 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5577 stride
= inst
->src
[i
].stride
;
5580 fprintf(file
, "<%u>", stride
);
5582 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
5585 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5586 fprintf(file
, ", ");
5591 if (inst
->force_writemask_all
)
5592 fprintf(file
, "NoMask ");
5594 if (inst
->exec_size
!= dispatch_width
)
5595 fprintf(file
, "group%d ", inst
->group
);
5597 fprintf(file
, "\n");
5601 * Possibly returns an instruction that set up @param reg.
5603 * Sometimes we want to take the result of some expression/variable
5604 * dereference tree and rewrite the instruction generating the result
5605 * of the tree. When processing the tree, we know that the
5606 * instructions generated are all writing temporaries that are dead
5607 * outside of this tree. So, if we have some instructions that write
5608 * a temporary, we're free to point that temp write somewhere else.
5610 * Note that this doesn't guarantee that the instruction generated
5611 * only reg -- it might be the size=4 destination of a texture instruction.
5614 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5619 end
->is_partial_write() ||
5620 !reg
.equals(end
->dst
)) {
5628 fs_visitor::setup_fs_payload_gen6()
5630 assert(stage
== MESA_SHADER_FRAGMENT
);
5631 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
5633 assert(devinfo
->gen
>= 6);
5635 /* R0-1: masks, pixel X/Y coordinates. */
5636 payload
.num_regs
= 2;
5637 /* R2: only for 32-pixel dispatch.*/
5639 /* R3-26: barycentric interpolation coordinates. These appear in the
5640 * same order that they appear in the brw_barycentric_mode
5641 * enum. Each set of coordinates occupies 2 registers if dispatch width
5642 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5643 * appear if they were enabled using the "Barycentric Interpolation
5644 * Mode" bits in WM_STATE.
5646 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5647 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
5648 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5649 payload
.num_regs
+= 2;
5650 if (dispatch_width
== 16) {
5651 payload
.num_regs
+= 2;
5656 /* R27: interpolated depth if uses source depth */
5657 prog_data
->uses_src_depth
=
5658 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5659 if (prog_data
->uses_src_depth
) {
5660 payload
.source_depth_reg
= payload
.num_regs
;
5662 if (dispatch_width
== 16) {
5663 /* R28: interpolated depth if not SIMD8. */
5668 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5669 prog_data
->uses_src_w
=
5670 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5671 if (prog_data
->uses_src_w
) {
5672 payload
.source_w_reg
= payload
.num_regs
;
5674 if (dispatch_width
== 16) {
5675 /* R30: interpolated W if not SIMD8. */
5680 /* R31: MSAA position offsets. */
5681 if (prog_data
->persample_dispatch
&&
5682 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5683 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5685 * "MSDISPMODE_PERSAMPLE is required in order to select
5688 * So we can only really get sample positions if we are doing real
5689 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5690 * persample dispatch, we hard-code it to 0.5.
5692 prog_data
->uses_pos_offset
= true;
5693 payload
.sample_pos_reg
= payload
.num_regs
;
5697 /* R32: MSAA input coverage mask */
5698 prog_data
->uses_sample_mask
=
5699 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5700 if (prog_data
->uses_sample_mask
) {
5701 assert(devinfo
->gen
>= 7);
5702 payload
.sample_mask_in_reg
= payload
.num_regs
;
5704 if (dispatch_width
== 16) {
5705 /* R33: input coverage mask if not SIMD8. */
5710 /* R34-: bary for 32-pixel. */
5711 /* R58-59: interp W for 32-pixel. */
5713 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5714 source_depth_to_render_target
= true;
5719 fs_visitor::setup_vs_payload()
5721 /* R0: thread header, R1: urb handles */
5722 payload
.num_regs
= 2;
5726 fs_visitor::setup_gs_payload()
5728 assert(stage
== MESA_SHADER_GEOMETRY
);
5730 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
5731 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
5733 /* R0: thread header, R1: output URB handles */
5734 payload
.num_regs
= 2;
5736 if (gs_prog_data
->include_primitive_id
) {
5737 /* R2: Primitive ID 0..7 */
5741 /* Always enable VUE handles so we can safely use pull model if needed.
5743 * The push model for a GS uses a ton of register space even for trivial
5744 * scenarios with just a few inputs, so just make things easier and a bit
5745 * safer by always having pull model available.
5747 gs_prog_data
->base
.include_vue_handles
= true;
5749 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5750 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5752 /* Use a maximum of 24 registers for push-model inputs. */
5753 const unsigned max_push_components
= 24;
5755 /* If pushing our inputs would take too many registers, reduce the URB read
5756 * length (which is in HWords, or 8 registers), and resort to pulling.
5758 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5759 * have to multiply by VerticesIn to obtain the total storage requirement.
5761 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5762 max_push_components
) {
5763 vue_prog_data
->urb_read_length
=
5764 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5769 fs_visitor::setup_cs_payload()
5771 assert(devinfo
->gen
>= 7);
5772 payload
.num_regs
= 1;
5776 fs_visitor::calculate_register_pressure()
5778 invalidate_live_intervals();
5779 calculate_live_intervals();
5781 unsigned num_instructions
= 0;
5782 foreach_block(block
, cfg
)
5783 num_instructions
+= block
->instructions
.length();
5785 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5787 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5788 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5789 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5794 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5796 * The needs_unlit_centroid_workaround ends up producing one of these per
5797 * channel of centroid input, so it's good to clean them up.
5799 * An assumption here is that nothing ever modifies the dispatched pixels
5800 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5801 * dictates that anyway.
5804 fs_visitor::opt_drop_redundant_mov_to_flags()
5806 bool flag_mov_found
[2] = {false};
5807 bool progress
= false;
5809 /* Instructions removed by this pass can only be added if this were true */
5810 if (!devinfo
->needs_unlit_centroid_workaround
)
5813 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5814 if (inst
->is_control_flow()) {
5815 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5816 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5817 if (!flag_mov_found
[inst
->flag_subreg
]) {
5818 flag_mov_found
[inst
->flag_subreg
] = true;
5820 inst
->remove(block
);
5823 } else if (inst
->flags_written()) {
5824 flag_mov_found
[inst
->flag_subreg
] = false;
5832 fs_visitor::optimize()
5834 /* Start by validating the shader we currently have. */
5837 /* bld is the common builder object pointing at the end of the program we
5838 * used to translate it into i965 IR. For the optimization and lowering
5839 * passes coming next, any code added after the end of the program without
5840 * having explicitly called fs_builder::at() clearly points at a mistake.
5841 * Ideally optimization passes wouldn't be part of the visitor so they
5842 * wouldn't have access to bld at all, but they do, so just in case some
5843 * pass forgets to ask for a location explicitly set it to NULL here to
5844 * make it trip. The dispatch width is initialized to a bogus value to
5845 * make sure that optimizations set the execution controls explicitly to
5846 * match the code they are manipulating instead of relying on the defaults.
5848 bld
= fs_builder(this, 64);
5850 assign_constant_locations();
5851 lower_constant_loads();
5855 split_virtual_grfs();
5858 #define OPT(pass, args...) ({ \
5860 bool this_progress = pass(args); \
5862 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5863 char filename[64]; \
5864 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5865 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5867 backend_shader::dump_instructions(filename); \
5872 progress = progress || this_progress; \
5876 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5878 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5879 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5881 backend_shader::dump_instructions(filename
);
5884 bool progress
= false;
5888 OPT(opt_drop_redundant_mov_to_flags
);
5889 OPT(remove_extra_rounding_modes
);
5896 OPT(remove_duplicate_mrf_writes
);
5900 OPT(opt_copy_propagation
);
5901 OPT(opt_predicated_break
, this);
5902 OPT(opt_cmod_propagation
);
5903 OPT(dead_code_eliminate
);
5904 OPT(opt_peephole_sel
);
5905 OPT(dead_control_flow_eliminate
, this);
5906 OPT(opt_register_renaming
);
5907 OPT(opt_saturate_propagation
);
5908 OPT(register_coalesce
);
5909 OPT(compute_to_mrf
);
5910 OPT(eliminate_find_live_channel
);
5912 OPT(compact_virtual_grfs
);
5918 if (OPT(lower_pack
)) {
5919 OPT(register_coalesce
);
5920 OPT(dead_code_eliminate
);
5923 OPT(lower_simd_width
);
5925 /* After SIMD lowering just in case we had to unroll the EOT send. */
5926 OPT(opt_sampler_eot
);
5928 OPT(lower_logical_sends
);
5931 OPT(opt_copy_propagation
);
5932 /* Only run after logical send lowering because it's easier to implement
5933 * in terms of physical sends.
5935 if (OPT(opt_zero_samples
))
5936 OPT(opt_copy_propagation
);
5937 /* Run after logical send lowering to give it a chance to CSE the
5938 * LOAD_PAYLOAD instructions created to construct the payloads of
5939 * e.g. texturing messages in cases where it wasn't possible to CSE the
5940 * whole logical instruction.
5943 OPT(register_coalesce
);
5944 OPT(compute_to_mrf
);
5945 OPT(dead_code_eliminate
);
5946 OPT(remove_duplicate_mrf_writes
);
5947 OPT(opt_peephole_sel
);
5950 OPT(opt_redundant_discard_jumps
);
5952 if (OPT(lower_load_payload
)) {
5953 split_virtual_grfs();
5954 OPT(register_coalesce
);
5955 OPT(compute_to_mrf
);
5956 OPT(dead_code_eliminate
);
5959 OPT(opt_combine_constants
);
5960 OPT(lower_integer_multiplication
);
5962 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5963 OPT(opt_cmod_propagation
);
5965 OPT(opt_copy_propagation
);
5966 OPT(dead_code_eliminate
);
5969 if (OPT(lower_conversions
)) {
5970 OPT(opt_copy_propagation
);
5971 OPT(dead_code_eliminate
);
5972 OPT(lower_simd_width
);
5975 lower_uniform_pull_constant_loads();
5981 * Three source instruction must have a GRF/MRF destination register.
5982 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5985 fs_visitor::fixup_3src_null_dest()
5987 bool progress
= false;
5989 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5990 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5991 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5998 invalidate_live_intervals();
6002 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
6004 bool allocated_without_spills
;
6006 static const enum instruction_scheduler_mode pre_modes
[] = {
6008 SCHEDULE_PRE_NON_LIFO
,
6012 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
6014 /* Try each scheduling heuristic to see if it can successfully register
6015 * allocate without spilling. They should be ordered by decreasing
6016 * performance but increasing likelihood of allocating.
6018 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
6019 schedule_instructions(pre_modes
[i
]);
6022 assign_regs_trivial();
6023 allocated_without_spills
= true;
6025 allocated_without_spills
= assign_regs(false, spill_all
);
6027 if (allocated_without_spills
)
6031 if (!allocated_without_spills
) {
6032 if (!allow_spilling
)
6033 fail("Failure to register allocate and spilling is not allowed.");
6035 /* We assume that any spilling is worse than just dropping back to
6036 * SIMD8. There's probably actually some intermediate point where
6037 * SIMD16 with a couple of spills is still better.
6039 if (dispatch_width
> min_dispatch_width
) {
6040 fail("Failure to register allocate. Reduce number of "
6041 "live scalar values to avoid this.");
6043 compiler
->shader_perf_log(log_data
,
6044 "%s shader triggered register spilling. "
6045 "Try reducing the number of live scalar "
6046 "values to improve performance.\n",
6050 /* Since we're out of heuristics, just go spill registers until we
6051 * get an allocation.
6053 while (!assign_regs(true, spill_all
)) {
6059 /* This must come after all optimization and register allocation, since
6060 * it inserts dead code that happens to have side effects, and it does
6061 * so based on the actual physical registers in use.
6063 insert_gen4_send_dependency_workarounds();
6068 opt_bank_conflicts();
6070 schedule_instructions(SCHEDULE_POST
);
6072 if (last_scratch
> 0) {
6073 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
6075 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
6077 if (stage
== MESA_SHADER_COMPUTE
) {
6078 if (devinfo
->is_haswell
) {
6079 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
6080 * field documentation, Haswell supports a minimum of 2kB of
6081 * scratch space for compute shaders, unlike every other stage
6084 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
6085 } else if (devinfo
->gen
<= 7) {
6086 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
6087 * field documentation, platforms prior to Haswell measure scratch
6088 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
6090 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
6091 max_scratch_size
= 12 * 1024;
6095 /* We currently only support up to 2MB of scratch space. If we
6096 * need to support more eventually, the documentation suggests
6097 * that we could allocate a larger buffer, and partition it out
6098 * ourselves. We'd just have to undo the hardware's address
6099 * calculation by subtracting (FFTID * Per Thread Scratch Space)
6100 * and then add FFTID * (Larger Per Thread Scratch Space).
6102 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
6103 * Thread Group Tracking > Local Memory/Scratch Space.
6105 assert(prog_data
->total_scratch
< max_scratch_size
);
6110 fs_visitor::run_vs()
6112 assert(stage
== MESA_SHADER_VERTEX
);
6116 if (shader_time_index
>= 0)
6117 emit_shader_time_begin();
6124 compute_clip_distance();
6128 if (shader_time_index
>= 0)
6129 emit_shader_time_end();
6135 assign_curb_setup();
6136 assign_vs_urb_setup();
6138 fixup_3src_null_dest();
6139 allocate_registers(8, true);
6145 fs_visitor::run_tcs_single_patch()
6147 assert(stage
== MESA_SHADER_TESS_CTRL
);
6149 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
6151 /* r1-r4 contain the ICP handles. */
6152 payload
.num_regs
= 5;
6154 if (shader_time_index
>= 0)
6155 emit_shader_time_begin();
6157 /* Initialize gl_InvocationID */
6158 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6159 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6160 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6161 bld
.MOV(channels_ud
, channels_uw
);
6163 if (tcs_prog_data
->instances
== 1) {
6164 invocation_id
= channels_ud
;
6166 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6168 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6169 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6170 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6171 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6172 brw_imm_ud(INTEL_MASK(23, 17)));
6173 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6175 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6178 /* Fix the disptach mask */
6179 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6180 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6181 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
6182 bld
.IF(BRW_PREDICATE_NORMAL
);
6187 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6188 bld
.emit(BRW_OPCODE_ENDIF
);
6191 /* Emit EOT write; set TR DS Cache bit */
6193 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6194 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6195 fs_reg(brw_imm_ud(0)),
6197 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6198 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6200 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6201 bld
.null_reg_ud(), payload
);
6205 if (shader_time_index
>= 0)
6206 emit_shader_time_end();
6215 assign_curb_setup();
6216 assign_tcs_single_patch_urb_setup();
6218 fixup_3src_null_dest();
6219 allocate_registers(8, true);
6225 fs_visitor::run_tes()
6227 assert(stage
== MESA_SHADER_TESS_EVAL
);
6229 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6230 payload
.num_regs
= 5;
6232 if (shader_time_index
>= 0)
6233 emit_shader_time_begin();
6242 if (shader_time_index
>= 0)
6243 emit_shader_time_end();
6249 assign_curb_setup();
6250 assign_tes_urb_setup();
6252 fixup_3src_null_dest();
6253 allocate_registers(8, true);
6259 fs_visitor::run_gs()
6261 assert(stage
== MESA_SHADER_GEOMETRY
);
6265 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6267 if (gs_compile
->control_data_header_size_bits
> 0) {
6268 /* Create a VGRF to store accumulated control data bits. */
6269 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6271 /* If we're outputting more than 32 control data bits, then EmitVertex()
6272 * will set control_data_bits to 0 after emitting the first vertex.
6273 * Otherwise, we need to initialize it to 0 here.
6275 if (gs_compile
->control_data_header_size_bits
<= 32) {
6276 const fs_builder abld
= bld
.annotate("initialize control data bits");
6277 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6281 if (shader_time_index
>= 0)
6282 emit_shader_time_begin();
6286 emit_gs_thread_end();
6288 if (shader_time_index
>= 0)
6289 emit_shader_time_end();
6298 assign_curb_setup();
6299 assign_gs_urb_setup();
6301 fixup_3src_null_dest();
6302 allocate_registers(8, true);
6307 /* From the SKL PRM, Volume 16, Workarounds:
6309 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
6310 * only header phases (R0-R2)
6312 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
6313 * have been header only.
6315 * Instead of enabling push constants one can alternatively enable one of the
6316 * inputs. Here one simply chooses "layer" which shouldn't impose much
6320 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
6322 if (wm_prog_data
->num_varying_inputs
)
6325 if (wm_prog_data
->base
.curb_read_length
)
6328 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
6329 wm_prog_data
->num_varying_inputs
= 1;
6333 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6335 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6336 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6338 assert(stage
== MESA_SHADER_FRAGMENT
);
6340 if (devinfo
->gen
>= 6)
6341 setup_fs_payload_gen6();
6343 setup_fs_payload_gen4();
6347 } else if (do_rep_send
) {
6348 assert(dispatch_width
== 16);
6349 emit_repclear_shader();
6351 if (shader_time_index
>= 0)
6352 emit_shader_time_begin();
6354 calculate_urb_setup();
6355 if (nir
->info
.inputs_read
> 0 ||
6356 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6357 if (devinfo
->gen
< 6)
6358 emit_interpolation_setup_gen4();
6360 emit_interpolation_setup_gen6();
6363 /* We handle discards by keeping track of the still-live pixels in f0.1.
6364 * Initialize it with the dispatched pixels.
6366 if (wm_prog_data
->uses_kill
) {
6367 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6368 discard_init
->flag_subreg
= 1;
6371 /* Generate FS IR for main(). (the visitor only descends into
6372 * functions called "main").
6379 if (wm_prog_data
->uses_kill
)
6380 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6382 if (wm_key
->alpha_test_func
)
6387 if (shader_time_index
>= 0)
6388 emit_shader_time_end();
6394 assign_curb_setup();
6396 if (devinfo
->gen
>= 9)
6397 gen9_ps_header_only_workaround(wm_prog_data
);
6401 fixup_3src_null_dest();
6402 allocate_registers(8, allow_spilling
);
6412 fs_visitor::run_cs(unsigned min_dispatch_width
)
6414 assert(stage
== MESA_SHADER_COMPUTE
);
6415 assert(dispatch_width
>= min_dispatch_width
);
6419 if (shader_time_index
>= 0)
6420 emit_shader_time_begin();
6422 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6423 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6424 const fs_builder abld
= bld
.exec_all().group(1, 0);
6425 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6426 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6434 emit_cs_terminate();
6436 if (shader_time_index
>= 0)
6437 emit_shader_time_end();
6443 assign_curb_setup();
6445 fixup_3src_null_dest();
6446 allocate_registers(min_dispatch_width
, true);
6455 * Return a bitfield where bit n is set if barycentric interpolation mode n
6456 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6458 * We examine the load_barycentric intrinsics rather than looking at input
6459 * variables so that we catch interpolateAtCentroid() messages too, which
6460 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6463 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6464 const nir_shader
*shader
)
6466 unsigned barycentric_interp_modes
= 0;
6468 nir_foreach_function(f
, shader
) {
6472 nir_foreach_block(block
, f
->impl
) {
6473 nir_foreach_instr(instr
, block
) {
6474 if (instr
->type
!= nir_instr_type_intrinsic
)
6477 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6478 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6481 /* Ignore WPOS; it doesn't require interpolation. */
6482 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6485 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6486 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6487 nir_intrinsic_interp_mode(intrin
);
6488 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6489 enum brw_barycentric_mode bary
=
6490 brw_barycentric_mode(interp
, bary_op
);
6492 barycentric_interp_modes
|= 1 << bary
;
6494 if (devinfo
->needs_unlit_centroid_workaround
&&
6495 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6496 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6501 return barycentric_interp_modes
;
6505 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6506 const nir_shader
*shader
)
6508 prog_data
->flat_inputs
= 0;
6510 nir_foreach_variable(var
, &shader
->inputs
) {
6511 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6513 if (input_index
< 0)
6517 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6518 prog_data
->flat_inputs
|= (1 << input_index
);
6523 computed_depth_mode(const nir_shader
*shader
)
6525 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6526 switch (shader
->info
.fs
.depth_layout
) {
6527 case FRAG_DEPTH_LAYOUT_NONE
:
6528 case FRAG_DEPTH_LAYOUT_ANY
:
6529 return BRW_PSCDEPTH_ON
;
6530 case FRAG_DEPTH_LAYOUT_GREATER
:
6531 return BRW_PSCDEPTH_ON_GE
;
6532 case FRAG_DEPTH_LAYOUT_LESS
:
6533 return BRW_PSCDEPTH_ON_LE
;
6534 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6535 return BRW_PSCDEPTH_OFF
;
6538 return BRW_PSCDEPTH_OFF
;
6542 * Move load_interpolated_input with simple (payload-based) barycentric modes
6543 * to the top of the program so we don't emit multiple PLNs for the same input.
6545 * This works around CSE not being able to handle non-dominating cases
6551 * interpolate the same exact input
6554 * This should be replaced by global value numbering someday.
6557 move_interpolation_to_top(nir_shader
*nir
)
6559 bool progress
= false;
6561 nir_foreach_function(f
, nir
) {
6565 nir_block
*top
= nir_start_block(f
->impl
);
6566 exec_node
*cursor_node
= NULL
;
6568 nir_foreach_block(block
, f
->impl
) {
6572 nir_foreach_instr_safe(instr
, block
) {
6573 if (instr
->type
!= nir_instr_type_intrinsic
)
6576 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6577 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6579 nir_intrinsic_instr
*bary_intrinsic
=
6580 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6581 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6583 /* Leave interpolateAtSample/Offset() where they are. */
6584 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6585 op
== nir_intrinsic_load_barycentric_at_offset
)
6588 nir_instr
*move
[3] = {
6589 &bary_intrinsic
->instr
,
6590 intrin
->src
[1].ssa
->parent_instr
,
6594 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6595 if (move
[i
]->block
!= top
) {
6596 move
[i
]->block
= top
;
6597 exec_node_remove(&move
[i
]->node
);
6599 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6601 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6603 cursor_node
= &move
[i
]->node
;
6609 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6610 ((unsigned) nir_metadata_block_index
|
6611 (unsigned) nir_metadata_dominance
));
6618 * Demote per-sample barycentric intrinsics to centroid.
6620 * Useful when rendering to a non-multisampled buffer.
6623 demote_sample_qualifiers(nir_shader
*nir
)
6625 bool progress
= true;
6627 nir_foreach_function(f
, nir
) {
6632 nir_builder_init(&b
, f
->impl
);
6634 nir_foreach_block(block
, f
->impl
) {
6635 nir_foreach_instr_safe(instr
, block
) {
6636 if (instr
->type
!= nir_instr_type_intrinsic
)
6639 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6640 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6641 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6644 b
.cursor
= nir_before_instr(instr
);
6645 nir_ssa_def
*centroid
=
6646 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6647 nir_intrinsic_interp_mode(intrin
));
6648 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6649 nir_src_for_ssa(centroid
));
6650 nir_instr_remove(instr
);
6655 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6656 ((unsigned) nir_metadata_block_index
|
6657 (unsigned) nir_metadata_dominance
));
6664 * Pre-gen6, the register file of the EUs was shared between threads,
6665 * and each thread used some subset allocated on a 16-register block
6666 * granularity. The unit states wanted these block counts.
6669 brw_register_blocks(int reg_count
)
6671 return ALIGN(reg_count
, 16) / 16 - 1;
6675 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6677 const struct brw_wm_prog_key
*key
,
6678 struct brw_wm_prog_data
*prog_data
,
6679 const nir_shader
*src_shader
,
6680 struct gl_program
*prog
,
6681 int shader_time_index8
, int shader_time_index16
,
6682 bool allow_spilling
,
6683 bool use_rep_send
, struct brw_vue_map
*vue_map
,
6686 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
6688 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6689 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6690 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
6691 brw_nir_lower_fs_outputs(shader
);
6693 if (devinfo
->gen
< 6) {
6694 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
, devinfo
);
6697 if (!key
->multisample_fbo
)
6698 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6699 NIR_PASS_V(shader
, move_interpolation_to_top
);
6700 shader
= brw_postprocess_nir(shader
, compiler
, true);
6702 /* key->alpha_test_func means simulating alpha testing via discards,
6703 * so the shader definitely kills pixels.
6705 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
6706 key
->alpha_test_func
;
6707 prog_data
->uses_omask
= key
->multisample_fbo
&&
6708 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6709 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6710 prog_data
->computed_stencil
=
6711 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6713 prog_data
->persample_dispatch
=
6714 key
->multisample_fbo
&&
6715 (key
->persample_interp
||
6716 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6717 SYSTEM_BIT_SAMPLE_POS
)) ||
6718 shader
->info
.fs
.uses_sample_qualifier
||
6719 shader
->info
.outputs_read
);
6721 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
6723 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6724 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
6725 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
6727 prog_data
->barycentric_interp_modes
=
6728 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6730 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6731 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6732 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6734 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6735 &prog_data
->base
, prog
, shader
, 8,
6736 shader_time_index8
);
6737 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6739 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6742 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6744 simd8_grf_start
= v8
.payload
.num_regs
;
6745 simd8_grf_used
= v8
.grf_used
;
6748 if (v8
.max_dispatch_width
>= 16 &&
6749 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6750 /* Try a SIMD16 compile */
6751 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6752 &prog_data
->base
, prog
, shader
, 16,
6753 shader_time_index16
);
6754 v16
.import_uniforms(&v8
);
6755 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6756 compiler
->shader_perf_log(log_data
,
6757 "SIMD16 shader failed to compile: %s",
6760 simd16_cfg
= v16
.cfg
;
6761 simd16_grf_start
= v16
.payload
.num_regs
;
6762 simd16_grf_used
= v16
.grf_used
;
6766 /* When the caller requests a repclear shader, they want SIMD16-only */
6770 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6771 * at the top to select the shader. We've never implemented that.
6772 * Instead, we just give them exactly one shader and we pick the widest one
6775 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6778 if (prog_data
->persample_dispatch
) {
6779 /* Starting with SandyBridge (where we first get MSAA), the different
6780 * pixel dispatch combinations are grouped into classifications A
6781 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6782 * generations, the only configurations supporting persample dispatch
6783 * are are this in which only one dispatch width is enabled.
6785 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6786 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6788 if (compiler
->devinfo
->gen
== 6 &&
6789 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6791 } else if (simd16_cfg
) {
6796 /* We have to compute the flat inputs after the visitor is finished running
6797 * because it relies on prog_data->urb_setup which is computed in
6798 * fs_visitor::calculate_urb_setup().
6800 brw_compute_flat_inputs(prog_data
, shader
);
6802 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6803 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6804 MESA_SHADER_FRAGMENT
);
6806 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6807 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6808 shader
->info
.label
?
6809 shader
->info
.label
: "unnamed",
6810 shader
->info
.name
));
6814 prog_data
->dispatch_8
= true;
6815 g
.generate_code(simd8_cfg
, 8);
6816 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6817 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6820 prog_data
->dispatch_16
= true;
6821 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6822 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6823 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6825 } else if (simd16_cfg
) {
6826 prog_data
->dispatch_16
= true;
6827 g
.generate_code(simd16_cfg
, 16);
6828 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6829 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6832 return g
.get_assembly(&prog_data
->base
.program_size
);
6836 fs_visitor::emit_cs_work_group_id_setup()
6838 assert(stage
== MESA_SHADER_COMPUTE
);
6840 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6842 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6843 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6844 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6846 bld
.MOV(*reg
, r0_1
);
6847 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6848 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6854 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6856 block
->dwords
= dwords
;
6857 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6858 block
->size
= block
->regs
* 32;
6862 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6863 struct brw_cs_prog_data
*cs_prog_data
)
6865 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
6866 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
6867 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6869 /* The thread ID should be stored in the last param dword */
6870 assert(subgroup_id_index
== -1 ||
6871 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
6873 unsigned cross_thread_dwords
, per_thread_dwords
;
6874 if (!cross_thread_supported
) {
6875 cross_thread_dwords
= 0u;
6876 per_thread_dwords
= prog_data
->nr_params
;
6877 } else if (subgroup_id_index
>= 0) {
6878 /* Fill all but the last register with cross-thread payload */
6879 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
6880 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6881 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6883 /* Fill all data using cross-thread payload */
6884 cross_thread_dwords
= prog_data
->nr_params
;
6885 per_thread_dwords
= 0u;
6888 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6889 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6891 unsigned total_dwords
=
6892 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6893 cs_prog_data
->push
.cross_thread
.size
) / 4;
6894 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6896 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6897 cs_prog_data
->push
.per_thread
.size
== 0);
6898 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6899 cs_prog_data
->push
.per_thread
.dwords
==
6900 prog_data
->nr_params
);
6904 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6906 cs_prog_data
->simd_size
= size
;
6907 unsigned group_size
= cs_prog_data
->local_size
[0] *
6908 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6909 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6913 compile_cs_to_nir(const struct brw_compiler
*compiler
,
6915 const struct brw_cs_prog_key
*key
,
6916 struct brw_cs_prog_data
*prog_data
,
6917 const nir_shader
*src_shader
,
6918 unsigned dispatch_width
)
6920 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6921 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6922 brw_nir_lower_cs_intrinsics(shader
, dispatch_width
);
6923 return brw_postprocess_nir(shader
, compiler
, true);
6927 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6929 const struct brw_cs_prog_key
*key
,
6930 struct brw_cs_prog_data
*prog_data
,
6931 const nir_shader
*src_shader
,
6932 int shader_time_index
,
6935 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
6936 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
6937 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
6938 unsigned local_workgroup_size
=
6939 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
6940 src_shader
->info
.cs
.local_size
[2];
6942 unsigned min_dispatch_width
=
6943 DIV_ROUND_UP(local_workgroup_size
, compiler
->devinfo
->max_cs_threads
);
6944 min_dispatch_width
= MAX2(8, min_dispatch_width
);
6945 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
6946 assert(min_dispatch_width
<= 32);
6948 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
6950 const char *fail_msg
= NULL
;
6951 unsigned promoted_constants
;
6953 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6955 if (min_dispatch_width
<= 8) {
6956 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
6957 prog_data
, src_shader
, 8);
6958 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6959 NULL
, /* Never used in core profile */
6960 nir8
, 8, shader_time_index
);
6961 if (!v8
->run_cs(min_dispatch_width
)) {
6962 fail_msg
= v8
->fail_msg
;
6964 /* We should always be able to do SIMD32 for compute shaders */
6965 assert(v8
->max_dispatch_width
>= 32);
6968 cs_set_simd_size(prog_data
, 8);
6969 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6970 promoted_constants
= v8
->promoted_constants
;
6974 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6975 !fail_msg
&& min_dispatch_width
<= 16) {
6976 /* Try a SIMD16 compile */
6977 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
6978 prog_data
, src_shader
, 16);
6979 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6980 NULL
, /* Never used in core profile */
6981 nir16
, 16, shader_time_index
);
6983 v16
->import_uniforms(v8
);
6985 if (!v16
->run_cs(min_dispatch_width
)) {
6986 compiler
->shader_perf_log(log_data
,
6987 "SIMD16 shader failed to compile: %s",
6991 "Couldn't generate SIMD16 program and not "
6992 "enough threads for SIMD8";
6995 /* We should always be able to do SIMD32 for compute shaders */
6996 assert(v16
->max_dispatch_width
>= 32);
6999 cs_set_simd_size(prog_data
, 16);
7000 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7001 promoted_constants
= v16
->promoted_constants
;
7005 /* We should always be able to do SIMD32 for compute shaders */
7006 assert(!v16
|| v16
->max_dispatch_width
>= 32);
7008 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
7009 /* Try a SIMD32 compile */
7010 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
7011 prog_data
, src_shader
, 32);
7012 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
7013 NULL
, /* Never used in core profile */
7014 nir32
, 32, shader_time_index
);
7016 v32
->import_uniforms(v8
);
7018 v32
->import_uniforms(v16
);
7020 if (!v32
->run_cs(min_dispatch_width
)) {
7021 compiler
->shader_perf_log(log_data
,
7022 "SIMD32 shader failed to compile: %s",
7026 "Couldn't generate SIMD32 program and not "
7027 "enough threads for SIMD16";
7031 cs_set_simd_size(prog_data
, 32);
7032 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
7033 promoted_constants
= v32
->promoted_constants
;
7037 const unsigned *ret
= NULL
;
7038 if (unlikely(cfg
== NULL
)) {
7041 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
7043 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
7044 promoted_constants
, false, MESA_SHADER_COMPUTE
);
7045 if (INTEL_DEBUG
& DEBUG_CS
) {
7046 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
7047 src_shader
->info
.label
?
7048 src_shader
->info
.label
: "unnamed",
7049 src_shader
->info
.name
);
7050 g
.enable_debug(name
);
7053 g
.generate_code(cfg
, prog_data
->simd_size
);
7055 ret
= g
.get_assembly(&prog_data
->base
.program_size
);
7066 * Test the dispatch mask packing assumptions of
7067 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
7068 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
7069 * executed with an unexpected dispatch mask.
7072 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
7074 const gl_shader_stage stage
= bld
.shader
->stage
;
7076 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
7077 bld
.shader
->stage_prog_data
)) {
7078 const fs_builder ubld
= bld
.exec_all().group(1, 0);
7079 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
7080 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
7083 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
7084 ubld
.AND(tmp
, mask
, tmp
);
7086 /* This will loop forever if the dispatch mask doesn't have the expected
7087 * form '2^n-1', in which case tmp will be non-zero.
7089 bld
.emit(BRW_OPCODE_DO
);
7090 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
7091 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));