2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
35 #include "brw_vec4_gs_visitor.h"
37 #include "brw_dead_control_flow.h"
38 #include "common/gen_debug.h"
39 #include "compiler/glsl_types.h"
40 #include "compiler/nir/nir_builder.h"
41 #include "program/prog_parameter.h"
45 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
49 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
50 const fs_reg
*src
, unsigned sources
)
52 memset(this, 0, sizeof(*this));
54 this->src
= new fs_reg
[MAX2(sources
, 3)];
55 for (unsigned i
= 0; i
< sources
; i
++)
56 this->src
[i
] = src
[i
];
58 this->opcode
= opcode
;
60 this->sources
= sources
;
61 this->exec_size
= exec_size
;
64 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
66 assert(this->exec_size
!= 0);
68 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
70 /* This will be the case for almost all instructions. */
77 this->size_written
= dst
.component_size(exec_size
);
80 this->size_written
= 0;
84 unreachable("Invalid destination register file");
87 this->writes_accumulator
= false;
92 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
95 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
97 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
100 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
102 init(opcode
, exec_size
, dst
, NULL
, 0);
105 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
108 const fs_reg src
[1] = { src0
};
109 init(opcode
, exec_size
, dst
, src
, 1);
112 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
113 const fs_reg
&src0
, const fs_reg
&src1
)
115 const fs_reg src
[2] = { src0
, src1
};
116 init(opcode
, exec_size
, dst
, src
, 2);
119 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
120 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
122 const fs_reg src
[3] = { src0
, src1
, src2
};
123 init(opcode
, exec_size
, dst
, src
, 3);
126 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
127 const fs_reg src
[], unsigned sources
)
129 init(opcode
, exec_width
, dst
, src
, sources
);
132 fs_inst::fs_inst(const fs_inst
&that
)
134 memcpy(this, &that
, sizeof(that
));
136 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
138 for (unsigned i
= 0; i
< that
.sources
; i
++)
139 this->src
[i
] = that
.src
[i
];
148 fs_inst::resize_sources(uint8_t num_sources
)
150 if (this->sources
!= num_sources
) {
151 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
153 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
154 src
[i
] = this->src
[i
];
158 this->sources
= num_sources
;
163 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
165 const fs_reg
&surf_index
,
166 const fs_reg
&varying_offset
,
167 uint32_t const_offset
)
169 /* We have our constant surface use a pitch of 4 bytes, so our index can
170 * be any component of a vector, and then we load 4 contiguous
171 * components starting from that.
173 * We break down the const_offset to a portion added to the variable offset
174 * and a portion done using fs_reg::offset, which means that if you have
175 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
176 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
177 * later notice that those loads are all the same and eliminate the
180 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
181 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
183 /* The pull load message will load a vec4 (16 bytes). If we are loading
184 * a double this means we are only loading 2 elements worth of data.
185 * We also want to use a 32-bit data type for the dst of the load operation
186 * so other parts of the driver don't get confused about the size of the
189 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
190 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
191 vec4_result
, surf_index
, vec4_offset
);
192 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
194 if (type_sz(dst
.type
) == 8) {
195 shuffle_32bit_load_result_to_64bit_data(
196 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
199 vec4_result
.type
= dst
.type
;
200 bld
.MOV(dst
, offset(vec4_result
, bld
,
201 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
205 * A helper for MOV generation for fixing up broken hardware SEND dependency
209 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
211 /* The caller always wants uncompressed to emit the minimal extra
212 * dependencies, and to avoid having to deal with aligning its regs to 2.
214 const fs_builder ubld
= bld
.annotate("send dependency resolve")
217 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
221 fs_inst::equals(fs_inst
*inst
) const
223 return (opcode
== inst
->opcode
&&
224 dst
.equals(inst
->dst
) &&
225 src
[0].equals(inst
->src
[0]) &&
226 src
[1].equals(inst
->src
[1]) &&
227 src
[2].equals(inst
->src
[2]) &&
228 saturate
== inst
->saturate
&&
229 predicate
== inst
->predicate
&&
230 conditional_mod
== inst
->conditional_mod
&&
231 mlen
== inst
->mlen
&&
232 base_mrf
== inst
->base_mrf
&&
233 target
== inst
->target
&&
235 header_size
== inst
->header_size
&&
236 shadow_compare
== inst
->shadow_compare
&&
237 exec_size
== inst
->exec_size
&&
238 offset
== inst
->offset
);
242 fs_inst::is_send_from_grf() const
245 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
246 case SHADER_OPCODE_SHADER_TIME_ADD
:
247 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
248 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
249 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
250 case SHADER_OPCODE_UNTYPED_ATOMIC
:
251 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
252 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
253 case SHADER_OPCODE_TYPED_ATOMIC
:
254 case SHADER_OPCODE_TYPED_SURFACE_READ
:
255 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
256 case SHADER_OPCODE_URB_WRITE_SIMD8
:
257 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
258 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
259 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
260 case SHADER_OPCODE_URB_READ_SIMD8
:
261 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
263 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
264 return src
[1].file
== VGRF
;
265 case FS_OPCODE_FB_WRITE
:
266 case FS_OPCODE_FB_READ
:
267 return src
[0].file
== VGRF
;
270 return src
[0].file
== VGRF
;
277 * Returns true if this instruction's sources and destinations cannot
278 * safely be the same register.
280 * In most cases, a register can be written over safely by the same
281 * instruction that is its last use. For a single instruction, the
282 * sources are dereferenced before writing of the destination starts
285 * However, there are a few cases where this can be problematic:
287 * - Virtual opcodes that translate to multiple instructions in the
288 * code generator: if src == dst and one instruction writes the
289 * destination before a later instruction reads the source, then
290 * src will have been clobbered.
292 * - SIMD16 compressed instructions with certain regioning (see below).
294 * The register allocator uses this information to set up conflicts between
295 * GRF sources and the destination.
298 fs_inst::has_source_and_destination_hazard() const
301 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
302 /* Multiple partial writes to the destination */
305 /* The SIMD16 compressed instruction
307 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
309 * is actually decoded in hardware as:
311 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
312 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
314 * Which is safe. However, if we have uniform accesses
315 * happening, we get into trouble:
317 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
318 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
320 * Now our destination for the first instruction overwrote the
321 * second instruction's src0, and we get garbage for those 8
322 * pixels. There's a similar issue for the pre-gen6
323 * pixel_x/pixel_y, which are registers of 16-bit values and thus
324 * would get stomped by the first decode as well.
326 if (exec_size
== 16) {
327 for (int i
= 0; i
< sources
; i
++) {
328 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
329 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
330 src
[i
].type
== BRW_REGISTER_TYPE_W
||
331 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
332 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
342 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
344 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
347 fs_reg reg
= this->src
[0];
348 if (reg
.file
!= VGRF
|| reg
.offset
!= 0 || reg
.stride
!= 1)
351 if (grf_alloc
.sizes
[reg
.nr
] * REG_SIZE
!= this->size_written
)
354 for (int i
= 0; i
< this->sources
; i
++) {
355 reg
.type
= this->src
[i
].type
;
356 if (!this->src
[i
].equals(reg
))
359 if (i
< this->header_size
) {
360 reg
.offset
+= REG_SIZE
;
362 reg
= horiz_offset(reg
, this->exec_size
);
370 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
)
372 if (devinfo
->gen
== 6 && is_math())
375 if (is_send_from_grf())
378 if (!backend_instruction::can_do_source_mods())
385 fs_inst::can_change_types() const
387 return dst
.type
== src
[0].type
&&
388 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
389 (opcode
== BRW_OPCODE_MOV
||
390 (opcode
== BRW_OPCODE_SEL
&&
391 dst
.type
== src
[1].type
&&
392 predicate
!= BRW_PREDICATE_NONE
&&
393 !src
[1].abs
&& !src
[1].negate
));
397 fs_inst::has_side_effects() const
399 return this->eot
|| backend_instruction::has_side_effects();
405 memset(this, 0, sizeof(*this));
406 type
= BRW_REGISTER_TYPE_UD
;
410 /** Generic unset register constructor. */
414 this->file
= BAD_FILE
;
417 fs_reg::fs_reg(struct ::brw_reg reg
) :
422 if (this->file
== IMM
&&
423 (this->type
!= BRW_REGISTER_TYPE_V
&&
424 this->type
!= BRW_REGISTER_TYPE_UV
&&
425 this->type
!= BRW_REGISTER_TYPE_VF
)) {
431 fs_reg::equals(const fs_reg
&r
) const
433 return (this->backend_reg::equals(r
) &&
438 fs_reg::is_contiguous() const
444 fs_reg::component_size(unsigned width
) const
446 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
449 return MAX2(width
* stride
, 1) * type_sz(type
);
453 type_size_scalar(const struct glsl_type
*type
)
455 unsigned int size
, i
;
457 switch (type
->base_type
) {
460 case GLSL_TYPE_FLOAT
:
462 return type
->components();
463 case GLSL_TYPE_DOUBLE
:
464 case GLSL_TYPE_UINT64
:
465 case GLSL_TYPE_INT64
:
466 return type
->components() * 2;
467 case GLSL_TYPE_ARRAY
:
468 return type_size_scalar(type
->fields
.array
) * type
->length
;
469 case GLSL_TYPE_STRUCT
:
471 for (i
= 0; i
< type
->length
; i
++) {
472 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
475 case GLSL_TYPE_SAMPLER
:
476 /* Samplers take up no register space, since they're baked in at
480 case GLSL_TYPE_ATOMIC_UINT
:
482 case GLSL_TYPE_SUBROUTINE
:
484 case GLSL_TYPE_IMAGE
:
485 return BRW_IMAGE_PARAM_SIZE
;
487 case GLSL_TYPE_ERROR
:
488 case GLSL_TYPE_INTERFACE
:
489 case GLSL_TYPE_FUNCTION
:
490 unreachable("not reached");
497 * Create a MOV to read the timestamp register.
499 * The caller is responsible for emitting the MOV. The return value is
500 * the destination of the MOV, with extra parameters set.
503 fs_visitor::get_timestamp(const fs_builder
&bld
)
505 assert(devinfo
->gen
>= 7);
507 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
510 BRW_REGISTER_TYPE_UD
));
512 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
514 /* We want to read the 3 fields we care about even if it's not enabled in
517 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
523 fs_visitor::emit_shader_time_begin()
525 /* We want only the low 32 bits of the timestamp. Since it's running
526 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
527 * which is plenty of time for our purposes. It is identical across the
528 * EUs, but since it's tracking GPU core speed it will increment at a
529 * varying rate as render P-states change.
531 shader_start_time
= component(
532 get_timestamp(bld
.annotate("shader time start")), 0);
536 fs_visitor::emit_shader_time_end()
538 /* Insert our code just before the final SEND with EOT. */
539 exec_node
*end
= this->instructions
.get_tail();
540 assert(end
&& ((fs_inst
*) end
)->eot
);
541 const fs_builder ibld
= bld
.annotate("shader time end")
542 .exec_all().at(NULL
, end
);
543 const fs_reg timestamp
= get_timestamp(ibld
);
545 /* We only use the low 32 bits of the timestamp - see
546 * emit_shader_time_begin()).
548 * We could also check if render P-states have changed (or anything
549 * else that might disrupt timing) by setting smear to 2 and checking if
550 * that field is != 0.
552 const fs_reg shader_end_time
= component(timestamp
, 0);
554 /* Check that there weren't any timestamp reset events (assuming these
555 * were the only two timestamp reads that happened).
557 const fs_reg reset
= component(timestamp
, 2);
558 set_condmod(BRW_CONDITIONAL_Z
,
559 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
560 ibld
.IF(BRW_PREDICATE_NORMAL
);
562 fs_reg start
= shader_start_time
;
564 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
565 BRW_REGISTER_TYPE_UD
),
567 const fs_builder cbld
= ibld
.group(1, 0);
568 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
570 /* If there were no instructions between the two timestamp gets, the diff
571 * is 2 cycles. Remove that overhead, so I can forget about that when
572 * trying to determine the time taken for single instructions.
574 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
575 SHADER_TIME_ADD(cbld
, 0, diff
);
576 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
577 ibld
.emit(BRW_OPCODE_ELSE
);
578 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
579 ibld
.emit(BRW_OPCODE_ENDIF
);
583 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
584 int shader_time_subindex
,
587 int index
= shader_time_index
* 3 + shader_time_subindex
;
588 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
591 if (dispatch_width
== 8)
592 payload
= vgrf(glsl_type::uvec2_type
);
594 payload
= vgrf(glsl_type::uint_type
);
596 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
600 fs_visitor::vfail(const char *format
, va_list va
)
609 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
610 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
612 this->fail_msg
= msg
;
615 fprintf(stderr
, "%s", msg
);
620 fs_visitor::fail(const char *format
, ...)
624 va_start(va
, format
);
630 * Mark this program as impossible to compile with dispatch width greater
633 * During the SIMD8 compile (which happens first), we can detect and flag
634 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
635 * SIMD16+ compile altogether.
637 * During a compile of dispatch width greater than n (if one happens anyway),
638 * this just calls fail().
641 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
643 if (dispatch_width
> n
) {
646 max_dispatch_width
= n
;
647 compiler
->shader_perf_log(log_data
,
648 "Shader dispatch width limited to SIMD%d: %s",
654 * Returns true if the instruction has a flag that means it won't
655 * update an entire destination register.
657 * For example, dead code elimination and live variable analysis want to know
658 * when a write to a variable screens off any preceding values that were in
662 fs_inst::is_partial_write() const
664 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
665 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
666 !this->dst
.is_contiguous() ||
667 this->dst
.offset
% REG_SIZE
!= 0);
671 fs_inst::components_read(unsigned i
) const
673 /* Return zero if the source is not present. */
674 if (src
[i
].file
== BAD_FILE
)
678 case FS_OPCODE_LINTERP
:
684 case FS_OPCODE_PIXEL_X
:
685 case FS_OPCODE_PIXEL_Y
:
689 case FS_OPCODE_FB_WRITE_LOGICAL
:
690 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
691 /* First/second FB write color. */
693 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
697 case SHADER_OPCODE_TEX_LOGICAL
:
698 case SHADER_OPCODE_TXD_LOGICAL
:
699 case SHADER_OPCODE_TXF_LOGICAL
:
700 case SHADER_OPCODE_TXL_LOGICAL
:
701 case SHADER_OPCODE_TXS_LOGICAL
:
702 case FS_OPCODE_TXB_LOGICAL
:
703 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
704 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
705 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
706 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
707 case SHADER_OPCODE_LOD_LOGICAL
:
708 case SHADER_OPCODE_TG4_LOGICAL
:
709 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
710 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
711 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
712 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
713 /* Texture coordinates. */
714 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
715 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
716 /* Texture derivatives. */
717 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
718 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
719 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
720 /* Texture offset. */
721 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
724 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
729 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
730 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
731 assert(src
[3].file
== IMM
);
732 /* Surface coordinates. */
735 /* Surface operation source (ignored for reads). */
741 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
742 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
743 assert(src
[3].file
== IMM
&&
745 /* Surface coordinates. */
748 /* Surface operation source. */
754 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
755 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
756 assert(src
[3].file
== IMM
&&
758 const unsigned op
= src
[4].ud
;
759 /* Surface coordinates. */
762 /* Surface operation source. */
763 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
765 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
766 op
== BRW_AOP_PREDEC
))
778 fs_inst::size_read(int arg
) const
781 case FS_OPCODE_FB_WRITE
:
782 case FS_OPCODE_FB_READ
:
783 case SHADER_OPCODE_URB_WRITE_SIMD8
:
784 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
785 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
786 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
787 case SHADER_OPCODE_URB_READ_SIMD8
:
788 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
789 case SHADER_OPCODE_UNTYPED_ATOMIC
:
790 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
791 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
792 case SHADER_OPCODE_TYPED_ATOMIC
:
793 case SHADER_OPCODE_TYPED_SURFACE_READ
:
794 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
795 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
797 return mlen
* REG_SIZE
;
800 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
801 /* The payload is actually stored in src1 */
803 return mlen
* REG_SIZE
;
806 case FS_OPCODE_LINTERP
:
811 case SHADER_OPCODE_LOAD_PAYLOAD
:
812 if (arg
< this->header_size
)
816 case CS_OPCODE_CS_TERMINATE
:
817 case SHADER_OPCODE_BARRIER
:
820 case SHADER_OPCODE_MOV_INDIRECT
:
822 assert(src
[2].file
== IMM
);
828 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
829 return mlen
* REG_SIZE
;
833 switch (src
[arg
].file
) {
836 return components_read(arg
) * type_sz(src
[arg
].type
);
842 return components_read(arg
) * src
[arg
].component_size(exec_size
);
844 unreachable("MRF registers are not allowed as sources");
850 /* Return the subset of flag registers that an instruction could
851 * potentially read or write based on the execution controls and flag
852 * subregister number of the instruction.
855 flag_mask(const fs_inst
*inst
)
857 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
858 const unsigned end
= start
+ inst
->exec_size
;
859 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
865 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
869 flag_mask(const fs_reg
&r
, unsigned sz
)
872 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
873 const unsigned end
= start
+ sz
;
874 return bit_mask(end
) & ~bit_mask(start
);
882 fs_inst::flags_read(const gen_device_info
*devinfo
) const
884 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
885 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
886 /* The vertical predication modes combine corresponding bits from
887 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
889 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
890 return flag_mask(this) << shift
| flag_mask(this);
891 } else if (predicate
) {
892 return flag_mask(this);
895 for (int i
= 0; i
< sources
; i
++) {
896 mask
|= flag_mask(src
[i
], size_read(i
));
903 fs_inst::flags_written() const
905 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
906 opcode
!= BRW_OPCODE_IF
&&
907 opcode
!= BRW_OPCODE_WHILE
)) ||
908 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
909 return flag_mask(this);
911 return flag_mask(dst
, size_written
);
916 * Returns how many MRFs an FS opcode will write over.
918 * Note that this is not the 0 or 1 implied writes in an actual gen
919 * instruction -- the FS opcodes often generate MOVs in addition.
922 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
927 if (inst
->base_mrf
== -1)
930 switch (inst
->opcode
) {
931 case SHADER_OPCODE_RCP
:
932 case SHADER_OPCODE_RSQ
:
933 case SHADER_OPCODE_SQRT
:
934 case SHADER_OPCODE_EXP2
:
935 case SHADER_OPCODE_LOG2
:
936 case SHADER_OPCODE_SIN
:
937 case SHADER_OPCODE_COS
:
938 return 1 * dispatch_width
/ 8;
939 case SHADER_OPCODE_POW
:
940 case SHADER_OPCODE_INT_QUOTIENT
:
941 case SHADER_OPCODE_INT_REMAINDER
:
942 return 2 * dispatch_width
/ 8;
943 case SHADER_OPCODE_TEX
:
945 case SHADER_OPCODE_TXD
:
946 case SHADER_OPCODE_TXF
:
947 case SHADER_OPCODE_TXF_CMS
:
948 case SHADER_OPCODE_TXF_MCS
:
949 case SHADER_OPCODE_TG4
:
950 case SHADER_OPCODE_TG4_OFFSET
:
951 case SHADER_OPCODE_TXL
:
952 case SHADER_OPCODE_TXS
:
953 case SHADER_OPCODE_LOD
:
954 case SHADER_OPCODE_SAMPLEINFO
:
956 case FS_OPCODE_FB_WRITE
:
958 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
959 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
961 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
963 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
966 unreachable("not reached");
971 fs_visitor::vgrf(const glsl_type
*const type
)
973 int reg_width
= dispatch_width
/ 8;
974 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
975 brw_type_for_base_type(type
));
978 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
983 this->type
= BRW_REGISTER_TYPE_F
;
984 this->stride
= (file
== UNIFORM
? 0 : 1);
987 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
993 this->stride
= (file
== UNIFORM
? 0 : 1);
996 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
997 * This brings in those uniform definitions
1000 fs_visitor::import_uniforms(fs_visitor
*v
)
1002 this->push_constant_loc
= v
->push_constant_loc
;
1003 this->pull_constant_loc
= v
->pull_constant_loc
;
1004 this->uniforms
= v
->uniforms
;
1008 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1010 assert(stage
== MESA_SHADER_FRAGMENT
);
1012 /* gl_FragCoord.x */
1013 bld
.MOV(wpos
, this->pixel_x
);
1014 wpos
= offset(wpos
, bld
, 1);
1016 /* gl_FragCoord.y */
1017 bld
.MOV(wpos
, this->pixel_y
);
1018 wpos
= offset(wpos
, bld
, 1);
1020 /* gl_FragCoord.z */
1021 if (devinfo
->gen
>= 6) {
1022 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1024 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1025 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1026 interp_reg(VARYING_SLOT_POS
, 2));
1028 wpos
= offset(wpos
, bld
, 1);
1030 /* gl_FragCoord.w: Already set up in emit_interpolation */
1031 bld
.MOV(wpos
, this->wpos_w
);
1034 enum brw_barycentric_mode
1035 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1037 /* Barycentric modes don't make sense for flat inputs. */
1038 assert(mode
!= INTERP_MODE_FLAT
);
1042 case nir_intrinsic_load_barycentric_pixel
:
1043 case nir_intrinsic_load_barycentric_at_offset
:
1044 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1046 case nir_intrinsic_load_barycentric_centroid
:
1047 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1049 case nir_intrinsic_load_barycentric_sample
:
1050 case nir_intrinsic_load_barycentric_at_sample
:
1051 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1054 unreachable("invalid intrinsic");
1057 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1060 return (enum brw_barycentric_mode
) bary
;
1064 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1066 static enum brw_barycentric_mode
1067 centroid_to_pixel(enum brw_barycentric_mode bary
)
1069 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1070 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1071 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1075 fs_visitor::emit_frontfacing_interpolation()
1077 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1079 if (devinfo
->gen
>= 6) {
1080 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1081 * a boolean result from this (~0/true or 0/false).
1083 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1084 * this task in only one instruction:
1085 * - a negation source modifier will flip the bit; and
1086 * - a W -> D type conversion will sign extend the bit into the high
1087 * word of the destination.
1089 * An ASR 15 fills the low word of the destination.
1091 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1094 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1096 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1097 * a boolean result from this (1/true or 0/false).
1099 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1100 * the negation source modifier to flip it. Unfortunately the SHR
1101 * instruction only operates on UD (or D with an abs source modifier)
1102 * sources without negation.
1104 * Instead, use ASR (which will give ~0/true or 0/false).
1106 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1109 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1116 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1118 assert(stage
== MESA_SHADER_FRAGMENT
);
1119 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1120 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1122 if (wm_prog_data
->persample_dispatch
) {
1123 /* Convert int_sample_pos to floating point */
1124 bld
.MOV(dst
, int_sample_pos
);
1125 /* Scale to the range [0, 1] */
1126 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1129 /* From ARB_sample_shading specification:
1130 * "When rendering to a non-multisample buffer, or if multisample
1131 * rasterization is disabled, gl_SamplePosition will always be
1134 bld
.MOV(dst
, brw_imm_f(0.5f
));
1139 fs_visitor::emit_samplepos_setup()
1141 assert(devinfo
->gen
>= 6);
1143 const fs_builder abld
= bld
.annotate("compute sample position");
1144 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1146 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1147 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1149 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1150 * mode will be enabled.
1152 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1153 * R31.1:0 Position Offset X/Y for Slot[3:0]
1154 * R31.3:2 Position Offset X/Y for Slot[7:4]
1157 * The X, Y sample positions come in as bytes in thread payload. So, read
1158 * the positions using vstride=16, width=8, hstride=2.
1160 struct brw_reg sample_pos_reg
=
1161 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1162 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1164 if (dispatch_width
== 8) {
1165 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1167 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1168 abld
.half(1).MOV(half(int_sample_x
, 1),
1169 fs_reg(suboffset(sample_pos_reg
, 16)));
1171 /* Compute gl_SamplePosition.x */
1172 compute_sample_position(pos
, int_sample_x
);
1173 pos
= offset(pos
, abld
, 1);
1174 if (dispatch_width
== 8) {
1175 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1177 abld
.half(0).MOV(half(int_sample_y
, 0),
1178 fs_reg(suboffset(sample_pos_reg
, 1)));
1179 abld
.half(1).MOV(half(int_sample_y
, 1),
1180 fs_reg(suboffset(sample_pos_reg
, 17)));
1182 /* Compute gl_SamplePosition.y */
1183 compute_sample_position(pos
, int_sample_y
);
1188 fs_visitor::emit_sampleid_setup()
1190 assert(stage
== MESA_SHADER_FRAGMENT
);
1191 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1192 assert(devinfo
->gen
>= 6);
1194 const fs_builder abld
= bld
.annotate("compute sample id");
1195 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1197 if (!key
->multisample_fbo
) {
1198 /* As per GL_ARB_sample_shading specification:
1199 * "When rendering to a non-multisample buffer, or if multisample
1200 * rasterization is disabled, gl_SampleID will always be zero."
1202 abld
.MOV(*reg
, brw_imm_d(0));
1203 } else if (devinfo
->gen
>= 8) {
1204 /* Sample ID comes in as 4-bit numbers in g1.0:
1206 * 15:12 Slot 3 SampleID (only used in SIMD16)
1207 * 11:8 Slot 2 SampleID (only used in SIMD16)
1208 * 7:4 Slot 1 SampleID
1209 * 3:0 Slot 0 SampleID
1211 * Each slot corresponds to four channels, so we want to replicate each
1212 * half-byte value to 4 channels in a row:
1214 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1215 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1217 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1218 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1220 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1221 * channels to read the first byte (7:0), and the second group of 8
1222 * channels to read the second byte (15:8). Then, we shift right by
1223 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1224 * values into place. Finally, we AND with 0xf to keep the low nibble.
1226 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1227 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1229 * TODO: These payload bits exist on Gen7 too, but they appear to always
1230 * be zero, so this code fails to work. We should find out why.
1232 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1234 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1235 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1236 brw_imm_v(0x44440000));
1237 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1239 const fs_reg t1
= component(fs_reg(VGRF
, alloc
.allocate(1),
1240 BRW_REGISTER_TYPE_D
), 0);
1241 const fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1243 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1244 * 8x multisampling, subspan 0 will represent sample N (where N
1245 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1246 * 7. We can find the value of N by looking at R0.0 bits 7:6
1247 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1248 * (since samples are always delivered in pairs). That is, we
1249 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1250 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1251 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1252 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1253 * populating a temporary variable with the sequence (0, 1, 2, 3),
1254 * and then reading from it using vstride=1, width=4, hstride=0.
1255 * These computations hold good for 4x multisampling as well.
1257 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1258 * the first four slots are sample 0 of subspan 0; the next four
1259 * are sample 1 of subspan 0; the third group is sample 0 of
1260 * subspan 1, and finally sample 1 of subspan 1.
1263 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1264 * accomodate 16x MSAA.
1266 abld
.exec_all().group(1, 0)
1267 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1269 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1271 /* This works for both SIMD8 and SIMD16 */
1272 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1274 /* This special instruction takes care of setting vstride=1,
1275 * width=4, hstride=0 of t2 during an ADD instruction.
1277 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1284 fs_visitor::emit_samplemaskin_setup()
1286 assert(stage
== MESA_SHADER_FRAGMENT
);
1287 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1288 assert(devinfo
->gen
>= 6);
1290 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1292 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1293 BRW_REGISTER_TYPE_D
));
1295 if (wm_prog_data
->persample_dispatch
) {
1296 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1297 * and a mask representing which sample is being processed by the
1298 * current shader invocation.
1300 * From the OES_sample_variables specification:
1301 * "When per-sample shading is active due to the use of a fragment input
1302 * qualified by "sample" or due to the use of the gl_SampleID or
1303 * gl_SamplePosition variables, only the bit for the current sample is
1304 * set in gl_SampleMaskIn."
1306 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1308 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1309 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1311 fs_reg one
= vgrf(glsl_type::int_type
);
1312 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1313 abld
.MOV(one
, brw_imm_d(1));
1314 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1315 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1317 /* In per-pixel mode, the coverage mask is sufficient. */
1318 *reg
= coverage_mask
;
1324 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1326 if (!src
.abs
&& !src
.negate
)
1329 fs_reg temp
= bld
.vgrf(src
.type
);
1336 fs_visitor::emit_discard_jump()
1338 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1340 /* For performance, after a discard, jump to the end of the
1341 * shader if all relevant channels have been discarded.
1343 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1344 discard_jump
->flag_subreg
= 1;
1346 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1347 discard_jump
->predicate_inverse
= true;
1351 fs_visitor::emit_gs_thread_end()
1353 assert(stage
== MESA_SHADER_GEOMETRY
);
1355 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1357 if (gs_compile
->control_data_header_size_bits
> 0) {
1358 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1361 const fs_builder abld
= bld
.annotate("thread end");
1364 if (gs_prog_data
->static_vertex_count
!= -1) {
1365 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1366 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1367 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1368 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1369 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1372 /* Delete now dead instructions. */
1373 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1379 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1383 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1384 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1385 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1388 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1389 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1390 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1391 sources
[1] = this->final_gs_vertex_count
;
1392 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1393 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1401 fs_visitor::assign_curb_setup()
1403 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1405 unsigned ubo_push_length
= 0;
1406 unsigned ubo_push_start
[4];
1407 for (int i
= 0; i
< 4; i
++) {
1408 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1409 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1412 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1414 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1415 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1416 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1417 if (inst
->src
[i
].file
== UNIFORM
) {
1418 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1420 if (inst
->src
[i
].nr
>= UBO_START
) {
1421 /* constant_nr is in 32-bit units, the rest are in bytes */
1422 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1423 inst
->src
[i
].offset
/ 4;
1424 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1425 constant_nr
= push_constant_loc
[uniform_nr
];
1427 /* Section 5.11 of the OpenGL 4.1 spec says:
1428 * "Out-of-bounds reads return undefined values, which include
1429 * values from other variables of the active program or zero."
1430 * Just return the first push constant.
1435 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1438 brw_reg
.abs
= inst
->src
[i
].abs
;
1439 brw_reg
.negate
= inst
->src
[i
].negate
;
1441 assert(inst
->src
[i
].stride
== 0);
1442 inst
->src
[i
] = byte_offset(
1443 retype(brw_reg
, inst
->src
[i
].type
),
1444 inst
->src
[i
].offset
% 4);
1449 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1450 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1454 fs_visitor::calculate_urb_setup()
1456 assert(stage
== MESA_SHADER_FRAGMENT
);
1457 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1458 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1460 memset(prog_data
->urb_setup
, -1,
1461 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1464 /* Figure out where each of the incoming setup attributes lands. */
1465 if (devinfo
->gen
>= 6) {
1466 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1467 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1468 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1469 * first 16 varying inputs, so we can put them wherever we want.
1470 * Just put them in order.
1472 * This is useful because it means that (a) inputs not used by the
1473 * fragment shader won't take up valuable register space, and (b) we
1474 * won't have to recompile the fragment shader if it gets paired with
1475 * a different vertex (or geometry) shader.
1477 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1478 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1479 BITFIELD64_BIT(i
)) {
1480 prog_data
->urb_setup
[i
] = urb_next
++;
1484 /* We have enough input varyings that the SF/SBE pipeline stage can't
1485 * arbitrarily rearrange them to suit our whim; we have to put them
1486 * in an order that matches the output of the previous pipeline stage
1487 * (geometry or vertex shader).
1489 struct brw_vue_map prev_stage_vue_map
;
1490 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1491 key
->input_slots_valid
,
1492 nir
->info
.separate_shader
);
1495 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1496 &prev_stage_vue_map
);
1498 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1499 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1501 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1502 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1503 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1504 BITFIELD64_BIT(varying
))) {
1505 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1508 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1511 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1512 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1513 /* Point size is packed into the header, not as a general attribute */
1514 if (i
== VARYING_SLOT_PSIZ
)
1517 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1518 /* The back color slot is skipped when the front color is
1519 * also written to. In addition, some slots can be
1520 * written in the vertex shader and not read in the
1521 * fragment shader. So the register number must always be
1522 * incremented, mapped or not.
1524 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1525 prog_data
->urb_setup
[i
] = urb_next
;
1531 * It's a FS only attribute, and we did interpolation for this attribute
1532 * in SF thread. So, count it here, too.
1534 * See compile_sf_prog() for more info.
1536 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1537 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1540 prog_data
->num_varying_inputs
= urb_next
;
1544 fs_visitor::assign_urb_setup()
1546 assert(stage
== MESA_SHADER_FRAGMENT
);
1547 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1549 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1551 /* Offset all the urb_setup[] index by the actual position of the
1552 * setup regs, now that the location of the constants has been chosen.
1554 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1555 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1556 assert(inst
->src
[1].file
== FIXED_GRF
);
1557 inst
->src
[1].nr
+= urb_start
;
1560 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1561 assert(inst
->src
[0].file
== FIXED_GRF
);
1562 inst
->src
[0].nr
+= urb_start
;
1566 /* Each attribute is 4 setup channels, each of which is half a reg. */
1567 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1571 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1573 for (int i
= 0; i
< inst
->sources
; i
++) {
1574 if (inst
->src
[i
].file
== ATTR
) {
1575 int grf
= payload
.num_regs
+
1576 prog_data
->curb_read_length
+
1578 inst
->src
[i
].offset
/ REG_SIZE
;
1580 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1582 * VertStride must be used to cross GRF register boundaries. This
1583 * rule implies that elements within a 'Width' cannot cross GRF
1586 * So, for registers that are large enough, we have to split the exec
1587 * size in two and trust the compression state to sort it out.
1589 unsigned total_size
= inst
->exec_size
*
1590 inst
->src
[i
].stride
*
1591 type_sz(inst
->src
[i
].type
);
1593 assert(total_size
<= 2 * REG_SIZE
);
1594 const unsigned exec_size
=
1595 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1597 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1598 struct brw_reg reg
=
1599 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1600 inst
->src
[i
].offset
% REG_SIZE
),
1601 exec_size
* inst
->src
[i
].stride
,
1602 width
, inst
->src
[i
].stride
);
1603 reg
.abs
= inst
->src
[i
].abs
;
1604 reg
.negate
= inst
->src
[i
].negate
;
1612 fs_visitor::assign_vs_urb_setup()
1614 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1616 assert(stage
== MESA_SHADER_VERTEX
);
1618 /* Each attribute is 4 regs. */
1619 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1621 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1623 /* Rewrite all ATTR file references to the hw grf that they land in. */
1624 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1625 convert_attr_sources_to_hw_regs(inst
);
1630 fs_visitor::assign_tcs_single_patch_urb_setup()
1632 assert(stage
== MESA_SHADER_TESS_CTRL
);
1634 /* Rewrite all ATTR file references to HW_REGs. */
1635 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1636 convert_attr_sources_to_hw_regs(inst
);
1641 fs_visitor::assign_tes_urb_setup()
1643 assert(stage
== MESA_SHADER_TESS_EVAL
);
1645 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1647 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1649 /* Rewrite all ATTR file references to HW_REGs. */
1650 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1651 convert_attr_sources_to_hw_regs(inst
);
1656 fs_visitor::assign_gs_urb_setup()
1658 assert(stage
== MESA_SHADER_GEOMETRY
);
1660 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1662 first_non_payload_grf
+=
1663 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1665 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1666 /* Rewrite all ATTR file references to GRFs. */
1667 convert_attr_sources_to_hw_regs(inst
);
1673 * Split large virtual GRFs into separate components if we can.
1675 * This is mostly duplicated with what brw_fs_vector_splitting does,
1676 * but that's really conservative because it's afraid of doing
1677 * splitting that doesn't result in real progress after the rest of
1678 * the optimization phases, which would cause infinite looping in
1679 * optimization. We can do it once here, safely. This also has the
1680 * opportunity to split interpolated values, or maybe even uniforms,
1681 * which we don't have at the IR level.
1683 * We want to split, because virtual GRFs are what we register
1684 * allocate and spill (due to contiguousness requirements for some
1685 * instructions), and they're what we naturally generate in the
1686 * codegen process, but most virtual GRFs don't actually need to be
1687 * contiguous sets of GRFs. If we split, we'll end up with reduced
1688 * live intervals and better dead code elimination and coalescing.
1691 fs_visitor::split_virtual_grfs()
1693 /* Compact the register file so we eliminate dead vgrfs. This
1694 * only defines split points for live registers, so if we have
1695 * too large dead registers they will hit assertions later.
1697 compact_virtual_grfs();
1699 int num_vars
= this->alloc
.count
;
1701 /* Count the total number of registers */
1703 int vgrf_to_reg
[num_vars
];
1704 for (int i
= 0; i
< num_vars
; i
++) {
1705 vgrf_to_reg
[i
] = reg_count
;
1706 reg_count
+= alloc
.sizes
[i
];
1709 /* An array of "split points". For each register slot, this indicates
1710 * if this slot can be separated from the previous slot. Every time an
1711 * instruction uses multiple elements of a register (as a source or
1712 * destination), we mark the used slots as inseparable. Then we go
1713 * through and split the registers into the smallest pieces we can.
1715 bool split_points
[reg_count
];
1716 memset(split_points
, 0, sizeof(split_points
));
1718 /* Mark all used registers as fully splittable */
1719 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1720 if (inst
->dst
.file
== VGRF
) {
1721 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1722 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1723 split_points
[reg
+ j
] = true;
1726 for (int i
= 0; i
< inst
->sources
; i
++) {
1727 if (inst
->src
[i
].file
== VGRF
) {
1728 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1729 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1730 split_points
[reg
+ j
] = true;
1735 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1736 if (inst
->dst
.file
== VGRF
) {
1737 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1738 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1739 split_points
[reg
+ j
] = false;
1741 for (int i
= 0; i
< inst
->sources
; i
++) {
1742 if (inst
->src
[i
].file
== VGRF
) {
1743 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1744 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1745 split_points
[reg
+ j
] = false;
1750 int new_virtual_grf
[reg_count
];
1751 int new_reg_offset
[reg_count
];
1754 for (int i
= 0; i
< num_vars
; i
++) {
1755 /* The first one should always be 0 as a quick sanity check. */
1756 assert(split_points
[reg
] == false);
1759 new_reg_offset
[reg
] = 0;
1764 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1765 /* If this is a split point, reset the offset to 0 and allocate a
1766 * new virtual GRF for the previous offset many registers
1768 if (split_points
[reg
]) {
1769 assert(offset
<= MAX_VGRF_SIZE
);
1770 int grf
= alloc
.allocate(offset
);
1771 for (int k
= reg
- offset
; k
< reg
; k
++)
1772 new_virtual_grf
[k
] = grf
;
1775 new_reg_offset
[reg
] = offset
;
1780 /* The last one gets the original register number */
1781 assert(offset
<= MAX_VGRF_SIZE
);
1782 alloc
.sizes
[i
] = offset
;
1783 for (int k
= reg
- offset
; k
< reg
; k
++)
1784 new_virtual_grf
[k
] = i
;
1786 assert(reg
== reg_count
);
1788 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1789 if (inst
->dst
.file
== VGRF
) {
1790 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1791 inst
->dst
.nr
= new_virtual_grf
[reg
];
1792 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
1793 inst
->dst
.offset
% REG_SIZE
;
1794 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1796 for (int i
= 0; i
< inst
->sources
; i
++) {
1797 if (inst
->src
[i
].file
== VGRF
) {
1798 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1799 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1800 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
1801 inst
->src
[i
].offset
% REG_SIZE
;
1802 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1806 invalidate_live_intervals();
1810 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1812 * During code generation, we create tons of temporary variables, many of
1813 * which get immediately killed and are never used again. Yet, in later
1814 * optimization and analysis passes, such as compute_live_intervals, we need
1815 * to loop over all the virtual GRFs. Compacting them can save a lot of
1819 fs_visitor::compact_virtual_grfs()
1821 bool progress
= false;
1822 int remap_table
[this->alloc
.count
];
1823 memset(remap_table
, -1, sizeof(remap_table
));
1825 /* Mark which virtual GRFs are used. */
1826 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1827 if (inst
->dst
.file
== VGRF
)
1828 remap_table
[inst
->dst
.nr
] = 0;
1830 for (int i
= 0; i
< inst
->sources
; i
++) {
1831 if (inst
->src
[i
].file
== VGRF
)
1832 remap_table
[inst
->src
[i
].nr
] = 0;
1836 /* Compact the GRF arrays. */
1838 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1839 if (remap_table
[i
] == -1) {
1840 /* We just found an unused register. This means that we are
1841 * actually going to compact something.
1845 remap_table
[i
] = new_index
;
1846 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1847 invalidate_live_intervals();
1852 this->alloc
.count
= new_index
;
1854 /* Patch all the instructions to use the newly renumbered registers */
1855 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1856 if (inst
->dst
.file
== VGRF
)
1857 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1859 for (int i
= 0; i
< inst
->sources
; i
++) {
1860 if (inst
->src
[i
].file
== VGRF
)
1861 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1865 /* Patch all the references to delta_xy, since they're used in register
1866 * allocation. If they're unused, switch them to BAD_FILE so we don't
1867 * think some random VGRF is delta_xy.
1869 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1870 if (delta_xy
[i
].file
== VGRF
) {
1871 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1872 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1874 delta_xy
[i
].file
= BAD_FILE
;
1883 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
,
1884 unsigned *max_chunk_bitsize
,
1885 bool contiguous
, unsigned bitsize
,
1886 const unsigned target_bitsize
,
1887 int *push_constant_loc
, int *pull_constant_loc
,
1888 unsigned *num_push_constants
,
1889 unsigned *num_pull_constants
,
1890 const unsigned max_push_components
,
1891 const unsigned max_chunk_size
,
1892 bool allow_pull_constants
,
1893 struct brw_stage_prog_data
*stage_prog_data
)
1895 /* This is the first live uniform in the chunk */
1896 if (*chunk_start
< 0)
1897 *chunk_start
= uniform
;
1899 /* Keep track of the maximum bit size access in contiguous uniforms */
1900 *max_chunk_bitsize
= MAX2(*max_chunk_bitsize
, bitsize
);
1902 /* If this element does not need to be contiguous with the next, we
1903 * split at this point and everything between chunk_start and u forms a
1907 /* If bitsize doesn't match the target one, skip it */
1908 if (*max_chunk_bitsize
!= target_bitsize
) {
1909 /* FIXME: right now we only support 32 and 64-bit accesses */
1910 assert(*max_chunk_bitsize
== 4 || *max_chunk_bitsize
== 8);
1911 *max_chunk_bitsize
= 0;
1916 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
1918 /* Decide whether we should push or pull this parameter. In the
1919 * Vulkan driver, push constants are explicitly exposed via the API
1920 * so we push everything. In GL, we only push small arrays.
1922 if (!allow_pull_constants
||
1923 (*num_push_constants
+ chunk_size
<= max_push_components
&&
1924 chunk_size
<= max_chunk_size
)) {
1925 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
1926 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1927 push_constant_loc
[j
] = (*num_push_constants
)++;
1929 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
1930 pull_constant_loc
[j
] = (*num_pull_constants
)++;
1933 *max_chunk_bitsize
= 0;
1939 * Assign UNIFORM file registers to either push constants or pull constants.
1941 * We allow a fragment shader to have more than the specified minimum
1942 * maximum number of fragment shader uniform components (64). If
1943 * there are too many of these, they'd fill up all of register space.
1944 * So, this will push some of them out to the pull constant buffer and
1945 * update the program to load them.
1948 fs_visitor::assign_constant_locations()
1950 /* Only the first compile gets to decide on locations. */
1951 if (dispatch_width
!= min_dispatch_width
)
1954 bool is_live
[uniforms
];
1955 memset(is_live
, 0, sizeof(is_live
));
1956 unsigned bitsize_access
[uniforms
];
1957 memset(bitsize_access
, 0, sizeof(bitsize_access
));
1959 /* For each uniform slot, a value of true indicates that the given slot and
1960 * the next slot must remain contiguous. This is used to keep us from
1961 * splitting arrays apart.
1963 bool contiguous
[uniforms
];
1964 memset(contiguous
, 0, sizeof(contiguous
));
1966 int thread_local_id_index
=
1967 (stage
== MESA_SHADER_COMPUTE
) ?
1968 brw_cs_prog_data(stage_prog_data
)->thread_local_id_index
: -1;
1970 /* First, we walk through the instructions and do two things:
1972 * 1) Figure out which uniforms are live.
1974 * 2) Mark any indirectly used ranges of registers as contiguous.
1976 * Note that we don't move constant-indexed accesses to arrays. No
1977 * testing has been done of the performance impact of this choice.
1979 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1980 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1981 if (inst
->src
[i
].file
!= UNIFORM
)
1984 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1986 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
1987 assert(inst
->src
[2].ud
% 4 == 0);
1988 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
1989 assert(last
< uniforms
);
1991 for (unsigned j
= constant_nr
; j
< last
; j
++) {
1993 contiguous
[j
] = true;
1994 bitsize_access
[j
] = MAX2(bitsize_access
[j
], type_sz(inst
->src
[i
].type
));
1996 is_live
[last
] = true;
1997 bitsize_access
[last
] = MAX2(bitsize_access
[last
], type_sz(inst
->src
[i
].type
));
1999 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2000 int regs_read
= inst
->components_read(i
) *
2001 type_sz(inst
->src
[i
].type
) / 4;
2002 for (int j
= 0; j
< regs_read
; j
++) {
2003 is_live
[constant_nr
+ j
] = true;
2004 bitsize_access
[constant_nr
+ j
] =
2005 MAX2(bitsize_access
[constant_nr
+ j
], type_sz(inst
->src
[i
].type
));
2012 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
2013 thread_local_id_index
= -1;
2015 /* Only allow 16 registers (128 uniform components) as push constants.
2017 * Just demote the end of the list. We could probably do better
2018 * here, demoting things that are rarely used in the program first.
2020 * If changing this value, note the limitation about total_regs in
2023 unsigned int max_push_components
= 16 * 8;
2024 if (thread_local_id_index
>= 0)
2025 max_push_components
--; /* Save a slot for the thread ID */
2027 /* We push small arrays, but no bigger than 16 floats. This is big enough
2028 * for a vec4 but hopefully not large enough to push out other stuff. We
2029 * should probably use a better heuristic at some point.
2031 const unsigned int max_chunk_size
= 16;
2033 unsigned int num_push_constants
= 0;
2034 unsigned int num_pull_constants
= 0;
2036 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2037 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2039 /* Default to -1 meaning no location */
2040 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2041 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2043 int chunk_start
= -1;
2044 unsigned max_chunk_bitsize
= 0;
2046 /* First push 64-bit uniforms to ensure they are properly aligned */
2047 const unsigned uniform_64_bit_size
= type_sz(BRW_REGISTER_TYPE_DF
);
2048 for (unsigned u
= 0; u
< uniforms
; u
++) {
2052 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2053 contiguous
[u
], bitsize_access
[u
],
2054 uniform_64_bit_size
,
2055 push_constant_loc
, pull_constant_loc
,
2056 &num_push_constants
, &num_pull_constants
,
2057 max_push_components
, max_chunk_size
,
2058 compiler
->supports_pull_constants
,
2063 /* Then push the rest of uniforms */
2064 const unsigned uniform_32_bit_size
= type_sz(BRW_REGISTER_TYPE_F
);
2065 for (unsigned u
= 0; u
< uniforms
; u
++) {
2069 /* Skip thread_local_id_index to put it in the last push register. */
2070 if (thread_local_id_index
== (int)u
)
2073 set_push_pull_constant_loc(u
, &chunk_start
, &max_chunk_bitsize
,
2074 contiguous
[u
], bitsize_access
[u
],
2075 uniform_32_bit_size
,
2076 push_constant_loc
, pull_constant_loc
,
2077 &num_push_constants
, &num_pull_constants
,
2078 max_push_components
, max_chunk_size
,
2079 compiler
->supports_pull_constants
,
2083 /* Add the CS local thread ID uniform at the end of the push constants */
2084 if (thread_local_id_index
>= 0)
2085 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2087 /* As the uniforms are going to be reordered, take the data from a temporary
2088 * copy of the original param[].
2090 uint32_t *param
= ralloc_array(NULL
, uint32_t, stage_prog_data
->nr_params
);
2091 memcpy(param
, stage_prog_data
->param
,
2092 sizeof(uint32_t) * stage_prog_data
->nr_params
);
2093 stage_prog_data
->nr_params
= num_push_constants
;
2094 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2096 /* Now that we know how many regular uniforms we'll push, reduce the
2097 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2099 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2100 for (int i
= 0; i
< 4; i
++) {
2101 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2103 if (push_length
+ range
->length
> 64)
2104 range
->length
= 64 - push_length
;
2106 push_length
+= range
->length
;
2108 assert(push_length
<= 64);
2110 /* Up until now, the param[] array has been indexed by reg + offset
2111 * of UNIFORM registers. Move pull constants into pull_param[] and
2112 * condense param[] to only contain the uniforms we chose to push.
2114 * NOTE: Because we are condensing the params[] array, we know that
2115 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2116 * having to make a copy.
2118 int new_thread_local_id_index
= -1;
2119 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2120 uint32_t value
= param
[i
];
2121 if (pull_constant_loc
[i
] != -1) {
2122 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2123 } else if (push_constant_loc
[i
] != -1) {
2124 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2125 if (thread_local_id_index
== (int)i
)
2126 new_thread_local_id_index
= push_constant_loc
[i
];
2131 if (stage
== MESA_SHADER_COMPUTE
)
2132 brw_cs_prog_data(stage_prog_data
)->thread_local_id_index
=
2133 new_thread_local_id_index
;
2137 fs_visitor::get_pull_locs(const fs_reg
&src
,
2138 unsigned *out_surf_index
,
2139 unsigned *out_pull_index
)
2141 assert(src
.file
== UNIFORM
);
2143 if (src
.nr
>= UBO_START
) {
2144 const struct brw_ubo_range
*range
=
2145 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2147 /* If this access is in our (reduced) range, use the push data. */
2148 if (src
.offset
/ 32 < range
->length
)
2151 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2152 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2156 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2158 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2159 /* A regular uniform push constant */
2160 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2161 *out_pull_index
= pull_constant_loc
[location
];
2169 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2170 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2173 fs_visitor::lower_constant_loads()
2175 unsigned index
, pull_index
;
2177 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2178 /* Set up the annotation tracking for new generated instructions. */
2179 const fs_builder
ibld(this, block
, inst
);
2181 for (int i
= 0; i
< inst
->sources
; i
++) {
2182 if (inst
->src
[i
].file
!= UNIFORM
)
2185 /* We'll handle this case later */
2186 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2189 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2192 assert(inst
->src
[i
].stride
== 0);
2194 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2195 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2196 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2197 const unsigned base
= pull_index
* 4;
2199 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2200 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2202 /* Rewrite the instruction to use the temporary VGRF. */
2203 inst
->src
[i
].file
= VGRF
;
2204 inst
->src
[i
].nr
= dst
.nr
;
2205 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2206 inst
->src
[i
].offset
% 4;
2208 brw_mark_surface_used(prog_data
, index
);
2211 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2212 inst
->src
[0].file
== UNIFORM
) {
2214 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2217 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2221 inst
->remove(block
);
2223 brw_mark_surface_used(prog_data
, index
);
2226 invalidate_live_intervals();
2230 fs_visitor::opt_algebraic()
2232 bool progress
= false;
2234 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2235 switch (inst
->opcode
) {
2236 case BRW_OPCODE_MOV
:
2237 if (inst
->src
[0].file
!= IMM
)
2240 if (inst
->saturate
) {
2241 if (inst
->dst
.type
!= inst
->src
[0].type
)
2242 assert(!"unimplemented: saturate mixed types");
2244 if (brw_saturate_immediate(inst
->dst
.type
,
2245 &inst
->src
[0].as_brw_reg())) {
2246 inst
->saturate
= false;
2252 case BRW_OPCODE_MUL
:
2253 if (inst
->src
[1].file
!= IMM
)
2257 if (inst
->src
[1].is_one()) {
2258 inst
->opcode
= BRW_OPCODE_MOV
;
2259 inst
->src
[1] = reg_undef
;
2265 if (inst
->src
[1].is_negative_one()) {
2266 inst
->opcode
= BRW_OPCODE_MOV
;
2267 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2268 inst
->src
[1] = reg_undef
;
2274 if (inst
->src
[1].is_zero()) {
2275 inst
->opcode
= BRW_OPCODE_MOV
;
2276 inst
->src
[0] = inst
->src
[1];
2277 inst
->src
[1] = reg_undef
;
2282 if (inst
->src
[0].file
== IMM
) {
2283 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2284 inst
->opcode
= BRW_OPCODE_MOV
;
2285 inst
->src
[0].f
*= inst
->src
[1].f
;
2286 inst
->src
[1] = reg_undef
;
2291 case BRW_OPCODE_ADD
:
2292 if (inst
->src
[1].file
!= IMM
)
2296 if (inst
->src
[1].is_zero()) {
2297 inst
->opcode
= BRW_OPCODE_MOV
;
2298 inst
->src
[1] = reg_undef
;
2303 if (inst
->src
[0].file
== IMM
) {
2304 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2305 inst
->opcode
= BRW_OPCODE_MOV
;
2306 inst
->src
[0].f
+= inst
->src
[1].f
;
2307 inst
->src
[1] = reg_undef
;
2313 if (inst
->src
[0].equals(inst
->src
[1])) {
2314 inst
->opcode
= BRW_OPCODE_MOV
;
2315 inst
->src
[1] = reg_undef
;
2320 case BRW_OPCODE_LRP
:
2321 if (inst
->src
[1].equals(inst
->src
[2])) {
2322 inst
->opcode
= BRW_OPCODE_MOV
;
2323 inst
->src
[0] = inst
->src
[1];
2324 inst
->src
[1] = reg_undef
;
2325 inst
->src
[2] = reg_undef
;
2330 case BRW_OPCODE_CMP
:
2331 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2333 inst
->src
[0].negate
&&
2334 inst
->src
[1].is_zero()) {
2335 inst
->src
[0].abs
= false;
2336 inst
->src
[0].negate
= false;
2337 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2342 case BRW_OPCODE_SEL
:
2343 if (inst
->src
[0].equals(inst
->src
[1])) {
2344 inst
->opcode
= BRW_OPCODE_MOV
;
2345 inst
->src
[1] = reg_undef
;
2346 inst
->predicate
= BRW_PREDICATE_NONE
;
2347 inst
->predicate_inverse
= false;
2349 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2350 switch (inst
->conditional_mod
) {
2351 case BRW_CONDITIONAL_LE
:
2352 case BRW_CONDITIONAL_L
:
2353 switch (inst
->src
[1].type
) {
2354 case BRW_REGISTER_TYPE_F
:
2355 if (inst
->src
[1].f
>= 1.0f
) {
2356 inst
->opcode
= BRW_OPCODE_MOV
;
2357 inst
->src
[1] = reg_undef
;
2358 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2366 case BRW_CONDITIONAL_GE
:
2367 case BRW_CONDITIONAL_G
:
2368 switch (inst
->src
[1].type
) {
2369 case BRW_REGISTER_TYPE_F
:
2370 if (inst
->src
[1].f
<= 0.0f
) {
2371 inst
->opcode
= BRW_OPCODE_MOV
;
2372 inst
->src
[1] = reg_undef
;
2373 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2385 case BRW_OPCODE_MAD
:
2386 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2387 inst
->opcode
= BRW_OPCODE_MOV
;
2388 inst
->src
[1] = reg_undef
;
2389 inst
->src
[2] = reg_undef
;
2391 } else if (inst
->src
[0].is_zero()) {
2392 inst
->opcode
= BRW_OPCODE_MUL
;
2393 inst
->src
[0] = inst
->src
[2];
2394 inst
->src
[2] = reg_undef
;
2396 } else if (inst
->src
[1].is_one()) {
2397 inst
->opcode
= BRW_OPCODE_ADD
;
2398 inst
->src
[1] = inst
->src
[2];
2399 inst
->src
[2] = reg_undef
;
2401 } else if (inst
->src
[2].is_one()) {
2402 inst
->opcode
= BRW_OPCODE_ADD
;
2403 inst
->src
[2] = reg_undef
;
2405 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2406 inst
->opcode
= BRW_OPCODE_ADD
;
2407 inst
->src
[1].f
*= inst
->src
[2].f
;
2408 inst
->src
[2] = reg_undef
;
2412 case SHADER_OPCODE_BROADCAST
:
2413 if (is_uniform(inst
->src
[0])) {
2414 inst
->opcode
= BRW_OPCODE_MOV
;
2416 inst
->force_writemask_all
= true;
2418 } else if (inst
->src
[1].file
== IMM
) {
2419 inst
->opcode
= BRW_OPCODE_MOV
;
2420 inst
->src
[0] = component(inst
->src
[0],
2423 inst
->force_writemask_all
= true;
2432 /* Swap if src[0] is immediate. */
2433 if (progress
&& inst
->is_commutative()) {
2434 if (inst
->src
[0].file
== IMM
) {
2435 fs_reg tmp
= inst
->src
[1];
2436 inst
->src
[1] = inst
->src
[0];
2445 * Optimize sample messages that have constant zero values for the trailing
2446 * texture coordinates. We can just reduce the message length for these
2447 * instructions instead of reserving a register for it. Trailing parameters
2448 * that aren't sent default to zero anyway. This will cause the dead code
2449 * eliminator to remove the MOV instruction that would otherwise be emitted to
2450 * set up the zero value.
2453 fs_visitor::opt_zero_samples()
2455 /* Gen4 infers the texturing opcode based on the message length so we can't
2458 if (devinfo
->gen
< 5)
2461 bool progress
= false;
2463 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2464 if (!inst
->is_tex())
2467 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2469 if (load_payload
->is_head_sentinel() ||
2470 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2473 /* We don't want to remove the message header or the first parameter.
2474 * Removing the first parameter is not allowed, see the Haswell PRM
2475 * volume 7, page 149:
2477 * "Parameter 0 is required except for the sampleinfo message, which
2478 * has no parameter 0"
2480 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2481 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2482 (inst
->exec_size
/ 8) +
2483 inst
->header_size
- 1].is_zero()) {
2484 inst
->mlen
-= inst
->exec_size
/ 8;
2490 invalidate_live_intervals();
2496 * Optimize sample messages which are followed by the final RT write.
2498 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2499 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2500 * final texturing results copied to the framebuffer write payload and modify
2501 * them to write to the framebuffer directly.
2504 fs_visitor::opt_sampler_eot()
2506 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2508 if (stage
!= MESA_SHADER_FRAGMENT
)
2511 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2514 /* FINISHME: It should be possible to implement this optimization when there
2515 * are multiple drawbuffers.
2517 if (key
->nr_color_regions
!= 1)
2520 /* Requires emitting a bunch of saturating MOV instructions during logical
2521 * send lowering to clamp the color payload, which the sampler unit isn't
2522 * going to do for us.
2524 if (key
->clamp_fragment_color
)
2527 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2528 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2529 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2530 assert(fb_write
->eot
);
2531 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2533 /* There wasn't one; nothing to do. */
2534 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2537 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2539 /* 3D Sampler » Messages » Message Format
2541 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2542 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2544 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2545 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2546 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2547 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2548 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2549 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2550 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2551 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2554 /* XXX - This shouldn't be necessary. */
2555 if (tex_inst
->prev
->is_head_sentinel())
2558 /* Check that the FB write sources are fully initialized by the single
2559 * texturing instruction.
2561 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2562 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2563 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2564 fb_write
->size_read(i
) != tex_inst
->size_written
)
2566 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2567 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2572 assert(!tex_inst
->eot
); /* We can't get here twice */
2573 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2575 const fs_builder
ibld(this, block
, tex_inst
);
2577 tex_inst
->offset
|= fb_write
->target
<< 24;
2578 tex_inst
->eot
= true;
2579 tex_inst
->dst
= ibld
.null_reg_ud();
2580 tex_inst
->size_written
= 0;
2581 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2583 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2584 * flag and submit a header together with the sampler message as required
2587 invalidate_live_intervals();
2592 fs_visitor::opt_register_renaming()
2594 bool progress
= false;
2597 int remap
[alloc
.count
];
2598 memset(remap
, -1, sizeof(int) * alloc
.count
);
2600 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2601 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2603 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2604 inst
->opcode
== BRW_OPCODE_WHILE
) {
2608 /* Rewrite instruction sources. */
2609 for (int i
= 0; i
< inst
->sources
; i
++) {
2610 if (inst
->src
[i
].file
== VGRF
&&
2611 remap
[inst
->src
[i
].nr
] != -1 &&
2612 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2613 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2618 const int dst
= inst
->dst
.nr
;
2621 inst
->dst
.file
== VGRF
&&
2622 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2623 !inst
->is_partial_write()) {
2624 if (remap
[dst
] == -1) {
2627 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2628 inst
->dst
.nr
= remap
[dst
];
2631 } else if (inst
->dst
.file
== VGRF
&&
2633 remap
[dst
] != dst
) {
2634 inst
->dst
.nr
= remap
[dst
];
2640 invalidate_live_intervals();
2642 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2643 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2644 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2653 * Remove redundant or useless discard jumps.
2655 * For example, we can eliminate jumps in the following sequence:
2657 * discard-jump (redundant with the next jump)
2658 * discard-jump (useless; jumps to the next instruction)
2662 fs_visitor::opt_redundant_discard_jumps()
2664 bool progress
= false;
2666 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2668 fs_inst
*placeholder_halt
= NULL
;
2669 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2670 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2671 placeholder_halt
= inst
;
2676 if (!placeholder_halt
)
2679 /* Delete any HALTs immediately before the placeholder halt. */
2680 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2681 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2682 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2683 prev
->remove(last_bblock
);
2688 invalidate_live_intervals();
2694 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2695 * from \p r.offset which overlaps the region starting at \p s.offset and
2696 * spanning \p ds bytes.
2698 static inline unsigned
2699 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
2701 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
2702 const int shift
= rel_offset
/ REG_SIZE
;
2703 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
2704 assert(reg_space(r
) == reg_space(s
) &&
2705 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
2706 return ((1 << n
) - 1) << shift
;
2710 fs_visitor::compute_to_mrf()
2712 bool progress
= false;
2715 /* No MRFs on Gen >= 7. */
2716 if (devinfo
->gen
>= 7)
2719 calculate_live_intervals();
2721 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2725 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2726 inst
->is_partial_write() ||
2727 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2728 inst
->dst
.type
!= inst
->src
[0].type
||
2729 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2730 !inst
->src
[0].is_contiguous() ||
2731 inst
->src
[0].offset
% REG_SIZE
!= 0)
2734 /* Can't compute-to-MRF this GRF if someone else was going to
2737 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2740 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2741 * things that computed the value of all GRFs of the source region. The
2742 * regs_left bitset keeps track of the registers we haven't yet found a
2743 * generating instruction for.
2745 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
2747 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2748 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2749 inst
->src
[0], inst
->size_read(0))) {
2750 /* Found the last thing to write our reg we want to turn
2751 * into a compute-to-MRF.
2754 /* If this one instruction didn't populate all the
2755 * channels, bail. We might be able to rewrite everything
2756 * that writes that reg, but it would require smarter
2759 if (scan_inst
->is_partial_write())
2762 /* Handling things not fully contained in the source of the copy
2763 * would need us to understand coalescing out more than one MOV at
2766 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
2767 inst
->src
[0], inst
->size_read(0)))
2770 /* SEND instructions can't have MRF as a destination. */
2771 if (scan_inst
->mlen
)
2774 if (devinfo
->gen
== 6) {
2775 /* gen6 math instructions must have the destination be
2776 * GRF, so no compute-to-MRF for them.
2778 if (scan_inst
->is_math()) {
2783 /* Clear the bits for any registers this instruction overwrites. */
2784 regs_left
&= ~mask_relative_to(
2785 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2790 /* We don't handle control flow here. Most computation of
2791 * values that end up in MRFs are shortly before the MRF
2794 if (block
->start() == scan_inst
)
2797 /* You can't read from an MRF, so if someone else reads our
2798 * MRF's source GRF that we wanted to rewrite, that stops us.
2800 bool interfered
= false;
2801 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2802 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
2803 inst
->src
[0], inst
->size_read(0))) {
2810 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2811 inst
->dst
, inst
->size_written
)) {
2812 /* If somebody else writes our MRF here, we can't
2813 * compute-to-MRF before that.
2818 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2819 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2820 inst
->dst
, inst
->size_written
)) {
2821 /* Found a SEND instruction, which means that there are
2822 * live values in MRFs from base_mrf to base_mrf +
2823 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2833 /* Found all generating instructions of our MRF's source value, so it
2834 * should be safe to rewrite them to point to the MRF directly.
2836 regs_left
= (1 << regs_read(inst
, 0)) - 1;
2838 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2839 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
2840 inst
->src
[0], inst
->size_read(0))) {
2841 /* Clear the bits for any registers this instruction overwrites. */
2842 regs_left
&= ~mask_relative_to(
2843 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
2845 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
2846 reg_offset(inst
->src
[0]);
2848 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2849 /* Apply the same address transformation done by the hardware
2850 * for COMPR4 MRF writes.
2852 assert(rel_offset
< 2 * REG_SIZE
);
2853 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
2855 /* Clear the COMPR4 bit if the generating instruction is not
2858 if (scan_inst
->size_written
< 2 * REG_SIZE
)
2859 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2862 /* Calculate the MRF number the result of this instruction is
2863 * ultimately written to.
2865 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
2868 scan_inst
->dst
.file
= MRF
;
2869 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
2870 scan_inst
->saturate
|= inst
->saturate
;
2877 inst
->remove(block
);
2882 invalidate_live_intervals();
2888 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2889 * flow. We could probably do better here with some form of divergence
2893 fs_visitor::eliminate_find_live_channel()
2895 bool progress
= false;
2898 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
2899 /* The optimization below assumes that channel zero is live on thread
2900 * dispatch, which may not be the case if the fixed function dispatches
2906 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2907 switch (inst
->opcode
) {
2913 case BRW_OPCODE_ENDIF
:
2914 case BRW_OPCODE_WHILE
:
2918 case FS_OPCODE_DISCARD_JUMP
:
2919 /* This can potentially make control flow non-uniform until the end
2924 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2926 inst
->opcode
= BRW_OPCODE_MOV
;
2927 inst
->src
[0] = brw_imm_ud(0u);
2929 inst
->force_writemask_all
= true;
2943 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2944 * instructions to FS_OPCODE_REP_FB_WRITE.
2947 fs_visitor::emit_repclear_shader()
2949 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2951 int color_mrf
= base_mrf
+ 2;
2955 mov
= bld
.exec_all().group(4, 0)
2956 .MOV(brw_message_reg(color_mrf
),
2957 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2959 struct brw_reg reg
=
2960 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
2961 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
2962 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2964 mov
= bld
.exec_all().group(4, 0)
2965 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
2969 if (key
->nr_color_regions
== 1) {
2970 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2971 write
->saturate
= key
->clamp_fragment_color
;
2972 write
->base_mrf
= color_mrf
;
2974 write
->header_size
= 0;
2977 assume(key
->nr_color_regions
> 0);
2978 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2979 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2980 write
->saturate
= key
->clamp_fragment_color
;
2981 write
->base_mrf
= base_mrf
;
2983 write
->header_size
= 2;
2991 assign_constant_locations();
2992 assign_curb_setup();
2994 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2996 assert(mov
->src
[0].file
== FIXED_GRF
);
2997 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3002 * Walks through basic blocks, looking for repeated MRF writes and
3003 * removing the later ones.
3006 fs_visitor::remove_duplicate_mrf_writes()
3008 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3009 bool progress
= false;
3011 /* Need to update the MRF tracking for compressed instructions. */
3012 if (dispatch_width
>= 16)
3015 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3017 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3018 if (inst
->is_control_flow()) {
3019 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3022 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3023 inst
->dst
.file
== MRF
) {
3024 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3025 if (prev_inst
&& inst
->equals(prev_inst
)) {
3026 inst
->remove(block
);
3032 /* Clear out the last-write records for MRFs that were overwritten. */
3033 if (inst
->dst
.file
== MRF
) {
3034 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3037 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3038 /* Found a SEND instruction, which will include two or fewer
3039 * implied MRF writes. We could do better here.
3041 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3042 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3046 /* Clear out any MRF move records whose sources got overwritten. */
3047 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3048 if (last_mrf_move
[i
] &&
3049 regions_overlap(inst
->dst
, inst
->size_written
,
3050 last_mrf_move
[i
]->src
[0],
3051 last_mrf_move
[i
]->size_read(0))) {
3052 last_mrf_move
[i
] = NULL
;
3056 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3057 inst
->dst
.file
== MRF
&&
3058 inst
->src
[0].file
!= ARF
&&
3059 !inst
->is_partial_write()) {
3060 last_mrf_move
[inst
->dst
.nr
] = inst
;
3065 invalidate_live_intervals();
3071 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3073 /* Clear the flag for registers that actually got read (as expected). */
3074 for (int i
= 0; i
< inst
->sources
; i
++) {
3076 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3077 grf
= inst
->src
[i
].nr
;
3082 if (grf
>= first_grf
&&
3083 grf
< first_grf
+ grf_len
) {
3084 deps
[grf
- first_grf
] = false;
3085 if (inst
->exec_size
== 16)
3086 deps
[grf
- first_grf
+ 1] = false;
3092 * Implements this workaround for the original 965:
3094 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3095 * check for post destination dependencies on this instruction, software
3096 * must ensure that there is no destination hazard for the case of ‘write
3097 * followed by a posted write’ shown in the following example.
3100 * 2. send r3.xy <rest of send instruction>
3103 * Due to no post-destination dependency check on the ‘send’, the above
3104 * code sequence could have two instructions (1 and 2) in flight at the
3105 * same time that both consider ‘r3’ as the target of their final writes.
3108 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3111 int write_len
= regs_written(inst
);
3112 int first_write_grf
= inst
->dst
.nr
;
3113 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3114 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3116 memset(needs_dep
, false, sizeof(needs_dep
));
3117 memset(needs_dep
, true, write_len
);
3119 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3121 /* Walk backwards looking for writes to registers we're writing which
3122 * aren't read since being written. If we hit the start of the program,
3123 * we assume that there are no outstanding dependencies on entry to the
3126 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3127 /* If we hit control flow, assume that there *are* outstanding
3128 * dependencies, and force their cleanup before our instruction.
3130 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3131 for (int i
= 0; i
< write_len
; i
++) {
3133 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3134 first_write_grf
+ i
);
3139 /* We insert our reads as late as possible on the assumption that any
3140 * instruction but a MOV that might have left us an outstanding
3141 * dependency has more latency than a MOV.
3143 if (scan_inst
->dst
.file
== VGRF
) {
3144 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3145 int reg
= scan_inst
->dst
.nr
+ i
;
3147 if (reg
>= first_write_grf
&&
3148 reg
< first_write_grf
+ write_len
&&
3149 needs_dep
[reg
- first_write_grf
]) {
3150 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3151 needs_dep
[reg
- first_write_grf
] = false;
3152 if (scan_inst
->exec_size
== 16)
3153 needs_dep
[reg
- first_write_grf
+ 1] = false;
3158 /* Clear the flag for registers that actually got read (as expected). */
3159 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3161 /* Continue the loop only if we haven't resolved all the dependencies */
3163 for (i
= 0; i
< write_len
; i
++) {
3173 * Implements this workaround for the original 965:
3175 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3176 * used as a destination register until after it has been sourced by an
3177 * instruction with a different destination register.
3180 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3182 int write_len
= regs_written(inst
);
3183 int first_write_grf
= inst
->dst
.nr
;
3184 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3185 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3187 memset(needs_dep
, false, sizeof(needs_dep
));
3188 memset(needs_dep
, true, write_len
);
3189 /* Walk forwards looking for writes to registers we're writing which aren't
3190 * read before being written.
3192 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3193 /* If we hit control flow, force resolve all remaining dependencies. */
3194 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3195 for (int i
= 0; i
< write_len
; i
++) {
3197 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3198 first_write_grf
+ i
);
3203 /* Clear the flag for registers that actually got read (as expected). */
3204 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3206 /* We insert our reads as late as possible since they're reading the
3207 * result of a SEND, which has massive latency.
3209 if (scan_inst
->dst
.file
== VGRF
&&
3210 scan_inst
->dst
.nr
>= first_write_grf
&&
3211 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3212 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3213 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3215 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3218 /* Continue the loop only if we haven't resolved all the dependencies */
3220 for (i
= 0; i
< write_len
; i
++) {
3230 fs_visitor::insert_gen4_send_dependency_workarounds()
3232 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3235 bool progress
= false;
3237 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3238 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3239 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3240 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3246 invalidate_live_intervals();
3250 * Turns the generic expression-style uniform pull constant load instruction
3251 * into a hardware-specific series of instructions for loading a pull
3254 * The expression style allows the CSE pass before this to optimize out
3255 * repeated loads from the same offset, and gives the pre-register-allocation
3256 * scheduling full flexibility, while the conversion to native instructions
3257 * allows the post-register-allocation scheduler the best information
3260 * Note that execution masking for setting up pull constant loads is special:
3261 * the channels that need to be written are unrelated to the current execution
3262 * mask, since a later instruction will use one of the result channels as a
3263 * source operand for all 8 or 16 of its channels.
3266 fs_visitor::lower_uniform_pull_constant_loads()
3268 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3269 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3272 if (devinfo
->gen
>= 7) {
3273 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3274 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3276 ubld
.group(8, 0).MOV(payload
,
3277 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3278 ubld
.group(1, 0).MOV(component(payload
, 2),
3279 brw_imm_ud(inst
->src
[1].ud
/ 16));
3281 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3282 inst
->src
[1] = payload
;
3283 inst
->header_size
= 1;
3286 invalidate_live_intervals();
3288 /* Before register allocation, we didn't tell the scheduler about the
3289 * MRF we use. We know it's safe to use this MRF because nothing
3290 * else does except for register spill/unspill, which generates and
3291 * uses its MRF within a single IR instruction.
3293 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3300 fs_visitor::lower_load_payload()
3302 bool progress
= false;
3304 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3305 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3308 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3309 assert(inst
->saturate
== false);
3310 fs_reg dst
= inst
->dst
;
3312 /* Get rid of COMPR4. We'll add it back in if we need it */
3313 if (dst
.file
== MRF
)
3314 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3316 const fs_builder
ibld(this, block
, inst
);
3317 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3319 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3320 if (inst
->src
[i
].file
!= BAD_FILE
) {
3321 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3322 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3323 hbld
.MOV(mov_dst
, mov_src
);
3325 dst
= offset(dst
, hbld
, 1);
3328 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3329 inst
->exec_size
> 8) {
3330 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3331 * a straightforward copy. Instead, the result of the
3332 * LOAD_PAYLOAD is treated as interleaved and the first four
3333 * non-header sources are unpacked as:
3344 * This is used for gen <= 5 fb writes.
3346 assert(inst
->exec_size
== 16);
3347 assert(inst
->header_size
+ 4 <= inst
->sources
);
3348 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3349 if (inst
->src
[i
].file
!= BAD_FILE
) {
3350 if (devinfo
->has_compr4
) {
3351 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3352 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3353 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3355 /* Platform doesn't have COMPR4. We have to fake it */
3356 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3357 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3359 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3366 /* The loop above only ever incremented us through the first set
3367 * of 4 registers. However, thanks to the magic of COMPR4, we
3368 * actually wrote to the first 8 registers, so we need to take
3369 * that into account now.
3373 /* The COMPR4 code took care of the first 4 sources. We'll let
3374 * the regular path handle any remaining sources. Yes, we are
3375 * modifying the instruction but we're about to delete it so
3376 * this really doesn't hurt anything.
3378 inst
->header_size
+= 4;
3381 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3382 if (inst
->src
[i
].file
!= BAD_FILE
)
3383 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3384 dst
= offset(dst
, ibld
, 1);
3387 inst
->remove(block
);
3392 invalidate_live_intervals();
3398 fs_visitor::lower_integer_multiplication()
3400 bool progress
= false;
3402 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3403 const fs_builder
ibld(this, block
, inst
);
3405 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3406 if (inst
->dst
.is_accumulator() ||
3407 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3408 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3411 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3412 * operation directly, but CHV/BXT cannot.
3414 if (devinfo
->gen
>= 8 &&
3415 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
))
3418 if (inst
->src
[1].file
== IMM
&&
3419 inst
->src
[1].ud
< (1 << 16)) {
3420 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3421 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3424 * If multiplying by an immediate value that fits in 16-bits, do a
3425 * single MUL instruction with that value in the proper location.
3427 if (devinfo
->gen
< 7) {
3428 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3430 ibld
.MOV(imm
, inst
->src
[1]);
3431 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3433 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3434 ibld
.MUL(inst
->dst
, inst
->src
[0],
3435 ud
? brw_imm_uw(inst
->src
[1].ud
)
3436 : brw_imm_w(inst
->src
[1].d
));
3439 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3440 * do 32-bit integer multiplication in one instruction, but instead
3441 * must do a sequence (which actually calculates a 64-bit result):
3443 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3444 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3445 * mov(8) g2<1>D acc0<8,8,1>D
3447 * But on Gen > 6, the ability to use second accumulator register
3448 * (acc1) for non-float data types was removed, preventing a simple
3449 * implementation in SIMD16. A 16-channel result can be calculated by
3450 * executing the three instructions twice in SIMD8, once with quarter
3451 * control of 1Q for the first eight channels and again with 2Q for
3452 * the second eight channels.
3454 * Which accumulator register is implicitly accessed (by AccWrEnable
3455 * for instance) is determined by the quarter control. Unfortunately
3456 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3457 * implicit accumulator access by an instruction with 2Q will access
3458 * acc1 regardless of whether the data type is usable in acc1.
3460 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3461 * integer data types.
3463 * Since we only want the low 32-bits of the result, we can do two
3464 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3465 * adjust the high result and add them (like the mach is doing):
3467 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3468 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3469 * shl(8) g9<1>D g8<8,8,1>D 16D
3470 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3472 * We avoid the shl instruction by realizing that we only want to add
3473 * the low 16-bits of the "high" result to the high 16-bits of the
3474 * "low" result and using proper regioning on the add:
3476 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3477 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3478 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3480 * Since it does not use the (single) accumulator register, we can
3481 * schedule multi-component multiplications much better.
3484 fs_reg orig_dst
= inst
->dst
;
3485 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3486 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3489 fs_reg low
= inst
->dst
;
3490 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3493 if (devinfo
->gen
>= 7) {
3494 if (inst
->src
[1].file
== IMM
) {
3495 ibld
.MUL(low
, inst
->src
[0],
3496 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3497 ibld
.MUL(high
, inst
->src
[0],
3498 brw_imm_uw(inst
->src
[1].ud
>> 16));
3500 ibld
.MUL(low
, inst
->src
[0],
3501 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3502 ibld
.MUL(high
, inst
->src
[0],
3503 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3506 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3508 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3512 ibld
.ADD(subscript(inst
->dst
, BRW_REGISTER_TYPE_UW
, 1),
3513 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3514 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3516 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3517 set_condmod(inst
->conditional_mod
,
3518 ibld
.MOV(orig_dst
, inst
->dst
));
3522 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3523 /* Should have been lowered to 8-wide. */
3524 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
3525 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3527 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3528 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3530 if (devinfo
->gen
>= 8) {
3531 /* Until Gen8, integer multiplies read 32-bits from one source,
3532 * and 16-bits from the other, and relying on the MACH instruction
3533 * to generate the high bits of the result.
3535 * On Gen8, the multiply instruction does a full 32x32-bit
3536 * multiply, but in order to do a 64-bit multiply we can simulate
3537 * the previous behavior and then use a MACH instruction.
3539 * FINISHME: Don't use source modifiers on src1.
3541 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3542 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3543 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3544 mul
->src
[1].stride
*= 2;
3546 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3548 /* Among other things the quarter control bits influence which
3549 * accumulator register is used by the hardware for instructions
3550 * that access the accumulator implicitly (e.g. MACH). A
3551 * second-half instruction would normally map to acc1, which
3552 * doesn't exist on Gen7 and up (the hardware does emulate it for
3553 * floating-point instructions *only* by taking advantage of the
3554 * extra precision of acc0 not normally used for floating point
3557 * HSW and up are careful enough not to try to access an
3558 * accumulator register that doesn't exist, but on earlier Gen7
3559 * hardware we need to make sure that the quarter control bits are
3560 * zero to avoid non-deterministic behaviour and emit an extra MOV
3561 * to get the result masked correctly according to the current
3565 mach
->force_writemask_all
= true;
3566 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3567 ibld
.MOV(inst
->dst
, mach
->dst
);
3573 inst
->remove(block
);
3578 invalidate_live_intervals();
3584 fs_visitor::lower_minmax()
3586 assert(devinfo
->gen
< 6);
3588 bool progress
= false;
3590 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3591 const fs_builder
ibld(this, block
, inst
);
3593 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3594 inst
->predicate
== BRW_PREDICATE_NONE
) {
3595 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3596 * the original SEL.L/GE instruction
3598 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3599 inst
->conditional_mod
);
3600 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3601 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3608 invalidate_live_intervals();
3614 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3615 fs_reg
*dst
, fs_reg color
, unsigned components
)
3617 if (key
->clamp_fragment_color
) {
3618 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3619 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3621 for (unsigned i
= 0; i
< components
; i
++)
3623 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3628 for (unsigned i
= 0; i
< components
; i
++)
3629 dst
[i
] = offset(color
, bld
, i
);
3633 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3634 const struct brw_wm_prog_data
*prog_data
,
3635 const brw_wm_prog_key
*key
,
3636 const fs_visitor::thread_payload
&payload
)
3638 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3639 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3640 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3641 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3642 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3643 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3644 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3645 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3646 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3647 const unsigned components
=
3648 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3650 /* We can potentially have a message length of up to 15, so we have to set
3651 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3654 int header_size
= 2, payload_header_size
;
3655 unsigned length
= 0;
3657 /* From the Sandy Bridge PRM, volume 4, page 198:
3659 * "Dispatched Pixel Enables. One bit per pixel indicating
3660 * which pixels were originally enabled when the thread was
3661 * dispatched. This field is only required for the end-of-
3662 * thread message and on all dual-source messages."
3664 if (devinfo
->gen
>= 6 &&
3665 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3666 color1
.file
== BAD_FILE
&&
3667 key
->nr_color_regions
== 1) {
3671 if (header_size
!= 0) {
3672 assert(header_size
== 2);
3673 /* Allocate 2 registers for a header */
3677 if (payload
.aa_dest_stencil_reg
) {
3678 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3679 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3680 .MOV(sources
[length
],
3681 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3685 if (sample_mask
.file
!= BAD_FILE
) {
3686 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3687 BRW_REGISTER_TYPE_UD
);
3689 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3690 * relevant. Since it's unsigned single words one vgrf is always
3691 * 16-wide, but only the lower or higher 8 channels will be used by the
3692 * hardware when doing a SIMD8 write depending on whether we have
3693 * selected the subspans for the first or second half respectively.
3695 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3696 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3697 sample_mask
.stride
*= 2;
3699 bld
.exec_all().annotate("FB write oMask")
3700 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3706 payload_header_size
= length
;
3708 if (src0_alpha
.file
!= BAD_FILE
) {
3709 /* FIXME: This is being passed at the wrong location in the payload and
3710 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3711 * It's supposed to be immediately before oMask but there seems to be no
3712 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3713 * requires header sources to form a contiguous segment at the beginning
3714 * of the message and src0_alpha has per-channel semantics.
3716 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3718 } else if (key
->replicate_alpha
&& inst
->target
!= 0) {
3719 /* Handle the case when fragment shader doesn't write to draw buffer
3720 * zero. No need to call setup_color_payload() for src0_alpha because
3721 * alpha value will be undefined.
3726 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3729 if (color1
.file
!= BAD_FILE
) {
3730 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3734 if (src_depth
.file
!= BAD_FILE
) {
3735 sources
[length
] = src_depth
;
3739 if (dst_depth
.file
!= BAD_FILE
) {
3740 sources
[length
] = dst_depth
;
3744 if (src_stencil
.file
!= BAD_FILE
) {
3745 assert(devinfo
->gen
>= 9);
3746 assert(bld
.dispatch_width() != 16);
3748 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3749 * available on gen9+. As such it's impossible to have both enabled at the
3750 * same time and therefore length cannot overrun the array.
3752 assert(length
< 15);
3754 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3755 bld
.exec_all().annotate("FB write OS")
3756 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3757 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3762 if (devinfo
->gen
>= 7) {
3763 /* Send from the GRF */
3764 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3765 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3766 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
3767 load
->dst
= payload
;
3769 inst
->src
[0] = payload
;
3770 inst
->resize_sources(1);
3772 /* Send from the MRF */
3773 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3774 sources
, length
, payload_header_size
);
3776 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3777 * will do this for us if we just give it a COMPR4 destination.
3779 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3780 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3782 inst
->resize_sources(0);
3786 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3787 inst
->mlen
= regs_written(load
);
3788 inst
->header_size
= header_size
;
3792 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
3794 const fs_builder
&ubld
= bld
.exec_all();
3795 const unsigned length
= 2;
3796 const fs_reg header
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
, length
);
3799 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3801 inst
->resize_sources(1);
3802 inst
->src
[0] = header
;
3803 inst
->opcode
= FS_OPCODE_FB_READ
;
3804 inst
->mlen
= length
;
3805 inst
->header_size
= length
;
3809 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3810 const fs_reg
&coordinate
,
3811 const fs_reg
&shadow_c
,
3812 const fs_reg
&lod
, const fs_reg
&lod2
,
3813 const fs_reg
&surface
,
3814 const fs_reg
&sampler
,
3815 unsigned coord_components
,
3816 unsigned grad_components
)
3818 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3819 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3820 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3821 fs_reg msg_end
= msg_begin
;
3824 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3826 for (unsigned i
= 0; i
< coord_components
; i
++)
3827 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3828 offset(coordinate
, bld
, i
));
3830 msg_end
= offset(msg_end
, bld
, coord_components
);
3832 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3833 * require all three components to be present and zero if they are unused.
3835 if (coord_components
> 0 &&
3836 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3837 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3838 for (unsigned i
= coord_components
; i
< 3; i
++)
3839 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3841 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3844 if (op
== SHADER_OPCODE_TXD
) {
3845 /* TXD unsupported in SIMD16 mode. */
3846 assert(bld
.dispatch_width() == 8);
3848 /* the slots for u and v are always present, but r is optional */
3849 if (coord_components
< 2)
3850 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3853 * dPdx = dudx, dvdx, drdx
3854 * dPdy = dudy, dvdy, drdy
3856 * 1-arg: Does not exist.
3858 * 2-arg: dudx dvdx dudy dvdy
3859 * dPdx.x dPdx.y dPdy.x dPdy.y
3862 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3863 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3864 * m5 m6 m7 m8 m9 m10
3866 for (unsigned i
= 0; i
< grad_components
; i
++)
3867 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3869 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3871 for (unsigned i
= 0; i
< grad_components
; i
++)
3872 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3874 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3878 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
3879 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
3881 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3882 bld
.dispatch_width() == 16);
3884 const brw_reg_type type
=
3885 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3886 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3887 bld
.MOV(retype(msg_end
, type
), lod
);
3888 msg_end
= offset(msg_end
, bld
, 1);
3891 if (shadow_c
.file
!= BAD_FILE
) {
3892 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3893 /* There's no plain shadow compare message, so we use shadow
3894 * compare with a bias of 0.0.
3896 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3897 msg_end
= offset(msg_end
, bld
, 1);
3900 bld
.MOV(msg_end
, shadow_c
);
3901 msg_end
= offset(msg_end
, bld
, 1);
3905 inst
->src
[0] = reg_undef
;
3906 inst
->src
[1] = surface
;
3907 inst
->src
[2] = sampler
;
3908 inst
->resize_sources(3);
3909 inst
->base_mrf
= msg_begin
.nr
;
3910 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3911 inst
->header_size
= 1;
3915 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3916 const fs_reg
&coordinate
,
3917 const fs_reg
&shadow_c
,
3918 const fs_reg
&lod
, const fs_reg
&lod2
,
3919 const fs_reg
&sample_index
,
3920 const fs_reg
&surface
,
3921 const fs_reg
&sampler
,
3922 unsigned coord_components
,
3923 unsigned grad_components
)
3925 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3926 fs_reg msg_coords
= message
;
3927 unsigned header_size
= 0;
3929 if (inst
->offset
!= 0) {
3930 /* The offsets set up by the visitor are in the m1 header, so we can't
3937 for (unsigned i
= 0; i
< coord_components
; i
++)
3938 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
3939 offset(coordinate
, bld
, i
));
3941 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3942 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3944 if (shadow_c
.file
!= BAD_FILE
) {
3945 fs_reg msg_shadow
= msg_lod
;
3946 bld
.MOV(msg_shadow
, shadow_c
);
3947 msg_lod
= offset(msg_shadow
, bld
, 1);
3952 case SHADER_OPCODE_TXL
:
3954 bld
.MOV(msg_lod
, lod
);
3955 msg_end
= offset(msg_lod
, bld
, 1);
3957 case SHADER_OPCODE_TXD
:
3960 * dPdx = dudx, dvdx, drdx
3961 * dPdy = dudy, dvdy, drdy
3963 * Load up these values:
3964 * - dudx dudy dvdx dvdy drdx drdy
3965 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3968 for (unsigned i
= 0; i
< grad_components
; i
++) {
3969 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
3970 msg_end
= offset(msg_end
, bld
, 1);
3972 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
3973 msg_end
= offset(msg_end
, bld
, 1);
3976 case SHADER_OPCODE_TXS
:
3977 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3978 bld
.MOV(msg_lod
, lod
);
3979 msg_end
= offset(msg_lod
, bld
, 1);
3981 case SHADER_OPCODE_TXF
:
3982 msg_lod
= offset(msg_coords
, bld
, 3);
3983 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3984 msg_end
= offset(msg_lod
, bld
, 1);
3986 case SHADER_OPCODE_TXF_CMS
:
3987 msg_lod
= offset(msg_coords
, bld
, 3);
3989 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3991 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3992 msg_end
= offset(msg_lod
, bld
, 2);
3999 inst
->src
[0] = reg_undef
;
4000 inst
->src
[1] = surface
;
4001 inst
->src
[2] = sampler
;
4002 inst
->resize_sources(3);
4003 inst
->base_mrf
= message
.nr
;
4004 inst
->mlen
= msg_end
.nr
- message
.nr
;
4005 inst
->header_size
= header_size
;
4007 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4008 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4012 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4014 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4017 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4021 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4022 const fs_reg
&coordinate
,
4023 const fs_reg
&shadow_c
,
4024 fs_reg lod
, const fs_reg
&lod2
,
4025 const fs_reg
&sample_index
,
4027 const fs_reg
&surface
,
4028 const fs_reg
&sampler
,
4029 const fs_reg
&tg4_offset
,
4030 unsigned coord_components
,
4031 unsigned grad_components
)
4033 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4034 unsigned reg_width
= bld
.dispatch_width() / 8;
4035 unsigned header_size
= 0, length
= 0;
4036 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4037 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4038 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4040 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4041 inst
->offset
!= 0 || inst
->eot
||
4042 op
== SHADER_OPCODE_SAMPLEINFO
||
4043 is_high_sampler(devinfo
, sampler
)) {
4044 /* For general texture offsets (no txf workaround), we need a header to
4045 * put them in. Note that we're only reserving space for it in the
4046 * message payload as it will be initialized implicitly by the
4049 * TG4 needs to place its channel select in the header, for interaction
4050 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4051 * larger sampler numbers we need to offset the Sampler State Pointer in
4055 sources
[0] = fs_reg();
4058 /* If we're requesting fewer than four channels worth of response,
4059 * and we have an explicit header, we need to set up the sampler
4060 * writemask. It's reversed from normal: 1 means "don't write".
4062 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4063 assert(regs_written(inst
) % reg_width
== 0);
4064 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4065 inst
->offset
|= mask
<< 12;
4069 if (shadow_c
.file
!= BAD_FILE
) {
4070 bld
.MOV(sources
[length
], shadow_c
);
4074 bool coordinate_done
= false;
4076 /* Set up the LOD info */
4079 case SHADER_OPCODE_TXL
:
4080 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4081 op
= SHADER_OPCODE_TXL_LZ
;
4084 bld
.MOV(sources
[length
], lod
);
4087 case SHADER_OPCODE_TXD
:
4088 /* TXD should have been lowered in SIMD16 mode. */
4089 assert(bld
.dispatch_width() == 8);
4091 /* Load dPdx and the coordinate together:
4092 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4094 for (unsigned i
= 0; i
< coord_components
; i
++) {
4095 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4097 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4098 * only derivatives for (u, v, r).
4100 if (i
< grad_components
) {
4101 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4102 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4106 coordinate_done
= true;
4108 case SHADER_OPCODE_TXS
:
4109 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4112 case SHADER_OPCODE_TXF
:
4113 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4114 * On Gen9 they are u, v, lod, r
4116 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4118 if (devinfo
->gen
>= 9) {
4119 if (coord_components
>= 2) {
4120 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4121 offset(coordinate
, bld
, 1));
4123 sources
[length
] = brw_imm_d(0);
4128 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4129 op
= SHADER_OPCODE_TXF_LZ
;
4131 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4135 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4136 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4137 offset(coordinate
, bld
, i
));
4139 coordinate_done
= true;
4142 case SHADER_OPCODE_TXF_CMS
:
4143 case SHADER_OPCODE_TXF_CMS_W
:
4144 case SHADER_OPCODE_TXF_UMS
:
4145 case SHADER_OPCODE_TXF_MCS
:
4146 if (op
== SHADER_OPCODE_TXF_UMS
||
4147 op
== SHADER_OPCODE_TXF_CMS
||
4148 op
== SHADER_OPCODE_TXF_CMS_W
) {
4149 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4153 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4154 /* Data from the multisample control surface. */
4155 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4158 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4161 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4162 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4165 offset(mcs
, bld
, 1));
4170 /* There is no offsetting for this message; just copy in the integer
4171 * texture coordinates.
4173 for (unsigned i
= 0; i
< coord_components
; i
++)
4174 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4175 offset(coordinate
, bld
, i
));
4177 coordinate_done
= true;
4179 case SHADER_OPCODE_TG4_OFFSET
:
4180 /* More crazy intermixing */
4181 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4182 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4184 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4185 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4186 offset(tg4_offset
, bld
, i
));
4188 if (coord_components
== 3) /* r if present */
4189 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4191 coordinate_done
= true;
4197 /* Set up the coordinate (except for cases where it was done above) */
4198 if (!coordinate_done
) {
4199 for (unsigned i
= 0; i
< coord_components
; i
++)
4200 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4205 mlen
= length
* reg_width
- header_size
;
4207 mlen
= length
* reg_width
;
4209 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4210 BRW_REGISTER_TYPE_F
);
4211 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4213 /* Generate the SEND. */
4215 inst
->src
[0] = src_payload
;
4216 inst
->src
[1] = surface
;
4217 inst
->src
[2] = sampler
;
4218 inst
->resize_sources(3);
4220 inst
->header_size
= header_size
;
4222 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4223 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4227 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4229 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4230 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4231 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4232 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4233 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4234 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4235 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4236 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4237 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4238 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
4239 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4240 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4241 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4242 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4244 if (devinfo
->gen
>= 7) {
4245 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4246 shadow_c
, lod
, lod2
, sample_index
,
4247 mcs
, surface
, sampler
, tg4_offset
,
4248 coord_components
, grad_components
);
4249 } else if (devinfo
->gen
>= 5) {
4250 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4251 shadow_c
, lod
, lod2
, sample_index
,
4253 coord_components
, grad_components
);
4255 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4256 shadow_c
, lod
, lod2
,
4258 coord_components
, grad_components
);
4263 * Initialize the header present in some typed and untyped surface
4267 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4269 fs_builder ubld
= bld
.exec_all().group(8, 0);
4270 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4271 ubld
.MOV(dst
, brw_imm_d(0));
4272 ubld
.MOV(component(dst
, 7), sample_mask
);
4277 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4278 const fs_reg
&sample_mask
)
4280 /* Get the logical send arguments. */
4281 const fs_reg
&addr
= inst
->src
[0];
4282 const fs_reg
&src
= inst
->src
[1];
4283 const fs_reg
&surface
= inst
->src
[2];
4284 const UNUSED fs_reg
&dims
= inst
->src
[3];
4285 const fs_reg
&arg
= inst
->src
[4];
4287 /* Calculate the total number of components of the payload. */
4288 const unsigned addr_sz
= inst
->components_read(0);
4289 const unsigned src_sz
= inst
->components_read(1);
4290 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4291 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4293 /* Allocate space for the payload. */
4294 fs_reg
*const components
= new fs_reg
[sz
];
4295 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4298 /* Construct the payload. */
4300 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4302 for (unsigned i
= 0; i
< addr_sz
; i
++)
4303 components
[n
++] = offset(addr
, bld
, i
);
4305 for (unsigned i
= 0; i
< src_sz
; i
++)
4306 components
[n
++] = offset(src
, bld
, i
);
4308 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4310 /* Update the original instruction. */
4312 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4313 inst
->header_size
= header_sz
;
4315 inst
->src
[0] = payload
;
4316 inst
->src
[1] = surface
;
4318 inst
->resize_sources(3);
4320 delete[] components
;
4324 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4326 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4328 if (devinfo
->gen
>= 7) {
4329 /* We are switching the instruction from an ALU-like instruction to a
4330 * send-from-grf instruction. Since sends can't handle strides or
4331 * source modifiers, we have to make a copy of the offset source.
4333 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4334 bld
.MOV(tmp
, inst
->src
[1]);
4337 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4340 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4341 BRW_REGISTER_TYPE_UD
);
4343 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4345 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4346 inst
->resize_sources(1);
4347 inst
->base_mrf
= payload
.nr
;
4348 inst
->header_size
= 1;
4349 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4354 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4356 assert(bld
.shader
->devinfo
->gen
< 6);
4359 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4361 if (inst
->sources
> 1) {
4362 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4363 * "Message Payload":
4365 * "Operand0[7]. For the INT DIV functions, this operand is the
4368 * "Operand1[7]. For the INT DIV functions, this operand is the
4371 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4372 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4373 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4375 inst
->resize_sources(1);
4376 inst
->src
[0] = src0
;
4378 assert(inst
->exec_size
== 8);
4379 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4384 fs_visitor::lower_logical_sends()
4386 bool progress
= false;
4388 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4389 const fs_builder
ibld(this, block
, inst
);
4391 switch (inst
->opcode
) {
4392 case FS_OPCODE_FB_WRITE_LOGICAL
:
4393 assert(stage
== MESA_SHADER_FRAGMENT
);
4394 lower_fb_write_logical_send(ibld
, inst
,
4395 brw_wm_prog_data(prog_data
),
4396 (const brw_wm_prog_key
*)key
,
4400 case FS_OPCODE_FB_READ_LOGICAL
:
4401 lower_fb_read_logical_send(ibld
, inst
);
4404 case SHADER_OPCODE_TEX_LOGICAL
:
4405 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4408 case SHADER_OPCODE_TXD_LOGICAL
:
4409 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4412 case SHADER_OPCODE_TXF_LOGICAL
:
4413 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4416 case SHADER_OPCODE_TXL_LOGICAL
:
4417 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4420 case SHADER_OPCODE_TXS_LOGICAL
:
4421 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4424 case FS_OPCODE_TXB_LOGICAL
:
4425 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4428 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4429 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4432 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4433 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4436 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4437 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4440 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4441 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4444 case SHADER_OPCODE_LOD_LOGICAL
:
4445 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4448 case SHADER_OPCODE_TG4_LOGICAL
:
4449 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4452 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4453 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4456 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4457 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4460 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4461 lower_surface_logical_send(ibld
, inst
,
4462 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4466 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4467 lower_surface_logical_send(ibld
, inst
,
4468 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4469 ibld
.sample_mask_reg());
4472 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4473 lower_surface_logical_send(ibld
, inst
,
4474 SHADER_OPCODE_UNTYPED_ATOMIC
,
4475 ibld
.sample_mask_reg());
4478 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4479 lower_surface_logical_send(ibld
, inst
,
4480 SHADER_OPCODE_TYPED_SURFACE_READ
,
4484 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4485 lower_surface_logical_send(ibld
, inst
,
4486 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4487 ibld
.sample_mask_reg());
4490 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4491 lower_surface_logical_send(ibld
, inst
,
4492 SHADER_OPCODE_TYPED_ATOMIC
,
4493 ibld
.sample_mask_reg());
4496 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4497 lower_varying_pull_constant_logical_send(ibld
, inst
);
4500 case SHADER_OPCODE_RCP
:
4501 case SHADER_OPCODE_RSQ
:
4502 case SHADER_OPCODE_SQRT
:
4503 case SHADER_OPCODE_EXP2
:
4504 case SHADER_OPCODE_LOG2
:
4505 case SHADER_OPCODE_SIN
:
4506 case SHADER_OPCODE_COS
:
4507 case SHADER_OPCODE_POW
:
4508 case SHADER_OPCODE_INT_QUOTIENT
:
4509 case SHADER_OPCODE_INT_REMAINDER
:
4510 /* The math opcodes are overloaded for the send-like and
4511 * expression-like instructions which seems kind of icky. Gen6+ has
4512 * a native (but rather quirky) MATH instruction so we don't need to
4513 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4514 * logical instructions (which we can easily recognize because they
4515 * have mlen = 0) into send-like virtual instructions.
4517 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4518 lower_math_logical_send(ibld
, inst
);
4533 invalidate_live_intervals();
4539 * Get the closest allowed SIMD width for instruction \p inst accounting for
4540 * some common regioning and execution control restrictions that apply to FPU
4541 * instructions. These restrictions don't necessarily have any relevance to
4542 * instructions not executed by the FPU pipeline like extended math, control
4543 * flow or send message instructions.
4545 * For virtual opcodes it's really up to the instruction -- In some cases
4546 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4547 * instructions) it may simplify virtual instruction lowering if we can
4548 * enforce FPU-like regioning restrictions already on the virtual instruction,
4549 * in other cases (e.g. virtual send-like instructions) this may be
4550 * excessively restrictive.
4553 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
4554 const fs_inst
*inst
)
4556 /* Maximum execution size representable in the instruction controls. */
4557 unsigned max_width
= MIN2(32, inst
->exec_size
);
4559 /* According to the PRMs:
4560 * "A. In Direct Addressing mode, a source cannot span more than 2
4561 * adjacent GRF registers.
4562 * B. A destination cannot span more than 2 adjacent GRF registers."
4564 * Look for the source or destination with the largest register region
4565 * which is the one that is going to limit the overall execution size of
4566 * the instruction due to this rule.
4568 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4570 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4571 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
4573 /* Calculate the maximum execution size of the instruction based on the
4574 * factor by which it goes over the hardware limit of 2 GRFs.
4577 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4579 /* According to the IVB PRMs:
4580 * "When destination spans two registers, the source MUST span two
4581 * registers. The exception to the above rule:
4583 * - When source is scalar, the source registers are not incremented.
4584 * - When source is packed integer Word and destination is packed
4585 * integer DWord, the source register is not incremented but the
4586 * source sub register is incremented."
4588 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4589 * restrictions. The code below intentionally doesn't check whether the
4590 * destination type is integer because empirically the hardware doesn't
4591 * seem to care what the actual type is as long as it's dword-aligned.
4593 if (devinfo
->gen
< 8) {
4594 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4595 /* IVB implements DF scalars as <0;2,1> regions. */
4596 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
4597 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
4598 const bool is_packed_word_exception
=
4599 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4600 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
4602 if (inst
->size_written
> REG_SIZE
&&
4603 inst
->size_read(i
) != 0 && inst
->size_read(i
) <= REG_SIZE
&&
4604 !is_scalar_exception
&& !is_packed_word_exception
) {
4605 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4606 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4611 /* From the IVB PRMs:
4612 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4613 * are applied for both halves of the SIMD32 instruction. If different
4614 * execution mask channels are required, split the instruction into two
4615 * SIMD16 instructions."
4617 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4618 * 32-wide control flow support in hardware and will behave similarly.
4620 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4621 max_width
= MIN2(max_width
, 16);
4623 /* From the IVB PRMs (applies to HSW too):
4624 * "Instructions with condition modifiers must not use SIMD32."
4626 * From the BDW PRMs (applies to later hardware too):
4627 * "Ternary instruction with condition modifiers must not use SIMD32."
4629 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4630 max_width
= MIN2(max_width
, 16);
4632 /* From the IVB PRMs (applies to other devices that don't have the
4633 * gen_device_info::supports_simd16_3src flag set):
4634 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4635 * SIMD8 is not allowed for DF operations."
4637 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4638 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4640 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4641 * the 8-bit quarter of the execution mask signals specified in the
4642 * instruction control fields) for the second compressed half of any
4643 * single-precision instruction (for double-precision instructions
4644 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4645 * the EU will apply the wrong execution controls for the second
4646 * sequential GRF write if the number of channels per GRF is not exactly
4647 * eight in single-precision mode (or four in double-float mode).
4649 * In this situation we calculate the maximum size of the split
4650 * instructions so they only ever write to a single register.
4652 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
4653 !inst
->force_writemask_all
) {
4654 const unsigned channels_per_grf
= inst
->exec_size
/
4655 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
4656 const unsigned exec_type_size
= get_exec_type_size(inst
);
4657 assert(exec_type_size
);
4659 /* The hardware shifts exactly 8 channels per compressed half of the
4660 * instruction in single-precision mode and exactly 4 in double-precision.
4662 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4663 max_width
= MIN2(max_width
, channels_per_grf
);
4665 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
4666 * because HW applies the same channel enable signals to both halves of
4667 * the compressed instruction which will be just wrong under
4668 * non-uniform control flow.
4670 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4671 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
4672 max_width
= MIN2(max_width
, 4);
4675 /* Only power-of-two execution sizes are representable in the instruction
4678 return 1 << _mesa_logbase2(max_width
);
4682 * Get the maximum allowed SIMD width for instruction \p inst accounting for
4683 * various payload size restrictions that apply to sampler message
4686 * This is only intended to provide a maximum theoretical bound for the
4687 * execution size of the message based on the number of argument components
4688 * alone, which in most cases will determine whether the SIMD8 or SIMD16
4689 * variant of the message can be used, though some messages may have
4690 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
4691 * the message length to determine the exact SIMD width and argument count,
4692 * which makes a number of sampler message combinations impossible to
4696 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
4697 const fs_inst
*inst
)
4699 /* Calculate the number of coordinate components that have to be present
4700 * assuming that additional arguments follow the texel coordinates in the
4701 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
4702 * need to pad to four or three components depending on the message,
4703 * pre-ILK we need to pad to at most three components.
4705 const unsigned req_coord_components
=
4706 (devinfo
->gen
>= 7 ||
4707 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
4708 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
4709 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
4712 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
4713 * variant of the TXL or TXF message.
4715 const bool implicit_lod
= devinfo
->gen
>= 9 &&
4716 (inst
->opcode
== SHADER_OPCODE_TXL
||
4717 inst
->opcode
== SHADER_OPCODE_TXF
) &&
4718 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
4720 /* Calculate the total number of argument components that need to be passed
4721 * to the sampler unit.
4723 const unsigned num_payload_components
=
4724 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
4725 req_coord_components
) +
4726 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
4727 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
4728 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
4729 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
4730 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
4731 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
4732 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
4734 /* SIMD16 messages with more than five arguments exceed the maximum message
4735 * size supported by the sampler, regardless of whether a header is
4738 return MIN2(inst
->exec_size
,
4739 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
4743 * Get the closest native SIMD width supported by the hardware for instruction
4744 * \p inst. The instruction will be left untouched by
4745 * fs_visitor::lower_simd_width() if the returned value is equal to the
4746 * original execution size.
4749 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
4750 const fs_inst
*inst
)
4752 switch (inst
->opcode
) {
4753 case BRW_OPCODE_MOV
:
4754 case BRW_OPCODE_SEL
:
4755 case BRW_OPCODE_NOT
:
4756 case BRW_OPCODE_AND
:
4758 case BRW_OPCODE_XOR
:
4759 case BRW_OPCODE_SHR
:
4760 case BRW_OPCODE_SHL
:
4761 case BRW_OPCODE_ASR
:
4762 case BRW_OPCODE_CMPN
:
4763 case BRW_OPCODE_CSEL
:
4764 case BRW_OPCODE_F32TO16
:
4765 case BRW_OPCODE_F16TO32
:
4766 case BRW_OPCODE_BFREV
:
4767 case BRW_OPCODE_BFE
:
4768 case BRW_OPCODE_ADD
:
4769 case BRW_OPCODE_MUL
:
4770 case BRW_OPCODE_AVG
:
4771 case BRW_OPCODE_FRC
:
4772 case BRW_OPCODE_RNDU
:
4773 case BRW_OPCODE_RNDD
:
4774 case BRW_OPCODE_RNDE
:
4775 case BRW_OPCODE_RNDZ
:
4776 case BRW_OPCODE_LZD
:
4777 case BRW_OPCODE_FBH
:
4778 case BRW_OPCODE_FBL
:
4779 case BRW_OPCODE_CBIT
:
4780 case BRW_OPCODE_SAD2
:
4781 case BRW_OPCODE_MAD
:
4782 case BRW_OPCODE_LRP
:
4783 case FS_OPCODE_PACK
:
4784 return get_fpu_lowered_simd_width(devinfo
, inst
);
4786 case BRW_OPCODE_CMP
: {
4787 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4788 * when the destination is a GRF the dependency-clear bit on the flag
4789 * register is cleared early.
4791 * Suggested workarounds are to disable coissuing CMP instructions
4792 * or to split CMP(16) instructions into two CMP(8) instructions.
4794 * We choose to split into CMP(8) instructions since disabling
4795 * coissuing would affect CMP instructions not otherwise affected by
4798 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4799 !inst
->dst
.is_null() ? 8 : ~0);
4800 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4802 case BRW_OPCODE_BFI1
:
4803 case BRW_OPCODE_BFI2
:
4804 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4806 * "Force BFI instructions to be executed always in SIMD8."
4808 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4809 get_fpu_lowered_simd_width(devinfo
, inst
));
4812 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4813 return inst
->exec_size
;
4815 case SHADER_OPCODE_RCP
:
4816 case SHADER_OPCODE_RSQ
:
4817 case SHADER_OPCODE_SQRT
:
4818 case SHADER_OPCODE_EXP2
:
4819 case SHADER_OPCODE_LOG2
:
4820 case SHADER_OPCODE_SIN
:
4821 case SHADER_OPCODE_COS
:
4822 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4825 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4826 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4827 MIN2(8, inst
->exec_size
));
4829 case SHADER_OPCODE_POW
:
4830 /* SIMD16 is only allowed on Gen7+. */
4831 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4832 MIN2(8, inst
->exec_size
));
4834 case SHADER_OPCODE_INT_QUOTIENT
:
4835 case SHADER_OPCODE_INT_REMAINDER
:
4836 /* Integer division is limited to SIMD8 on all generations. */
4837 return MIN2(8, inst
->exec_size
);
4839 case FS_OPCODE_LINTERP
:
4840 case FS_OPCODE_GET_BUFFER_SIZE
:
4841 case FS_OPCODE_DDX_COARSE
:
4842 case FS_OPCODE_DDX_FINE
:
4843 case FS_OPCODE_DDY_COARSE
:
4844 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4845 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4846 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4847 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4848 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4849 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4850 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4851 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4852 return MIN2(16, inst
->exec_size
);
4854 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4855 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4856 * message used to implement varying pull constant loads, so expand it
4857 * to SIMD16. An alternative with longer message payload length but
4858 * shorter return payload would be to use the SIMD8 sampler message that
4859 * takes (header, u, v, r) as parameters instead of (header, u).
4861 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4863 case FS_OPCODE_DDY_FINE
:
4864 /* The implementation of this virtual opcode may require emitting
4865 * compressed Align16 instructions, which are severely limited on some
4868 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4869 * Region Restrictions):
4871 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4872 * and SIMD8 is not allowed for DF operations."
4874 * In this context, "DW operations" means "operations acting on 32-bit
4875 * values", so it includes operations on floats.
4877 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4878 * (Instruction Compression -> Rules and Restrictions):
4880 * "A compressed instruction must be in Align1 access mode. Align16
4881 * mode instructions cannot be compressed."
4883 * Similar text exists in the g45 PRM.
4885 * Empirically, compressed align16 instructions using odd register
4886 * numbers don't appear to work on Sandybridge either.
4888 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4889 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4890 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4892 case SHADER_OPCODE_MULH
:
4893 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4894 * is 8-wide on Gen7+.
4896 return (devinfo
->gen
>= 7 ? 8 :
4897 get_fpu_lowered_simd_width(devinfo
, inst
));
4899 case FS_OPCODE_FB_WRITE_LOGICAL
:
4900 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4903 assert(devinfo
->gen
!= 6 ||
4904 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4905 inst
->exec_size
== 8);
4906 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4907 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4908 8 : MIN2(16, inst
->exec_size
));
4910 case FS_OPCODE_FB_READ_LOGICAL
:
4911 return MIN2(16, inst
->exec_size
);
4913 case SHADER_OPCODE_TEX_LOGICAL
:
4914 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4915 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4916 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4917 case SHADER_OPCODE_LOD_LOGICAL
:
4918 case SHADER_OPCODE_TG4_LOGICAL
:
4919 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4920 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4921 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4922 return get_sampler_lowered_simd_width(devinfo
, inst
);
4924 case SHADER_OPCODE_TXD_LOGICAL
:
4925 /* TXD is unsupported in SIMD16 mode. */
4928 case SHADER_OPCODE_TXL_LOGICAL
:
4929 case FS_OPCODE_TXB_LOGICAL
:
4930 /* Only one execution size is representable pre-ILK depending on whether
4931 * the shadow reference argument is present.
4933 if (devinfo
->gen
== 4)
4934 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
4936 return get_sampler_lowered_simd_width(devinfo
, inst
);
4938 case SHADER_OPCODE_TXF_LOGICAL
:
4939 case SHADER_OPCODE_TXS_LOGICAL
:
4940 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4941 * messages. Use SIMD16 instead.
4943 if (devinfo
->gen
== 4)
4946 return get_sampler_lowered_simd_width(devinfo
, inst
);
4948 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4949 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4950 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4953 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4954 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4955 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4956 return MIN2(16, inst
->exec_size
);
4958 case SHADER_OPCODE_URB_READ_SIMD8
:
4959 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
4960 case SHADER_OPCODE_URB_WRITE_SIMD8
:
4961 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
4962 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
4963 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
4964 return MIN2(8, inst
->exec_size
);
4966 case SHADER_OPCODE_MOV_INDIRECT
: {
4967 /* From IVB and HSW PRMs:
4969 * "2.When the destination requires two registers and the sources are
4970 * indirect, the sources must use 1x1 regioning mode.
4972 * In case of DF instructions in HSW/IVB, the exec_size is limited by
4973 * the EU decompression logic not handling VxH indirect addressing
4976 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
4977 /* Prior to Broadwell, we only have 8 address subregisters. */
4978 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
4979 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
4983 case SHADER_OPCODE_LOAD_PAYLOAD
: {
4984 const unsigned reg_count
=
4985 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
4987 if (reg_count
> 2) {
4988 /* Only LOAD_PAYLOAD instructions with per-channel destination region
4989 * can be easily lowered (which excludes headers and heterogeneous
4992 assert(!inst
->header_size
);
4993 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4994 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
4995 inst
->src
[i
].file
== BAD_FILE
);
4997 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4999 return inst
->exec_size
;
5003 return inst
->exec_size
;
5008 * Return true if splitting out the group of channels of instruction \p inst
5009 * given by lbld.group() requires allocating a temporary for the i-th source
5010 * of the lowered instruction.
5013 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5015 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5016 (inst
->components_read(i
) == 1 &&
5017 lbld
.dispatch_width() <= inst
->exec_size
));
5021 * Extract the data that would be consumed by the channel group given by
5022 * lbld.group() from the i-th source region of instruction \p inst and return
5023 * it as result in packed form. If any copy instructions are required they
5024 * will be emitted before the given \p inst in \p block.
5027 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
5030 /* Specified channel group from the source region. */
5031 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5033 if (needs_src_copy(lbld
, inst
, i
)) {
5034 /* Builder of the right width to perform the copy avoiding uninitialized
5035 * data if the lowered execution size is greater than the original
5036 * execution size of the instruction.
5038 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5039 inst
->exec_size
), 0);
5040 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5042 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5043 cbld
.at(block
, inst
)
5044 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5048 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5049 /* The source is invariant for all dispatch_width-wide groups of the
5052 return inst
->src
[i
];
5055 /* We can just point the lowered instruction at the right channel group
5056 * from the original region.
5063 * Return true if splitting out the group of channels of instruction \p inst
5064 * given by lbld.group() requires allocating a temporary for the destination
5065 * of the lowered instruction and copying the data back to the original
5066 * destination region.
5069 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5071 /* If the instruction writes more than one component we'll have to shuffle
5072 * the results of multiple lowered instructions in order to make sure that
5073 * they end up arranged correctly in the original destination region.
5075 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
5078 /* If the lowered execution size is larger than the original the result of
5079 * the instruction won't fit in the original destination, so we'll have to
5080 * allocate a temporary in any case.
5082 if (lbld
.dispatch_width() > inst
->exec_size
)
5085 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5086 /* If we already made a copy of the source for other reasons there won't
5087 * be any overlap with the destination.
5089 if (needs_src_copy(lbld
, inst
, i
))
5092 /* In order to keep the logic simple we emit a copy whenever the
5093 * destination region doesn't exactly match an overlapping source, which
5094 * may point at the source and destination not being aligned group by
5095 * group which could cause one of the lowered instructions to overwrite
5096 * the data read from the same source by other lowered instructions.
5098 if (regions_overlap(inst
->dst
, inst
->size_written
,
5099 inst
->src
[i
], inst
->size_read(i
)) &&
5100 !inst
->dst
.equals(inst
->src
[i
]))
5108 * Insert data from a packed temporary into the channel group given by
5109 * lbld.group() of the destination region of instruction \p inst and return
5110 * the temporary as result. If any copy instructions are required they will
5111 * be emitted around the given \p inst in \p block.
5114 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5116 /* Builder of the right width to perform the copy avoiding uninitialized
5117 * data if the lowered execution size is greater than the original
5118 * execution size of the instruction.
5120 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5121 inst
->exec_size
), 0);
5123 /* Specified channel group from the destination region. */
5124 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5125 const unsigned dst_size
= inst
->size_written
/
5126 inst
->dst
.component_size(inst
->exec_size
);
5128 if (needs_dst_copy(lbld
, inst
)) {
5129 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5131 if (inst
->predicate
) {
5132 /* Handle predication by copying the original contents of
5133 * the destination into the temporary before emitting the
5134 * lowered instruction.
5136 for (unsigned k
= 0; k
< dst_size
; ++k
)
5137 cbld
.at(block
, inst
)
5138 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5141 for (unsigned k
= 0; k
< dst_size
; ++k
)
5142 cbld
.at(block
, inst
->next
)
5143 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5148 /* No need to allocate a temporary for the lowered instruction, just
5149 * take the right group of channels from the original region.
5156 fs_visitor::lower_simd_width()
5158 bool progress
= false;
5160 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5161 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5163 if (lower_width
!= inst
->exec_size
) {
5164 /* Builder matching the original instruction. We may also need to
5165 * emit an instruction of width larger than the original, set the
5166 * execution size of the builder to the highest of both for now so
5167 * we're sure that both cases can be handled.
5169 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5170 const fs_builder ibld
= bld
.at(block
, inst
)
5171 .exec_all(inst
->force_writemask_all
)
5172 .group(max_width
, inst
->group
/ max_width
);
5174 /* Split the copies in chunks of the execution width of either the
5175 * original or the lowered instruction, whichever is lower.
5177 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5178 const unsigned dst_size
= inst
->size_written
/
5179 inst
->dst
.component_size(inst
->exec_size
);
5181 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5183 for (unsigned i
= 0; i
< n
; i
++) {
5184 /* Emit a copy of the original instruction with the lowered width.
5185 * If the EOT flag was set throw it away except for the last
5186 * instruction to avoid killing the thread prematurely.
5188 fs_inst split_inst
= *inst
;
5189 split_inst
.exec_size
= lower_width
;
5190 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5192 /* Select the correct channel enables for the i-th group, then
5193 * transform the sources and destination and emit the lowered
5196 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5198 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5199 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5201 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5202 split_inst
.size_written
=
5203 split_inst
.dst
.component_size(lower_width
) * dst_size
;
5205 lbld
.emit(split_inst
);
5208 inst
->remove(block
);
5214 invalidate_live_intervals();
5220 fs_visitor::dump_instructions()
5222 dump_instructions(NULL
);
5226 fs_visitor::dump_instructions(const char *name
)
5228 FILE *file
= stderr
;
5229 if (name
&& geteuid() != 0) {
5230 file
= fopen(name
, "w");
5236 calculate_register_pressure();
5237 int ip
= 0, max_pressure
= 0;
5238 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5239 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5240 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5241 dump_instruction(inst
, file
);
5244 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5247 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5248 fprintf(file
, "%4d: ", ip
++);
5249 dump_instruction(inst
, file
);
5253 if (file
!= stderr
) {
5259 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5261 dump_instruction(be_inst
, stderr
);
5265 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5267 fs_inst
*inst
= (fs_inst
*)be_inst
;
5269 if (inst
->predicate
) {
5270 fprintf(file
, "(%cf0.%d) ",
5271 inst
->predicate_inverse
? '-' : '+',
5275 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5277 fprintf(file
, ".sat");
5278 if (inst
->conditional_mod
) {
5279 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5280 if (!inst
->predicate
&&
5281 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5282 inst
->opcode
!= BRW_OPCODE_IF
&&
5283 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5284 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5287 fprintf(file
, "(%d) ", inst
->exec_size
);
5290 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5294 fprintf(file
, "(EOT) ");
5297 switch (inst
->dst
.file
) {
5299 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5302 fprintf(file
, "g%d", inst
->dst
.nr
);
5305 fprintf(file
, "m%d", inst
->dst
.nr
);
5308 fprintf(file
, "(null)");
5311 fprintf(file
, "***u%d***", inst
->dst
.nr
);
5314 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
5317 switch (inst
->dst
.nr
) {
5319 fprintf(file
, "null");
5321 case BRW_ARF_ADDRESS
:
5322 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5324 case BRW_ARF_ACCUMULATOR
:
5325 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5328 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5331 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5336 unreachable("not reached");
5339 if (inst
->dst
.offset
||
5340 (inst
->dst
.file
== VGRF
&&
5341 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
5342 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
5343 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
5344 inst
->dst
.offset
% reg_size
);
5347 if (inst
->dst
.stride
!= 1)
5348 fprintf(file
, "<%u>", inst
->dst
.stride
);
5349 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
5351 for (int i
= 0; i
< inst
->sources
; i
++) {
5352 if (inst
->src
[i
].negate
)
5354 if (inst
->src
[i
].abs
)
5356 switch (inst
->src
[i
].file
) {
5358 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5361 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5364 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5367 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
5370 fprintf(file
, "u%d", inst
->src
[i
].nr
);
5373 fprintf(file
, "(null)");
5376 switch (inst
->src
[i
].type
) {
5377 case BRW_REGISTER_TYPE_F
:
5378 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5380 case BRW_REGISTER_TYPE_DF
:
5381 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5383 case BRW_REGISTER_TYPE_W
:
5384 case BRW_REGISTER_TYPE_D
:
5385 fprintf(file
, "%dd", inst
->src
[i
].d
);
5387 case BRW_REGISTER_TYPE_UW
:
5388 case BRW_REGISTER_TYPE_UD
:
5389 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5391 case BRW_REGISTER_TYPE_VF
:
5392 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5393 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5394 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5395 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5396 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5399 fprintf(file
, "???");
5404 switch (inst
->src
[i
].nr
) {
5406 fprintf(file
, "null");
5408 case BRW_ARF_ADDRESS
:
5409 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5411 case BRW_ARF_ACCUMULATOR
:
5412 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5415 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5418 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5424 if (inst
->src
[i
].offset
||
5425 (inst
->src
[i
].file
== VGRF
&&
5426 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
5427 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
5428 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
5429 inst
->src
[i
].offset
% reg_size
);
5432 if (inst
->src
[i
].abs
)
5435 if (inst
->src
[i
].file
!= IMM
) {
5437 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5438 unsigned hstride
= inst
->src
[i
].hstride
;
5439 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5441 stride
= inst
->src
[i
].stride
;
5444 fprintf(file
, "<%u>", stride
);
5446 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
5449 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5450 fprintf(file
, ", ");
5455 if (inst
->force_writemask_all
)
5456 fprintf(file
, "NoMask ");
5458 if (inst
->exec_size
!= dispatch_width
)
5459 fprintf(file
, "group%d ", inst
->group
);
5461 fprintf(file
, "\n");
5465 * Possibly returns an instruction that set up @param reg.
5467 * Sometimes we want to take the result of some expression/variable
5468 * dereference tree and rewrite the instruction generating the result
5469 * of the tree. When processing the tree, we know that the
5470 * instructions generated are all writing temporaries that are dead
5471 * outside of this tree. So, if we have some instructions that write
5472 * a temporary, we're free to point that temp write somewhere else.
5474 * Note that this doesn't guarantee that the instruction generated
5475 * only reg -- it might be the size=4 destination of a texture instruction.
5478 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5483 end
->is_partial_write() ||
5484 !reg
.equals(end
->dst
)) {
5492 fs_visitor::setup_fs_payload_gen6()
5494 assert(stage
== MESA_SHADER_FRAGMENT
);
5495 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
5497 assert(devinfo
->gen
>= 6);
5499 /* R0-1: masks, pixel X/Y coordinates. */
5500 payload
.num_regs
= 2;
5501 /* R2: only for 32-pixel dispatch.*/
5503 /* R3-26: barycentric interpolation coordinates. These appear in the
5504 * same order that they appear in the brw_barycentric_mode
5505 * enum. Each set of coordinates occupies 2 registers if dispatch width
5506 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5507 * appear if they were enabled using the "Barycentric Interpolation
5508 * Mode" bits in WM_STATE.
5510 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5511 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
5512 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5513 payload
.num_regs
+= 2;
5514 if (dispatch_width
== 16) {
5515 payload
.num_regs
+= 2;
5520 /* R27: interpolated depth if uses source depth */
5521 prog_data
->uses_src_depth
=
5522 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5523 if (prog_data
->uses_src_depth
) {
5524 payload
.source_depth_reg
= payload
.num_regs
;
5526 if (dispatch_width
== 16) {
5527 /* R28: interpolated depth if not SIMD8. */
5532 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5533 prog_data
->uses_src_w
=
5534 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5535 if (prog_data
->uses_src_w
) {
5536 payload
.source_w_reg
= payload
.num_regs
;
5538 if (dispatch_width
== 16) {
5539 /* R30: interpolated W if not SIMD8. */
5544 /* R31: MSAA position offsets. */
5545 if (prog_data
->persample_dispatch
&&
5546 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5547 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5549 * "MSDISPMODE_PERSAMPLE is required in order to select
5552 * So we can only really get sample positions if we are doing real
5553 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5554 * persample dispatch, we hard-code it to 0.5.
5556 prog_data
->uses_pos_offset
= true;
5557 payload
.sample_pos_reg
= payload
.num_regs
;
5561 /* R32: MSAA input coverage mask */
5562 prog_data
->uses_sample_mask
=
5563 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5564 if (prog_data
->uses_sample_mask
) {
5565 assert(devinfo
->gen
>= 7);
5566 payload
.sample_mask_in_reg
= payload
.num_regs
;
5568 if (dispatch_width
== 16) {
5569 /* R33: input coverage mask if not SIMD8. */
5574 /* R34-: bary for 32-pixel. */
5575 /* R58-59: interp W for 32-pixel. */
5577 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5578 source_depth_to_render_target
= true;
5583 fs_visitor::setup_vs_payload()
5585 /* R0: thread header, R1: urb handles */
5586 payload
.num_regs
= 2;
5590 fs_visitor::setup_gs_payload()
5592 assert(stage
== MESA_SHADER_GEOMETRY
);
5594 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
5595 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
5597 /* R0: thread header, R1: output URB handles */
5598 payload
.num_regs
= 2;
5600 if (gs_prog_data
->include_primitive_id
) {
5601 /* R2: Primitive ID 0..7 */
5605 /* Always enable VUE handles so we can safely use pull model if needed.
5607 * The push model for a GS uses a ton of register space even for trivial
5608 * scenarios with just a few inputs, so just make things easier and a bit
5609 * safer by always having pull model available.
5611 gs_prog_data
->base
.include_vue_handles
= true;
5613 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5614 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5616 /* Use a maximum of 24 registers for push-model inputs. */
5617 const unsigned max_push_components
= 24;
5619 /* If pushing our inputs would take too many registers, reduce the URB read
5620 * length (which is in HWords, or 8 registers), and resort to pulling.
5622 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5623 * have to multiply by VerticesIn to obtain the total storage requirement.
5625 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5626 max_push_components
) {
5627 vue_prog_data
->urb_read_length
=
5628 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5633 fs_visitor::setup_cs_payload()
5635 assert(devinfo
->gen
>= 7);
5636 payload
.num_regs
= 1;
5640 fs_visitor::calculate_register_pressure()
5642 invalidate_live_intervals();
5643 calculate_live_intervals();
5645 unsigned num_instructions
= 0;
5646 foreach_block(block
, cfg
)
5647 num_instructions
+= block
->instructions
.length();
5649 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5651 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5652 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5653 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5658 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5660 * The needs_unlit_centroid_workaround ends up producing one of these per
5661 * channel of centroid input, so it's good to clean them up.
5663 * An assumption here is that nothing ever modifies the dispatched pixels
5664 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5665 * dictates that anyway.
5668 fs_visitor::opt_drop_redundant_mov_to_flags()
5670 bool flag_mov_found
[2] = {false};
5671 bool progress
= false;
5673 /* Instructions removed by this pass can only be added if this were true */
5674 if (!devinfo
->needs_unlit_centroid_workaround
)
5677 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5678 if (inst
->is_control_flow()) {
5679 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5680 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5681 if (!flag_mov_found
[inst
->flag_subreg
]) {
5682 flag_mov_found
[inst
->flag_subreg
] = true;
5684 inst
->remove(block
);
5687 } else if (inst
->flags_written()) {
5688 flag_mov_found
[inst
->flag_subreg
] = false;
5696 fs_visitor::optimize()
5698 /* Start by validating the shader we currently have. */
5701 /* bld is the common builder object pointing at the end of the program we
5702 * used to translate it into i965 IR. For the optimization and lowering
5703 * passes coming next, any code added after the end of the program without
5704 * having explicitly called fs_builder::at() clearly points at a mistake.
5705 * Ideally optimization passes wouldn't be part of the visitor so they
5706 * wouldn't have access to bld at all, but they do, so just in case some
5707 * pass forgets to ask for a location explicitly set it to NULL here to
5708 * make it trip. The dispatch width is initialized to a bogus value to
5709 * make sure that optimizations set the execution controls explicitly to
5710 * match the code they are manipulating instead of relying on the defaults.
5712 bld
= fs_builder(this, 64);
5714 assign_constant_locations();
5715 lower_constant_loads();
5719 split_virtual_grfs();
5722 #define OPT(pass, args...) ({ \
5724 bool this_progress = pass(args); \
5726 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5727 char filename[64]; \
5728 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5729 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5731 backend_shader::dump_instructions(filename); \
5736 progress = progress || this_progress; \
5740 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5742 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5743 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5745 backend_shader::dump_instructions(filename
);
5748 bool progress
= false;
5752 OPT(opt_drop_redundant_mov_to_flags
);
5759 OPT(remove_duplicate_mrf_writes
);
5763 OPT(opt_copy_propagation
);
5764 OPT(opt_predicated_break
, this);
5765 OPT(opt_cmod_propagation
);
5766 OPT(dead_code_eliminate
);
5767 OPT(opt_peephole_sel
);
5768 OPT(dead_control_flow_eliminate
, this);
5769 OPT(opt_register_renaming
);
5770 OPT(opt_saturate_propagation
);
5771 OPT(register_coalesce
);
5772 OPT(compute_to_mrf
);
5773 OPT(eliminate_find_live_channel
);
5775 OPT(compact_virtual_grfs
);
5781 if (OPT(lower_pack
)) {
5782 OPT(register_coalesce
);
5783 OPT(dead_code_eliminate
);
5786 OPT(lower_simd_width
);
5788 /* After SIMD lowering just in case we had to unroll the EOT send. */
5789 OPT(opt_sampler_eot
);
5791 OPT(lower_logical_sends
);
5794 OPT(opt_copy_propagation
);
5795 /* Only run after logical send lowering because it's easier to implement
5796 * in terms of physical sends.
5798 if (OPT(opt_zero_samples
))
5799 OPT(opt_copy_propagation
);
5800 /* Run after logical send lowering to give it a chance to CSE the
5801 * LOAD_PAYLOAD instructions created to construct the payloads of
5802 * e.g. texturing messages in cases where it wasn't possible to CSE the
5803 * whole logical instruction.
5806 OPT(register_coalesce
);
5807 OPT(compute_to_mrf
);
5808 OPT(dead_code_eliminate
);
5809 OPT(remove_duplicate_mrf_writes
);
5810 OPT(opt_peephole_sel
);
5813 OPT(opt_redundant_discard_jumps
);
5815 if (OPT(lower_load_payload
)) {
5816 split_virtual_grfs();
5817 OPT(register_coalesce
);
5818 OPT(compute_to_mrf
);
5819 OPT(dead_code_eliminate
);
5822 OPT(opt_combine_constants
);
5823 OPT(lower_integer_multiplication
);
5825 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5826 OPT(opt_cmod_propagation
);
5828 OPT(opt_copy_propagation
);
5829 OPT(dead_code_eliminate
);
5832 if (OPT(lower_conversions
)) {
5833 OPT(opt_copy_propagation
);
5834 OPT(dead_code_eliminate
);
5835 OPT(lower_simd_width
);
5838 lower_uniform_pull_constant_loads();
5844 * Three source instruction must have a GRF/MRF destination register.
5845 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5848 fs_visitor::fixup_3src_null_dest()
5850 bool progress
= false;
5852 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5853 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5854 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5861 invalidate_live_intervals();
5865 fs_visitor::allocate_registers(bool allow_spilling
)
5867 bool allocated_without_spills
;
5869 static const enum instruction_scheduler_mode pre_modes
[] = {
5871 SCHEDULE_PRE_NON_LIFO
,
5875 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5877 /* Try each scheduling heuristic to see if it can successfully register
5878 * allocate without spilling. They should be ordered by decreasing
5879 * performance but increasing likelihood of allocating.
5881 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5882 schedule_instructions(pre_modes
[i
]);
5885 assign_regs_trivial();
5886 allocated_without_spills
= true;
5888 allocated_without_spills
= assign_regs(false, spill_all
);
5890 if (allocated_without_spills
)
5894 if (!allocated_without_spills
) {
5895 if (!allow_spilling
)
5896 fail("Failure to register allocate and spilling is not allowed.");
5898 /* We assume that any spilling is worse than just dropping back to
5899 * SIMD8. There's probably actually some intermediate point where
5900 * SIMD16 with a couple of spills is still better.
5902 if (dispatch_width
> min_dispatch_width
) {
5903 fail("Failure to register allocate. Reduce number of "
5904 "live scalar values to avoid this.");
5906 compiler
->shader_perf_log(log_data
,
5907 "%s shader triggered register spilling. "
5908 "Try reducing the number of live scalar "
5909 "values to improve performance.\n",
5913 /* Since we're out of heuristics, just go spill registers until we
5914 * get an allocation.
5916 while (!assign_regs(true, spill_all
)) {
5922 /* This must come after all optimization and register allocation, since
5923 * it inserts dead code that happens to have side effects, and it does
5924 * so based on the actual physical registers in use.
5926 insert_gen4_send_dependency_workarounds();
5931 schedule_instructions(SCHEDULE_POST
);
5933 if (last_scratch
> 0) {
5934 MAYBE_UNUSED
unsigned max_scratch_size
= 2 * 1024 * 1024;
5936 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5938 if (stage
== MESA_SHADER_COMPUTE
) {
5939 if (devinfo
->is_haswell
) {
5940 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5941 * field documentation, Haswell supports a minimum of 2kB of
5942 * scratch space for compute shaders, unlike every other stage
5945 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5946 } else if (devinfo
->gen
<= 7) {
5947 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5948 * field documentation, platforms prior to Haswell measure scratch
5949 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5951 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
5952 max_scratch_size
= 12 * 1024;
5956 /* We currently only support up to 2MB of scratch space. If we
5957 * need to support more eventually, the documentation suggests
5958 * that we could allocate a larger buffer, and partition it out
5959 * ourselves. We'd just have to undo the hardware's address
5960 * calculation by subtracting (FFTID * Per Thread Scratch Space)
5961 * and then add FFTID * (Larger Per Thread Scratch Space).
5963 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
5964 * Thread Group Tracking > Local Memory/Scratch Space.
5966 assert(prog_data
->total_scratch
< max_scratch_size
);
5971 fs_visitor::run_vs()
5973 assert(stage
== MESA_SHADER_VERTEX
);
5977 if (shader_time_index
>= 0)
5978 emit_shader_time_begin();
5985 compute_clip_distance();
5989 if (shader_time_index
>= 0)
5990 emit_shader_time_end();
5996 assign_curb_setup();
5997 assign_vs_urb_setup();
5999 fixup_3src_null_dest();
6000 allocate_registers(true);
6006 fs_visitor::run_tcs_single_patch()
6008 assert(stage
== MESA_SHADER_TESS_CTRL
);
6010 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
6012 /* r1-r4 contain the ICP handles. */
6013 payload
.num_regs
= 5;
6015 if (shader_time_index
>= 0)
6016 emit_shader_time_begin();
6018 /* Initialize gl_InvocationID */
6019 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6020 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6021 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6022 bld
.MOV(channels_ud
, channels_uw
);
6024 if (tcs_prog_data
->instances
== 1) {
6025 invocation_id
= channels_ud
;
6027 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6029 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6030 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6031 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6032 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6033 brw_imm_ud(INTEL_MASK(23, 17)));
6034 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6036 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6039 /* Fix the disptach mask */
6040 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6041 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6042 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
6043 bld
.IF(BRW_PREDICATE_NORMAL
);
6048 if (nir
->info
.tess
.tcs_vertices_out
% 8) {
6049 bld
.emit(BRW_OPCODE_ENDIF
);
6052 /* Emit EOT write; set TR DS Cache bit */
6054 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6055 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6056 fs_reg(brw_imm_ud(0)),
6058 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6059 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6061 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6062 bld
.null_reg_ud(), payload
);
6066 if (shader_time_index
>= 0)
6067 emit_shader_time_end();
6076 assign_curb_setup();
6077 assign_tcs_single_patch_urb_setup();
6079 fixup_3src_null_dest();
6080 allocate_registers(true);
6086 fs_visitor::run_tes()
6088 assert(stage
== MESA_SHADER_TESS_EVAL
);
6090 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6091 payload
.num_regs
= 5;
6093 if (shader_time_index
>= 0)
6094 emit_shader_time_begin();
6103 if (shader_time_index
>= 0)
6104 emit_shader_time_end();
6110 assign_curb_setup();
6111 assign_tes_urb_setup();
6113 fixup_3src_null_dest();
6114 allocate_registers(true);
6120 fs_visitor::run_gs()
6122 assert(stage
== MESA_SHADER_GEOMETRY
);
6126 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6128 if (gs_compile
->control_data_header_size_bits
> 0) {
6129 /* Create a VGRF to store accumulated control data bits. */
6130 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6132 /* If we're outputting more than 32 control data bits, then EmitVertex()
6133 * will set control_data_bits to 0 after emitting the first vertex.
6134 * Otherwise, we need to initialize it to 0 here.
6136 if (gs_compile
->control_data_header_size_bits
<= 32) {
6137 const fs_builder abld
= bld
.annotate("initialize control data bits");
6138 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6142 if (shader_time_index
>= 0)
6143 emit_shader_time_begin();
6147 emit_gs_thread_end();
6149 if (shader_time_index
>= 0)
6150 emit_shader_time_end();
6159 assign_curb_setup();
6160 assign_gs_urb_setup();
6162 fixup_3src_null_dest();
6163 allocate_registers(true);
6169 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6171 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
6172 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6174 assert(stage
== MESA_SHADER_FRAGMENT
);
6176 if (devinfo
->gen
>= 6)
6177 setup_fs_payload_gen6();
6179 setup_fs_payload_gen4();
6183 } else if (do_rep_send
) {
6184 assert(dispatch_width
== 16);
6185 emit_repclear_shader();
6187 if (shader_time_index
>= 0)
6188 emit_shader_time_begin();
6190 calculate_urb_setup();
6191 if (nir
->info
.inputs_read
> 0 ||
6192 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
6193 if (devinfo
->gen
< 6)
6194 emit_interpolation_setup_gen4();
6196 emit_interpolation_setup_gen6();
6199 /* We handle discards by keeping track of the still-live pixels in f0.1.
6200 * Initialize it with the dispatched pixels.
6202 if (wm_prog_data
->uses_kill
) {
6203 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6204 discard_init
->flag_subreg
= 1;
6207 /* Generate FS IR for main(). (the visitor only descends into
6208 * functions called "main").
6215 if (wm_prog_data
->uses_kill
)
6216 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6218 if (wm_key
->alpha_test_func
)
6223 if (shader_time_index
>= 0)
6224 emit_shader_time_end();
6230 assign_curb_setup();
6233 fixup_3src_null_dest();
6234 allocate_registers(allow_spilling
);
6244 fs_visitor::run_cs()
6246 assert(stage
== MESA_SHADER_COMPUTE
);
6250 if (shader_time_index
>= 0)
6251 emit_shader_time_begin();
6253 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6254 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6255 const fs_builder abld
= bld
.exec_all().group(1, 0);
6256 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
6257 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6265 emit_cs_terminate();
6267 if (shader_time_index
>= 0)
6268 emit_shader_time_end();
6274 assign_curb_setup();
6276 fixup_3src_null_dest();
6277 allocate_registers(true);
6286 * Return a bitfield where bit n is set if barycentric interpolation mode n
6287 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6289 * We examine the load_barycentric intrinsics rather than looking at input
6290 * variables so that we catch interpolateAtCentroid() messages too, which
6291 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
6294 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
6295 const nir_shader
*shader
)
6297 unsigned barycentric_interp_modes
= 0;
6299 nir_foreach_function(f
, shader
) {
6303 nir_foreach_block(block
, f
->impl
) {
6304 nir_foreach_instr(instr
, block
) {
6305 if (instr
->type
!= nir_instr_type_intrinsic
)
6308 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6309 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6312 /* Ignore WPOS; it doesn't require interpolation. */
6313 if (nir_intrinsic_base(intrin
) == VARYING_SLOT_POS
)
6316 intrin
= nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6317 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
6318 nir_intrinsic_interp_mode(intrin
);
6319 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
6320 enum brw_barycentric_mode bary
=
6321 brw_barycentric_mode(interp
, bary_op
);
6323 barycentric_interp_modes
|= 1 << bary
;
6325 if (devinfo
->needs_unlit_centroid_workaround
&&
6326 bary_op
== nir_intrinsic_load_barycentric_centroid
)
6327 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
6332 return barycentric_interp_modes
;
6336 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6337 const nir_shader
*shader
)
6339 prog_data
->flat_inputs
= 0;
6341 nir_foreach_variable(var
, &shader
->inputs
) {
6342 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6344 if (input_index
< 0)
6348 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6349 prog_data
->flat_inputs
|= (1 << input_index
);
6354 computed_depth_mode(const nir_shader
*shader
)
6356 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6357 switch (shader
->info
.fs
.depth_layout
) {
6358 case FRAG_DEPTH_LAYOUT_NONE
:
6359 case FRAG_DEPTH_LAYOUT_ANY
:
6360 return BRW_PSCDEPTH_ON
;
6361 case FRAG_DEPTH_LAYOUT_GREATER
:
6362 return BRW_PSCDEPTH_ON_GE
;
6363 case FRAG_DEPTH_LAYOUT_LESS
:
6364 return BRW_PSCDEPTH_ON_LE
;
6365 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6366 return BRW_PSCDEPTH_OFF
;
6369 return BRW_PSCDEPTH_OFF
;
6373 * Move load_interpolated_input with simple (payload-based) barycentric modes
6374 * to the top of the program so we don't emit multiple PLNs for the same input.
6376 * This works around CSE not being able to handle non-dominating cases
6382 * interpolate the same exact input
6385 * This should be replaced by global value numbering someday.
6388 move_interpolation_to_top(nir_shader
*nir
)
6390 bool progress
= false;
6392 nir_foreach_function(f
, nir
) {
6396 nir_block
*top
= nir_start_block(f
->impl
);
6397 exec_node
*cursor_node
= NULL
;
6399 nir_foreach_block(block
, f
->impl
) {
6403 nir_foreach_instr_safe(instr
, block
) {
6404 if (instr
->type
!= nir_instr_type_intrinsic
)
6407 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6408 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
6410 nir_intrinsic_instr
*bary_intrinsic
=
6411 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
6412 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
6414 /* Leave interpolateAtSample/Offset() where they are. */
6415 if (op
== nir_intrinsic_load_barycentric_at_sample
||
6416 op
== nir_intrinsic_load_barycentric_at_offset
)
6419 nir_instr
*move
[3] = {
6420 &bary_intrinsic
->instr
,
6421 intrin
->src
[1].ssa
->parent_instr
,
6425 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
6426 if (move
[i
]->block
!= top
) {
6427 move
[i
]->block
= top
;
6428 exec_node_remove(&move
[i
]->node
);
6430 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
6432 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
6434 cursor_node
= &move
[i
]->node
;
6440 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6441 ((unsigned) nir_metadata_block_index
|
6442 (unsigned) nir_metadata_dominance
));
6449 * Demote per-sample barycentric intrinsics to centroid.
6451 * Useful when rendering to a non-multisampled buffer.
6454 demote_sample_qualifiers(nir_shader
*nir
)
6456 bool progress
= true;
6458 nir_foreach_function(f
, nir
) {
6463 nir_builder_init(&b
, f
->impl
);
6465 nir_foreach_block(block
, f
->impl
) {
6466 nir_foreach_instr_safe(instr
, block
) {
6467 if (instr
->type
!= nir_instr_type_intrinsic
)
6470 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
6471 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
6472 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
6475 b
.cursor
= nir_before_instr(instr
);
6476 nir_ssa_def
*centroid
=
6477 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
6478 nir_intrinsic_interp_mode(intrin
));
6479 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
6480 nir_src_for_ssa(centroid
));
6481 nir_instr_remove(instr
);
6486 nir_metadata_preserve(f
->impl
, (nir_metadata
)
6487 ((unsigned) nir_metadata_block_index
|
6488 (unsigned) nir_metadata_dominance
));
6495 * Pre-gen6, the register file of the EUs was shared between threads,
6496 * and each thread used some subset allocated on a 16-register block
6497 * granularity. The unit states wanted these block counts.
6500 brw_register_blocks(int reg_count
)
6502 return ALIGN(reg_count
, 16) / 16 - 1;
6506 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6508 const struct brw_wm_prog_key
*key
,
6509 struct brw_wm_prog_data
*prog_data
,
6510 const nir_shader
*src_shader
,
6511 struct gl_program
*prog
,
6512 int shader_time_index8
, int shader_time_index16
,
6513 bool allow_spilling
,
6514 bool use_rep_send
, struct brw_vue_map
*vue_map
,
6515 unsigned *final_assembly_size
,
6518 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
6520 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6521 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6522 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
6523 brw_nir_lower_fs_outputs(shader
);
6525 if (devinfo
->gen
< 6) {
6526 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
, devinfo
);
6529 if (!key
->multisample_fbo
)
6530 NIR_PASS_V(shader
, demote_sample_qualifiers
);
6531 NIR_PASS_V(shader
, move_interpolation_to_top
);
6532 shader
= brw_postprocess_nir(shader
, compiler
, true);
6534 /* key->alpha_test_func means simulating alpha testing via discards,
6535 * so the shader definitely kills pixels.
6537 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
6538 key
->alpha_test_func
;
6539 prog_data
->uses_omask
= key
->multisample_fbo
&&
6540 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6541 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6542 prog_data
->computed_stencil
=
6543 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6545 prog_data
->persample_dispatch
=
6546 key
->multisample_fbo
&&
6547 (key
->persample_interp
||
6548 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6549 SYSTEM_BIT_SAMPLE_POS
)) ||
6550 shader
->info
.fs
.uses_sample_qualifier
||
6551 shader
->info
.outputs_read
);
6553 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
6555 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6556 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
6557 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
6559 prog_data
->barycentric_interp_modes
=
6560 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6562 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6563 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6564 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6566 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6567 &prog_data
->base
, prog
, shader
, 8,
6568 shader_time_index8
);
6569 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6571 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6574 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6576 simd8_grf_start
= v8
.payload
.num_regs
;
6577 simd8_grf_used
= v8
.grf_used
;
6580 if (v8
.max_dispatch_width
>= 16 &&
6581 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6582 /* Try a SIMD16 compile */
6583 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6584 &prog_data
->base
, prog
, shader
, 16,
6585 shader_time_index16
);
6586 v16
.import_uniforms(&v8
);
6587 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6588 compiler
->shader_perf_log(log_data
,
6589 "SIMD16 shader failed to compile: %s",
6592 simd16_cfg
= v16
.cfg
;
6593 simd16_grf_start
= v16
.payload
.num_regs
;
6594 simd16_grf_used
= v16
.grf_used
;
6598 /* When the caller requests a repclear shader, they want SIMD16-only */
6602 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6603 * at the top to select the shader. We've never implemented that.
6604 * Instead, we just give them exactly one shader and we pick the widest one
6607 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6610 if (prog_data
->persample_dispatch
) {
6611 /* Starting with SandyBridge (where we first get MSAA), the different
6612 * pixel dispatch combinations are grouped into classifications A
6613 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6614 * generations, the only configurations supporting persample dispatch
6615 * are are this in which only one dispatch width is enabled.
6617 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6618 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6620 if (compiler
->devinfo
->gen
== 6 &&
6621 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6623 } else if (simd16_cfg
) {
6628 /* We have to compute the flat inputs after the visitor is finished running
6629 * because it relies on prog_data->urb_setup which is computed in
6630 * fs_visitor::calculate_urb_setup().
6632 brw_compute_flat_inputs(prog_data
, shader
);
6634 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6635 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6636 MESA_SHADER_FRAGMENT
);
6638 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6639 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6640 shader
->info
.label
?
6641 shader
->info
.label
: "unnamed",
6642 shader
->info
.name
));
6646 prog_data
->dispatch_8
= true;
6647 g
.generate_code(simd8_cfg
, 8);
6648 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6649 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6652 prog_data
->dispatch_16
= true;
6653 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6654 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6655 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6657 } else if (simd16_cfg
) {
6658 prog_data
->dispatch_16
= true;
6659 g
.generate_code(simd16_cfg
, 16);
6660 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6661 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6664 return g
.get_assembly(final_assembly_size
);
6668 fs_visitor::emit_cs_work_group_id_setup()
6670 assert(stage
== MESA_SHADER_COMPUTE
);
6672 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6674 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6675 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6676 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6678 bld
.MOV(*reg
, r0_1
);
6679 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6680 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6686 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6688 block
->dwords
= dwords
;
6689 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6690 block
->size
= block
->regs
* 32;
6694 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
6695 struct brw_cs_prog_data
*cs_prog_data
)
6697 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
6698 bool fill_thread_id
=
6699 cs_prog_data
->thread_local_id_index
>= 0 &&
6700 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6701 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6703 /* The thread ID should be stored in the last param dword */
6704 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6705 assert(!fill_thread_id
||
6706 cs_prog_data
->thread_local_id_index
==
6707 (int)prog_data
->nr_params
- 1);
6709 unsigned cross_thread_dwords
, per_thread_dwords
;
6710 if (!cross_thread_supported
) {
6711 cross_thread_dwords
= 0u;
6712 per_thread_dwords
= prog_data
->nr_params
;
6713 } else if (fill_thread_id
) {
6714 /* Fill all but the last register with cross-thread payload */
6715 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6716 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6717 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6719 /* Fill all data using cross-thread payload */
6720 cross_thread_dwords
= prog_data
->nr_params
;
6721 per_thread_dwords
= 0u;
6724 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6725 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6727 unsigned total_dwords
=
6728 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6729 cs_prog_data
->push
.cross_thread
.size
) / 4;
6730 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6732 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6733 cs_prog_data
->push
.per_thread
.size
== 0);
6734 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6735 cs_prog_data
->push
.per_thread
.dwords
==
6736 prog_data
->nr_params
);
6740 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6742 cs_prog_data
->simd_size
= size
;
6743 unsigned group_size
= cs_prog_data
->local_size
[0] *
6744 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6745 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6749 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6751 const struct brw_cs_prog_key
*key
,
6752 struct brw_cs_prog_data
*prog_data
,
6753 const nir_shader
*src_shader
,
6754 int shader_time_index
,
6755 unsigned *final_assembly_size
,
6758 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6759 shader
= brw_nir_apply_sampler_key(shader
, compiler
, &key
->tex
, true);
6761 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6762 * the thread_local_id_index.
6764 assert(prog_data
->thread_local_id_index
>= 0);
6765 shader
->num_uniforms
=
6766 MAX2(shader
->num_uniforms
,
6767 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6769 brw_nir_lower_cs_intrinsics(shader
, prog_data
);
6770 shader
= brw_postprocess_nir(shader
, compiler
, true);
6772 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6773 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6774 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6775 unsigned local_workgroup_size
=
6776 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6777 shader
->info
.cs
.local_size
[2];
6779 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6780 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6783 const char *fail_msg
= NULL
;
6785 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6787 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6788 NULL
, /* Never used in core profile */
6789 shader
, 8, shader_time_index
);
6790 if (simd_required
<= 8) {
6792 fail_msg
= v8
.fail_msg
;
6795 cs_set_simd_size(prog_data
, 8);
6796 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6797 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6801 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6802 NULL
, /* Never used in core profile */
6803 shader
, 16, shader_time_index
);
6804 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6805 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6806 simd_required
<= 16) {
6807 /* Try a SIMD16 compile */
6808 if (simd_required
<= 8)
6809 v16
.import_uniforms(&v8
);
6810 if (!v16
.run_cs()) {
6811 compiler
->shader_perf_log(log_data
,
6812 "SIMD16 shader failed to compile: %s",
6816 "Couldn't generate SIMD16 program and not "
6817 "enough threads for SIMD8";
6821 cs_set_simd_size(prog_data
, 16);
6822 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6823 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6827 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6828 NULL
, /* Never used in core profile */
6829 shader
, 32, shader_time_index
);
6830 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6831 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6832 /* Try a SIMD32 compile */
6833 if (simd_required
<= 8)
6834 v32
.import_uniforms(&v8
);
6835 else if (simd_required
<= 16)
6836 v32
.import_uniforms(&v16
);
6838 if (!v32
.run_cs()) {
6839 compiler
->shader_perf_log(log_data
,
6840 "SIMD32 shader failed to compile: %s",
6844 "Couldn't generate SIMD32 program and not "
6845 "enough threads for SIMD16";
6849 cs_set_simd_size(prog_data
, 32);
6850 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6854 if (unlikely(cfg
== NULL
)) {
6857 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6862 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6863 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6864 MESA_SHADER_COMPUTE
);
6865 if (INTEL_DEBUG
& DEBUG_CS
) {
6866 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6867 shader
->info
.label
? shader
->info
.label
:
6870 g
.enable_debug(name
);
6873 g
.generate_code(cfg
, prog_data
->simd_size
);
6875 return g
.get_assembly(final_assembly_size
);
6879 * Test the dispatch mask packing assumptions of
6880 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
6881 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
6882 * executed with an unexpected dispatch mask.
6885 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
6887 const gl_shader_stage stage
= bld
.shader
->stage
;
6889 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
6890 bld
.shader
->stage_prog_data
)) {
6891 const fs_builder ubld
= bld
.exec_all().group(1, 0);
6892 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
6893 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
6896 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
6897 ubld
.AND(tmp
, mask
, tmp
);
6899 /* This will loop forever if the dispatch mask doesn't have the expected
6900 * form '2^n-1', in which case tmp will be non-zero.
6902 bld
.emit(BRW_OPCODE_DO
);
6903 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
6904 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));