2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
34 #include "brw_fs_live_variables.h"
36 #include "brw_vec4_gs_visitor.h"
38 #include "brw_dead_control_flow.h"
39 #include "dev/gen_debug.h"
40 #include "compiler/glsl_types.h"
41 #include "compiler/nir/nir_builder.h"
42 #include "program/prog_parameter.h"
43 #include "util/u_math.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset((void*)this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->size_written
= dst
.component_size(exec_size
);
82 this->size_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy((void*)this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable offset
176 * and a portion done using fs_reg::offset, which means that if you have
177 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
178 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
179 * later notice that those loads are all the same and eliminate the
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
196 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
197 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
201 * A helper for MOV generation for fixing up broken hardware SEND dependency
205 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
207 /* The caller always wants uncompressed to emit the minimal extra
208 * dependencies, and to avoid having to deal with aligning its regs to 2.
210 const fs_builder ubld
= bld
.annotate("send dependency resolve")
213 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
217 fs_inst::is_send_from_grf() const
220 case SHADER_OPCODE_SEND
:
221 case SHADER_OPCODE_SHADER_TIME_ADD
:
222 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
223 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
224 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
225 case SHADER_OPCODE_URB_WRITE_SIMD8
:
226 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
227 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
228 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
229 case SHADER_OPCODE_URB_READ_SIMD8
:
230 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
231 case SHADER_OPCODE_INTERLOCK
:
232 case SHADER_OPCODE_MEMORY_FENCE
:
233 case SHADER_OPCODE_BARRIER
:
235 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
236 return src
[1].file
== VGRF
;
237 case FS_OPCODE_FB_WRITE
:
238 case FS_OPCODE_FB_READ
:
239 return src
[0].file
== VGRF
;
242 return src
[0].file
== VGRF
;
249 fs_inst::is_control_source(unsigned arg
) const
252 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
253 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
254 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
257 case SHADER_OPCODE_BROADCAST
:
258 case SHADER_OPCODE_SHUFFLE
:
259 case SHADER_OPCODE_QUAD_SWIZZLE
:
260 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
261 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
262 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
263 case SHADER_OPCODE_GET_BUFFER_SIZE
:
266 case SHADER_OPCODE_MOV_INDIRECT
:
267 case SHADER_OPCODE_CLUSTER_BROADCAST
:
268 case SHADER_OPCODE_TEX
:
270 case SHADER_OPCODE_TXD
:
271 case SHADER_OPCODE_TXF
:
272 case SHADER_OPCODE_TXF_LZ
:
273 case SHADER_OPCODE_TXF_CMS
:
274 case SHADER_OPCODE_TXF_CMS_W
:
275 case SHADER_OPCODE_TXF_UMS
:
276 case SHADER_OPCODE_TXF_MCS
:
277 case SHADER_OPCODE_TXL
:
278 case SHADER_OPCODE_TXL_LZ
:
279 case SHADER_OPCODE_TXS
:
280 case SHADER_OPCODE_LOD
:
281 case SHADER_OPCODE_TG4
:
282 case SHADER_OPCODE_TG4_OFFSET
:
283 case SHADER_OPCODE_SAMPLEINFO
:
284 return arg
== 1 || arg
== 2;
286 case SHADER_OPCODE_SEND
:
287 return arg
== 0 || arg
== 1;
295 fs_inst::is_payload(unsigned arg
) const
298 case FS_OPCODE_FB_WRITE
:
299 case FS_OPCODE_FB_READ
:
300 case SHADER_OPCODE_URB_WRITE_SIMD8
:
301 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
302 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
303 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
304 case SHADER_OPCODE_URB_READ_SIMD8
:
305 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
306 case VEC4_OPCODE_UNTYPED_ATOMIC
:
307 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
308 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
309 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
310 case SHADER_OPCODE_SHADER_TIME_ADD
:
311 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
312 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
313 case SHADER_OPCODE_INTERLOCK
:
314 case SHADER_OPCODE_MEMORY_FENCE
:
315 case SHADER_OPCODE_BARRIER
:
318 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
321 case SHADER_OPCODE_SEND
:
322 return arg
== 2 || arg
== 3;
333 * Returns true if this instruction's sources and destinations cannot
334 * safely be the same register.
336 * In most cases, a register can be written over safely by the same
337 * instruction that is its last use. For a single instruction, the
338 * sources are dereferenced before writing of the destination starts
341 * However, there are a few cases where this can be problematic:
343 * - Virtual opcodes that translate to multiple instructions in the
344 * code generator: if src == dst and one instruction writes the
345 * destination before a later instruction reads the source, then
346 * src will have been clobbered.
348 * - SIMD16 compressed instructions with certain regioning (see below).
350 * The register allocator uses this information to set up conflicts between
351 * GRF sources and the destination.
354 fs_inst::has_source_and_destination_hazard() const
357 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
358 /* Multiple partial writes to the destination */
360 case SHADER_OPCODE_SHUFFLE
:
361 /* This instruction returns an arbitrary channel from the source and
362 * gets split into smaller instructions in the generator. It's possible
363 * that one of the instructions will read from a channel corresponding
364 * to an earlier instruction.
366 case SHADER_OPCODE_SEL_EXEC
:
367 /* This is implemented as
369 * mov(16) g4<1>D 0D { align1 WE_all 1H };
370 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
372 * Because the source is only read in the second instruction, the first
373 * may stomp all over it.
376 case SHADER_OPCODE_QUAD_SWIZZLE
:
378 case BRW_SWIZZLE_XXXX
:
379 case BRW_SWIZZLE_YYYY
:
380 case BRW_SWIZZLE_ZZZZ
:
381 case BRW_SWIZZLE_WWWW
:
382 case BRW_SWIZZLE_XXZZ
:
383 case BRW_SWIZZLE_YYWW
:
384 case BRW_SWIZZLE_XYXY
:
385 case BRW_SWIZZLE_ZWZW
:
386 /* These can be implemented as a single Align1 region on all
387 * platforms, so there's never a hazard between source and
388 * destination. C.f. fs_generator::generate_quad_swizzle().
392 return !is_uniform(src
[0]);
395 /* The SIMD16 compressed instruction
397 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
399 * is actually decoded in hardware as:
401 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
402 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
404 * Which is safe. However, if we have uniform accesses
405 * happening, we get into trouble:
407 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
408 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
410 * Now our destination for the first instruction overwrote the
411 * second instruction's src0, and we get garbage for those 8
412 * pixels. There's a similar issue for the pre-gen6
413 * pixel_x/pixel_y, which are registers of 16-bit values and thus
414 * would get stomped by the first decode as well.
416 if (exec_size
== 16) {
417 for (int i
= 0; i
< sources
; i
++) {
418 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
419 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
420 src
[i
].type
== BRW_REGISTER_TYPE_W
||
421 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
422 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
432 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
) const
434 if (devinfo
->gen
== 6 && is_math())
437 if (is_send_from_grf())
440 /* From GEN:BUG:1604601757:
442 * "When multiplying a DW and any lower precision integer, source modifier
445 if (devinfo
->gen
>= 12 && (opcode
== BRW_OPCODE_MUL
||
446 opcode
== BRW_OPCODE_MAD
)) {
447 const brw_reg_type exec_type
= get_exec_type(this);
448 const unsigned min_type_sz
= opcode
== BRW_OPCODE_MAD
?
449 MIN2(type_sz(src
[1].type
), type_sz(src
[2].type
)) :
450 MIN2(type_sz(src
[0].type
), type_sz(src
[1].type
));
452 if (brw_reg_type_is_integer(exec_type
) &&
453 type_sz(exec_type
) >= 4 &&
454 type_sz(exec_type
) != min_type_sz
)
458 if (!backend_instruction::can_do_source_mods())
465 fs_inst::can_do_cmod()
467 if (!backend_instruction::can_do_cmod())
470 /* The accumulator result appears to get used for the conditional modifier
471 * generation. When negating a UD value, there is a 33rd bit generated for
472 * the sign in the accumulator value, so now you can't check, for example,
473 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
475 for (unsigned i
= 0; i
< sources
; i
++) {
476 if (type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
484 fs_inst::can_change_types() const
486 return dst
.type
== src
[0].type
&&
487 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
488 (opcode
== BRW_OPCODE_MOV
||
489 (opcode
== BRW_OPCODE_SEL
&&
490 dst
.type
== src
[1].type
&&
491 predicate
!= BRW_PREDICATE_NONE
&&
492 !src
[1].abs
&& !src
[1].negate
));
498 memset((void*)this, 0, sizeof(*this));
499 type
= BRW_REGISTER_TYPE_UD
;
503 /** Generic unset register constructor. */
507 this->file
= BAD_FILE
;
510 fs_reg::fs_reg(struct ::brw_reg reg
) :
515 if (this->file
== IMM
&&
516 (this->type
!= BRW_REGISTER_TYPE_V
&&
517 this->type
!= BRW_REGISTER_TYPE_UV
&&
518 this->type
!= BRW_REGISTER_TYPE_VF
)) {
524 fs_reg::equals(const fs_reg
&r
) const
526 return (this->backend_reg::equals(r
) &&
531 fs_reg::negative_equals(const fs_reg
&r
) const
533 return (this->backend_reg::negative_equals(r
) &&
538 fs_reg::is_contiguous() const
543 return hstride
== BRW_HORIZONTAL_STRIDE_1
&&
544 vstride
== width
+ hstride
;
555 unreachable("Invalid register file");
559 fs_reg::component_size(unsigned width
) const
561 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
564 return MAX2(width
* stride
, 1) * type_sz(type
);
568 * Create a MOV to read the timestamp register.
571 fs_visitor::get_timestamp(const fs_builder
&bld
)
573 assert(devinfo
->gen
>= 7);
575 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
578 BRW_REGISTER_TYPE_UD
));
580 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
582 /* We want to read the 3 fields we care about even if it's not enabled in
585 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
591 fs_visitor::emit_shader_time_begin()
593 /* We want only the low 32 bits of the timestamp. Since it's running
594 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
595 * which is plenty of time for our purposes. It is identical across the
596 * EUs, but since it's tracking GPU core speed it will increment at a
597 * varying rate as render P-states change.
599 shader_start_time
= component(
600 get_timestamp(bld
.annotate("shader time start")), 0);
604 fs_visitor::emit_shader_time_end()
606 /* Insert our code just before the final SEND with EOT. */
607 exec_node
*end
= this->instructions
.get_tail();
608 assert(end
&& ((fs_inst
*) end
)->eot
);
609 const fs_builder ibld
= bld
.annotate("shader time end")
610 .exec_all().at(NULL
, end
);
611 const fs_reg timestamp
= get_timestamp(ibld
);
613 /* We only use the low 32 bits of the timestamp - see
614 * emit_shader_time_begin()).
616 * We could also check if render P-states have changed (or anything
617 * else that might disrupt timing) by setting smear to 2 and checking if
618 * that field is != 0.
620 const fs_reg shader_end_time
= component(timestamp
, 0);
622 /* Check that there weren't any timestamp reset events (assuming these
623 * were the only two timestamp reads that happened).
625 const fs_reg reset
= component(timestamp
, 2);
626 set_condmod(BRW_CONDITIONAL_Z
,
627 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
628 ibld
.IF(BRW_PREDICATE_NORMAL
);
630 fs_reg start
= shader_start_time
;
632 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
633 BRW_REGISTER_TYPE_UD
),
635 const fs_builder cbld
= ibld
.group(1, 0);
636 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
638 /* If there were no instructions between the two timestamp gets, the diff
639 * is 2 cycles. Remove that overhead, so I can forget about that when
640 * trying to determine the time taken for single instructions.
642 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
643 SHADER_TIME_ADD(cbld
, 0, diff
);
644 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
645 ibld
.emit(BRW_OPCODE_ELSE
);
646 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
647 ibld
.emit(BRW_OPCODE_ENDIF
);
651 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
652 int shader_time_subindex
,
655 int index
= shader_time_index
* 3 + shader_time_subindex
;
656 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
659 if (dispatch_width
== 8)
660 payload
= vgrf(glsl_type::uvec2_type
);
662 payload
= vgrf(glsl_type::uint_type
);
664 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
668 fs_visitor::vfail(const char *format
, va_list va
)
677 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
678 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
680 this->fail_msg
= msg
;
683 fprintf(stderr
, "%s", msg
);
688 fs_visitor::fail(const char *format
, ...)
692 va_start(va
, format
);
698 * Mark this program as impossible to compile with dispatch width greater
701 * During the SIMD8 compile (which happens first), we can detect and flag
702 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
703 * SIMD16+ compile altogether.
705 * During a compile of dispatch width greater than n (if one happens anyway),
706 * this just calls fail().
709 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
711 if (dispatch_width
> n
) {
714 max_dispatch_width
= n
;
715 compiler
->shader_perf_log(log_data
,
716 "Shader dispatch width limited to SIMD%d: %s",
722 * Returns true if the instruction has a flag that means it won't
723 * update an entire destination register.
725 * For example, dead code elimination and live variable analysis want to know
726 * when a write to a variable screens off any preceding values that were in
730 fs_inst::is_partial_write() const
732 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
733 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
734 !this->dst
.is_contiguous() ||
735 this->dst
.offset
% REG_SIZE
!= 0);
739 fs_inst::components_read(unsigned i
) const
741 /* Return zero if the source is not present. */
742 if (src
[i
].file
== BAD_FILE
)
746 case FS_OPCODE_LINTERP
:
752 case FS_OPCODE_PIXEL_X
:
753 case FS_OPCODE_PIXEL_Y
:
757 case FS_OPCODE_FB_WRITE_LOGICAL
:
758 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
759 /* First/second FB write color. */
761 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
765 case SHADER_OPCODE_TEX_LOGICAL
:
766 case SHADER_OPCODE_TXD_LOGICAL
:
767 case SHADER_OPCODE_TXF_LOGICAL
:
768 case SHADER_OPCODE_TXL_LOGICAL
:
769 case SHADER_OPCODE_TXS_LOGICAL
:
770 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
771 case FS_OPCODE_TXB_LOGICAL
:
772 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
773 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
774 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
775 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
776 case SHADER_OPCODE_LOD_LOGICAL
:
777 case SHADER_OPCODE_TG4_LOGICAL
:
778 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
779 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
780 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
781 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
782 /* Texture coordinates. */
783 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
784 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
785 /* Texture derivatives. */
786 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
787 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
788 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
789 /* Texture offset. */
790 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
793 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
798 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
799 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
800 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
);
801 /* Surface coordinates. */
802 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
803 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
804 /* Surface operation source (ignored for reads). */
805 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
810 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
811 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
812 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
813 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
814 /* Surface coordinates. */
815 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
816 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
817 /* Surface operation source. */
818 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
819 return src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
823 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
824 assert(src
[2].file
== IMM
);
827 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
828 assert(src
[2].file
== IMM
);
829 return i
== 1 ? src
[2].ud
: 1;
831 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
832 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
833 assert(src
[2].file
== IMM
);
836 const unsigned op
= src
[2].ud
;
851 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
852 assert(src
[2].file
== IMM
);
855 const unsigned op
= src
[2].ud
;
856 return op
== BRW_AOP_FCMPWR
? 2 : 1;
861 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
862 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
863 /* Scattered logical opcodes use the following params:
864 * src[0] Surface coordinates
865 * src[1] Surface operation source (ignored for reads)
867 * src[3] IMM with always 1 dimension.
868 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
870 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
871 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
872 return i
== SURFACE_LOGICAL_SRC_DATA
? 0 : 1;
874 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
875 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
876 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
877 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
880 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
881 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
882 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
883 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
884 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
885 /* Surface coordinates. */
886 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
887 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
888 /* Surface operation source. */
889 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_CMPWR
)
891 else if (i
== SURFACE_LOGICAL_SRC_DATA
&&
892 (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
|| op
== BRW_AOP_PREDEC
))
897 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
898 return (i
== 0 ? 2 : 1);
900 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
: {
901 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
902 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
903 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
904 /* Surface coordinates. */
905 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
906 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
907 /* Surface operation source. */
908 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_FCMPWR
)
920 fs_inst::size_read(int arg
) const
923 case SHADER_OPCODE_SEND
:
925 return mlen
* REG_SIZE
;
926 } else if (arg
== 3) {
927 return ex_mlen
* REG_SIZE
;
931 case FS_OPCODE_FB_WRITE
:
932 case FS_OPCODE_REP_FB_WRITE
:
935 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
937 return mlen
* REG_SIZE
;
941 case FS_OPCODE_FB_READ
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8
:
943 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
944 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
945 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
946 case SHADER_OPCODE_URB_READ_SIMD8
:
947 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
948 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
949 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
951 return mlen
* REG_SIZE
;
954 case FS_OPCODE_SET_SAMPLE_ID
:
959 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
960 /* The payload is actually stored in src1 */
962 return mlen
* REG_SIZE
;
965 case FS_OPCODE_LINTERP
:
970 case SHADER_OPCODE_LOAD_PAYLOAD
:
971 if (arg
< this->header_size
)
975 case CS_OPCODE_CS_TERMINATE
:
976 case SHADER_OPCODE_BARRIER
:
979 case SHADER_OPCODE_MOV_INDIRECT
:
981 assert(src
[2].file
== IMM
);
987 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
988 return mlen
* REG_SIZE
;
992 switch (src
[arg
].file
) {
995 return components_read(arg
) * type_sz(src
[arg
].type
);
1001 return components_read(arg
) * src
[arg
].component_size(exec_size
);
1003 unreachable("MRF registers are not allowed as sources");
1010 predicate_width(brw_predicate predicate
)
1012 switch (predicate
) {
1013 case BRW_PREDICATE_NONE
: return 1;
1014 case BRW_PREDICATE_NORMAL
: return 1;
1015 case BRW_PREDICATE_ALIGN1_ANY2H
: return 2;
1016 case BRW_PREDICATE_ALIGN1_ALL2H
: return 2;
1017 case BRW_PREDICATE_ALIGN1_ANY4H
: return 4;
1018 case BRW_PREDICATE_ALIGN1_ALL4H
: return 4;
1019 case BRW_PREDICATE_ALIGN1_ANY8H
: return 8;
1020 case BRW_PREDICATE_ALIGN1_ALL8H
: return 8;
1021 case BRW_PREDICATE_ALIGN1_ANY16H
: return 16;
1022 case BRW_PREDICATE_ALIGN1_ALL16H
: return 16;
1023 case BRW_PREDICATE_ALIGN1_ANY32H
: return 32;
1024 case BRW_PREDICATE_ALIGN1_ALL32H
: return 32;
1025 default: unreachable("Unsupported predicate");
1029 /* Return the subset of flag registers that an instruction could
1030 * potentially read or write based on the execution controls and flag
1031 * subregister number of the instruction.
1034 flag_mask(const fs_inst
*inst
, unsigned width
)
1036 assert(util_is_power_of_two_nonzero(width
));
1037 const unsigned start
= (inst
->flag_subreg
* 16 + inst
->group
) &
1039 const unsigned end
= start
+ ALIGN(inst
->exec_size
, width
);
1040 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
1044 bit_mask(unsigned n
)
1046 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
1050 flag_mask(const fs_reg
&r
, unsigned sz
)
1052 if (r
.file
== ARF
) {
1053 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
1054 const unsigned end
= start
+ sz
;
1055 return bit_mask(end
) & ~bit_mask(start
);
1063 fs_inst::flags_read(const gen_device_info
*devinfo
) const
1065 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
1066 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
1067 /* The vertical predication modes combine corresponding bits from
1068 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
1070 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
1071 return flag_mask(this, 1) << shift
| flag_mask(this, 1);
1072 } else if (predicate
) {
1073 return flag_mask(this, predicate_width(predicate
));
1076 for (int i
= 0; i
< sources
; i
++) {
1077 mask
|= flag_mask(src
[i
], size_read(i
));
1084 fs_inst::flags_written() const
1086 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1087 opcode
!= BRW_OPCODE_CSEL
&&
1088 opcode
!= BRW_OPCODE_IF
&&
1089 opcode
!= BRW_OPCODE_WHILE
)) ||
1090 opcode
== FS_OPCODE_FB_WRITE
) {
1091 return flag_mask(this, 1);
1092 } else if (opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
1093 opcode
== FS_OPCODE_LOAD_LIVE_CHANNELS
) {
1094 return flag_mask(this, 32);
1096 return flag_mask(dst
, size_written
);
1101 * Returns how many MRFs an FS opcode will write over.
1103 * Note that this is not the 0 or 1 implied writes in an actual gen
1104 * instruction -- the FS opcodes often generate MOVs in addition.
1107 fs_inst::implied_mrf_writes() const
1116 case SHADER_OPCODE_RCP
:
1117 case SHADER_OPCODE_RSQ
:
1118 case SHADER_OPCODE_SQRT
:
1119 case SHADER_OPCODE_EXP2
:
1120 case SHADER_OPCODE_LOG2
:
1121 case SHADER_OPCODE_SIN
:
1122 case SHADER_OPCODE_COS
:
1123 return 1 * exec_size
/ 8;
1124 case SHADER_OPCODE_POW
:
1125 case SHADER_OPCODE_INT_QUOTIENT
:
1126 case SHADER_OPCODE_INT_REMAINDER
:
1127 return 2 * exec_size
/ 8;
1128 case SHADER_OPCODE_TEX
:
1130 case SHADER_OPCODE_TXD
:
1131 case SHADER_OPCODE_TXF
:
1132 case SHADER_OPCODE_TXF_CMS
:
1133 case SHADER_OPCODE_TXF_MCS
:
1134 case SHADER_OPCODE_TG4
:
1135 case SHADER_OPCODE_TG4_OFFSET
:
1136 case SHADER_OPCODE_TXL
:
1137 case SHADER_OPCODE_TXS
:
1138 case SHADER_OPCODE_LOD
:
1139 case SHADER_OPCODE_SAMPLEINFO
:
1141 case FS_OPCODE_FB_WRITE
:
1142 case FS_OPCODE_REP_FB_WRITE
:
1143 return src
[0].file
== BAD_FILE
? 0 : 2;
1144 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1145 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1147 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1149 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1152 unreachable("not reached");
1157 fs_visitor::vgrf(const glsl_type
*const type
)
1159 int reg_width
= dispatch_width
/ 8;
1161 alloc
.allocate(glsl_count_dword_slots(type
, false) * reg_width
),
1162 brw_type_for_base_type(type
));
1165 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1170 this->type
= BRW_REGISTER_TYPE_F
;
1171 this->stride
= (file
== UNIFORM
? 0 : 1);
1174 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1180 this->stride
= (file
== UNIFORM
? 0 : 1);
1183 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1184 * This brings in those uniform definitions
1187 fs_visitor::import_uniforms(fs_visitor
*v
)
1189 this->push_constant_loc
= v
->push_constant_loc
;
1190 this->pull_constant_loc
= v
->pull_constant_loc
;
1191 this->uniforms
= v
->uniforms
;
1192 this->subgroup_id
= v
->subgroup_id
;
1196 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1198 assert(stage
== MESA_SHADER_FRAGMENT
);
1200 /* gl_FragCoord.x */
1201 bld
.MOV(wpos
, this->pixel_x
);
1202 wpos
= offset(wpos
, bld
, 1);
1204 /* gl_FragCoord.y */
1205 bld
.MOV(wpos
, this->pixel_y
);
1206 wpos
= offset(wpos
, bld
, 1);
1208 /* gl_FragCoord.z */
1209 if (devinfo
->gen
>= 6) {
1210 bld
.MOV(wpos
, fetch_payload_reg(bld
, payload
.source_depth_reg
));
1212 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1213 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1214 component(interp_reg(VARYING_SLOT_POS
, 2), 0));
1216 wpos
= offset(wpos
, bld
, 1);
1218 /* gl_FragCoord.w: Already set up in emit_interpolation */
1219 bld
.MOV(wpos
, this->wpos_w
);
1222 enum brw_barycentric_mode
1223 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1225 /* Barycentric modes don't make sense for flat inputs. */
1226 assert(mode
!= INTERP_MODE_FLAT
);
1230 case nir_intrinsic_load_barycentric_pixel
:
1231 case nir_intrinsic_load_barycentric_at_offset
:
1232 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1234 case nir_intrinsic_load_barycentric_centroid
:
1235 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1237 case nir_intrinsic_load_barycentric_sample
:
1238 case nir_intrinsic_load_barycentric_at_sample
:
1239 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1242 unreachable("invalid intrinsic");
1245 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1248 return (enum brw_barycentric_mode
) bary
;
1252 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1254 static enum brw_barycentric_mode
1255 centroid_to_pixel(enum brw_barycentric_mode bary
)
1257 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1258 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1259 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1263 fs_visitor::emit_frontfacing_interpolation()
1265 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1267 if (devinfo
->gen
>= 12) {
1268 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
1270 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1271 bld
.ASR(tmp
, g1
, brw_imm_d(15));
1273 } else if (devinfo
->gen
>= 6) {
1274 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1275 * a boolean result from this (~0/true or 0/false).
1277 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1278 * this task in only one instruction:
1279 * - a negation source modifier will flip the bit; and
1280 * - a W -> D type conversion will sign extend the bit into the high
1281 * word of the destination.
1283 * An ASR 15 fills the low word of the destination.
1285 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1288 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1290 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1291 * a boolean result from this (1/true or 0/false).
1293 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1294 * the negation source modifier to flip it. Unfortunately the SHR
1295 * instruction only operates on UD (or D with an abs source modifier)
1296 * sources without negation.
1298 * Instead, use ASR (which will give ~0/true or 0/false).
1300 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1303 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1310 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1312 assert(stage
== MESA_SHADER_FRAGMENT
);
1313 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1314 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1316 if (wm_prog_data
->persample_dispatch
) {
1317 /* Convert int_sample_pos to floating point */
1318 bld
.MOV(dst
, int_sample_pos
);
1319 /* Scale to the range [0, 1] */
1320 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1323 /* From ARB_sample_shading specification:
1324 * "When rendering to a non-multisample buffer, or if multisample
1325 * rasterization is disabled, gl_SamplePosition will always be
1328 bld
.MOV(dst
, brw_imm_f(0.5f
));
1333 fs_visitor::emit_samplepos_setup()
1335 assert(devinfo
->gen
>= 6);
1337 const fs_builder abld
= bld
.annotate("compute sample position");
1338 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1340 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1341 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1343 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1344 * mode will be enabled.
1346 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1347 * R31.1:0 Position Offset X/Y for Slot[3:0]
1348 * R31.3:2 Position Offset X/Y for Slot[7:4]
1351 * The X, Y sample positions come in as bytes in thread payload. So, read
1352 * the positions using vstride=16, width=8, hstride=2.
1354 const fs_reg sample_pos_reg
=
1355 fetch_payload_reg(abld
, payload
.sample_pos_reg
, BRW_REGISTER_TYPE_W
);
1357 /* Compute gl_SamplePosition.x */
1358 abld
.MOV(int_sample_x
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 0));
1359 compute_sample_position(offset(pos
, abld
, 0), int_sample_x
);
1361 /* Compute gl_SamplePosition.y */
1362 abld
.MOV(int_sample_y
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 1));
1363 compute_sample_position(offset(pos
, abld
, 1), int_sample_y
);
1368 fs_visitor::emit_sampleid_setup()
1370 assert(stage
== MESA_SHADER_FRAGMENT
);
1371 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1372 assert(devinfo
->gen
>= 6);
1374 const fs_builder abld
= bld
.annotate("compute sample id");
1375 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1377 if (!key
->multisample_fbo
) {
1378 /* As per GL_ARB_sample_shading specification:
1379 * "When rendering to a non-multisample buffer, or if multisample
1380 * rasterization is disabled, gl_SampleID will always be zero."
1382 abld
.MOV(*reg
, brw_imm_d(0));
1383 } else if (devinfo
->gen
>= 8) {
1384 /* Sample ID comes in as 4-bit numbers in g1.0:
1386 * 15:12 Slot 3 SampleID (only used in SIMD16)
1387 * 11:8 Slot 2 SampleID (only used in SIMD16)
1388 * 7:4 Slot 1 SampleID
1389 * 3:0 Slot 0 SampleID
1391 * Each slot corresponds to four channels, so we want to replicate each
1392 * half-byte value to 4 channels in a row:
1394 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1395 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1397 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1398 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1400 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1401 * channels to read the first byte (7:0), and the second group of 8
1402 * channels to read the second byte (15:8). Then, we shift right by
1403 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1404 * values into place. Finally, we AND with 0xf to keep the low nibble.
1406 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1407 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1409 * TODO: These payload bits exist on Gen7 too, but they appear to always
1410 * be zero, so this code fails to work. We should find out why.
1412 const fs_reg tmp
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1414 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
1415 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
1416 hbld
.SHR(offset(tmp
, hbld
, i
),
1417 stride(retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UB
),
1419 brw_imm_v(0x44440000));
1422 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1424 const fs_reg t1
= component(abld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
1425 const fs_reg t2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1427 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1428 * 8x multisampling, subspan 0 will represent sample N (where N
1429 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1430 * 7. We can find the value of N by looking at R0.0 bits 7:6
1431 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1432 * (since samples are always delivered in pairs). That is, we
1433 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1434 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1435 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1436 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1437 * populating a temporary variable with the sequence (0, 1, 2, 3),
1438 * and then reading from it using vstride=1, width=4, hstride=0.
1439 * These computations hold good for 4x multisampling as well.
1441 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1442 * the first four slots are sample 0 of subspan 0; the next four
1443 * are sample 1 of subspan 0; the third group is sample 0 of
1444 * subspan 1, and finally sample 1 of subspan 1.
1447 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1448 * accomodate 16x MSAA.
1450 abld
.exec_all().group(1, 0)
1451 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1453 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1455 /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1456 * can assume 4x MSAA. Disallow it on IVB+
1458 * FINISHME: One day, we could come up with a way to do this that
1459 * actually works on gen7.
1461 if (devinfo
->gen
>= 7)
1462 limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
1463 abld
.exec_all().group(8, 0).MOV(t2
, brw_imm_v(0x32103210));
1465 /* This special instruction takes care of setting vstride=1,
1466 * width=4, hstride=0 of t2 during an ADD instruction.
1468 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1475 fs_visitor::emit_samplemaskin_setup()
1477 assert(stage
== MESA_SHADER_FRAGMENT
);
1478 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1479 assert(devinfo
->gen
>= 6);
1481 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1483 fs_reg coverage_mask
=
1484 fetch_payload_reg(bld
, payload
.sample_mask_in_reg
, BRW_REGISTER_TYPE_D
);
1486 if (wm_prog_data
->persample_dispatch
) {
1487 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1488 * and a mask representing which sample is being processed by the
1489 * current shader invocation.
1491 * From the OES_sample_variables specification:
1492 * "When per-sample shading is active due to the use of a fragment input
1493 * qualified by "sample" or due to the use of the gl_SampleID or
1494 * gl_SamplePosition variables, only the bit for the current sample is
1495 * set in gl_SampleMaskIn."
1497 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1499 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1500 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1502 fs_reg one
= vgrf(glsl_type::int_type
);
1503 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1504 abld
.MOV(one
, brw_imm_d(1));
1505 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1506 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1508 /* In per-pixel mode, the coverage mask is sufficient. */
1509 *reg
= coverage_mask
;
1515 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1517 if (!src
.abs
&& !src
.negate
)
1520 fs_reg temp
= bld
.vgrf(src
.type
);
1527 fs_visitor::emit_discard_jump()
1529 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1531 /* For performance, after a discard, jump to the end of the
1532 * shader if all relevant channels have been discarded.
1534 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1535 discard_jump
->flag_subreg
= sample_mask_flag_subreg(this);
1537 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1538 discard_jump
->predicate_inverse
= true;
1542 fs_visitor::emit_gs_thread_end()
1544 assert(stage
== MESA_SHADER_GEOMETRY
);
1546 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1548 if (gs_compile
->control_data_header_size_bits
> 0) {
1549 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1552 const fs_builder abld
= bld
.annotate("thread end");
1555 if (gs_prog_data
->static_vertex_count
!= -1) {
1556 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1557 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1558 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1559 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1560 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1563 /* Delete now dead instructions. */
1564 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1570 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1574 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1575 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1576 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1579 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1580 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1581 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1582 sources
[1] = this->final_gs_vertex_count
;
1583 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1584 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1592 fs_visitor::assign_curb_setup()
1594 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1596 unsigned ubo_push_length
= 0;
1597 unsigned ubo_push_start
[4];
1598 for (int i
= 0; i
< 4; i
++) {
1599 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1600 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1603 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1605 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1606 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1607 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1608 if (inst
->src
[i
].file
== UNIFORM
) {
1609 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1611 if (inst
->src
[i
].nr
>= UBO_START
) {
1612 /* constant_nr is in 32-bit units, the rest are in bytes */
1613 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1614 inst
->src
[i
].offset
/ 4;
1615 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1616 constant_nr
= push_constant_loc
[uniform_nr
];
1618 /* Section 5.11 of the OpenGL 4.1 spec says:
1619 * "Out-of-bounds reads return undefined values, which include
1620 * values from other variables of the active program or zero."
1621 * Just return the first push constant.
1626 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1629 brw_reg
.abs
= inst
->src
[i
].abs
;
1630 brw_reg
.negate
= inst
->src
[i
].negate
;
1632 assert(inst
->src
[i
].stride
== 0);
1633 inst
->src
[i
] = byte_offset(
1634 retype(brw_reg
, inst
->src
[i
].type
),
1635 inst
->src
[i
].offset
% 4);
1640 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1641 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1645 * Build up an array of indices into the urb_setup array that
1646 * references the active entries of the urb_setup array.
1647 * Used to accelerate walking the active entries of the urb_setup array
1651 brw_compute_urb_setup_index(struct brw_wm_prog_data
*wm_prog_data
)
1653 /* Make sure uint8_t is sufficient */
1654 STATIC_ASSERT(VARYING_SLOT_MAX
<= 0xff);
1656 for (uint8_t attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1657 if (wm_prog_data
->urb_setup
[attr
] >= 0) {
1658 wm_prog_data
->urb_setup_attribs
[index
++] = attr
;
1661 wm_prog_data
->urb_setup_attribs_count
= index
;
1665 calculate_urb_setup(const struct gen_device_info
*devinfo
,
1666 const struct brw_wm_prog_key
*key
,
1667 struct brw_wm_prog_data
*prog_data
,
1668 const nir_shader
*nir
)
1670 memset(prog_data
->urb_setup
, -1,
1671 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1674 /* Figure out where each of the incoming setup attributes lands. */
1675 if (devinfo
->gen
>= 6) {
1676 if (util_bitcount64(nir
->info
.inputs_read
&
1677 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1678 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1679 * first 16 varying inputs, so we can put them wherever we want.
1680 * Just put them in order.
1682 * This is useful because it means that (a) inputs not used by the
1683 * fragment shader won't take up valuable register space, and (b) we
1684 * won't have to recompile the fragment shader if it gets paired with
1685 * a different vertex (or geometry) shader.
1687 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1688 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1689 BITFIELD64_BIT(i
)) {
1690 prog_data
->urb_setup
[i
] = urb_next
++;
1694 /* We have enough input varyings that the SF/SBE pipeline stage can't
1695 * arbitrarily rearrange them to suit our whim; we have to put them
1696 * in an order that matches the output of the previous pipeline stage
1697 * (geometry or vertex shader).
1699 struct brw_vue_map prev_stage_vue_map
;
1700 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1701 key
->input_slots_valid
,
1702 nir
->info
.separate_shader
);
1705 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1706 &prev_stage_vue_map
);
1708 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1709 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1711 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1712 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1713 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1714 BITFIELD64_BIT(varying
))) {
1715 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1718 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1721 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1722 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1723 /* Point size is packed into the header, not as a general attribute */
1724 if (i
== VARYING_SLOT_PSIZ
)
1727 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1728 /* The back color slot is skipped when the front color is
1729 * also written to. In addition, some slots can be
1730 * written in the vertex shader and not read in the
1731 * fragment shader. So the register number must always be
1732 * incremented, mapped or not.
1734 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1735 prog_data
->urb_setup
[i
] = urb_next
;
1741 * It's a FS only attribute, and we did interpolation for this attribute
1742 * in SF thread. So, count it here, too.
1744 * See compile_sf_prog() for more info.
1746 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1747 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1750 prog_data
->num_varying_inputs
= urb_next
;
1752 brw_compute_urb_setup_index(prog_data
);
1756 fs_visitor::assign_urb_setup()
1758 assert(stage
== MESA_SHADER_FRAGMENT
);
1759 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1761 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1763 /* Offset all the urb_setup[] index by the actual position of the
1764 * setup regs, now that the location of the constants has been chosen.
1766 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1767 for (int i
= 0; i
< inst
->sources
; i
++) {
1768 if (inst
->src
[i
].file
== ATTR
) {
1769 /* ATTR regs in the FS are in units of logical scalar inputs each
1770 * of which consumes half of a GRF register.
1772 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1773 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1774 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1775 inst
->src
[i
].offset
;
1776 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1777 1 : MIN2(inst
->exec_size
, 8);
1778 struct brw_reg reg
= stride(
1779 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1781 width
* inst
->src
[i
].stride
,
1782 width
, inst
->src
[i
].stride
);
1783 reg
.abs
= inst
->src
[i
].abs
;
1784 reg
.negate
= inst
->src
[i
].negate
;
1790 /* Each attribute is 4 setup channels, each of which is half a reg. */
1791 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1795 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1797 for (int i
= 0; i
< inst
->sources
; i
++) {
1798 if (inst
->src
[i
].file
== ATTR
) {
1799 int grf
= payload
.num_regs
+
1800 prog_data
->curb_read_length
+
1802 inst
->src
[i
].offset
/ REG_SIZE
;
1804 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1806 * VertStride must be used to cross GRF register boundaries. This
1807 * rule implies that elements within a 'Width' cannot cross GRF
1810 * So, for registers that are large enough, we have to split the exec
1811 * size in two and trust the compression state to sort it out.
1813 unsigned total_size
= inst
->exec_size
*
1814 inst
->src
[i
].stride
*
1815 type_sz(inst
->src
[i
].type
);
1817 assert(total_size
<= 2 * REG_SIZE
);
1818 const unsigned exec_size
=
1819 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1821 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1822 struct brw_reg reg
=
1823 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1824 inst
->src
[i
].offset
% REG_SIZE
),
1825 exec_size
* inst
->src
[i
].stride
,
1826 width
, inst
->src
[i
].stride
);
1827 reg
.abs
= inst
->src
[i
].abs
;
1828 reg
.negate
= inst
->src
[i
].negate
;
1836 fs_visitor::assign_vs_urb_setup()
1838 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1840 assert(stage
== MESA_SHADER_VERTEX
);
1842 /* Each attribute is 4 regs. */
1843 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1845 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1847 /* Rewrite all ATTR file references to the hw grf that they land in. */
1848 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1849 convert_attr_sources_to_hw_regs(inst
);
1854 fs_visitor::assign_tcs_urb_setup()
1856 assert(stage
== MESA_SHADER_TESS_CTRL
);
1858 /* Rewrite all ATTR file references to HW_REGs. */
1859 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1860 convert_attr_sources_to_hw_regs(inst
);
1865 fs_visitor::assign_tes_urb_setup()
1867 assert(stage
== MESA_SHADER_TESS_EVAL
);
1869 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1871 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1873 /* Rewrite all ATTR file references to HW_REGs. */
1874 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1875 convert_attr_sources_to_hw_regs(inst
);
1880 fs_visitor::assign_gs_urb_setup()
1882 assert(stage
== MESA_SHADER_GEOMETRY
);
1884 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1886 first_non_payload_grf
+=
1887 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1889 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1890 /* Rewrite all ATTR file references to GRFs. */
1891 convert_attr_sources_to_hw_regs(inst
);
1897 * Split large virtual GRFs into separate components if we can.
1899 * This is mostly duplicated with what brw_fs_vector_splitting does,
1900 * but that's really conservative because it's afraid of doing
1901 * splitting that doesn't result in real progress after the rest of
1902 * the optimization phases, which would cause infinite looping in
1903 * optimization. We can do it once here, safely. This also has the
1904 * opportunity to split interpolated values, or maybe even uniforms,
1905 * which we don't have at the IR level.
1907 * We want to split, because virtual GRFs are what we register
1908 * allocate and spill (due to contiguousness requirements for some
1909 * instructions), and they're what we naturally generate in the
1910 * codegen process, but most virtual GRFs don't actually need to be
1911 * contiguous sets of GRFs. If we split, we'll end up with reduced
1912 * live intervals and better dead code elimination and coalescing.
1915 fs_visitor::split_virtual_grfs()
1917 /* Compact the register file so we eliminate dead vgrfs. This
1918 * only defines split points for live registers, so if we have
1919 * too large dead registers they will hit assertions later.
1921 compact_virtual_grfs();
1923 int num_vars
= this->alloc
.count
;
1925 /* Count the total number of registers */
1927 int vgrf_to_reg
[num_vars
];
1928 for (int i
= 0; i
< num_vars
; i
++) {
1929 vgrf_to_reg
[i
] = reg_count
;
1930 reg_count
+= alloc
.sizes
[i
];
1933 /* An array of "split points". For each register slot, this indicates
1934 * if this slot can be separated from the previous slot. Every time an
1935 * instruction uses multiple elements of a register (as a source or
1936 * destination), we mark the used slots as inseparable. Then we go
1937 * through and split the registers into the smallest pieces we can.
1939 bool *split_points
= new bool[reg_count
];
1940 memset(split_points
, 0, reg_count
* sizeof(*split_points
));
1942 /* Mark all used registers as fully splittable */
1943 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1944 if (inst
->dst
.file
== VGRF
) {
1945 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1946 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1947 split_points
[reg
+ j
] = true;
1950 for (int i
= 0; i
< inst
->sources
; i
++) {
1951 if (inst
->src
[i
].file
== VGRF
) {
1952 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1953 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1954 split_points
[reg
+ j
] = true;
1959 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1960 /* We fix up undef instructions later */
1961 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
1962 /* UNDEF instructions are currently only used to undef entire
1963 * registers. We need this invariant later when we split them.
1965 assert(inst
->dst
.file
== VGRF
);
1966 assert(inst
->dst
.offset
== 0);
1967 assert(inst
->size_written
== alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
);
1971 if (inst
->dst
.file
== VGRF
) {
1972 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
1973 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
1974 split_points
[reg
+ j
] = false;
1976 for (int i
= 0; i
< inst
->sources
; i
++) {
1977 if (inst
->src
[i
].file
== VGRF
) {
1978 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
1979 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
1980 split_points
[reg
+ j
] = false;
1985 int *new_virtual_grf
= new int[reg_count
];
1986 int *new_reg_offset
= new int[reg_count
];
1989 for (int i
= 0; i
< num_vars
; i
++) {
1990 /* The first one should always be 0 as a quick sanity check. */
1991 assert(split_points
[reg
] == false);
1994 new_reg_offset
[reg
] = 0;
1999 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
2000 /* If this is a split point, reset the offset to 0 and allocate a
2001 * new virtual GRF for the previous offset many registers
2003 if (split_points
[reg
]) {
2004 assert(offset
<= MAX_VGRF_SIZE
);
2005 int grf
= alloc
.allocate(offset
);
2006 for (int k
= reg
- offset
; k
< reg
; k
++)
2007 new_virtual_grf
[k
] = grf
;
2010 new_reg_offset
[reg
] = offset
;
2015 /* The last one gets the original register number */
2016 assert(offset
<= MAX_VGRF_SIZE
);
2017 alloc
.sizes
[i
] = offset
;
2018 for (int k
= reg
- offset
; k
< reg
; k
++)
2019 new_virtual_grf
[k
] = i
;
2021 assert(reg
== reg_count
);
2023 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2024 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2025 const fs_builder
ibld(this, block
, inst
);
2026 assert(inst
->size_written
% REG_SIZE
== 0);
2027 unsigned reg_offset
= 0;
2028 while (reg_offset
< inst
->size_written
/ REG_SIZE
) {
2029 reg
= vgrf_to_reg
[inst
->dst
.nr
] + reg_offset
;
2030 ibld
.UNDEF(fs_reg(VGRF
, new_virtual_grf
[reg
], inst
->dst
.type
));
2031 reg_offset
+= alloc
.sizes
[new_virtual_grf
[reg
]];
2033 inst
->remove(block
);
2037 if (inst
->dst
.file
== VGRF
) {
2038 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2039 inst
->dst
.nr
= new_virtual_grf
[reg
];
2040 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
2041 inst
->dst
.offset
% REG_SIZE
;
2042 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2044 for (int i
= 0; i
< inst
->sources
; i
++) {
2045 if (inst
->src
[i
].file
== VGRF
) {
2046 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2047 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
2048 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
2049 inst
->src
[i
].offset
% REG_SIZE
;
2050 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2054 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
| DEPENDENCY_VARIABLES
);
2056 delete[] split_points
;
2057 delete[] new_virtual_grf
;
2058 delete[] new_reg_offset
;
2062 * Remove unused virtual GRFs and compact the vgrf_* arrays.
2064 * During code generation, we create tons of temporary variables, many of
2065 * which get immediately killed and are never used again. Yet, in later
2066 * optimization and analysis passes, such as compute_live_intervals, we need
2067 * to loop over all the virtual GRFs. Compacting them can save a lot of
2071 fs_visitor::compact_virtual_grfs()
2073 bool progress
= false;
2074 int *remap_table
= new int[this->alloc
.count
];
2075 memset(remap_table
, -1, this->alloc
.count
* sizeof(int));
2077 /* Mark which virtual GRFs are used. */
2078 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2079 if (inst
->dst
.file
== VGRF
)
2080 remap_table
[inst
->dst
.nr
] = 0;
2082 for (int i
= 0; i
< inst
->sources
; i
++) {
2083 if (inst
->src
[i
].file
== VGRF
)
2084 remap_table
[inst
->src
[i
].nr
] = 0;
2088 /* Compact the GRF arrays. */
2090 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2091 if (remap_table
[i
] == -1) {
2092 /* We just found an unused register. This means that we are
2093 * actually going to compact something.
2097 remap_table
[i
] = new_index
;
2098 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2099 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
| DEPENDENCY_VARIABLES
);
2104 this->alloc
.count
= new_index
;
2106 /* Patch all the instructions to use the newly renumbered registers */
2107 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2108 if (inst
->dst
.file
== VGRF
)
2109 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
2111 for (int i
= 0; i
< inst
->sources
; i
++) {
2112 if (inst
->src
[i
].file
== VGRF
)
2113 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
2117 /* Patch all the references to delta_xy, since they're used in register
2118 * allocation. If they're unused, switch them to BAD_FILE so we don't
2119 * think some random VGRF is delta_xy.
2121 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2122 if (delta_xy
[i
].file
== VGRF
) {
2123 if (remap_table
[delta_xy
[i
].nr
] != -1) {
2124 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2126 delta_xy
[i
].file
= BAD_FILE
;
2131 delete[] remap_table
;
2137 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
2139 if (prog_data
->nr_params
== 0)
2142 /* The local thread id is always the last parameter in the list */
2143 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
2144 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
2145 return prog_data
->nr_params
- 1;
2151 * Struct for handling complex alignments.
2153 * A complex alignment is stored as multiplier and an offset. A value is
2154 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
2155 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
2158 * N | cplx_align_apply({8, 2}, N)
2159 * ----+-----------------------------
2173 #define CPLX_ALIGN_MAX_MUL 8
2176 cplx_align_assert_sane(struct cplx_align a
)
2178 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
2179 assert(a
.offset
< a
.mul
);
2183 * Combines two alignments to produce a least multiple of sorts.
2185 * The returned alignment is the smallest (in terms of multiplier) such that
2186 * anything aligned to both a and b will be aligned to the new alignment.
2187 * This function will assert-fail if a and b are not compatible, i.e. if the
2188 * offset parameters are such that no common alignment is possible.
2190 static struct cplx_align
2191 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2193 cplx_align_assert_sane(a
);
2194 cplx_align_assert_sane(b
);
2196 /* Assert that the alignments agree. */
2197 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2199 return a
.mul
> b
.mul
? a
: b
;
2203 * Apply a complex alignment
2205 * This function will return the smallest number greater than or equal to
2206 * offset that is aligned to align.
2209 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2211 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2214 #define UNIFORM_SLOT_SIZE 4
2216 struct uniform_slot_info
{
2217 /** True if the given uniform slot is live */
2220 /** True if this slot and the next slot must remain contiguous */
2221 unsigned contiguous
:1;
2223 struct cplx_align align
;
2227 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2228 unsigned num_slots
, unsigned alignment
)
2230 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2231 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2233 /* We can't align a slot to anything less than the slot size */
2234 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2236 struct cplx_align align
= {alignment
, 0};
2237 cplx_align_assert_sane(align
);
2239 for (unsigned i
= 0; i
< num_slots
; i
++) {
2240 slots
[i
].is_live
= true;
2241 if (i
< num_slots
- 1)
2242 slots
[i
].contiguous
= true;
2244 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2245 if (slots
[i
].align
.mul
== 0) {
2246 slots
[i
].align
= align
;
2248 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2254 * Assign UNIFORM file registers to either push constants or pull constants.
2256 * We allow a fragment shader to have more than the specified minimum
2257 * maximum number of fragment shader uniform components (64). If
2258 * there are too many of these, they'd fill up all of register space.
2259 * So, this will push some of them out to the pull constant buffer and
2260 * update the program to load them.
2263 fs_visitor::assign_constant_locations()
2265 /* Only the first compile gets to decide on locations. */
2266 if (push_constant_loc
) {
2267 assert(pull_constant_loc
);
2271 if (compiler
->compact_params
) {
2272 struct uniform_slot_info slots
[uniforms
+ 1];
2273 memset(slots
, 0, sizeof(slots
));
2275 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2276 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2277 if (inst
->src
[i
].file
!= UNIFORM
)
2280 /* NIR tightly packs things so the uniform number might not be
2281 * aligned (if we have a double right after a float, for
2282 * instance). This is fine because the process of re-arranging
2283 * them will ensure that things are properly aligned. The offset
2284 * into that uniform, however, must be aligned.
2286 * In Vulkan, we have explicit offsets but everything is crammed
2287 * into a single "variable" so inst->src[i].nr will always be 0.
2288 * Everything will be properly aligned relative to that one base.
2290 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2292 unsigned u
= inst
->src
[i
].nr
+
2293 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2298 unsigned slots_read
;
2299 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2300 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2302 unsigned bytes_read
= inst
->components_read(i
) *
2303 type_sz(inst
->src
[i
].type
);
2304 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2307 assert(u
+ slots_read
<= uniforms
);
2308 mark_uniform_slots_read(&slots
[u
], slots_read
,
2309 type_sz(inst
->src
[i
].type
));
2313 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2315 /* Only allow 16 registers (128 uniform components) as push constants.
2317 * Just demote the end of the list. We could probably do better
2318 * here, demoting things that are rarely used in the program first.
2320 * If changing this value, note the limitation about total_regs in
2323 unsigned int max_push_components
= 16 * 8;
2324 if (subgroup_id_index
>= 0)
2325 max_push_components
--; /* Save a slot for the thread ID */
2327 /* We push small arrays, but no bigger than 16 floats. This is big
2328 * enough for a vec4 but hopefully not large enough to push out other
2329 * stuff. We should probably use a better heuristic at some point.
2331 const unsigned int max_chunk_size
= 16;
2333 unsigned int num_push_constants
= 0;
2334 unsigned int num_pull_constants
= 0;
2336 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2337 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2339 /* Default to -1 meaning no location */
2340 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2341 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2343 int chunk_start
= -1;
2344 struct cplx_align align
;
2345 for (unsigned u
= 0; u
< uniforms
; u
++) {
2346 if (!slots
[u
].is_live
) {
2347 assert(chunk_start
== -1);
2351 /* Skip subgroup_id_index to put it in the last push register. */
2352 if (subgroup_id_index
== (int)u
)
2355 if (chunk_start
== -1) {
2357 align
= slots
[u
].align
;
2359 /* Offset into the chunk */
2360 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2362 /* Shift the slot alignment down by the chunk offset so it is
2363 * comparable with the base chunk alignment.
2365 struct cplx_align slot_align
= slots
[u
].align
;
2367 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2369 align
= cplx_align_combine(align
, slot_align
);
2372 /* Sanity check the alignment */
2373 cplx_align_assert_sane(align
);
2375 if (slots
[u
].contiguous
)
2378 /* Adjust the alignment to be in terms of slots, not bytes */
2379 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2380 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2381 align
.mul
/= UNIFORM_SLOT_SIZE
;
2382 align
.offset
/= UNIFORM_SLOT_SIZE
;
2384 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2385 unsigned chunk_size
= u
- chunk_start
+ 1;
2386 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2387 (chunk_size
< max_chunk_size
&&
2388 push_start_align
+ chunk_size
<= max_push_components
)) {
2389 /* Align up the number of push constants */
2390 num_push_constants
= push_start_align
;
2391 for (unsigned i
= 0; i
< chunk_size
; i
++)
2392 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2394 /* We need to pull this one */
2395 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2396 for (unsigned i
= 0; i
< chunk_size
; i
++)
2397 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2400 /* Reset the chunk and start again */
2404 /* Add the CS local thread ID uniform at the end of the push constants */
2405 if (subgroup_id_index
>= 0)
2406 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2408 /* As the uniforms are going to be reordered, stash the old array and
2409 * create two new arrays for push/pull params.
2411 uint32_t *param
= stage_prog_data
->param
;
2412 stage_prog_data
->nr_params
= num_push_constants
;
2413 if (num_push_constants
) {
2414 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2415 num_push_constants
);
2417 stage_prog_data
->param
= NULL
;
2419 assert(stage_prog_data
->nr_pull_params
== 0);
2420 assert(stage_prog_data
->pull_param
== NULL
);
2421 if (num_pull_constants
> 0) {
2422 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2423 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2424 num_pull_constants
);
2427 /* Up until now, the param[] array has been indexed by reg + offset
2428 * of UNIFORM registers. Move pull constants into pull_param[] and
2429 * condense param[] to only contain the uniforms we chose to push.
2431 * NOTE: Because we are condensing the params[] array, we know that
2432 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2433 * having to make a copy.
2435 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2436 uint32_t value
= param
[i
];
2437 if (pull_constant_loc
[i
] != -1) {
2438 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2439 } else if (push_constant_loc
[i
] != -1) {
2440 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2445 /* If we don't want to compact anything, just set up dummy push/pull
2446 * arrays. All the rest of the compiler cares about are these arrays.
2448 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2449 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2451 for (unsigned u
= 0; u
< uniforms
; u
++)
2452 push_constant_loc
[u
] = u
;
2454 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2457 /* Now that we know how many regular uniforms we'll push, reduce the
2458 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2460 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2461 for (int i
= 0; i
< 4; i
++) {
2462 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2464 if (push_length
+ range
->length
> 64)
2465 range
->length
= 64 - push_length
;
2467 push_length
+= range
->length
;
2469 assert(push_length
<= 64);
2473 fs_visitor::get_pull_locs(const fs_reg
&src
,
2474 unsigned *out_surf_index
,
2475 unsigned *out_pull_index
)
2477 assert(src
.file
== UNIFORM
);
2479 if (src
.nr
>= UBO_START
) {
2480 const struct brw_ubo_range
*range
=
2481 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2483 /* If this access is in our (reduced) range, use the push data. */
2484 if (src
.offset
/ 32 < range
->length
)
2487 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2488 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2490 prog_data
->has_ubo_pull
= true;
2494 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2496 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2497 /* A regular uniform push constant */
2498 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2499 *out_pull_index
= pull_constant_loc
[location
];
2501 prog_data
->has_ubo_pull
= true;
2509 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2510 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2513 fs_visitor::lower_constant_loads()
2515 unsigned index
, pull_index
;
2517 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2518 /* Set up the annotation tracking for new generated instructions. */
2519 const fs_builder
ibld(this, block
, inst
);
2521 for (int i
= 0; i
< inst
->sources
; i
++) {
2522 if (inst
->src
[i
].file
!= UNIFORM
)
2525 /* We'll handle this case later */
2526 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2529 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2532 assert(inst
->src
[i
].stride
== 0);
2534 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2535 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2536 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2537 const unsigned base
= pull_index
* 4;
2539 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2540 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2542 /* Rewrite the instruction to use the temporary VGRF. */
2543 inst
->src
[i
].file
= VGRF
;
2544 inst
->src
[i
].nr
= dst
.nr
;
2545 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2546 inst
->src
[i
].offset
% 4;
2549 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2550 inst
->src
[0].file
== UNIFORM
) {
2552 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2555 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2559 inst
->remove(block
);
2562 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
2566 fs_visitor::opt_algebraic()
2568 bool progress
= false;
2570 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2571 switch (inst
->opcode
) {
2572 case BRW_OPCODE_MOV
:
2573 if (!devinfo
->has_64bit_float
&&
2574 !devinfo
->has_64bit_int
&&
2575 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2576 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2577 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2578 assert(inst
->dst
.type
== inst
->src
[0].type
);
2579 assert(!inst
->saturate
);
2580 assert(!inst
->src
[0].abs
);
2581 assert(!inst
->src
[0].negate
);
2582 const brw::fs_builder
ibld(this, block
, inst
);
2584 if (inst
->src
[0].file
== IMM
) {
2585 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2586 brw_imm_ud(inst
->src
[0].u64
>> 32));
2587 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2588 brw_imm_ud(inst
->src
[0].u64
));
2590 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2591 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1));
2592 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2593 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0));
2596 inst
->remove(block
);
2600 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2601 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2602 inst
->dst
.is_null() &&
2603 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2604 inst
->src
[0].abs
= false;
2605 inst
->src
[0].negate
= false;
2610 if (inst
->src
[0].file
!= IMM
)
2613 if (inst
->saturate
) {
2614 /* Full mixed-type saturates don't happen. However, we can end up
2617 * mov.sat(8) g21<1>DF -1F
2619 * Other mixed-size-but-same-base-type cases may also be possible.
2621 if (inst
->dst
.type
!= inst
->src
[0].type
&&
2622 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
2623 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2624 assert(!"unimplemented: saturate mixed types");
2626 if (brw_saturate_immediate(inst
->src
[0].type
,
2627 &inst
->src
[0].as_brw_reg())) {
2628 inst
->saturate
= false;
2634 case BRW_OPCODE_MUL
:
2635 if (inst
->src
[1].file
!= IMM
)
2639 if (inst
->src
[1].is_one()) {
2640 inst
->opcode
= BRW_OPCODE_MOV
;
2641 inst
->src
[1] = reg_undef
;
2647 if (inst
->src
[1].is_negative_one()) {
2648 inst
->opcode
= BRW_OPCODE_MOV
;
2649 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2650 inst
->src
[1] = reg_undef
;
2655 if (inst
->src
[0].file
== IMM
) {
2656 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2657 inst
->opcode
= BRW_OPCODE_MOV
;
2658 inst
->src
[0].f
*= inst
->src
[1].f
;
2659 inst
->src
[1] = reg_undef
;
2664 case BRW_OPCODE_ADD
:
2665 if (inst
->src
[1].file
!= IMM
)
2668 if (inst
->src
[0].file
== IMM
) {
2669 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2670 inst
->opcode
= BRW_OPCODE_MOV
;
2671 inst
->src
[0].f
+= inst
->src
[1].f
;
2672 inst
->src
[1] = reg_undef
;
2678 if (inst
->src
[0].equals(inst
->src
[1]) ||
2679 inst
->src
[1].is_zero()) {
2680 /* On Gen8+, the OR instruction can have a source modifier that
2681 * performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
2682 * or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
2684 if (inst
->src
[0].negate
) {
2685 inst
->opcode
= BRW_OPCODE_NOT
;
2686 inst
->src
[0].negate
= false;
2688 inst
->opcode
= BRW_OPCODE_MOV
;
2690 inst
->src
[1] = reg_undef
;
2695 case BRW_OPCODE_CMP
:
2696 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2697 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2698 inst
->src
[1].is_zero() &&
2699 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2700 inst
->src
[0].abs
= false;
2701 inst
->src
[0].negate
= false;
2706 case BRW_OPCODE_SEL
:
2707 if (!devinfo
->has_64bit_float
&&
2708 !devinfo
->has_64bit_int
&&
2709 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2710 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2711 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2712 assert(inst
->dst
.type
== inst
->src
[0].type
);
2713 assert(!inst
->saturate
);
2714 assert(!inst
->src
[0].abs
&& !inst
->src
[0].negate
);
2715 assert(!inst
->src
[1].abs
&& !inst
->src
[1].negate
);
2716 const brw::fs_builder
ibld(this, block
, inst
);
2718 set_predicate(inst
->predicate
,
2719 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2720 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
2721 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0)));
2722 set_predicate(inst
->predicate
,
2723 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2724 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
2725 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1)));
2727 inst
->remove(block
);
2730 if (inst
->src
[0].equals(inst
->src
[1])) {
2731 inst
->opcode
= BRW_OPCODE_MOV
;
2732 inst
->src
[1] = reg_undef
;
2733 inst
->predicate
= BRW_PREDICATE_NONE
;
2734 inst
->predicate_inverse
= false;
2736 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2737 switch (inst
->conditional_mod
) {
2738 case BRW_CONDITIONAL_LE
:
2739 case BRW_CONDITIONAL_L
:
2740 switch (inst
->src
[1].type
) {
2741 case BRW_REGISTER_TYPE_F
:
2742 if (inst
->src
[1].f
>= 1.0f
) {
2743 inst
->opcode
= BRW_OPCODE_MOV
;
2744 inst
->src
[1] = reg_undef
;
2745 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2753 case BRW_CONDITIONAL_GE
:
2754 case BRW_CONDITIONAL_G
:
2755 switch (inst
->src
[1].type
) {
2756 case BRW_REGISTER_TYPE_F
:
2757 if (inst
->src
[1].f
<= 0.0f
) {
2758 inst
->opcode
= BRW_OPCODE_MOV
;
2759 inst
->src
[1] = reg_undef
;
2760 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2772 case BRW_OPCODE_MAD
:
2773 if (inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
2774 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
2775 inst
->src
[2].type
!= BRW_REGISTER_TYPE_F
)
2777 if (inst
->src
[1].is_one()) {
2778 inst
->opcode
= BRW_OPCODE_ADD
;
2779 inst
->src
[1] = inst
->src
[2];
2780 inst
->src
[2] = reg_undef
;
2782 } else if (inst
->src
[2].is_one()) {
2783 inst
->opcode
= BRW_OPCODE_ADD
;
2784 inst
->src
[2] = reg_undef
;
2788 case SHADER_OPCODE_BROADCAST
:
2789 if (is_uniform(inst
->src
[0])) {
2790 inst
->opcode
= BRW_OPCODE_MOV
;
2792 inst
->force_writemask_all
= true;
2794 } else if (inst
->src
[1].file
== IMM
) {
2795 inst
->opcode
= BRW_OPCODE_MOV
;
2796 /* It's possible that the selected component will be too large and
2797 * overflow the register. This can happen if someone does a
2798 * readInvocation() from GLSL or SPIR-V and provides an OOB
2799 * invocationIndex. If this happens and we some how manage
2800 * to constant fold it in and get here, then component() may cause
2801 * us to start reading outside of the VGRF which will lead to an
2802 * assert later. Instead, just let it wrap around if it goes over
2805 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2806 inst
->src
[0] = component(inst
->src
[0], comp
);
2808 inst
->force_writemask_all
= true;
2813 case SHADER_OPCODE_SHUFFLE
:
2814 if (is_uniform(inst
->src
[0])) {
2815 inst
->opcode
= BRW_OPCODE_MOV
;
2818 } else if (inst
->src
[1].file
== IMM
) {
2819 inst
->opcode
= BRW_OPCODE_MOV
;
2820 inst
->src
[0] = component(inst
->src
[0],
2831 /* Swap if src[0] is immediate. */
2832 if (progress
&& inst
->is_commutative()) {
2833 if (inst
->src
[0].file
== IMM
) {
2834 fs_reg tmp
= inst
->src
[1];
2835 inst
->src
[1] = inst
->src
[0];
2842 invalidate_analysis(DEPENDENCY_INSTRUCTION_DATA_FLOW
|
2843 DEPENDENCY_INSTRUCTION_DETAIL
);
2849 * Optimize sample messages that have constant zero values for the trailing
2850 * texture coordinates. We can just reduce the message length for these
2851 * instructions instead of reserving a register for it. Trailing parameters
2852 * that aren't sent default to zero anyway. This will cause the dead code
2853 * eliminator to remove the MOV instruction that would otherwise be emitted to
2854 * set up the zero value.
2857 fs_visitor::opt_zero_samples()
2859 /* Gen4 infers the texturing opcode based on the message length so we can't
2862 if (devinfo
->gen
< 5)
2865 bool progress
= false;
2867 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2868 if (!inst
->is_tex())
2871 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2873 if (load_payload
->is_head_sentinel() ||
2874 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2877 /* We don't want to remove the message header or the first parameter.
2878 * Removing the first parameter is not allowed, see the Haswell PRM
2879 * volume 7, page 149:
2881 * "Parameter 0 is required except for the sampleinfo message, which
2882 * has no parameter 0"
2884 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2885 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2886 (inst
->exec_size
/ 8) +
2887 inst
->header_size
- 1].is_zero()) {
2888 inst
->mlen
-= inst
->exec_size
/ 8;
2894 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
);
2900 * Optimize sample messages which are followed by the final RT write.
2902 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2903 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2904 * final texturing results copied to the framebuffer write payload and modify
2905 * them to write to the framebuffer directly.
2908 fs_visitor::opt_sampler_eot()
2910 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2912 if (stage
!= MESA_SHADER_FRAGMENT
|| dispatch_width
> 16)
2915 if (devinfo
->gen
!= 9 && !devinfo
->is_cherryview
)
2918 /* FINISHME: It should be possible to implement this optimization when there
2919 * are multiple drawbuffers.
2921 if (key
->nr_color_regions
!= 1)
2924 /* Requires emitting a bunch of saturating MOV instructions during logical
2925 * send lowering to clamp the color payload, which the sampler unit isn't
2926 * going to do for us.
2928 if (key
->clamp_fragment_color
)
2931 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2932 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2933 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2934 assert(fb_write
->eot
);
2935 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2937 /* There wasn't one; nothing to do. */
2938 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2941 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2943 /* 3D Sampler » Messages » Message Format
2945 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2946 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2948 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2949 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2950 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2951 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2952 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2953 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2954 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2955 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2958 /* XXX - This shouldn't be necessary. */
2959 if (tex_inst
->prev
->is_head_sentinel())
2962 /* Check that the FB write sources are fully initialized by the single
2963 * texturing instruction.
2965 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2966 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2967 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2968 fb_write
->size_read(i
) != tex_inst
->size_written
)
2970 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2971 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2976 assert(!tex_inst
->eot
); /* We can't get here twice */
2977 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2979 const fs_builder
ibld(this, block
, tex_inst
);
2981 tex_inst
->offset
|= fb_write
->target
<< 24;
2982 tex_inst
->eot
= true;
2983 tex_inst
->dst
= ibld
.null_reg_ud();
2984 tex_inst
->size_written
= 0;
2985 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2987 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2988 * flag and submit a header together with the sampler message as required
2991 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
2996 fs_visitor::opt_register_renaming()
2998 bool progress
= false;
3001 unsigned remap
[alloc
.count
];
3002 memset(remap
, ~0u, sizeof(unsigned) * alloc
.count
);
3004 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3005 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
3007 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
3008 inst
->opcode
== BRW_OPCODE_WHILE
) {
3012 /* Rewrite instruction sources. */
3013 for (int i
= 0; i
< inst
->sources
; i
++) {
3014 if (inst
->src
[i
].file
== VGRF
&&
3015 remap
[inst
->src
[i
].nr
] != ~0u &&
3016 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
3017 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
3022 const unsigned dst
= inst
->dst
.nr
;
3025 inst
->dst
.file
== VGRF
&&
3026 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
3027 !inst
->is_partial_write()) {
3028 if (remap
[dst
] == ~0u) {
3031 remap
[dst
] = alloc
.allocate(regs_written(inst
));
3032 inst
->dst
.nr
= remap
[dst
];
3035 } else if (inst
->dst
.file
== VGRF
&&
3036 remap
[dst
] != ~0u &&
3037 remap
[dst
] != dst
) {
3038 inst
->dst
.nr
= remap
[dst
];
3044 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
|
3045 DEPENDENCY_VARIABLES
);
3047 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
3048 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != ~0u) {
3049 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
3058 * Remove redundant or useless discard jumps.
3060 * For example, we can eliminate jumps in the following sequence:
3062 * discard-jump (redundant with the next jump)
3063 * discard-jump (useless; jumps to the next instruction)
3067 fs_visitor::opt_redundant_discard_jumps()
3069 bool progress
= false;
3071 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
3073 fs_inst
*placeholder_halt
= NULL
;
3074 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
3075 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
3076 placeholder_halt
= inst
;
3081 if (!placeholder_halt
)
3084 /* Delete any HALTs immediately before the placeholder halt. */
3085 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
3086 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
3087 prev
= (fs_inst
*) placeholder_halt
->prev
) {
3088 prev
->remove(last_bblock
);
3093 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3099 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
3100 * from \p r.offset which overlaps the region starting at \p s.offset and
3101 * spanning \p ds bytes.
3103 static inline unsigned
3104 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
3106 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
3107 const int shift
= rel_offset
/ REG_SIZE
;
3108 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
3109 assert(reg_space(r
) == reg_space(s
) &&
3110 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
3111 return ((1 << n
) - 1) << shift
;
3115 fs_visitor::compute_to_mrf()
3117 bool progress
= false;
3120 /* No MRFs on Gen >= 7. */
3121 if (devinfo
->gen
>= 7)
3124 const fs_live_variables
&live
= live_analysis
.require();
3126 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3130 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3131 inst
->is_partial_write() ||
3132 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
3133 inst
->dst
.type
!= inst
->src
[0].type
||
3134 inst
->src
[0].abs
|| inst
->src
[0].negate
||
3135 !inst
->src
[0].is_contiguous() ||
3136 inst
->src
[0].offset
% REG_SIZE
!= 0)
3139 /* Can't compute-to-MRF this GRF if someone else was going to
3142 if (live
.vgrf_end
[inst
->src
[0].nr
] > ip
)
3145 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3146 * things that computed the value of all GRFs of the source region. The
3147 * regs_left bitset keeps track of the registers we haven't yet found a
3148 * generating instruction for.
3150 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3152 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3153 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3154 inst
->src
[0], inst
->size_read(0))) {
3155 /* Found the last thing to write our reg we want to turn
3156 * into a compute-to-MRF.
3159 /* If this one instruction didn't populate all the
3160 * channels, bail. We might be able to rewrite everything
3161 * that writes that reg, but it would require smarter
3164 if (scan_inst
->is_partial_write())
3167 /* Handling things not fully contained in the source of the copy
3168 * would need us to understand coalescing out more than one MOV at
3171 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3172 inst
->src
[0], inst
->size_read(0)))
3175 /* SEND instructions can't have MRF as a destination. */
3176 if (scan_inst
->mlen
)
3179 if (devinfo
->gen
== 6) {
3180 /* gen6 math instructions must have the destination be
3181 * GRF, so no compute-to-MRF for them.
3183 if (scan_inst
->is_math()) {
3188 /* Clear the bits for any registers this instruction overwrites. */
3189 regs_left
&= ~mask_relative_to(
3190 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3195 /* We don't handle control flow here. Most computation of
3196 * values that end up in MRFs are shortly before the MRF
3199 if (block
->start() == scan_inst
)
3202 /* You can't read from an MRF, so if someone else reads our
3203 * MRF's source GRF that we wanted to rewrite, that stops us.
3205 bool interfered
= false;
3206 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3207 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3208 inst
->src
[0], inst
->size_read(0))) {
3215 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3216 inst
->dst
, inst
->size_written
)) {
3217 /* If somebody else writes our MRF here, we can't
3218 * compute-to-MRF before that.
3223 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3224 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3225 inst
->dst
, inst
->size_written
)) {
3226 /* Found a SEND instruction, which means that there are
3227 * live values in MRFs from base_mrf to base_mrf +
3228 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3238 /* Found all generating instructions of our MRF's source value, so it
3239 * should be safe to rewrite them to point to the MRF directly.
3241 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3243 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3244 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3245 inst
->src
[0], inst
->size_read(0))) {
3246 /* Clear the bits for any registers this instruction overwrites. */
3247 regs_left
&= ~mask_relative_to(
3248 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3250 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3251 reg_offset(inst
->src
[0]);
3253 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3254 /* Apply the same address transformation done by the hardware
3255 * for COMPR4 MRF writes.
3257 assert(rel_offset
< 2 * REG_SIZE
);
3258 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3260 /* Clear the COMPR4 bit if the generating instruction is not
3263 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3264 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3267 /* Calculate the MRF number the result of this instruction is
3268 * ultimately written to.
3270 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3273 scan_inst
->dst
.file
= MRF
;
3274 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3275 scan_inst
->saturate
|= inst
->saturate
;
3282 inst
->remove(block
);
3287 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3293 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3294 * flow. We could probably do better here with some form of divergence
3298 fs_visitor::eliminate_find_live_channel()
3300 bool progress
= false;
3303 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3304 /* The optimization below assumes that channel zero is live on thread
3305 * dispatch, which may not be the case if the fixed function dispatches
3311 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3312 switch (inst
->opcode
) {
3318 case BRW_OPCODE_ENDIF
:
3319 case BRW_OPCODE_WHILE
:
3323 case FS_OPCODE_DISCARD_JUMP
:
3324 /* This can potentially make control flow non-uniform until the end
3329 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3331 inst
->opcode
= BRW_OPCODE_MOV
;
3332 inst
->src
[0] = brw_imm_ud(0u);
3334 inst
->force_writemask_all
= true;
3345 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
);
3351 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3352 * instructions to FS_OPCODE_REP_FB_WRITE.
3355 fs_visitor::emit_repclear_shader()
3357 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3359 int color_mrf
= base_mrf
+ 2;
3363 mov
= bld
.exec_all().group(4, 0)
3364 .MOV(brw_message_reg(color_mrf
),
3365 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3367 struct brw_reg reg
=
3368 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3369 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3370 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3372 mov
= bld
.exec_all().group(4, 0)
3373 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3376 fs_inst
*write
= NULL
;
3377 if (key
->nr_color_regions
== 1) {
3378 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3379 write
->saturate
= key
->clamp_fragment_color
;
3380 write
->base_mrf
= color_mrf
;
3382 write
->header_size
= 0;
3385 assume(key
->nr_color_regions
> 0);
3387 struct brw_reg header
=
3388 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3389 bld
.exec_all().group(16, 0)
3390 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3392 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3394 bld
.exec_all().group(1, 0)
3395 .MOV(component(header
, 2), brw_imm_ud(i
));
3398 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3399 write
->saturate
= key
->clamp_fragment_color
;
3400 write
->base_mrf
= base_mrf
;
3402 write
->header_size
= 2;
3407 write
->last_rt
= true;
3411 assign_constant_locations();
3412 assign_curb_setup();
3414 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3416 assert(mov
->src
[0].file
== FIXED_GRF
);
3417 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3424 * Walks through basic blocks, looking for repeated MRF writes and
3425 * removing the later ones.
3428 fs_visitor::remove_duplicate_mrf_writes()
3430 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3431 bool progress
= false;
3433 /* Need to update the MRF tracking for compressed instructions. */
3434 if (dispatch_width
>= 16)
3437 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3439 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3440 if (inst
->is_control_flow()) {
3441 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3444 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3445 inst
->dst
.file
== MRF
) {
3446 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3447 if (prev_inst
&& prev_inst
->opcode
== BRW_OPCODE_MOV
&&
3448 inst
->dst
.equals(prev_inst
->dst
) &&
3449 inst
->src
[0].equals(prev_inst
->src
[0]) &&
3450 inst
->saturate
== prev_inst
->saturate
&&
3451 inst
->predicate
== prev_inst
->predicate
&&
3452 inst
->conditional_mod
== prev_inst
->conditional_mod
&&
3453 inst
->exec_size
== prev_inst
->exec_size
) {
3454 inst
->remove(block
);
3460 /* Clear out the last-write records for MRFs that were overwritten. */
3461 if (inst
->dst
.file
== MRF
) {
3462 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3465 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3466 /* Found a SEND instruction, which will include two or fewer
3467 * implied MRF writes. We could do better here.
3469 for (unsigned i
= 0; i
< inst
->implied_mrf_writes(); i
++) {
3470 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3474 /* Clear out any MRF move records whose sources got overwritten. */
3475 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3476 if (last_mrf_move
[i
] &&
3477 regions_overlap(inst
->dst
, inst
->size_written
,
3478 last_mrf_move
[i
]->src
[0],
3479 last_mrf_move
[i
]->size_read(0))) {
3480 last_mrf_move
[i
] = NULL
;
3484 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3485 inst
->dst
.file
== MRF
&&
3486 inst
->src
[0].file
!= ARF
&&
3487 !inst
->is_partial_write()) {
3488 last_mrf_move
[inst
->dst
.nr
] = inst
;
3493 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3499 * Rounding modes for conversion instructions are included for each
3500 * conversion, but right now it is a state. So once it is set,
3501 * we don't need to call it again for subsequent calls.
3503 * This is useful for vector/matrices conversions, as setting the
3504 * mode once is enough for the full vector/matrix
3507 fs_visitor::remove_extra_rounding_modes()
3509 bool progress
= false;
3510 unsigned execution_mode
= this->nir
->info
.float_controls_execution_mode
;
3512 brw_rnd_mode base_mode
= BRW_RND_MODE_UNSPECIFIED
;
3513 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
|
3514 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
|
3515 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
) &
3517 base_mode
= BRW_RND_MODE_RTNE
;
3518 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
|
3519 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
|
3520 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
) &
3522 base_mode
= BRW_RND_MODE_RTZ
;
3524 foreach_block (block
, cfg
) {
3525 brw_rnd_mode prev_mode
= base_mode
;
3527 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3528 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3529 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3530 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3531 if (mode
== prev_mode
) {
3532 inst
->remove(block
);
3542 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3548 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3550 /* Clear the flag for registers that actually got read (as expected). */
3551 for (int i
= 0; i
< inst
->sources
; i
++) {
3553 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3554 grf
= inst
->src
[i
].nr
;
3559 if (grf
>= first_grf
&&
3560 grf
< first_grf
+ grf_len
) {
3561 deps
[grf
- first_grf
] = false;
3562 if (inst
->exec_size
== 16)
3563 deps
[grf
- first_grf
+ 1] = false;
3569 * Implements this workaround for the original 965:
3571 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3572 * check for post destination dependencies on this instruction, software
3573 * must ensure that there is no destination hazard for the case of ‘write
3574 * followed by a posted write’ shown in the following example.
3577 * 2. send r3.xy <rest of send instruction>
3580 * Due to no post-destination dependency check on the ‘send’, the above
3581 * code sequence could have two instructions (1 and 2) in flight at the
3582 * same time that both consider ‘r3’ as the target of their final writes.
3585 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3588 int write_len
= regs_written(inst
);
3589 int first_write_grf
= inst
->dst
.nr
;
3590 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3591 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3593 memset(needs_dep
, false, sizeof(needs_dep
));
3594 memset(needs_dep
, true, write_len
);
3596 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3598 /* Walk backwards looking for writes to registers we're writing which
3599 * aren't read since being written. If we hit the start of the program,
3600 * we assume that there are no outstanding dependencies on entry to the
3603 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3604 /* If we hit control flow, assume that there *are* outstanding
3605 * dependencies, and force their cleanup before our instruction.
3607 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3608 for (int i
= 0; i
< write_len
; i
++) {
3610 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3611 first_write_grf
+ i
);
3616 /* We insert our reads as late as possible on the assumption that any
3617 * instruction but a MOV that might have left us an outstanding
3618 * dependency has more latency than a MOV.
3620 if (scan_inst
->dst
.file
== VGRF
) {
3621 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3622 int reg
= scan_inst
->dst
.nr
+ i
;
3624 if (reg
>= first_write_grf
&&
3625 reg
< first_write_grf
+ write_len
&&
3626 needs_dep
[reg
- first_write_grf
]) {
3627 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3628 needs_dep
[reg
- first_write_grf
] = false;
3629 if (scan_inst
->exec_size
== 16)
3630 needs_dep
[reg
- first_write_grf
+ 1] = false;
3635 /* Clear the flag for registers that actually got read (as expected). */
3636 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3638 /* Continue the loop only if we haven't resolved all the dependencies */
3640 for (i
= 0; i
< write_len
; i
++) {
3650 * Implements this workaround for the original 965:
3652 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3653 * used as a destination register until after it has been sourced by an
3654 * instruction with a different destination register.
3657 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3659 int write_len
= regs_written(inst
);
3660 unsigned first_write_grf
= inst
->dst
.nr
;
3661 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3662 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3664 memset(needs_dep
, false, sizeof(needs_dep
));
3665 memset(needs_dep
, true, write_len
);
3666 /* Walk forwards looking for writes to registers we're writing which aren't
3667 * read before being written.
3669 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3670 /* If we hit control flow, force resolve all remaining dependencies. */
3671 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3672 for (int i
= 0; i
< write_len
; i
++) {
3674 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3675 first_write_grf
+ i
);
3680 /* Clear the flag for registers that actually got read (as expected). */
3681 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3683 /* We insert our reads as late as possible since they're reading the
3684 * result of a SEND, which has massive latency.
3686 if (scan_inst
->dst
.file
== VGRF
&&
3687 scan_inst
->dst
.nr
>= first_write_grf
&&
3688 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3689 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3690 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3692 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3695 /* Continue the loop only if we haven't resolved all the dependencies */
3697 for (i
= 0; i
< write_len
; i
++) {
3707 fs_visitor::insert_gen4_send_dependency_workarounds()
3709 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3712 bool progress
= false;
3714 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3715 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3716 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3717 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3723 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3727 * Turns the generic expression-style uniform pull constant load instruction
3728 * into a hardware-specific series of instructions for loading a pull
3731 * The expression style allows the CSE pass before this to optimize out
3732 * repeated loads from the same offset, and gives the pre-register-allocation
3733 * scheduling full flexibility, while the conversion to native instructions
3734 * allows the post-register-allocation scheduler the best information
3737 * Note that execution masking for setting up pull constant loads is special:
3738 * the channels that need to be written are unrelated to the current execution
3739 * mask, since a later instruction will use one of the result channels as a
3740 * source operand for all 8 or 16 of its channels.
3743 fs_visitor::lower_uniform_pull_constant_loads()
3745 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3746 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3749 if (devinfo
->gen
>= 7) {
3750 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3751 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3753 ubld
.group(8, 0).MOV(payload
,
3754 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3755 ubld
.group(1, 0).MOV(component(payload
, 2),
3756 brw_imm_ud(inst
->src
[1].ud
/ 16));
3758 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3759 inst
->src
[1] = payload
;
3760 inst
->header_size
= 1;
3763 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
3765 /* Before register allocation, we didn't tell the scheduler about the
3766 * MRF we use. We know it's safe to use this MRF because nothing
3767 * else does except for register spill/unspill, which generates and
3768 * uses its MRF within a single IR instruction.
3770 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3777 fs_visitor::lower_load_payload()
3779 bool progress
= false;
3781 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3782 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3785 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3786 assert(inst
->saturate
== false);
3787 fs_reg dst
= inst
->dst
;
3789 /* Get rid of COMPR4. We'll add it back in if we need it */
3790 if (dst
.file
== MRF
)
3791 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3793 const fs_builder
ibld(this, block
, inst
);
3794 const fs_builder ubld
= ibld
.exec_all();
3796 for (uint8_t i
= 0; i
< inst
->header_size
;) {
3797 /* Number of header GRFs to initialize at once with a single MOV
3801 (i
+ 1 < inst
->header_size
&& inst
->src
[i
].stride
== 1 &&
3802 inst
->src
[i
+ 1].equals(byte_offset(inst
->src
[i
], REG_SIZE
))) ?
3805 if (inst
->src
[i
].file
!= BAD_FILE
)
3806 ubld
.group(8 * n
, 0).MOV(retype(dst
, BRW_REGISTER_TYPE_UD
),
3807 retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
));
3809 dst
= byte_offset(dst
, n
* REG_SIZE
);
3813 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3814 inst
->exec_size
> 8) {
3815 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3816 * a straightforward copy. Instead, the result of the
3817 * LOAD_PAYLOAD is treated as interleaved and the first four
3818 * non-header sources are unpacked as:
3829 * This is used for gen <= 5 fb writes.
3831 assert(inst
->exec_size
== 16);
3832 assert(inst
->header_size
+ 4 <= inst
->sources
);
3833 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3834 if (inst
->src
[i
].file
!= BAD_FILE
) {
3835 if (devinfo
->has_compr4
) {
3836 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3837 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3838 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3840 /* Platform doesn't have COMPR4. We have to fake it */
3841 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3842 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3844 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3851 /* The loop above only ever incremented us through the first set
3852 * of 4 registers. However, thanks to the magic of COMPR4, we
3853 * actually wrote to the first 8 registers, so we need to take
3854 * that into account now.
3858 /* The COMPR4 code took care of the first 4 sources. We'll let
3859 * the regular path handle any remaining sources. Yes, we are
3860 * modifying the instruction but we're about to delete it so
3861 * this really doesn't hurt anything.
3863 inst
->header_size
+= 4;
3866 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3867 if (inst
->src
[i
].file
!= BAD_FILE
) {
3868 dst
.type
= inst
->src
[i
].type
;
3869 ibld
.MOV(dst
, inst
->src
[i
]);
3871 dst
.type
= BRW_REGISTER_TYPE_UD
;
3873 dst
= offset(dst
, ibld
, 1);
3876 inst
->remove(block
);
3881 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3887 fs_visitor::lower_mul_dword_inst(fs_inst
*inst
, bblock_t
*block
)
3889 const fs_builder
ibld(this, block
, inst
);
3891 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3892 if (inst
->src
[1].file
== IMM
&&
3893 (( ud
&& inst
->src
[1].ud
<= UINT16_MAX
) ||
3894 (!ud
&& inst
->src
[1].d
<= INT16_MAX
&& inst
->src
[1].d
>= INT16_MIN
))) {
3895 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3896 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3899 * If multiplying by an immediate value that fits in 16-bits, do a
3900 * single MUL instruction with that value in the proper location.
3902 if (devinfo
->gen
< 7) {
3903 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8), inst
->dst
.type
);
3904 ibld
.MOV(imm
, inst
->src
[1]);
3905 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3907 ibld
.MUL(inst
->dst
, inst
->src
[0],
3908 ud
? brw_imm_uw(inst
->src
[1].ud
)
3909 : brw_imm_w(inst
->src
[1].d
));
3912 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3913 * do 32-bit integer multiplication in one instruction, but instead
3914 * must do a sequence (which actually calculates a 64-bit result):
3916 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3917 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3918 * mov(8) g2<1>D acc0<8,8,1>D
3920 * But on Gen > 6, the ability to use second accumulator register
3921 * (acc1) for non-float data types was removed, preventing a simple
3922 * implementation in SIMD16. A 16-channel result can be calculated by
3923 * executing the three instructions twice in SIMD8, once with quarter
3924 * control of 1Q for the first eight channels and again with 2Q for
3925 * the second eight channels.
3927 * Which accumulator register is implicitly accessed (by AccWrEnable
3928 * for instance) is determined by the quarter control. Unfortunately
3929 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3930 * implicit accumulator access by an instruction with 2Q will access
3931 * acc1 regardless of whether the data type is usable in acc1.
3933 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3934 * integer data types.
3936 * Since we only want the low 32-bits of the result, we can do two
3937 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3938 * adjust the high result and add them (like the mach is doing):
3940 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3941 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3942 * shl(8) g9<1>D g8<8,8,1>D 16D
3943 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3945 * We avoid the shl instruction by realizing that we only want to add
3946 * the low 16-bits of the "high" result to the high 16-bits of the
3947 * "low" result and using proper regioning on the add:
3949 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3950 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3951 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3953 * Since it does not use the (single) accumulator register, we can
3954 * schedule multi-component multiplications much better.
3957 bool needs_mov
= false;
3958 fs_reg orig_dst
= inst
->dst
;
3960 /* Get a new VGRF for the "low" 32x16-bit multiplication result if
3961 * reusing the original destination is impossible due to hardware
3962 * restrictions, source/destination overlap, or it being the null
3965 fs_reg low
= inst
->dst
;
3966 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3967 regions_overlap(inst
->dst
, inst
->size_written
,
3968 inst
->src
[0], inst
->size_read(0)) ||
3969 regions_overlap(inst
->dst
, inst
->size_written
,
3970 inst
->src
[1], inst
->size_read(1)) ||
3971 inst
->dst
.stride
>= 4) {
3973 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
3977 /* Get a new VGRF but keep the same stride as inst->dst */
3978 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)), inst
->dst
.type
);
3979 high
.stride
= inst
->dst
.stride
;
3980 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
3982 if (devinfo
->gen
>= 7) {
3983 if (inst
->src
[1].abs
)
3984 lower_src_modifiers(this, block
, inst
, 1);
3986 if (inst
->src
[1].file
== IMM
) {
3987 ibld
.MUL(low
, inst
->src
[0],
3988 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3989 ibld
.MUL(high
, inst
->src
[0],
3990 brw_imm_uw(inst
->src
[1].ud
>> 16));
3992 ibld
.MUL(low
, inst
->src
[0],
3993 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3994 ibld
.MUL(high
, inst
->src
[0],
3995 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3998 if (inst
->src
[0].abs
)
3999 lower_src_modifiers(this, block
, inst
, 0);
4001 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
4003 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
4007 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
4008 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
4009 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
4011 if (needs_mov
|| inst
->conditional_mod
)
4012 set_condmod(inst
->conditional_mod
, ibld
.MOV(orig_dst
, low
));
4017 fs_visitor::lower_mul_qword_inst(fs_inst
*inst
, bblock_t
*block
)
4019 const fs_builder
ibld(this, block
, inst
);
4021 /* Considering two 64-bit integers ab and cd where each letter ab
4022 * corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd
4023 * only need to provide the YZ part of the result. -------
4025 * Only BD needs to be 64 bits. For AD and BC we only care + AD
4026 * about the lower 32 bits (since they are part of the upper + BC
4027 * 32 bits of our result). AC is not needed since it starts + AC
4028 * on the 65th bit of the result. -------
4031 unsigned int q_regs
= regs_written(inst
);
4032 unsigned int d_regs
= (q_regs
+ 1) / 2;
4034 fs_reg
bd(VGRF
, alloc
.allocate(q_regs
), BRW_REGISTER_TYPE_UQ
);
4035 fs_reg
ad(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4036 fs_reg
bc(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4038 /* Here we need the full 64 bit result for 32b * 32b. */
4039 if (devinfo
->has_integer_dword_mul
) {
4040 ibld
.MUL(bd
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4041 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4043 fs_reg
bd_high(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4044 fs_reg
bd_low(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4045 fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), BRW_REGISTER_TYPE_UD
);
4047 fs_inst
*mul
= ibld
.MUL(acc
,
4048 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4049 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4050 mul
->writes_accumulator
= true;
4052 ibld
.MACH(bd_high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4053 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4054 ibld
.MOV(bd_low
, acc
);
4056 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 0), bd_low
);
4057 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), bd_high
);
4060 ibld
.MUL(ad
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
4061 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4062 ibld
.MUL(bc
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4063 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1));
4065 ibld
.ADD(ad
, ad
, bc
);
4066 ibld
.ADD(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1),
4067 subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), ad
);
4069 ibld
.MOV(inst
->dst
, bd
);
4073 fs_visitor::lower_mulh_inst(fs_inst
*inst
, bblock_t
*block
)
4075 const fs_builder
ibld(this, block
, inst
);
4077 /* According to the BDW+ BSpec page for the "Multiply Accumulate
4078 * High" instruction:
4080 * "An added preliminary mov is required for source modification on
4082 * mov (8) r3.0<1>:d -r3<8;8,1>:d
4083 * mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
4084 * mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
4086 if (devinfo
->gen
>= 8 && (inst
->src
[1].negate
|| inst
->src
[1].abs
))
4087 lower_src_modifiers(this, block
, inst
, 1);
4089 /* Should have been lowered to 8-wide. */
4090 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
4091 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), inst
->dst
.type
);
4092 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
4093 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4095 if (devinfo
->gen
>= 8) {
4096 /* Until Gen8, integer multiplies read 32-bits from one source,
4097 * and 16-bits from the other, and relying on the MACH instruction
4098 * to generate the high bits of the result.
4100 * On Gen8, the multiply instruction does a full 32x32-bit
4101 * multiply, but in order to do a 64-bit multiply we can simulate
4102 * the previous behavior and then use a MACH instruction.
4104 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
4105 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
4106 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
4107 mul
->src
[1].stride
*= 2;
4109 if (mul
->src
[1].file
== IMM
) {
4110 mul
->src
[1] = brw_imm_uw(mul
->src
[1].ud
);
4112 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4114 /* Among other things the quarter control bits influence which
4115 * accumulator register is used by the hardware for instructions
4116 * that access the accumulator implicitly (e.g. MACH). A
4117 * second-half instruction would normally map to acc1, which
4118 * doesn't exist on Gen7 and up (the hardware does emulate it for
4119 * floating-point instructions *only* by taking advantage of the
4120 * extra precision of acc0 not normally used for floating point
4123 * HSW and up are careful enough not to try to access an
4124 * accumulator register that doesn't exist, but on earlier Gen7
4125 * hardware we need to make sure that the quarter control bits are
4126 * zero to avoid non-deterministic behaviour and emit an extra MOV
4127 * to get the result masked correctly according to the current
4131 mach
->force_writemask_all
= true;
4132 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
4133 ibld
.MOV(inst
->dst
, mach
->dst
);
4138 fs_visitor::lower_integer_multiplication()
4140 bool progress
= false;
4142 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4143 if (inst
->opcode
== BRW_OPCODE_MUL
) {
4144 /* If the instruction is already in a form that does not need lowering,
4147 if (devinfo
->gen
>= 7) {
4148 if (type_sz(inst
->src
[1].type
) < 4 && type_sz(inst
->src
[0].type
) <= 4)
4151 if (type_sz(inst
->src
[0].type
) < 4 && type_sz(inst
->src
[1].type
) <= 4)
4155 if ((inst
->dst
.type
== BRW_REGISTER_TYPE_Q
||
4156 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
) &&
4157 (inst
->src
[0].type
== BRW_REGISTER_TYPE_Q
||
4158 inst
->src
[0].type
== BRW_REGISTER_TYPE_UQ
) &&
4159 (inst
->src
[1].type
== BRW_REGISTER_TYPE_Q
||
4160 inst
->src
[1].type
== BRW_REGISTER_TYPE_UQ
)) {
4161 lower_mul_qword_inst(inst
, block
);
4162 inst
->remove(block
);
4164 } else if (!inst
->dst
.is_accumulator() &&
4165 (inst
->dst
.type
== BRW_REGISTER_TYPE_D
||
4166 inst
->dst
.type
== BRW_REGISTER_TYPE_UD
) &&
4167 !devinfo
->has_integer_dword_mul
) {
4168 lower_mul_dword_inst(inst
, block
);
4169 inst
->remove(block
);
4172 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
4173 lower_mulh_inst(inst
, block
);
4174 inst
->remove(block
);
4181 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
4187 fs_visitor::lower_minmax()
4189 assert(devinfo
->gen
< 6);
4191 bool progress
= false;
4193 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4194 const fs_builder
ibld(this, block
, inst
);
4196 if (inst
->opcode
== BRW_OPCODE_SEL
&&
4197 inst
->predicate
== BRW_PREDICATE_NONE
) {
4198 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
4199 * the original SEL.L/GE instruction
4201 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4202 inst
->conditional_mod
);
4203 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4204 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
4211 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
4217 fs_visitor::lower_sub_sat()
4219 bool progress
= false;
4221 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4222 const fs_builder
ibld(this, block
, inst
);
4224 if (inst
->opcode
== SHADER_OPCODE_USUB_SAT
||
4225 inst
->opcode
== SHADER_OPCODE_ISUB_SAT
) {
4226 /* The fundamental problem is the hardware performs source negation
4227 * at the bit width of the source. If the source is 0x80000000D, the
4228 * negation is 0x80000000D. As a result, subtractSaturate(0,
4229 * 0x80000000) will produce 0x80000000 instead of 0x7fffffff. There
4230 * are at least three ways to resolve this:
4232 * 1. Use the accumulator for the negated source. The accumulator is
4233 * 33 bits, so our source 0x80000000 is sign-extended to
4234 * 0x1800000000. The negation of which is 0x080000000. This
4235 * doesn't help for 64-bit integers (which are already bigger than
4236 * 33 bits). There are also only 8 accumulators, so SIMD16 or
4237 * SIMD32 instructions would have to be split into multiple SIMD8
4240 * 2. Use slightly different math. For any n-bit value x, we know (x
4241 * >> 1) != -(x >> 1). We can use this fact to only do
4242 * subtractions involving (x >> 1). subtractSaturate(a, b) ==
4243 * subtractSaturate(subtractSaturate(a, (b >> 1)), b - (b >> 1)).
4245 * 3. For unsigned sources, it is sufficient to replace the
4246 * subtractSaturate with (a > b) ? a - b : 0.
4248 * It may also be possible to use the SUBB instruction. This
4249 * implicitly writes the accumulator, so it could only be used in the
4250 * same situations as #1 above. It is further limited by only
4251 * allowing UD sources.
4253 if (inst
->exec_size
== 8 && inst
->src
[0].type
!= BRW_REGISTER_TYPE_Q
&&
4254 inst
->src
[0].type
!= BRW_REGISTER_TYPE_UQ
) {
4255 fs_reg
acc(ARF
, BRW_ARF_ACCUMULATOR
, inst
->src
[1].type
);
4257 ibld
.MOV(acc
, inst
->src
[1]);
4258 fs_inst
*add
= ibld
.ADD(inst
->dst
, acc
, inst
->src
[0]);
4259 add
->saturate
= true;
4260 add
->src
[0].negate
= true;
4261 } else if (inst
->opcode
== SHADER_OPCODE_ISUB_SAT
) {
4263 * dst = add.sat(add.sat(src0, -tmp), -(src1 - tmp));
4265 fs_reg tmp1
= ibld
.vgrf(inst
->src
[0].type
);
4266 fs_reg tmp2
= ibld
.vgrf(inst
->src
[0].type
);
4267 fs_reg tmp3
= ibld
.vgrf(inst
->src
[0].type
);
4270 ibld
.SHR(tmp1
, inst
->src
[1], brw_imm_d(1));
4272 add
= ibld
.ADD(tmp2
, inst
->src
[1], tmp1
);
4273 add
->src
[1].negate
= true;
4275 add
= ibld
.ADD(tmp3
, inst
->src
[0], tmp1
);
4276 add
->src
[1].negate
= true;
4277 add
->saturate
= true;
4279 add
= ibld
.ADD(inst
->dst
, tmp3
, tmp2
);
4280 add
->src
[1].negate
= true;
4281 add
->saturate
= true;
4283 /* a > b ? a - b : 0 */
4284 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4287 fs_inst
*add
= ibld
.ADD(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4288 add
->src
[1].negate
= !add
->src
[1].negate
;
4290 ibld
.SEL(inst
->dst
, inst
->dst
, brw_imm_ud(0))
4291 ->predicate
= BRW_PREDICATE_NORMAL
;
4294 inst
->remove(block
);
4300 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
4306 * Get the mask of SIMD channels enabled during dispatch and not yet disabled
4307 * by discard. Due to the layout of the sample mask in the fragment shader
4308 * thread payload, \p bld is required to have a dispatch_width() not greater
4309 * than 16 for fragment shaders.
4312 sample_mask_reg(const fs_builder
&bld
)
4314 const fs_visitor
*v
= static_cast<const fs_visitor
*>(bld
.shader
);
4316 if (v
->stage
!= MESA_SHADER_FRAGMENT
) {
4317 return brw_imm_ud(0xffffffff);
4318 } else if (brw_wm_prog_data(v
->stage_prog_data
)->uses_kill
) {
4319 assert(bld
.dispatch_width() <= 16);
4320 return brw_flag_subreg(sample_mask_flag_subreg(v
) + bld
.group() / 16);
4322 assert(v
->devinfo
->gen
>= 6 && bld
.dispatch_width() <= 16);
4323 return retype(brw_vec1_grf((bld
.group() >= 16 ? 2 : 1), 7),
4324 BRW_REGISTER_TYPE_UW
);
4329 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
4330 fs_reg
*dst
, fs_reg color
, unsigned components
)
4332 if (key
->clamp_fragment_color
) {
4333 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
4334 assert(color
.type
== BRW_REGISTER_TYPE_F
);
4336 for (unsigned i
= 0; i
< components
; i
++)
4338 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
4343 for (unsigned i
= 0; i
< components
; i
++)
4344 dst
[i
] = offset(color
, bld
, i
);
4348 brw_fb_write_msg_control(const fs_inst
*inst
,
4349 const struct brw_wm_prog_data
*prog_data
)
4353 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
4354 assert(inst
->group
== 0 && inst
->exec_size
== 16);
4355 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
4356 } else if (prog_data
->dual_src_blend
) {
4357 assert(inst
->exec_size
== 8);
4359 if (inst
->group
% 16 == 0)
4360 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
4361 else if (inst
->group
% 16 == 8)
4362 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
4364 unreachable("Invalid dual-source FB write instruction group");
4366 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
4368 if (inst
->exec_size
== 16)
4369 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
4370 else if (inst
->exec_size
== 8)
4371 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
4373 unreachable("Invalid FB write execution size");
4380 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
4381 const struct brw_wm_prog_data
*prog_data
,
4382 const brw_wm_prog_key
*key
,
4383 const fs_visitor::thread_payload
&payload
)
4385 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
4386 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4387 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
4388 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
4389 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
4390 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
4391 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
4392 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
4393 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
4394 const unsigned components
=
4395 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
4397 assert(inst
->target
!= 0 || src0_alpha
.file
== BAD_FILE
);
4399 /* We can potentially have a message length of up to 15, so we have to set
4400 * base_mrf to either 0 or 1 in order to fit in m0..m15.
4403 int header_size
= 2, payload_header_size
;
4404 unsigned length
= 0;
4406 if (devinfo
->gen
< 6) {
4407 /* TODO: Support SIMD32 on gen4-5 */
4408 assert(bld
.group() < 16);
4410 /* For gen4-5, we always have a header consisting of g0 and g1. We have
4411 * an implied MOV from g0,g1 to the start of the message. The MOV from
4412 * g0 is handled by the hardware and the MOV from g1 is provided by the
4413 * generator. This is required because, on gen4-5, the generator may
4414 * generate two write messages with different message lengths in order
4415 * to handle AA data properly.
4417 * Also, since the pixel mask goes in the g0 portion of the message and
4418 * since render target writes are the last thing in the shader, we write
4419 * the pixel mask directly into g0 and it will get copied as part of the
4422 if (prog_data
->uses_kill
) {
4423 bld
.exec_all().group(1, 0)
4424 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
4425 sample_mask_reg(bld
));
4428 assert(length
== 0);
4430 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
4431 prog_data
->uses_kill
) ||
4432 (devinfo
->gen
< 11 &&
4433 (color1
.file
!= BAD_FILE
|| key
->nr_color_regions
> 1))) {
4434 /* From the Sandy Bridge PRM, volume 4, page 198:
4436 * "Dispatched Pixel Enables. One bit per pixel indicating
4437 * which pixels were originally enabled when the thread was
4438 * dispatched. This field is only required for the end-of-
4439 * thread message and on all dual-source messages."
4441 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4443 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4444 if (bld
.group() < 16) {
4445 /* The header starts off as g0 and g1 for the first half */
4446 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4447 BRW_REGISTER_TYPE_UD
));
4449 /* The header starts off as g0 and g2 for the second half */
4450 assert(bld
.group() < 32);
4451 const fs_reg header_sources
[2] = {
4452 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4453 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4455 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4458 uint32_t g00_bits
= 0;
4460 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4463 if (src0_alpha
.file
!= BAD_FILE
)
4464 g00_bits
|= 1 << 11;
4466 /* Set computes stencil to render target */
4467 if (prog_data
->computed_stencil
)
4468 g00_bits
|= 1 << 14;
4471 /* OR extra bits into g0.0 */
4472 ubld
.group(1, 0).OR(component(header
, 0),
4473 retype(brw_vec1_grf(0, 0),
4474 BRW_REGISTER_TYPE_UD
),
4475 brw_imm_ud(g00_bits
));
4478 /* Set the render target index for choosing BLEND_STATE. */
4479 if (inst
->target
> 0) {
4480 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4483 if (prog_data
->uses_kill
) {
4484 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4485 BRW_REGISTER_TYPE_UW
),
4486 sample_mask_reg(bld
));
4489 assert(length
== 0);
4490 sources
[0] = header
;
4491 sources
[1] = horiz_offset(header
, 8);
4494 assert(length
== 0 || length
== 2);
4495 header_size
= length
;
4497 if (payload
.aa_dest_stencil_reg
[0]) {
4498 assert(inst
->group
< 16);
4499 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4500 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4501 .MOV(sources
[length
],
4502 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
[0], 0)));
4506 if (src0_alpha
.file
!= BAD_FILE
) {
4507 for (unsigned i
= 0; i
< bld
.dispatch_width() / 8; i
++) {
4508 const fs_builder
&ubld
= bld
.exec_all().group(8, i
)
4509 .annotate("FB write src0 alpha");
4510 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_F
);
4511 ubld
.MOV(tmp
, horiz_offset(src0_alpha
, i
* 8));
4512 setup_color_payload(ubld
, key
, &sources
[length
], tmp
, 1);
4517 if (sample_mask
.file
!= BAD_FILE
) {
4518 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4519 BRW_REGISTER_TYPE_UD
);
4521 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4522 * relevant. Since it's unsigned single words one vgrf is always
4523 * 16-wide, but only the lower or higher 8 channels will be used by the
4524 * hardware when doing a SIMD8 write depending on whether we have
4525 * selected the subspans for the first or second half respectively.
4527 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4528 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4529 sample_mask
.stride
*= 2;
4531 bld
.exec_all().annotate("FB write oMask")
4532 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4538 payload_header_size
= length
;
4540 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4543 if (color1
.file
!= BAD_FILE
) {
4544 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4548 if (src_depth
.file
!= BAD_FILE
) {
4549 sources
[length
] = src_depth
;
4553 if (dst_depth
.file
!= BAD_FILE
) {
4554 sources
[length
] = dst_depth
;
4558 if (src_stencil
.file
!= BAD_FILE
) {
4559 assert(devinfo
->gen
>= 9);
4560 assert(bld
.dispatch_width() == 8);
4562 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4563 * available on gen9+. As such it's impossible to have both enabled at the
4564 * same time and therefore length cannot overrun the array.
4566 assert(length
< 15);
4568 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4569 bld
.exec_all().annotate("FB write OS")
4570 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4571 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4576 if (devinfo
->gen
>= 7) {
4577 /* Send from the GRF */
4578 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4579 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4580 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4581 load
->dst
= payload
;
4583 uint32_t msg_ctl
= brw_fb_write_msg_control(inst
, prog_data
);
4584 uint32_t ex_desc
= 0;
4587 (inst
->group
/ 16) << 11 | /* rt slot group */
4588 brw_dp_write_desc(devinfo
, inst
->target
, msg_ctl
,
4589 GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
,
4590 inst
->last_rt
, false);
4592 if (devinfo
->gen
>= 11) {
4593 /* Set the "Render Target Index" and "Src0 Alpha Present" fields
4594 * in the extended message descriptor, in lieu of using a header.
4596 ex_desc
= inst
->target
<< 12 | (src0_alpha
.file
!= BAD_FILE
) << 15;
4598 if (key
->nr_color_regions
== 0)
4599 ex_desc
|= 1 << 20; /* Null Render Target */
4602 inst
->opcode
= SHADER_OPCODE_SEND
;
4603 inst
->resize_sources(3);
4604 inst
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4605 inst
->src
[0] = brw_imm_ud(inst
->desc
);
4606 inst
->src
[1] = brw_imm_ud(ex_desc
);
4607 inst
->src
[2] = payload
;
4608 inst
->mlen
= regs_written(load
);
4610 inst
->header_size
= header_size
;
4611 inst
->check_tdr
= true;
4612 inst
->send_has_side_effects
= true;
4614 /* Send from the MRF */
4615 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4616 sources
, length
, payload_header_size
);
4618 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4619 * will do this for us if we just give it a COMPR4 destination.
4621 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4622 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4624 if (devinfo
->gen
< 6) {
4625 /* Set up src[0] for the implied MOV from grf0-1 */
4626 inst
->resize_sources(1);
4627 inst
->src
[0] = brw_vec8_grf(0, 0);
4629 inst
->resize_sources(0);
4632 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4633 inst
->mlen
= regs_written(load
);
4634 inst
->header_size
= header_size
;
4639 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4641 const fs_builder
&ubld
= bld
.exec_all().group(8, 0);
4642 const unsigned length
= 2;
4643 const fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, length
);
4645 if (bld
.group() < 16) {
4646 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4647 BRW_REGISTER_TYPE_UD
));
4649 assert(bld
.group() < 32);
4650 const fs_reg header_sources
[] = {
4651 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4652 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
)
4654 ubld
.LOAD_PAYLOAD(header
, header_sources
, ARRAY_SIZE(header_sources
), 0);
4657 inst
->resize_sources(1);
4658 inst
->src
[0] = header
;
4659 inst
->opcode
= FS_OPCODE_FB_READ
;
4660 inst
->mlen
= length
;
4661 inst
->header_size
= length
;
4665 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4666 const fs_reg
&coordinate
,
4667 const fs_reg
&shadow_c
,
4668 const fs_reg
&lod
, const fs_reg
&lod2
,
4669 const fs_reg
&surface
,
4670 const fs_reg
&sampler
,
4671 unsigned coord_components
,
4672 unsigned grad_components
)
4674 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4675 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4676 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4677 fs_reg msg_end
= msg_begin
;
4680 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4682 for (unsigned i
= 0; i
< coord_components
; i
++)
4683 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4684 offset(coordinate
, bld
, i
));
4686 msg_end
= offset(msg_end
, bld
, coord_components
);
4688 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4689 * require all three components to be present and zero if they are unused.
4691 if (coord_components
> 0 &&
4692 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4693 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4694 for (unsigned i
= coord_components
; i
< 3; i
++)
4695 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4697 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4700 if (op
== SHADER_OPCODE_TXD
) {
4701 /* TXD unsupported in SIMD16 mode. */
4702 assert(bld
.dispatch_width() == 8);
4704 /* the slots for u and v are always present, but r is optional */
4705 if (coord_components
< 2)
4706 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4709 * dPdx = dudx, dvdx, drdx
4710 * dPdy = dudy, dvdy, drdy
4712 * 1-arg: Does not exist.
4714 * 2-arg: dudx dvdx dudy dvdy
4715 * dPdx.x dPdx.y dPdy.x dPdy.y
4718 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4719 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4720 * m5 m6 m7 m8 m9 m10
4722 for (unsigned i
= 0; i
< grad_components
; i
++)
4723 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4725 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4727 for (unsigned i
= 0; i
< grad_components
; i
++)
4728 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4730 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4734 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4735 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4737 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4738 bld
.dispatch_width() == 16);
4740 const brw_reg_type type
=
4741 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4742 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4743 bld
.MOV(retype(msg_end
, type
), lod
);
4744 msg_end
= offset(msg_end
, bld
, 1);
4747 if (shadow_c
.file
!= BAD_FILE
) {
4748 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4749 /* There's no plain shadow compare message, so we use shadow
4750 * compare with a bias of 0.0.
4752 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4753 msg_end
= offset(msg_end
, bld
, 1);
4756 bld
.MOV(msg_end
, shadow_c
);
4757 msg_end
= offset(msg_end
, bld
, 1);
4761 inst
->src
[0] = reg_undef
;
4762 inst
->src
[1] = surface
;
4763 inst
->src
[2] = sampler
;
4764 inst
->resize_sources(3);
4765 inst
->base_mrf
= msg_begin
.nr
;
4766 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4767 inst
->header_size
= 1;
4771 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4772 const fs_reg
&coordinate
,
4773 const fs_reg
&shadow_c
,
4774 const fs_reg
&lod
, const fs_reg
&lod2
,
4775 const fs_reg
&sample_index
,
4776 const fs_reg
&surface
,
4777 const fs_reg
&sampler
,
4778 unsigned coord_components
,
4779 unsigned grad_components
)
4781 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4782 fs_reg msg_coords
= message
;
4783 unsigned header_size
= 0;
4785 if (inst
->offset
!= 0) {
4786 /* The offsets set up by the visitor are in the m1 header, so we can't
4793 for (unsigned i
= 0; i
< coord_components
; i
++)
4794 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4795 offset(coordinate
, bld
, i
));
4797 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4798 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4800 if (shadow_c
.file
!= BAD_FILE
) {
4801 fs_reg msg_shadow
= msg_lod
;
4802 bld
.MOV(msg_shadow
, shadow_c
);
4803 msg_lod
= offset(msg_shadow
, bld
, 1);
4808 case SHADER_OPCODE_TXL
:
4810 bld
.MOV(msg_lod
, lod
);
4811 msg_end
= offset(msg_lod
, bld
, 1);
4813 case SHADER_OPCODE_TXD
:
4816 * dPdx = dudx, dvdx, drdx
4817 * dPdy = dudy, dvdy, drdy
4819 * Load up these values:
4820 * - dudx dudy dvdx dvdy drdx drdy
4821 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4824 for (unsigned i
= 0; i
< grad_components
; i
++) {
4825 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4826 msg_end
= offset(msg_end
, bld
, 1);
4828 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4829 msg_end
= offset(msg_end
, bld
, 1);
4832 case SHADER_OPCODE_TXS
:
4833 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4834 bld
.MOV(msg_lod
, lod
);
4835 msg_end
= offset(msg_lod
, bld
, 1);
4837 case SHADER_OPCODE_TXF
:
4838 msg_lod
= offset(msg_coords
, bld
, 3);
4839 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4840 msg_end
= offset(msg_lod
, bld
, 1);
4842 case SHADER_OPCODE_TXF_CMS
:
4843 msg_lod
= offset(msg_coords
, bld
, 3);
4845 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4847 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4848 msg_end
= offset(msg_lod
, bld
, 2);
4855 inst
->src
[0] = reg_undef
;
4856 inst
->src
[1] = surface
;
4857 inst
->src
[2] = sampler
;
4858 inst
->resize_sources(3);
4859 inst
->base_mrf
= message
.nr
;
4860 inst
->mlen
= msg_end
.nr
- message
.nr
;
4861 inst
->header_size
= header_size
;
4863 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4864 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4868 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4870 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4873 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4877 sampler_msg_type(const gen_device_info
*devinfo
,
4878 opcode opcode
, bool shadow_compare
)
4880 assert(devinfo
->gen
>= 5);
4882 case SHADER_OPCODE_TEX
:
4883 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
:
4884 GEN5_SAMPLER_MESSAGE_SAMPLE
;
4886 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
:
4887 GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
4888 case SHADER_OPCODE_TXL
:
4889 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
:
4890 GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
4891 case SHADER_OPCODE_TXL_LZ
:
4892 return shadow_compare
? GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
:
4893 GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
4894 case SHADER_OPCODE_TXS
:
4895 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4896 return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
4897 case SHADER_OPCODE_TXD
:
4898 assert(!shadow_compare
|| devinfo
->gen
>= 8 || devinfo
->is_haswell
);
4899 return shadow_compare
? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
:
4900 GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
4901 case SHADER_OPCODE_TXF
:
4902 return GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4903 case SHADER_OPCODE_TXF_LZ
:
4904 assert(devinfo
->gen
>= 9);
4905 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
4906 case SHADER_OPCODE_TXF_CMS_W
:
4907 assert(devinfo
->gen
>= 9);
4908 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
4909 case SHADER_OPCODE_TXF_CMS
:
4910 return devinfo
->gen
>= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
:
4911 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4912 case SHADER_OPCODE_TXF_UMS
:
4913 assert(devinfo
->gen
>= 7);
4914 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
4915 case SHADER_OPCODE_TXF_MCS
:
4916 assert(devinfo
->gen
>= 7);
4917 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
4918 case SHADER_OPCODE_LOD
:
4919 return GEN5_SAMPLER_MESSAGE_LOD
;
4920 case SHADER_OPCODE_TG4
:
4921 assert(devinfo
->gen
>= 7);
4922 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
:
4923 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
4925 case SHADER_OPCODE_TG4_OFFSET
:
4926 assert(devinfo
->gen
>= 7);
4927 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
:
4928 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
4929 case SHADER_OPCODE_SAMPLEINFO
:
4930 return GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
4932 unreachable("not reached");
4937 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4938 const fs_reg
&coordinate
,
4939 const fs_reg
&shadow_c
,
4940 fs_reg lod
, const fs_reg
&lod2
,
4941 const fs_reg
&min_lod
,
4942 const fs_reg
&sample_index
,
4944 const fs_reg
&surface
,
4945 const fs_reg
&sampler
,
4946 const fs_reg
&surface_handle
,
4947 const fs_reg
&sampler_handle
,
4948 const fs_reg
&tg4_offset
,
4949 unsigned coord_components
,
4950 unsigned grad_components
)
4952 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4953 const brw_stage_prog_data
*prog_data
= bld
.shader
->stage_prog_data
;
4954 unsigned reg_width
= bld
.dispatch_width() / 8;
4955 unsigned header_size
= 0, length
= 0;
4956 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4957 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4958 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4960 /* We must have exactly one of surface/sampler and surface/sampler_handle */
4961 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
4962 assert((sampler
.file
== BAD_FILE
) != (sampler_handle
.file
== BAD_FILE
));
4964 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4965 inst
->offset
!= 0 || inst
->eot
||
4966 op
== SHADER_OPCODE_SAMPLEINFO
||
4967 sampler_handle
.file
!= BAD_FILE
||
4968 is_high_sampler(devinfo
, sampler
)) {
4969 /* For general texture offsets (no txf workaround), we need a header to
4972 * TG4 needs to place its channel select in the header, for interaction
4973 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4974 * larger sampler numbers we need to offset the Sampler State Pointer in
4977 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4981 /* If we're requesting fewer than four channels worth of response,
4982 * and we have an explicit header, we need to set up the sampler
4983 * writemask. It's reversed from normal: 1 means "don't write".
4985 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4986 assert(regs_written(inst
) % reg_width
== 0);
4987 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4988 inst
->offset
|= mask
<< 12;
4991 /* Build the actual header */
4992 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4993 const fs_builder ubld1
= ubld
.group(1, 0);
4994 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4996 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4997 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4998 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4999 /* The vertex and fragment stages have g0.2 set to 0, so
5000 * header0.2 is 0 when g0 is copied. Other stages may not, so we
5001 * must set it to 0 to avoid setting undesirable bits in the
5004 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
5007 if (sampler_handle
.file
!= BAD_FILE
) {
5008 /* Bindless sampler handles aren't relative to the sampler state
5009 * pointer passed into the shader through SAMPLER_STATE_POINTERS_*.
5010 * Instead, it's an absolute pointer relative to dynamic state base
5013 * Sampler states are 16 bytes each and the pointer we give here has
5014 * to be 32-byte aligned. In order to avoid more indirect messages
5015 * than required, we assume that all bindless sampler states are
5016 * 32-byte aligned. This sacrifices a bit of general state base
5017 * address space but means we can do something more efficient in the
5020 ubld1
.MOV(component(header
, 3), sampler_handle
);
5021 } else if (is_high_sampler(devinfo
, sampler
)) {
5022 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
5023 assert(sampler
.ud
>= 16);
5024 const int sampler_state_size
= 16; /* 16 bytes */
5026 ubld1
.ADD(component(header
, 3),
5027 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5028 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
5030 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
5031 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
5032 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
5033 ubld1
.ADD(component(header
, 3),
5034 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5040 if (shadow_c
.file
!= BAD_FILE
) {
5041 bld
.MOV(sources
[length
], shadow_c
);
5045 bool coordinate_done
= false;
5047 /* Set up the LOD info */
5050 case SHADER_OPCODE_TXL
:
5051 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
5052 op
= SHADER_OPCODE_TXL_LZ
;
5055 bld
.MOV(sources
[length
], lod
);
5058 case SHADER_OPCODE_TXD
:
5059 /* TXD should have been lowered in SIMD16 mode. */
5060 assert(bld
.dispatch_width() == 8);
5062 /* Load dPdx and the coordinate together:
5063 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
5065 for (unsigned i
= 0; i
< coord_components
; i
++) {
5066 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5068 /* For cube map array, the coordinate is (u,v,r,ai) but there are
5069 * only derivatives for (u, v, r).
5071 if (i
< grad_components
) {
5072 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
5073 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
5077 coordinate_done
= true;
5079 case SHADER_OPCODE_TXS
:
5080 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
5083 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5084 /* We need an LOD; just use 0 */
5085 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
5088 case SHADER_OPCODE_TXF
:
5089 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
5090 * On Gen9 they are u, v, lod, r
5092 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
5094 if (devinfo
->gen
>= 9) {
5095 if (coord_components
>= 2) {
5096 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
5097 offset(coordinate
, bld
, 1));
5099 sources
[length
] = brw_imm_d(0);
5104 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
5105 op
= SHADER_OPCODE_TXF_LZ
;
5107 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
5111 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
5112 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5113 offset(coordinate
, bld
, i
));
5115 coordinate_done
= true;
5118 case SHADER_OPCODE_TXF_CMS
:
5119 case SHADER_OPCODE_TXF_CMS_W
:
5120 case SHADER_OPCODE_TXF_UMS
:
5121 case SHADER_OPCODE_TXF_MCS
:
5122 if (op
== SHADER_OPCODE_TXF_UMS
||
5123 op
== SHADER_OPCODE_TXF_CMS
||
5124 op
== SHADER_OPCODE_TXF_CMS_W
) {
5125 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
5129 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
5130 /* Data from the multisample control surface. */
5131 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
5134 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
5137 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
5138 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
5141 offset(mcs
, bld
, 1));
5146 /* There is no offsetting for this message; just copy in the integer
5147 * texture coordinates.
5149 for (unsigned i
= 0; i
< coord_components
; i
++)
5150 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5151 offset(coordinate
, bld
, i
));
5153 coordinate_done
= true;
5155 case SHADER_OPCODE_TG4_OFFSET
:
5156 /* More crazy intermixing */
5157 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
5158 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5160 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
5161 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5162 offset(tg4_offset
, bld
, i
));
5164 if (coord_components
== 3) /* r if present */
5165 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
5167 coordinate_done
= true;
5173 /* Set up the coordinate (except for cases where it was done above) */
5174 if (!coordinate_done
) {
5175 for (unsigned i
= 0; i
< coord_components
; i
++)
5176 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5179 if (min_lod
.file
!= BAD_FILE
) {
5180 /* Account for all of the missing coordinate sources */
5181 length
+= 4 - coord_components
;
5182 if (op
== SHADER_OPCODE_TXD
)
5183 length
+= (3 - grad_components
) * 2;
5185 bld
.MOV(sources
[length
++], min_lod
);
5190 mlen
= length
* reg_width
- header_size
;
5192 mlen
= length
* reg_width
;
5194 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
5195 BRW_REGISTER_TYPE_F
);
5196 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
5198 /* Generate the SEND. */
5199 inst
->opcode
= SHADER_OPCODE_SEND
;
5201 inst
->header_size
= header_size
;
5203 const unsigned msg_type
=
5204 sampler_msg_type(devinfo
, op
, inst
->shadow_compare
);
5205 const unsigned simd_mode
=
5206 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5207 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5209 uint32_t base_binding_table_index
;
5211 case SHADER_OPCODE_TG4
:
5212 case SHADER_OPCODE_TG4_OFFSET
:
5213 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
5215 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5216 base_binding_table_index
= prog_data
->binding_table
.image_start
;
5219 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
5223 inst
->sfid
= BRW_SFID_SAMPLER
;
5224 if (surface
.file
== IMM
&&
5225 (sampler
.file
== IMM
|| sampler_handle
.file
!= BAD_FILE
)) {
5226 inst
->desc
= brw_sampler_desc(devinfo
,
5227 surface
.ud
+ base_binding_table_index
,
5228 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5231 0 /* return_format unused on gen7+ */);
5232 inst
->src
[0] = brw_imm_ud(0);
5233 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5234 } else if (surface_handle
.file
!= BAD_FILE
) {
5235 /* Bindless surface */
5236 assert(devinfo
->gen
>= 9);
5237 inst
->desc
= brw_sampler_desc(devinfo
,
5239 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5242 0 /* return_format unused on gen7+ */);
5244 /* For bindless samplers, the entire address is included in the message
5245 * header so we can leave the portion in the message descriptor 0.
5247 if (sampler_handle
.file
!= BAD_FILE
|| sampler
.file
== IMM
) {
5248 inst
->src
[0] = brw_imm_ud(0);
5250 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5251 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5252 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5253 inst
->src
[0] = desc
;
5256 /* We assume that the driver provided the handle in the top 20 bits so
5257 * we can use the surface handle directly as the extended descriptor.
5259 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5261 /* Immediate portion of the descriptor */
5262 inst
->desc
= brw_sampler_desc(devinfo
,
5267 0 /* return_format unused on gen7+ */);
5268 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5269 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5270 if (surface
.equals(sampler
)) {
5271 /* This case is common in GL */
5272 ubld
.MUL(desc
, surface
, brw_imm_ud(0x101));
5274 if (sampler_handle
.file
!= BAD_FILE
) {
5275 ubld
.MOV(desc
, surface
);
5276 } else if (sampler
.file
== IMM
) {
5277 ubld
.OR(desc
, surface
, brw_imm_ud(sampler
.ud
<< 8));
5279 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5280 ubld
.OR(desc
, desc
, surface
);
5283 if (base_binding_table_index
)
5284 ubld
.ADD(desc
, desc
, brw_imm_ud(base_binding_table_index
));
5285 ubld
.AND(desc
, desc
, brw_imm_ud(0xfff));
5287 inst
->src
[0] = component(desc
, 0);
5288 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5291 inst
->src
[2] = src_payload
;
5292 inst
->resize_sources(3);
5295 /* EOT sampler messages don't make sense to split because it would
5296 * involve ending half of the thread early.
5298 assert(inst
->group
== 0);
5299 /* We need to use SENDC for EOT sampler messages */
5300 inst
->check_tdr
= true;
5301 inst
->send_has_side_effects
= true;
5304 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
5305 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
5309 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
5311 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5312 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
5313 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
5314 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
5315 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
5316 const fs_reg
&min_lod
= inst
->src
[TEX_LOGICAL_SRC_MIN_LOD
];
5317 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
5318 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
5319 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
5320 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
5321 const fs_reg
&surface_handle
= inst
->src
[TEX_LOGICAL_SRC_SURFACE_HANDLE
];
5322 const fs_reg
&sampler_handle
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
];
5323 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
5324 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
5325 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
5326 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
5327 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
5329 if (devinfo
->gen
>= 7) {
5330 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
5331 shadow_c
, lod
, lod2
, min_lod
,
5333 mcs
, surface
, sampler
,
5334 surface_handle
, sampler_handle
,
5336 coord_components
, grad_components
);
5337 } else if (devinfo
->gen
>= 5) {
5338 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
5339 shadow_c
, lod
, lod2
, sample_index
,
5341 coord_components
, grad_components
);
5343 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
5344 shadow_c
, lod
, lod2
,
5346 coord_components
, grad_components
);
5351 * Predicate the specified instruction on the sample mask.
5354 emit_predicate_on_sample_mask(const fs_builder
&bld
, fs_inst
*inst
)
5356 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
&&
5357 bld
.group() == inst
->group
&&
5358 bld
.dispatch_width() == inst
->exec_size
);
5360 const fs_visitor
*v
= static_cast<const fs_visitor
*>(bld
.shader
);
5361 const fs_reg sample_mask
= sample_mask_reg(bld
);
5362 const unsigned subreg
= sample_mask_flag_subreg(v
);
5364 if (brw_wm_prog_data(v
->stage_prog_data
)->uses_kill
) {
5365 assert(sample_mask
.file
== ARF
&&
5366 sample_mask
.nr
== brw_flag_subreg(subreg
).nr
&&
5367 sample_mask
.subnr
== brw_flag_subreg(
5368 subreg
+ inst
->group
/ 16).subnr
);
5370 bld
.group(1, 0).exec_all()
5371 .MOV(brw_flag_subreg(subreg
+ inst
->group
/ 16), sample_mask
);
5374 if (inst
->predicate
) {
5375 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
5376 assert(!inst
->predicate_inverse
);
5377 assert(inst
->flag_subreg
== 0);
5378 /* Combine the sample mask with the existing predicate by using a
5379 * vertical predication mode.
5381 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
5383 inst
->flag_subreg
= subreg
;
5384 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5385 inst
->predicate_inverse
= false;
5390 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5392 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5394 /* Get the logical send arguments. */
5395 const fs_reg
&addr
= inst
->src
[SURFACE_LOGICAL_SRC_ADDRESS
];
5396 const fs_reg
&src
= inst
->src
[SURFACE_LOGICAL_SRC_DATA
];
5397 const fs_reg
&surface
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE
];
5398 const fs_reg
&surface_handle
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
];
5399 const UNUSED fs_reg
&dims
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_DIMS
];
5400 const fs_reg
&arg
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_ARG
];
5401 assert(arg
.file
== IMM
);
5403 /* We must have exactly one of surface and surface_handle */
5404 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
5406 /* Calculate the total number of components of the payload. */
5407 const unsigned addr_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_ADDRESS
);
5408 const unsigned src_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_DATA
);
5410 const bool is_typed_access
=
5411 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
||
5412 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
||
5413 inst
->opcode
== SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
;
5415 const bool is_surface_access
= is_typed_access
||
5416 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
||
5417 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
||
5418 inst
->opcode
== SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
;
5420 const bool is_stateless
=
5421 surface
.file
== IMM
&& (surface
.ud
== BRW_BTI_STATELESS
||
5422 surface
.ud
== GEN8_BTI_STATELESS_NON_COHERENT
);
5424 const bool has_side_effects
= inst
->has_side_effects();
5425 fs_reg sample_mask
= has_side_effects
? sample_mask_reg(bld
) :
5426 fs_reg(brw_imm_d(0xffff));
5428 /* From the BDW PRM Volume 7, page 147:
5430 * "For the Data Cache Data Port*, the header must be present for the
5431 * following message types: [...] Typed read/write/atomics"
5433 * Earlier generations have a similar wording. Because of this restriction
5434 * we don't attempt to implement sample masks via predication for such
5435 * messages prior to Gen9, since we have to provide a header anyway. On
5436 * Gen11+ the header has been removed so we can only use predication.
5438 * For all stateless A32 messages, we also need a header
5441 if ((devinfo
->gen
< 9 && is_typed_access
) || is_stateless
) {
5442 fs_builder ubld
= bld
.exec_all().group(8, 0);
5443 header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5444 ubld
.MOV(header
, brw_imm_d(0));
5446 /* Both the typed and scattered byte/dword A32 messages take a buffer
5447 * base address in R0.5:[31:0] (See MH1_A32_PSM for typed messages or
5448 * MH_A32_GO for byte/dword scattered messages in the SKL PRM Vol. 2d
5449 * for more details.) This is conveniently where the HW places the
5450 * scratch surface base address.
5452 * From the SKL PRM Vol. 7 "Per-Thread Scratch Space":
5454 * "When a thread becomes 'active' it is allocated a portion of
5455 * scratch space, sized according to PerThreadScratchSpace. The
5456 * starting location of each thread’s scratch space allocation,
5457 * ScratchSpaceOffset, is passed in the thread payload in
5458 * R0.5[31:10] and is specified as a 1KB-granular offset from the
5459 * GeneralStateBaseAddress. The computation of ScratchSpaceOffset
5460 * includes the starting address of the stage’s scratch space
5461 * allocation, as programmed by ScratchSpaceBasePointer."
5463 * The base address is passed in bits R0.5[31:10] and the bottom 10
5464 * bits of R0.5 are used for other things. Therefore, we have to
5465 * mask off the bottom 10 bits so that we don't get a garbage base
5468 ubld
.group(1, 0).AND(component(header
, 5),
5469 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD
),
5470 brw_imm_ud(0xfffffc00));
5472 if (is_surface_access
)
5473 ubld
.group(1, 0).MOV(component(header
, 7), sample_mask
);
5475 const unsigned header_sz
= header
.file
!= BAD_FILE
? 1 : 0;
5477 fs_reg payload
, payload2
;
5478 unsigned mlen
, ex_mlen
= 0;
5479 if (devinfo
->gen
>= 9 &&
5480 (src
.file
== BAD_FILE
|| header
.file
== BAD_FILE
)) {
5481 /* We have split sends on gen9 and above */
5482 if (header
.file
== BAD_FILE
) {
5483 payload
= bld
.move_to_vgrf(addr
, addr_sz
);
5484 payload2
= bld
.move_to_vgrf(src
, src_sz
);
5485 mlen
= addr_sz
* (inst
->exec_size
/ 8);
5486 ex_mlen
= src_sz
* (inst
->exec_size
/ 8);
5488 assert(src
.file
== BAD_FILE
);
5490 payload2
= bld
.move_to_vgrf(addr
, addr_sz
);
5492 ex_mlen
= addr_sz
* (inst
->exec_size
/ 8);
5495 /* Allocate space for the payload. */
5496 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
5497 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
5498 fs_reg
*const components
= new fs_reg
[sz
];
5501 /* Construct the payload. */
5502 if (header
.file
!= BAD_FILE
)
5503 components
[n
++] = header
;
5505 for (unsigned i
= 0; i
< addr_sz
; i
++)
5506 components
[n
++] = offset(addr
, bld
, i
);
5508 for (unsigned i
= 0; i
< src_sz
; i
++)
5509 components
[n
++] = offset(src
, bld
, i
);
5511 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
5512 mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
5514 delete[] components
;
5517 /* Predicate the instruction on the sample mask if no header is
5520 if ((header
.file
== BAD_FILE
|| !is_surface_access
) &&
5521 sample_mask
.file
!= BAD_FILE
&& sample_mask
.file
!= IMM
)
5522 emit_predicate_on_sample_mask(bld
, inst
);
5525 switch (inst
->opcode
) {
5526 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5527 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5528 /* Byte scattered opcodes go through the normal data cache */
5529 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
5532 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5533 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5534 sfid
= devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
5535 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
5536 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
;
5539 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5540 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5541 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5542 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5543 /* Untyped Surface messages go through the data cache but the SFID value
5544 * changed on Haswell.
5546 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5547 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5548 GEN7_SFID_DATAPORT_DATA_CACHE
);
5551 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5552 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5553 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5554 /* Typed surface messages go through the render cache on IVB and the
5555 * data cache on HSW+.
5557 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5558 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5559 GEN6_SFID_DATAPORT_RENDER_CACHE
);
5563 unreachable("Unsupported surface opcode");
5567 switch (inst
->opcode
) {
5568 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5569 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5570 arg
.ud
, /* num_channels */
5574 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5575 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5576 arg
.ud
, /* num_channels */
5580 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5581 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5582 arg
.ud
, /* bit_size */
5586 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5587 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5588 arg
.ud
, /* bit_size */
5592 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5593 assert(arg
.ud
== 32); /* bit_size */
5594 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5598 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5599 assert(arg
.ud
== 32); /* bit_size */
5600 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5604 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5605 desc
= brw_dp_untyped_atomic_desc(devinfo
, inst
->exec_size
,
5606 arg
.ud
, /* atomic_op */
5607 !inst
->dst
.is_null());
5610 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5611 desc
= brw_dp_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5612 arg
.ud
, /* atomic_op */
5613 !inst
->dst
.is_null());
5616 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5617 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5618 arg
.ud
, /* num_channels */
5622 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5623 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5624 arg
.ud
, /* num_channels */
5628 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5629 desc
= brw_dp_typed_atomic_desc(devinfo
, inst
->exec_size
, inst
->group
,
5630 arg
.ud
, /* atomic_op */
5631 !inst
->dst
.is_null());
5635 unreachable("Unknown surface logical instruction");
5638 /* Update the original instruction. */
5639 inst
->opcode
= SHADER_OPCODE_SEND
;
5641 inst
->ex_mlen
= ex_mlen
;
5642 inst
->header_size
= header_sz
;
5643 inst
->send_has_side_effects
= has_side_effects
;
5644 inst
->send_is_volatile
= !has_side_effects
;
5646 /* Set up SFID and descriptors */
5649 if (surface
.file
== IMM
) {
5650 inst
->desc
|= surface
.ud
& 0xff;
5651 inst
->src
[0] = brw_imm_ud(0);
5652 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5653 } else if (surface_handle
.file
!= BAD_FILE
) {
5654 /* Bindless surface */
5655 assert(devinfo
->gen
>= 9);
5656 inst
->desc
|= GEN9_BTI_BINDLESS
;
5657 inst
->src
[0] = brw_imm_ud(0);
5659 /* We assume that the driver provided the handle in the top 20 bits so
5660 * we can use the surface handle directly as the extended descriptor.
5662 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5664 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5665 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5666 ubld
.AND(tmp
, surface
, brw_imm_ud(0xff));
5667 inst
->src
[0] = component(tmp
, 0);
5668 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5671 /* Finally, the payload */
5672 inst
->src
[2] = payload
;
5673 inst
->src
[3] = payload2
;
5675 inst
->resize_sources(4);
5679 lower_a64_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5681 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5683 const fs_reg
&addr
= inst
->src
[0];
5684 const fs_reg
&src
= inst
->src
[1];
5685 const unsigned src_comps
= inst
->components_read(1);
5686 assert(inst
->src
[2].file
== IMM
);
5687 const unsigned arg
= inst
->src
[2].ud
;
5688 const bool has_side_effects
= inst
->has_side_effects();
5690 /* If the surface message has side effects and we're a fragment shader, we
5691 * have to predicate with the sample mask to avoid helper invocations.
5693 if (has_side_effects
&& bld
.shader
->stage
== MESA_SHADER_FRAGMENT
)
5694 emit_predicate_on_sample_mask(bld
, inst
);
5696 fs_reg payload
, payload2
;
5697 unsigned mlen
, ex_mlen
= 0;
5698 if (devinfo
->gen
>= 9) {
5699 /* On Skylake and above, we have SENDS */
5700 mlen
= 2 * (inst
->exec_size
/ 8);
5701 ex_mlen
= src_comps
* type_sz(src
.type
) * inst
->exec_size
/ REG_SIZE
;
5702 payload
= retype(bld
.move_to_vgrf(addr
, 1), BRW_REGISTER_TYPE_UD
);
5703 payload2
= retype(bld
.move_to_vgrf(src
, src_comps
),
5704 BRW_REGISTER_TYPE_UD
);
5706 /* Add two because the address is 64-bit */
5707 const unsigned dwords
= 2 + src_comps
;
5708 mlen
= dwords
* (inst
->exec_size
/ 8);
5714 for (unsigned i
= 0; i
< src_comps
; i
++)
5715 sources
[1 + i
] = offset(src
, bld
, i
);
5717 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, dwords
);
5718 bld
.LOAD_PAYLOAD(payload
, sources
, 1 + src_comps
, 0);
5722 switch (inst
->opcode
) {
5723 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5724 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5725 arg
, /* num_channels */
5729 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5730 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5731 arg
, /* num_channels */
5735 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5736 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5741 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5742 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5747 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5748 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 32,
5749 arg
, /* atomic_op */
5750 !inst
->dst
.is_null());
5753 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5754 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 64,
5755 arg
, /* atomic_op */
5756 !inst
->dst
.is_null());
5760 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5761 desc
= brw_dp_a64_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5762 arg
, /* atomic_op */
5763 !inst
->dst
.is_null());
5767 unreachable("Unknown A64 logical instruction");
5770 /* Update the original instruction. */
5771 inst
->opcode
= SHADER_OPCODE_SEND
;
5773 inst
->ex_mlen
= ex_mlen
;
5774 inst
->header_size
= 0;
5775 inst
->send_has_side_effects
= has_side_effects
;
5776 inst
->send_is_volatile
= !has_side_effects
;
5778 /* Set up SFID and descriptors */
5779 inst
->sfid
= HSW_SFID_DATAPORT_DATA_CACHE_1
;
5781 inst
->resize_sources(4);
5782 inst
->src
[0] = brw_imm_ud(0); /* desc */
5783 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5784 inst
->src
[2] = payload
;
5785 inst
->src
[3] = payload2
;
5789 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5791 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5793 if (devinfo
->gen
>= 7) {
5794 fs_reg index
= inst
->src
[0];
5795 /* We are switching the instruction from an ALU-like instruction to a
5796 * send-from-grf instruction. Since sends can't handle strides or
5797 * source modifiers, we have to make a copy of the offset source.
5799 fs_reg offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5800 bld
.MOV(offset
, inst
->src
[1]);
5802 const unsigned simd_mode
=
5803 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5804 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5806 inst
->opcode
= SHADER_OPCODE_SEND
;
5807 inst
->mlen
= inst
->exec_size
/ 8;
5808 inst
->resize_sources(3);
5810 inst
->sfid
= BRW_SFID_SAMPLER
;
5811 inst
->desc
= brw_sampler_desc(devinfo
, 0, 0,
5812 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
5814 if (index
.file
== IMM
) {
5815 inst
->desc
|= index
.ud
& 0xff;
5816 inst
->src
[0] = brw_imm_ud(0);
5818 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5819 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5820 ubld
.AND(tmp
, index
, brw_imm_ud(0xff));
5821 inst
->src
[0] = component(tmp
, 0);
5823 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5824 inst
->src
[2] = offset
; /* payload */
5826 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
5827 BRW_REGISTER_TYPE_UD
);
5829 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
5831 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
5832 inst
->resize_sources(1);
5833 inst
->base_mrf
= payload
.nr
;
5834 inst
->header_size
= 1;
5835 inst
->mlen
= 1 + inst
->exec_size
/ 8;
5840 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5842 assert(bld
.shader
->devinfo
->gen
< 6);
5845 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
5847 if (inst
->sources
> 1) {
5848 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
5849 * "Message Payload":
5851 * "Operand0[7]. For the INT DIV functions, this operand is the
5854 * "Operand1[7]. For the INT DIV functions, this operand is the
5857 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
5858 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
5859 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
5861 inst
->resize_sources(1);
5862 inst
->src
[0] = src0
;
5864 assert(inst
->exec_size
== 8);
5865 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
5870 fs_visitor::lower_logical_sends()
5872 bool progress
= false;
5874 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5875 const fs_builder
ibld(this, block
, inst
);
5877 switch (inst
->opcode
) {
5878 case FS_OPCODE_FB_WRITE_LOGICAL
:
5879 assert(stage
== MESA_SHADER_FRAGMENT
);
5880 lower_fb_write_logical_send(ibld
, inst
,
5881 brw_wm_prog_data(prog_data
),
5882 (const brw_wm_prog_key
*)key
,
5886 case FS_OPCODE_FB_READ_LOGICAL
:
5887 lower_fb_read_logical_send(ibld
, inst
);
5890 case SHADER_OPCODE_TEX_LOGICAL
:
5891 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
5894 case SHADER_OPCODE_TXD_LOGICAL
:
5895 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
5898 case SHADER_OPCODE_TXF_LOGICAL
:
5899 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
5902 case SHADER_OPCODE_TXL_LOGICAL
:
5903 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
5906 case SHADER_OPCODE_TXS_LOGICAL
:
5907 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
5910 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5911 lower_sampler_logical_send(ibld
, inst
,
5912 SHADER_OPCODE_IMAGE_SIZE_LOGICAL
);
5915 case FS_OPCODE_TXB_LOGICAL
:
5916 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
5919 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5920 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
5923 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5924 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
5927 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5928 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
5931 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5932 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
5935 case SHADER_OPCODE_LOD_LOGICAL
:
5936 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
5939 case SHADER_OPCODE_TG4_LOGICAL
:
5940 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
5943 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5944 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
5947 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5948 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
5951 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5952 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5953 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5954 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5955 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5956 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5957 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5958 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5959 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5960 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5961 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5962 lower_surface_logical_send(ibld
, inst
);
5965 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5966 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5967 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5968 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5969 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5970 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5971 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5972 lower_a64_logical_send(ibld
, inst
);
5975 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5976 lower_varying_pull_constant_logical_send(ibld
, inst
);
5979 case SHADER_OPCODE_RCP
:
5980 case SHADER_OPCODE_RSQ
:
5981 case SHADER_OPCODE_SQRT
:
5982 case SHADER_OPCODE_EXP2
:
5983 case SHADER_OPCODE_LOG2
:
5984 case SHADER_OPCODE_SIN
:
5985 case SHADER_OPCODE_COS
:
5986 case SHADER_OPCODE_POW
:
5987 case SHADER_OPCODE_INT_QUOTIENT
:
5988 case SHADER_OPCODE_INT_REMAINDER
:
5989 /* The math opcodes are overloaded for the send-like and
5990 * expression-like instructions which seems kind of icky. Gen6+ has
5991 * a native (but rather quirky) MATH instruction so we don't need to
5992 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
5993 * logical instructions (which we can easily recognize because they
5994 * have mlen = 0) into send-like virtual instructions.
5996 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
5997 lower_math_logical_send(ibld
, inst
);
6012 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
6018 is_mixed_float_with_fp32_dst(const fs_inst
*inst
)
6020 /* This opcode sometimes uses :W type on the source even if the operand is
6021 * a :HF, because in gen7 there is no support for :HF, and thus it uses :W.
6023 if (inst
->opcode
== BRW_OPCODE_F16TO32
)
6026 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
)
6029 for (int i
= 0; i
< inst
->sources
; i
++) {
6030 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_HF
)
6038 is_mixed_float_with_packed_fp16_dst(const fs_inst
*inst
)
6040 /* This opcode sometimes uses :W type on the destination even if the
6041 * destination is a :HF, because in gen7 there is no support for :HF, and
6044 if (inst
->opcode
== BRW_OPCODE_F32TO16
&&
6045 inst
->dst
.stride
== 1)
6048 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_HF
||
6049 inst
->dst
.stride
!= 1)
6052 for (int i
= 0; i
< inst
->sources
; i
++) {
6053 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_F
)
6061 * Get the closest allowed SIMD width for instruction \p inst accounting for
6062 * some common regioning and execution control restrictions that apply to FPU
6063 * instructions. These restrictions don't necessarily have any relevance to
6064 * instructions not executed by the FPU pipeline like extended math, control
6065 * flow or send message instructions.
6067 * For virtual opcodes it's really up to the instruction -- In some cases
6068 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
6069 * instructions) it may simplify virtual instruction lowering if we can
6070 * enforce FPU-like regioning restrictions already on the virtual instruction,
6071 * in other cases (e.g. virtual send-like instructions) this may be
6072 * excessively restrictive.
6075 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
6076 const fs_inst
*inst
)
6078 /* Maximum execution size representable in the instruction controls. */
6079 unsigned max_width
= MIN2(32, inst
->exec_size
);
6081 /* According to the PRMs:
6082 * "A. In Direct Addressing mode, a source cannot span more than 2
6083 * adjacent GRF registers.
6084 * B. A destination cannot span more than 2 adjacent GRF registers."
6086 * Look for the source or destination with the largest register region
6087 * which is the one that is going to limit the overall execution size of
6088 * the instruction due to this rule.
6090 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6092 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6093 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
6095 /* Calculate the maximum execution size of the instruction based on the
6096 * factor by which it goes over the hardware limit of 2 GRFs.
6099 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
6101 /* According to the IVB PRMs:
6102 * "When destination spans two registers, the source MUST span two
6103 * registers. The exception to the above rule:
6105 * - When source is scalar, the source registers are not incremented.
6106 * - When source is packed integer Word and destination is packed
6107 * integer DWord, the source register is not incremented but the
6108 * source sub register is incremented."
6110 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
6111 * restrictions. The code below intentionally doesn't check whether the
6112 * destination type is integer because empirically the hardware doesn't
6113 * seem to care what the actual type is as long as it's dword-aligned.
6115 if (devinfo
->gen
< 8) {
6116 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6117 /* IVB implements DF scalars as <0;2,1> regions. */
6118 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
6119 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
6120 const bool is_packed_word_exception
=
6121 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
6122 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
6124 /* We check size_read(i) against size_written instead of REG_SIZE
6125 * because we want to properly handle SIMD32. In SIMD32, you can end
6126 * up with writes to 4 registers and a source that reads 2 registers
6127 * and we may still need to lower all the way to SIMD8 in that case.
6129 if (inst
->size_written
> REG_SIZE
&&
6130 inst
->size_read(i
) != 0 &&
6131 inst
->size_read(i
) < inst
->size_written
&&
6132 !is_scalar_exception
&& !is_packed_word_exception
) {
6133 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6134 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6139 if (devinfo
->gen
< 6) {
6140 /* From the G45 PRM, Volume 4 Page 361:
6142 * "Operand Alignment Rule: With the exceptions listed below, a
6143 * source/destination operand in general should be aligned to even
6144 * 256-bit physical register with a region size equal to two 256-bit
6145 * physical registers."
6147 * Normally we enforce this by allocating virtual registers to the
6148 * even-aligned class. But we need to handle payload registers.
6150 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6151 if (inst
->src
[i
].file
== FIXED_GRF
&& (inst
->src
[i
].nr
& 1) &&
6152 inst
->size_read(i
) > REG_SIZE
) {
6153 max_width
= MIN2(max_width
, 8);
6158 /* From the IVB PRMs:
6159 * "When an instruction is SIMD32, the low 16 bits of the execution mask
6160 * are applied for both halves of the SIMD32 instruction. If different
6161 * execution mask channels are required, split the instruction into two
6162 * SIMD16 instructions."
6164 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
6165 * 32-wide control flow support in hardware and will behave similarly.
6167 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
6168 max_width
= MIN2(max_width
, 16);
6170 /* From the IVB PRMs (applies to HSW too):
6171 * "Instructions with condition modifiers must not use SIMD32."
6173 * From the BDW PRMs (applies to later hardware too):
6174 * "Ternary instruction with condition modifiers must not use SIMD32."
6176 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
6177 max_width
= MIN2(max_width
, 16);
6179 /* From the IVB PRMs (applies to other devices that don't have the
6180 * gen_device_info::supports_simd16_3src flag set):
6181 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
6182 * SIMD8 is not allowed for DF operations."
6184 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
6185 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6187 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
6188 * the 8-bit quarter of the execution mask signals specified in the
6189 * instruction control fields) for the second compressed half of any
6190 * single-precision instruction (for double-precision instructions
6191 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
6192 * the EU will apply the wrong execution controls for the second
6193 * sequential GRF write if the number of channels per GRF is not exactly
6194 * eight in single-precision mode (or four in double-float mode).
6196 * In this situation we calculate the maximum size of the split
6197 * instructions so they only ever write to a single register.
6199 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
6200 !inst
->force_writemask_all
) {
6201 const unsigned channels_per_grf
= inst
->exec_size
/
6202 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6203 const unsigned exec_type_size
= get_exec_type_size(inst
);
6204 assert(exec_type_size
);
6206 /* The hardware shifts exactly 8 channels per compressed half of the
6207 * instruction in single-precision mode and exactly 4 in double-precision.
6209 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
6210 max_width
= MIN2(max_width
, channels_per_grf
);
6212 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
6213 * because HW applies the same channel enable signals to both halves of
6214 * the compressed instruction which will be just wrong under
6215 * non-uniform control flow.
6217 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6218 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
6219 max_width
= MIN2(max_width
, 4);
6222 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6225 * "No SIMD16 in mixed mode when destination is f32. Instruction
6226 * execution size must be no more than 8."
6228 * FIXME: the simulator doesn't seem to complain if we don't do this and
6229 * empirical testing with existing CTS tests show that they pass just fine
6230 * without implementing this, however, since our interpretation of the PRM
6231 * is that conversion MOVs between HF and F are still mixed-float
6232 * instructions (and therefore subject to this restriction) we decided to
6233 * split them to be safe. Might be useful to do additional investigation to
6234 * lift the restriction if we can ensure that it is safe though, since these
6235 * conversions are common when half-float types are involved since many
6236 * instructions do not support HF types and conversions from/to F are
6239 if (is_mixed_float_with_fp32_dst(inst
))
6240 max_width
= MIN2(max_width
, 8);
6242 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6245 * "No SIMD16 in mixed mode when destination is packed f16 for both
6246 * Align1 and Align16."
6248 if (is_mixed_float_with_packed_fp16_dst(inst
))
6249 max_width
= MIN2(max_width
, 8);
6251 /* Only power-of-two execution sizes are representable in the instruction
6254 return 1 << _mesa_logbase2(max_width
);
6258 * Get the maximum allowed SIMD width for instruction \p inst accounting for
6259 * various payload size restrictions that apply to sampler message
6262 * This is only intended to provide a maximum theoretical bound for the
6263 * execution size of the message based on the number of argument components
6264 * alone, which in most cases will determine whether the SIMD8 or SIMD16
6265 * variant of the message can be used, though some messages may have
6266 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
6267 * the message length to determine the exact SIMD width and argument count,
6268 * which makes a number of sampler message combinations impossible to
6272 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
6273 const fs_inst
*inst
)
6275 /* If we have a min_lod parameter on anything other than a simple sample
6276 * message, it will push it over 5 arguments and we have to fall back to
6279 if (inst
->opcode
!= SHADER_OPCODE_TEX
&&
6280 inst
->components_read(TEX_LOGICAL_SRC_MIN_LOD
))
6283 /* Calculate the number of coordinate components that have to be present
6284 * assuming that additional arguments follow the texel coordinates in the
6285 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
6286 * need to pad to four or three components depending on the message,
6287 * pre-ILK we need to pad to at most three components.
6289 const unsigned req_coord_components
=
6290 (devinfo
->gen
>= 7 ||
6291 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
6292 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
6293 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
6296 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
6297 * variant of the TXL or TXF message.
6299 const bool implicit_lod
= devinfo
->gen
>= 9 &&
6300 (inst
->opcode
== SHADER_OPCODE_TXL
||
6301 inst
->opcode
== SHADER_OPCODE_TXF
) &&
6302 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
6304 /* Calculate the total number of argument components that need to be passed
6305 * to the sampler unit.
6307 const unsigned num_payload_components
=
6308 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
6309 req_coord_components
) +
6310 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
6311 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
6312 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
6313 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
6314 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
6315 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
6316 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
6318 /* SIMD16 messages with more than five arguments exceed the maximum message
6319 * size supported by the sampler, regardless of whether a header is
6322 return MIN2(inst
->exec_size
,
6323 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
6327 * Get the closest native SIMD width supported by the hardware for instruction
6328 * \p inst. The instruction will be left untouched by
6329 * fs_visitor::lower_simd_width() if the returned value is equal to the
6330 * original execution size.
6333 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
6334 const fs_inst
*inst
)
6336 switch (inst
->opcode
) {
6337 case BRW_OPCODE_MOV
:
6338 case BRW_OPCODE_SEL
:
6339 case BRW_OPCODE_NOT
:
6340 case BRW_OPCODE_AND
:
6342 case BRW_OPCODE_XOR
:
6343 case BRW_OPCODE_SHR
:
6344 case BRW_OPCODE_SHL
:
6345 case BRW_OPCODE_ASR
:
6346 case BRW_OPCODE_ROR
:
6347 case BRW_OPCODE_ROL
:
6348 case BRW_OPCODE_CMPN
:
6349 case BRW_OPCODE_CSEL
:
6350 case BRW_OPCODE_F32TO16
:
6351 case BRW_OPCODE_F16TO32
:
6352 case BRW_OPCODE_BFREV
:
6353 case BRW_OPCODE_BFE
:
6354 case BRW_OPCODE_ADD
:
6355 case BRW_OPCODE_MUL
:
6356 case BRW_OPCODE_AVG
:
6357 case BRW_OPCODE_FRC
:
6358 case BRW_OPCODE_RNDU
:
6359 case BRW_OPCODE_RNDD
:
6360 case BRW_OPCODE_RNDE
:
6361 case BRW_OPCODE_RNDZ
:
6362 case BRW_OPCODE_LZD
:
6363 case BRW_OPCODE_FBH
:
6364 case BRW_OPCODE_FBL
:
6365 case BRW_OPCODE_CBIT
:
6366 case BRW_OPCODE_SAD2
:
6367 case BRW_OPCODE_MAD
:
6368 case BRW_OPCODE_LRP
:
6369 case FS_OPCODE_PACK
:
6370 case SHADER_OPCODE_SEL_EXEC
:
6371 case SHADER_OPCODE_CLUSTER_BROADCAST
:
6372 return get_fpu_lowered_simd_width(devinfo
, inst
);
6374 case BRW_OPCODE_CMP
: {
6375 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
6376 * when the destination is a GRF the dependency-clear bit on the flag
6377 * register is cleared early.
6379 * Suggested workarounds are to disable coissuing CMP instructions
6380 * or to split CMP(16) instructions into two CMP(8) instructions.
6382 * We choose to split into CMP(8) instructions since disabling
6383 * coissuing would affect CMP instructions not otherwise affected by
6386 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6387 !inst
->dst
.is_null() ? 8 : ~0);
6388 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
6390 case BRW_OPCODE_BFI1
:
6391 case BRW_OPCODE_BFI2
:
6392 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
6394 * "Force BFI instructions to be executed always in SIMD8."
6396 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
6397 get_fpu_lowered_simd_width(devinfo
, inst
));
6400 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
6401 return inst
->exec_size
;
6403 case SHADER_OPCODE_RCP
:
6404 case SHADER_OPCODE_RSQ
:
6405 case SHADER_OPCODE_SQRT
:
6406 case SHADER_OPCODE_EXP2
:
6407 case SHADER_OPCODE_LOG2
:
6408 case SHADER_OPCODE_SIN
:
6409 case SHADER_OPCODE_COS
: {
6410 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
6411 * Gen6. Extended Math Function is limited to SIMD8 with half-float.
6413 if (devinfo
->gen
== 6 || (devinfo
->gen
== 4 && !devinfo
->is_g4x
))
6414 return MIN2(8, inst
->exec_size
);
6415 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6416 return MIN2(8, inst
->exec_size
);
6417 return MIN2(16, inst
->exec_size
);
6420 case SHADER_OPCODE_POW
: {
6421 /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
6422 * to SIMD8 with half-float
6424 if (devinfo
->gen
< 7)
6425 return MIN2(8, inst
->exec_size
);
6426 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6427 return MIN2(8, inst
->exec_size
);
6428 return MIN2(16, inst
->exec_size
);
6431 case SHADER_OPCODE_USUB_SAT
:
6432 case SHADER_OPCODE_ISUB_SAT
:
6433 return get_fpu_lowered_simd_width(devinfo
, inst
);
6435 case SHADER_OPCODE_INT_QUOTIENT
:
6436 case SHADER_OPCODE_INT_REMAINDER
:
6437 /* Integer division is limited to SIMD8 on all generations. */
6438 return MIN2(8, inst
->exec_size
);
6440 case FS_OPCODE_LINTERP
:
6441 case SHADER_OPCODE_GET_BUFFER_SIZE
:
6442 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
6443 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
6444 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6445 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6446 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
6447 return MIN2(16, inst
->exec_size
);
6449 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
6450 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
6451 * message used to implement varying pull constant loads, so expand it
6452 * to SIMD16. An alternative with longer message payload length but
6453 * shorter return payload would be to use the SIMD8 sampler message that
6454 * takes (header, u, v, r) as parameters instead of (header, u).
6456 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
6458 case FS_OPCODE_DDX_COARSE
:
6459 case FS_OPCODE_DDX_FINE
:
6460 case FS_OPCODE_DDY_COARSE
:
6461 case FS_OPCODE_DDY_FINE
:
6462 /* The implementation of this virtual opcode may require emitting
6463 * compressed Align16 instructions, which are severely limited on some
6466 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
6467 * Region Restrictions):
6469 * "In Align16 access mode, SIMD16 is not allowed for DW operations
6470 * and SIMD8 is not allowed for DF operations."
6472 * In this context, "DW operations" means "operations acting on 32-bit
6473 * values", so it includes operations on floats.
6475 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
6476 * (Instruction Compression -> Rules and Restrictions):
6478 * "A compressed instruction must be in Align1 access mode. Align16
6479 * mode instructions cannot be compressed."
6481 * Similar text exists in the g45 PRM.
6483 * Empirically, compressed align16 instructions using odd register
6484 * numbers don't appear to work on Sandybridge either.
6486 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
6487 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
6488 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
6490 case SHADER_OPCODE_MULH
:
6491 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
6492 * is 8-wide on Gen7+.
6494 return (devinfo
->gen
>= 7 ? 8 :
6495 get_fpu_lowered_simd_width(devinfo
, inst
));
6497 case FS_OPCODE_FB_WRITE_LOGICAL
:
6498 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
6501 assert(devinfo
->gen
!= 6 ||
6502 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
6503 inst
->exec_size
== 8);
6504 /* Dual-source FB writes are unsupported in SIMD16 mode. */
6505 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
6506 8 : MIN2(16, inst
->exec_size
));
6508 case FS_OPCODE_FB_READ_LOGICAL
:
6509 return MIN2(16, inst
->exec_size
);
6511 case SHADER_OPCODE_TEX_LOGICAL
:
6512 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
6513 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
6514 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
6515 case SHADER_OPCODE_LOD_LOGICAL
:
6516 case SHADER_OPCODE_TG4_LOGICAL
:
6517 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
6518 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
6519 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
6520 return get_sampler_lowered_simd_width(devinfo
, inst
);
6522 case SHADER_OPCODE_TXD_LOGICAL
:
6523 /* TXD is unsupported in SIMD16 mode. */
6526 case SHADER_OPCODE_TXL_LOGICAL
:
6527 case FS_OPCODE_TXB_LOGICAL
:
6528 /* Only one execution size is representable pre-ILK depending on whether
6529 * the shadow reference argument is present.
6531 if (devinfo
->gen
== 4)
6532 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
6534 return get_sampler_lowered_simd_width(devinfo
, inst
);
6536 case SHADER_OPCODE_TXF_LOGICAL
:
6537 case SHADER_OPCODE_TXS_LOGICAL
:
6538 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
6539 * messages. Use SIMD16 instead.
6541 if (devinfo
->gen
== 4)
6544 return get_sampler_lowered_simd_width(devinfo
, inst
);
6546 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
6547 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
6548 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
6551 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
6552 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6553 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
6554 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
6555 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
6556 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
6557 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
6558 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
6559 return MIN2(16, inst
->exec_size
);
6561 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
6562 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
6563 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
6564 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
6565 return devinfo
->gen
<= 8 ? 8 : MIN2(16, inst
->exec_size
);
6567 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
6568 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
6569 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6572 case SHADER_OPCODE_URB_READ_SIMD8
:
6573 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
6574 case SHADER_OPCODE_URB_WRITE_SIMD8
:
6575 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
6576 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
6577 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
6578 return MIN2(8, inst
->exec_size
);
6580 case SHADER_OPCODE_QUAD_SWIZZLE
: {
6581 const unsigned swiz
= inst
->src
[1].ud
;
6582 return (is_uniform(inst
->src
[0]) ?
6583 get_fpu_lowered_simd_width(devinfo
, inst
) :
6584 devinfo
->gen
< 11 && type_sz(inst
->src
[0].type
) == 4 ? 8 :
6585 swiz
== BRW_SWIZZLE_XYXY
|| swiz
== BRW_SWIZZLE_ZWZW
? 4 :
6586 get_fpu_lowered_simd_width(devinfo
, inst
));
6588 case SHADER_OPCODE_MOV_INDIRECT
: {
6589 /* From IVB and HSW PRMs:
6591 * "2.When the destination requires two registers and the sources are
6592 * indirect, the sources must use 1x1 regioning mode.
6594 * In case of DF instructions in HSW/IVB, the exec_size is limited by
6595 * the EU decompression logic not handling VxH indirect addressing
6598 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
6599 /* Prior to Broadwell, we only have 8 address subregisters. */
6600 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
6601 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
6605 case SHADER_OPCODE_LOAD_PAYLOAD
: {
6606 const unsigned reg_count
=
6607 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
6609 if (reg_count
> 2) {
6610 /* Only LOAD_PAYLOAD instructions with per-channel destination region
6611 * can be easily lowered (which excludes headers and heterogeneous
6614 assert(!inst
->header_size
);
6615 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6616 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
6617 inst
->src
[i
].file
== BAD_FILE
);
6619 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
6621 return inst
->exec_size
;
6625 return inst
->exec_size
;
6630 * Return true if splitting out the group of channels of instruction \p inst
6631 * given by lbld.group() requires allocating a temporary for the i-th source
6632 * of the lowered instruction.
6635 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
6637 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
6638 (inst
->components_read(i
) == 1 &&
6639 lbld
.dispatch_width() <= inst
->exec_size
)) ||
6640 (inst
->flags_written() &
6641 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
6645 * Extract the data that would be consumed by the channel group given by
6646 * lbld.group() from the i-th source region of instruction \p inst and return
6647 * it as result in packed form.
6650 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
6652 assert(lbld
.group() >= inst
->group
);
6654 /* Specified channel group from the source region. */
6655 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group() - inst
->group
);
6657 if (needs_src_copy(lbld
, inst
, i
)) {
6658 /* Builder of the right width to perform the copy avoiding uninitialized
6659 * data if the lowered execution size is greater than the original
6660 * execution size of the instruction.
6662 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
6663 inst
->exec_size
), 0);
6664 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
6666 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
6667 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
6671 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
6672 /* The source is invariant for all dispatch_width-wide groups of the
6675 return inst
->src
[i
];
6678 /* We can just point the lowered instruction at the right channel group
6679 * from the original region.
6686 * Return true if splitting out the group of channels of instruction \p inst
6687 * given by lbld.group() requires allocating a temporary for the destination
6688 * of the lowered instruction and copying the data back to the original
6689 * destination region.
6692 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
6694 /* If the instruction writes more than one component we'll have to shuffle
6695 * the results of multiple lowered instructions in order to make sure that
6696 * they end up arranged correctly in the original destination region.
6698 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
6701 /* If the lowered execution size is larger than the original the result of
6702 * the instruction won't fit in the original destination, so we'll have to
6703 * allocate a temporary in any case.
6705 if (lbld
.dispatch_width() > inst
->exec_size
)
6708 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6709 /* If we already made a copy of the source for other reasons there won't
6710 * be any overlap with the destination.
6712 if (needs_src_copy(lbld
, inst
, i
))
6715 /* In order to keep the logic simple we emit a copy whenever the
6716 * destination region doesn't exactly match an overlapping source, which
6717 * may point at the source and destination not being aligned group by
6718 * group which could cause one of the lowered instructions to overwrite
6719 * the data read from the same source by other lowered instructions.
6721 if (regions_overlap(inst
->dst
, inst
->size_written
,
6722 inst
->src
[i
], inst
->size_read(i
)) &&
6723 !inst
->dst
.equals(inst
->src
[i
]))
6731 * Insert data from a packed temporary into the channel group given by
6732 * lbld.group() of the destination region of instruction \p inst and return
6733 * the temporary as result. Any copy instructions that are required for
6734 * unzipping the previous value (in the case of partial writes) will be
6735 * inserted using \p lbld_before and any copy instructions required for
6736 * zipping up the destination of \p inst will be inserted using \p lbld_after.
6739 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
6742 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
6743 assert(lbld_before
.group() == lbld_after
.group());
6744 assert(lbld_after
.group() >= inst
->group
);
6746 /* Specified channel group from the destination region. */
6747 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group() - inst
->group
);
6748 const unsigned dst_size
= inst
->size_written
/
6749 inst
->dst
.component_size(inst
->exec_size
);
6751 if (needs_dst_copy(lbld_after
, inst
)) {
6752 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
6754 if (inst
->predicate
) {
6755 /* Handle predication by copying the original contents of
6756 * the destination into the temporary before emitting the
6757 * lowered instruction.
6759 const fs_builder gbld_before
=
6760 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
6761 inst
->exec_size
), 0);
6762 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6763 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
6764 offset(dst
, inst
->exec_size
, k
));
6768 const fs_builder gbld_after
=
6769 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
6770 inst
->exec_size
), 0);
6771 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6772 /* Use a builder of the right width to perform the copy avoiding
6773 * uninitialized data if the lowered execution size is greater than
6774 * the original execution size of the instruction.
6776 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
6777 offset(tmp
, lbld_after
, k
));
6783 /* No need to allocate a temporary for the lowered instruction, just
6784 * take the right group of channels from the original region.
6791 fs_visitor::lower_simd_width()
6793 bool progress
= false;
6795 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6796 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
6798 if (lower_width
!= inst
->exec_size
) {
6799 /* Builder matching the original instruction. We may also need to
6800 * emit an instruction of width larger than the original, set the
6801 * execution size of the builder to the highest of both for now so
6802 * we're sure that both cases can be handled.
6804 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
6805 const fs_builder ibld
= bld
.at(block
, inst
)
6806 .exec_all(inst
->force_writemask_all
)
6807 .group(max_width
, inst
->group
/ max_width
);
6809 /* Split the copies in chunks of the execution width of either the
6810 * original or the lowered instruction, whichever is lower.
6812 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
6813 const unsigned dst_size
= inst
->size_written
/
6814 inst
->dst
.component_size(inst
->exec_size
);
6816 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
6818 /* Inserting the zip, unzip, and duplicated instructions in all of
6819 * the right spots is somewhat tricky. All of the unzip and any
6820 * instructions from the zip which unzip the destination prior to
6821 * writing need to happen before all of the per-group instructions
6822 * and the zip instructions need to happen after. In order to sort
6823 * this all out, we insert the unzip instructions before \p inst,
6824 * insert the per-group instructions after \p inst (i.e. before
6825 * inst->next), and insert the zip instructions before the
6826 * instruction after \p inst. Since we are inserting instructions
6827 * after \p inst, inst->next is a moving target and we need to save
6828 * it off here so that we insert the zip instructions in the right
6831 * Since we're inserting split instructions after after_inst, the
6832 * instructions will end up in the reverse order that we insert them.
6833 * However, certain render target writes require that the low group
6834 * instructions come before the high group. From the Ivy Bridge PRM
6835 * Vol. 4, Pt. 1, Section 3.9.11:
6837 * "If multiple SIMD8 Dual Source messages are delivered by the
6838 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
6839 * issued before the SIMD8_DUALSRC_HI message with the same Slot
6840 * Group Select setting."
6842 * And, from Section 3.9.11.1 of the same PRM:
6844 * "When SIMD32 or SIMD16 PS threads send render target writes
6845 * with multiple SIMD8 and SIMD16 messages, the following must
6848 * All the slots (as described above) must have a corresponding
6849 * render target write irrespective of the slot's validity. A slot
6850 * is considered valid when at least one sample is enabled. For
6851 * example, a SIMD16 PS thread must send two SIMD8 render target
6852 * writes to cover all the slots.
6854 * PS thread must send SIMD render target write messages with
6855 * increasing slot numbers. For example, SIMD16 thread has
6856 * Slot[15:0] and if two SIMD8 render target writes are used, the
6857 * first SIMD8 render target write must send Slot[7:0] and the
6858 * next one must send Slot[15:8]."
6860 * In order to make low group instructions come before high group
6861 * instructions (this is required for some render target writes), we
6862 * split from the highest group to lowest.
6864 exec_node
*const after_inst
= inst
->next
;
6865 for (int i
= n
- 1; i
>= 0; i
--) {
6866 /* Emit a copy of the original instruction with the lowered width.
6867 * If the EOT flag was set throw it away except for the last
6868 * instruction to avoid killing the thread prematurely.
6870 fs_inst split_inst
= *inst
;
6871 split_inst
.exec_size
= lower_width
;
6872 split_inst
.eot
= inst
->eot
&& i
== int(n
- 1);
6874 /* Select the correct channel enables for the i-th group, then
6875 * transform the sources and destination and emit the lowered
6878 const fs_builder lbld
= ibld
.group(lower_width
, i
);
6880 for (unsigned j
= 0; j
< inst
->sources
; j
++)
6881 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
6883 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
6884 lbld
.at(block
, after_inst
), inst
);
6885 split_inst
.size_written
=
6886 split_inst
.dst
.component_size(lower_width
) * dst_size
;
6888 lbld
.at(block
, inst
->next
).emit(split_inst
);
6891 inst
->remove(block
);
6897 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
6903 * Transform barycentric vectors into the interleaved form expected by the PLN
6904 * instruction and returned by the Gen7+ PI shared function.
6906 * For channels 0-15 in SIMD16 mode they are expected to be laid out as
6907 * follows in the register file:
6914 * There is no need to handle SIMD32 here -- This is expected to be run after
6915 * SIMD lowering, since SIMD lowering relies on vectors having the standard
6919 fs_visitor::lower_barycentrics()
6921 const bool has_interleaved_layout
= devinfo
->has_pln
|| devinfo
->gen
>= 7;
6922 bool progress
= false;
6924 if (stage
!= MESA_SHADER_FRAGMENT
|| !has_interleaved_layout
)
6927 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6928 if (inst
->exec_size
< 16)
6931 const fs_builder
ibld(this, block
, inst
);
6932 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
6934 switch (inst
->opcode
) {
6935 case FS_OPCODE_LINTERP
: {
6936 assert(inst
->exec_size
== 16);
6937 const fs_reg tmp
= ibld
.vgrf(inst
->src
[0].type
, 2);
6940 for (unsigned i
= 0; i
< ARRAY_SIZE(srcs
); i
++)
6941 srcs
[i
] = horiz_offset(offset(inst
->src
[0], ibld
, i
% 2),
6944 ubld
.LOAD_PAYLOAD(tmp
, srcs
, ARRAY_SIZE(srcs
), ARRAY_SIZE(srcs
));
6950 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6951 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6952 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
: {
6953 assert(inst
->exec_size
== 16);
6954 const fs_reg tmp
= ibld
.vgrf(inst
->dst
.type
, 2);
6956 for (unsigned i
= 0; i
< 2; i
++) {
6957 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
6958 fs_inst
*mov
= ibld
.at(block
, inst
->next
).group(8, g
)
6959 .MOV(horiz_offset(offset(inst
->dst
, ibld
, i
),
6961 offset(tmp
, ubld
, 2 * g
+ i
));
6962 mov
->predicate
= inst
->predicate
;
6963 mov
->predicate_inverse
= inst
->predicate_inverse
;
6964 mov
->flag_subreg
= inst
->flag_subreg
;
6978 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
6984 fs_visitor::dump_instructions() const
6986 dump_instructions(NULL
);
6990 fs_visitor::dump_instructions(const char *name
) const
6992 FILE *file
= stderr
;
6993 if (name
&& geteuid() != 0) {
6994 file
= fopen(name
, "w");
7000 const register_pressure
&rp
= regpressure_analysis
.require();
7001 unsigned ip
= 0, max_pressure
= 0;
7002 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
7003 max_pressure
= MAX2(max_pressure
, rp
.regs_live_at_ip
[ip
]);
7004 fprintf(file
, "{%3d} %4d: ", rp
.regs_live_at_ip
[ip
], ip
);
7005 dump_instruction(inst
, file
);
7008 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
7011 foreach_in_list(backend_instruction
, inst
, &instructions
) {
7012 fprintf(file
, "%4d: ", ip
++);
7013 dump_instruction(inst
, file
);
7017 if (file
!= stderr
) {
7023 fs_visitor::dump_instruction(const backend_instruction
*be_inst
) const
7025 dump_instruction(be_inst
, stderr
);
7029 fs_visitor::dump_instruction(const backend_instruction
*be_inst
, FILE *file
) const
7031 const fs_inst
*inst
= (const fs_inst
*)be_inst
;
7033 if (inst
->predicate
) {
7034 fprintf(file
, "(%cf%d.%d) ",
7035 inst
->predicate_inverse
? '-' : '+',
7036 inst
->flag_subreg
/ 2,
7037 inst
->flag_subreg
% 2);
7040 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
7042 fprintf(file
, ".sat");
7043 if (inst
->conditional_mod
) {
7044 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
7045 if (!inst
->predicate
&&
7046 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
7047 inst
->opcode
!= BRW_OPCODE_CSEL
&&
7048 inst
->opcode
!= BRW_OPCODE_IF
&&
7049 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
7050 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
7051 inst
->flag_subreg
% 2);
7054 fprintf(file
, "(%d) ", inst
->exec_size
);
7057 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
7060 if (inst
->ex_mlen
) {
7061 fprintf(file
, "(ex_mlen: %d) ", inst
->ex_mlen
);
7065 fprintf(file
, "(EOT) ");
7068 switch (inst
->dst
.file
) {
7070 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
7073 fprintf(file
, "g%d", inst
->dst
.nr
);
7076 fprintf(file
, "m%d", inst
->dst
.nr
);
7079 fprintf(file
, "(null)");
7082 fprintf(file
, "***u%d***", inst
->dst
.nr
);
7085 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
7088 switch (inst
->dst
.nr
) {
7090 fprintf(file
, "null");
7092 case BRW_ARF_ADDRESS
:
7093 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
7095 case BRW_ARF_ACCUMULATOR
:
7096 fprintf(file
, "acc%d", inst
->dst
.subnr
);
7099 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7102 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7107 unreachable("not reached");
7110 if (inst
->dst
.offset
||
7111 (inst
->dst
.file
== VGRF
&&
7112 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
7113 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
7114 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
7115 inst
->dst
.offset
% reg_size
);
7118 if (inst
->dst
.stride
!= 1)
7119 fprintf(file
, "<%u>", inst
->dst
.stride
);
7120 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
7122 for (int i
= 0; i
< inst
->sources
; i
++) {
7123 if (inst
->src
[i
].negate
)
7125 if (inst
->src
[i
].abs
)
7127 switch (inst
->src
[i
].file
) {
7129 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
7132 fprintf(file
, "g%d", inst
->src
[i
].nr
);
7135 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
7138 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
7141 fprintf(file
, "u%d", inst
->src
[i
].nr
);
7144 fprintf(file
, "(null)");
7147 switch (inst
->src
[i
].type
) {
7148 case BRW_REGISTER_TYPE_F
:
7149 fprintf(file
, "%-gf", inst
->src
[i
].f
);
7151 case BRW_REGISTER_TYPE_DF
:
7152 fprintf(file
, "%fdf", inst
->src
[i
].df
);
7154 case BRW_REGISTER_TYPE_W
:
7155 case BRW_REGISTER_TYPE_D
:
7156 fprintf(file
, "%dd", inst
->src
[i
].d
);
7158 case BRW_REGISTER_TYPE_UW
:
7159 case BRW_REGISTER_TYPE_UD
:
7160 fprintf(file
, "%uu", inst
->src
[i
].ud
);
7162 case BRW_REGISTER_TYPE_Q
:
7163 fprintf(file
, "%" PRId64
"q", inst
->src
[i
].d64
);
7165 case BRW_REGISTER_TYPE_UQ
:
7166 fprintf(file
, "%" PRIu64
"uq", inst
->src
[i
].u64
);
7168 case BRW_REGISTER_TYPE_VF
:
7169 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
7170 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
7171 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
7172 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
7173 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
7175 case BRW_REGISTER_TYPE_V
:
7176 case BRW_REGISTER_TYPE_UV
:
7177 fprintf(file
, "%08x%s", inst
->src
[i
].ud
,
7178 inst
->src
[i
].type
== BRW_REGISTER_TYPE_V
? "V" : "UV");
7181 fprintf(file
, "???");
7186 switch (inst
->src
[i
].nr
) {
7188 fprintf(file
, "null");
7190 case BRW_ARF_ADDRESS
:
7191 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
7193 case BRW_ARF_ACCUMULATOR
:
7194 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
7197 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7200 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7206 if (inst
->src
[i
].offset
||
7207 (inst
->src
[i
].file
== VGRF
&&
7208 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
7209 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
7210 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
7211 inst
->src
[i
].offset
% reg_size
);
7214 if (inst
->src
[i
].abs
)
7217 if (inst
->src
[i
].file
!= IMM
) {
7219 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
7220 unsigned hstride
= inst
->src
[i
].hstride
;
7221 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
7223 stride
= inst
->src
[i
].stride
;
7226 fprintf(file
, "<%u>", stride
);
7228 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
7231 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
7232 fprintf(file
, ", ");
7237 if (inst
->force_writemask_all
)
7238 fprintf(file
, "NoMask ");
7240 if (inst
->exec_size
!= dispatch_width
)
7241 fprintf(file
, "group%d ", inst
->group
);
7243 fprintf(file
, "\n");
7247 fs_visitor::setup_fs_payload_gen6()
7249 assert(stage
== MESA_SHADER_FRAGMENT
);
7250 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
7251 const unsigned payload_width
= MIN2(16, dispatch_width
);
7252 assert(dispatch_width
% payload_width
== 0);
7253 assert(devinfo
->gen
>= 6);
7255 prog_data
->uses_src_depth
= prog_data
->uses_src_w
=
7256 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) != 0;
7258 prog_data
->uses_sample_mask
=
7259 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
7261 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
7263 * "MSDISPMODE_PERSAMPLE is required in order to select
7266 * So we can only really get sample positions if we are doing real
7267 * per-sample dispatch. If we need gl_SamplePosition and we don't have
7268 * persample dispatch, we hard-code it to 0.5.
7270 prog_data
->uses_pos_offset
= prog_data
->persample_dispatch
&&
7271 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
7273 /* R0: PS thread payload header. */
7276 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7277 /* R1: masks, pixel X/Y coordinates. */
7278 payload
.subspan_coord_reg
[j
] = payload
.num_regs
++;
7281 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7282 /* R3-26: barycentric interpolation coordinates. These appear in the
7283 * same order that they appear in the brw_barycentric_mode enum. Each
7284 * set of coordinates occupies 2 registers if dispatch width == 8 and 4
7285 * registers if dispatch width == 16. Coordinates only appear if they
7286 * were enabled using the "Barycentric Interpolation Mode" bits in
7289 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
7290 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
7291 payload
.barycentric_coord_reg
[i
][j
] = payload
.num_regs
;
7292 payload
.num_regs
+= payload_width
/ 4;
7296 /* R27-28: interpolated depth if uses source depth */
7297 if (prog_data
->uses_src_depth
) {
7298 payload
.source_depth_reg
[j
] = payload
.num_regs
;
7299 payload
.num_regs
+= payload_width
/ 8;
7302 /* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
7303 if (prog_data
->uses_src_w
) {
7304 payload
.source_w_reg
[j
] = payload
.num_regs
;
7305 payload
.num_regs
+= payload_width
/ 8;
7308 /* R31: MSAA position offsets. */
7309 if (prog_data
->uses_pos_offset
) {
7310 payload
.sample_pos_reg
[j
] = payload
.num_regs
;
7314 /* R32-33: MSAA input coverage mask */
7315 if (prog_data
->uses_sample_mask
) {
7316 assert(devinfo
->gen
>= 7);
7317 payload
.sample_mask_in_reg
[j
] = payload
.num_regs
;
7318 payload
.num_regs
+= payload_width
/ 8;
7322 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
7323 source_depth_to_render_target
= true;
7328 fs_visitor::setup_vs_payload()
7330 /* R0: thread header, R1: urb handles */
7331 payload
.num_regs
= 2;
7335 fs_visitor::setup_gs_payload()
7337 assert(stage
== MESA_SHADER_GEOMETRY
);
7339 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
7340 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7342 /* R0: thread header, R1: output URB handles */
7343 payload
.num_regs
= 2;
7345 if (gs_prog_data
->include_primitive_id
) {
7346 /* R2: Primitive ID 0..7 */
7350 /* Always enable VUE handles so we can safely use pull model if needed.
7352 * The push model for a GS uses a ton of register space even for trivial
7353 * scenarios with just a few inputs, so just make things easier and a bit
7354 * safer by always having pull model available.
7356 gs_prog_data
->base
.include_vue_handles
= true;
7358 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
7359 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
7361 /* Use a maximum of 24 registers for push-model inputs. */
7362 const unsigned max_push_components
= 24;
7364 /* If pushing our inputs would take too many registers, reduce the URB read
7365 * length (which is in HWords, or 8 registers), and resort to pulling.
7367 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
7368 * have to multiply by VerticesIn to obtain the total storage requirement.
7370 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
7371 max_push_components
) {
7372 vue_prog_data
->urb_read_length
=
7373 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
7378 fs_visitor::setup_cs_payload()
7380 assert(devinfo
->gen
>= 7);
7381 payload
.num_regs
= 1;
7384 brw::register_pressure::register_pressure(const fs_visitor
*v
)
7386 const fs_live_variables
&live
= v
->live_analysis
.require();
7387 const unsigned num_instructions
= v
->cfg
->num_blocks
?
7388 v
->cfg
->blocks
[v
->cfg
->num_blocks
- 1]->end_ip
+ 1 : 0;
7390 regs_live_at_ip
= new unsigned[num_instructions
]();
7392 for (unsigned reg
= 0; reg
< v
->alloc
.count
; reg
++) {
7393 for (int ip
= live
.vgrf_start
[reg
]; ip
<= live
.vgrf_end
[reg
]; ip
++)
7394 regs_live_at_ip
[ip
] += v
->alloc
.sizes
[reg
];
7398 brw::register_pressure::~register_pressure()
7400 delete[] regs_live_at_ip
;
7404 fs_visitor::invalidate_analysis(brw::analysis_dependency_class c
)
7406 backend_shader::invalidate_analysis(c
);
7407 live_analysis
.invalidate(c
);
7408 regpressure_analysis
.invalidate(c
);
7412 fs_visitor::optimize()
7414 /* Start by validating the shader we currently have. */
7417 /* bld is the common builder object pointing at the end of the program we
7418 * used to translate it into i965 IR. For the optimization and lowering
7419 * passes coming next, any code added after the end of the program without
7420 * having explicitly called fs_builder::at() clearly points at a mistake.
7421 * Ideally optimization passes wouldn't be part of the visitor so they
7422 * wouldn't have access to bld at all, but they do, so just in case some
7423 * pass forgets to ask for a location explicitly set it to NULL here to
7424 * make it trip. The dispatch width is initialized to a bogus value to
7425 * make sure that optimizations set the execution controls explicitly to
7426 * match the code they are manipulating instead of relying on the defaults.
7428 bld
= fs_builder(this, 64);
7430 assign_constant_locations();
7431 lower_constant_loads();
7435 split_virtual_grfs();
7438 #define OPT(pass, args...) ({ \
7440 bool this_progress = pass(args); \
7442 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
7443 char filename[64]; \
7444 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
7445 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
7447 backend_shader::dump_instructions(filename); \
7452 progress = progress || this_progress; \
7456 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
7458 snprintf(filename
, 64, "%s%d-%s-00-00-start",
7459 stage_abbrev
, dispatch_width
, nir
->info
.name
);
7461 backend_shader::dump_instructions(filename
);
7464 bool progress
= false;
7468 /* Before anything else, eliminate dead code. The results of some NIR
7469 * instructions may effectively be calculated twice. Once when the
7470 * instruction is encountered, and again when the user of that result is
7471 * encountered. Wipe those away before algebraic optimizations and
7472 * especially copy propagation can mix things up.
7474 OPT(dead_code_eliminate
);
7476 OPT(remove_extra_rounding_modes
);
7483 OPT(remove_duplicate_mrf_writes
);
7487 OPT(opt_copy_propagation
);
7488 OPT(opt_predicated_break
, this);
7489 OPT(opt_cmod_propagation
);
7490 OPT(dead_code_eliminate
);
7491 OPT(opt_peephole_sel
);
7492 OPT(dead_control_flow_eliminate
, this);
7493 OPT(opt_register_renaming
);
7494 OPT(opt_saturate_propagation
);
7495 OPT(register_coalesce
);
7496 OPT(compute_to_mrf
);
7497 OPT(eliminate_find_live_channel
);
7499 OPT(compact_virtual_grfs
);
7505 if (OPT(lower_pack
)) {
7506 OPT(register_coalesce
);
7507 OPT(dead_code_eliminate
);
7510 OPT(lower_simd_width
);
7511 OPT(lower_barycentrics
);
7513 /* After SIMD lowering just in case we had to unroll the EOT send. */
7514 OPT(opt_sampler_eot
);
7516 OPT(lower_logical_sends
);
7518 /* After logical SEND lowering. */
7519 OPT(fixup_nomask_control_flow
);
7522 OPT(opt_copy_propagation
);
7523 /* Only run after logical send lowering because it's easier to implement
7524 * in terms of physical sends.
7526 if (OPT(opt_zero_samples
))
7527 OPT(opt_copy_propagation
);
7528 /* Run after logical send lowering to give it a chance to CSE the
7529 * LOAD_PAYLOAD instructions created to construct the payloads of
7530 * e.g. texturing messages in cases where it wasn't possible to CSE the
7531 * whole logical instruction.
7534 OPT(register_coalesce
);
7535 OPT(compute_to_mrf
);
7536 OPT(dead_code_eliminate
);
7537 OPT(remove_duplicate_mrf_writes
);
7538 OPT(opt_peephole_sel
);
7541 OPT(opt_redundant_discard_jumps
);
7543 if (OPT(lower_load_payload
)) {
7544 split_virtual_grfs();
7546 /* Lower 64 bit MOVs generated by payload lowering. */
7547 if (!devinfo
->has_64bit_float
&& !devinfo
->has_64bit_int
)
7550 OPT(register_coalesce
);
7551 OPT(lower_simd_width
);
7552 OPT(compute_to_mrf
);
7553 OPT(dead_code_eliminate
);
7556 OPT(opt_combine_constants
);
7557 OPT(lower_integer_multiplication
);
7560 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
7561 OPT(opt_cmod_propagation
);
7563 OPT(opt_copy_propagation
);
7564 OPT(dead_code_eliminate
);
7567 if (OPT(lower_regioning
)) {
7568 OPT(opt_copy_propagation
);
7569 OPT(dead_code_eliminate
);
7570 OPT(lower_simd_width
);
7573 OPT(fixup_sends_duplicate_payload
);
7575 lower_uniform_pull_constant_loads();
7581 * From the Skylake PRM Vol. 2a docs for sends:
7583 * "It is required that the second block of GRFs does not overlap with the
7586 * There are plenty of cases where we may accidentally violate this due to
7587 * having, for instance, both sources be the constant 0. This little pass
7588 * just adds a new vgrf for the second payload and copies it over.
7591 fs_visitor::fixup_sends_duplicate_payload()
7593 bool progress
= false;
7595 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7596 if (inst
->opcode
== SHADER_OPCODE_SEND
&& inst
->ex_mlen
> 0 &&
7597 regions_overlap(inst
->src
[2], inst
->mlen
* REG_SIZE
,
7598 inst
->src
[3], inst
->ex_mlen
* REG_SIZE
)) {
7599 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(inst
->ex_mlen
),
7600 BRW_REGISTER_TYPE_UD
);
7601 /* Sadly, we've lost all notion of channels and bit sizes at this
7602 * point. Just WE_all it.
7604 const fs_builder ibld
= bld
.at(block
, inst
).exec_all().group(16, 0);
7605 fs_reg copy_src
= retype(inst
->src
[3], BRW_REGISTER_TYPE_UD
);
7606 fs_reg copy_dst
= tmp
;
7607 for (unsigned i
= 0; i
< inst
->ex_mlen
; i
+= 2) {
7608 if (inst
->ex_mlen
== i
+ 1) {
7609 /* Only one register left; do SIMD8 */
7610 ibld
.group(8, 0).MOV(copy_dst
, copy_src
);
7612 ibld
.MOV(copy_dst
, copy_src
);
7614 copy_src
= offset(copy_src
, ibld
, 1);
7615 copy_dst
= offset(copy_dst
, ibld
, 1);
7623 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
7629 * Three source instruction must have a GRF/MRF destination register.
7630 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
7633 fs_visitor::fixup_3src_null_dest()
7635 bool progress
= false;
7637 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7638 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
7639 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
7646 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
|
7647 DEPENDENCY_VARIABLES
);
7651 * Find the first instruction in the program that might start a region of
7652 * divergent control flow due to a HALT jump. There is no
7653 * find_halt_control_flow_region_end(), the region of divergence extends until
7654 * the only FS_OPCODE_PLACEHOLDER_HALT in the program.
7656 static const fs_inst
*
7657 find_halt_control_flow_region_start(const fs_visitor
*v
)
7659 if (brw_wm_prog_data(v
->prog_data
)->uses_kill
) {
7660 foreach_block_and_inst(block
, fs_inst
, inst
, v
->cfg
) {
7661 if (inst
->opcode
== FS_OPCODE_DISCARD_JUMP
||
7662 inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
)
7671 * Work around the Gen12 hardware bug filed as GEN:BUG:1407528679. EU fusion
7672 * can cause a BB to be executed with all channels disabled, which will lead
7673 * to the execution of any NoMask instructions in it, even though any
7674 * execution-masked instructions will be correctly shot down. This may break
7675 * assumptions of some NoMask SEND messages whose descriptor depends on data
7676 * generated by live invocations of the shader.
7678 * This avoids the problem by predicating certain instructions on an ANY
7679 * horizontal predicate that makes sure that their execution is omitted when
7680 * all channels of the program are disabled.
7683 fs_visitor::fixup_nomask_control_flow()
7685 if (devinfo
->gen
!= 12)
7688 const brw_predicate pred
= dispatch_width
> 16 ? BRW_PREDICATE_ALIGN1_ANY32H
:
7689 dispatch_width
> 8 ? BRW_PREDICATE_ALIGN1_ANY16H
:
7690 BRW_PREDICATE_ALIGN1_ANY8H
;
7691 const fs_inst
*halt_start
= find_halt_control_flow_region_start(this);
7693 bool progress
= false;
7695 const fs_live_variables
&live_vars
= live_analysis
.require();
7697 /* Scan the program backwards in order to be able to easily determine
7698 * whether the flag register is live at any point.
7700 foreach_block_reverse_safe(block
, cfg
) {
7701 BITSET_WORD flag_liveout
= live_vars
.block_data
[block
->num
]
7703 STATIC_ASSERT(ARRAY_SIZE(live_vars
.block_data
[0].flag_liveout
) == 1);
7705 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
7706 if (!inst
->predicate
&& inst
->exec_size
>= 8)
7707 flag_liveout
&= ~inst
->flags_written();
7709 switch (inst
->opcode
) {
7712 /* Note that this doesn't handle FS_OPCODE_DISCARD_JUMP since only
7713 * the first one in the program closes the region of divergent
7714 * control flow due to any HALT instructions -- Instead this is
7715 * handled with the halt_start check below.
7720 case BRW_OPCODE_WHILE
:
7721 case BRW_OPCODE_ENDIF
:
7722 case FS_OPCODE_PLACEHOLDER_HALT
:
7727 /* Note that the vast majority of NoMask SEND instructions in the
7728 * program are harmless while executed in a block with all
7729 * channels disabled, since any instructions with side effects we
7730 * could hit here should be execution-masked.
7732 * The main concern is NoMask SEND instructions where the message
7733 * descriptor or header depends on data generated by live
7734 * invocations of the shader (RESINFO and
7735 * FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD with a dynamically
7736 * computed surface index seem to be the only examples right now
7737 * where this could easily lead to GPU hangs). Unfortunately we
7738 * have no straightforward way to detect that currently, so just
7739 * predicate any NoMask SEND instructions we find under control
7742 * If this proves to have a measurable performance impact it can
7743 * be easily extended with a whitelist of messages we know we can
7744 * safely omit the predication for.
7746 if (depth
&& inst
->force_writemask_all
&&
7747 is_send(inst
) && !inst
->predicate
) {
7748 /* We need to load the execution mask into the flag register by
7749 * using a builder with channel group matching the whole shader
7750 * (rather than the default which is derived from the original
7751 * instruction), in order to avoid getting a right-shifted
7754 const fs_builder ubld
= fs_builder(this, block
, inst
)
7755 .exec_all().group(dispatch_width
, 0);
7756 const fs_reg flag
= retype(brw_flag_reg(0, 0),
7757 BRW_REGISTER_TYPE_UD
);
7759 /* Due to the lack of flag register allocation we need to save
7760 * and restore the flag register if it's live.
7762 const bool save_flag
= flag_liveout
&
7763 flag_mask(flag
, dispatch_width
/ 8);
7764 const fs_reg tmp
= ubld
.group(1, 0).vgrf(flag
.type
);
7767 ubld
.group(1, 0).MOV(tmp
, flag
);
7769 ubld
.emit(FS_OPCODE_LOAD_LIVE_CHANNELS
);
7771 set_predicate(pred
, inst
);
7772 inst
->flag_subreg
= 0;
7775 ubld
.group(1, 0).at(block
, inst
->next
).MOV(flag
, tmp
);
7782 if (inst
== halt_start
)
7785 flag_liveout
|= inst
->flags_read(devinfo
);
7790 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
7796 fs_visitor::allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
)
7800 static const enum instruction_scheduler_mode pre_modes
[] = {
7802 SCHEDULE_PRE_NON_LIFO
,
7806 static const char *scheduler_mode_name
[] = {
7812 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
7814 /* Try each scheduling heuristic to see if it can successfully register
7815 * allocate without spilling. They should be ordered by decreasing
7816 * performance but increasing likelihood of allocating.
7818 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
7819 schedule_instructions(pre_modes
[i
]);
7820 this->shader_stats
.scheduler_mode
= scheduler_mode_name
[i
];
7823 assign_regs_trivial();
7828 /* Scheduling may create additional opportunities for CMOD propagation,
7829 * so let's do it again. If CMOD propagation made any progress,
7830 * elminate dead code one more time.
7832 bool progress
= false;
7833 const int iteration
= 99;
7836 if (OPT(opt_cmod_propagation
)) {
7837 /* dead_code_eliminate "undoes" the fixing done by
7838 * fixup_3src_null_dest, so we have to do it again if
7839 * dead_code_eliminiate makes any progress.
7841 if (OPT(dead_code_eliminate
))
7842 fixup_3src_null_dest();
7846 /* We only allow spilling for the last schedule mode and only if the
7847 * allow_spilling parameter and dispatch width work out ok.
7849 bool can_spill
= allow_spilling
&&
7850 (i
== ARRAY_SIZE(pre_modes
) - 1) &&
7851 dispatch_width
== min_dispatch_width
;
7853 /* We should only spill registers on the last scheduling. */
7854 assert(!spilled_any_registers
);
7856 allocated
= assign_regs(can_spill
, spill_all
);
7862 if (!allow_spilling
)
7863 fail("Failure to register allocate and spilling is not allowed.");
7865 /* We assume that any spilling is worse than just dropping back to
7866 * SIMD8. There's probably actually some intermediate point where
7867 * SIMD16 with a couple of spills is still better.
7869 if (dispatch_width
> min_dispatch_width
) {
7870 fail("Failure to register allocate. Reduce number of "
7871 "live scalar values to avoid this.");
7874 /* If we failed to allocate, we must have a reason */
7876 } else if (spilled_any_registers
) {
7877 compiler
->shader_perf_log(log_data
,
7878 "%s shader triggered register spilling. "
7879 "Try reducing the number of live scalar "
7880 "values to improve performance.\n",
7884 /* This must come after all optimization and register allocation, since
7885 * it inserts dead code that happens to have side effects, and it does
7886 * so based on the actual physical registers in use.
7888 insert_gen4_send_dependency_workarounds();
7893 opt_bank_conflicts();
7895 schedule_instructions(SCHEDULE_POST
);
7897 if (last_scratch
> 0) {
7898 ASSERTED
unsigned max_scratch_size
= 2 * 1024 * 1024;
7900 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
7902 if (stage
== MESA_SHADER_COMPUTE
) {
7903 if (devinfo
->is_haswell
) {
7904 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7905 * field documentation, Haswell supports a minimum of 2kB of
7906 * scratch space for compute shaders, unlike every other stage
7909 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
7910 } else if (devinfo
->gen
<= 7) {
7911 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7912 * field documentation, platforms prior to Haswell measure scratch
7913 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
7915 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
7916 max_scratch_size
= 12 * 1024;
7920 /* We currently only support up to 2MB of scratch space. If we
7921 * need to support more eventually, the documentation suggests
7922 * that we could allocate a larger buffer, and partition it out
7923 * ourselves. We'd just have to undo the hardware's address
7924 * calculation by subtracting (FFTID * Per Thread Scratch Space)
7925 * and then add FFTID * (Larger Per Thread Scratch Space).
7927 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
7928 * Thread Group Tracking > Local Memory/Scratch Space.
7930 assert(prog_data
->total_scratch
< max_scratch_size
);
7937 fs_visitor::run_vs()
7939 assert(stage
== MESA_SHADER_VERTEX
);
7943 if (shader_time_index
>= 0)
7944 emit_shader_time_begin();
7953 if (shader_time_index
>= 0)
7954 emit_shader_time_end();
7960 assign_curb_setup();
7961 assign_vs_urb_setup();
7963 fixup_3src_null_dest();
7964 allocate_registers(8, true);
7970 fs_visitor::set_tcs_invocation_id()
7972 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7973 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
7975 const unsigned instance_id_mask
=
7976 devinfo
->gen
>= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
7977 const unsigned instance_id_shift
=
7978 devinfo
->gen
>= 11 ? 16 : 17;
7980 /* Get instance number from g0.2 bits 22:16 or 23:17 */
7981 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7982 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
7983 brw_imm_ud(instance_id_mask
));
7985 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7987 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
) {
7988 /* gl_InvocationID is just the thread number */
7989 bld
.SHR(invocation_id
, t
, brw_imm_ud(instance_id_shift
));
7993 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
);
7995 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
7996 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7997 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
7998 bld
.MOV(channels_ud
, channels_uw
);
8000 if (tcs_prog_data
->instances
== 1) {
8001 invocation_id
= channels_ud
;
8003 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
8004 bld
.SHR(instance_times_8
, t
, brw_imm_ud(instance_id_shift
- 3));
8005 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
8010 fs_visitor::run_tcs()
8012 assert(stage
== MESA_SHADER_TESS_CTRL
);
8014 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
8015 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
8016 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
8018 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
||
8019 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
8021 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
8022 /* r1-r4 contain the ICP handles. */
8023 payload
.num_regs
= 5;
8025 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
8026 assert(tcs_key
->input_vertices
> 0);
8027 /* r1 contains output handles, r2 may contain primitive ID, then the
8028 * ICP handles occupy the next 1-32 registers.
8030 payload
.num_regs
= 2 + tcs_prog_data
->include_primitive_id
+
8031 tcs_key
->input_vertices
;
8034 if (shader_time_index
>= 0)
8035 emit_shader_time_begin();
8037 /* Initialize gl_InvocationID */
8038 set_tcs_invocation_id();
8040 const bool fix_dispatch_mask
=
8041 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
&&
8042 (nir
->info
.tess
.tcs_vertices_out
% 8) != 0;
8044 /* Fix the disptach mask */
8045 if (fix_dispatch_mask
) {
8046 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
8047 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
8048 bld
.IF(BRW_PREDICATE_NORMAL
);
8053 if (fix_dispatch_mask
) {
8054 bld
.emit(BRW_OPCODE_ENDIF
);
8057 /* Emit EOT write; set TR DS Cache bit */
8059 fs_reg(get_tcs_output_urb_handle()),
8060 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
8061 fs_reg(brw_imm_ud(0)),
8063 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
8064 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
8066 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
8067 bld
.null_reg_ud(), payload
);
8071 if (shader_time_index
>= 0)
8072 emit_shader_time_end();
8081 assign_curb_setup();
8082 assign_tcs_urb_setup();
8084 fixup_3src_null_dest();
8085 allocate_registers(8, true);
8091 fs_visitor::run_tes()
8093 assert(stage
== MESA_SHADER_TESS_EVAL
);
8095 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
8096 payload
.num_regs
= 5;
8098 if (shader_time_index
>= 0)
8099 emit_shader_time_begin();
8108 if (shader_time_index
>= 0)
8109 emit_shader_time_end();
8115 assign_curb_setup();
8116 assign_tes_urb_setup();
8118 fixup_3src_null_dest();
8119 allocate_registers(8, true);
8125 fs_visitor::run_gs()
8127 assert(stage
== MESA_SHADER_GEOMETRY
);
8131 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
8133 if (gs_compile
->control_data_header_size_bits
> 0) {
8134 /* Create a VGRF to store accumulated control data bits. */
8135 this->control_data_bits
= vgrf(glsl_type::uint_type
);
8137 /* If we're outputting more than 32 control data bits, then EmitVertex()
8138 * will set control_data_bits to 0 after emitting the first vertex.
8139 * Otherwise, we need to initialize it to 0 here.
8141 if (gs_compile
->control_data_header_size_bits
<= 32) {
8142 const fs_builder abld
= bld
.annotate("initialize control data bits");
8143 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
8147 if (shader_time_index
>= 0)
8148 emit_shader_time_begin();
8152 emit_gs_thread_end();
8154 if (shader_time_index
>= 0)
8155 emit_shader_time_end();
8164 assign_curb_setup();
8165 assign_gs_urb_setup();
8167 fixup_3src_null_dest();
8168 allocate_registers(8, true);
8173 /* From the SKL PRM, Volume 16, Workarounds:
8175 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
8176 * only header phases (R0-R2)
8178 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
8179 * have been header only.
8181 * Instead of enabling push constants one can alternatively enable one of the
8182 * inputs. Here one simply chooses "layer" which shouldn't impose much
8186 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
8188 if (wm_prog_data
->num_varying_inputs
)
8191 if (wm_prog_data
->base
.curb_read_length
)
8194 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
8195 wm_prog_data
->num_varying_inputs
= 1;
8197 brw_compute_urb_setup_index(wm_prog_data
);
8201 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
8203 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
8204 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
8206 assert(stage
== MESA_SHADER_FRAGMENT
);
8208 if (devinfo
->gen
>= 6)
8209 setup_fs_payload_gen6();
8211 setup_fs_payload_gen4();
8215 } else if (do_rep_send
) {
8216 assert(dispatch_width
== 16);
8217 emit_repclear_shader();
8219 if (shader_time_index
>= 0)
8220 emit_shader_time_begin();
8222 if (nir
->info
.inputs_read
> 0 ||
8223 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) ||
8224 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
8225 if (devinfo
->gen
< 6)
8226 emit_interpolation_setup_gen4();
8228 emit_interpolation_setup_gen6();
8231 /* We handle discards by keeping track of the still-live pixels in f0.1.
8232 * Initialize it with the dispatched pixels.
8234 if (wm_prog_data
->uses_kill
) {
8235 const unsigned lower_width
= MIN2(dispatch_width
, 16);
8236 for (unsigned i
= 0; i
< dispatch_width
/ lower_width
; i
++) {
8237 const fs_reg dispatch_mask
=
8238 devinfo
->gen
>= 6 ? brw_vec1_grf((i
? 2 : 1), 7) :
8240 bld
.exec_all().group(1, 0)
8241 .MOV(sample_mask_reg(bld
.group(lower_width
, i
)),
8242 retype(dispatch_mask
, BRW_REGISTER_TYPE_UW
));
8251 if (wm_prog_data
->uses_kill
)
8252 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
8254 if (wm_key
->alpha_test_func
)
8259 if (shader_time_index
>= 0)
8260 emit_shader_time_end();
8266 assign_curb_setup();
8268 if (devinfo
->gen
>= 9)
8269 gen9_ps_header_only_workaround(wm_prog_data
);
8273 fixup_3src_null_dest();
8274 allocate_registers(8, allow_spilling
);
8284 fs_visitor::run_cs(unsigned min_dispatch_width
)
8286 assert(stage
== MESA_SHADER_COMPUTE
);
8287 assert(dispatch_width
>= min_dispatch_width
);
8291 if (shader_time_index
>= 0)
8292 emit_shader_time_begin();
8294 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
8295 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
8296 const fs_builder abld
= bld
.exec_all().group(1, 0);
8297 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
8298 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
8306 emit_cs_terminate();
8308 if (shader_time_index
>= 0)
8309 emit_shader_time_end();
8315 assign_curb_setup();
8317 fixup_3src_null_dest();
8318 allocate_registers(min_dispatch_width
, true);
8327 is_used_in_not_interp_frag_coord(nir_ssa_def
*def
)
8329 nir_foreach_use(src
, def
) {
8330 if (src
->parent_instr
->type
!= nir_instr_type_intrinsic
)
8333 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(src
->parent_instr
);
8334 if (intrin
->intrinsic
!= nir_intrinsic_load_frag_coord
)
8338 nir_foreach_if_use(src
, def
)
8345 * Return a bitfield where bit n is set if barycentric interpolation mode n
8346 * (see enum brw_barycentric_mode) is needed by the fragment shader.
8348 * We examine the load_barycentric intrinsics rather than looking at input
8349 * variables so that we catch interpolateAtCentroid() messages too, which
8350 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
8353 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
8354 const nir_shader
*shader
)
8356 unsigned barycentric_interp_modes
= 0;
8358 nir_foreach_function(f
, shader
) {
8362 nir_foreach_block(block
, f
->impl
) {
8363 nir_foreach_instr(instr
, block
) {
8364 if (instr
->type
!= nir_instr_type_intrinsic
)
8367 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8368 switch (intrin
->intrinsic
) {
8369 case nir_intrinsic_load_barycentric_pixel
:
8370 case nir_intrinsic_load_barycentric_centroid
:
8371 case nir_intrinsic_load_barycentric_sample
:
8377 /* Ignore WPOS; it doesn't require interpolation. */
8378 assert(intrin
->dest
.is_ssa
);
8379 if (!is_used_in_not_interp_frag_coord(&intrin
->dest
.ssa
))
8382 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
8383 nir_intrinsic_interp_mode(intrin
);
8384 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
8385 enum brw_barycentric_mode bary
=
8386 brw_barycentric_mode(interp
, bary_op
);
8388 barycentric_interp_modes
|= 1 << bary
;
8390 if (devinfo
->needs_unlit_centroid_workaround
&&
8391 bary_op
== nir_intrinsic_load_barycentric_centroid
)
8392 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
8397 return barycentric_interp_modes
;
8401 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
8402 const nir_shader
*shader
)
8404 prog_data
->flat_inputs
= 0;
8406 nir_foreach_variable(var
, &shader
->inputs
) {
8407 unsigned slots
= glsl_count_attribute_slots(var
->type
, false);
8408 for (unsigned s
= 0; s
< slots
; s
++) {
8409 int input_index
= prog_data
->urb_setup
[var
->data
.location
+ s
];
8411 if (input_index
< 0)
8415 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
8416 prog_data
->flat_inputs
|= 1 << input_index
;
8422 computed_depth_mode(const nir_shader
*shader
)
8424 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
8425 switch (shader
->info
.fs
.depth_layout
) {
8426 case FRAG_DEPTH_LAYOUT_NONE
:
8427 case FRAG_DEPTH_LAYOUT_ANY
:
8428 return BRW_PSCDEPTH_ON
;
8429 case FRAG_DEPTH_LAYOUT_GREATER
:
8430 return BRW_PSCDEPTH_ON_GE
;
8431 case FRAG_DEPTH_LAYOUT_LESS
:
8432 return BRW_PSCDEPTH_ON_LE
;
8433 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
8434 return BRW_PSCDEPTH_OFF
;
8437 return BRW_PSCDEPTH_OFF
;
8441 * Move load_interpolated_input with simple (payload-based) barycentric modes
8442 * to the top of the program so we don't emit multiple PLNs for the same input.
8444 * This works around CSE not being able to handle non-dominating cases
8450 * interpolate the same exact input
8453 * This should be replaced by global value numbering someday.
8456 move_interpolation_to_top(nir_shader
*nir
)
8458 bool progress
= false;
8460 nir_foreach_function(f
, nir
) {
8464 nir_block
*top
= nir_start_block(f
->impl
);
8465 exec_node
*cursor_node
= NULL
;
8467 nir_foreach_block(block
, f
->impl
) {
8471 nir_foreach_instr_safe(instr
, block
) {
8472 if (instr
->type
!= nir_instr_type_intrinsic
)
8475 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8476 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
8478 nir_intrinsic_instr
*bary_intrinsic
=
8479 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
8480 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
8482 /* Leave interpolateAtSample/Offset() where they are. */
8483 if (op
== nir_intrinsic_load_barycentric_at_sample
||
8484 op
== nir_intrinsic_load_barycentric_at_offset
)
8487 nir_instr
*move
[3] = {
8488 &bary_intrinsic
->instr
,
8489 intrin
->src
[1].ssa
->parent_instr
,
8493 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
8494 if (move
[i
]->block
!= top
) {
8495 move
[i
]->block
= top
;
8496 exec_node_remove(&move
[i
]->node
);
8498 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
8500 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
8502 cursor_node
= &move
[i
]->node
;
8508 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8509 ((unsigned) nir_metadata_block_index
|
8510 (unsigned) nir_metadata_dominance
));
8517 * Demote per-sample barycentric intrinsics to centroid.
8519 * Useful when rendering to a non-multisampled buffer.
8522 demote_sample_qualifiers(nir_shader
*nir
)
8524 bool progress
= true;
8526 nir_foreach_function(f
, nir
) {
8531 nir_builder_init(&b
, f
->impl
);
8533 nir_foreach_block(block
, f
->impl
) {
8534 nir_foreach_instr_safe(instr
, block
) {
8535 if (instr
->type
!= nir_instr_type_intrinsic
)
8538 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8539 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
8540 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
8543 b
.cursor
= nir_before_instr(instr
);
8544 nir_ssa_def
*centroid
=
8545 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
8546 nir_intrinsic_interp_mode(intrin
));
8547 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
8548 nir_src_for_ssa(centroid
));
8549 nir_instr_remove(instr
);
8554 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8555 ((unsigned) nir_metadata_block_index
|
8556 (unsigned) nir_metadata_dominance
));
8563 * Pre-gen6, the register file of the EUs was shared between threads,
8564 * and each thread used some subset allocated on a 16-register block
8565 * granularity. The unit states wanted these block counts.
8568 brw_register_blocks(int reg_count
)
8570 return ALIGN(reg_count
, 16) / 16 - 1;
8574 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
8576 const struct brw_wm_prog_key
*key
,
8577 struct brw_wm_prog_data
*prog_data
,
8579 int shader_time_index8
, int shader_time_index16
,
8580 int shader_time_index32
, bool allow_spilling
,
8581 bool use_rep_send
, struct brw_vue_map
*vue_map
,
8582 struct brw_compile_stats
*stats
,
8585 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
8587 unsigned max_subgroup_size
= unlikely(INTEL_DEBUG
& DEBUG_DO32
) ? 32 : 16;
8589 brw_nir_apply_key(shader
, compiler
, &key
->base
, max_subgroup_size
, true);
8590 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
8591 brw_nir_lower_fs_outputs(shader
);
8593 if (devinfo
->gen
< 6)
8594 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
);
8596 /* From the SKL PRM, Volume 7, "Alpha Coverage":
8597 * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
8598 * hardware, regardless of the state setting for this feature."
8600 if (devinfo
->gen
> 6 && key
->alpha_to_coverage
) {
8601 /* Run constant fold optimization in order to get the correct source
8602 * offset to determine render target 0 store instruction in
8603 * emit_alpha_to_coverage pass.
8605 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8606 NIR_PASS_V(shader
, brw_nir_lower_alpha_to_coverage
);
8609 if (!key
->multisample_fbo
)
8610 NIR_PASS_V(shader
, demote_sample_qualifiers
);
8611 NIR_PASS_V(shader
, move_interpolation_to_top
);
8612 brw_postprocess_nir(shader
, compiler
, true);
8614 /* key->alpha_test_func means simulating alpha testing via discards,
8615 * so the shader definitely kills pixels.
8617 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
8618 key
->alpha_test_func
;
8619 prog_data
->uses_omask
= key
->multisample_fbo
&&
8620 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
8621 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
8622 prog_data
->computed_stencil
=
8623 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
8625 prog_data
->persample_dispatch
=
8626 key
->multisample_fbo
&&
8627 (key
->persample_interp
||
8628 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
8629 SYSTEM_BIT_SAMPLE_POS
)) ||
8630 shader
->info
.fs
.uses_sample_qualifier
||
8631 shader
->info
.outputs_read
);
8633 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
8635 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
8636 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
8637 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
8639 prog_data
->barycentric_interp_modes
=
8640 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
8642 calculate_urb_setup(devinfo
, key
, prog_data
, shader
);
8643 brw_compute_flat_inputs(prog_data
, shader
);
8645 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
, *simd32_cfg
= NULL
;
8646 struct shader_stats v8_shader_stats
, v16_shader_stats
, v32_shader_stats
;
8648 fs_visitor
v8(compiler
, log_data
, mem_ctx
, &key
->base
,
8649 &prog_data
->base
, shader
, 8,
8650 shader_time_index8
);
8651 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
8653 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
8656 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
8658 v8_shader_stats
= v8
.shader_stats
;
8659 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
8660 prog_data
->reg_blocks_8
= brw_register_blocks(v8
.grf_used
);
8663 /* Limit dispatch width to simd8 with dual source blending on gen8.
8664 * See: https://gitlab.freedesktop.org/mesa/mesa/issues/1917
8666 if (devinfo
->gen
== 8 && prog_data
->dual_src_blend
&&
8667 !(INTEL_DEBUG
& DEBUG_NO8
)) {
8668 assert(!use_rep_send
);
8669 v8
.limit_dispatch_width(8, "gen8 workaround: "
8670 "using SIMD8 when dual src blending.\n");
8673 if (v8
.max_dispatch_width
>= 16 &&
8674 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
8675 /* Try a SIMD16 compile */
8676 fs_visitor
v16(compiler
, log_data
, mem_ctx
, &key
->base
,
8677 &prog_data
->base
, shader
, 16,
8678 shader_time_index16
);
8679 v16
.import_uniforms(&v8
);
8680 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
8681 compiler
->shader_perf_log(log_data
,
8682 "SIMD16 shader failed to compile: %s",
8685 simd16_cfg
= v16
.cfg
;
8686 v16_shader_stats
= v16
.shader_stats
;
8687 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
8688 prog_data
->reg_blocks_16
= brw_register_blocks(v16
.grf_used
);
8692 /* Currently, the compiler only supports SIMD32 on SNB+ */
8693 if (v8
.max_dispatch_width
>= 32 && !use_rep_send
&&
8694 compiler
->devinfo
->gen
>= 6 &&
8695 unlikely(INTEL_DEBUG
& DEBUG_DO32
)) {
8696 /* Try a SIMD32 compile */
8697 fs_visitor
v32(compiler
, log_data
, mem_ctx
, &key
->base
,
8698 &prog_data
->base
, shader
, 32,
8699 shader_time_index32
);
8700 v32
.import_uniforms(&v8
);
8701 if (!v32
.run_fs(allow_spilling
, false)) {
8702 compiler
->shader_perf_log(log_data
,
8703 "SIMD32 shader failed to compile: %s",
8706 simd32_cfg
= v32
.cfg
;
8707 v32_shader_stats
= v32
.shader_stats
;
8708 prog_data
->dispatch_grf_start_reg_32
= v32
.payload
.num_regs
;
8709 prog_data
->reg_blocks_32
= brw_register_blocks(v32
.grf_used
);
8713 /* When the caller requests a repclear shader, they want SIMD16-only */
8717 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
8718 * at the top to select the shader. We've never implemented that.
8719 * Instead, we just give them exactly one shader and we pick the widest one
8722 if (compiler
->devinfo
->gen
< 5) {
8723 if (simd32_cfg
|| simd16_cfg
)
8729 /* If computed depth is enabled SNB only allows SIMD8. */
8730 if (compiler
->devinfo
->gen
== 6 &&
8731 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
)
8732 assert(simd16_cfg
== NULL
&& simd32_cfg
== NULL
);
8734 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
8735 /* Iron lake and earlier only have one Dispatch GRF start field. Make
8736 * the data available in the base prog data struct for convenience.
8739 prog_data
->base
.dispatch_grf_start_reg
=
8740 prog_data
->dispatch_grf_start_reg_16
;
8741 } else if (simd32_cfg
) {
8742 prog_data
->base
.dispatch_grf_start_reg
=
8743 prog_data
->dispatch_grf_start_reg_32
;
8747 if (prog_data
->persample_dispatch
) {
8748 /* Starting with SandyBridge (where we first get MSAA), the different
8749 * pixel dispatch combinations are grouped into classifications A
8750 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
8751 * generations, the only configurations supporting persample dispatch
8752 * are are this in which only one dispatch width is enabled.
8754 if (simd32_cfg
|| simd16_cfg
)
8760 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8761 v8
.runtime_check_aads_emit
, MESA_SHADER_FRAGMENT
);
8763 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
8764 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
8765 shader
->info
.label
?
8766 shader
->info
.label
: "unnamed",
8767 shader
->info
.name
));
8771 prog_data
->dispatch_8
= true;
8772 g
.generate_code(simd8_cfg
, 8, v8_shader_stats
, stats
);
8773 stats
= stats
? stats
+ 1 : NULL
;
8777 prog_data
->dispatch_16
= true;
8778 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16, v16_shader_stats
, stats
);
8779 stats
= stats
? stats
+ 1 : NULL
;
8783 prog_data
->dispatch_32
= true;
8784 prog_data
->prog_offset_32
= g
.generate_code(simd32_cfg
, 32, v32_shader_stats
, stats
);
8785 stats
= stats
? stats
+ 1 : NULL
;
8788 return g
.get_assembly();
8792 fs_visitor::emit_cs_work_group_id_setup()
8794 assert(stage
== MESA_SHADER_COMPUTE
);
8796 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
8798 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
8799 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
8800 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
8802 bld
.MOV(*reg
, r0_1
);
8803 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
8804 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
8810 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
8812 block
->dwords
= dwords
;
8813 block
->regs
= DIV_ROUND_UP(dwords
, 8);
8814 block
->size
= block
->regs
* 32;
8818 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
8819 struct brw_cs_prog_data
*cs_prog_data
)
8821 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
8822 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
8823 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
8825 /* The thread ID should be stored in the last param dword */
8826 assert(subgroup_id_index
== -1 ||
8827 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
8829 unsigned cross_thread_dwords
, per_thread_dwords
;
8830 if (!cross_thread_supported
) {
8831 cross_thread_dwords
= 0u;
8832 per_thread_dwords
= prog_data
->nr_params
;
8833 } else if (subgroup_id_index
>= 0) {
8834 /* Fill all but the last register with cross-thread payload */
8835 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
8836 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
8837 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
8839 /* Fill all data using cross-thread payload */
8840 cross_thread_dwords
= prog_data
->nr_params
;
8841 per_thread_dwords
= 0u;
8844 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
8845 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
8847 unsigned total_dwords
=
8848 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
8849 cs_prog_data
->push
.cross_thread
.size
) / 4;
8850 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
8852 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
8853 cs_prog_data
->push
.per_thread
.size
== 0);
8854 assert(cs_prog_data
->push
.cross_thread
.dwords
+
8855 cs_prog_data
->push
.per_thread
.dwords
==
8856 prog_data
->nr_params
);
8860 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
8862 cs_prog_data
->simd_size
= size
;
8863 unsigned group_size
= cs_prog_data
->local_size
[0] *
8864 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
8865 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
8869 compile_cs_to_nir(const struct brw_compiler
*compiler
,
8871 const struct brw_cs_prog_key
*key
,
8872 const nir_shader
*src_shader
,
8873 unsigned dispatch_width
)
8875 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
8876 brw_nir_apply_key(shader
, compiler
, &key
->base
, dispatch_width
, true);
8878 NIR_PASS_V(shader
, brw_nir_lower_cs_intrinsics
, dispatch_width
);
8880 /* Clean up after the local index and ID calculations. */
8881 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8882 NIR_PASS_V(shader
, nir_opt_dce
);
8884 brw_postprocess_nir(shader
, compiler
, true);
8890 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
8892 const struct brw_cs_prog_key
*key
,
8893 struct brw_cs_prog_data
*prog_data
,
8894 const nir_shader
*src_shader
,
8895 int shader_time_index
,
8896 struct brw_compile_stats
*stats
,
8899 prog_data
->base
.total_shared
= src_shader
->info
.cs
.shared_size
;
8900 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
8901 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
8902 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
8903 prog_data
->slm_size
= src_shader
->num_shared
;
8904 unsigned local_workgroup_size
=
8905 src_shader
->info
.cs
.local_size
[0] * src_shader
->info
.cs
.local_size
[1] *
8906 src_shader
->info
.cs
.local_size
[2];
8908 /* Limit max_threads to 64 for the GPGPU_WALKER command */
8909 const uint32_t max_threads
= MIN2(64, compiler
->devinfo
->max_cs_threads
);
8910 unsigned min_dispatch_width
=
8911 DIV_ROUND_UP(local_workgroup_size
, max_threads
);
8912 min_dispatch_width
= MAX2(8, min_dispatch_width
);
8913 min_dispatch_width
= util_next_power_of_two(min_dispatch_width
);
8914 assert(min_dispatch_width
<= 32);
8915 unsigned max_dispatch_width
= 32;
8917 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
8918 fs_visitor
*v
= NULL
;
8919 const char *fail_msg
= NULL
;
8921 if ((int)key
->base
.subgroup_size_type
>= (int)BRW_SUBGROUP_SIZE_REQUIRE_8
) {
8922 /* These enum values are expressly chosen to be equal to the subgroup
8923 * size that they require.
8925 const unsigned required_dispatch_width
=
8926 (unsigned)key
->base
.subgroup_size_type
;
8927 assert(required_dispatch_width
== 8 ||
8928 required_dispatch_width
== 16 ||
8929 required_dispatch_width
== 32);
8930 if (required_dispatch_width
< min_dispatch_width
||
8931 required_dispatch_width
> max_dispatch_width
) {
8932 fail_msg
= "Cannot satisfy explicit subgroup size";
8934 min_dispatch_width
= max_dispatch_width
= required_dispatch_width
;
8938 /* Now the main event: Visit the shader IR and generate our CS IR for it.
8940 if (!fail_msg
&& min_dispatch_width
<= 8 && max_dispatch_width
>= 8) {
8941 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8943 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8945 nir8
, 8, shader_time_index
);
8946 if (!v8
->run_cs(min_dispatch_width
)) {
8947 fail_msg
= v8
->fail_msg
;
8949 /* We should always be able to do SIMD32 for compute shaders */
8950 assert(v8
->max_dispatch_width
>= 32);
8953 cs_set_simd_size(prog_data
, 8);
8954 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8958 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
8959 !fail_msg
&& min_dispatch_width
<= 16 && max_dispatch_width
>= 16) {
8960 /* Try a SIMD16 compile */
8961 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8963 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8965 nir16
, 16, shader_time_index
);
8967 v16
->import_uniforms(v8
);
8969 if (!v16
->run_cs(min_dispatch_width
)) {
8970 compiler
->shader_perf_log(log_data
,
8971 "SIMD16 shader failed to compile: %s",
8975 "Couldn't generate SIMD16 program and not "
8976 "enough threads for SIMD8";
8979 /* We should always be able to do SIMD32 for compute shaders */
8980 assert(v16
->max_dispatch_width
>= 32);
8983 cs_set_simd_size(prog_data
, 16);
8984 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
8988 /* We should always be able to do SIMD32 for compute shaders */
8989 assert(!v16
|| v16
->max_dispatch_width
>= 32);
8991 if (!fail_msg
&& (min_dispatch_width
> 16 || (INTEL_DEBUG
& DEBUG_DO32
)) &&
8992 max_dispatch_width
>= 32) {
8993 /* Try a SIMD32 compile */
8994 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8996 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8998 nir32
, 32, shader_time_index
);
9000 v32
->import_uniforms(v8
);
9002 v32
->import_uniforms(v16
);
9004 if (!v32
->run_cs(min_dispatch_width
)) {
9005 compiler
->shader_perf_log(log_data
,
9006 "SIMD32 shader failed to compile: %s",
9010 "Couldn't generate SIMD32 program and not "
9011 "enough threads for SIMD16";
9015 cs_set_simd_size(prog_data
, 32);
9016 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
9020 const unsigned *ret
= NULL
;
9021 if (unlikely(v
== NULL
)) {
9024 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
9026 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
9027 v
->runtime_check_aads_emit
, MESA_SHADER_COMPUTE
);
9028 if (INTEL_DEBUG
& DEBUG_CS
) {
9029 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
9030 src_shader
->info
.label
?
9031 src_shader
->info
.label
: "unnamed",
9032 src_shader
->info
.name
);
9033 g
.enable_debug(name
);
9036 g
.generate_code(v
->cfg
, prog_data
->simd_size
, v
->shader_stats
, stats
);
9038 ret
= g
.get_assembly();
9049 * Test the dispatch mask packing assumptions of
9050 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
9051 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
9052 * executed with an unexpected dispatch mask.
9055 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
9057 const gl_shader_stage stage
= bld
.shader
->stage
;
9059 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
9060 bld
.shader
->stage_prog_data
)) {
9061 const fs_builder ubld
= bld
.exec_all().group(1, 0);
9062 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
9063 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
9066 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
9067 ubld
.AND(tmp
, mask
, tmp
);
9069 /* This will loop forever if the dispatch mask doesn't have the expected
9070 * form '2^n-1', in which case tmp will be non-zero.
9072 bld
.emit(BRW_OPCODE_DO
);
9073 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
9074 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));
9079 fs_visitor::workgroup_size() const
9081 assert(stage
== MESA_SHADER_COMPUTE
);
9082 const struct brw_cs_prog_data
*cs
= brw_cs_prog_data(prog_data
);
9083 return cs
->local_size
[0] * cs
->local_size
[1] * cs
->local_size
[2];