2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
34 #include "brw_fs_live_variables.h"
36 #include "brw_vec4_gs_visitor.h"
38 #include "brw_dead_control_flow.h"
39 #include "dev/gen_debug.h"
40 #include "compiler/glsl_types.h"
41 #include "compiler/nir/nir_builder.h"
42 #include "program/prog_parameter.h"
43 #include "util/u_math.h"
47 static unsigned get_lowered_simd_width(const struct gen_device_info
*devinfo
,
51 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
52 const fs_reg
*src
, unsigned sources
)
54 memset((void*)this, 0, sizeof(*this));
56 this->src
= new fs_reg
[MAX2(sources
, 3)];
57 for (unsigned i
= 0; i
< sources
; i
++)
58 this->src
[i
] = src
[i
];
60 this->opcode
= opcode
;
62 this->sources
= sources
;
63 this->exec_size
= exec_size
;
66 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
68 assert(this->exec_size
!= 0);
70 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
72 /* This will be the case for almost all instructions. */
79 this->size_written
= dst
.component_size(exec_size
);
82 this->size_written
= 0;
86 unreachable("Invalid destination register file");
89 this->writes_accumulator
= false;
94 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
99 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
104 init(opcode
, exec_size
, dst
, NULL
, 0);
107 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg src
[1] = { src0
};
111 init(opcode
, exec_size
, dst
, src
, 1);
114 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
115 const fs_reg
&src0
, const fs_reg
&src1
)
117 const fs_reg src
[2] = { src0
, src1
};
118 init(opcode
, exec_size
, dst
, src
, 2);
121 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
122 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
124 const fs_reg src
[3] = { src0
, src1
, src2
};
125 init(opcode
, exec_size
, dst
, src
, 3);
128 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
129 const fs_reg src
[], unsigned sources
)
131 init(opcode
, exec_width
, dst
, src
, sources
);
134 fs_inst::fs_inst(const fs_inst
&that
)
136 memcpy((void*)this, &that
, sizeof(that
));
138 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
140 for (unsigned i
= 0; i
< that
.sources
; i
++)
141 this->src
[i
] = that
.src
[i
];
150 fs_inst::resize_sources(uint8_t num_sources
)
152 if (this->sources
!= num_sources
) {
153 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
155 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
156 src
[i
] = this->src
[i
];
160 this->sources
= num_sources
;
165 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
167 const fs_reg
&surf_index
,
168 const fs_reg
&varying_offset
,
169 uint32_t const_offset
)
171 /* We have our constant surface use a pitch of 4 bytes, so our index can
172 * be any component of a vector, and then we load 4 contiguous
173 * components starting from that.
175 * We break down the const_offset to a portion added to the variable offset
176 * and a portion done using fs_reg::offset, which means that if you have
177 * GLSL using something like "uniform vec4 a[20]; gl_FragColor = a[i]",
178 * we'll temporarily generate 4 vec4 loads from offset i * 4, and CSE can
179 * later notice that those loads are all the same and eliminate the
182 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
183 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
185 /* The pull load message will load a vec4 (16 bytes). If we are loading
186 * a double this means we are only loading 2 elements worth of data.
187 * We also want to use a 32-bit data type for the dst of the load operation
188 * so other parts of the driver don't get confused about the size of the
191 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
192 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
193 vec4_result
, surf_index
, vec4_offset
);
194 inst
->size_written
= 4 * vec4_result
.component_size(inst
->exec_size
);
196 shuffle_from_32bit_read(bld
, dst
, vec4_result
,
197 (const_offset
& 0xf) / type_sz(dst
.type
), 1);
201 * A helper for MOV generation for fixing up broken hardware SEND dependency
205 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
207 /* The caller always wants uncompressed to emit the minimal extra
208 * dependencies, and to avoid having to deal with aligning its regs to 2.
210 const fs_builder ubld
= bld
.annotate("send dependency resolve")
213 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
217 fs_inst::is_send_from_grf() const
220 case SHADER_OPCODE_SEND
:
221 case SHADER_OPCODE_SHADER_TIME_ADD
:
222 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
223 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
224 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
225 case SHADER_OPCODE_URB_WRITE_SIMD8
:
226 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
227 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
228 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
229 case SHADER_OPCODE_URB_READ_SIMD8
:
230 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
231 case SHADER_OPCODE_INTERLOCK
:
232 case SHADER_OPCODE_MEMORY_FENCE
:
233 case SHADER_OPCODE_BARRIER
:
235 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
236 return src
[1].file
== VGRF
;
237 case FS_OPCODE_FB_WRITE
:
238 case FS_OPCODE_FB_READ
:
239 return src
[0].file
== VGRF
;
242 return src
[0].file
== VGRF
;
249 fs_inst::is_control_source(unsigned arg
) const
252 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
253 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
254 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
257 case SHADER_OPCODE_BROADCAST
:
258 case SHADER_OPCODE_SHUFFLE
:
259 case SHADER_OPCODE_QUAD_SWIZZLE
:
260 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
261 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
262 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
263 case SHADER_OPCODE_GET_BUFFER_SIZE
:
266 case SHADER_OPCODE_MOV_INDIRECT
:
267 case SHADER_OPCODE_CLUSTER_BROADCAST
:
268 case SHADER_OPCODE_TEX
:
270 case SHADER_OPCODE_TXD
:
271 case SHADER_OPCODE_TXF
:
272 case SHADER_OPCODE_TXF_LZ
:
273 case SHADER_OPCODE_TXF_CMS
:
274 case SHADER_OPCODE_TXF_CMS_W
:
275 case SHADER_OPCODE_TXF_UMS
:
276 case SHADER_OPCODE_TXF_MCS
:
277 case SHADER_OPCODE_TXL
:
278 case SHADER_OPCODE_TXL_LZ
:
279 case SHADER_OPCODE_TXS
:
280 case SHADER_OPCODE_LOD
:
281 case SHADER_OPCODE_TG4
:
282 case SHADER_OPCODE_TG4_OFFSET
:
283 case SHADER_OPCODE_SAMPLEINFO
:
284 return arg
== 1 || arg
== 2;
286 case SHADER_OPCODE_SEND
:
287 return arg
== 0 || arg
== 1;
295 fs_inst::is_payload(unsigned arg
) const
298 case FS_OPCODE_FB_WRITE
:
299 case FS_OPCODE_FB_READ
:
300 case SHADER_OPCODE_URB_WRITE_SIMD8
:
301 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
302 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
303 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
304 case SHADER_OPCODE_URB_READ_SIMD8
:
305 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
306 case VEC4_OPCODE_UNTYPED_ATOMIC
:
307 case VEC4_OPCODE_UNTYPED_SURFACE_READ
:
308 case VEC4_OPCODE_UNTYPED_SURFACE_WRITE
:
309 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
310 case SHADER_OPCODE_SHADER_TIME_ADD
:
311 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
312 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
313 case SHADER_OPCODE_INTERLOCK
:
314 case SHADER_OPCODE_MEMORY_FENCE
:
315 case SHADER_OPCODE_BARRIER
:
318 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
321 case SHADER_OPCODE_SEND
:
322 return arg
== 2 || arg
== 3;
333 * Returns true if this instruction's sources and destinations cannot
334 * safely be the same register.
336 * In most cases, a register can be written over safely by the same
337 * instruction that is its last use. For a single instruction, the
338 * sources are dereferenced before writing of the destination starts
341 * However, there are a few cases where this can be problematic:
343 * - Virtual opcodes that translate to multiple instructions in the
344 * code generator: if src == dst and one instruction writes the
345 * destination before a later instruction reads the source, then
346 * src will have been clobbered.
348 * - SIMD16 compressed instructions with certain regioning (see below).
350 * The register allocator uses this information to set up conflicts between
351 * GRF sources and the destination.
354 fs_inst::has_source_and_destination_hazard() const
357 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
358 /* Multiple partial writes to the destination */
360 case SHADER_OPCODE_SHUFFLE
:
361 /* This instruction returns an arbitrary channel from the source and
362 * gets split into smaller instructions in the generator. It's possible
363 * that one of the instructions will read from a channel corresponding
364 * to an earlier instruction.
366 case SHADER_OPCODE_SEL_EXEC
:
367 /* This is implemented as
369 * mov(16) g4<1>D 0D { align1 WE_all 1H };
370 * mov(16) g4<1>D g5<8,8,1>D { align1 1H }
372 * Because the source is only read in the second instruction, the first
373 * may stomp all over it.
376 case SHADER_OPCODE_QUAD_SWIZZLE
:
378 case BRW_SWIZZLE_XXXX
:
379 case BRW_SWIZZLE_YYYY
:
380 case BRW_SWIZZLE_ZZZZ
:
381 case BRW_SWIZZLE_WWWW
:
382 case BRW_SWIZZLE_XXZZ
:
383 case BRW_SWIZZLE_YYWW
:
384 case BRW_SWIZZLE_XYXY
:
385 case BRW_SWIZZLE_ZWZW
:
386 /* These can be implemented as a single Align1 region on all
387 * platforms, so there's never a hazard between source and
388 * destination. C.f. fs_generator::generate_quad_swizzle().
392 return !is_uniform(src
[0]);
395 /* The SIMD16 compressed instruction
397 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
399 * is actually decoded in hardware as:
401 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
402 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
404 * Which is safe. However, if we have uniform accesses
405 * happening, we get into trouble:
407 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
408 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
410 * Now our destination for the first instruction overwrote the
411 * second instruction's src0, and we get garbage for those 8
412 * pixels. There's a similar issue for the pre-gen6
413 * pixel_x/pixel_y, which are registers of 16-bit values and thus
414 * would get stomped by the first decode as well.
416 if (exec_size
== 16) {
417 for (int i
= 0; i
< sources
; i
++) {
418 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
419 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
420 src
[i
].type
== BRW_REGISTER_TYPE_W
||
421 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
422 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
432 fs_inst::can_do_source_mods(const struct gen_device_info
*devinfo
) const
434 if (devinfo
->gen
== 6 && is_math())
437 if (is_send_from_grf())
440 /* From GEN:BUG:1604601757:
442 * "When multiplying a DW and any lower precision integer, source modifier
445 if (devinfo
->gen
>= 12 && (opcode
== BRW_OPCODE_MUL
||
446 opcode
== BRW_OPCODE_MAD
)) {
447 const brw_reg_type exec_type
= get_exec_type(this);
448 const unsigned min_type_sz
= opcode
== BRW_OPCODE_MAD
?
449 MIN2(type_sz(src
[1].type
), type_sz(src
[2].type
)) :
450 MIN2(type_sz(src
[0].type
), type_sz(src
[1].type
));
452 if (brw_reg_type_is_integer(exec_type
) &&
453 type_sz(exec_type
) >= 4 &&
454 type_sz(exec_type
) != min_type_sz
)
458 if (!backend_instruction::can_do_source_mods())
465 fs_inst::can_do_cmod()
467 if (!backend_instruction::can_do_cmod())
470 /* The accumulator result appears to get used for the conditional modifier
471 * generation. When negating a UD value, there is a 33rd bit generated for
472 * the sign in the accumulator value, so now you can't check, for example,
473 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
475 for (unsigned i
= 0; i
< sources
; i
++) {
476 if (type_is_unsigned_int(src
[i
].type
) && src
[i
].negate
)
484 fs_inst::can_change_types() const
486 return dst
.type
== src
[0].type
&&
487 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
488 (opcode
== BRW_OPCODE_MOV
||
489 (opcode
== BRW_OPCODE_SEL
&&
490 dst
.type
== src
[1].type
&&
491 predicate
!= BRW_PREDICATE_NONE
&&
492 !src
[1].abs
&& !src
[1].negate
));
498 memset((void*)this, 0, sizeof(*this));
499 type
= BRW_REGISTER_TYPE_UD
;
503 /** Generic unset register constructor. */
507 this->file
= BAD_FILE
;
510 fs_reg::fs_reg(struct ::brw_reg reg
) :
515 if (this->file
== IMM
&&
516 (this->type
!= BRW_REGISTER_TYPE_V
&&
517 this->type
!= BRW_REGISTER_TYPE_UV
&&
518 this->type
!= BRW_REGISTER_TYPE_VF
)) {
524 fs_reg::equals(const fs_reg
&r
) const
526 return (this->backend_reg::equals(r
) &&
531 fs_reg::negative_equals(const fs_reg
&r
) const
533 return (this->backend_reg::negative_equals(r
) &&
538 fs_reg::is_contiguous() const
543 return hstride
== BRW_HORIZONTAL_STRIDE_1
&&
544 vstride
== width
+ hstride
;
555 unreachable("Invalid register file");
559 fs_reg::component_size(unsigned width
) const
561 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
564 return MAX2(width
* stride
, 1) * type_sz(type
);
568 * Create a MOV to read the timestamp register.
571 fs_visitor::get_timestamp(const fs_builder
&bld
)
573 assert(devinfo
->gen
>= 7);
575 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
578 BRW_REGISTER_TYPE_UD
));
580 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
582 /* We want to read the 3 fields we care about even if it's not enabled in
585 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
591 fs_visitor::emit_shader_time_begin()
593 /* We want only the low 32 bits of the timestamp. Since it's running
594 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
595 * which is plenty of time for our purposes. It is identical across the
596 * EUs, but since it's tracking GPU core speed it will increment at a
597 * varying rate as render P-states change.
599 shader_start_time
= component(
600 get_timestamp(bld
.annotate("shader time start")), 0);
604 fs_visitor::emit_shader_time_end()
606 /* Insert our code just before the final SEND with EOT. */
607 exec_node
*end
= this->instructions
.get_tail();
608 assert(end
&& ((fs_inst
*) end
)->eot
);
609 const fs_builder ibld
= bld
.annotate("shader time end")
610 .exec_all().at(NULL
, end
);
611 const fs_reg timestamp
= get_timestamp(ibld
);
613 /* We only use the low 32 bits of the timestamp - see
614 * emit_shader_time_begin()).
616 * We could also check if render P-states have changed (or anything
617 * else that might disrupt timing) by setting smear to 2 and checking if
618 * that field is != 0.
620 const fs_reg shader_end_time
= component(timestamp
, 0);
622 /* Check that there weren't any timestamp reset events (assuming these
623 * were the only two timestamp reads that happened).
625 const fs_reg reset
= component(timestamp
, 2);
626 set_condmod(BRW_CONDITIONAL_Z
,
627 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
628 ibld
.IF(BRW_PREDICATE_NORMAL
);
630 fs_reg start
= shader_start_time
;
632 const fs_reg diff
= component(fs_reg(VGRF
, alloc
.allocate(1),
633 BRW_REGISTER_TYPE_UD
),
635 const fs_builder cbld
= ibld
.group(1, 0);
636 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
638 /* If there were no instructions between the two timestamp gets, the diff
639 * is 2 cycles. Remove that overhead, so I can forget about that when
640 * trying to determine the time taken for single instructions.
642 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
643 SHADER_TIME_ADD(cbld
, 0, diff
);
644 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
645 ibld
.emit(BRW_OPCODE_ELSE
);
646 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
647 ibld
.emit(BRW_OPCODE_ENDIF
);
651 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
652 int shader_time_subindex
,
655 int index
= shader_time_index
* 3 + shader_time_subindex
;
656 struct brw_reg offset
= brw_imm_d(index
* BRW_SHADER_TIME_STRIDE
);
659 if (dispatch_width
== 8)
660 payload
= vgrf(glsl_type::uvec2_type
);
662 payload
= vgrf(glsl_type::uint_type
);
664 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
668 fs_visitor::vfail(const char *format
, va_list va
)
677 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
678 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
680 this->fail_msg
= msg
;
683 fprintf(stderr
, "%s", msg
);
688 fs_visitor::fail(const char *format
, ...)
692 va_start(va
, format
);
698 * Mark this program as impossible to compile with dispatch width greater
701 * During the SIMD8 compile (which happens first), we can detect and flag
702 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
703 * SIMD16+ compile altogether.
705 * During a compile of dispatch width greater than n (if one happens anyway),
706 * this just calls fail().
709 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
711 if (dispatch_width
> n
) {
714 max_dispatch_width
= n
;
715 compiler
->shader_perf_log(log_data
,
716 "Shader dispatch width limited to SIMD%d: %s",
722 * Returns true if the instruction has a flag that means it won't
723 * update an entire destination register.
725 * For example, dead code elimination and live variable analysis want to know
726 * when a write to a variable screens off any preceding values that were in
730 fs_inst::is_partial_write() const
732 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
733 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
734 !this->dst
.is_contiguous() ||
735 this->dst
.offset
% REG_SIZE
!= 0);
739 fs_inst::components_read(unsigned i
) const
741 /* Return zero if the source is not present. */
742 if (src
[i
].file
== BAD_FILE
)
746 case FS_OPCODE_LINTERP
:
752 case FS_OPCODE_PIXEL_X
:
753 case FS_OPCODE_PIXEL_Y
:
757 case FS_OPCODE_FB_WRITE_LOGICAL
:
758 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
759 /* First/second FB write color. */
761 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
765 case SHADER_OPCODE_TEX_LOGICAL
:
766 case SHADER_OPCODE_TXD_LOGICAL
:
767 case SHADER_OPCODE_TXF_LOGICAL
:
768 case SHADER_OPCODE_TXL_LOGICAL
:
769 case SHADER_OPCODE_TXS_LOGICAL
:
770 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
771 case FS_OPCODE_TXB_LOGICAL
:
772 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
773 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
774 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
775 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
776 case SHADER_OPCODE_LOD_LOGICAL
:
777 case SHADER_OPCODE_TG4_LOGICAL
:
778 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
779 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
780 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
781 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
782 /* Texture coordinates. */
783 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
784 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
785 /* Texture derivatives. */
786 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
787 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
788 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
789 /* Texture offset. */
790 else if (i
== TEX_LOGICAL_SRC_TG4_OFFSET
)
793 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
798 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
799 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
800 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
);
801 /* Surface coordinates. */
802 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
803 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
804 /* Surface operation source (ignored for reads). */
805 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
810 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
811 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
812 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
813 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
814 /* Surface coordinates. */
815 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
816 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
817 /* Surface operation source. */
818 else if (i
== SURFACE_LOGICAL_SRC_DATA
)
819 return src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
823 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
824 assert(src
[2].file
== IMM
);
827 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
828 assert(src
[2].file
== IMM
);
829 return i
== 1 ? src
[2].ud
: 1;
831 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
832 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
833 assert(src
[2].file
== IMM
);
836 const unsigned op
= src
[2].ud
;
851 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
852 assert(src
[2].file
== IMM
);
855 const unsigned op
= src
[2].ud
;
856 return op
== BRW_AOP_FCMPWR
? 2 : 1;
861 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
862 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
863 /* Scattered logical opcodes use the following params:
864 * src[0] Surface coordinates
865 * src[1] Surface operation source (ignored for reads)
867 * src[3] IMM with always 1 dimension.
868 * src[4] IMM with arg bitsize for scattered read/write 8, 16, 32
870 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
871 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
872 return i
== SURFACE_LOGICAL_SRC_DATA
? 0 : 1;
874 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
875 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
876 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
877 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
880 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
881 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
882 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
883 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
884 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
885 /* Surface coordinates. */
886 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
887 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
888 /* Surface operation source. */
889 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_CMPWR
)
891 else if (i
== SURFACE_LOGICAL_SRC_DATA
&&
892 (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
|| op
== BRW_AOP_PREDEC
))
897 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
898 return (i
== 0 ? 2 : 1);
900 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
: {
901 assert(src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].file
== IMM
&&
902 src
[SURFACE_LOGICAL_SRC_IMM_ARG
].file
== IMM
);
903 const unsigned op
= src
[SURFACE_LOGICAL_SRC_IMM_ARG
].ud
;
904 /* Surface coordinates. */
905 if (i
== SURFACE_LOGICAL_SRC_ADDRESS
)
906 return src
[SURFACE_LOGICAL_SRC_IMM_DIMS
].ud
;
907 /* Surface operation source. */
908 else if (i
== SURFACE_LOGICAL_SRC_DATA
&& op
== BRW_AOP_FCMPWR
)
920 fs_inst::size_read(int arg
) const
923 case SHADER_OPCODE_SEND
:
925 return mlen
* REG_SIZE
;
926 } else if (arg
== 3) {
927 return ex_mlen
* REG_SIZE
;
931 case FS_OPCODE_FB_WRITE
:
932 case FS_OPCODE_REP_FB_WRITE
:
935 return src
[0].file
== BAD_FILE
? 0 : 2 * REG_SIZE
;
937 return mlen
* REG_SIZE
;
941 case FS_OPCODE_FB_READ
:
942 case SHADER_OPCODE_URB_WRITE_SIMD8
:
943 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
944 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
945 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
946 case SHADER_OPCODE_URB_READ_SIMD8
:
947 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
948 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
949 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
951 return mlen
* REG_SIZE
;
954 case FS_OPCODE_SET_SAMPLE_ID
:
959 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
960 /* The payload is actually stored in src1 */
962 return mlen
* REG_SIZE
;
965 case FS_OPCODE_LINTERP
:
970 case SHADER_OPCODE_LOAD_PAYLOAD
:
971 if (arg
< this->header_size
)
975 case CS_OPCODE_CS_TERMINATE
:
976 case SHADER_OPCODE_BARRIER
:
979 case SHADER_OPCODE_MOV_INDIRECT
:
981 assert(src
[2].file
== IMM
);
987 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
988 return mlen
* REG_SIZE
;
992 switch (src
[arg
].file
) {
995 return components_read(arg
) * type_sz(src
[arg
].type
);
1001 return components_read(arg
) * src
[arg
].component_size(exec_size
);
1003 unreachable("MRF registers are not allowed as sources");
1010 predicate_width(brw_predicate predicate
)
1012 switch (predicate
) {
1013 case BRW_PREDICATE_NONE
: return 1;
1014 case BRW_PREDICATE_NORMAL
: return 1;
1015 case BRW_PREDICATE_ALIGN1_ANY2H
: return 2;
1016 case BRW_PREDICATE_ALIGN1_ALL2H
: return 2;
1017 case BRW_PREDICATE_ALIGN1_ANY4H
: return 4;
1018 case BRW_PREDICATE_ALIGN1_ALL4H
: return 4;
1019 case BRW_PREDICATE_ALIGN1_ANY8H
: return 8;
1020 case BRW_PREDICATE_ALIGN1_ALL8H
: return 8;
1021 case BRW_PREDICATE_ALIGN1_ANY16H
: return 16;
1022 case BRW_PREDICATE_ALIGN1_ALL16H
: return 16;
1023 case BRW_PREDICATE_ALIGN1_ANY32H
: return 32;
1024 case BRW_PREDICATE_ALIGN1_ALL32H
: return 32;
1025 default: unreachable("Unsupported predicate");
1029 /* Return the subset of flag registers that an instruction could
1030 * potentially read or write based on the execution controls and flag
1031 * subregister number of the instruction.
1034 flag_mask(const fs_inst
*inst
, unsigned width
)
1036 assert(util_is_power_of_two_nonzero(width
));
1037 const unsigned start
= (inst
->flag_subreg
* 16 + inst
->group
) &
1039 const unsigned end
= start
+ ALIGN(inst
->exec_size
, width
);
1040 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
1044 bit_mask(unsigned n
)
1046 return (n
>= CHAR_BIT
* sizeof(bit_mask(n
)) ? ~0u : (1u << n
) - 1);
1050 flag_mask(const fs_reg
&r
, unsigned sz
)
1052 if (r
.file
== ARF
) {
1053 const unsigned start
= (r
.nr
- BRW_ARF_FLAG
) * 4 + r
.subnr
;
1054 const unsigned end
= start
+ sz
;
1055 return bit_mask(end
) & ~bit_mask(start
);
1063 fs_inst::flags_read(const gen_device_info
*devinfo
) const
1065 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
1066 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
1067 /* The vertical predication modes combine corresponding bits from
1068 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
1070 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
1071 return flag_mask(this, 1) << shift
| flag_mask(this, 1);
1072 } else if (predicate
) {
1073 return flag_mask(this, predicate_width(predicate
));
1076 for (int i
= 0; i
< sources
; i
++) {
1077 mask
|= flag_mask(src
[i
], size_read(i
));
1084 fs_inst::flags_written() const
1086 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1087 opcode
!= BRW_OPCODE_CSEL
&&
1088 opcode
!= BRW_OPCODE_IF
&&
1089 opcode
!= BRW_OPCODE_WHILE
)) ||
1090 opcode
== FS_OPCODE_FB_WRITE
) {
1091 return flag_mask(this, 1);
1092 } else if (opcode
== SHADER_OPCODE_FIND_LIVE_CHANNEL
||
1093 opcode
== FS_OPCODE_LOAD_LIVE_CHANNELS
) {
1094 return flag_mask(this, 32);
1096 return flag_mask(dst
, size_written
);
1101 * Returns how many MRFs an FS opcode will write over.
1103 * Note that this is not the 0 or 1 implied writes in an actual gen
1104 * instruction -- the FS opcodes often generate MOVs in addition.
1107 fs_inst::implied_mrf_writes() const
1116 case SHADER_OPCODE_RCP
:
1117 case SHADER_OPCODE_RSQ
:
1118 case SHADER_OPCODE_SQRT
:
1119 case SHADER_OPCODE_EXP2
:
1120 case SHADER_OPCODE_LOG2
:
1121 case SHADER_OPCODE_SIN
:
1122 case SHADER_OPCODE_COS
:
1123 return 1 * exec_size
/ 8;
1124 case SHADER_OPCODE_POW
:
1125 case SHADER_OPCODE_INT_QUOTIENT
:
1126 case SHADER_OPCODE_INT_REMAINDER
:
1127 return 2 * exec_size
/ 8;
1128 case SHADER_OPCODE_TEX
:
1130 case SHADER_OPCODE_TXD
:
1131 case SHADER_OPCODE_TXF
:
1132 case SHADER_OPCODE_TXF_CMS
:
1133 case SHADER_OPCODE_TXF_MCS
:
1134 case SHADER_OPCODE_TG4
:
1135 case SHADER_OPCODE_TG4_OFFSET
:
1136 case SHADER_OPCODE_TXL
:
1137 case SHADER_OPCODE_TXS
:
1138 case SHADER_OPCODE_LOD
:
1139 case SHADER_OPCODE_SAMPLEINFO
:
1141 case FS_OPCODE_FB_WRITE
:
1142 case FS_OPCODE_REP_FB_WRITE
:
1143 return src
[0].file
== BAD_FILE
? 0 : 2;
1144 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1145 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1147 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
1149 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1152 unreachable("not reached");
1157 fs_visitor::vgrf(const glsl_type
*const type
)
1159 int reg_width
= dispatch_width
/ 8;
1161 alloc
.allocate(glsl_count_dword_slots(type
, false) * reg_width
),
1162 brw_type_for_base_type(type
));
1165 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1170 this->type
= BRW_REGISTER_TYPE_F
;
1171 this->stride
= (file
== UNIFORM
? 0 : 1);
1174 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1180 this->stride
= (file
== UNIFORM
? 0 : 1);
1183 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1184 * This brings in those uniform definitions
1187 fs_visitor::import_uniforms(fs_visitor
*v
)
1189 this->push_constant_loc
= v
->push_constant_loc
;
1190 this->pull_constant_loc
= v
->pull_constant_loc
;
1191 this->uniforms
= v
->uniforms
;
1192 this->subgroup_id
= v
->subgroup_id
;
1193 for (unsigned i
= 0; i
< ARRAY_SIZE(this->group_size
); i
++)
1194 this->group_size
[i
] = v
->group_size
[i
];
1198 fs_visitor::emit_fragcoord_interpolation(fs_reg wpos
)
1200 assert(stage
== MESA_SHADER_FRAGMENT
);
1202 /* gl_FragCoord.x */
1203 bld
.MOV(wpos
, this->pixel_x
);
1204 wpos
= offset(wpos
, bld
, 1);
1206 /* gl_FragCoord.y */
1207 bld
.MOV(wpos
, this->pixel_y
);
1208 wpos
= offset(wpos
, bld
, 1);
1210 /* gl_FragCoord.z */
1211 if (devinfo
->gen
>= 6) {
1212 bld
.MOV(wpos
, fetch_payload_reg(bld
, payload
.source_depth_reg
));
1214 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1215 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1216 component(interp_reg(VARYING_SLOT_POS
, 2), 0));
1218 wpos
= offset(wpos
, bld
, 1);
1220 /* gl_FragCoord.w: Already set up in emit_interpolation */
1221 bld
.MOV(wpos
, this->wpos_w
);
1224 enum brw_barycentric_mode
1225 brw_barycentric_mode(enum glsl_interp_mode mode
, nir_intrinsic_op op
)
1227 /* Barycentric modes don't make sense for flat inputs. */
1228 assert(mode
!= INTERP_MODE_FLAT
);
1232 case nir_intrinsic_load_barycentric_pixel
:
1233 case nir_intrinsic_load_barycentric_at_offset
:
1234 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1236 case nir_intrinsic_load_barycentric_centroid
:
1237 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1239 case nir_intrinsic_load_barycentric_sample
:
1240 case nir_intrinsic_load_barycentric_at_sample
:
1241 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1244 unreachable("invalid intrinsic");
1247 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1250 return (enum brw_barycentric_mode
) bary
;
1254 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1256 static enum brw_barycentric_mode
1257 centroid_to_pixel(enum brw_barycentric_mode bary
)
1259 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1260 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1261 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1265 fs_visitor::emit_frontfacing_interpolation()
1267 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1269 if (devinfo
->gen
>= 12) {
1270 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
1272 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1273 bld
.ASR(tmp
, g1
, brw_imm_d(15));
1275 } else if (devinfo
->gen
>= 6) {
1276 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1277 * a boolean result from this (~0/true or 0/false).
1279 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1280 * this task in only one instruction:
1281 * - a negation source modifier will flip the bit; and
1282 * - a W -> D type conversion will sign extend the bit into the high
1283 * word of the destination.
1285 * An ASR 15 fills the low word of the destination.
1287 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1290 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1292 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1293 * a boolean result from this (1/true or 0/false).
1295 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1296 * the negation source modifier to flip it. Unfortunately the SHR
1297 * instruction only operates on UD (or D with an abs source modifier)
1298 * sources without negation.
1300 * Instead, use ASR (which will give ~0/true or 0/false).
1302 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1305 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1312 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1314 assert(stage
== MESA_SHADER_FRAGMENT
);
1315 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1316 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1318 if (wm_prog_data
->persample_dispatch
) {
1319 /* Convert int_sample_pos to floating point */
1320 bld
.MOV(dst
, int_sample_pos
);
1321 /* Scale to the range [0, 1] */
1322 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1325 /* From ARB_sample_shading specification:
1326 * "When rendering to a non-multisample buffer, or if multisample
1327 * rasterization is disabled, gl_SamplePosition will always be
1330 bld
.MOV(dst
, brw_imm_f(0.5f
));
1335 fs_visitor::emit_samplepos_setup()
1337 assert(devinfo
->gen
>= 6);
1339 const fs_builder abld
= bld
.annotate("compute sample position");
1340 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1342 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1343 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1345 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1346 * mode will be enabled.
1348 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1349 * R31.1:0 Position Offset X/Y for Slot[3:0]
1350 * R31.3:2 Position Offset X/Y for Slot[7:4]
1353 * The X, Y sample positions come in as bytes in thread payload. So, read
1354 * the positions using vstride=16, width=8, hstride=2.
1356 const fs_reg sample_pos_reg
=
1357 fetch_payload_reg(abld
, payload
.sample_pos_reg
, BRW_REGISTER_TYPE_W
);
1359 /* Compute gl_SamplePosition.x */
1360 abld
.MOV(int_sample_x
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 0));
1361 compute_sample_position(offset(pos
, abld
, 0), int_sample_x
);
1363 /* Compute gl_SamplePosition.y */
1364 abld
.MOV(int_sample_y
, subscript(sample_pos_reg
, BRW_REGISTER_TYPE_B
, 1));
1365 compute_sample_position(offset(pos
, abld
, 1), int_sample_y
);
1370 fs_visitor::emit_sampleid_setup()
1372 assert(stage
== MESA_SHADER_FRAGMENT
);
1373 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1374 assert(devinfo
->gen
>= 6);
1376 const fs_builder abld
= bld
.annotate("compute sample id");
1377 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uint_type
));
1379 if (!key
->multisample_fbo
) {
1380 /* As per GL_ARB_sample_shading specification:
1381 * "When rendering to a non-multisample buffer, or if multisample
1382 * rasterization is disabled, gl_SampleID will always be zero."
1384 abld
.MOV(*reg
, brw_imm_d(0));
1385 } else if (devinfo
->gen
>= 8) {
1386 /* Sample ID comes in as 4-bit numbers in g1.0:
1388 * 15:12 Slot 3 SampleID (only used in SIMD16)
1389 * 11:8 Slot 2 SampleID (only used in SIMD16)
1390 * 7:4 Slot 1 SampleID
1391 * 3:0 Slot 0 SampleID
1393 * Each slot corresponds to four channels, so we want to replicate each
1394 * half-byte value to 4 channels in a row:
1396 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1397 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1399 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1400 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1402 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1403 * channels to read the first byte (7:0), and the second group of 8
1404 * channels to read the second byte (15:8). Then, we shift right by
1405 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1406 * values into place. Finally, we AND with 0xf to keep the low nibble.
1408 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1409 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1411 * TODO: These payload bits exist on Gen7 too, but they appear to always
1412 * be zero, so this code fails to work. We should find out why.
1414 const fs_reg tmp
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1416 for (unsigned i
= 0; i
< DIV_ROUND_UP(dispatch_width
, 16); i
++) {
1417 const fs_builder hbld
= abld
.group(MIN2(16, dispatch_width
), i
);
1418 hbld
.SHR(offset(tmp
, hbld
, i
),
1419 stride(retype(brw_vec1_grf(1 + i
, 0), BRW_REGISTER_TYPE_UB
),
1421 brw_imm_v(0x44440000));
1424 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1426 const fs_reg t1
= component(abld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
1427 const fs_reg t2
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
1429 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1430 * 8x multisampling, subspan 0 will represent sample N (where N
1431 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1432 * 7. We can find the value of N by looking at R0.0 bits 7:6
1433 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1434 * (since samples are always delivered in pairs). That is, we
1435 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1436 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1437 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1438 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1439 * populating a temporary variable with the sequence (0, 1, 2, 3),
1440 * and then reading from it using vstride=1, width=4, hstride=0.
1441 * These computations hold good for 4x multisampling as well.
1443 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1444 * the first four slots are sample 0 of subspan 0; the next four
1445 * are sample 1 of subspan 0; the third group is sample 0 of
1446 * subspan 1, and finally sample 1 of subspan 1.
1449 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1450 * accomodate 16x MSAA.
1452 abld
.exec_all().group(1, 0)
1453 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1455 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1457 /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we
1458 * can assume 4x MSAA. Disallow it on IVB+
1460 * FINISHME: One day, we could come up with a way to do this that
1461 * actually works on gen7.
1463 if (devinfo
->gen
>= 7)
1464 limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gen7");
1465 abld
.exec_all().group(8, 0).MOV(t2
, brw_imm_v(0x32103210));
1467 /* This special instruction takes care of setting vstride=1,
1468 * width=4, hstride=0 of t2 during an ADD instruction.
1470 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1477 fs_visitor::emit_samplemaskin_setup()
1479 assert(stage
== MESA_SHADER_FRAGMENT
);
1480 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
1481 assert(devinfo
->gen
>= 6);
1483 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1485 fs_reg coverage_mask
=
1486 fetch_payload_reg(bld
, payload
.sample_mask_in_reg
, BRW_REGISTER_TYPE_D
);
1488 if (wm_prog_data
->persample_dispatch
) {
1489 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1490 * and a mask representing which sample is being processed by the
1491 * current shader invocation.
1493 * From the OES_sample_variables specification:
1494 * "When per-sample shading is active due to the use of a fragment input
1495 * qualified by "sample" or due to the use of the gl_SampleID or
1496 * gl_SamplePosition variables, only the bit for the current sample is
1497 * set in gl_SampleMaskIn."
1499 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1501 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1502 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1504 fs_reg one
= vgrf(glsl_type::int_type
);
1505 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1506 abld
.MOV(one
, brw_imm_d(1));
1507 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1508 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1510 /* In per-pixel mode, the coverage mask is sufficient. */
1511 *reg
= coverage_mask
;
1517 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1519 if (!src
.abs
&& !src
.negate
)
1522 fs_reg temp
= bld
.vgrf(src
.type
);
1529 fs_visitor::emit_discard_jump()
1531 assert(brw_wm_prog_data(this->prog_data
)->uses_kill
);
1533 /* For performance, after a discard, jump to the end of the
1534 * shader if all relevant channels have been discarded.
1536 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1537 discard_jump
->flag_subreg
= sample_mask_flag_subreg(this);
1539 discard_jump
->predicate
= BRW_PREDICATE_ALIGN1_ANY4H
;
1540 discard_jump
->predicate_inverse
= true;
1544 fs_visitor::emit_gs_thread_end()
1546 assert(stage
== MESA_SHADER_GEOMETRY
);
1548 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1550 if (gs_compile
->control_data_header_size_bits
> 0) {
1551 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1554 const fs_builder abld
= bld
.annotate("thread end");
1557 if (gs_prog_data
->static_vertex_count
!= -1) {
1558 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1559 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1560 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1561 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1562 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1565 /* Delete now dead instructions. */
1566 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1572 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1576 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1577 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1578 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1581 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1582 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1583 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1584 sources
[1] = this->final_gs_vertex_count
;
1585 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1586 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1594 fs_visitor::assign_curb_setup()
1596 unsigned uniform_push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
1598 unsigned ubo_push_length
= 0;
1599 unsigned ubo_push_start
[4];
1600 for (int i
= 0; i
< 4; i
++) {
1601 ubo_push_start
[i
] = 8 * (ubo_push_length
+ uniform_push_length
);
1602 ubo_push_length
+= stage_prog_data
->ubo_ranges
[i
].length
;
1605 prog_data
->curb_read_length
= uniform_push_length
+ ubo_push_length
;
1609 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1610 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1611 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1612 if (inst
->src
[i
].file
== UNIFORM
) {
1613 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ 4;
1615 if (inst
->src
[i
].nr
>= UBO_START
) {
1616 /* constant_nr is in 32-bit units, the rest are in bytes */
1617 constant_nr
= ubo_push_start
[inst
->src
[i
].nr
- UBO_START
] +
1618 inst
->src
[i
].offset
/ 4;
1619 } else if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1620 constant_nr
= push_constant_loc
[uniform_nr
];
1622 /* Section 5.11 of the OpenGL 4.1 spec says:
1623 * "Out-of-bounds reads return undefined values, which include
1624 * values from other variables of the active program or zero."
1625 * Just return the first push constant.
1630 assert(constant_nr
/ 8 < 64);
1631 used
|= BITFIELD64_BIT(constant_nr
/ 8);
1633 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1636 brw_reg
.abs
= inst
->src
[i
].abs
;
1637 brw_reg
.negate
= inst
->src
[i
].negate
;
1639 assert(inst
->src
[i
].stride
== 0);
1640 inst
->src
[i
] = byte_offset(
1641 retype(brw_reg
, inst
->src
[i
].type
),
1642 inst
->src
[i
].offset
% 4);
1647 uint64_t want_zero
= used
& stage_prog_data
->zero_push_reg
;
1649 assert(!compiler
->compact_params
);
1650 fs_builder ubld
= bld
.exec_all().group(8, 0).at(
1651 cfg
->first_block(), cfg
->first_block()->start());
1653 /* push_reg_mask_param is in 32-bit units */
1654 unsigned mask_param
= stage_prog_data
->push_reg_mask_param
;
1655 struct brw_reg mask
= brw_vec1_grf(payload
.num_regs
+ mask_param
/ 8,
1659 for (unsigned i
= 0; i
< 64; i
++) {
1660 if (i
% 16 == 0 && (want_zero
& BITFIELD64_RANGE(i
, 16))) {
1661 fs_reg shifted
= ubld
.vgrf(BRW_REGISTER_TYPE_W
, 2);
1662 ubld
.SHL(horiz_offset(shifted
, 8),
1663 byte_offset(retype(mask
, BRW_REGISTER_TYPE_W
), i
/ 8),
1664 brw_imm_v(0x01234567));
1665 ubld
.SHL(shifted
, horiz_offset(shifted
, 8), brw_imm_w(8));
1667 fs_builder ubld16
= ubld
.group(16, 0);
1668 b32
= ubld16
.vgrf(BRW_REGISTER_TYPE_D
);
1669 ubld16
.group(16, 0).ASR(b32
, shifted
, brw_imm_w(15));
1672 if (want_zero
& BITFIELD64_BIT(i
)) {
1673 assert(i
< prog_data
->curb_read_length
);
1674 struct brw_reg push_reg
=
1675 retype(brw_vec8_grf(payload
.num_regs
+ i
, 0),
1676 BRW_REGISTER_TYPE_D
);
1678 ubld
.AND(push_reg
, push_reg
, component(b32
, i
% 16));
1682 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
1685 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1686 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1690 * Build up an array of indices into the urb_setup array that
1691 * references the active entries of the urb_setup array.
1692 * Used to accelerate walking the active entries of the urb_setup array
1696 brw_compute_urb_setup_index(struct brw_wm_prog_data
*wm_prog_data
)
1698 /* Make sure uint8_t is sufficient */
1699 STATIC_ASSERT(VARYING_SLOT_MAX
<= 0xff);
1701 for (uint8_t attr
= 0; attr
< VARYING_SLOT_MAX
; attr
++) {
1702 if (wm_prog_data
->urb_setup
[attr
] >= 0) {
1703 wm_prog_data
->urb_setup_attribs
[index
++] = attr
;
1706 wm_prog_data
->urb_setup_attribs_count
= index
;
1710 calculate_urb_setup(const struct gen_device_info
*devinfo
,
1711 const struct brw_wm_prog_key
*key
,
1712 struct brw_wm_prog_data
*prog_data
,
1713 const nir_shader
*nir
)
1715 memset(prog_data
->urb_setup
, -1,
1716 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1719 /* Figure out where each of the incoming setup attributes lands. */
1720 if (devinfo
->gen
>= 6) {
1721 if (util_bitcount64(nir
->info
.inputs_read
&
1722 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1723 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1724 * first 16 varying inputs, so we can put them wherever we want.
1725 * Just put them in order.
1727 * This is useful because it means that (a) inputs not used by the
1728 * fragment shader won't take up valuable register space, and (b) we
1729 * won't have to recompile the fragment shader if it gets paired with
1730 * a different vertex (or geometry) shader.
1732 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1733 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1734 BITFIELD64_BIT(i
)) {
1735 prog_data
->urb_setup
[i
] = urb_next
++;
1739 /* We have enough input varyings that the SF/SBE pipeline stage can't
1740 * arbitrarily rearrange them to suit our whim; we have to put them
1741 * in an order that matches the output of the previous pipeline stage
1742 * (geometry or vertex shader).
1744 struct brw_vue_map prev_stage_vue_map
;
1745 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1746 key
->input_slots_valid
,
1747 nir
->info
.separate_shader
, 1);
1750 brw_compute_first_urb_slot_required(nir
->info
.inputs_read
,
1751 &prev_stage_vue_map
);
1753 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1754 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1756 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1757 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1758 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1759 BITFIELD64_BIT(varying
))) {
1760 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1763 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1766 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1767 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1768 /* Point size is packed into the header, not as a general attribute */
1769 if (i
== VARYING_SLOT_PSIZ
)
1772 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1773 /* The back color slot is skipped when the front color is
1774 * also written to. In addition, some slots can be
1775 * written in the vertex shader and not read in the
1776 * fragment shader. So the register number must always be
1777 * incremented, mapped or not.
1779 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1780 prog_data
->urb_setup
[i
] = urb_next
;
1786 * It's a FS only attribute, and we did interpolation for this attribute
1787 * in SF thread. So, count it here, too.
1789 * See compile_sf_prog() for more info.
1791 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1792 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1795 prog_data
->num_varying_inputs
= urb_next
;
1796 prog_data
->inputs
= nir
->info
.inputs_read
;
1798 brw_compute_urb_setup_index(prog_data
);
1802 fs_visitor::assign_urb_setup()
1804 assert(stage
== MESA_SHADER_FRAGMENT
);
1805 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
1807 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1809 /* Offset all the urb_setup[] index by the actual position of the
1810 * setup regs, now that the location of the constants has been chosen.
1812 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1813 for (int i
= 0; i
< inst
->sources
; i
++) {
1814 if (inst
->src
[i
].file
== ATTR
) {
1815 /* ATTR regs in the FS are in units of logical scalar inputs each
1816 * of which consumes half of a GRF register.
1818 assert(inst
->src
[i
].offset
< REG_SIZE
/ 2);
1819 const unsigned grf
= urb_start
+ inst
->src
[i
].nr
/ 2;
1820 const unsigned offset
= (inst
->src
[i
].nr
% 2) * (REG_SIZE
/ 2) +
1821 inst
->src
[i
].offset
;
1822 const unsigned width
= inst
->src
[i
].stride
== 0 ?
1823 1 : MIN2(inst
->exec_size
, 8);
1824 struct brw_reg reg
= stride(
1825 byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1827 width
* inst
->src
[i
].stride
,
1828 width
, inst
->src
[i
].stride
);
1829 reg
.abs
= inst
->src
[i
].abs
;
1830 reg
.negate
= inst
->src
[i
].negate
;
1836 /* Each attribute is 4 setup channels, each of which is half a reg. */
1837 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1841 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1843 for (int i
= 0; i
< inst
->sources
; i
++) {
1844 if (inst
->src
[i
].file
== ATTR
) {
1845 int grf
= payload
.num_regs
+
1846 prog_data
->curb_read_length
+
1848 inst
->src
[i
].offset
/ REG_SIZE
;
1850 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1852 * VertStride must be used to cross GRF register boundaries. This
1853 * rule implies that elements within a 'Width' cannot cross GRF
1856 * So, for registers that are large enough, we have to split the exec
1857 * size in two and trust the compression state to sort it out.
1859 unsigned total_size
= inst
->exec_size
*
1860 inst
->src
[i
].stride
*
1861 type_sz(inst
->src
[i
].type
);
1863 assert(total_size
<= 2 * REG_SIZE
);
1864 const unsigned exec_size
=
1865 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1867 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1868 struct brw_reg reg
=
1869 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1870 inst
->src
[i
].offset
% REG_SIZE
),
1871 exec_size
* inst
->src
[i
].stride
,
1872 width
, inst
->src
[i
].stride
);
1873 reg
.abs
= inst
->src
[i
].abs
;
1874 reg
.negate
= inst
->src
[i
].negate
;
1882 fs_visitor::assign_vs_urb_setup()
1884 struct brw_vs_prog_data
*vs_prog_data
= brw_vs_prog_data(prog_data
);
1886 assert(stage
== MESA_SHADER_VERTEX
);
1888 /* Each attribute is 4 regs. */
1889 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1891 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1893 /* Rewrite all ATTR file references to the hw grf that they land in. */
1894 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1895 convert_attr_sources_to_hw_regs(inst
);
1900 fs_visitor::assign_tcs_urb_setup()
1902 assert(stage
== MESA_SHADER_TESS_CTRL
);
1904 /* Rewrite all ATTR file references to HW_REGs. */
1905 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1906 convert_attr_sources_to_hw_regs(inst
);
1911 fs_visitor::assign_tes_urb_setup()
1913 assert(stage
== MESA_SHADER_TESS_EVAL
);
1915 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1917 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1919 /* Rewrite all ATTR file references to HW_REGs. */
1920 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1921 convert_attr_sources_to_hw_regs(inst
);
1926 fs_visitor::assign_gs_urb_setup()
1928 assert(stage
== MESA_SHADER_GEOMETRY
);
1930 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
1932 first_non_payload_grf
+=
1933 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1935 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1936 /* Rewrite all ATTR file references to GRFs. */
1937 convert_attr_sources_to_hw_regs(inst
);
1943 * Split large virtual GRFs into separate components if we can.
1945 * This is mostly duplicated with what brw_fs_vector_splitting does,
1946 * but that's really conservative because it's afraid of doing
1947 * splitting that doesn't result in real progress after the rest of
1948 * the optimization phases, which would cause infinite looping in
1949 * optimization. We can do it once here, safely. This also has the
1950 * opportunity to split interpolated values, or maybe even uniforms,
1951 * which we don't have at the IR level.
1953 * We want to split, because virtual GRFs are what we register
1954 * allocate and spill (due to contiguousness requirements for some
1955 * instructions), and they're what we naturally generate in the
1956 * codegen process, but most virtual GRFs don't actually need to be
1957 * contiguous sets of GRFs. If we split, we'll end up with reduced
1958 * live intervals and better dead code elimination and coalescing.
1961 fs_visitor::split_virtual_grfs()
1963 /* Compact the register file so we eliminate dead vgrfs. This
1964 * only defines split points for live registers, so if we have
1965 * too large dead registers they will hit assertions later.
1967 compact_virtual_grfs();
1969 int num_vars
= this->alloc
.count
;
1971 /* Count the total number of registers */
1973 int vgrf_to_reg
[num_vars
];
1974 for (int i
= 0; i
< num_vars
; i
++) {
1975 vgrf_to_reg
[i
] = reg_count
;
1976 reg_count
+= alloc
.sizes
[i
];
1979 /* An array of "split points". For each register slot, this indicates
1980 * if this slot can be separated from the previous slot. Every time an
1981 * instruction uses multiple elements of a register (as a source or
1982 * destination), we mark the used slots as inseparable. Then we go
1983 * through and split the registers into the smallest pieces we can.
1985 bool *split_points
= new bool[reg_count
];
1986 memset(split_points
, 0, reg_count
* sizeof(*split_points
));
1988 /* Mark all used registers as fully splittable */
1989 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1990 if (inst
->dst
.file
== VGRF
) {
1991 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1992 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1993 split_points
[reg
+ j
] = true;
1996 for (int i
= 0; i
< inst
->sources
; i
++) {
1997 if (inst
->src
[i
].file
== VGRF
) {
1998 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1999 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
2000 split_points
[reg
+ j
] = true;
2005 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2006 /* We fix up undef instructions later */
2007 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2008 /* UNDEF instructions are currently only used to undef entire
2009 * registers. We need this invariant later when we split them.
2011 assert(inst
->dst
.file
== VGRF
);
2012 assert(inst
->dst
.offset
== 0);
2013 assert(inst
->size_written
== alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
);
2017 if (inst
->dst
.file
== VGRF
) {
2018 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2019 for (unsigned j
= 1; j
< regs_written(inst
); j
++)
2020 split_points
[reg
+ j
] = false;
2022 for (int i
= 0; i
< inst
->sources
; i
++) {
2023 if (inst
->src
[i
].file
== VGRF
) {
2024 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2025 for (unsigned j
= 1; j
< regs_read(inst
, i
); j
++)
2026 split_points
[reg
+ j
] = false;
2031 int *new_virtual_grf
= new int[reg_count
];
2032 int *new_reg_offset
= new int[reg_count
];
2035 for (int i
= 0; i
< num_vars
; i
++) {
2036 /* The first one should always be 0 as a quick sanity check. */
2037 assert(split_points
[reg
] == false);
2040 new_reg_offset
[reg
] = 0;
2045 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
2046 /* If this is a split point, reset the offset to 0 and allocate a
2047 * new virtual GRF for the previous offset many registers
2049 if (split_points
[reg
]) {
2050 assert(offset
<= MAX_VGRF_SIZE
);
2051 int grf
= alloc
.allocate(offset
);
2052 for (int k
= reg
- offset
; k
< reg
; k
++)
2053 new_virtual_grf
[k
] = grf
;
2056 new_reg_offset
[reg
] = offset
;
2061 /* The last one gets the original register number */
2062 assert(offset
<= MAX_VGRF_SIZE
);
2063 alloc
.sizes
[i
] = offset
;
2064 for (int k
= reg
- offset
; k
< reg
; k
++)
2065 new_virtual_grf
[k
] = i
;
2067 assert(reg
== reg_count
);
2069 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2070 if (inst
->opcode
== SHADER_OPCODE_UNDEF
) {
2071 const fs_builder
ibld(this, block
, inst
);
2072 assert(inst
->size_written
% REG_SIZE
== 0);
2073 unsigned reg_offset
= 0;
2074 while (reg_offset
< inst
->size_written
/ REG_SIZE
) {
2075 reg
= vgrf_to_reg
[inst
->dst
.nr
] + reg_offset
;
2076 ibld
.UNDEF(fs_reg(VGRF
, new_virtual_grf
[reg
], inst
->dst
.type
));
2077 reg_offset
+= alloc
.sizes
[new_virtual_grf
[reg
]];
2079 inst
->remove(block
);
2083 if (inst
->dst
.file
== VGRF
) {
2084 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.offset
/ REG_SIZE
;
2085 inst
->dst
.nr
= new_virtual_grf
[reg
];
2086 inst
->dst
.offset
= new_reg_offset
[reg
] * REG_SIZE
+
2087 inst
->dst
.offset
% REG_SIZE
;
2088 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2090 for (int i
= 0; i
< inst
->sources
; i
++) {
2091 if (inst
->src
[i
].file
== VGRF
) {
2092 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].offset
/ REG_SIZE
;
2093 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
2094 inst
->src
[i
].offset
= new_reg_offset
[reg
] * REG_SIZE
+
2095 inst
->src
[i
].offset
% REG_SIZE
;
2096 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2100 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
| DEPENDENCY_VARIABLES
);
2102 delete[] split_points
;
2103 delete[] new_virtual_grf
;
2104 delete[] new_reg_offset
;
2108 * Remove unused virtual GRFs and compact the vgrf_* arrays.
2110 * During code generation, we create tons of temporary variables, many of
2111 * which get immediately killed and are never used again. Yet, in later
2112 * optimization and analysis passes, such as compute_live_intervals, we need
2113 * to loop over all the virtual GRFs. Compacting them can save a lot of
2117 fs_visitor::compact_virtual_grfs()
2119 bool progress
= false;
2120 int *remap_table
= new int[this->alloc
.count
];
2121 memset(remap_table
, -1, this->alloc
.count
* sizeof(int));
2123 /* Mark which virtual GRFs are used. */
2124 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2125 if (inst
->dst
.file
== VGRF
)
2126 remap_table
[inst
->dst
.nr
] = 0;
2128 for (int i
= 0; i
< inst
->sources
; i
++) {
2129 if (inst
->src
[i
].file
== VGRF
)
2130 remap_table
[inst
->src
[i
].nr
] = 0;
2134 /* Compact the GRF arrays. */
2136 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2137 if (remap_table
[i
] == -1) {
2138 /* We just found an unused register. This means that we are
2139 * actually going to compact something.
2143 remap_table
[i
] = new_index
;
2144 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2145 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
| DEPENDENCY_VARIABLES
);
2150 this->alloc
.count
= new_index
;
2152 /* Patch all the instructions to use the newly renumbered registers */
2153 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2154 if (inst
->dst
.file
== VGRF
)
2155 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
2157 for (int i
= 0; i
< inst
->sources
; i
++) {
2158 if (inst
->src
[i
].file
== VGRF
)
2159 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
2163 /* Patch all the references to delta_xy, since they're used in register
2164 * allocation. If they're unused, switch them to BAD_FILE so we don't
2165 * think some random VGRF is delta_xy.
2167 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2168 if (delta_xy
[i
].file
== VGRF
) {
2169 if (remap_table
[delta_xy
[i
].nr
] != -1) {
2170 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
2172 delta_xy
[i
].file
= BAD_FILE
;
2177 delete[] remap_table
;
2183 get_subgroup_id_param_index(const brw_stage_prog_data
*prog_data
)
2185 if (prog_data
->nr_params
== 0)
2188 /* The local thread id is always the last parameter in the list */
2189 uint32_t last_param
= prog_data
->param
[prog_data
->nr_params
- 1];
2190 if (last_param
== BRW_PARAM_BUILTIN_SUBGROUP_ID
)
2191 return prog_data
->nr_params
- 1;
2197 * Struct for handling complex alignments.
2199 * A complex alignment is stored as multiplier and an offset. A value is
2200 * considered to be aligned if it is {offset} larger than a multiple of {mul}.
2201 * For instance, with an alignment of {8, 2}, cplx_align_apply would do the
2204 * N | cplx_align_apply({8, 2}, N)
2205 * ----+-----------------------------
2219 #define CPLX_ALIGN_MAX_MUL 8
2222 cplx_align_assert_sane(struct cplx_align a
)
2224 assert(a
.mul
> 0 && util_is_power_of_two_nonzero(a
.mul
));
2225 assert(a
.offset
< a
.mul
);
2229 * Combines two alignments to produce a least multiple of sorts.
2231 * The returned alignment is the smallest (in terms of multiplier) such that
2232 * anything aligned to both a and b will be aligned to the new alignment.
2233 * This function will assert-fail if a and b are not compatible, i.e. if the
2234 * offset parameters are such that no common alignment is possible.
2236 static struct cplx_align
2237 cplx_align_combine(struct cplx_align a
, struct cplx_align b
)
2239 cplx_align_assert_sane(a
);
2240 cplx_align_assert_sane(b
);
2242 /* Assert that the alignments agree. */
2243 assert((a
.offset
& (b
.mul
- 1)) == (b
.offset
& (a
.mul
- 1)));
2245 return a
.mul
> b
.mul
? a
: b
;
2249 * Apply a complex alignment
2251 * This function will return the smallest number greater than or equal to
2252 * offset that is aligned to align.
2255 cplx_align_apply(struct cplx_align align
, unsigned offset
)
2257 return ALIGN(offset
- align
.offset
, align
.mul
) + align
.offset
;
2260 #define UNIFORM_SLOT_SIZE 4
2262 struct uniform_slot_info
{
2263 /** True if the given uniform slot is live */
2266 /** True if this slot and the next slot must remain contiguous */
2267 unsigned contiguous
:1;
2269 struct cplx_align align
;
2273 mark_uniform_slots_read(struct uniform_slot_info
*slots
,
2274 unsigned num_slots
, unsigned alignment
)
2276 assert(alignment
> 0 && util_is_power_of_two_nonzero(alignment
));
2277 assert(alignment
<= CPLX_ALIGN_MAX_MUL
);
2279 /* We can't align a slot to anything less than the slot size */
2280 alignment
= MAX2(alignment
, UNIFORM_SLOT_SIZE
);
2282 struct cplx_align align
= {alignment
, 0};
2283 cplx_align_assert_sane(align
);
2285 for (unsigned i
= 0; i
< num_slots
; i
++) {
2286 slots
[i
].is_live
= true;
2287 if (i
< num_slots
- 1)
2288 slots
[i
].contiguous
= true;
2290 align
.offset
= (i
* UNIFORM_SLOT_SIZE
) & (align
.mul
- 1);
2291 if (slots
[i
].align
.mul
== 0) {
2292 slots
[i
].align
= align
;
2294 slots
[i
].align
= cplx_align_combine(slots
[i
].align
, align
);
2300 * Assign UNIFORM file registers to either push constants or pull constants.
2302 * We allow a fragment shader to have more than the specified minimum
2303 * maximum number of fragment shader uniform components (64). If
2304 * there are too many of these, they'd fill up all of register space.
2305 * So, this will push some of them out to the pull constant buffer and
2306 * update the program to load them.
2309 fs_visitor::assign_constant_locations()
2311 /* Only the first compile gets to decide on locations. */
2312 if (push_constant_loc
) {
2313 assert(pull_constant_loc
);
2317 if (compiler
->compact_params
) {
2318 struct uniform_slot_info slots
[uniforms
+ 1];
2319 memset(slots
, 0, sizeof(slots
));
2321 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2322 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2323 if (inst
->src
[i
].file
!= UNIFORM
)
2326 /* NIR tightly packs things so the uniform number might not be
2327 * aligned (if we have a double right after a float, for
2328 * instance). This is fine because the process of re-arranging
2329 * them will ensure that things are properly aligned. The offset
2330 * into that uniform, however, must be aligned.
2332 * In Vulkan, we have explicit offsets but everything is crammed
2333 * into a single "variable" so inst->src[i].nr will always be 0.
2334 * Everything will be properly aligned relative to that one base.
2336 assert(inst
->src
[i
].offset
% type_sz(inst
->src
[i
].type
) == 0);
2338 unsigned u
= inst
->src
[i
].nr
+
2339 inst
->src
[i
].offset
/ UNIFORM_SLOT_SIZE
;
2344 unsigned slots_read
;
2345 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2346 slots_read
= DIV_ROUND_UP(inst
->src
[2].ud
, UNIFORM_SLOT_SIZE
);
2348 unsigned bytes_read
= inst
->components_read(i
) *
2349 type_sz(inst
->src
[i
].type
);
2350 slots_read
= DIV_ROUND_UP(bytes_read
, UNIFORM_SLOT_SIZE
);
2353 assert(u
+ slots_read
<= uniforms
);
2354 mark_uniform_slots_read(&slots
[u
], slots_read
,
2355 type_sz(inst
->src
[i
].type
));
2359 int subgroup_id_index
= get_subgroup_id_param_index(stage_prog_data
);
2361 /* Only allow 16 registers (128 uniform components) as push constants.
2363 * Just demote the end of the list. We could probably do better
2364 * here, demoting things that are rarely used in the program first.
2366 * If changing this value, note the limitation about total_regs in
2369 unsigned int max_push_components
= 16 * 8;
2370 if (subgroup_id_index
>= 0)
2371 max_push_components
--; /* Save a slot for the thread ID */
2373 /* We push small arrays, but no bigger than 16 floats. This is big
2374 * enough for a vec4 but hopefully not large enough to push out other
2375 * stuff. We should probably use a better heuristic at some point.
2377 const unsigned int max_chunk_size
= 16;
2379 unsigned int num_push_constants
= 0;
2380 unsigned int num_pull_constants
= 0;
2382 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2383 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2385 /* Default to -1 meaning no location */
2386 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2387 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2389 int chunk_start
= -1;
2390 struct cplx_align align
;
2391 for (unsigned u
= 0; u
< uniforms
; u
++) {
2392 if (!slots
[u
].is_live
) {
2393 assert(chunk_start
== -1);
2397 /* Skip subgroup_id_index to put it in the last push register. */
2398 if (subgroup_id_index
== (int)u
)
2401 if (chunk_start
== -1) {
2403 align
= slots
[u
].align
;
2405 /* Offset into the chunk */
2406 unsigned chunk_offset
= (u
- chunk_start
) * UNIFORM_SLOT_SIZE
;
2408 /* Shift the slot alignment down by the chunk offset so it is
2409 * comparable with the base chunk alignment.
2411 struct cplx_align slot_align
= slots
[u
].align
;
2413 (slot_align
.offset
- chunk_offset
) & (align
.mul
- 1);
2415 align
= cplx_align_combine(align
, slot_align
);
2418 /* Sanity check the alignment */
2419 cplx_align_assert_sane(align
);
2421 if (slots
[u
].contiguous
)
2424 /* Adjust the alignment to be in terms of slots, not bytes */
2425 assert((align
.mul
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2426 assert((align
.offset
& (UNIFORM_SLOT_SIZE
- 1)) == 0);
2427 align
.mul
/= UNIFORM_SLOT_SIZE
;
2428 align
.offset
/= UNIFORM_SLOT_SIZE
;
2430 unsigned push_start_align
= cplx_align_apply(align
, num_push_constants
);
2431 unsigned chunk_size
= u
- chunk_start
+ 1;
2432 if ((!compiler
->supports_pull_constants
&& u
< UBO_START
) ||
2433 (chunk_size
< max_chunk_size
&&
2434 push_start_align
+ chunk_size
<= max_push_components
)) {
2435 /* Align up the number of push constants */
2436 num_push_constants
= push_start_align
;
2437 for (unsigned i
= 0; i
< chunk_size
; i
++)
2438 push_constant_loc
[chunk_start
+ i
] = num_push_constants
++;
2440 /* We need to pull this one */
2441 num_pull_constants
= cplx_align_apply(align
, num_pull_constants
);
2442 for (unsigned i
= 0; i
< chunk_size
; i
++)
2443 pull_constant_loc
[chunk_start
+ i
] = num_pull_constants
++;
2446 /* Reset the chunk and start again */
2450 /* Add the CS local thread ID uniform at the end of the push constants */
2451 if (subgroup_id_index
>= 0)
2452 push_constant_loc
[subgroup_id_index
] = num_push_constants
++;
2454 /* As the uniforms are going to be reordered, stash the old array and
2455 * create two new arrays for push/pull params.
2457 uint32_t *param
= stage_prog_data
->param
;
2458 stage_prog_data
->nr_params
= num_push_constants
;
2459 if (num_push_constants
) {
2460 stage_prog_data
->param
= rzalloc_array(mem_ctx
, uint32_t,
2461 num_push_constants
);
2463 stage_prog_data
->param
= NULL
;
2465 assert(stage_prog_data
->nr_pull_params
== 0);
2466 assert(stage_prog_data
->pull_param
== NULL
);
2467 if (num_pull_constants
> 0) {
2468 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2469 stage_prog_data
->pull_param
= rzalloc_array(mem_ctx
, uint32_t,
2470 num_pull_constants
);
2473 /* Up until now, the param[] array has been indexed by reg + offset
2474 * of UNIFORM registers. Move pull constants into pull_param[] and
2475 * condense param[] to only contain the uniforms we chose to push.
2477 * NOTE: Because we are condensing the params[] array, we know that
2478 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2479 * having to make a copy.
2481 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2482 uint32_t value
= param
[i
];
2483 if (pull_constant_loc
[i
] != -1) {
2484 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2485 } else if (push_constant_loc
[i
] != -1) {
2486 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2491 /* If we don't want to compact anything, just set up dummy push/pull
2492 * arrays. All the rest of the compiler cares about are these arrays.
2494 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2495 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2497 for (unsigned u
= 0; u
< uniforms
; u
++)
2498 push_constant_loc
[u
] = u
;
2500 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2503 /* Now that we know how many regular uniforms we'll push, reduce the
2504 * UBO push ranges so we don't exceed the 3DSTATE_CONSTANT limits.
2506 unsigned push_length
= DIV_ROUND_UP(stage_prog_data
->nr_params
, 8);
2507 for (int i
= 0; i
< 4; i
++) {
2508 struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2510 if (push_length
+ range
->length
> 64)
2511 range
->length
= 64 - push_length
;
2513 push_length
+= range
->length
;
2515 assert(push_length
<= 64);
2519 fs_visitor::get_pull_locs(const fs_reg
&src
,
2520 unsigned *out_surf_index
,
2521 unsigned *out_pull_index
)
2523 assert(src
.file
== UNIFORM
);
2525 if (src
.nr
>= UBO_START
) {
2526 const struct brw_ubo_range
*range
=
2527 &prog_data
->ubo_ranges
[src
.nr
- UBO_START
];
2529 /* If this access is in our (reduced) range, use the push data. */
2530 if (src
.offset
/ 32 < range
->length
)
2533 *out_surf_index
= prog_data
->binding_table
.ubo_start
+ range
->block
;
2534 *out_pull_index
= (32 * range
->start
+ src
.offset
) / 4;
2536 prog_data
->has_ubo_pull
= true;
2540 const unsigned location
= src
.nr
+ src
.offset
/ 4;
2542 if (location
< uniforms
&& pull_constant_loc
[location
] != -1) {
2543 /* A regular uniform push constant */
2544 *out_surf_index
= stage_prog_data
->binding_table
.pull_constants_start
;
2545 *out_pull_index
= pull_constant_loc
[location
];
2547 prog_data
->has_ubo_pull
= true;
2555 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2556 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2559 fs_visitor::lower_constant_loads()
2561 unsigned index
, pull_index
;
2563 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2564 /* Set up the annotation tracking for new generated instructions. */
2565 const fs_builder
ibld(this, block
, inst
);
2567 for (int i
= 0; i
< inst
->sources
; i
++) {
2568 if (inst
->src
[i
].file
!= UNIFORM
)
2571 /* We'll handle this case later */
2572 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2575 if (!get_pull_locs(inst
->src
[i
], &index
, &pull_index
))
2578 assert(inst
->src
[i
].stride
== 0);
2580 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
2581 const fs_builder ubld
= ibld
.exec_all().group(block_sz
/ 4, 0);
2582 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
2583 const unsigned base
= pull_index
* 4;
2585 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2586 dst
, brw_imm_ud(index
), brw_imm_ud(base
& ~(block_sz
- 1)));
2588 /* Rewrite the instruction to use the temporary VGRF. */
2589 inst
->src
[i
].file
= VGRF
;
2590 inst
->src
[i
].nr
= dst
.nr
;
2591 inst
->src
[i
].offset
= (base
& (block_sz
- 1)) +
2592 inst
->src
[i
].offset
% 4;
2595 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2596 inst
->src
[0].file
== UNIFORM
) {
2598 if (!get_pull_locs(inst
->src
[0], &index
, &pull_index
))
2601 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2605 inst
->remove(block
);
2608 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
2612 fs_visitor::opt_algebraic()
2614 bool progress
= false;
2616 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2617 switch (inst
->opcode
) {
2618 case BRW_OPCODE_MOV
:
2619 if (!devinfo
->has_64bit_float
&&
2620 !devinfo
->has_64bit_int
&&
2621 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2622 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2623 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2624 assert(inst
->dst
.type
== inst
->src
[0].type
);
2625 assert(!inst
->saturate
);
2626 assert(!inst
->src
[0].abs
);
2627 assert(!inst
->src
[0].negate
);
2628 const brw::fs_builder
ibld(this, block
, inst
);
2630 if (inst
->src
[0].file
== IMM
) {
2631 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2632 brw_imm_ud(inst
->src
[0].u64
>> 32));
2633 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2634 brw_imm_ud(inst
->src
[0].u64
));
2636 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2637 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1));
2638 ibld
.MOV(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2639 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0));
2642 inst
->remove(block
);
2646 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2647 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2648 inst
->dst
.is_null() &&
2649 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2650 inst
->src
[0].abs
= false;
2651 inst
->src
[0].negate
= false;
2656 if (inst
->src
[0].file
!= IMM
)
2659 if (inst
->saturate
) {
2660 /* Full mixed-type saturates don't happen. However, we can end up
2663 * mov.sat(8) g21<1>DF -1F
2665 * Other mixed-size-but-same-base-type cases may also be possible.
2667 if (inst
->dst
.type
!= inst
->src
[0].type
&&
2668 inst
->dst
.type
!= BRW_REGISTER_TYPE_DF
&&
2669 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
)
2670 assert(!"unimplemented: saturate mixed types");
2672 if (brw_saturate_immediate(inst
->src
[0].type
,
2673 &inst
->src
[0].as_brw_reg())) {
2674 inst
->saturate
= false;
2680 case BRW_OPCODE_MUL
:
2681 if (inst
->src
[1].file
!= IMM
)
2685 if (inst
->src
[1].is_one()) {
2686 inst
->opcode
= BRW_OPCODE_MOV
;
2687 inst
->src
[1] = reg_undef
;
2693 if (inst
->src
[1].is_negative_one()) {
2694 inst
->opcode
= BRW_OPCODE_MOV
;
2695 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2696 inst
->src
[1] = reg_undef
;
2701 if (inst
->src
[0].file
== IMM
) {
2702 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2703 inst
->opcode
= BRW_OPCODE_MOV
;
2704 inst
->src
[0].f
*= inst
->src
[1].f
;
2705 inst
->src
[1] = reg_undef
;
2710 case BRW_OPCODE_ADD
:
2711 if (inst
->src
[1].file
!= IMM
)
2714 if (brw_reg_type_is_integer(inst
->src
[1].type
) &&
2715 inst
->src
[1].is_zero()) {
2716 inst
->opcode
= BRW_OPCODE_MOV
;
2717 inst
->src
[1] = reg_undef
;
2722 if (inst
->src
[0].file
== IMM
) {
2723 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2724 inst
->opcode
= BRW_OPCODE_MOV
;
2725 inst
->src
[0].f
+= inst
->src
[1].f
;
2726 inst
->src
[1] = reg_undef
;
2732 if (inst
->src
[0].equals(inst
->src
[1]) ||
2733 inst
->src
[1].is_zero()) {
2734 /* On Gen8+, the OR instruction can have a source modifier that
2735 * performs logical not on the operand. Cases of 'OR r0, ~r1, 0'
2736 * or 'OR r0, ~r1, ~r1' should become a NOT instead of a MOV.
2738 if (inst
->src
[0].negate
) {
2739 inst
->opcode
= BRW_OPCODE_NOT
;
2740 inst
->src
[0].negate
= false;
2742 inst
->opcode
= BRW_OPCODE_MOV
;
2744 inst
->src
[1] = reg_undef
;
2749 case BRW_OPCODE_CMP
:
2750 if ((inst
->conditional_mod
== BRW_CONDITIONAL_Z
||
2751 inst
->conditional_mod
== BRW_CONDITIONAL_NZ
) &&
2752 inst
->src
[1].is_zero() &&
2753 (inst
->src
[0].abs
|| inst
->src
[0].negate
)) {
2754 inst
->src
[0].abs
= false;
2755 inst
->src
[0].negate
= false;
2760 case BRW_OPCODE_SEL
:
2761 if (!devinfo
->has_64bit_float
&&
2762 !devinfo
->has_64bit_int
&&
2763 (inst
->dst
.type
== BRW_REGISTER_TYPE_DF
||
2764 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
||
2765 inst
->dst
.type
== BRW_REGISTER_TYPE_Q
)) {
2766 assert(inst
->dst
.type
== inst
->src
[0].type
);
2767 assert(!inst
->saturate
);
2768 assert(!inst
->src
[0].abs
&& !inst
->src
[0].negate
);
2769 assert(!inst
->src
[1].abs
&& !inst
->src
[1].negate
);
2770 const brw::fs_builder
ibld(this, block
, inst
);
2772 set_predicate(inst
->predicate
,
2773 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 0),
2774 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
2775 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0)));
2776 set_predicate(inst
->predicate
,
2777 ibld
.SEL(subscript(inst
->dst
, BRW_REGISTER_TYPE_UD
, 1),
2778 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
2779 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1)));
2781 inst
->remove(block
);
2784 if (inst
->src
[0].equals(inst
->src
[1])) {
2785 inst
->opcode
= BRW_OPCODE_MOV
;
2786 inst
->src
[1] = reg_undef
;
2787 inst
->predicate
= BRW_PREDICATE_NONE
;
2788 inst
->predicate_inverse
= false;
2790 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2791 switch (inst
->conditional_mod
) {
2792 case BRW_CONDITIONAL_LE
:
2793 case BRW_CONDITIONAL_L
:
2794 switch (inst
->src
[1].type
) {
2795 case BRW_REGISTER_TYPE_F
:
2796 if (inst
->src
[1].f
>= 1.0f
) {
2797 inst
->opcode
= BRW_OPCODE_MOV
;
2798 inst
->src
[1] = reg_undef
;
2799 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2807 case BRW_CONDITIONAL_GE
:
2808 case BRW_CONDITIONAL_G
:
2809 switch (inst
->src
[1].type
) {
2810 case BRW_REGISTER_TYPE_F
:
2811 if (inst
->src
[1].f
<= 0.0f
) {
2812 inst
->opcode
= BRW_OPCODE_MOV
;
2813 inst
->src
[1] = reg_undef
;
2814 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2826 case BRW_OPCODE_MAD
:
2827 if (inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
2828 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
2829 inst
->src
[2].type
!= BRW_REGISTER_TYPE_F
)
2831 if (inst
->src
[1].is_one()) {
2832 inst
->opcode
= BRW_OPCODE_ADD
;
2833 inst
->src
[1] = inst
->src
[2];
2834 inst
->src
[2] = reg_undef
;
2836 } else if (inst
->src
[2].is_one()) {
2837 inst
->opcode
= BRW_OPCODE_ADD
;
2838 inst
->src
[2] = reg_undef
;
2842 case SHADER_OPCODE_BROADCAST
:
2843 if (is_uniform(inst
->src
[0])) {
2844 inst
->opcode
= BRW_OPCODE_MOV
;
2846 inst
->force_writemask_all
= true;
2848 } else if (inst
->src
[1].file
== IMM
) {
2849 inst
->opcode
= BRW_OPCODE_MOV
;
2850 /* It's possible that the selected component will be too large and
2851 * overflow the register. This can happen if someone does a
2852 * readInvocation() from GLSL or SPIR-V and provides an OOB
2853 * invocationIndex. If this happens and we some how manage
2854 * to constant fold it in and get here, then component() may cause
2855 * us to start reading outside of the VGRF which will lead to an
2856 * assert later. Instead, just let it wrap around if it goes over
2859 const unsigned comp
= inst
->src
[1].ud
& (inst
->exec_size
- 1);
2860 inst
->src
[0] = component(inst
->src
[0], comp
);
2862 inst
->force_writemask_all
= true;
2867 case SHADER_OPCODE_SHUFFLE
:
2868 if (is_uniform(inst
->src
[0])) {
2869 inst
->opcode
= BRW_OPCODE_MOV
;
2872 } else if (inst
->src
[1].file
== IMM
) {
2873 inst
->opcode
= BRW_OPCODE_MOV
;
2874 inst
->src
[0] = component(inst
->src
[0],
2885 /* Swap if src[0] is immediate. */
2886 if (progress
&& inst
->is_commutative()) {
2887 if (inst
->src
[0].file
== IMM
) {
2888 fs_reg tmp
= inst
->src
[1];
2889 inst
->src
[1] = inst
->src
[0];
2896 invalidate_analysis(DEPENDENCY_INSTRUCTION_DATA_FLOW
|
2897 DEPENDENCY_INSTRUCTION_DETAIL
);
2903 * Optimize sample messages that have constant zero values for the trailing
2904 * texture coordinates. We can just reduce the message length for these
2905 * instructions instead of reserving a register for it. Trailing parameters
2906 * that aren't sent default to zero anyway. This will cause the dead code
2907 * eliminator to remove the MOV instruction that would otherwise be emitted to
2908 * set up the zero value.
2911 fs_visitor::opt_zero_samples()
2913 /* Gen4 infers the texturing opcode based on the message length so we can't
2916 if (devinfo
->gen
< 5)
2919 bool progress
= false;
2921 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2922 if (!inst
->is_tex())
2925 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2927 if (load_payload
->is_head_sentinel() ||
2928 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2931 /* We don't want to remove the message header or the first parameter.
2932 * Removing the first parameter is not allowed, see the Haswell PRM
2933 * volume 7, page 149:
2935 * "Parameter 0 is required except for the sampleinfo message, which
2936 * has no parameter 0"
2938 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2939 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2940 (inst
->exec_size
/ 8) +
2941 inst
->header_size
- 1].is_zero()) {
2942 inst
->mlen
-= inst
->exec_size
/ 8;
2948 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
);
2954 fs_visitor::opt_register_renaming()
2956 bool progress
= false;
2959 unsigned remap
[alloc
.count
];
2960 memset(remap
, ~0u, sizeof(unsigned) * alloc
.count
);
2962 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2963 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2965 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2966 inst
->opcode
== BRW_OPCODE_WHILE
) {
2970 /* Rewrite instruction sources. */
2971 for (int i
= 0; i
< inst
->sources
; i
++) {
2972 if (inst
->src
[i
].file
== VGRF
&&
2973 remap
[inst
->src
[i
].nr
] != ~0u &&
2974 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2975 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2980 const unsigned dst
= inst
->dst
.nr
;
2983 inst
->dst
.file
== VGRF
&&
2984 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
== inst
->size_written
&&
2985 !inst
->is_partial_write()) {
2986 if (remap
[dst
] == ~0u) {
2989 remap
[dst
] = alloc
.allocate(regs_written(inst
));
2990 inst
->dst
.nr
= remap
[dst
];
2993 } else if (inst
->dst
.file
== VGRF
&&
2994 remap
[dst
] != ~0u &&
2995 remap
[dst
] != dst
) {
2996 inst
->dst
.nr
= remap
[dst
];
3002 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
|
3003 DEPENDENCY_VARIABLES
);
3005 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
3006 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != ~0u) {
3007 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
3016 * Remove redundant or useless discard jumps.
3018 * For example, we can eliminate jumps in the following sequence:
3020 * discard-jump (redundant with the next jump)
3021 * discard-jump (useless; jumps to the next instruction)
3025 fs_visitor::opt_redundant_discard_jumps()
3027 bool progress
= false;
3029 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
3031 fs_inst
*placeholder_halt
= NULL
;
3032 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
3033 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
3034 placeholder_halt
= inst
;
3039 if (!placeholder_halt
)
3042 /* Delete any HALTs immediately before the placeholder halt. */
3043 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
3044 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
3045 prev
= (fs_inst
*) placeholder_halt
->prev
) {
3046 prev
->remove(last_bblock
);
3051 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3057 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
3058 * from \p r.offset which overlaps the region starting at \p s.offset and
3059 * spanning \p ds bytes.
3061 static inline unsigned
3062 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned ds
)
3064 const int rel_offset
= reg_offset(s
) - reg_offset(r
);
3065 const int shift
= rel_offset
/ REG_SIZE
;
3066 const unsigned n
= DIV_ROUND_UP(rel_offset
% REG_SIZE
+ ds
, REG_SIZE
);
3067 assert(reg_space(r
) == reg_space(s
) &&
3068 shift
>= 0 && shift
< int(8 * sizeof(unsigned)));
3069 return ((1 << n
) - 1) << shift
;
3073 fs_visitor::compute_to_mrf()
3075 bool progress
= false;
3078 /* No MRFs on Gen >= 7. */
3079 if (devinfo
->gen
>= 7)
3082 const fs_live_variables
&live
= live_analysis
.require();
3084 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3088 if (inst
->opcode
!= BRW_OPCODE_MOV
||
3089 inst
->is_partial_write() ||
3090 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
3091 inst
->dst
.type
!= inst
->src
[0].type
||
3092 inst
->src
[0].abs
|| inst
->src
[0].negate
||
3093 !inst
->src
[0].is_contiguous() ||
3094 inst
->src
[0].offset
% REG_SIZE
!= 0)
3097 /* Can't compute-to-MRF this GRF if someone else was going to
3100 if (live
.vgrf_end
[inst
->src
[0].nr
] > ip
)
3103 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
3104 * things that computed the value of all GRFs of the source region. The
3105 * regs_left bitset keeps track of the registers we haven't yet found a
3106 * generating instruction for.
3108 unsigned regs_left
= (1 << regs_read(inst
, 0)) - 1;
3110 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3111 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3112 inst
->src
[0], inst
->size_read(0))) {
3113 /* Found the last thing to write our reg we want to turn
3114 * into a compute-to-MRF.
3117 /* If this one instruction didn't populate all the
3118 * channels, bail. We might be able to rewrite everything
3119 * that writes that reg, but it would require smarter
3122 if (scan_inst
->is_partial_write())
3125 /* Handling things not fully contained in the source of the copy
3126 * would need us to understand coalescing out more than one MOV at
3129 if (!region_contained_in(scan_inst
->dst
, scan_inst
->size_written
,
3130 inst
->src
[0], inst
->size_read(0)))
3133 /* SEND instructions can't have MRF as a destination. */
3134 if (scan_inst
->mlen
)
3137 if (devinfo
->gen
== 6) {
3138 /* gen6 math instructions must have the destination be
3139 * GRF, so no compute-to-MRF for them.
3141 if (scan_inst
->is_math()) {
3146 /* Clear the bits for any registers this instruction overwrites. */
3147 regs_left
&= ~mask_relative_to(
3148 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3153 /* We don't handle control flow here. Most computation of
3154 * values that end up in MRFs are shortly before the MRF
3157 if (block
->start() == scan_inst
)
3160 /* You can't read from an MRF, so if someone else reads our
3161 * MRF's source GRF that we wanted to rewrite, that stops us.
3163 bool interfered
= false;
3164 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
3165 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->size_read(i
),
3166 inst
->src
[0], inst
->size_read(0))) {
3173 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3174 inst
->dst
, inst
->size_written
)) {
3175 /* If somebody else writes our MRF here, we can't
3176 * compute-to-MRF before that.
3181 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
3182 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
3183 inst
->dst
, inst
->size_written
)) {
3184 /* Found a SEND instruction, which means that there are
3185 * live values in MRFs from base_mrf to base_mrf +
3186 * scan_inst->mlen - 1. Don't go pushing our MRF write up
3196 /* Found all generating instructions of our MRF's source value, so it
3197 * should be safe to rewrite them to point to the MRF directly.
3199 regs_left
= (1 << regs_read(inst
, 0)) - 1;
3201 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3202 if (regions_overlap(scan_inst
->dst
, scan_inst
->size_written
,
3203 inst
->src
[0], inst
->size_read(0))) {
3204 /* Clear the bits for any registers this instruction overwrites. */
3205 regs_left
&= ~mask_relative_to(
3206 inst
->src
[0], scan_inst
->dst
, scan_inst
->size_written
);
3208 const unsigned rel_offset
= reg_offset(scan_inst
->dst
) -
3209 reg_offset(inst
->src
[0]);
3211 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
3212 /* Apply the same address transformation done by the hardware
3213 * for COMPR4 MRF writes.
3215 assert(rel_offset
< 2 * REG_SIZE
);
3216 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
* 4;
3218 /* Clear the COMPR4 bit if the generating instruction is not
3221 if (scan_inst
->size_written
< 2 * REG_SIZE
)
3222 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
3225 /* Calculate the MRF number the result of this instruction is
3226 * ultimately written to.
3228 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
/ REG_SIZE
;
3231 scan_inst
->dst
.file
= MRF
;
3232 scan_inst
->dst
.offset
= inst
->dst
.offset
+ rel_offset
% REG_SIZE
;
3233 scan_inst
->saturate
|= inst
->saturate
;
3240 inst
->remove(block
);
3245 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3251 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
3252 * flow. We could probably do better here with some form of divergence
3256 fs_visitor::eliminate_find_live_channel()
3258 bool progress
= false;
3261 if (!brw_stage_has_packed_dispatch(devinfo
, stage
, stage_prog_data
)) {
3262 /* The optimization below assumes that channel zero is live on thread
3263 * dispatch, which may not be the case if the fixed function dispatches
3269 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3270 switch (inst
->opcode
) {
3276 case BRW_OPCODE_ENDIF
:
3277 case BRW_OPCODE_WHILE
:
3281 case FS_OPCODE_DISCARD_JUMP
:
3282 /* This can potentially make control flow non-uniform until the end
3287 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3289 inst
->opcode
= BRW_OPCODE_MOV
;
3290 inst
->src
[0] = brw_imm_ud(0u);
3292 inst
->force_writemask_all
= true;
3303 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
);
3309 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3310 * instructions to FS_OPCODE_REP_FB_WRITE.
3313 fs_visitor::emit_repclear_shader()
3315 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3317 int color_mrf
= base_mrf
+ 2;
3321 mov
= bld
.exec_all().group(4, 0)
3322 .MOV(brw_message_reg(color_mrf
),
3323 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3325 struct brw_reg reg
=
3326 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3327 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3328 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3330 mov
= bld
.exec_all().group(4, 0)
3331 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3334 fs_inst
*write
= NULL
;
3335 if (key
->nr_color_regions
== 1) {
3336 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3337 write
->saturate
= key
->clamp_fragment_color
;
3338 write
->base_mrf
= color_mrf
;
3340 write
->header_size
= 0;
3343 assume(key
->nr_color_regions
> 0);
3345 struct brw_reg header
=
3346 retype(brw_message_reg(base_mrf
), BRW_REGISTER_TYPE_UD
);
3347 bld
.exec_all().group(16, 0)
3348 .MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3350 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3352 bld
.exec_all().group(1, 0)
3353 .MOV(component(header
, 2), brw_imm_ud(i
));
3356 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3357 write
->saturate
= key
->clamp_fragment_color
;
3358 write
->base_mrf
= base_mrf
;
3360 write
->header_size
= 2;
3365 write
->last_rt
= true;
3369 assign_constant_locations();
3370 assign_curb_setup();
3372 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3374 assert(mov
->src
[0].file
== FIXED_GRF
);
3375 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3382 * Walks through basic blocks, looking for repeated MRF writes and
3383 * removing the later ones.
3386 fs_visitor::remove_duplicate_mrf_writes()
3388 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3389 bool progress
= false;
3391 /* Need to update the MRF tracking for compressed instructions. */
3392 if (dispatch_width
>= 16)
3395 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3397 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3398 if (inst
->is_control_flow()) {
3399 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3402 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3403 inst
->dst
.file
== MRF
) {
3404 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3405 if (prev_inst
&& prev_inst
->opcode
== BRW_OPCODE_MOV
&&
3406 inst
->dst
.equals(prev_inst
->dst
) &&
3407 inst
->src
[0].equals(prev_inst
->src
[0]) &&
3408 inst
->saturate
== prev_inst
->saturate
&&
3409 inst
->predicate
== prev_inst
->predicate
&&
3410 inst
->conditional_mod
== prev_inst
->conditional_mod
&&
3411 inst
->exec_size
== prev_inst
->exec_size
) {
3412 inst
->remove(block
);
3418 /* Clear out the last-write records for MRFs that were overwritten. */
3419 if (inst
->dst
.file
== MRF
) {
3420 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3423 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3424 /* Found a SEND instruction, which will include two or fewer
3425 * implied MRF writes. We could do better here.
3427 for (unsigned i
= 0; i
< inst
->implied_mrf_writes(); i
++) {
3428 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3432 /* Clear out any MRF move records whose sources got overwritten. */
3433 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3434 if (last_mrf_move
[i
] &&
3435 regions_overlap(inst
->dst
, inst
->size_written
,
3436 last_mrf_move
[i
]->src
[0],
3437 last_mrf_move
[i
]->size_read(0))) {
3438 last_mrf_move
[i
] = NULL
;
3442 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3443 inst
->dst
.file
== MRF
&&
3444 inst
->src
[0].file
!= ARF
&&
3445 !inst
->is_partial_write()) {
3446 last_mrf_move
[inst
->dst
.nr
] = inst
;
3451 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3457 * Rounding modes for conversion instructions are included for each
3458 * conversion, but right now it is a state. So once it is set,
3459 * we don't need to call it again for subsequent calls.
3461 * This is useful for vector/matrices conversions, as setting the
3462 * mode once is enough for the full vector/matrix
3465 fs_visitor::remove_extra_rounding_modes()
3467 bool progress
= false;
3468 unsigned execution_mode
= this->nir
->info
.float_controls_execution_mode
;
3470 brw_rnd_mode base_mode
= BRW_RND_MODE_UNSPECIFIED
;
3471 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
|
3472 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
|
3473 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
) &
3475 base_mode
= BRW_RND_MODE_RTNE
;
3476 if ((FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
|
3477 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
|
3478 FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
) &
3480 base_mode
= BRW_RND_MODE_RTZ
;
3482 foreach_block (block
, cfg
) {
3483 brw_rnd_mode prev_mode
= base_mode
;
3485 foreach_inst_in_block_safe (fs_inst
, inst
, block
) {
3486 if (inst
->opcode
== SHADER_OPCODE_RND_MODE
) {
3487 assert(inst
->src
[0].file
== BRW_IMMEDIATE_VALUE
);
3488 const brw_rnd_mode mode
= (brw_rnd_mode
) inst
->src
[0].d
;
3489 if (mode
== prev_mode
) {
3490 inst
->remove(block
);
3500 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3506 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3508 /* Clear the flag for registers that actually got read (as expected). */
3509 for (int i
= 0; i
< inst
->sources
; i
++) {
3511 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3512 grf
= inst
->src
[i
].nr
;
3517 if (grf
>= first_grf
&&
3518 grf
< first_grf
+ grf_len
) {
3519 deps
[grf
- first_grf
] = false;
3520 if (inst
->exec_size
== 16)
3521 deps
[grf
- first_grf
+ 1] = false;
3527 * Implements this workaround for the original 965:
3529 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3530 * check for post destination dependencies on this instruction, software
3531 * must ensure that there is no destination hazard for the case of ‘write
3532 * followed by a posted write’ shown in the following example.
3535 * 2. send r3.xy <rest of send instruction>
3538 * Due to no post-destination dependency check on the ‘send’, the above
3539 * code sequence could have two instructions (1 and 2) in flight at the
3540 * same time that both consider ‘r3’ as the target of their final writes.
3543 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3546 int write_len
= regs_written(inst
);
3547 int first_write_grf
= inst
->dst
.nr
;
3548 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3549 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3551 memset(needs_dep
, false, sizeof(needs_dep
));
3552 memset(needs_dep
, true, write_len
);
3554 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3556 /* Walk backwards looking for writes to registers we're writing which
3557 * aren't read since being written. If we hit the start of the program,
3558 * we assume that there are no outstanding dependencies on entry to the
3561 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3562 /* If we hit control flow, assume that there *are* outstanding
3563 * dependencies, and force their cleanup before our instruction.
3565 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3566 for (int i
= 0; i
< write_len
; i
++) {
3568 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3569 first_write_grf
+ i
);
3574 /* We insert our reads as late as possible on the assumption that any
3575 * instruction but a MOV that might have left us an outstanding
3576 * dependency has more latency than a MOV.
3578 if (scan_inst
->dst
.file
== VGRF
) {
3579 for (unsigned i
= 0; i
< regs_written(scan_inst
); i
++) {
3580 int reg
= scan_inst
->dst
.nr
+ i
;
3582 if (reg
>= first_write_grf
&&
3583 reg
< first_write_grf
+ write_len
&&
3584 needs_dep
[reg
- first_write_grf
]) {
3585 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3586 needs_dep
[reg
- first_write_grf
] = false;
3587 if (scan_inst
->exec_size
== 16)
3588 needs_dep
[reg
- first_write_grf
+ 1] = false;
3593 /* Clear the flag for registers that actually got read (as expected). */
3594 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3596 /* Continue the loop only if we haven't resolved all the dependencies */
3598 for (i
= 0; i
< write_len
; i
++) {
3608 * Implements this workaround for the original 965:
3610 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3611 * used as a destination register until after it has been sourced by an
3612 * instruction with a different destination register.
3615 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3617 int write_len
= regs_written(inst
);
3618 unsigned first_write_grf
= inst
->dst
.nr
;
3619 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3620 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3622 memset(needs_dep
, false, sizeof(needs_dep
));
3623 memset(needs_dep
, true, write_len
);
3624 /* Walk forwards looking for writes to registers we're writing which aren't
3625 * read before being written.
3627 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3628 /* If we hit control flow, force resolve all remaining dependencies. */
3629 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3630 for (int i
= 0; i
< write_len
; i
++) {
3632 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3633 first_write_grf
+ i
);
3638 /* Clear the flag for registers that actually got read (as expected). */
3639 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3641 /* We insert our reads as late as possible since they're reading the
3642 * result of a SEND, which has massive latency.
3644 if (scan_inst
->dst
.file
== VGRF
&&
3645 scan_inst
->dst
.nr
>= first_write_grf
&&
3646 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3647 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3648 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3650 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3653 /* Continue the loop only if we haven't resolved all the dependencies */
3655 for (i
= 0; i
< write_len
; i
++) {
3665 fs_visitor::insert_gen4_send_dependency_workarounds()
3667 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3670 bool progress
= false;
3672 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3673 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3674 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3675 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3681 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3685 * Turns the generic expression-style uniform pull constant load instruction
3686 * into a hardware-specific series of instructions for loading a pull
3689 * The expression style allows the CSE pass before this to optimize out
3690 * repeated loads from the same offset, and gives the pre-register-allocation
3691 * scheduling full flexibility, while the conversion to native instructions
3692 * allows the post-register-allocation scheduler the best information
3695 * Note that execution masking for setting up pull constant loads is special:
3696 * the channels that need to be written are unrelated to the current execution
3697 * mask, since a later instruction will use one of the result channels as a
3698 * source operand for all 8 or 16 of its channels.
3701 fs_visitor::lower_uniform_pull_constant_loads()
3703 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3704 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3707 if (devinfo
->gen
>= 7) {
3708 const fs_builder ubld
= fs_builder(this, block
, inst
).exec_all();
3709 const fs_reg payload
= ubld
.group(8, 0).vgrf(BRW_REGISTER_TYPE_UD
);
3711 ubld
.group(8, 0).MOV(payload
,
3712 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
3713 ubld
.group(1, 0).MOV(component(payload
, 2),
3714 brw_imm_ud(inst
->src
[1].ud
/ 16));
3716 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3717 inst
->src
[1] = payload
;
3718 inst
->header_size
= 1;
3721 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
3723 /* Before register allocation, we didn't tell the scheduler about the
3724 * MRF we use. We know it's safe to use this MRF because nothing
3725 * else does except for register spill/unspill, which generates and
3726 * uses its MRF within a single IR instruction.
3728 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3735 fs_visitor::lower_load_payload()
3737 bool progress
= false;
3739 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3740 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3743 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3744 assert(inst
->saturate
== false);
3745 fs_reg dst
= inst
->dst
;
3747 /* Get rid of COMPR4. We'll add it back in if we need it */
3748 if (dst
.file
== MRF
)
3749 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3751 const fs_builder
ibld(this, block
, inst
);
3752 const fs_builder ubld
= ibld
.exec_all();
3754 for (uint8_t i
= 0; i
< inst
->header_size
;) {
3755 /* Number of header GRFs to initialize at once with a single MOV
3759 (i
+ 1 < inst
->header_size
&& inst
->src
[i
].stride
== 1 &&
3760 inst
->src
[i
+ 1].equals(byte_offset(inst
->src
[i
], REG_SIZE
))) ?
3763 if (inst
->src
[i
].file
!= BAD_FILE
)
3764 ubld
.group(8 * n
, 0).MOV(retype(dst
, BRW_REGISTER_TYPE_UD
),
3765 retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
));
3767 dst
= byte_offset(dst
, n
* REG_SIZE
);
3771 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3772 inst
->exec_size
> 8) {
3773 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3774 * a straightforward copy. Instead, the result of the
3775 * LOAD_PAYLOAD is treated as interleaved and the first four
3776 * non-header sources are unpacked as:
3787 * This is used for gen <= 5 fb writes.
3789 assert(inst
->exec_size
== 16);
3790 assert(inst
->header_size
+ 4 <= inst
->sources
);
3791 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3792 if (inst
->src
[i
].file
!= BAD_FILE
) {
3793 if (devinfo
->has_compr4
) {
3794 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3795 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3796 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3798 /* Platform doesn't have COMPR4. We have to fake it */
3799 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3800 ibld
.quarter(0).MOV(mov_dst
, quarter(inst
->src
[i
], 0));
3802 ibld
.quarter(1).MOV(mov_dst
, quarter(inst
->src
[i
], 1));
3809 /* The loop above only ever incremented us through the first set
3810 * of 4 registers. However, thanks to the magic of COMPR4, we
3811 * actually wrote to the first 8 registers, so we need to take
3812 * that into account now.
3816 /* The COMPR4 code took care of the first 4 sources. We'll let
3817 * the regular path handle any remaining sources. Yes, we are
3818 * modifying the instruction but we're about to delete it so
3819 * this really doesn't hurt anything.
3821 inst
->header_size
+= 4;
3824 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3825 if (inst
->src
[i
].file
!= BAD_FILE
) {
3826 dst
.type
= inst
->src
[i
].type
;
3827 ibld
.MOV(dst
, inst
->src
[i
]);
3829 dst
.type
= BRW_REGISTER_TYPE_UD
;
3831 dst
= offset(dst
, ibld
, 1);
3834 inst
->remove(block
);
3839 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
3845 fs_visitor::lower_mul_dword_inst(fs_inst
*inst
, bblock_t
*block
)
3847 const fs_builder
ibld(this, block
, inst
);
3849 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3850 if (inst
->src
[1].file
== IMM
&&
3851 (( ud
&& inst
->src
[1].ud
<= UINT16_MAX
) ||
3852 (!ud
&& inst
->src
[1].d
<= INT16_MAX
&& inst
->src
[1].d
>= INT16_MIN
))) {
3853 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3854 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3857 * If multiplying by an immediate value that fits in 16-bits, do a
3858 * single MUL instruction with that value in the proper location.
3860 if (devinfo
->gen
< 7) {
3861 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8), inst
->dst
.type
);
3862 ibld
.MOV(imm
, inst
->src
[1]);
3863 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3865 ibld
.MUL(inst
->dst
, inst
->src
[0],
3866 ud
? brw_imm_uw(inst
->src
[1].ud
)
3867 : brw_imm_w(inst
->src
[1].d
));
3870 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3871 * do 32-bit integer multiplication in one instruction, but instead
3872 * must do a sequence (which actually calculates a 64-bit result):
3874 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3875 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3876 * mov(8) g2<1>D acc0<8,8,1>D
3878 * But on Gen > 6, the ability to use second accumulator register
3879 * (acc1) for non-float data types was removed, preventing a simple
3880 * implementation in SIMD16. A 16-channel result can be calculated by
3881 * executing the three instructions twice in SIMD8, once with quarter
3882 * control of 1Q for the first eight channels and again with 2Q for
3883 * the second eight channels.
3885 * Which accumulator register is implicitly accessed (by AccWrEnable
3886 * for instance) is determined by the quarter control. Unfortunately
3887 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3888 * implicit accumulator access by an instruction with 2Q will access
3889 * acc1 regardless of whether the data type is usable in acc1.
3891 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3892 * integer data types.
3894 * Since we only want the low 32-bits of the result, we can do two
3895 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3896 * adjust the high result and add them (like the mach is doing):
3898 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3899 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3900 * shl(8) g9<1>D g8<8,8,1>D 16D
3901 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3903 * We avoid the shl instruction by realizing that we only want to add
3904 * the low 16-bits of the "high" result to the high 16-bits of the
3905 * "low" result and using proper regioning on the add:
3907 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3908 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3909 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3911 * Since it does not use the (single) accumulator register, we can
3912 * schedule multi-component multiplications much better.
3915 bool needs_mov
= false;
3916 fs_reg orig_dst
= inst
->dst
;
3918 /* Get a new VGRF for the "low" 32x16-bit multiplication result if
3919 * reusing the original destination is impossible due to hardware
3920 * restrictions, source/destination overlap, or it being the null
3923 fs_reg low
= inst
->dst
;
3924 if (orig_dst
.is_null() || orig_dst
.file
== MRF
||
3925 regions_overlap(inst
->dst
, inst
->size_written
,
3926 inst
->src
[0], inst
->size_read(0)) ||
3927 regions_overlap(inst
->dst
, inst
->size_written
,
3928 inst
->src
[1], inst
->size_read(1)) ||
3929 inst
->dst
.stride
>= 4) {
3931 low
= fs_reg(VGRF
, alloc
.allocate(regs_written(inst
)),
3935 /* Get a new VGRF but keep the same stride as inst->dst */
3936 fs_reg
high(VGRF
, alloc
.allocate(regs_written(inst
)), inst
->dst
.type
);
3937 high
.stride
= inst
->dst
.stride
;
3938 high
.offset
= inst
->dst
.offset
% REG_SIZE
;
3940 if (devinfo
->gen
>= 7) {
3941 if (inst
->src
[1].abs
)
3942 lower_src_modifiers(this, block
, inst
, 1);
3944 if (inst
->src
[1].file
== IMM
) {
3945 ibld
.MUL(low
, inst
->src
[0],
3946 brw_imm_uw(inst
->src
[1].ud
& 0xffff));
3947 ibld
.MUL(high
, inst
->src
[0],
3948 brw_imm_uw(inst
->src
[1].ud
>> 16));
3950 ibld
.MUL(low
, inst
->src
[0],
3951 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
3952 ibld
.MUL(high
, inst
->src
[0],
3953 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 1));
3956 if (inst
->src
[0].abs
)
3957 lower_src_modifiers(this, block
, inst
, 0);
3959 ibld
.MUL(low
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 0),
3961 ibld
.MUL(high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UW
, 1),
3965 ibld
.ADD(subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3966 subscript(low
, BRW_REGISTER_TYPE_UW
, 1),
3967 subscript(high
, BRW_REGISTER_TYPE_UW
, 0));
3969 if (needs_mov
|| inst
->conditional_mod
)
3970 set_condmod(inst
->conditional_mod
, ibld
.MOV(orig_dst
, low
));
3975 fs_visitor::lower_mul_qword_inst(fs_inst
*inst
, bblock_t
*block
)
3977 const fs_builder
ibld(this, block
, inst
);
3979 /* Considering two 64-bit integers ab and cd where each letter ab
3980 * corresponds to 32 bits, we get a 128-bit result WXYZ. We * cd
3981 * only need to provide the YZ part of the result. -------
3983 * Only BD needs to be 64 bits. For AD and BC we only care + AD
3984 * about the lower 32 bits (since they are part of the upper + BC
3985 * 32 bits of our result). AC is not needed since it starts + AC
3986 * on the 65th bit of the result. -------
3989 unsigned int q_regs
= regs_written(inst
);
3990 unsigned int d_regs
= (q_regs
+ 1) / 2;
3992 fs_reg
bd(VGRF
, alloc
.allocate(q_regs
), BRW_REGISTER_TYPE_UQ
);
3993 fs_reg
ad(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
3994 fs_reg
bc(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
3996 /* Here we need the full 64 bit result for 32b * 32b. */
3997 if (devinfo
->has_integer_dword_mul
) {
3998 ibld
.MUL(bd
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
3999 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4001 fs_reg
bd_high(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4002 fs_reg
bd_low(VGRF
, alloc
.allocate(d_regs
), BRW_REGISTER_TYPE_UD
);
4003 fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), BRW_REGISTER_TYPE_UD
);
4005 fs_inst
*mul
= ibld
.MUL(acc
,
4006 subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4007 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UW
, 0));
4008 mul
->writes_accumulator
= true;
4010 ibld
.MACH(bd_high
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4011 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4012 ibld
.MOV(bd_low
, acc
);
4014 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 0), bd_low
);
4015 ibld
.MOV(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), bd_high
);
4018 ibld
.MUL(ad
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 1),
4019 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 0));
4020 ibld
.MUL(bc
, subscript(inst
->src
[0], BRW_REGISTER_TYPE_UD
, 0),
4021 subscript(inst
->src
[1], BRW_REGISTER_TYPE_UD
, 1));
4023 ibld
.ADD(ad
, ad
, bc
);
4024 ibld
.ADD(subscript(bd
, BRW_REGISTER_TYPE_UD
, 1),
4025 subscript(bd
, BRW_REGISTER_TYPE_UD
, 1), ad
);
4027 ibld
.MOV(inst
->dst
, bd
);
4031 fs_visitor::lower_mulh_inst(fs_inst
*inst
, bblock_t
*block
)
4033 const fs_builder
ibld(this, block
, inst
);
4035 /* According to the BDW+ BSpec page for the "Multiply Accumulate
4036 * High" instruction:
4038 * "An added preliminary mov is required for source modification on
4040 * mov (8) r3.0<1>:d -r3<8;8,1>:d
4041 * mul (8) acc0:d r2.0<8;8,1>:d r3.0<16;8,2>:uw
4042 * mach (8) r5.0<1>:d r2.0<8;8,1>:d r3.0<8;8,1>:d"
4044 if (devinfo
->gen
>= 8 && (inst
->src
[1].negate
|| inst
->src
[1].abs
))
4045 lower_src_modifiers(this, block
, inst
, 1);
4047 /* Should have been lowered to 8-wide. */
4048 assert(inst
->exec_size
<= get_lowered_simd_width(devinfo
, inst
));
4049 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
), inst
->dst
.type
);
4050 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
4051 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4053 if (devinfo
->gen
>= 8) {
4054 /* Until Gen8, integer multiplies read 32-bits from one source,
4055 * and 16-bits from the other, and relying on the MACH instruction
4056 * to generate the high bits of the result.
4058 * On Gen8, the multiply instruction does a full 32x32-bit
4059 * multiply, but in order to do a 64-bit multiply we can simulate
4060 * the previous behavior and then use a MACH instruction.
4062 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
4063 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
4064 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
4065 mul
->src
[1].stride
*= 2;
4067 if (mul
->src
[1].file
== IMM
) {
4068 mul
->src
[1] = brw_imm_uw(mul
->src
[1].ud
);
4070 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4072 /* Among other things the quarter control bits influence which
4073 * accumulator register is used by the hardware for instructions
4074 * that access the accumulator implicitly (e.g. MACH). A
4075 * second-half instruction would normally map to acc1, which
4076 * doesn't exist on Gen7 and up (the hardware does emulate it for
4077 * floating-point instructions *only* by taking advantage of the
4078 * extra precision of acc0 not normally used for floating point
4081 * HSW and up are careful enough not to try to access an
4082 * accumulator register that doesn't exist, but on earlier Gen7
4083 * hardware we need to make sure that the quarter control bits are
4084 * zero to avoid non-deterministic behaviour and emit an extra MOV
4085 * to get the result masked correctly according to the current
4089 mach
->force_writemask_all
= true;
4090 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
4091 ibld
.MOV(inst
->dst
, mach
->dst
);
4096 fs_visitor::lower_integer_multiplication()
4098 bool progress
= false;
4100 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4101 if (inst
->opcode
== BRW_OPCODE_MUL
) {
4102 /* If the instruction is already in a form that does not need lowering,
4105 if (devinfo
->gen
>= 7) {
4106 if (type_sz(inst
->src
[1].type
) < 4 && type_sz(inst
->src
[0].type
) <= 4)
4109 if (type_sz(inst
->src
[0].type
) < 4 && type_sz(inst
->src
[1].type
) <= 4)
4113 if ((inst
->dst
.type
== BRW_REGISTER_TYPE_Q
||
4114 inst
->dst
.type
== BRW_REGISTER_TYPE_UQ
) &&
4115 (inst
->src
[0].type
== BRW_REGISTER_TYPE_Q
||
4116 inst
->src
[0].type
== BRW_REGISTER_TYPE_UQ
) &&
4117 (inst
->src
[1].type
== BRW_REGISTER_TYPE_Q
||
4118 inst
->src
[1].type
== BRW_REGISTER_TYPE_UQ
)) {
4119 lower_mul_qword_inst(inst
, block
);
4120 inst
->remove(block
);
4122 } else if (!inst
->dst
.is_accumulator() &&
4123 (inst
->dst
.type
== BRW_REGISTER_TYPE_D
||
4124 inst
->dst
.type
== BRW_REGISTER_TYPE_UD
) &&
4125 !devinfo
->has_integer_dword_mul
) {
4126 lower_mul_dword_inst(inst
, block
);
4127 inst
->remove(block
);
4130 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
4131 lower_mulh_inst(inst
, block
);
4132 inst
->remove(block
);
4139 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
4145 fs_visitor::lower_minmax()
4147 assert(devinfo
->gen
< 6);
4149 bool progress
= false;
4151 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4152 const fs_builder
ibld(this, block
, inst
);
4154 if (inst
->opcode
== BRW_OPCODE_SEL
&&
4155 inst
->predicate
== BRW_PREDICATE_NONE
) {
4156 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
4157 * the original SEL.L/GE instruction
4159 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4160 inst
->conditional_mod
);
4161 inst
->predicate
= BRW_PREDICATE_NORMAL
;
4162 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
4169 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
);
4175 fs_visitor::lower_sub_sat()
4177 bool progress
= false;
4179 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4180 const fs_builder
ibld(this, block
, inst
);
4182 if (inst
->opcode
== SHADER_OPCODE_USUB_SAT
||
4183 inst
->opcode
== SHADER_OPCODE_ISUB_SAT
) {
4184 /* The fundamental problem is the hardware performs source negation
4185 * at the bit width of the source. If the source is 0x80000000D, the
4186 * negation is 0x80000000D. As a result, subtractSaturate(0,
4187 * 0x80000000) will produce 0x80000000 instead of 0x7fffffff. There
4188 * are at least three ways to resolve this:
4190 * 1. Use the accumulator for the negated source. The accumulator is
4191 * 33 bits, so our source 0x80000000 is sign-extended to
4192 * 0x1800000000. The negation of which is 0x080000000. This
4193 * doesn't help for 64-bit integers (which are already bigger than
4194 * 33 bits). There are also only 8 accumulators, so SIMD16 or
4195 * SIMD32 instructions would have to be split into multiple SIMD8
4198 * 2. Use slightly different math. For any n-bit value x, we know (x
4199 * >> 1) != -(x >> 1). We can use this fact to only do
4200 * subtractions involving (x >> 1). subtractSaturate(a, b) ==
4201 * subtractSaturate(subtractSaturate(a, (b >> 1)), b - (b >> 1)).
4203 * 3. For unsigned sources, it is sufficient to replace the
4204 * subtractSaturate with (a > b) ? a - b : 0.
4206 * It may also be possible to use the SUBB instruction. This
4207 * implicitly writes the accumulator, so it could only be used in the
4208 * same situations as #1 above. It is further limited by only
4209 * allowing UD sources.
4211 if (inst
->exec_size
== 8 && inst
->src
[0].type
!= BRW_REGISTER_TYPE_Q
&&
4212 inst
->src
[0].type
!= BRW_REGISTER_TYPE_UQ
) {
4213 fs_reg
acc(ARF
, BRW_ARF_ACCUMULATOR
, inst
->src
[1].type
);
4215 ibld
.MOV(acc
, inst
->src
[1]);
4216 fs_inst
*add
= ibld
.ADD(inst
->dst
, acc
, inst
->src
[0]);
4217 add
->saturate
= true;
4218 add
->src
[0].negate
= true;
4219 } else if (inst
->opcode
== SHADER_OPCODE_ISUB_SAT
) {
4221 * dst = add.sat(add.sat(src0, -tmp), -(src1 - tmp));
4223 fs_reg tmp1
= ibld
.vgrf(inst
->src
[0].type
);
4224 fs_reg tmp2
= ibld
.vgrf(inst
->src
[0].type
);
4225 fs_reg tmp3
= ibld
.vgrf(inst
->src
[0].type
);
4228 ibld
.SHR(tmp1
, inst
->src
[1], brw_imm_d(1));
4230 add
= ibld
.ADD(tmp2
, inst
->src
[1], tmp1
);
4231 add
->src
[1].negate
= true;
4233 add
= ibld
.ADD(tmp3
, inst
->src
[0], tmp1
);
4234 add
->src
[1].negate
= true;
4235 add
->saturate
= true;
4237 add
= ibld
.ADD(inst
->dst
, tmp3
, tmp2
);
4238 add
->src
[1].negate
= true;
4239 add
->saturate
= true;
4241 /* a > b ? a - b : 0 */
4242 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
4245 fs_inst
*add
= ibld
.ADD(inst
->dst
, inst
->src
[0], inst
->src
[1]);
4246 add
->src
[1].negate
= !add
->src
[1].negate
;
4248 ibld
.SEL(inst
->dst
, inst
->dst
, brw_imm_ud(0))
4249 ->predicate
= BRW_PREDICATE_NORMAL
;
4252 inst
->remove(block
);
4258 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
4264 * Get the mask of SIMD channels enabled during dispatch and not yet disabled
4265 * by discard. Due to the layout of the sample mask in the fragment shader
4266 * thread payload, \p bld is required to have a dispatch_width() not greater
4267 * than 16 for fragment shaders.
4270 sample_mask_reg(const fs_builder
&bld
)
4272 const fs_visitor
*v
= static_cast<const fs_visitor
*>(bld
.shader
);
4274 if (v
->stage
!= MESA_SHADER_FRAGMENT
) {
4275 return brw_imm_ud(0xffffffff);
4276 } else if (brw_wm_prog_data(v
->stage_prog_data
)->uses_kill
) {
4277 assert(bld
.dispatch_width() <= 16);
4278 return brw_flag_subreg(sample_mask_flag_subreg(v
) + bld
.group() / 16);
4280 assert(v
->devinfo
->gen
>= 6 && bld
.dispatch_width() <= 16);
4281 return retype(brw_vec1_grf((bld
.group() >= 16 ? 2 : 1), 7),
4282 BRW_REGISTER_TYPE_UW
);
4287 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
4288 fs_reg
*dst
, fs_reg color
, unsigned components
)
4290 if (key
->clamp_fragment_color
) {
4291 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
4292 assert(color
.type
== BRW_REGISTER_TYPE_F
);
4294 for (unsigned i
= 0; i
< components
; i
++)
4296 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
4301 for (unsigned i
= 0; i
< components
; i
++)
4302 dst
[i
] = offset(color
, bld
, i
);
4306 brw_fb_write_msg_control(const fs_inst
*inst
,
4307 const struct brw_wm_prog_data
*prog_data
)
4311 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
4312 assert(inst
->group
== 0 && inst
->exec_size
== 16);
4313 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
4314 } else if (prog_data
->dual_src_blend
) {
4315 assert(inst
->exec_size
== 8);
4317 if (inst
->group
% 16 == 0)
4318 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
4319 else if (inst
->group
% 16 == 8)
4320 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
4322 unreachable("Invalid dual-source FB write instruction group");
4324 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
4326 if (inst
->exec_size
== 16)
4327 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
4328 else if (inst
->exec_size
== 8)
4329 mctl
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
4331 unreachable("Invalid FB write execution size");
4338 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
4339 const struct brw_wm_prog_data
*prog_data
,
4340 const brw_wm_prog_key
*key
,
4341 const fs_visitor::thread_payload
&payload
)
4343 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
4344 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4345 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
4346 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
4347 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
4348 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
4349 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
4350 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
4351 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
4352 const unsigned components
=
4353 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
4355 assert(inst
->target
!= 0 || src0_alpha
.file
== BAD_FILE
);
4357 /* We can potentially have a message length of up to 15, so we have to set
4358 * base_mrf to either 0 or 1 in order to fit in m0..m15.
4361 int header_size
= 2, payload_header_size
;
4362 unsigned length
= 0;
4364 if (devinfo
->gen
< 6) {
4365 /* TODO: Support SIMD32 on gen4-5 */
4366 assert(bld
.group() < 16);
4368 /* For gen4-5, we always have a header consisting of g0 and g1. We have
4369 * an implied MOV from g0,g1 to the start of the message. The MOV from
4370 * g0 is handled by the hardware and the MOV from g1 is provided by the
4371 * generator. This is required because, on gen4-5, the generator may
4372 * generate two write messages with different message lengths in order
4373 * to handle AA data properly.
4375 * Also, since the pixel mask goes in the g0 portion of the message and
4376 * since render target writes are the last thing in the shader, we write
4377 * the pixel mask directly into g0 and it will get copied as part of the
4380 if (prog_data
->uses_kill
) {
4381 bld
.exec_all().group(1, 0)
4382 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
),
4383 sample_mask_reg(bld
));
4386 assert(length
== 0);
4388 } else if ((devinfo
->gen
<= 7 && !devinfo
->is_haswell
&&
4389 prog_data
->uses_kill
) ||
4390 (devinfo
->gen
< 11 &&
4391 (color1
.file
!= BAD_FILE
|| key
->nr_color_regions
> 1))) {
4392 /* From the Sandy Bridge PRM, volume 4, page 198:
4394 * "Dispatched Pixel Enables. One bit per pixel indicating
4395 * which pixels were originally enabled when the thread was
4396 * dispatched. This field is only required for the end-of-
4397 * thread message and on all dual-source messages."
4399 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4401 fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4402 if (bld
.group() < 16) {
4403 /* The header starts off as g0 and g1 for the first half */
4404 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4405 BRW_REGISTER_TYPE_UD
));
4407 /* The header starts off as g0 and g2 for the second half */
4408 assert(bld
.group() < 32);
4409 const fs_reg header_sources
[2] = {
4410 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4411 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
),
4413 ubld
.LOAD_PAYLOAD(header
, header_sources
, 2, 0);
4415 /* Gen12 will require additional fix-ups if we ever hit this path. */
4416 assert(devinfo
->gen
< 12);
4419 uint32_t g00_bits
= 0;
4421 /* Set "Source0 Alpha Present to RenderTarget" bit in message
4424 if (src0_alpha
.file
!= BAD_FILE
)
4425 g00_bits
|= 1 << 11;
4427 /* Set computes stencil to render target */
4428 if (prog_data
->computed_stencil
)
4429 g00_bits
|= 1 << 14;
4432 /* OR extra bits into g0.0 */
4433 ubld
.group(1, 0).OR(component(header
, 0),
4434 retype(brw_vec1_grf(0, 0),
4435 BRW_REGISTER_TYPE_UD
),
4436 brw_imm_ud(g00_bits
));
4439 /* Set the render target index for choosing BLEND_STATE. */
4440 if (inst
->target
> 0) {
4441 ubld
.group(1, 0).MOV(component(header
, 2), brw_imm_ud(inst
->target
));
4444 if (prog_data
->uses_kill
) {
4445 ubld
.group(1, 0).MOV(retype(component(header
, 15),
4446 BRW_REGISTER_TYPE_UW
),
4447 sample_mask_reg(bld
));
4450 assert(length
== 0);
4451 sources
[0] = header
;
4452 sources
[1] = horiz_offset(header
, 8);
4455 assert(length
== 0 || length
== 2);
4456 header_size
= length
;
4458 if (payload
.aa_dest_stencil_reg
[0]) {
4459 assert(inst
->group
< 16);
4460 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
4461 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
4462 .MOV(sources
[length
],
4463 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
[0], 0)));
4467 if (src0_alpha
.file
!= BAD_FILE
) {
4468 for (unsigned i
= 0; i
< bld
.dispatch_width() / 8; i
++) {
4469 const fs_builder
&ubld
= bld
.exec_all().group(8, i
)
4470 .annotate("FB write src0 alpha");
4471 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_F
);
4472 ubld
.MOV(tmp
, horiz_offset(src0_alpha
, i
* 8));
4473 setup_color_payload(ubld
, key
, &sources
[length
], tmp
, 1);
4478 if (sample_mask
.file
!= BAD_FILE
) {
4479 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
4480 BRW_REGISTER_TYPE_UD
);
4482 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
4483 * relevant. Since it's unsigned single words one vgrf is always
4484 * 16-wide, but only the lower or higher 8 channels will be used by the
4485 * hardware when doing a SIMD8 write depending on whether we have
4486 * selected the subspans for the first or second half respectively.
4488 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
4489 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
4490 sample_mask
.stride
*= 2;
4492 bld
.exec_all().annotate("FB write oMask")
4493 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
4499 payload_header_size
= length
;
4501 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
4504 if (color1
.file
!= BAD_FILE
) {
4505 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
4509 if (src_depth
.file
!= BAD_FILE
) {
4510 sources
[length
] = src_depth
;
4514 if (dst_depth
.file
!= BAD_FILE
) {
4515 sources
[length
] = dst_depth
;
4519 if (src_stencil
.file
!= BAD_FILE
) {
4520 assert(devinfo
->gen
>= 9);
4521 assert(bld
.dispatch_width() == 8);
4523 /* XXX: src_stencil is only available on gen9+. dst_depth is never
4524 * available on gen9+. As such it's impossible to have both enabled at the
4525 * same time and therefore length cannot overrun the array.
4527 assert(length
< 15);
4529 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4530 bld
.exec_all().annotate("FB write OS")
4531 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
4532 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
4537 if (devinfo
->gen
>= 7) {
4538 /* Send from the GRF */
4539 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
4540 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
4541 payload
.nr
= bld
.shader
->alloc
.allocate(regs_written(load
));
4542 load
->dst
= payload
;
4544 uint32_t msg_ctl
= brw_fb_write_msg_control(inst
, prog_data
);
4545 uint32_t ex_desc
= 0;
4548 (inst
->group
/ 16) << 11 | /* rt slot group */
4549 brw_dp_write_desc(devinfo
, inst
->target
, msg_ctl
,
4550 GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
,
4551 inst
->last_rt
, false);
4553 if (devinfo
->gen
>= 11) {
4554 /* Set the "Render Target Index" and "Src0 Alpha Present" fields
4555 * in the extended message descriptor, in lieu of using a header.
4557 ex_desc
= inst
->target
<< 12 | (src0_alpha
.file
!= BAD_FILE
) << 15;
4559 if (key
->nr_color_regions
== 0)
4560 ex_desc
|= 1 << 20; /* Null Render Target */
4563 inst
->opcode
= SHADER_OPCODE_SEND
;
4564 inst
->resize_sources(3);
4565 inst
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4566 inst
->src
[0] = brw_imm_ud(inst
->desc
);
4567 inst
->src
[1] = brw_imm_ud(ex_desc
);
4568 inst
->src
[2] = payload
;
4569 inst
->mlen
= regs_written(load
);
4571 inst
->header_size
= header_size
;
4572 inst
->check_tdr
= true;
4573 inst
->send_has_side_effects
= true;
4575 /* Send from the MRF */
4576 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
4577 sources
, length
, payload_header_size
);
4579 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
4580 * will do this for us if we just give it a COMPR4 destination.
4582 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
4583 load
->dst
.nr
|= BRW_MRF_COMPR4
;
4585 if (devinfo
->gen
< 6) {
4586 /* Set up src[0] for the implied MOV from grf0-1 */
4587 inst
->resize_sources(1);
4588 inst
->src
[0] = brw_vec8_grf(0, 0);
4590 inst
->resize_sources(0);
4593 inst
->opcode
= FS_OPCODE_FB_WRITE
;
4594 inst
->mlen
= regs_written(load
);
4595 inst
->header_size
= header_size
;
4600 lower_fb_read_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4602 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4603 const fs_builder
&ubld
= bld
.exec_all().group(8, 0);
4604 const unsigned length
= 2;
4605 const fs_reg header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, length
);
4607 if (bld
.group() < 16) {
4608 ubld
.group(16, 0).MOV(header
, retype(brw_vec8_grf(0, 0),
4609 BRW_REGISTER_TYPE_UD
));
4611 assert(bld
.group() < 32);
4612 const fs_reg header_sources
[] = {
4613 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
),
4614 retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_UD
)
4616 ubld
.LOAD_PAYLOAD(header
, header_sources
, ARRAY_SIZE(header_sources
), 0);
4618 if (devinfo
->gen
>= 12) {
4619 /* On Gen12 the Viewport and Render Target Array Index fields (AKA
4620 * Poly 0 Info) are provided in r1.1 instead of r0.0, and the render
4621 * target message header format was updated accordingly -- However
4622 * the updated format only works for the lower 16 channels in a
4623 * SIMD32 thread, since the higher 16 channels want the subspan data
4624 * from r2 instead of r1, so we need to copy over the contents of
4625 * r1.1 in order to fix things up.
4627 ubld
.group(1, 0).MOV(component(header
, 9),
4628 retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_UD
));
4632 inst
->resize_sources(1);
4633 inst
->src
[0] = header
;
4634 inst
->opcode
= FS_OPCODE_FB_READ
;
4635 inst
->mlen
= length
;
4636 inst
->header_size
= length
;
4640 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4641 const fs_reg
&coordinate
,
4642 const fs_reg
&shadow_c
,
4643 const fs_reg
&lod
, const fs_reg
&lod2
,
4644 const fs_reg
&surface
,
4645 const fs_reg
&sampler
,
4646 unsigned coord_components
,
4647 unsigned grad_components
)
4649 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
4650 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
4651 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
4652 fs_reg msg_end
= msg_begin
;
4655 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
4657 for (unsigned i
= 0; i
< coord_components
; i
++)
4658 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
4659 offset(coordinate
, bld
, i
));
4661 msg_end
= offset(msg_end
, bld
, coord_components
);
4663 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
4664 * require all three components to be present and zero if they are unused.
4666 if (coord_components
> 0 &&
4667 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
4668 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
4669 assert(coord_components
<= 3);
4670 for (unsigned i
= 0; i
< 3 - coord_components
; i
++)
4671 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
4673 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
4676 if (op
== SHADER_OPCODE_TXD
) {
4677 /* TXD unsupported in SIMD16 mode. */
4678 assert(bld
.dispatch_width() == 8);
4680 /* the slots for u and v are always present, but r is optional */
4681 if (coord_components
< 2)
4682 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
4685 * dPdx = dudx, dvdx, drdx
4686 * dPdy = dudy, dvdy, drdy
4688 * 1-arg: Does not exist.
4690 * 2-arg: dudx dvdx dudy dvdy
4691 * dPdx.x dPdx.y dPdy.x dPdy.y
4694 * 3-arg: dudx dvdx drdx dudy dvdy drdy
4695 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
4696 * m5 m6 m7 m8 m9 m10
4698 for (unsigned i
= 0; i
< grad_components
; i
++)
4699 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
4701 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4703 for (unsigned i
= 0; i
< grad_components
; i
++)
4704 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
4706 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
4710 /* Bias/LOD with shadow comparator is unsupported in SIMD16 -- *Without*
4711 * shadow comparator (including RESINFO) it's unsupported in SIMD8 mode.
4713 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
4714 bld
.dispatch_width() == 16);
4716 const brw_reg_type type
=
4717 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
4718 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
4719 bld
.MOV(retype(msg_end
, type
), lod
);
4720 msg_end
= offset(msg_end
, bld
, 1);
4723 if (shadow_c
.file
!= BAD_FILE
) {
4724 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
4725 /* There's no plain shadow compare message, so we use shadow
4726 * compare with a bias of 0.0.
4728 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4729 msg_end
= offset(msg_end
, bld
, 1);
4732 bld
.MOV(msg_end
, shadow_c
);
4733 msg_end
= offset(msg_end
, bld
, 1);
4737 inst
->src
[0] = reg_undef
;
4738 inst
->src
[1] = surface
;
4739 inst
->src
[2] = sampler
;
4740 inst
->resize_sources(3);
4741 inst
->base_mrf
= msg_begin
.nr
;
4742 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4743 inst
->header_size
= 1;
4747 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4748 const fs_reg
&coordinate
,
4749 const fs_reg
&shadow_c
,
4750 const fs_reg
&lod
, const fs_reg
&lod2
,
4751 const fs_reg
&sample_index
,
4752 const fs_reg
&surface
,
4753 const fs_reg
&sampler
,
4754 unsigned coord_components
,
4755 unsigned grad_components
)
4757 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4758 fs_reg msg_coords
= message
;
4759 unsigned header_size
= 0;
4761 if (inst
->offset
!= 0) {
4762 /* The offsets set up by the visitor are in the m1 header, so we can't
4769 for (unsigned i
= 0; i
< coord_components
; i
++)
4770 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4771 offset(coordinate
, bld
, i
));
4773 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4774 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4776 if (shadow_c
.file
!= BAD_FILE
) {
4777 fs_reg msg_shadow
= msg_lod
;
4778 bld
.MOV(msg_shadow
, shadow_c
);
4779 msg_lod
= offset(msg_shadow
, bld
, 1);
4784 case SHADER_OPCODE_TXL
:
4786 bld
.MOV(msg_lod
, lod
);
4787 msg_end
= offset(msg_lod
, bld
, 1);
4789 case SHADER_OPCODE_TXD
:
4792 * dPdx = dudx, dvdx, drdx
4793 * dPdy = dudy, dvdy, drdy
4795 * Load up these values:
4796 * - dudx dudy dvdx dvdy drdx drdy
4797 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4800 for (unsigned i
= 0; i
< grad_components
; i
++) {
4801 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4802 msg_end
= offset(msg_end
, bld
, 1);
4804 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4805 msg_end
= offset(msg_end
, bld
, 1);
4808 case SHADER_OPCODE_TXS
:
4809 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4810 bld
.MOV(msg_lod
, lod
);
4811 msg_end
= offset(msg_lod
, bld
, 1);
4813 case SHADER_OPCODE_TXF
:
4814 msg_lod
= offset(msg_coords
, bld
, 3);
4815 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4816 msg_end
= offset(msg_lod
, bld
, 1);
4818 case SHADER_OPCODE_TXF_CMS
:
4819 msg_lod
= offset(msg_coords
, bld
, 3);
4821 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4823 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4824 msg_end
= offset(msg_lod
, bld
, 2);
4831 inst
->src
[0] = reg_undef
;
4832 inst
->src
[1] = surface
;
4833 inst
->src
[2] = sampler
;
4834 inst
->resize_sources(3);
4835 inst
->base_mrf
= message
.nr
;
4836 inst
->mlen
= msg_end
.nr
- message
.nr
;
4837 inst
->header_size
= header_size
;
4839 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4840 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4844 is_high_sampler(const struct gen_device_info
*devinfo
, const fs_reg
&sampler
)
4846 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4849 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4853 sampler_msg_type(const gen_device_info
*devinfo
,
4854 opcode opcode
, bool shadow_compare
)
4856 assert(devinfo
->gen
>= 5);
4858 case SHADER_OPCODE_TEX
:
4859 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
:
4860 GEN5_SAMPLER_MESSAGE_SAMPLE
;
4862 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
:
4863 GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
4864 case SHADER_OPCODE_TXL
:
4865 return shadow_compare
? GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
:
4866 GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
4867 case SHADER_OPCODE_TXL_LZ
:
4868 return shadow_compare
? GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
:
4869 GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
4870 case SHADER_OPCODE_TXS
:
4871 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
4872 return GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
4873 case SHADER_OPCODE_TXD
:
4874 assert(!shadow_compare
|| devinfo
->gen
>= 8 || devinfo
->is_haswell
);
4875 return shadow_compare
? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
:
4876 GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
4877 case SHADER_OPCODE_TXF
:
4878 return GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4879 case SHADER_OPCODE_TXF_LZ
:
4880 assert(devinfo
->gen
>= 9);
4881 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
4882 case SHADER_OPCODE_TXF_CMS_W
:
4883 assert(devinfo
->gen
>= 9);
4884 return GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
4885 case SHADER_OPCODE_TXF_CMS
:
4886 return devinfo
->gen
>= 7 ? GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
:
4887 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
4888 case SHADER_OPCODE_TXF_UMS
:
4889 assert(devinfo
->gen
>= 7);
4890 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
4891 case SHADER_OPCODE_TXF_MCS
:
4892 assert(devinfo
->gen
>= 7);
4893 return GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
4894 case SHADER_OPCODE_LOD
:
4895 return GEN5_SAMPLER_MESSAGE_LOD
;
4896 case SHADER_OPCODE_TG4
:
4897 assert(devinfo
->gen
>= 7);
4898 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
:
4899 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
4901 case SHADER_OPCODE_TG4_OFFSET
:
4902 assert(devinfo
->gen
>= 7);
4903 return shadow_compare
? GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
:
4904 GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
4905 case SHADER_OPCODE_SAMPLEINFO
:
4906 return GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
4908 unreachable("not reached");
4913 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4914 const fs_reg
&coordinate
,
4915 const fs_reg
&shadow_c
,
4916 fs_reg lod
, const fs_reg
&lod2
,
4917 const fs_reg
&min_lod
,
4918 const fs_reg
&sample_index
,
4920 const fs_reg
&surface
,
4921 const fs_reg
&sampler
,
4922 const fs_reg
&surface_handle
,
4923 const fs_reg
&sampler_handle
,
4924 const fs_reg
&tg4_offset
,
4925 unsigned coord_components
,
4926 unsigned grad_components
)
4928 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4929 const brw_stage_prog_data
*prog_data
= bld
.shader
->stage_prog_data
;
4930 unsigned reg_width
= bld
.dispatch_width() / 8;
4931 unsigned header_size
= 0, length
= 0;
4932 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4933 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4934 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4936 /* We must have exactly one of surface/sampler and surface/sampler_handle */
4937 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
4938 assert((sampler
.file
== BAD_FILE
) != (sampler_handle
.file
== BAD_FILE
));
4940 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4941 inst
->offset
!= 0 || inst
->eot
||
4942 op
== SHADER_OPCODE_SAMPLEINFO
||
4943 sampler_handle
.file
!= BAD_FILE
||
4944 is_high_sampler(devinfo
, sampler
)) {
4945 /* For general texture offsets (no txf workaround), we need a header to
4948 * TG4 needs to place its channel select in the header, for interaction
4949 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4950 * larger sampler numbers we need to offset the Sampler State Pointer in
4953 fs_reg header
= retype(sources
[0], BRW_REGISTER_TYPE_UD
);
4957 /* If we're requesting fewer than four channels worth of response,
4958 * and we have an explicit header, we need to set up the sampler
4959 * writemask. It's reversed from normal: 1 means "don't write".
4961 if (!inst
->eot
&& regs_written(inst
) != 4 * reg_width
) {
4962 assert(regs_written(inst
) % reg_width
== 0);
4963 unsigned mask
= ~((1 << (regs_written(inst
) / reg_width
)) - 1) & 0xf;
4964 inst
->offset
|= mask
<< 12;
4967 /* Build the actual header */
4968 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4969 const fs_builder ubld1
= ubld
.group(1, 0);
4970 ubld
.MOV(header
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
4972 ubld1
.MOV(component(header
, 2), brw_imm_ud(inst
->offset
));
4973 } else if (bld
.shader
->stage
!= MESA_SHADER_VERTEX
&&
4974 bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
) {
4975 /* The vertex and fragment stages have g0.2 set to 0, so
4976 * header0.2 is 0 when g0 is copied. Other stages may not, so we
4977 * must set it to 0 to avoid setting undesirable bits in the
4980 ubld1
.MOV(component(header
, 2), brw_imm_ud(0));
4983 if (sampler_handle
.file
!= BAD_FILE
) {
4984 /* Bindless sampler handles aren't relative to the sampler state
4985 * pointer passed into the shader through SAMPLER_STATE_POINTERS_*.
4986 * Instead, it's an absolute pointer relative to dynamic state base
4989 * Sampler states are 16 bytes each and the pointer we give here has
4990 * to be 32-byte aligned. In order to avoid more indirect messages
4991 * than required, we assume that all bindless sampler states are
4992 * 32-byte aligned. This sacrifices a bit of general state base
4993 * address space but means we can do something more efficient in the
4996 ubld1
.MOV(component(header
, 3), sampler_handle
);
4997 } else if (is_high_sampler(devinfo
, sampler
)) {
4998 if (sampler
.file
== BRW_IMMEDIATE_VALUE
) {
4999 assert(sampler
.ud
>= 16);
5000 const int sampler_state_size
= 16; /* 16 bytes */
5002 ubld1
.ADD(component(header
, 3),
5003 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5004 brw_imm_ud(16 * (sampler
.ud
/ 16) * sampler_state_size
));
5006 fs_reg tmp
= ubld1
.vgrf(BRW_REGISTER_TYPE_UD
);
5007 ubld1
.AND(tmp
, sampler
, brw_imm_ud(0x0f0));
5008 ubld1
.SHL(tmp
, tmp
, brw_imm_ud(4));
5009 ubld1
.ADD(component(header
, 3),
5010 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD
),
5016 if (shadow_c
.file
!= BAD_FILE
) {
5017 bld
.MOV(sources
[length
], shadow_c
);
5021 bool coordinate_done
= false;
5023 /* Set up the LOD info */
5026 case SHADER_OPCODE_TXL
:
5027 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
5028 op
= SHADER_OPCODE_TXL_LZ
;
5031 bld
.MOV(sources
[length
], lod
);
5034 case SHADER_OPCODE_TXD
:
5035 /* TXD should have been lowered in SIMD16 mode. */
5036 assert(bld
.dispatch_width() == 8);
5038 /* Load dPdx and the coordinate together:
5039 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
5041 for (unsigned i
= 0; i
< coord_components
; i
++) {
5042 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5044 /* For cube map array, the coordinate is (u,v,r,ai) but there are
5045 * only derivatives for (u, v, r).
5047 if (i
< grad_components
) {
5048 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
5049 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
5053 coordinate_done
= true;
5055 case SHADER_OPCODE_TXS
:
5056 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
5059 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5060 /* We need an LOD; just use 0 */
5061 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), brw_imm_ud(0));
5064 case SHADER_OPCODE_TXF
:
5065 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
5066 * On Gen9 they are u, v, lod, r
5068 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
5070 if (devinfo
->gen
>= 9) {
5071 if (coord_components
>= 2) {
5072 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
5073 offset(coordinate
, bld
, 1));
5075 sources
[length
] = brw_imm_d(0);
5080 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
5081 op
= SHADER_OPCODE_TXF_LZ
;
5083 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
5087 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
5088 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5089 offset(coordinate
, bld
, i
));
5091 coordinate_done
= true;
5094 case SHADER_OPCODE_TXF_CMS
:
5095 case SHADER_OPCODE_TXF_CMS_W
:
5096 case SHADER_OPCODE_TXF_UMS
:
5097 case SHADER_OPCODE_TXF_MCS
:
5098 if (op
== SHADER_OPCODE_TXF_UMS
||
5099 op
== SHADER_OPCODE_TXF_CMS
||
5100 op
== SHADER_OPCODE_TXF_CMS_W
) {
5101 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
5105 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
5106 /* Data from the multisample control surface. */
5107 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
5110 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
5113 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
5114 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
5117 offset(mcs
, bld
, 1));
5122 /* There is no offsetting for this message; just copy in the integer
5123 * texture coordinates.
5125 for (unsigned i
= 0; i
< coord_components
; i
++)
5126 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5127 offset(coordinate
, bld
, i
));
5129 coordinate_done
= true;
5131 case SHADER_OPCODE_TG4_OFFSET
:
5132 /* More crazy intermixing */
5133 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
5134 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5136 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
5137 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
5138 offset(tg4_offset
, bld
, i
));
5140 if (coord_components
== 3) /* r if present */
5141 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
5143 coordinate_done
= true;
5149 /* Set up the coordinate (except for cases where it was done above) */
5150 if (!coordinate_done
) {
5151 for (unsigned i
= 0; i
< coord_components
; i
++)
5152 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
5155 if (min_lod
.file
!= BAD_FILE
) {
5156 /* Account for all of the missing coordinate sources */
5157 length
+= 4 - coord_components
;
5158 if (op
== SHADER_OPCODE_TXD
)
5159 length
+= (3 - grad_components
) * 2;
5161 bld
.MOV(sources
[length
++], min_lod
);
5166 mlen
= length
* reg_width
- header_size
;
5168 mlen
= length
* reg_width
;
5170 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
5171 BRW_REGISTER_TYPE_F
);
5172 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
5174 /* Generate the SEND. */
5175 inst
->opcode
= SHADER_OPCODE_SEND
;
5177 inst
->header_size
= header_size
;
5179 const unsigned msg_type
=
5180 sampler_msg_type(devinfo
, op
, inst
->shadow_compare
);
5181 const unsigned simd_mode
=
5182 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5183 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5185 uint32_t base_binding_table_index
;
5187 case SHADER_OPCODE_TG4
:
5188 case SHADER_OPCODE_TG4_OFFSET
:
5189 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
5191 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5192 base_binding_table_index
= prog_data
->binding_table
.image_start
;
5195 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
5199 inst
->sfid
= BRW_SFID_SAMPLER
;
5200 if (surface
.file
== IMM
&&
5201 (sampler
.file
== IMM
|| sampler_handle
.file
!= BAD_FILE
)) {
5202 inst
->desc
= brw_sampler_desc(devinfo
,
5203 surface
.ud
+ base_binding_table_index
,
5204 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5207 0 /* return_format unused on gen7+ */);
5208 inst
->src
[0] = brw_imm_ud(0);
5209 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5210 } else if (surface_handle
.file
!= BAD_FILE
) {
5211 /* Bindless surface */
5212 assert(devinfo
->gen
>= 9);
5213 inst
->desc
= brw_sampler_desc(devinfo
,
5215 sampler
.file
== IMM
? sampler
.ud
% 16 : 0,
5218 0 /* return_format unused on gen7+ */);
5220 /* For bindless samplers, the entire address is included in the message
5221 * header so we can leave the portion in the message descriptor 0.
5223 if (sampler_handle
.file
!= BAD_FILE
|| sampler
.file
== IMM
) {
5224 inst
->src
[0] = brw_imm_ud(0);
5226 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5227 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5228 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5229 inst
->src
[0] = desc
;
5232 /* We assume that the driver provided the handle in the top 20 bits so
5233 * we can use the surface handle directly as the extended descriptor.
5235 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5237 /* Immediate portion of the descriptor */
5238 inst
->desc
= brw_sampler_desc(devinfo
,
5243 0 /* return_format unused on gen7+ */);
5244 const fs_builder ubld
= bld
.group(1, 0).exec_all();
5245 fs_reg desc
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5246 if (surface
.equals(sampler
)) {
5247 /* This case is common in GL */
5248 ubld
.MUL(desc
, surface
, brw_imm_ud(0x101));
5250 if (sampler_handle
.file
!= BAD_FILE
) {
5251 ubld
.MOV(desc
, surface
);
5252 } else if (sampler
.file
== IMM
) {
5253 ubld
.OR(desc
, surface
, brw_imm_ud(sampler
.ud
<< 8));
5255 ubld
.SHL(desc
, sampler
, brw_imm_ud(8));
5256 ubld
.OR(desc
, desc
, surface
);
5259 if (base_binding_table_index
)
5260 ubld
.ADD(desc
, desc
, brw_imm_ud(base_binding_table_index
));
5261 ubld
.AND(desc
, desc
, brw_imm_ud(0xfff));
5263 inst
->src
[0] = component(desc
, 0);
5264 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5267 inst
->src
[2] = src_payload
;
5268 inst
->resize_sources(3);
5271 /* EOT sampler messages don't make sense to split because it would
5272 * involve ending half of the thread early.
5274 assert(inst
->group
== 0);
5275 /* We need to use SENDC for EOT sampler messages */
5276 inst
->check_tdr
= true;
5277 inst
->send_has_side_effects
= true;
5280 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
5281 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
5285 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
5287 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5288 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
5289 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
5290 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
5291 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
5292 const fs_reg
&min_lod
= inst
->src
[TEX_LOGICAL_SRC_MIN_LOD
];
5293 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
5294 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
5295 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
5296 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
5297 const fs_reg
&surface_handle
= inst
->src
[TEX_LOGICAL_SRC_SURFACE_HANDLE
];
5298 const fs_reg
&sampler_handle
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
];
5299 const fs_reg
&tg4_offset
= inst
->src
[TEX_LOGICAL_SRC_TG4_OFFSET
];
5300 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
5301 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
5302 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
5303 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
5305 if (devinfo
->gen
>= 7) {
5306 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
5307 shadow_c
, lod
, lod2
, min_lod
,
5309 mcs
, surface
, sampler
,
5310 surface_handle
, sampler_handle
,
5312 coord_components
, grad_components
);
5313 } else if (devinfo
->gen
>= 5) {
5314 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
5315 shadow_c
, lod
, lod2
, sample_index
,
5317 coord_components
, grad_components
);
5319 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
5320 shadow_c
, lod
, lod2
,
5322 coord_components
, grad_components
);
5327 * Predicate the specified instruction on the sample mask.
5330 emit_predicate_on_sample_mask(const fs_builder
&bld
, fs_inst
*inst
)
5332 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
&&
5333 bld
.group() == inst
->group
&&
5334 bld
.dispatch_width() == inst
->exec_size
);
5336 const fs_visitor
*v
= static_cast<const fs_visitor
*>(bld
.shader
);
5337 const fs_reg sample_mask
= sample_mask_reg(bld
);
5338 const unsigned subreg
= sample_mask_flag_subreg(v
);
5340 if (brw_wm_prog_data(v
->stage_prog_data
)->uses_kill
) {
5341 assert(sample_mask
.file
== ARF
&&
5342 sample_mask
.nr
== brw_flag_subreg(subreg
).nr
&&
5343 sample_mask
.subnr
== brw_flag_subreg(
5344 subreg
+ inst
->group
/ 16).subnr
);
5346 bld
.group(1, 0).exec_all()
5347 .MOV(brw_flag_subreg(subreg
+ inst
->group
/ 16), sample_mask
);
5350 if (inst
->predicate
) {
5351 assert(inst
->predicate
== BRW_PREDICATE_NORMAL
);
5352 assert(!inst
->predicate_inverse
);
5353 assert(inst
->flag_subreg
== 0);
5354 /* Combine the sample mask with the existing predicate by using a
5355 * vertical predication mode.
5357 inst
->predicate
= BRW_PREDICATE_ALIGN1_ALLV
;
5359 inst
->flag_subreg
= subreg
;
5360 inst
->predicate
= BRW_PREDICATE_NORMAL
;
5361 inst
->predicate_inverse
= false;
5366 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5368 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5370 /* Get the logical send arguments. */
5371 const fs_reg
&addr
= inst
->src
[SURFACE_LOGICAL_SRC_ADDRESS
];
5372 const fs_reg
&src
= inst
->src
[SURFACE_LOGICAL_SRC_DATA
];
5373 const fs_reg
&surface
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE
];
5374 const fs_reg
&surface_handle
= inst
->src
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
];
5375 const UNUSED fs_reg
&dims
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_DIMS
];
5376 const fs_reg
&arg
= inst
->src
[SURFACE_LOGICAL_SRC_IMM_ARG
];
5377 assert(arg
.file
== IMM
);
5379 /* We must have exactly one of surface and surface_handle */
5380 assert((surface
.file
== BAD_FILE
) != (surface_handle
.file
== BAD_FILE
));
5382 /* Calculate the total number of components of the payload. */
5383 const unsigned addr_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_ADDRESS
);
5384 const unsigned src_sz
= inst
->components_read(SURFACE_LOGICAL_SRC_DATA
);
5386 const bool is_typed_access
=
5387 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
||
5388 inst
->opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
||
5389 inst
->opcode
== SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
;
5391 const bool is_surface_access
= is_typed_access
||
5392 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
||
5393 inst
->opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
||
5394 inst
->opcode
== SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
;
5396 const bool is_stateless
=
5397 surface
.file
== IMM
&& (surface
.ud
== BRW_BTI_STATELESS
||
5398 surface
.ud
== GEN8_BTI_STATELESS_NON_COHERENT
);
5400 const bool has_side_effects
= inst
->has_side_effects();
5401 fs_reg sample_mask
= has_side_effects
? sample_mask_reg(bld
) :
5402 fs_reg(brw_imm_d(0xffff));
5404 /* From the BDW PRM Volume 7, page 147:
5406 * "For the Data Cache Data Port*, the header must be present for the
5407 * following message types: [...] Typed read/write/atomics"
5409 * Earlier generations have a similar wording. Because of this restriction
5410 * we don't attempt to implement sample masks via predication for such
5411 * messages prior to Gen9, since we have to provide a header anyway. On
5412 * Gen11+ the header has been removed so we can only use predication.
5414 * For all stateless A32 messages, we also need a header
5417 if ((devinfo
->gen
< 9 && is_typed_access
) || is_stateless
) {
5418 fs_builder ubld
= bld
.exec_all().group(8, 0);
5419 header
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5420 ubld
.MOV(header
, brw_imm_d(0));
5422 /* Both the typed and scattered byte/dword A32 messages take a buffer
5423 * base address in R0.5:[31:0] (See MH1_A32_PSM for typed messages or
5424 * MH_A32_GO for byte/dword scattered messages in the SKL PRM Vol. 2d
5425 * for more details.) This is conveniently where the HW places the
5426 * scratch surface base address.
5428 * From the SKL PRM Vol. 7 "Per-Thread Scratch Space":
5430 * "When a thread becomes 'active' it is allocated a portion of
5431 * scratch space, sized according to PerThreadScratchSpace. The
5432 * starting location of each thread’s scratch space allocation,
5433 * ScratchSpaceOffset, is passed in the thread payload in
5434 * R0.5[31:10] and is specified as a 1KB-granular offset from the
5435 * GeneralStateBaseAddress. The computation of ScratchSpaceOffset
5436 * includes the starting address of the stage’s scratch space
5437 * allocation, as programmed by ScratchSpaceBasePointer."
5439 * The base address is passed in bits R0.5[31:10] and the bottom 10
5440 * bits of R0.5 are used for other things. Therefore, we have to
5441 * mask off the bottom 10 bits so that we don't get a garbage base
5444 ubld
.group(1, 0).AND(component(header
, 5),
5445 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD
),
5446 brw_imm_ud(0xfffffc00));
5448 if (is_surface_access
)
5449 ubld
.group(1, 0).MOV(component(header
, 7), sample_mask
);
5451 const unsigned header_sz
= header
.file
!= BAD_FILE
? 1 : 0;
5453 fs_reg payload
, payload2
;
5454 unsigned mlen
, ex_mlen
= 0;
5455 if (devinfo
->gen
>= 9 &&
5456 (src
.file
== BAD_FILE
|| header
.file
== BAD_FILE
)) {
5457 /* We have split sends on gen9 and above */
5458 if (header
.file
== BAD_FILE
) {
5459 payload
= bld
.move_to_vgrf(addr
, addr_sz
);
5460 payload2
= bld
.move_to_vgrf(src
, src_sz
);
5461 mlen
= addr_sz
* (inst
->exec_size
/ 8);
5462 ex_mlen
= src_sz
* (inst
->exec_size
/ 8);
5464 assert(src
.file
== BAD_FILE
);
5466 payload2
= bld
.move_to_vgrf(addr
, addr_sz
);
5468 ex_mlen
= addr_sz
* (inst
->exec_size
/ 8);
5471 /* Allocate space for the payload. */
5472 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
5473 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
5474 fs_reg
*const components
= new fs_reg
[sz
];
5477 /* Construct the payload. */
5478 if (header
.file
!= BAD_FILE
)
5479 components
[n
++] = header
;
5481 for (unsigned i
= 0; i
< addr_sz
; i
++)
5482 components
[n
++] = offset(addr
, bld
, i
);
5484 for (unsigned i
= 0; i
< src_sz
; i
++)
5485 components
[n
++] = offset(src
, bld
, i
);
5487 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
5488 mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
5490 delete[] components
;
5493 /* Predicate the instruction on the sample mask if no header is
5496 if ((header
.file
== BAD_FILE
|| !is_surface_access
) &&
5497 sample_mask
.file
!= BAD_FILE
&& sample_mask
.file
!= IMM
)
5498 emit_predicate_on_sample_mask(bld
, inst
);
5501 switch (inst
->opcode
) {
5502 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5503 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5504 /* Byte scattered opcodes go through the normal data cache */
5505 sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
5508 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5509 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5510 sfid
= devinfo
->gen
>= 7 ? GEN7_SFID_DATAPORT_DATA_CACHE
:
5511 devinfo
->gen
>= 6 ? GEN6_SFID_DATAPORT_RENDER_CACHE
:
5512 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
;
5515 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5516 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5517 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5518 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5519 /* Untyped Surface messages go through the data cache but the SFID value
5520 * changed on Haswell.
5522 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5523 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5524 GEN7_SFID_DATAPORT_DATA_CACHE
);
5527 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5528 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5529 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5530 /* Typed surface messages go through the render cache on IVB and the
5531 * data cache on HSW+.
5533 sfid
= (devinfo
->gen
>= 8 || devinfo
->is_haswell
?
5534 HSW_SFID_DATAPORT_DATA_CACHE_1
:
5535 GEN6_SFID_DATAPORT_RENDER_CACHE
);
5539 unreachable("Unsupported surface opcode");
5543 switch (inst
->opcode
) {
5544 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5545 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5546 arg
.ud
, /* num_channels */
5550 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5551 desc
= brw_dp_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5552 arg
.ud
, /* num_channels */
5556 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5557 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5558 arg
.ud
, /* bit_size */
5562 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5563 desc
= brw_dp_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5564 arg
.ud
, /* bit_size */
5568 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5569 assert(arg
.ud
== 32); /* bit_size */
5570 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5574 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5575 assert(arg
.ud
== 32); /* bit_size */
5576 desc
= brw_dp_dword_scattered_rw_desc(devinfo
, inst
->exec_size
,
5580 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5581 desc
= brw_dp_untyped_atomic_desc(devinfo
, inst
->exec_size
,
5582 arg
.ud
, /* atomic_op */
5583 !inst
->dst
.is_null());
5586 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5587 desc
= brw_dp_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5588 arg
.ud
, /* atomic_op */
5589 !inst
->dst
.is_null());
5592 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5593 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5594 arg
.ud
, /* num_channels */
5598 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5599 desc
= brw_dp_typed_surface_rw_desc(devinfo
, inst
->exec_size
, inst
->group
,
5600 arg
.ud
, /* num_channels */
5604 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5605 desc
= brw_dp_typed_atomic_desc(devinfo
, inst
->exec_size
, inst
->group
,
5606 arg
.ud
, /* atomic_op */
5607 !inst
->dst
.is_null());
5611 unreachable("Unknown surface logical instruction");
5614 /* Update the original instruction. */
5615 inst
->opcode
= SHADER_OPCODE_SEND
;
5617 inst
->ex_mlen
= ex_mlen
;
5618 inst
->header_size
= header_sz
;
5619 inst
->send_has_side_effects
= has_side_effects
;
5620 inst
->send_is_volatile
= !has_side_effects
;
5622 /* Set up SFID and descriptors */
5625 if (surface
.file
== IMM
) {
5626 inst
->desc
|= surface
.ud
& 0xff;
5627 inst
->src
[0] = brw_imm_ud(0);
5628 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5629 } else if (surface_handle
.file
!= BAD_FILE
) {
5630 /* Bindless surface */
5631 assert(devinfo
->gen
>= 9);
5632 inst
->desc
|= GEN9_BTI_BINDLESS
;
5633 inst
->src
[0] = brw_imm_ud(0);
5635 /* We assume that the driver provided the handle in the top 20 bits so
5636 * we can use the surface handle directly as the extended descriptor.
5638 inst
->src
[1] = retype(surface_handle
, BRW_REGISTER_TYPE_UD
);
5640 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5641 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5642 ubld
.AND(tmp
, surface
, brw_imm_ud(0xff));
5643 inst
->src
[0] = component(tmp
, 0);
5644 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5647 /* Finally, the payload */
5648 inst
->src
[2] = payload
;
5649 inst
->src
[3] = payload2
;
5651 inst
->resize_sources(4);
5655 lower_a64_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5657 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5659 const fs_reg
&addr
= inst
->src
[0];
5660 const fs_reg
&src
= inst
->src
[1];
5661 const unsigned src_comps
= inst
->components_read(1);
5662 assert(inst
->src
[2].file
== IMM
);
5663 const unsigned arg
= inst
->src
[2].ud
;
5664 const bool has_side_effects
= inst
->has_side_effects();
5666 /* If the surface message has side effects and we're a fragment shader, we
5667 * have to predicate with the sample mask to avoid helper invocations.
5669 if (has_side_effects
&& bld
.shader
->stage
== MESA_SHADER_FRAGMENT
)
5670 emit_predicate_on_sample_mask(bld
, inst
);
5672 fs_reg payload
, payload2
;
5673 unsigned mlen
, ex_mlen
= 0;
5674 if (devinfo
->gen
>= 9) {
5675 /* On Skylake and above, we have SENDS */
5676 mlen
= 2 * (inst
->exec_size
/ 8);
5677 ex_mlen
= src_comps
* type_sz(src
.type
) * inst
->exec_size
/ REG_SIZE
;
5678 payload
= retype(bld
.move_to_vgrf(addr
, 1), BRW_REGISTER_TYPE_UD
);
5679 payload2
= retype(bld
.move_to_vgrf(src
, src_comps
),
5680 BRW_REGISTER_TYPE_UD
);
5682 /* Add two because the address is 64-bit */
5683 const unsigned dwords
= 2 + src_comps
;
5684 mlen
= dwords
* (inst
->exec_size
/ 8);
5690 for (unsigned i
= 0; i
< src_comps
; i
++)
5691 sources
[1 + i
] = offset(src
, bld
, i
);
5693 payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, dwords
);
5694 bld
.LOAD_PAYLOAD(payload
, sources
, 1 + src_comps
, 0);
5698 switch (inst
->opcode
) {
5699 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5700 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5701 arg
, /* num_channels */
5705 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5706 desc
= brw_dp_a64_untyped_surface_rw_desc(devinfo
, inst
->exec_size
,
5707 arg
, /* num_channels */
5711 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5712 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5717 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5718 desc
= brw_dp_a64_byte_scattered_rw_desc(devinfo
, inst
->exec_size
,
5723 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5724 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 32,
5725 arg
, /* atomic_op */
5726 !inst
->dst
.is_null());
5729 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5730 desc
= brw_dp_a64_untyped_atomic_desc(devinfo
, inst
->exec_size
, 64,
5731 arg
, /* atomic_op */
5732 !inst
->dst
.is_null());
5736 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5737 desc
= brw_dp_a64_untyped_atomic_float_desc(devinfo
, inst
->exec_size
,
5738 arg
, /* atomic_op */
5739 !inst
->dst
.is_null());
5743 unreachable("Unknown A64 logical instruction");
5746 /* Update the original instruction. */
5747 inst
->opcode
= SHADER_OPCODE_SEND
;
5749 inst
->ex_mlen
= ex_mlen
;
5750 inst
->header_size
= 0;
5751 inst
->send_has_side_effects
= has_side_effects
;
5752 inst
->send_is_volatile
= !has_side_effects
;
5754 /* Set up SFID and descriptors */
5755 inst
->sfid
= HSW_SFID_DATAPORT_DATA_CACHE_1
;
5757 inst
->resize_sources(4);
5758 inst
->src
[0] = brw_imm_ud(0); /* desc */
5759 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5760 inst
->src
[2] = payload
;
5761 inst
->src
[3] = payload2
;
5765 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5767 const gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5769 if (devinfo
->gen
>= 7) {
5770 fs_reg index
= inst
->src
[0];
5771 /* We are switching the instruction from an ALU-like instruction to a
5772 * send-from-grf instruction. Since sends can't handle strides or
5773 * source modifiers, we have to make a copy of the offset source.
5775 fs_reg offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5776 bld
.MOV(offset
, inst
->src
[1]);
5778 const unsigned simd_mode
=
5779 inst
->exec_size
<= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8
:
5780 BRW_SAMPLER_SIMD_MODE_SIMD16
;
5782 inst
->opcode
= SHADER_OPCODE_SEND
;
5783 inst
->mlen
= inst
->exec_size
/ 8;
5784 inst
->resize_sources(3);
5786 inst
->sfid
= BRW_SFID_SAMPLER
;
5787 inst
->desc
= brw_sampler_desc(devinfo
, 0, 0,
5788 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
5790 if (index
.file
== IMM
) {
5791 inst
->desc
|= index
.ud
& 0xff;
5792 inst
->src
[0] = brw_imm_ud(0);
5794 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5795 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
5796 ubld
.AND(tmp
, index
, brw_imm_ud(0xff));
5797 inst
->src
[0] = component(tmp
, 0);
5799 inst
->src
[1] = brw_imm_ud(0); /* ex_desc */
5800 inst
->src
[2] = offset
; /* payload */
5802 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
5803 BRW_REGISTER_TYPE_UD
);
5805 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
5807 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
5808 inst
->resize_sources(1);
5809 inst
->base_mrf
= payload
.nr
;
5810 inst
->header_size
= 1;
5811 inst
->mlen
= 1 + inst
->exec_size
/ 8;
5816 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
5818 assert(bld
.shader
->devinfo
->gen
< 6);
5821 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
5823 if (inst
->sources
> 1) {
5824 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
5825 * "Message Payload":
5827 * "Operand0[7]. For the INT DIV functions, this operand is the
5830 * "Operand1[7]. For the INT DIV functions, this operand is the
5833 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
5834 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
5835 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
5837 inst
->resize_sources(1);
5838 inst
->src
[0] = src0
;
5840 assert(inst
->exec_size
== 8);
5841 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
5846 fs_visitor::lower_logical_sends()
5848 bool progress
= false;
5850 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5851 const fs_builder
ibld(this, block
, inst
);
5853 switch (inst
->opcode
) {
5854 case FS_OPCODE_FB_WRITE_LOGICAL
:
5855 assert(stage
== MESA_SHADER_FRAGMENT
);
5856 lower_fb_write_logical_send(ibld
, inst
,
5857 brw_wm_prog_data(prog_data
),
5858 (const brw_wm_prog_key
*)key
,
5862 case FS_OPCODE_FB_READ_LOGICAL
:
5863 lower_fb_read_logical_send(ibld
, inst
);
5866 case SHADER_OPCODE_TEX_LOGICAL
:
5867 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
5870 case SHADER_OPCODE_TXD_LOGICAL
:
5871 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
5874 case SHADER_OPCODE_TXF_LOGICAL
:
5875 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
5878 case SHADER_OPCODE_TXL_LOGICAL
:
5879 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
5882 case SHADER_OPCODE_TXS_LOGICAL
:
5883 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
5886 case SHADER_OPCODE_IMAGE_SIZE_LOGICAL
:
5887 lower_sampler_logical_send(ibld
, inst
,
5888 SHADER_OPCODE_IMAGE_SIZE_LOGICAL
);
5891 case FS_OPCODE_TXB_LOGICAL
:
5892 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
5895 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
5896 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
5899 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
5900 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
5903 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
5904 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
5907 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
5908 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
5911 case SHADER_OPCODE_LOD_LOGICAL
:
5912 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
5915 case SHADER_OPCODE_TG4_LOGICAL
:
5916 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
5919 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
5920 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
5923 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
5924 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
5927 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5928 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5929 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
5930 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
5931 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
5932 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
5933 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5934 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5935 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5936 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5937 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5938 lower_surface_logical_send(ibld
, inst
);
5941 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
5942 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
5943 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
5944 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
5945 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
5946 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
5947 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
5948 lower_a64_logical_send(ibld
, inst
);
5951 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
5952 lower_varying_pull_constant_logical_send(ibld
, inst
);
5955 case SHADER_OPCODE_RCP
:
5956 case SHADER_OPCODE_RSQ
:
5957 case SHADER_OPCODE_SQRT
:
5958 case SHADER_OPCODE_EXP2
:
5959 case SHADER_OPCODE_LOG2
:
5960 case SHADER_OPCODE_SIN
:
5961 case SHADER_OPCODE_COS
:
5962 case SHADER_OPCODE_POW
:
5963 case SHADER_OPCODE_INT_QUOTIENT
:
5964 case SHADER_OPCODE_INT_REMAINDER
:
5965 /* The math opcodes are overloaded for the send-like and
5966 * expression-like instructions which seems kind of icky. Gen6+ has
5967 * a native (but rather quirky) MATH instruction so we don't need to
5968 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
5969 * logical instructions (which we can easily recognize because they
5970 * have mlen = 0) into send-like virtual instructions.
5972 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
5973 lower_math_logical_send(ibld
, inst
);
5988 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
5994 is_mixed_float_with_fp32_dst(const fs_inst
*inst
)
5996 /* This opcode sometimes uses :W type on the source even if the operand is
5997 * a :HF, because in gen7 there is no support for :HF, and thus it uses :W.
5999 if (inst
->opcode
== BRW_OPCODE_F16TO32
)
6002 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_F
)
6005 for (int i
= 0; i
< inst
->sources
; i
++) {
6006 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_HF
)
6014 is_mixed_float_with_packed_fp16_dst(const fs_inst
*inst
)
6016 /* This opcode sometimes uses :W type on the destination even if the
6017 * destination is a :HF, because in gen7 there is no support for :HF, and
6020 if (inst
->opcode
== BRW_OPCODE_F32TO16
&&
6021 inst
->dst
.stride
== 1)
6024 if (inst
->dst
.type
!= BRW_REGISTER_TYPE_HF
||
6025 inst
->dst
.stride
!= 1)
6028 for (int i
= 0; i
< inst
->sources
; i
++) {
6029 if (inst
->src
[i
].type
== BRW_REGISTER_TYPE_F
)
6037 * Get the closest allowed SIMD width for instruction \p inst accounting for
6038 * some common regioning and execution control restrictions that apply to FPU
6039 * instructions. These restrictions don't necessarily have any relevance to
6040 * instructions not executed by the FPU pipeline like extended math, control
6041 * flow or send message instructions.
6043 * For virtual opcodes it's really up to the instruction -- In some cases
6044 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
6045 * instructions) it may simplify virtual instruction lowering if we can
6046 * enforce FPU-like regioning restrictions already on the virtual instruction,
6047 * in other cases (e.g. virtual send-like instructions) this may be
6048 * excessively restrictive.
6051 get_fpu_lowered_simd_width(const struct gen_device_info
*devinfo
,
6052 const fs_inst
*inst
)
6054 /* Maximum execution size representable in the instruction controls. */
6055 unsigned max_width
= MIN2(32, inst
->exec_size
);
6057 /* According to the PRMs:
6058 * "A. In Direct Addressing mode, a source cannot span more than 2
6059 * adjacent GRF registers.
6060 * B. A destination cannot span more than 2 adjacent GRF registers."
6062 * Look for the source or destination with the largest register region
6063 * which is the one that is going to limit the overall execution size of
6064 * the instruction due to this rule.
6066 unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6068 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6069 reg_count
= MAX2(reg_count
, DIV_ROUND_UP(inst
->size_read(i
), REG_SIZE
));
6071 /* Calculate the maximum execution size of the instruction based on the
6072 * factor by which it goes over the hardware limit of 2 GRFs.
6075 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
6077 /* According to the IVB PRMs:
6078 * "When destination spans two registers, the source MUST span two
6079 * registers. The exception to the above rule:
6081 * - When source is scalar, the source registers are not incremented.
6082 * - When source is packed integer Word and destination is packed
6083 * integer DWord, the source register is not incremented but the
6084 * source sub register is incremented."
6086 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
6087 * restrictions. The code below intentionally doesn't check whether the
6088 * destination type is integer because empirically the hardware doesn't
6089 * seem to care what the actual type is as long as it's dword-aligned.
6091 if (devinfo
->gen
< 8) {
6092 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6093 /* IVB implements DF scalars as <0;2,1> regions. */
6094 const bool is_scalar_exception
= is_uniform(inst
->src
[i
]) &&
6095 (devinfo
->is_haswell
|| type_sz(inst
->src
[i
].type
) != 8);
6096 const bool is_packed_word_exception
=
6097 type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
6098 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1;
6100 /* We check size_read(i) against size_written instead of REG_SIZE
6101 * because we want to properly handle SIMD32. In SIMD32, you can end
6102 * up with writes to 4 registers and a source that reads 2 registers
6103 * and we may still need to lower all the way to SIMD8 in that case.
6105 if (inst
->size_written
> REG_SIZE
&&
6106 inst
->size_read(i
) != 0 &&
6107 inst
->size_read(i
) < inst
->size_written
&&
6108 !is_scalar_exception
&& !is_packed_word_exception
) {
6109 const unsigned reg_count
= DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6110 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6115 if (devinfo
->gen
< 6) {
6116 /* From the G45 PRM, Volume 4 Page 361:
6118 * "Operand Alignment Rule: With the exceptions listed below, a
6119 * source/destination operand in general should be aligned to even
6120 * 256-bit physical register with a region size equal to two 256-bit
6121 * physical registers."
6123 * Normally we enforce this by allocating virtual registers to the
6124 * even-aligned class. But we need to handle payload registers.
6126 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6127 if (inst
->src
[i
].file
== FIXED_GRF
&& (inst
->src
[i
].nr
& 1) &&
6128 inst
->size_read(i
) > REG_SIZE
) {
6129 max_width
= MIN2(max_width
, 8);
6134 /* From the IVB PRMs:
6135 * "When an instruction is SIMD32, the low 16 bits of the execution mask
6136 * are applied for both halves of the SIMD32 instruction. If different
6137 * execution mask channels are required, split the instruction into two
6138 * SIMD16 instructions."
6140 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
6141 * 32-wide control flow support in hardware and will behave similarly.
6143 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
6144 max_width
= MIN2(max_width
, 16);
6146 /* From the IVB PRMs (applies to HSW too):
6147 * "Instructions with condition modifiers must not use SIMD32."
6149 * From the BDW PRMs (applies to later hardware too):
6150 * "Ternary instruction with condition modifiers must not use SIMD32."
6152 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
6153 max_width
= MIN2(max_width
, 16);
6155 /* From the IVB PRMs (applies to other devices that don't have the
6156 * gen_device_info::supports_simd16_3src flag set):
6157 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
6158 * SIMD8 is not allowed for DF operations."
6160 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
6161 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
6163 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
6164 * the 8-bit quarter of the execution mask signals specified in the
6165 * instruction control fields) for the second compressed half of any
6166 * single-precision instruction (for double-precision instructions
6167 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
6168 * the EU will apply the wrong execution controls for the second
6169 * sequential GRF write if the number of channels per GRF is not exactly
6170 * eight in single-precision mode (or four in double-float mode).
6172 * In this situation we calculate the maximum size of the split
6173 * instructions so they only ever write to a single register.
6175 if (devinfo
->gen
< 8 && inst
->size_written
> REG_SIZE
&&
6176 !inst
->force_writemask_all
) {
6177 const unsigned channels_per_grf
= inst
->exec_size
/
6178 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
);
6179 const unsigned exec_type_size
= get_exec_type_size(inst
);
6180 assert(exec_type_size
);
6182 /* The hardware shifts exactly 8 channels per compressed half of the
6183 * instruction in single-precision mode and exactly 4 in double-precision.
6185 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
6186 max_width
= MIN2(max_width
, channels_per_grf
);
6188 /* Lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYT
6189 * because HW applies the same channel enable signals to both halves of
6190 * the compressed instruction which will be just wrong under
6191 * non-uniform control flow.
6193 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6194 (exec_type_size
== 8 || type_sz(inst
->dst
.type
) == 8))
6195 max_width
= MIN2(max_width
, 4);
6198 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6201 * "No SIMD16 in mixed mode when destination is f32. Instruction
6202 * execution size must be no more than 8."
6204 * FIXME: the simulator doesn't seem to complain if we don't do this and
6205 * empirical testing with existing CTS tests show that they pass just fine
6206 * without implementing this, however, since our interpretation of the PRM
6207 * is that conversion MOVs between HF and F are still mixed-float
6208 * instructions (and therefore subject to this restriction) we decided to
6209 * split them to be safe. Might be useful to do additional investigation to
6210 * lift the restriction if we can ensure that it is safe though, since these
6211 * conversions are common when half-float types are involved since many
6212 * instructions do not support HF types and conversions from/to F are
6215 if (is_mixed_float_with_fp32_dst(inst
))
6216 max_width
= MIN2(max_width
, 8);
6218 /* From the SKL PRM, Special Restrictions for Handling Mixed Mode
6221 * "No SIMD16 in mixed mode when destination is packed f16 for both
6222 * Align1 and Align16."
6224 if (is_mixed_float_with_packed_fp16_dst(inst
))
6225 max_width
= MIN2(max_width
, 8);
6227 /* Only power-of-two execution sizes are representable in the instruction
6230 return 1 << util_logbase2(max_width
);
6234 * Get the maximum allowed SIMD width for instruction \p inst accounting for
6235 * various payload size restrictions that apply to sampler message
6238 * This is only intended to provide a maximum theoretical bound for the
6239 * execution size of the message based on the number of argument components
6240 * alone, which in most cases will determine whether the SIMD8 or SIMD16
6241 * variant of the message can be used, though some messages may have
6242 * additional restrictions not accounted for here (e.g. pre-ILK hardware uses
6243 * the message length to determine the exact SIMD width and argument count,
6244 * which makes a number of sampler message combinations impossible to
6248 get_sampler_lowered_simd_width(const struct gen_device_info
*devinfo
,
6249 const fs_inst
*inst
)
6251 /* If we have a min_lod parameter on anything other than a simple sample
6252 * message, it will push it over 5 arguments and we have to fall back to
6255 if (inst
->opcode
!= SHADER_OPCODE_TEX
&&
6256 inst
->components_read(TEX_LOGICAL_SRC_MIN_LOD
))
6259 /* Calculate the number of coordinate components that have to be present
6260 * assuming that additional arguments follow the texel coordinates in the
6261 * message payload. On IVB+ there is no need for padding, on ILK-SNB we
6262 * need to pad to four or three components depending on the message,
6263 * pre-ILK we need to pad to at most three components.
6265 const unsigned req_coord_components
=
6266 (devinfo
->gen
>= 7 ||
6267 !inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
)) ? 0 :
6268 (devinfo
->gen
>= 5 && inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
6269 inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
) ? 4 :
6272 /* On Gen9+ the LOD argument is for free if we're able to use the LZ
6273 * variant of the TXL or TXF message.
6275 const bool implicit_lod
= devinfo
->gen
>= 9 &&
6276 (inst
->opcode
== SHADER_OPCODE_TXL
||
6277 inst
->opcode
== SHADER_OPCODE_TXF
) &&
6278 inst
->src
[TEX_LOGICAL_SRC_LOD
].is_zero();
6280 /* Calculate the total number of argument components that need to be passed
6281 * to the sampler unit.
6283 const unsigned num_payload_components
=
6284 MAX2(inst
->components_read(TEX_LOGICAL_SRC_COORDINATE
),
6285 req_coord_components
) +
6286 inst
->components_read(TEX_LOGICAL_SRC_SHADOW_C
) +
6287 (implicit_lod
? 0 : inst
->components_read(TEX_LOGICAL_SRC_LOD
)) +
6288 inst
->components_read(TEX_LOGICAL_SRC_LOD2
) +
6289 inst
->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX
) +
6290 (inst
->opcode
== SHADER_OPCODE_TG4_OFFSET_LOGICAL
?
6291 inst
->components_read(TEX_LOGICAL_SRC_TG4_OFFSET
) : 0) +
6292 inst
->components_read(TEX_LOGICAL_SRC_MCS
);
6294 /* SIMD16 messages with more than five arguments exceed the maximum message
6295 * size supported by the sampler, regardless of whether a header is
6298 return MIN2(inst
->exec_size
,
6299 num_payload_components
> MAX_SAMPLER_MESSAGE_SIZE
/ 2 ? 8 : 16);
6303 * Get the closest native SIMD width supported by the hardware for instruction
6304 * \p inst. The instruction will be left untouched by
6305 * fs_visitor::lower_simd_width() if the returned value is equal to the
6306 * original execution size.
6309 get_lowered_simd_width(const struct gen_device_info
*devinfo
,
6310 const fs_inst
*inst
)
6312 switch (inst
->opcode
) {
6313 case BRW_OPCODE_MOV
:
6314 case BRW_OPCODE_SEL
:
6315 case BRW_OPCODE_NOT
:
6316 case BRW_OPCODE_AND
:
6318 case BRW_OPCODE_XOR
:
6319 case BRW_OPCODE_SHR
:
6320 case BRW_OPCODE_SHL
:
6321 case BRW_OPCODE_ASR
:
6322 case BRW_OPCODE_ROR
:
6323 case BRW_OPCODE_ROL
:
6324 case BRW_OPCODE_CMPN
:
6325 case BRW_OPCODE_CSEL
:
6326 case BRW_OPCODE_F32TO16
:
6327 case BRW_OPCODE_F16TO32
:
6328 case BRW_OPCODE_BFREV
:
6329 case BRW_OPCODE_BFE
:
6330 case BRW_OPCODE_ADD
:
6331 case BRW_OPCODE_MUL
:
6332 case BRW_OPCODE_AVG
:
6333 case BRW_OPCODE_FRC
:
6334 case BRW_OPCODE_RNDU
:
6335 case BRW_OPCODE_RNDD
:
6336 case BRW_OPCODE_RNDE
:
6337 case BRW_OPCODE_RNDZ
:
6338 case BRW_OPCODE_LZD
:
6339 case BRW_OPCODE_FBH
:
6340 case BRW_OPCODE_FBL
:
6341 case BRW_OPCODE_CBIT
:
6342 case BRW_OPCODE_SAD2
:
6343 case BRW_OPCODE_MAD
:
6344 case BRW_OPCODE_LRP
:
6345 case FS_OPCODE_PACK
:
6346 case SHADER_OPCODE_SEL_EXEC
:
6347 case SHADER_OPCODE_CLUSTER_BROADCAST
:
6348 return get_fpu_lowered_simd_width(devinfo
, inst
);
6350 case BRW_OPCODE_CMP
: {
6351 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
6352 * when the destination is a GRF the dependency-clear bit on the flag
6353 * register is cleared early.
6355 * Suggested workarounds are to disable coissuing CMP instructions
6356 * or to split CMP(16) instructions into two CMP(8) instructions.
6358 * We choose to split into CMP(8) instructions since disabling
6359 * coissuing would affect CMP instructions not otherwise affected by
6362 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
6363 !inst
->dst
.is_null() ? 8 : ~0);
6364 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
6366 case BRW_OPCODE_BFI1
:
6367 case BRW_OPCODE_BFI2
:
6368 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
6370 * "Force BFI instructions to be executed always in SIMD8."
6372 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
6373 get_fpu_lowered_simd_width(devinfo
, inst
));
6376 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
6377 return inst
->exec_size
;
6379 case SHADER_OPCODE_RCP
:
6380 case SHADER_OPCODE_RSQ
:
6381 case SHADER_OPCODE_SQRT
:
6382 case SHADER_OPCODE_EXP2
:
6383 case SHADER_OPCODE_LOG2
:
6384 case SHADER_OPCODE_SIN
:
6385 case SHADER_OPCODE_COS
: {
6386 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
6387 * Gen6. Extended Math Function is limited to SIMD8 with half-float.
6389 if (devinfo
->gen
== 6 || (devinfo
->gen
== 4 && !devinfo
->is_g4x
))
6390 return MIN2(8, inst
->exec_size
);
6391 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6392 return MIN2(8, inst
->exec_size
);
6393 return MIN2(16, inst
->exec_size
);
6396 case SHADER_OPCODE_POW
: {
6397 /* SIMD16 is only allowed on Gen7+. Extended Math Function is limited
6398 * to SIMD8 with half-float
6400 if (devinfo
->gen
< 7)
6401 return MIN2(8, inst
->exec_size
);
6402 if (inst
->dst
.type
== BRW_REGISTER_TYPE_HF
)
6403 return MIN2(8, inst
->exec_size
);
6404 return MIN2(16, inst
->exec_size
);
6407 case SHADER_OPCODE_USUB_SAT
:
6408 case SHADER_OPCODE_ISUB_SAT
:
6409 return get_fpu_lowered_simd_width(devinfo
, inst
);
6411 case SHADER_OPCODE_INT_QUOTIENT
:
6412 case SHADER_OPCODE_INT_REMAINDER
:
6413 /* Integer division is limited to SIMD8 on all generations. */
6414 return MIN2(8, inst
->exec_size
);
6416 case FS_OPCODE_LINTERP
:
6417 case SHADER_OPCODE_GET_BUFFER_SIZE
:
6418 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
6419 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
6420 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6421 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6422 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
6423 return MIN2(16, inst
->exec_size
);
6425 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
6426 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
6427 * message used to implement varying pull constant loads, so expand it
6428 * to SIMD16. An alternative with longer message payload length but
6429 * shorter return payload would be to use the SIMD8 sampler message that
6430 * takes (header, u, v, r) as parameters instead of (header, u).
6432 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
6434 case FS_OPCODE_DDX_COARSE
:
6435 case FS_OPCODE_DDX_FINE
:
6436 case FS_OPCODE_DDY_COARSE
:
6437 case FS_OPCODE_DDY_FINE
:
6438 /* The implementation of this virtual opcode may require emitting
6439 * compressed Align16 instructions, which are severely limited on some
6442 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
6443 * Region Restrictions):
6445 * "In Align16 access mode, SIMD16 is not allowed for DW operations
6446 * and SIMD8 is not allowed for DF operations."
6448 * In this context, "DW operations" means "operations acting on 32-bit
6449 * values", so it includes operations on floats.
6451 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
6452 * (Instruction Compression -> Rules and Restrictions):
6454 * "A compressed instruction must be in Align1 access mode. Align16
6455 * mode instructions cannot be compressed."
6457 * Similar text exists in the g45 PRM.
6459 * Empirically, compressed align16 instructions using odd register
6460 * numbers don't appear to work on Sandybridge either.
6462 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
6463 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
6464 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
6466 case SHADER_OPCODE_MULH
:
6467 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
6468 * is 8-wide on Gen7+.
6470 return (devinfo
->gen
>= 7 ? 8 :
6471 get_fpu_lowered_simd_width(devinfo
, inst
));
6473 case FS_OPCODE_FB_WRITE_LOGICAL
:
6474 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
6477 assert(devinfo
->gen
!= 6 ||
6478 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
6479 inst
->exec_size
== 8);
6480 /* Dual-source FB writes are unsupported in SIMD16 mode. */
6481 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
6482 8 : MIN2(16, inst
->exec_size
));
6484 case FS_OPCODE_FB_READ_LOGICAL
:
6485 return MIN2(16, inst
->exec_size
);
6487 case SHADER_OPCODE_TEX_LOGICAL
:
6488 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
6489 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
6490 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
6491 case SHADER_OPCODE_LOD_LOGICAL
:
6492 case SHADER_OPCODE_TG4_LOGICAL
:
6493 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
6494 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
6495 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
6496 return get_sampler_lowered_simd_width(devinfo
, inst
);
6498 case SHADER_OPCODE_TXD_LOGICAL
:
6499 /* TXD is unsupported in SIMD16 mode. */
6502 case SHADER_OPCODE_TXL_LOGICAL
:
6503 case FS_OPCODE_TXB_LOGICAL
:
6504 /* Only one execution size is representable pre-ILK depending on whether
6505 * the shadow reference argument is present.
6507 if (devinfo
->gen
== 4)
6508 return inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
].file
== BAD_FILE
? 16 : 8;
6510 return get_sampler_lowered_simd_width(devinfo
, inst
);
6512 case SHADER_OPCODE_TXF_LOGICAL
:
6513 case SHADER_OPCODE_TXS_LOGICAL
:
6514 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
6515 * messages. Use SIMD16 instead.
6517 if (devinfo
->gen
== 4)
6520 return get_sampler_lowered_simd_width(devinfo
, inst
);
6522 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
6523 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
6524 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
6527 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
6528 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6529 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
6530 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
6531 case SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
:
6532 case SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
:
6533 case SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
:
6534 case SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
:
6535 return MIN2(16, inst
->exec_size
);
6537 case SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
:
6538 case SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
:
6539 case SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
:
6540 case SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
:
6541 return devinfo
->gen
<= 8 ? 8 : MIN2(16, inst
->exec_size
);
6543 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
:
6544 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
:
6545 case SHADER_OPCODE_A64_UNTYPED_ATOMIC_FLOAT_LOGICAL
:
6548 case SHADER_OPCODE_URB_READ_SIMD8
:
6549 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
6550 case SHADER_OPCODE_URB_WRITE_SIMD8
:
6551 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
6552 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
6553 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
6554 return MIN2(8, inst
->exec_size
);
6556 case SHADER_OPCODE_QUAD_SWIZZLE
: {
6557 const unsigned swiz
= inst
->src
[1].ud
;
6558 return (is_uniform(inst
->src
[0]) ?
6559 get_fpu_lowered_simd_width(devinfo
, inst
) :
6560 devinfo
->gen
< 11 && type_sz(inst
->src
[0].type
) == 4 ? 8 :
6561 swiz
== BRW_SWIZZLE_XYXY
|| swiz
== BRW_SWIZZLE_ZWZW
? 4 :
6562 get_fpu_lowered_simd_width(devinfo
, inst
));
6564 case SHADER_OPCODE_MOV_INDIRECT
: {
6565 /* From IVB and HSW PRMs:
6567 * "2.When the destination requires two registers and the sources are
6568 * indirect, the sources must use 1x1 regioning mode.
6570 * In case of DF instructions in HSW/IVB, the exec_size is limited by
6571 * the EU decompression logic not handling VxH indirect addressing
6574 const unsigned max_size
= (devinfo
->gen
>= 8 ? 2 : 1) * REG_SIZE
;
6575 /* Prior to Broadwell, we only have 8 address subregisters. */
6576 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
6577 max_size
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
6581 case SHADER_OPCODE_LOAD_PAYLOAD
: {
6582 const unsigned reg_count
=
6583 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
6585 if (reg_count
> 2) {
6586 /* Only LOAD_PAYLOAD instructions with per-channel destination region
6587 * can be easily lowered (which excludes headers and heterogeneous
6590 assert(!inst
->header_size
);
6591 for (unsigned i
= 0; i
< inst
->sources
; i
++)
6592 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
6593 inst
->src
[i
].file
== BAD_FILE
);
6595 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
6597 return inst
->exec_size
;
6601 return inst
->exec_size
;
6606 * Return true if splitting out the group of channels of instruction \p inst
6607 * given by lbld.group() requires allocating a temporary for the i-th source
6608 * of the lowered instruction.
6611 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
6613 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
6614 (inst
->components_read(i
) == 1 &&
6615 lbld
.dispatch_width() <= inst
->exec_size
)) ||
6616 (inst
->flags_written() &
6617 flag_mask(inst
->src
[i
], type_sz(inst
->src
[i
].type
)));
6621 * Extract the data that would be consumed by the channel group given by
6622 * lbld.group() from the i-th source region of instruction \p inst and return
6623 * it as result in packed form.
6626 emit_unzip(const fs_builder
&lbld
, fs_inst
*inst
, unsigned i
)
6628 assert(lbld
.group() >= inst
->group
);
6630 /* Specified channel group from the source region. */
6631 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group() - inst
->group
);
6633 if (needs_src_copy(lbld
, inst
, i
)) {
6634 /* Builder of the right width to perform the copy avoiding uninitialized
6635 * data if the lowered execution size is greater than the original
6636 * execution size of the instruction.
6638 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
6639 inst
->exec_size
), 0);
6640 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
6642 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
6643 cbld
.MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
6647 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
6648 /* The source is invariant for all dispatch_width-wide groups of the
6651 return inst
->src
[i
];
6654 /* We can just point the lowered instruction at the right channel group
6655 * from the original region.
6662 * Return true if splitting out the group of channels of instruction \p inst
6663 * given by lbld.group() requires allocating a temporary for the destination
6664 * of the lowered instruction and copying the data back to the original
6665 * destination region.
6668 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
6670 /* If the instruction writes more than one component we'll have to shuffle
6671 * the results of multiple lowered instructions in order to make sure that
6672 * they end up arranged correctly in the original destination region.
6674 if (inst
->size_written
> inst
->dst
.component_size(inst
->exec_size
))
6677 /* If the lowered execution size is larger than the original the result of
6678 * the instruction won't fit in the original destination, so we'll have to
6679 * allocate a temporary in any case.
6681 if (lbld
.dispatch_width() > inst
->exec_size
)
6684 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
6685 /* If we already made a copy of the source for other reasons there won't
6686 * be any overlap with the destination.
6688 if (needs_src_copy(lbld
, inst
, i
))
6691 /* In order to keep the logic simple we emit a copy whenever the
6692 * destination region doesn't exactly match an overlapping source, which
6693 * may point at the source and destination not being aligned group by
6694 * group which could cause one of the lowered instructions to overwrite
6695 * the data read from the same source by other lowered instructions.
6697 if (regions_overlap(inst
->dst
, inst
->size_written
,
6698 inst
->src
[i
], inst
->size_read(i
)) &&
6699 !inst
->dst
.equals(inst
->src
[i
]))
6707 * Insert data from a packed temporary into the channel group given by
6708 * lbld.group() of the destination region of instruction \p inst and return
6709 * the temporary as result. Any copy instructions that are required for
6710 * unzipping the previous value (in the case of partial writes) will be
6711 * inserted using \p lbld_before and any copy instructions required for
6712 * zipping up the destination of \p inst will be inserted using \p lbld_after.
6715 emit_zip(const fs_builder
&lbld_before
, const fs_builder
&lbld_after
,
6718 assert(lbld_before
.dispatch_width() == lbld_after
.dispatch_width());
6719 assert(lbld_before
.group() == lbld_after
.group());
6720 assert(lbld_after
.group() >= inst
->group
);
6722 /* Specified channel group from the destination region. */
6723 const fs_reg dst
= horiz_offset(inst
->dst
, lbld_after
.group() - inst
->group
);
6724 const unsigned dst_size
= inst
->size_written
/
6725 inst
->dst
.component_size(inst
->exec_size
);
6727 if (needs_dst_copy(lbld_after
, inst
)) {
6728 const fs_reg tmp
= lbld_after
.vgrf(inst
->dst
.type
, dst_size
);
6730 if (inst
->predicate
) {
6731 /* Handle predication by copying the original contents of
6732 * the destination into the temporary before emitting the
6733 * lowered instruction.
6735 const fs_builder gbld_before
=
6736 lbld_before
.group(MIN2(lbld_before
.dispatch_width(),
6737 inst
->exec_size
), 0);
6738 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6739 gbld_before
.MOV(offset(tmp
, lbld_before
, k
),
6740 offset(dst
, inst
->exec_size
, k
));
6744 const fs_builder gbld_after
=
6745 lbld_after
.group(MIN2(lbld_after
.dispatch_width(),
6746 inst
->exec_size
), 0);
6747 for (unsigned k
= 0; k
< dst_size
; ++k
) {
6748 /* Use a builder of the right width to perform the copy avoiding
6749 * uninitialized data if the lowered execution size is greater than
6750 * the original execution size of the instruction.
6752 gbld_after
.MOV(offset(dst
, inst
->exec_size
, k
),
6753 offset(tmp
, lbld_after
, k
));
6759 /* No need to allocate a temporary for the lowered instruction, just
6760 * take the right group of channels from the original region.
6767 fs_visitor::lower_simd_width()
6769 bool progress
= false;
6771 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6772 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
6774 if (lower_width
!= inst
->exec_size
) {
6775 /* Builder matching the original instruction. We may also need to
6776 * emit an instruction of width larger than the original, set the
6777 * execution size of the builder to the highest of both for now so
6778 * we're sure that both cases can be handled.
6780 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
6781 const fs_builder ibld
= bld
.at(block
, inst
)
6782 .exec_all(inst
->force_writemask_all
)
6783 .group(max_width
, inst
->group
/ max_width
);
6785 /* Split the copies in chunks of the execution width of either the
6786 * original or the lowered instruction, whichever is lower.
6788 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
6789 const unsigned dst_size
= inst
->size_written
/
6790 inst
->dst
.component_size(inst
->exec_size
);
6792 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
6794 /* Inserting the zip, unzip, and duplicated instructions in all of
6795 * the right spots is somewhat tricky. All of the unzip and any
6796 * instructions from the zip which unzip the destination prior to
6797 * writing need to happen before all of the per-group instructions
6798 * and the zip instructions need to happen after. In order to sort
6799 * this all out, we insert the unzip instructions before \p inst,
6800 * insert the per-group instructions after \p inst (i.e. before
6801 * inst->next), and insert the zip instructions before the
6802 * instruction after \p inst. Since we are inserting instructions
6803 * after \p inst, inst->next is a moving target and we need to save
6804 * it off here so that we insert the zip instructions in the right
6807 * Since we're inserting split instructions after after_inst, the
6808 * instructions will end up in the reverse order that we insert them.
6809 * However, certain render target writes require that the low group
6810 * instructions come before the high group. From the Ivy Bridge PRM
6811 * Vol. 4, Pt. 1, Section 3.9.11:
6813 * "If multiple SIMD8 Dual Source messages are delivered by the
6814 * pixel shader thread, each SIMD8_DUALSRC_LO message must be
6815 * issued before the SIMD8_DUALSRC_HI message with the same Slot
6816 * Group Select setting."
6818 * And, from Section 3.9.11.1 of the same PRM:
6820 * "When SIMD32 or SIMD16 PS threads send render target writes
6821 * with multiple SIMD8 and SIMD16 messages, the following must
6824 * All the slots (as described above) must have a corresponding
6825 * render target write irrespective of the slot's validity. A slot
6826 * is considered valid when at least one sample is enabled. For
6827 * example, a SIMD16 PS thread must send two SIMD8 render target
6828 * writes to cover all the slots.
6830 * PS thread must send SIMD render target write messages with
6831 * increasing slot numbers. For example, SIMD16 thread has
6832 * Slot[15:0] and if two SIMD8 render target writes are used, the
6833 * first SIMD8 render target write must send Slot[7:0] and the
6834 * next one must send Slot[15:8]."
6836 * In order to make low group instructions come before high group
6837 * instructions (this is required for some render target writes), we
6838 * split from the highest group to lowest.
6840 exec_node
*const after_inst
= inst
->next
;
6841 for (int i
= n
- 1; i
>= 0; i
--) {
6842 /* Emit a copy of the original instruction with the lowered width.
6843 * If the EOT flag was set throw it away except for the last
6844 * instruction to avoid killing the thread prematurely.
6846 fs_inst split_inst
= *inst
;
6847 split_inst
.exec_size
= lower_width
;
6848 split_inst
.eot
= inst
->eot
&& i
== int(n
- 1);
6850 /* Select the correct channel enables for the i-th group, then
6851 * transform the sources and destination and emit the lowered
6854 const fs_builder lbld
= ibld
.group(lower_width
, i
);
6856 for (unsigned j
= 0; j
< inst
->sources
; j
++)
6857 split_inst
.src
[j
] = emit_unzip(lbld
.at(block
, inst
), inst
, j
);
6859 split_inst
.dst
= emit_zip(lbld
.at(block
, inst
),
6860 lbld
.at(block
, after_inst
), inst
);
6861 split_inst
.size_written
=
6862 split_inst
.dst
.component_size(lower_width
) * dst_size
;
6864 lbld
.at(block
, inst
->next
).emit(split_inst
);
6867 inst
->remove(block
);
6873 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
6879 * Transform barycentric vectors into the interleaved form expected by the PLN
6880 * instruction and returned by the Gen7+ PI shared function.
6882 * For channels 0-15 in SIMD16 mode they are expected to be laid out as
6883 * follows in the register file:
6890 * There is no need to handle SIMD32 here -- This is expected to be run after
6891 * SIMD lowering, since SIMD lowering relies on vectors having the standard
6895 fs_visitor::lower_barycentrics()
6897 const bool has_interleaved_layout
= devinfo
->has_pln
|| devinfo
->gen
>= 7;
6898 bool progress
= false;
6900 if (stage
!= MESA_SHADER_FRAGMENT
|| !has_interleaved_layout
)
6903 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
6904 if (inst
->exec_size
< 16)
6907 const fs_builder
ibld(this, block
, inst
);
6908 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
6910 switch (inst
->opcode
) {
6911 case FS_OPCODE_LINTERP
: {
6912 assert(inst
->exec_size
== 16);
6913 const fs_reg tmp
= ibld
.vgrf(inst
->src
[0].type
, 2);
6916 for (unsigned i
= 0; i
< ARRAY_SIZE(srcs
); i
++)
6917 srcs
[i
] = horiz_offset(offset(inst
->src
[0], ibld
, i
% 2),
6920 ubld
.LOAD_PAYLOAD(tmp
, srcs
, ARRAY_SIZE(srcs
), ARRAY_SIZE(srcs
));
6926 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
6927 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
6928 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
: {
6929 assert(inst
->exec_size
== 16);
6930 const fs_reg tmp
= ibld
.vgrf(inst
->dst
.type
, 2);
6932 for (unsigned i
= 0; i
< 2; i
++) {
6933 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
6934 fs_inst
*mov
= ibld
.at(block
, inst
->next
).group(8, g
)
6935 .MOV(horiz_offset(offset(inst
->dst
, ibld
, i
),
6937 offset(tmp
, ubld
, 2 * g
+ i
));
6938 mov
->predicate
= inst
->predicate
;
6939 mov
->predicate_inverse
= inst
->predicate_inverse
;
6940 mov
->flag_subreg
= inst
->flag_subreg
;
6954 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
6960 fs_visitor::dump_instructions() const
6962 dump_instructions(NULL
);
6966 fs_visitor::dump_instructions(const char *name
) const
6968 FILE *file
= stderr
;
6969 if (name
&& geteuid() != 0) {
6970 file
= fopen(name
, "w");
6976 const register_pressure
&rp
= regpressure_analysis
.require();
6977 unsigned ip
= 0, max_pressure
= 0;
6978 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
6979 max_pressure
= MAX2(max_pressure
, rp
.regs_live_at_ip
[ip
]);
6980 fprintf(file
, "{%3d} %4d: ", rp
.regs_live_at_ip
[ip
], ip
);
6981 dump_instruction(inst
, file
);
6984 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
6987 foreach_in_list(backend_instruction
, inst
, &instructions
) {
6988 fprintf(file
, "%4d: ", ip
++);
6989 dump_instruction(inst
, file
);
6993 if (file
!= stderr
) {
6999 fs_visitor::dump_instruction(const backend_instruction
*be_inst
) const
7001 dump_instruction(be_inst
, stderr
);
7005 fs_visitor::dump_instruction(const backend_instruction
*be_inst
, FILE *file
) const
7007 const fs_inst
*inst
= (const fs_inst
*)be_inst
;
7009 if (inst
->predicate
) {
7010 fprintf(file
, "(%cf%d.%d) ",
7011 inst
->predicate_inverse
? '-' : '+',
7012 inst
->flag_subreg
/ 2,
7013 inst
->flag_subreg
% 2);
7016 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
7018 fprintf(file
, ".sat");
7019 if (inst
->conditional_mod
) {
7020 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
7021 if (!inst
->predicate
&&
7022 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
7023 inst
->opcode
!= BRW_OPCODE_CSEL
&&
7024 inst
->opcode
!= BRW_OPCODE_IF
&&
7025 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
7026 fprintf(file
, ".f%d.%d", inst
->flag_subreg
/ 2,
7027 inst
->flag_subreg
% 2);
7030 fprintf(file
, "(%d) ", inst
->exec_size
);
7033 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
7036 if (inst
->ex_mlen
) {
7037 fprintf(file
, "(ex_mlen: %d) ", inst
->ex_mlen
);
7041 fprintf(file
, "(EOT) ");
7044 switch (inst
->dst
.file
) {
7046 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
7049 fprintf(file
, "g%d", inst
->dst
.nr
);
7052 fprintf(file
, "m%d", inst
->dst
.nr
);
7055 fprintf(file
, "(null)");
7058 fprintf(file
, "***u%d***", inst
->dst
.nr
);
7061 fprintf(file
, "***attr%d***", inst
->dst
.nr
);
7064 switch (inst
->dst
.nr
) {
7066 fprintf(file
, "null");
7068 case BRW_ARF_ADDRESS
:
7069 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
7071 case BRW_ARF_ACCUMULATOR
:
7072 fprintf(file
, "acc%d", inst
->dst
.subnr
);
7075 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7078 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
7083 unreachable("not reached");
7086 if (inst
->dst
.offset
||
7087 (inst
->dst
.file
== VGRF
&&
7088 alloc
.sizes
[inst
->dst
.nr
] * REG_SIZE
!= inst
->size_written
)) {
7089 const unsigned reg_size
= (inst
->dst
.file
== UNIFORM
? 4 : REG_SIZE
);
7090 fprintf(file
, "+%d.%d", inst
->dst
.offset
/ reg_size
,
7091 inst
->dst
.offset
% reg_size
);
7094 if (inst
->dst
.stride
!= 1)
7095 fprintf(file
, "<%u>", inst
->dst
.stride
);
7096 fprintf(file
, ":%s, ", brw_reg_type_to_letters(inst
->dst
.type
));
7098 for (int i
= 0; i
< inst
->sources
; i
++) {
7099 if (inst
->src
[i
].negate
)
7101 if (inst
->src
[i
].abs
)
7103 switch (inst
->src
[i
].file
) {
7105 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
7108 fprintf(file
, "g%d", inst
->src
[i
].nr
);
7111 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
7114 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
7117 fprintf(file
, "u%d", inst
->src
[i
].nr
);
7120 fprintf(file
, "(null)");
7123 switch (inst
->src
[i
].type
) {
7124 case BRW_REGISTER_TYPE_F
:
7125 fprintf(file
, "%-gf", inst
->src
[i
].f
);
7127 case BRW_REGISTER_TYPE_DF
:
7128 fprintf(file
, "%fdf", inst
->src
[i
].df
);
7130 case BRW_REGISTER_TYPE_W
:
7131 case BRW_REGISTER_TYPE_D
:
7132 fprintf(file
, "%dd", inst
->src
[i
].d
);
7134 case BRW_REGISTER_TYPE_UW
:
7135 case BRW_REGISTER_TYPE_UD
:
7136 fprintf(file
, "%uu", inst
->src
[i
].ud
);
7138 case BRW_REGISTER_TYPE_Q
:
7139 fprintf(file
, "%" PRId64
"q", inst
->src
[i
].d64
);
7141 case BRW_REGISTER_TYPE_UQ
:
7142 fprintf(file
, "%" PRIu64
"uq", inst
->src
[i
].u64
);
7144 case BRW_REGISTER_TYPE_VF
:
7145 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
7146 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
7147 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
7148 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
7149 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
7151 case BRW_REGISTER_TYPE_V
:
7152 case BRW_REGISTER_TYPE_UV
:
7153 fprintf(file
, "%08x%s", inst
->src
[i
].ud
,
7154 inst
->src
[i
].type
== BRW_REGISTER_TYPE_V
? "V" : "UV");
7157 fprintf(file
, "???");
7162 switch (inst
->src
[i
].nr
) {
7164 fprintf(file
, "null");
7166 case BRW_ARF_ADDRESS
:
7167 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
7169 case BRW_ARF_ACCUMULATOR
:
7170 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
7173 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7176 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
7182 if (inst
->src
[i
].offset
||
7183 (inst
->src
[i
].file
== VGRF
&&
7184 alloc
.sizes
[inst
->src
[i
].nr
] * REG_SIZE
!= inst
->size_read(i
))) {
7185 const unsigned reg_size
= (inst
->src
[i
].file
== UNIFORM
? 4 : REG_SIZE
);
7186 fprintf(file
, "+%d.%d", inst
->src
[i
].offset
/ reg_size
,
7187 inst
->src
[i
].offset
% reg_size
);
7190 if (inst
->src
[i
].abs
)
7193 if (inst
->src
[i
].file
!= IMM
) {
7195 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
7196 unsigned hstride
= inst
->src
[i
].hstride
;
7197 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
7199 stride
= inst
->src
[i
].stride
;
7202 fprintf(file
, "<%u>", stride
);
7204 fprintf(file
, ":%s", brw_reg_type_to_letters(inst
->src
[i
].type
));
7207 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
7208 fprintf(file
, ", ");
7213 if (inst
->force_writemask_all
)
7214 fprintf(file
, "NoMask ");
7216 if (inst
->exec_size
!= dispatch_width
)
7217 fprintf(file
, "group%d ", inst
->group
);
7219 fprintf(file
, "\n");
7223 fs_visitor::setup_fs_payload_gen6()
7225 assert(stage
== MESA_SHADER_FRAGMENT
);
7226 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
7227 const unsigned payload_width
= MIN2(16, dispatch_width
);
7228 assert(dispatch_width
% payload_width
== 0);
7229 assert(devinfo
->gen
>= 6);
7231 prog_data
->uses_src_depth
= prog_data
->uses_src_w
=
7232 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) != 0;
7234 prog_data
->uses_sample_mask
=
7235 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
7237 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
7239 * "MSDISPMODE_PERSAMPLE is required in order to select
7242 * So we can only really get sample positions if we are doing real
7243 * per-sample dispatch. If we need gl_SamplePosition and we don't have
7244 * persample dispatch, we hard-code it to 0.5.
7246 prog_data
->uses_pos_offset
= prog_data
->persample_dispatch
&&
7247 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
);
7249 /* R0: PS thread payload header. */
7252 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7253 /* R1: masks, pixel X/Y coordinates. */
7254 payload
.subspan_coord_reg
[j
] = payload
.num_regs
++;
7257 for (unsigned j
= 0; j
< dispatch_width
/ payload_width
; j
++) {
7258 /* R3-26: barycentric interpolation coordinates. These appear in the
7259 * same order that they appear in the brw_barycentric_mode enum. Each
7260 * set of coordinates occupies 2 registers if dispatch width == 8 and 4
7261 * registers if dispatch width == 16. Coordinates only appear if they
7262 * were enabled using the "Barycentric Interpolation Mode" bits in
7265 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
7266 if (prog_data
->barycentric_interp_modes
& (1 << i
)) {
7267 payload
.barycentric_coord_reg
[i
][j
] = payload
.num_regs
;
7268 payload
.num_regs
+= payload_width
/ 4;
7272 /* R27-28: interpolated depth if uses source depth */
7273 if (prog_data
->uses_src_depth
) {
7274 payload
.source_depth_reg
[j
] = payload
.num_regs
;
7275 payload
.num_regs
+= payload_width
/ 8;
7278 /* R29-30: interpolated W set if GEN6_WM_USES_SOURCE_W. */
7279 if (prog_data
->uses_src_w
) {
7280 payload
.source_w_reg
[j
] = payload
.num_regs
;
7281 payload
.num_regs
+= payload_width
/ 8;
7284 /* R31: MSAA position offsets. */
7285 if (prog_data
->uses_pos_offset
) {
7286 payload
.sample_pos_reg
[j
] = payload
.num_regs
;
7290 /* R32-33: MSAA input coverage mask */
7291 if (prog_data
->uses_sample_mask
) {
7292 assert(devinfo
->gen
>= 7);
7293 payload
.sample_mask_in_reg
[j
] = payload
.num_regs
;
7294 payload
.num_regs
+= payload_width
/ 8;
7298 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
7299 source_depth_to_render_target
= true;
7304 fs_visitor::setup_vs_payload()
7306 /* R0: thread header, R1: urb handles */
7307 payload
.num_regs
= 2;
7311 fs_visitor::setup_gs_payload()
7313 assert(stage
== MESA_SHADER_GEOMETRY
);
7315 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
7316 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7318 /* R0: thread header, R1: output URB handles */
7319 payload
.num_regs
= 2;
7321 if (gs_prog_data
->include_primitive_id
) {
7322 /* R2: Primitive ID 0..7 */
7326 /* Always enable VUE handles so we can safely use pull model if needed.
7328 * The push model for a GS uses a ton of register space even for trivial
7329 * scenarios with just a few inputs, so just make things easier and a bit
7330 * safer by always having pull model available.
7332 gs_prog_data
->base
.include_vue_handles
= true;
7334 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
7335 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
7337 /* Use a maximum of 24 registers for push-model inputs. */
7338 const unsigned max_push_components
= 24;
7340 /* If pushing our inputs would take too many registers, reduce the URB read
7341 * length (which is in HWords, or 8 registers), and resort to pulling.
7343 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
7344 * have to multiply by VerticesIn to obtain the total storage requirement.
7346 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
7347 max_push_components
) {
7348 vue_prog_data
->urb_read_length
=
7349 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
7354 fs_visitor::setup_cs_payload()
7356 assert(devinfo
->gen
>= 7);
7357 payload
.num_regs
= 1;
7360 brw::register_pressure::register_pressure(const fs_visitor
*v
)
7362 const fs_live_variables
&live
= v
->live_analysis
.require();
7363 const unsigned num_instructions
= v
->cfg
->num_blocks
?
7364 v
->cfg
->blocks
[v
->cfg
->num_blocks
- 1]->end_ip
+ 1 : 0;
7366 regs_live_at_ip
= new unsigned[num_instructions
]();
7368 for (unsigned reg
= 0; reg
< v
->alloc
.count
; reg
++) {
7369 for (int ip
= live
.vgrf_start
[reg
]; ip
<= live
.vgrf_end
[reg
]; ip
++)
7370 regs_live_at_ip
[ip
] += v
->alloc
.sizes
[reg
];
7374 brw::register_pressure::~register_pressure()
7376 delete[] regs_live_at_ip
;
7380 fs_visitor::invalidate_analysis(brw::analysis_dependency_class c
)
7382 backend_shader::invalidate_analysis(c
);
7383 live_analysis
.invalidate(c
);
7384 regpressure_analysis
.invalidate(c
);
7388 fs_visitor::optimize()
7390 /* Start by validating the shader we currently have. */
7393 /* bld is the common builder object pointing at the end of the program we
7394 * used to translate it into i965 IR. For the optimization and lowering
7395 * passes coming next, any code added after the end of the program without
7396 * having explicitly called fs_builder::at() clearly points at a mistake.
7397 * Ideally optimization passes wouldn't be part of the visitor so they
7398 * wouldn't have access to bld at all, but they do, so just in case some
7399 * pass forgets to ask for a location explicitly set it to NULL here to
7400 * make it trip. The dispatch width is initialized to a bogus value to
7401 * make sure that optimizations set the execution controls explicitly to
7402 * match the code they are manipulating instead of relying on the defaults.
7404 bld
= fs_builder(this, 64);
7406 assign_constant_locations();
7407 lower_constant_loads();
7411 split_virtual_grfs();
7414 #define OPT(pass, args...) ({ \
7416 bool this_progress = pass(args); \
7418 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
7419 char filename[64]; \
7420 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
7421 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
7423 backend_shader::dump_instructions(filename); \
7428 progress = progress || this_progress; \
7432 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
7434 snprintf(filename
, 64, "%s%d-%s-00-00-start",
7435 stage_abbrev
, dispatch_width
, nir
->info
.name
);
7437 backend_shader::dump_instructions(filename
);
7440 bool progress
= false;
7444 /* Before anything else, eliminate dead code. The results of some NIR
7445 * instructions may effectively be calculated twice. Once when the
7446 * instruction is encountered, and again when the user of that result is
7447 * encountered. Wipe those away before algebraic optimizations and
7448 * especially copy propagation can mix things up.
7450 OPT(dead_code_eliminate
);
7452 OPT(remove_extra_rounding_modes
);
7459 OPT(remove_duplicate_mrf_writes
);
7463 OPT(opt_copy_propagation
);
7464 OPT(opt_predicated_break
, this);
7465 OPT(opt_cmod_propagation
);
7466 OPT(dead_code_eliminate
);
7467 OPT(opt_peephole_sel
);
7468 OPT(dead_control_flow_eliminate
, this);
7469 OPT(opt_register_renaming
);
7470 OPT(opt_saturate_propagation
);
7471 OPT(register_coalesce
);
7472 OPT(compute_to_mrf
);
7473 OPT(eliminate_find_live_channel
);
7475 OPT(compact_virtual_grfs
);
7481 if (OPT(lower_pack
)) {
7482 OPT(register_coalesce
);
7483 OPT(dead_code_eliminate
);
7486 OPT(lower_simd_width
);
7487 OPT(lower_barycentrics
);
7488 OPT(lower_logical_sends
);
7490 /* After logical SEND lowering. */
7491 OPT(fixup_nomask_control_flow
);
7494 OPT(opt_copy_propagation
);
7495 /* Only run after logical send lowering because it's easier to implement
7496 * in terms of physical sends.
7498 if (OPT(opt_zero_samples
))
7499 OPT(opt_copy_propagation
);
7500 /* Run after logical send lowering to give it a chance to CSE the
7501 * LOAD_PAYLOAD instructions created to construct the payloads of
7502 * e.g. texturing messages in cases where it wasn't possible to CSE the
7503 * whole logical instruction.
7506 OPT(register_coalesce
);
7507 OPT(compute_to_mrf
);
7508 OPT(dead_code_eliminate
);
7509 OPT(remove_duplicate_mrf_writes
);
7510 OPT(opt_peephole_sel
);
7513 OPT(opt_redundant_discard_jumps
);
7515 if (OPT(lower_load_payload
)) {
7516 split_virtual_grfs();
7518 /* Lower 64 bit MOVs generated by payload lowering. */
7519 if (!devinfo
->has_64bit_float
&& !devinfo
->has_64bit_int
)
7522 OPT(register_coalesce
);
7523 OPT(lower_simd_width
);
7524 OPT(compute_to_mrf
);
7525 OPT(dead_code_eliminate
);
7528 OPT(opt_combine_constants
);
7529 OPT(lower_integer_multiplication
);
7532 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
7533 OPT(opt_cmod_propagation
);
7535 OPT(opt_copy_propagation
);
7536 OPT(dead_code_eliminate
);
7539 if (OPT(lower_regioning
)) {
7540 OPT(opt_copy_propagation
);
7541 OPT(dead_code_eliminate
);
7542 OPT(lower_simd_width
);
7545 OPT(fixup_sends_duplicate_payload
);
7547 lower_uniform_pull_constant_loads();
7553 * From the Skylake PRM Vol. 2a docs for sends:
7555 * "It is required that the second block of GRFs does not overlap with the
7558 * There are plenty of cases where we may accidentally violate this due to
7559 * having, for instance, both sources be the constant 0. This little pass
7560 * just adds a new vgrf for the second payload and copies it over.
7563 fs_visitor::fixup_sends_duplicate_payload()
7565 bool progress
= false;
7567 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7568 if (inst
->opcode
== SHADER_OPCODE_SEND
&& inst
->ex_mlen
> 0 &&
7569 regions_overlap(inst
->src
[2], inst
->mlen
* REG_SIZE
,
7570 inst
->src
[3], inst
->ex_mlen
* REG_SIZE
)) {
7571 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(inst
->ex_mlen
),
7572 BRW_REGISTER_TYPE_UD
);
7573 /* Sadly, we've lost all notion of channels and bit sizes at this
7574 * point. Just WE_all it.
7576 const fs_builder ibld
= bld
.at(block
, inst
).exec_all().group(16, 0);
7577 fs_reg copy_src
= retype(inst
->src
[3], BRW_REGISTER_TYPE_UD
);
7578 fs_reg copy_dst
= tmp
;
7579 for (unsigned i
= 0; i
< inst
->ex_mlen
; i
+= 2) {
7580 if (inst
->ex_mlen
== i
+ 1) {
7581 /* Only one register left; do SIMD8 */
7582 ibld
.group(8, 0).MOV(copy_dst
, copy_src
);
7584 ibld
.MOV(copy_dst
, copy_src
);
7586 copy_src
= offset(copy_src
, ibld
, 1);
7587 copy_dst
= offset(copy_dst
, ibld
, 1);
7595 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
7601 * Three source instruction must have a GRF/MRF destination register.
7602 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
7605 fs_visitor::fixup_3src_null_dest()
7607 bool progress
= false;
7609 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
7610 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
7611 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
7618 invalidate_analysis(DEPENDENCY_INSTRUCTION_DETAIL
|
7619 DEPENDENCY_VARIABLES
);
7623 * Find the first instruction in the program that might start a region of
7624 * divergent control flow due to a HALT jump. There is no
7625 * find_halt_control_flow_region_end(), the region of divergence extends until
7626 * the only FS_OPCODE_PLACEHOLDER_HALT in the program.
7628 static const fs_inst
*
7629 find_halt_control_flow_region_start(const fs_visitor
*v
)
7631 if (brw_wm_prog_data(v
->prog_data
)->uses_kill
) {
7632 foreach_block_and_inst(block
, fs_inst
, inst
, v
->cfg
) {
7633 if (inst
->opcode
== FS_OPCODE_DISCARD_JUMP
||
7634 inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
)
7643 * Work around the Gen12 hardware bug filed as GEN:BUG:1407528679. EU fusion
7644 * can cause a BB to be executed with all channels disabled, which will lead
7645 * to the execution of any NoMask instructions in it, even though any
7646 * execution-masked instructions will be correctly shot down. This may break
7647 * assumptions of some NoMask SEND messages whose descriptor depends on data
7648 * generated by live invocations of the shader.
7650 * This avoids the problem by predicating certain instructions on an ANY
7651 * horizontal predicate that makes sure that their execution is omitted when
7652 * all channels of the program are disabled.
7655 fs_visitor::fixup_nomask_control_flow()
7657 if (devinfo
->gen
!= 12)
7660 const brw_predicate pred
= dispatch_width
> 16 ? BRW_PREDICATE_ALIGN1_ANY32H
:
7661 dispatch_width
> 8 ? BRW_PREDICATE_ALIGN1_ANY16H
:
7662 BRW_PREDICATE_ALIGN1_ANY8H
;
7663 const fs_inst
*halt_start
= find_halt_control_flow_region_start(this);
7665 bool progress
= false;
7667 const fs_live_variables
&live_vars
= live_analysis
.require();
7669 /* Scan the program backwards in order to be able to easily determine
7670 * whether the flag register is live at any point.
7672 foreach_block_reverse_safe(block
, cfg
) {
7673 BITSET_WORD flag_liveout
= live_vars
.block_data
[block
->num
]
7675 STATIC_ASSERT(ARRAY_SIZE(live_vars
.block_data
[0].flag_liveout
) == 1);
7677 foreach_inst_in_block_reverse_safe(fs_inst
, inst
, block
) {
7678 if (!inst
->predicate
&& inst
->exec_size
>= 8)
7679 flag_liveout
&= ~inst
->flags_written();
7681 switch (inst
->opcode
) {
7684 /* Note that this doesn't handle FS_OPCODE_DISCARD_JUMP since only
7685 * the first one in the program closes the region of divergent
7686 * control flow due to any HALT instructions -- Instead this is
7687 * handled with the halt_start check below.
7692 case BRW_OPCODE_WHILE
:
7693 case BRW_OPCODE_ENDIF
:
7694 case FS_OPCODE_PLACEHOLDER_HALT
:
7699 /* Note that the vast majority of NoMask SEND instructions in the
7700 * program are harmless while executed in a block with all
7701 * channels disabled, since any instructions with side effects we
7702 * could hit here should be execution-masked.
7704 * The main concern is NoMask SEND instructions where the message
7705 * descriptor or header depends on data generated by live
7706 * invocations of the shader (RESINFO and
7707 * FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD with a dynamically
7708 * computed surface index seem to be the only examples right now
7709 * where this could easily lead to GPU hangs). Unfortunately we
7710 * have no straightforward way to detect that currently, so just
7711 * predicate any NoMask SEND instructions we find under control
7714 * If this proves to have a measurable performance impact it can
7715 * be easily extended with a whitelist of messages we know we can
7716 * safely omit the predication for.
7718 if (depth
&& inst
->force_writemask_all
&&
7719 is_send(inst
) && !inst
->predicate
) {
7720 /* We need to load the execution mask into the flag register by
7721 * using a builder with channel group matching the whole shader
7722 * (rather than the default which is derived from the original
7723 * instruction), in order to avoid getting a right-shifted
7726 const fs_builder ubld
= fs_builder(this, block
, inst
)
7727 .exec_all().group(dispatch_width
, 0);
7728 const fs_reg flag
= retype(brw_flag_reg(0, 0),
7729 BRW_REGISTER_TYPE_UD
);
7731 /* Due to the lack of flag register allocation we need to save
7732 * and restore the flag register if it's live.
7734 const bool save_flag
= flag_liveout
&
7735 flag_mask(flag
, dispatch_width
/ 8);
7736 const fs_reg tmp
= ubld
.group(1, 0).vgrf(flag
.type
);
7739 ubld
.group(1, 0).MOV(tmp
, flag
);
7741 ubld
.emit(FS_OPCODE_LOAD_LIVE_CHANNELS
);
7743 set_predicate(pred
, inst
);
7744 inst
->flag_subreg
= 0;
7747 ubld
.group(1, 0).at(block
, inst
->next
).MOV(flag
, tmp
);
7754 if (inst
== halt_start
)
7757 flag_liveout
|= inst
->flags_read(devinfo
);
7762 invalidate_analysis(DEPENDENCY_INSTRUCTIONS
| DEPENDENCY_VARIABLES
);
7768 fs_visitor::allocate_registers(bool allow_spilling
)
7772 static const enum instruction_scheduler_mode pre_modes
[] = {
7774 SCHEDULE_PRE_NON_LIFO
,
7778 static const char *scheduler_mode_name
[] = {
7784 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
7786 /* Try each scheduling heuristic to see if it can successfully register
7787 * allocate without spilling. They should be ordered by decreasing
7788 * performance but increasing likelihood of allocating.
7790 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
7791 schedule_instructions(pre_modes
[i
]);
7792 this->shader_stats
.scheduler_mode
= scheduler_mode_name
[i
];
7795 assign_regs_trivial();
7800 /* Scheduling may create additional opportunities for CMOD propagation,
7801 * so let's do it again. If CMOD propagation made any progress,
7802 * elminate dead code one more time.
7804 bool progress
= false;
7805 const int iteration
= 99;
7808 if (OPT(opt_cmod_propagation
)) {
7809 /* dead_code_eliminate "undoes" the fixing done by
7810 * fixup_3src_null_dest, so we have to do it again if
7811 * dead_code_eliminiate makes any progress.
7813 if (OPT(dead_code_eliminate
))
7814 fixup_3src_null_dest();
7817 bool can_spill
= allow_spilling
&&
7818 (i
== ARRAY_SIZE(pre_modes
) - 1);
7820 /* We should only spill registers on the last scheduling. */
7821 assert(!spilled_any_registers
);
7823 allocated
= assign_regs(can_spill
, spill_all
);
7829 fail("Failure to register allocate. Reduce number of "
7830 "live scalar values to avoid this.");
7831 } else if (spilled_any_registers
) {
7832 compiler
->shader_perf_log(log_data
,
7833 "%s shader triggered register spilling. "
7834 "Try reducing the number of live scalar "
7835 "values to improve performance.\n",
7839 /* This must come after all optimization and register allocation, since
7840 * it inserts dead code that happens to have side effects, and it does
7841 * so based on the actual physical registers in use.
7843 insert_gen4_send_dependency_workarounds();
7848 opt_bank_conflicts();
7850 schedule_instructions(SCHEDULE_POST
);
7852 if (last_scratch
> 0) {
7853 ASSERTED
unsigned max_scratch_size
= 2 * 1024 * 1024;
7855 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
7857 if (stage
== MESA_SHADER_COMPUTE
) {
7858 if (devinfo
->is_haswell
) {
7859 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7860 * field documentation, Haswell supports a minimum of 2kB of
7861 * scratch space for compute shaders, unlike every other stage
7864 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
7865 } else if (devinfo
->gen
<= 7) {
7866 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
7867 * field documentation, platforms prior to Haswell measure scratch
7868 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
7870 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
7871 max_scratch_size
= 12 * 1024;
7875 /* We currently only support up to 2MB of scratch space. If we
7876 * need to support more eventually, the documentation suggests
7877 * that we could allocate a larger buffer, and partition it out
7878 * ourselves. We'd just have to undo the hardware's address
7879 * calculation by subtracting (FFTID * Per Thread Scratch Space)
7880 * and then add FFTID * (Larger Per Thread Scratch Space).
7882 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
7883 * Thread Group Tracking > Local Memory/Scratch Space.
7885 assert(prog_data
->total_scratch
< max_scratch_size
);
7892 fs_visitor::run_vs()
7894 assert(stage
== MESA_SHADER_VERTEX
);
7898 if (shader_time_index
>= 0)
7899 emit_shader_time_begin();
7908 if (shader_time_index
>= 0)
7909 emit_shader_time_end();
7915 assign_curb_setup();
7916 assign_vs_urb_setup();
7918 fixup_3src_null_dest();
7919 allocate_registers(true /* allow_spilling */);
7925 fs_visitor::set_tcs_invocation_id()
7927 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7928 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
7930 const unsigned instance_id_mask
=
7931 devinfo
->gen
>= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
7932 const unsigned instance_id_shift
=
7933 devinfo
->gen
>= 11 ? 16 : 17;
7935 /* Get instance number from g0.2 bits 22:16 or 23:17 */
7936 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7937 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
7938 brw_imm_ud(instance_id_mask
));
7940 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7942 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
) {
7943 /* gl_InvocationID is just the thread number */
7944 bld
.SHR(invocation_id
, t
, brw_imm_ud(instance_id_shift
));
7948 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
);
7950 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
7951 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7952 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
7953 bld
.MOV(channels_ud
, channels_uw
);
7955 if (tcs_prog_data
->instances
== 1) {
7956 invocation_id
= channels_ud
;
7958 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
7959 bld
.SHR(instance_times_8
, t
, brw_imm_ud(instance_id_shift
- 3));
7960 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
7965 fs_visitor::run_tcs()
7967 assert(stage
== MESA_SHADER_TESS_CTRL
);
7969 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
7970 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
7971 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
7973 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
||
7974 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7976 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
7977 /* r1-r4 contain the ICP handles. */
7978 payload
.num_regs
= 5;
7980 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
7981 assert(tcs_key
->input_vertices
> 0);
7982 /* r1 contains output handles, r2 may contain primitive ID, then the
7983 * ICP handles occupy the next 1-32 registers.
7985 payload
.num_regs
= 2 + tcs_prog_data
->include_primitive_id
+
7986 tcs_key
->input_vertices
;
7989 if (shader_time_index
>= 0)
7990 emit_shader_time_begin();
7992 /* Initialize gl_InvocationID */
7993 set_tcs_invocation_id();
7995 const bool fix_dispatch_mask
=
7996 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
&&
7997 (nir
->info
.tess
.tcs_vertices_out
% 8) != 0;
7999 /* Fix the disptach mask */
8000 if (fix_dispatch_mask
) {
8001 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
8002 brw_imm_ud(nir
->info
.tess
.tcs_vertices_out
), BRW_CONDITIONAL_L
);
8003 bld
.IF(BRW_PREDICATE_NORMAL
);
8008 if (fix_dispatch_mask
) {
8009 bld
.emit(BRW_OPCODE_ENDIF
);
8012 /* Emit EOT write; set TR DS Cache bit */
8014 fs_reg(get_tcs_output_urb_handle()),
8015 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
8016 fs_reg(brw_imm_ud(0)),
8018 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
8019 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
8021 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
8022 bld
.null_reg_ud(), payload
);
8026 if (shader_time_index
>= 0)
8027 emit_shader_time_end();
8036 assign_curb_setup();
8037 assign_tcs_urb_setup();
8039 fixup_3src_null_dest();
8040 allocate_registers(true /* allow_spilling */);
8046 fs_visitor::run_tes()
8048 assert(stage
== MESA_SHADER_TESS_EVAL
);
8050 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
8051 payload
.num_regs
= 5;
8053 if (shader_time_index
>= 0)
8054 emit_shader_time_begin();
8063 if (shader_time_index
>= 0)
8064 emit_shader_time_end();
8070 assign_curb_setup();
8071 assign_tes_urb_setup();
8073 fixup_3src_null_dest();
8074 allocate_registers(true /* allow_spilling */);
8080 fs_visitor::run_gs()
8082 assert(stage
== MESA_SHADER_GEOMETRY
);
8086 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
8088 if (gs_compile
->control_data_header_size_bits
> 0) {
8089 /* Create a VGRF to store accumulated control data bits. */
8090 this->control_data_bits
= vgrf(glsl_type::uint_type
);
8092 /* If we're outputting more than 32 control data bits, then EmitVertex()
8093 * will set control_data_bits to 0 after emitting the first vertex.
8094 * Otherwise, we need to initialize it to 0 here.
8096 if (gs_compile
->control_data_header_size_bits
<= 32) {
8097 const fs_builder abld
= bld
.annotate("initialize control data bits");
8098 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
8102 if (shader_time_index
>= 0)
8103 emit_shader_time_begin();
8107 emit_gs_thread_end();
8109 if (shader_time_index
>= 0)
8110 emit_shader_time_end();
8119 assign_curb_setup();
8120 assign_gs_urb_setup();
8122 fixup_3src_null_dest();
8123 allocate_registers(true /* allow_spilling */);
8128 /* From the SKL PRM, Volume 16, Workarounds:
8130 * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
8131 * only header phases (R0-R2)
8133 * WA: Enable a non-header phase (e.g. push constant) when dispatch would
8134 * have been header only.
8136 * Instead of enabling push constants one can alternatively enable one of the
8137 * inputs. Here one simply chooses "layer" which shouldn't impose much
8141 gen9_ps_header_only_workaround(struct brw_wm_prog_data
*wm_prog_data
)
8143 if (wm_prog_data
->num_varying_inputs
)
8146 if (wm_prog_data
->base
.curb_read_length
)
8149 wm_prog_data
->urb_setup
[VARYING_SLOT_LAYER
] = 0;
8150 wm_prog_data
->num_varying_inputs
= 1;
8152 brw_compute_urb_setup_index(wm_prog_data
);
8156 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
8158 struct brw_wm_prog_data
*wm_prog_data
= brw_wm_prog_data(this->prog_data
);
8159 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
8161 assert(stage
== MESA_SHADER_FRAGMENT
);
8163 if (devinfo
->gen
>= 6)
8164 setup_fs_payload_gen6();
8166 setup_fs_payload_gen4();
8170 } else if (do_rep_send
) {
8171 assert(dispatch_width
== 16);
8172 emit_repclear_shader();
8174 if (shader_time_index
>= 0)
8175 emit_shader_time_begin();
8177 if (nir
->info
.inputs_read
> 0 ||
8178 (nir
->info
.system_values_read
& (1ull << SYSTEM_VALUE_FRAG_COORD
)) ||
8179 (nir
->info
.outputs_read
> 0 && !wm_key
->coherent_fb_fetch
)) {
8180 if (devinfo
->gen
< 6)
8181 emit_interpolation_setup_gen4();
8183 emit_interpolation_setup_gen6();
8186 /* We handle discards by keeping track of the still-live pixels in f0.1.
8187 * Initialize it with the dispatched pixels.
8189 if (wm_prog_data
->uses_kill
) {
8190 const unsigned lower_width
= MIN2(dispatch_width
, 16);
8191 for (unsigned i
= 0; i
< dispatch_width
/ lower_width
; i
++) {
8192 const fs_reg dispatch_mask
=
8193 devinfo
->gen
>= 6 ? brw_vec1_grf((i
? 2 : 1), 7) :
8195 bld
.exec_all().group(1, 0)
8196 .MOV(sample_mask_reg(bld
.group(lower_width
, i
)),
8197 retype(dispatch_mask
, BRW_REGISTER_TYPE_UW
));
8201 if (nir
->info
.writes_memory
)
8202 wm_prog_data
->has_side_effects
= true;
8209 if (wm_prog_data
->uses_kill
)
8210 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
8212 if (wm_key
->alpha_test_func
)
8217 if (shader_time_index
>= 0)
8218 emit_shader_time_end();
8224 assign_curb_setup();
8226 if (devinfo
->gen
>= 9)
8227 gen9_ps_header_only_workaround(wm_prog_data
);
8231 fixup_3src_null_dest();
8233 allocate_registers(allow_spilling
);
8243 fs_visitor::run_cs(bool allow_spilling
)
8245 assert(stage
== MESA_SHADER_COMPUTE
);
8249 if (shader_time_index
>= 0)
8250 emit_shader_time_begin();
8252 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
8253 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
8254 const fs_builder abld
= bld
.exec_all().group(1, 0);
8255 abld
.MOV(retype(brw_sr0_reg(1), BRW_REGISTER_TYPE_UW
),
8256 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
8264 emit_cs_terminate();
8266 if (shader_time_index
>= 0)
8267 emit_shader_time_end();
8273 assign_curb_setup();
8275 fixup_3src_null_dest();
8276 allocate_registers(allow_spilling
);
8285 is_used_in_not_interp_frag_coord(nir_ssa_def
*def
)
8287 nir_foreach_use(src
, def
) {
8288 if (src
->parent_instr
->type
!= nir_instr_type_intrinsic
)
8291 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(src
->parent_instr
);
8292 if (intrin
->intrinsic
!= nir_intrinsic_load_frag_coord
)
8296 nir_foreach_if_use(src
, def
)
8303 * Return a bitfield where bit n is set if barycentric interpolation mode n
8304 * (see enum brw_barycentric_mode) is needed by the fragment shader.
8306 * We examine the load_barycentric intrinsics rather than looking at input
8307 * variables so that we catch interpolateAtCentroid() messages too, which
8308 * also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
8311 brw_compute_barycentric_interp_modes(const struct gen_device_info
*devinfo
,
8312 const nir_shader
*shader
)
8314 unsigned barycentric_interp_modes
= 0;
8316 nir_foreach_function(f
, shader
) {
8320 nir_foreach_block(block
, f
->impl
) {
8321 nir_foreach_instr(instr
, block
) {
8322 if (instr
->type
!= nir_instr_type_intrinsic
)
8325 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8326 switch (intrin
->intrinsic
) {
8327 case nir_intrinsic_load_barycentric_pixel
:
8328 case nir_intrinsic_load_barycentric_centroid
:
8329 case nir_intrinsic_load_barycentric_sample
:
8335 /* Ignore WPOS; it doesn't require interpolation. */
8336 assert(intrin
->dest
.is_ssa
);
8337 if (!is_used_in_not_interp_frag_coord(&intrin
->dest
.ssa
))
8340 enum glsl_interp_mode interp
= (enum glsl_interp_mode
)
8341 nir_intrinsic_interp_mode(intrin
);
8342 nir_intrinsic_op bary_op
= intrin
->intrinsic
;
8343 enum brw_barycentric_mode bary
=
8344 brw_barycentric_mode(interp
, bary_op
);
8346 barycentric_interp_modes
|= 1 << bary
;
8348 if (devinfo
->needs_unlit_centroid_workaround
&&
8349 bary_op
== nir_intrinsic_load_barycentric_centroid
)
8350 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary
);
8355 return barycentric_interp_modes
;
8359 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
8360 const nir_shader
*shader
)
8362 prog_data
->flat_inputs
= 0;
8364 nir_foreach_variable(var
, &shader
->inputs
) {
8365 unsigned slots
= glsl_count_attribute_slots(var
->type
, false);
8366 for (unsigned s
= 0; s
< slots
; s
++) {
8367 int input_index
= prog_data
->urb_setup
[var
->data
.location
+ s
];
8369 if (input_index
< 0)
8373 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
8374 prog_data
->flat_inputs
|= 1 << input_index
;
8380 computed_depth_mode(const nir_shader
*shader
)
8382 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
8383 switch (shader
->info
.fs
.depth_layout
) {
8384 case FRAG_DEPTH_LAYOUT_NONE
:
8385 case FRAG_DEPTH_LAYOUT_ANY
:
8386 return BRW_PSCDEPTH_ON
;
8387 case FRAG_DEPTH_LAYOUT_GREATER
:
8388 return BRW_PSCDEPTH_ON_GE
;
8389 case FRAG_DEPTH_LAYOUT_LESS
:
8390 return BRW_PSCDEPTH_ON_LE
;
8391 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
8392 return BRW_PSCDEPTH_OFF
;
8395 return BRW_PSCDEPTH_OFF
;
8399 * Move load_interpolated_input with simple (payload-based) barycentric modes
8400 * to the top of the program so we don't emit multiple PLNs for the same input.
8402 * This works around CSE not being able to handle non-dominating cases
8408 * interpolate the same exact input
8411 * This should be replaced by global value numbering someday.
8414 move_interpolation_to_top(nir_shader
*nir
)
8416 bool progress
= false;
8418 nir_foreach_function(f
, nir
) {
8422 nir_block
*top
= nir_start_block(f
->impl
);
8423 exec_node
*cursor_node
= NULL
;
8425 nir_foreach_block(block
, f
->impl
) {
8429 nir_foreach_instr_safe(instr
, block
) {
8430 if (instr
->type
!= nir_instr_type_intrinsic
)
8433 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8434 if (intrin
->intrinsic
!= nir_intrinsic_load_interpolated_input
)
8436 nir_intrinsic_instr
*bary_intrinsic
=
8437 nir_instr_as_intrinsic(intrin
->src
[0].ssa
->parent_instr
);
8438 nir_intrinsic_op op
= bary_intrinsic
->intrinsic
;
8440 /* Leave interpolateAtSample/Offset() where they are. */
8441 if (op
== nir_intrinsic_load_barycentric_at_sample
||
8442 op
== nir_intrinsic_load_barycentric_at_offset
)
8445 nir_instr
*move
[3] = {
8446 &bary_intrinsic
->instr
,
8447 intrin
->src
[1].ssa
->parent_instr
,
8451 for (unsigned i
= 0; i
< ARRAY_SIZE(move
); i
++) {
8452 if (move
[i
]->block
!= top
) {
8453 move
[i
]->block
= top
;
8454 exec_node_remove(&move
[i
]->node
);
8456 exec_node_insert_after(cursor_node
, &move
[i
]->node
);
8458 exec_list_push_head(&top
->instr_list
, &move
[i
]->node
);
8460 cursor_node
= &move
[i
]->node
;
8466 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8467 ((unsigned) nir_metadata_block_index
|
8468 (unsigned) nir_metadata_dominance
));
8475 * Demote per-sample barycentric intrinsics to centroid.
8477 * Useful when rendering to a non-multisampled buffer.
8480 demote_sample_qualifiers(nir_shader
*nir
)
8482 bool progress
= true;
8484 nir_foreach_function(f
, nir
) {
8489 nir_builder_init(&b
, f
->impl
);
8491 nir_foreach_block(block
, f
->impl
) {
8492 nir_foreach_instr_safe(instr
, block
) {
8493 if (instr
->type
!= nir_instr_type_intrinsic
)
8496 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
8497 if (intrin
->intrinsic
!= nir_intrinsic_load_barycentric_sample
&&
8498 intrin
->intrinsic
!= nir_intrinsic_load_barycentric_at_sample
)
8501 b
.cursor
= nir_before_instr(instr
);
8502 nir_ssa_def
*centroid
=
8503 nir_load_barycentric(&b
, nir_intrinsic_load_barycentric_centroid
,
8504 nir_intrinsic_interp_mode(intrin
));
8505 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
,
8506 nir_src_for_ssa(centroid
));
8507 nir_instr_remove(instr
);
8512 nir_metadata_preserve(f
->impl
, (nir_metadata
)
8513 ((unsigned) nir_metadata_block_index
|
8514 (unsigned) nir_metadata_dominance
));
8521 * Pre-gen6, the register file of the EUs was shared between threads,
8522 * and each thread used some subset allocated on a 16-register block
8523 * granularity. The unit states wanted these block counts.
8526 brw_register_blocks(int reg_count
)
8528 return ALIGN(reg_count
, 16) / 16 - 1;
8532 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
8534 const struct brw_wm_prog_key
*key
,
8535 struct brw_wm_prog_data
*prog_data
,
8537 int shader_time_index8
, int shader_time_index16
,
8538 int shader_time_index32
, bool allow_spilling
,
8539 bool use_rep_send
, struct brw_vue_map
*vue_map
,
8540 struct brw_compile_stats
*stats
,
8543 const struct gen_device_info
*devinfo
= compiler
->devinfo
;
8544 const unsigned max_subgroup_size
= compiler
->devinfo
->gen
>= 6 ? 32 : 16;
8546 brw_nir_apply_key(shader
, compiler
, &key
->base
, max_subgroup_size
, true);
8547 brw_nir_lower_fs_inputs(shader
, devinfo
, key
);
8548 brw_nir_lower_fs_outputs(shader
);
8550 if (devinfo
->gen
< 6)
8551 brw_setup_vue_interpolation(vue_map
, shader
, prog_data
);
8553 /* From the SKL PRM, Volume 7, "Alpha Coverage":
8554 * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in
8555 * hardware, regardless of the state setting for this feature."
8557 if (devinfo
->gen
> 6 && key
->alpha_to_coverage
) {
8558 /* Run constant fold optimization in order to get the correct source
8559 * offset to determine render target 0 store instruction in
8560 * emit_alpha_to_coverage pass.
8562 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8563 NIR_PASS_V(shader
, brw_nir_lower_alpha_to_coverage
);
8566 if (!key
->multisample_fbo
)
8567 NIR_PASS_V(shader
, demote_sample_qualifiers
);
8568 NIR_PASS_V(shader
, move_interpolation_to_top
);
8569 brw_postprocess_nir(shader
, compiler
, true);
8571 /* key->alpha_test_func means simulating alpha testing via discards,
8572 * so the shader definitely kills pixels.
8574 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
||
8575 key
->alpha_test_func
;
8576 prog_data
->uses_omask
= key
->multisample_fbo
&&
8577 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
8578 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
8579 prog_data
->computed_stencil
=
8580 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
8582 prog_data
->persample_dispatch
=
8583 key
->multisample_fbo
&&
8584 (key
->persample_interp
||
8585 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
8586 SYSTEM_BIT_SAMPLE_POS
)) ||
8587 shader
->info
.fs
.uses_sample_qualifier
||
8588 shader
->info
.outputs_read
);
8590 prog_data
->has_render_target_reads
= shader
->info
.outputs_read
!= 0ull;
8592 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
8593 prog_data
->post_depth_coverage
= shader
->info
.fs
.post_depth_coverage
;
8594 prog_data
->inner_coverage
= shader
->info
.fs
.inner_coverage
;
8596 prog_data
->barycentric_interp_modes
=
8597 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
8599 calculate_urb_setup(devinfo
, key
, prog_data
, shader
);
8600 brw_compute_flat_inputs(prog_data
, shader
);
8602 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
8603 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
, *simd32_cfg
= NULL
;
8604 float throughput
= 0;
8605 bool has_spilled
= false;
8607 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8608 &prog_data
->base
, shader
, 8, shader_time_index8
);
8609 if (!v8
->run_fs(allow_spilling
, false /* do_rep_send */)) {
8611 *error_str
= ralloc_strdup(mem_ctx
, v8
->fail_msg
);
8615 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
8616 simd8_cfg
= v8
->cfg
;
8617 prog_data
->base
.dispatch_grf_start_reg
= v8
->payload
.num_regs
;
8618 prog_data
->reg_blocks_8
= brw_register_blocks(v8
->grf_used
);
8619 const performance
&perf
= v8
->performance_analysis
.require();
8620 throughput
= MAX2(throughput
, perf
.throughput
);
8621 has_spilled
= v8
->spilled_any_registers
;
8622 allow_spilling
= false;
8625 /* Limit dispatch width to simd8 with dual source blending on gen8.
8626 * See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1917
8628 if (devinfo
->gen
== 8 && prog_data
->dual_src_blend
&&
8629 !(INTEL_DEBUG
& DEBUG_NO8
)) {
8630 assert(!use_rep_send
);
8631 v8
->limit_dispatch_width(8, "gen8 workaround: "
8632 "using SIMD8 when dual src blending.\n");
8636 v8
->max_dispatch_width
>= 16 &&
8637 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
8638 /* Try a SIMD16 compile */
8639 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8640 &prog_data
->base
, shader
, 16, shader_time_index16
);
8641 v16
->import_uniforms(v8
);
8642 if (!v16
->run_fs(allow_spilling
, use_rep_send
)) {
8643 compiler
->shader_perf_log(log_data
,
8644 "SIMD16 shader failed to compile: %s",
8647 simd16_cfg
= v16
->cfg
;
8648 prog_data
->dispatch_grf_start_reg_16
= v16
->payload
.num_regs
;
8649 prog_data
->reg_blocks_16
= brw_register_blocks(v16
->grf_used
);
8650 const performance
&perf
= v16
->performance_analysis
.require();
8651 throughput
= MAX2(throughput
, perf
.throughput
);
8652 has_spilled
= v16
->spilled_any_registers
;
8653 allow_spilling
= false;
8657 /* Currently, the compiler only supports SIMD32 on SNB+ */
8659 v8
->max_dispatch_width
>= 32 && !use_rep_send
&&
8660 devinfo
->gen
>= 6 && simd16_cfg
&&
8661 !(INTEL_DEBUG
& DEBUG_NO32
)) {
8662 /* Try a SIMD32 compile */
8663 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8664 &prog_data
->base
, shader
, 32, shader_time_index32
);
8665 v32
->import_uniforms(v8
);
8666 if (!v32
->run_fs(allow_spilling
, false)) {
8667 compiler
->shader_perf_log(log_data
,
8668 "SIMD32 shader failed to compile: %s",
8671 const performance
&perf
= v32
->performance_analysis
.require();
8673 if (!(INTEL_DEBUG
& DEBUG_DO32
) && throughput
>= perf
.throughput
) {
8674 compiler
->shader_perf_log(log_data
, "SIMD32 shader inefficient\n");
8676 simd32_cfg
= v32
->cfg
;
8677 prog_data
->dispatch_grf_start_reg_32
= v32
->payload
.num_regs
;
8678 prog_data
->reg_blocks_32
= brw_register_blocks(v32
->grf_used
);
8679 throughput
= MAX2(throughput
, perf
.throughput
);
8684 /* When the caller requests a repclear shader, they want SIMD16-only */
8688 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
8689 * at the top to select the shader. We've never implemented that.
8690 * Instead, we just give them exactly one shader and we pick the widest one
8693 if (compiler
->devinfo
->gen
< 5) {
8694 if (simd32_cfg
|| simd16_cfg
)
8700 /* If computed depth is enabled SNB only allows SIMD8. */
8701 if (compiler
->devinfo
->gen
== 6 &&
8702 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
)
8703 assert(simd16_cfg
== NULL
&& simd32_cfg
== NULL
);
8705 if (compiler
->devinfo
->gen
<= 5 && !simd8_cfg
) {
8706 /* Iron lake and earlier only have one Dispatch GRF start field. Make
8707 * the data available in the base prog data struct for convenience.
8710 prog_data
->base
.dispatch_grf_start_reg
=
8711 prog_data
->dispatch_grf_start_reg_16
;
8712 } else if (simd32_cfg
) {
8713 prog_data
->base
.dispatch_grf_start_reg
=
8714 prog_data
->dispatch_grf_start_reg_32
;
8718 if (prog_data
->persample_dispatch
) {
8719 /* Starting with SandyBridge (where we first get MSAA), the different
8720 * pixel dispatch combinations are grouped into classifications A
8721 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On most hardware
8722 * generations, the only configurations supporting persample dispatch
8723 * are those in which only one dispatch width is enabled.
8725 * The Gen12 hardware spec has a similar dispatch grouping table, but
8726 * the following conflicting restriction applies (from the page on
8727 * "Structure_3DSTATE_PS_BODY"), so we need to keep the SIMD16 shader:
8729 * "SIMD32 may only be enabled if SIMD16 or (dual)SIMD8 is also
8732 if (simd32_cfg
|| simd16_cfg
)
8734 if (simd32_cfg
&& devinfo
->gen
< 12)
8738 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
8739 v8
->runtime_check_aads_emit
, MESA_SHADER_FRAGMENT
);
8741 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
8742 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
8743 shader
->info
.label
?
8744 shader
->info
.label
: "unnamed",
8745 shader
->info
.name
));
8749 prog_data
->dispatch_8
= true;
8750 g
.generate_code(simd8_cfg
, 8, v8
->shader_stats
,
8751 v8
->performance_analysis
.require(), stats
);
8752 stats
= stats
? stats
+ 1 : NULL
;
8756 prog_data
->dispatch_16
= true;
8757 prog_data
->prog_offset_16
= g
.generate_code(
8758 simd16_cfg
, 16, v16
->shader_stats
,
8759 v16
->performance_analysis
.require(), stats
);
8760 stats
= stats
? stats
+ 1 : NULL
;
8764 prog_data
->dispatch_32
= true;
8765 prog_data
->prog_offset_32
= g
.generate_code(
8766 simd32_cfg
, 32, v32
->shader_stats
,
8767 v32
->performance_analysis
.require(), stats
);
8768 stats
= stats
? stats
+ 1 : NULL
;
8775 return g
.get_assembly();
8779 fs_visitor::emit_cs_work_group_id_setup()
8781 assert(stage
== MESA_SHADER_COMPUTE
);
8783 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
8785 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
8786 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
8787 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
8789 bld
.MOV(*reg
, r0_1
);
8790 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
8791 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
8797 brw_cs_push_const_total_size(const struct brw_cs_prog_data
*cs_prog_data
,
8800 assert(cs_prog_data
->push
.per_thread
.size
% REG_SIZE
== 0);
8801 assert(cs_prog_data
->push
.cross_thread
.size
% REG_SIZE
== 0);
8802 return cs_prog_data
->push
.per_thread
.size
* threads
+
8803 cs_prog_data
->push
.cross_thread
.size
;
8807 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
8809 block
->dwords
= dwords
;
8810 block
->regs
= DIV_ROUND_UP(dwords
, 8);
8811 block
->size
= block
->regs
* 32;
8815 cs_fill_push_const_info(const struct gen_device_info
*devinfo
,
8816 struct brw_cs_prog_data
*cs_prog_data
)
8818 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
8819 int subgroup_id_index
= get_subgroup_id_param_index(prog_data
);
8820 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
8822 /* The thread ID should be stored in the last param dword */
8823 assert(subgroup_id_index
== -1 ||
8824 subgroup_id_index
== (int)prog_data
->nr_params
- 1);
8826 unsigned cross_thread_dwords
, per_thread_dwords
;
8827 if (!cross_thread_supported
) {
8828 cross_thread_dwords
= 0u;
8829 per_thread_dwords
= prog_data
->nr_params
;
8830 } else if (subgroup_id_index
>= 0) {
8831 /* Fill all but the last register with cross-thread payload */
8832 cross_thread_dwords
= 8 * (subgroup_id_index
/ 8);
8833 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
8834 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
8836 /* Fill all data using cross-thread payload */
8837 cross_thread_dwords
= prog_data
->nr_params
;
8838 per_thread_dwords
= 0u;
8841 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
8842 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
8844 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
8845 cs_prog_data
->push
.per_thread
.size
== 0);
8846 assert(cs_prog_data
->push
.cross_thread
.dwords
+
8847 cs_prog_data
->push
.per_thread
.dwords
==
8848 prog_data
->nr_params
);
8852 filter_simd(const nir_instr
*instr
, const void *_options
)
8854 if (instr
->type
!= nir_instr_type_intrinsic
)
8857 switch (nir_instr_as_intrinsic(instr
)->intrinsic
) {
8858 case nir_intrinsic_load_simd_width_intel
:
8859 case nir_intrinsic_load_subgroup_id
:
8867 static nir_ssa_def
*
8868 lower_simd(nir_builder
*b
, nir_instr
*instr
, void *options
)
8870 uintptr_t simd_width
= (uintptr_t)options
;
8872 switch (nir_instr_as_intrinsic(instr
)->intrinsic
) {
8873 case nir_intrinsic_load_simd_width_intel
:
8874 return nir_imm_int(b
, simd_width
);
8876 case nir_intrinsic_load_subgroup_id
:
8877 /* If the whole workgroup fits in one thread, we can lower subgroup_id
8878 * to a constant zero.
8880 if (!b
->shader
->info
.cs
.local_size_variable
) {
8881 unsigned local_workgroup_size
= b
->shader
->info
.cs
.local_size
[0] *
8882 b
->shader
->info
.cs
.local_size
[1] *
8883 b
->shader
->info
.cs
.local_size
[2];
8884 if (local_workgroup_size
<= simd_width
)
8885 return nir_imm_int(b
, 0);
8895 brw_nir_lower_simd(nir_shader
*nir
, unsigned dispatch_width
)
8897 nir_shader_lower_instructions(nir
, filter_simd
, lower_simd
,
8898 (void *)(uintptr_t)dispatch_width
);
8902 compile_cs_to_nir(const struct brw_compiler
*compiler
,
8904 const struct brw_cs_prog_key
*key
,
8905 const nir_shader
*src_shader
,
8906 unsigned dispatch_width
)
8908 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
8909 brw_nir_apply_key(shader
, compiler
, &key
->base
, dispatch_width
, true);
8911 NIR_PASS_V(shader
, brw_nir_lower_simd
, dispatch_width
);
8913 /* Clean up after the local index and ID calculations. */
8914 NIR_PASS_V(shader
, nir_opt_constant_folding
);
8915 NIR_PASS_V(shader
, nir_opt_dce
);
8917 brw_postprocess_nir(shader
, compiler
, true);
8923 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
8925 const struct brw_cs_prog_key
*key
,
8926 struct brw_cs_prog_data
*prog_data
,
8927 const nir_shader
*src_shader
,
8928 int shader_time_index
,
8929 struct brw_compile_stats
*stats
,
8932 prog_data
->base
.total_shared
= src_shader
->info
.cs
.shared_size
;
8933 prog_data
->slm_size
= src_shader
->num_shared
;
8935 /* Generate code for all the possible SIMD variants. */
8938 unsigned min_dispatch_width
;
8939 unsigned max_dispatch_width
;
8941 if (src_shader
->info
.cs
.local_size_variable
) {
8942 generate_all
= true;
8943 min_dispatch_width
= 8;
8944 max_dispatch_width
= 32;
8946 generate_all
= false;
8947 prog_data
->local_size
[0] = src_shader
->info
.cs
.local_size
[0];
8948 prog_data
->local_size
[1] = src_shader
->info
.cs
.local_size
[1];
8949 prog_data
->local_size
[2] = src_shader
->info
.cs
.local_size
[2];
8950 unsigned local_workgroup_size
= prog_data
->local_size
[0] *
8951 prog_data
->local_size
[1] *
8952 prog_data
->local_size
[2];
8954 /* Limit max_threads to 64 for the GPGPU_WALKER command */
8955 const uint32_t max_threads
= MIN2(64, compiler
->devinfo
->max_cs_threads
);
8956 min_dispatch_width
= util_next_power_of_two(
8957 MAX2(8, DIV_ROUND_UP(local_workgroup_size
, max_threads
)));
8958 assert(min_dispatch_width
<= 32);
8959 max_dispatch_width
= 32;
8962 if ((int)key
->base
.subgroup_size_type
>= (int)BRW_SUBGROUP_SIZE_REQUIRE_8
) {
8963 /* These enum values are expressly chosen to be equal to the subgroup
8964 * size that they require.
8966 const unsigned required_dispatch_width
=
8967 (unsigned)key
->base
.subgroup_size_type
;
8968 assert(required_dispatch_width
== 8 ||
8969 required_dispatch_width
== 16 ||
8970 required_dispatch_width
== 32);
8971 if (required_dispatch_width
< min_dispatch_width
||
8972 required_dispatch_width
> max_dispatch_width
) {
8974 *error_str
= ralloc_strdup(mem_ctx
,
8975 "Cannot satisfy explicit subgroup size");
8979 min_dispatch_width
= max_dispatch_width
= required_dispatch_width
;
8982 assert(min_dispatch_width
<= max_dispatch_width
);
8984 fs_visitor
*v8
= NULL
, *v16
= NULL
, *v32
= NULL
;
8985 fs_visitor
*v
= NULL
;
8987 if (likely(!(INTEL_DEBUG
& DEBUG_NO8
)) &&
8988 min_dispatch_width
<= 8 && max_dispatch_width
>= 8) {
8989 nir_shader
*nir8
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
8991 v8
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
8993 nir8
, 8, shader_time_index
);
8994 if (!v8
->run_cs(true /* allow_spilling */)) {
8996 *error_str
= ralloc_strdup(mem_ctx
, v8
->fail_msg
);
9001 /* We should always be able to do SIMD32 for compute shaders */
9002 assert(v8
->max_dispatch_width
>= 32);
9005 prog_data
->prog_mask
|= 1 << 0;
9006 if (v8
->spilled_any_registers
)
9007 prog_data
->prog_spilled
|= 1 << 0;
9008 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
9011 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
9012 (generate_all
|| !prog_data
->prog_spilled
) &&
9013 min_dispatch_width
<= 16 && max_dispatch_width
>= 16) {
9014 /* Try a SIMD16 compile */
9015 nir_shader
*nir16
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
9017 v16
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
9019 nir16
, 16, shader_time_index
);
9021 v16
->import_uniforms(v8
);
9023 const bool allow_spilling
= generate_all
|| v
== NULL
;
9024 if (!v16
->run_cs(allow_spilling
)) {
9025 compiler
->shader_perf_log(log_data
,
9026 "SIMD16 shader failed to compile: %s",
9031 *error_str
= ralloc_asprintf(
9032 mem_ctx
, "Not enough threads for SIMD8 and "
9033 "couldn't generate SIMD16: %s", v16
->fail_msg
);
9039 /* We should always be able to do SIMD32 for compute shaders */
9040 assert(v16
->max_dispatch_width
>= 32);
9043 prog_data
->prog_mask
|= 1 << 1;
9044 if (v16
->spilled_any_registers
)
9045 prog_data
->prog_spilled
|= 1 << 1;
9046 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
9050 /* The SIMD32 is only enabled for cases it is needed unless forced.
9052 * TODO: Use performance_analysis and drop this boolean.
9054 const bool needs_32
= min_dispatch_width
> 16 ||
9055 (INTEL_DEBUG
& DEBUG_DO32
) ||
9058 if (likely(!(INTEL_DEBUG
& DEBUG_NO32
)) &&
9059 (generate_all
|| !prog_data
->prog_spilled
) &&
9061 min_dispatch_width
<= 32 && max_dispatch_width
>= 32) {
9062 /* Try a SIMD32 compile */
9063 nir_shader
*nir32
= compile_cs_to_nir(compiler
, mem_ctx
, key
,
9065 v32
= new fs_visitor(compiler
, log_data
, mem_ctx
, &key
->base
,
9067 nir32
, 32, shader_time_index
);
9069 v32
->import_uniforms(v8
);
9071 v32
->import_uniforms(v16
);
9073 const bool allow_spilling
= generate_all
|| v
== NULL
;
9074 if (!v32
->run_cs(allow_spilling
)) {
9075 compiler
->shader_perf_log(log_data
,
9076 "SIMD32 shader failed to compile: %s",
9080 assert(v16
== NULL
);
9082 *error_str
= ralloc_asprintf(
9083 mem_ctx
, "Not enough threads for SIMD16 and "
9084 "couldn't generate SIMD32: %s", v32
->fail_msg
);
9091 prog_data
->prog_mask
|= 1 << 2;
9092 if (v32
->spilled_any_registers
)
9093 prog_data
->prog_spilled
|= 1 << 2;
9094 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
9098 if (unlikely(!v
&& (INTEL_DEBUG
& (DEBUG_NO8
| DEBUG_NO16
| DEBUG_NO32
)))) {
9101 ralloc_strdup(mem_ctx
,
9102 "Cannot satisfy INTEL_DEBUG flags SIMD restrictions");
9109 const unsigned *ret
= NULL
;
9111 fs_generator
g(compiler
, log_data
, mem_ctx
, &prog_data
->base
,
9112 v
->runtime_check_aads_emit
, MESA_SHADER_COMPUTE
);
9113 if (INTEL_DEBUG
& DEBUG_CS
) {
9114 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
9115 src_shader
->info
.label
?
9116 src_shader
->info
.label
: "unnamed",
9117 src_shader
->info
.name
);
9118 g
.enable_debug(name
);
9122 if (prog_data
->prog_mask
& (1 << 0)) {
9124 prog_data
->prog_offset
[0] =
9125 g
.generate_code(v8
->cfg
, 8, v8
->shader_stats
,
9126 v8
->performance_analysis
.require(), stats
);
9127 stats
= stats
? stats
+ 1 : NULL
;
9130 if (prog_data
->prog_mask
& (1 << 1)) {
9132 prog_data
->prog_offset
[1] =
9133 g
.generate_code(v16
->cfg
, 16, v16
->shader_stats
,
9134 v16
->performance_analysis
.require(), stats
);
9135 stats
= stats
? stats
+ 1 : NULL
;
9138 if (prog_data
->prog_mask
& (1 << 2)) {
9140 prog_data
->prog_offset
[2] =
9141 g
.generate_code(v32
->cfg
, 32, v32
->shader_stats
,
9142 v32
->performance_analysis
.require(), stats
);
9143 stats
= stats
? stats
+ 1 : NULL
;
9146 /* Only one dispatch width will be valid, and will be at offset 0,
9147 * which is already the default value of prog_offset_* fields.
9149 prog_data
->prog_mask
= 1 << (v
->dispatch_width
/ 16);
9150 g
.generate_code(v
->cfg
, v
->dispatch_width
, v
->shader_stats
,
9151 v
->performance_analysis
.require(), stats
);
9154 ret
= g
.get_assembly();
9164 brw_cs_simd_size_for_group_size(const struct gen_device_info
*devinfo
,
9165 const struct brw_cs_prog_data
*cs_prog_data
,
9166 unsigned group_size
)
9168 const unsigned mask
= cs_prog_data
->prog_mask
;
9171 static const unsigned simd8
= 1 << 0;
9172 static const unsigned simd16
= 1 << 1;
9173 static const unsigned simd32
= 1 << 2;
9175 if (unlikely(INTEL_DEBUG
& DEBUG_DO32
) && (mask
& simd32
))
9178 /* Limit max_threads to 64 for the GPGPU_WALKER command */
9179 const uint32_t max_threads
= MIN2(64, devinfo
->max_cs_threads
);
9181 if ((mask
& simd8
) && group_size
<= 8 * max_threads
) {
9182 /* Prefer SIMD16 if can do without spilling. Matches logic in
9185 if ((mask
& simd16
) && (~cs_prog_data
->prog_spilled
& simd16
))
9190 if ((mask
& simd16
) && group_size
<= 16 * max_threads
)
9193 assert(mask
& simd32
);
9194 assert(group_size
<= 32 * max_threads
);
9199 * Test the dispatch mask packing assumptions of
9200 * brw_stage_has_packed_dispatch(). Call this from e.g. the top of
9201 * fs_visitor::emit_nir_code() to cause a GPU hang if any shader invocation is
9202 * executed with an unexpected dispatch mask.
9205 brw_fs_test_dispatch_packing(const fs_builder
&bld
)
9207 const gl_shader_stage stage
= bld
.shader
->stage
;
9209 if (brw_stage_has_packed_dispatch(bld
.shader
->devinfo
, stage
,
9210 bld
.shader
->stage_prog_data
)) {
9211 const fs_builder ubld
= bld
.exec_all().group(1, 0);
9212 const fs_reg tmp
= component(bld
.vgrf(BRW_REGISTER_TYPE_UD
), 0);
9213 const fs_reg mask
= (stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
9216 ubld
.ADD(tmp
, mask
, brw_imm_ud(1));
9217 ubld
.AND(tmp
, mask
, tmp
);
9219 /* This will loop forever if the dispatch mask doesn't have the expected
9220 * form '2^n-1', in which case tmp will be non-zero.
9222 bld
.emit(BRW_OPCODE_DO
);
9223 bld
.CMP(bld
.null_reg_ud(), tmp
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
9224 set_predicate(BRW_PREDICATE_NORMAL
, bld
.emit(BRW_OPCODE_WHILE
));
9229 fs_visitor::workgroup_size() const
9231 assert(stage
== MESA_SHADER_COMPUTE
);
9232 const struct brw_cs_prog_data
*cs
= brw_cs_prog_data(prog_data
);
9233 return cs
->local_size
[0] * cs
->local_size
[1] * cs
->local_size
[2];