0cec6fdcbad7a0e348f22fd54072350bea31de08
[mesa.git] / src / intel / compiler / brw_fs.h
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #ifndef BRW_FS_H
29 #define BRW_FS_H
30
31 #include "brw_shader.h"
32 #include "brw_ir_fs.h"
33 #include "brw_fs_builder.h"
34 #include "compiler/nir/nir.h"
35
36 struct bblock_t;
37 namespace {
38 struct acp_entry;
39 }
40
41 namespace brw {
42 class fs_live_variables;
43 }
44
45 struct brw_gs_compile;
46
47 static inline fs_reg
48 offset(const fs_reg &reg, const brw::fs_builder &bld, unsigned delta)
49 {
50 return offset(reg, bld.dispatch_width(), delta);
51 }
52
53 #define UBO_START ((1 << 16) - 4)
54
55 /**
56 * The fragment shader front-end.
57 *
58 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
59 */
60 class fs_visitor : public backend_shader
61 {
62 public:
63 fs_visitor(const struct brw_compiler *compiler, void *log_data,
64 void *mem_ctx,
65 const void *key,
66 struct brw_stage_prog_data *prog_data,
67 struct gl_program *prog,
68 const nir_shader *shader,
69 unsigned dispatch_width,
70 int shader_time_index,
71 const struct brw_vue_map *input_vue_map = NULL);
72 fs_visitor(const struct brw_compiler *compiler, void *log_data,
73 void *mem_ctx,
74 struct brw_gs_compile *gs_compile,
75 struct brw_gs_prog_data *prog_data,
76 const nir_shader *shader,
77 int shader_time_index);
78 void init();
79 ~fs_visitor();
80
81 fs_reg vgrf(const glsl_type *const type);
82 void import_uniforms(fs_visitor *v);
83 void setup_uniform_clipplane_values();
84 void compute_clip_distance();
85
86 fs_inst *get_instruction_generating_reg(fs_inst *start,
87 fs_inst *end,
88 const fs_reg &reg);
89
90 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
91 const fs_reg &dst,
92 const fs_reg &surf_index,
93 const fs_reg &varying_offset,
94 uint32_t const_offset);
95 void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
96
97 bool run_fs(bool allow_spilling, bool do_rep_send);
98 bool run_vs();
99 bool run_tcs_single_patch();
100 bool run_tes();
101 bool run_gs();
102 bool run_cs(unsigned min_dispatch_width);
103 void optimize();
104 void allocate_registers(unsigned min_dispatch_width, bool allow_spilling);
105 void setup_fs_payload_gen4();
106 void setup_fs_payload_gen6();
107 void setup_vs_payload();
108 void setup_gs_payload();
109 void setup_cs_payload();
110 void fixup_3src_null_dest();
111 void assign_curb_setup();
112 void calculate_urb_setup();
113 void assign_urb_setup();
114 void convert_attr_sources_to_hw_regs(fs_inst *inst);
115 void assign_vs_urb_setup();
116 void assign_tcs_single_patch_urb_setup();
117 void assign_tes_urb_setup();
118 void assign_gs_urb_setup();
119 bool assign_regs(bool allow_spilling, bool spill_all);
120 void assign_regs_trivial();
121 void calculate_payload_ranges(int payload_node_count,
122 int *payload_last_use_ip);
123 void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
124 int first_payload_node);
125 int choose_spill_reg(struct ra_graph *g);
126 void spill_reg(int spill_reg);
127 void split_virtual_grfs();
128 bool compact_virtual_grfs();
129 void assign_constant_locations();
130 bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index,
131 unsigned *out_pull_index);
132 void lower_constant_loads();
133 void invalidate_live_intervals();
134 void calculate_live_intervals();
135 void calculate_register_pressure();
136 void validate();
137 bool opt_algebraic();
138 bool opt_redundant_discard_jumps();
139 bool opt_cse();
140 bool opt_cse_local(bblock_t *block);
141 bool opt_copy_propagation();
142 bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
143 bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
144 bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block,
145 exec_list *acp);
146 bool opt_drop_redundant_mov_to_flags();
147 bool opt_register_renaming();
148 bool opt_bank_conflicts();
149 bool register_coalesce();
150 bool compute_to_mrf();
151 bool eliminate_find_live_channel();
152 bool dead_code_eliminate();
153 bool remove_duplicate_mrf_writes();
154 bool remove_extra_rounding_modes();
155
156 bool opt_sampler_eot();
157 bool virtual_grf_interferes(int a, int b);
158 void schedule_instructions(instruction_scheduler_mode mode);
159 void insert_gen4_send_dependency_workarounds();
160 void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
161 fs_inst *inst);
162 void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
163 fs_inst *inst);
164 void vfail(const char *msg, va_list args);
165 void fail(const char *msg, ...);
166 void limit_dispatch_width(unsigned n, const char *msg);
167 void lower_uniform_pull_constant_loads();
168 bool lower_load_payload();
169 bool lower_pack();
170 bool lower_conversions();
171 bool lower_logical_sends();
172 bool lower_integer_multiplication();
173 bool lower_minmax();
174 bool lower_simd_width();
175 bool opt_combine_constants();
176
177 void emit_dummy_fs();
178 void emit_repclear_shader();
179 void emit_fragcoord_interpolation(fs_reg wpos);
180 fs_reg *emit_frontfacing_interpolation();
181 fs_reg *emit_samplepos_setup();
182 fs_reg *emit_sampleid_setup();
183 fs_reg *emit_samplemaskin_setup();
184 void emit_interpolation_setup_gen4();
185 void emit_interpolation_setup_gen6();
186 void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
187 fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
188 const fs_reg &sampler);
189 void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
190 fs_reg resolve_source_modifiers(const fs_reg &src);
191 void emit_discard_jump();
192 bool opt_peephole_sel();
193 bool opt_peephole_predicated_break();
194 bool opt_saturate_propagation();
195 bool opt_cmod_propagation();
196 bool opt_zero_samples();
197
198 void emit_nir_code();
199 void nir_setup_outputs();
200 void nir_setup_uniforms();
201 void nir_emit_system_values();
202 void nir_emit_impl(nir_function_impl *impl);
203 void nir_emit_cf_list(exec_list *list);
204 void nir_emit_if(nir_if *if_stmt);
205 void nir_emit_loop(nir_loop *loop);
206 void nir_emit_block(nir_block *block);
207 void nir_emit_instr(nir_instr *instr);
208 void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
209 void nir_emit_load_const(const brw::fs_builder &bld,
210 nir_load_const_instr *instr);
211 void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
212 nir_intrinsic_instr *instr);
213 void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
214 nir_intrinsic_instr *instr);
215 void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
216 nir_intrinsic_instr *instr);
217 void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
218 nir_intrinsic_instr *instr);
219 void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
220 nir_intrinsic_instr *instr);
221 void nir_emit_intrinsic(const brw::fs_builder &bld,
222 nir_intrinsic_instr *instr);
223 void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
224 nir_intrinsic_instr *instr);
225 void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
226 int op, nir_intrinsic_instr *instr);
227 void nir_emit_shared_atomic(const brw::fs_builder &bld,
228 int op, nir_intrinsic_instr *instr);
229 void nir_emit_texture(const brw::fs_builder &bld,
230 nir_tex_instr *instr);
231 void nir_emit_jump(const brw::fs_builder &bld,
232 nir_jump_instr *instr);
233 fs_reg get_nir_src(const nir_src &src);
234 fs_reg get_nir_src_imm(const nir_src &src);
235 fs_reg get_nir_dest(const nir_dest &dest);
236 fs_reg get_nir_image_deref(const nir_deref_var *deref);
237 fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
238 void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
239 unsigned wr_mask);
240
241 bool optimize_extract_to_float(nir_alu_instr *instr,
242 const fs_reg &result);
243 bool optimize_frontfacing_ternary(nir_alu_instr *instr,
244 const fs_reg &result);
245
246 void emit_alpha_test();
247 fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
248 fs_reg color1, fs_reg color2,
249 fs_reg src0_alpha, unsigned components);
250 void emit_fb_writes();
251 fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld,
252 const fs_reg &dst, unsigned target);
253 void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
254 void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
255 unsigned stream_id);
256 void emit_gs_control_data_bits(const fs_reg &vertex_count);
257 void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
258 void emit_gs_vertex(const nir_src &vertex_count_nir_src,
259 unsigned stream_id);
260 void emit_gs_thread_end();
261 void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
262 unsigned base_offset, const nir_src &offset_src,
263 unsigned num_components, unsigned first_component);
264 void emit_cs_terminate();
265 fs_reg *emit_cs_work_group_id_setup();
266
267 void emit_barrier();
268
269 void emit_shader_time_begin();
270 void emit_shader_time_end();
271 void SHADER_TIME_ADD(const brw::fs_builder &bld,
272 int shader_time_subindex,
273 fs_reg value);
274
275 fs_reg get_timestamp(const brw::fs_builder &bld);
276
277 struct brw_reg interp_reg(int location, int channel);
278
279 int implied_mrf_writes(fs_inst *inst);
280
281 virtual void dump_instructions();
282 virtual void dump_instructions(const char *name);
283 void dump_instruction(backend_instruction *inst);
284 void dump_instruction(backend_instruction *inst, FILE *file);
285
286 const void *const key;
287 const struct brw_sampler_prog_key_data *key_tex;
288
289 struct brw_gs_compile *gs_compile;
290
291 struct brw_stage_prog_data *prog_data;
292 struct gl_program *prog;
293
294 const struct brw_vue_map *input_vue_map;
295
296 int *virtual_grf_start;
297 int *virtual_grf_end;
298 brw::fs_live_variables *live_intervals;
299
300 int *regs_live_at_ip;
301
302 /** Number of uniform variable components visited. */
303 unsigned uniforms;
304
305 /** Byte-offset for the next available spot in the scratch space buffer. */
306 unsigned last_scratch;
307
308 /**
309 * Array mapping UNIFORM register numbers to the pull parameter index,
310 * or -1 if this uniform register isn't being uploaded as a pull constant.
311 */
312 int *pull_constant_loc;
313
314 /**
315 * Array mapping UNIFORM register numbers to the push parameter index,
316 * or -1 if this uniform register isn't being uploaded as a push constant.
317 */
318 int *push_constant_loc;
319
320 fs_reg subgroup_id;
321 fs_reg frag_depth;
322 fs_reg frag_stencil;
323 fs_reg sample_mask;
324 fs_reg outputs[VARYING_SLOT_MAX];
325 fs_reg dual_src_output;
326 int first_non_payload_grf;
327 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
328 unsigned max_grf;
329
330 fs_reg *nir_locals;
331 fs_reg *nir_ssa_values;
332 fs_reg *nir_system_values;
333
334 bool failed;
335 char *fail_msg;
336
337 /** Register numbers for thread payload fields. */
338 struct thread_payload {
339 uint8_t source_depth_reg;
340 uint8_t source_w_reg;
341 uint8_t aa_dest_stencil_reg;
342 uint8_t dest_depth_reg;
343 uint8_t sample_pos_reg;
344 uint8_t sample_mask_in_reg;
345 uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT];
346 uint8_t local_invocation_id_reg;
347
348 /** The number of thread payload registers the hardware will supply. */
349 uint8_t num_regs;
350 } payload;
351
352 bool source_depth_to_render_target;
353 bool runtime_check_aads_emit;
354
355 fs_reg pixel_x;
356 fs_reg pixel_y;
357 fs_reg wpos_w;
358 fs_reg pixel_w;
359 fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
360 fs_reg shader_start_time;
361 fs_reg userplane[MAX_CLIP_PLANES];
362 fs_reg final_gs_vertex_count;
363 fs_reg control_data_bits;
364 fs_reg invocation_id;
365
366 unsigned grf_used;
367 bool spilled_any_registers;
368
369 const unsigned dispatch_width; /**< 8, 16 or 32 */
370 unsigned max_dispatch_width;
371
372 int shader_time_index;
373
374 unsigned promoted_constants;
375 brw::fs_builder bld;
376 };
377
378 /**
379 * The fragment shader code generator.
380 *
381 * Translates FS IR to actual i965 assembly code.
382 */
383 class fs_generator
384 {
385 public:
386 fs_generator(const struct brw_compiler *compiler, void *log_data,
387 void *mem_ctx,
388 const void *key,
389 struct brw_stage_prog_data *prog_data,
390 unsigned promoted_constants,
391 bool runtime_check_aads_emit,
392 gl_shader_stage stage);
393 ~fs_generator();
394
395 void enable_debug(const char *shader_name);
396 int generate_code(const cfg_t *cfg, int dispatch_width);
397 const unsigned *get_assembly(unsigned int *assembly_size);
398
399 private:
400 void fire_fb_write(fs_inst *inst,
401 struct brw_reg payload,
402 struct brw_reg implied_header,
403 GLuint nr);
404 void generate_fb_write(fs_inst *inst, struct brw_reg payload);
405 void generate_fb_read(fs_inst *inst, struct brw_reg dst,
406 struct brw_reg payload);
407 void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
408 void generate_urb_write(fs_inst *inst, struct brw_reg payload);
409 void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
410 void generate_barrier(fs_inst *inst, struct brw_reg src);
411 void generate_linterp(fs_inst *inst, struct brw_reg dst,
412 struct brw_reg *src);
413 void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
414 struct brw_reg surface_index,
415 struct brw_reg sampler_index);
416 void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
417 struct brw_reg src,
418 struct brw_reg surf_index);
419 void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
420 void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src);
421 void generate_scratch_write(fs_inst *inst, struct brw_reg src);
422 void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
423 void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
424 void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
425 struct brw_reg index,
426 struct brw_reg offset);
427 void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
428 struct brw_reg dst,
429 struct brw_reg surf_index,
430 struct brw_reg payload);
431 void generate_varying_pull_constant_load_gen4(fs_inst *inst,
432 struct brw_reg dst,
433 struct brw_reg index);
434 void generate_varying_pull_constant_load_gen7(fs_inst *inst,
435 struct brw_reg dst,
436 struct brw_reg index,
437 struct brw_reg offset);
438 void generate_mov_dispatch_to_flags(fs_inst *inst);
439
440 void generate_pixel_interpolator_query(fs_inst *inst,
441 struct brw_reg dst,
442 struct brw_reg src,
443 struct brw_reg msg_data,
444 unsigned msg_type);
445
446 void generate_set_sample_id(fs_inst *inst,
447 struct brw_reg dst,
448 struct brw_reg src0,
449 struct brw_reg src1);
450
451 void generate_discard_jump(fs_inst *inst);
452
453 void generate_pack_half_2x16_split(fs_inst *inst,
454 struct brw_reg dst,
455 struct brw_reg x,
456 struct brw_reg y);
457 void generate_unpack_half_2x16_split(fs_inst *inst,
458 struct brw_reg dst,
459 struct brw_reg src);
460
461 void generate_shader_time_add(fs_inst *inst,
462 struct brw_reg payload,
463 struct brw_reg offset,
464 struct brw_reg value);
465
466 void generate_mov_indirect(fs_inst *inst,
467 struct brw_reg dst,
468 struct brw_reg reg,
469 struct brw_reg indirect_byte_offset);
470
471 bool patch_discard_jumps_to_fb_writes();
472
473 const struct brw_compiler *compiler;
474 void *log_data; /* Passed to compiler->*_log functions */
475
476 const struct gen_device_info *devinfo;
477
478 struct brw_codegen *p;
479 const void * const key;
480 struct brw_stage_prog_data * const prog_data;
481
482 unsigned dispatch_width; /**< 8, 16 or 32 */
483
484 exec_list discard_halt_patches;
485 unsigned promoted_constants;
486 bool runtime_check_aads_emit;
487 bool debug_flag;
488 const char *shader_name;
489 gl_shader_stage stage;
490 void *mem_ctx;
491 };
492
493 void shuffle_32bit_load_result_to_64bit_data(const brw::fs_builder &bld,
494 const fs_reg &dst,
495 const fs_reg &src,
496 uint32_t components);
497
498 fs_reg shuffle_64bit_data_for_32bit_write(const brw::fs_builder &bld,
499 const fs_reg &src,
500 uint32_t components);
501
502 void shuffle_32bit_load_result_to_16bit_data(const brw::fs_builder &bld,
503 const fs_reg &dst,
504 const fs_reg &src,
505 uint32_t components);
506
507 void shuffle_16bit_data_for_32bit_write(const brw::fs_builder &bld,
508 const fs_reg &dst,
509 const fs_reg &src,
510 uint32_t components);
511
512 fs_reg setup_imm_df(const brw::fs_builder &bld,
513 double v);
514
515 enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
516 nir_intrinsic_op op);
517
518 #endif /* BRW_FS_H */