2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
31 #include "brw_shader.h"
32 #include "brw_ir_fs.h"
33 #include "brw_fs_builder.h"
34 #include "brw_fs_live_variables.h"
35 #include "brw_ir_performance.h"
36 #include "compiler/nir/nir.h"
47 * Register pressure analysis of a shader. Estimates how many registers
48 * are live at any point of the program in GRF units.
50 struct register_pressure
{
51 register_pressure(const fs_visitor
*v
);
54 analysis_dependency_class
55 dependency_class() const
57 return (DEPENDENCY_INSTRUCTION_IDENTITY
|
58 DEPENDENCY_INSTRUCTION_DATA_FLOW
|
59 DEPENDENCY_VARIABLES
);
63 validate(const fs_visitor
*) const
69 unsigned *regs_live_at_ip
;
73 struct brw_gs_compile
;
76 offset(const fs_reg
®
, const brw::fs_builder
&bld
, unsigned delta
)
78 return offset(reg
, bld
.dispatch_width(), delta
);
81 #define UBO_START ((1 << 16) - 4)
84 const char *scheduler_mode
;
85 unsigned promoted_constants
;
89 * The fragment shader front-end.
91 * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
93 class fs_visitor
: public backend_shader
96 fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
98 const brw_base_prog_key
*key
,
99 struct brw_stage_prog_data
*prog_data
,
100 const nir_shader
*shader
,
101 unsigned dispatch_width
,
102 int shader_time_index
,
103 const struct brw_vue_map
*input_vue_map
= NULL
);
104 fs_visitor(const struct brw_compiler
*compiler
, void *log_data
,
106 struct brw_gs_compile
*gs_compile
,
107 struct brw_gs_prog_data
*prog_data
,
108 const nir_shader
*shader
,
109 int shader_time_index
);
113 fs_reg
vgrf(const glsl_type
*const type
);
114 void import_uniforms(fs_visitor
*v
);
116 void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder
&bld
,
118 const fs_reg
&surf_index
,
119 const fs_reg
&varying_offset
,
120 uint32_t const_offset
);
121 void DEP_RESOLVE_MOV(const brw::fs_builder
&bld
, int grf
);
123 bool run_fs(bool allow_spilling
, bool do_rep_send
);
128 bool run_cs(unsigned min_dispatch_width
);
130 void allocate_registers(unsigned min_dispatch_width
, bool allow_spilling
);
131 void setup_fs_payload_gen4();
132 void setup_fs_payload_gen6();
133 void setup_vs_payload();
134 void setup_gs_payload();
135 void setup_cs_payload();
136 bool fixup_sends_duplicate_payload();
137 void fixup_3src_null_dest();
138 bool fixup_nomask_control_flow();
139 void assign_curb_setup();
140 void assign_urb_setup();
141 void convert_attr_sources_to_hw_regs(fs_inst
*inst
);
142 void assign_vs_urb_setup();
143 void assign_tcs_urb_setup();
144 void assign_tes_urb_setup();
145 void assign_gs_urb_setup();
146 bool assign_regs(bool allow_spilling
, bool spill_all
);
147 void assign_regs_trivial();
148 void calculate_payload_ranges(int payload_node_count
,
149 int *payload_last_use_ip
) const;
150 void split_virtual_grfs();
151 bool compact_virtual_grfs();
152 void assign_constant_locations();
153 bool get_pull_locs(const fs_reg
&src
, unsigned *out_surf_index
,
154 unsigned *out_pull_index
);
155 void lower_constant_loads();
156 virtual void invalidate_analysis(brw::analysis_dependency_class c
);
158 bool opt_algebraic();
159 bool opt_redundant_discard_jumps();
161 bool opt_cse_local(const brw::fs_live_variables
&live
, bblock_t
*block
, int &ip
);
163 bool opt_copy_propagation();
164 bool try_copy_propagate(fs_inst
*inst
, int arg
, acp_entry
*entry
);
165 bool try_constant_propagate(fs_inst
*inst
, acp_entry
*entry
);
166 bool opt_copy_propagation_local(void *mem_ctx
, bblock_t
*block
,
168 bool opt_drop_redundant_mov_to_flags();
169 bool opt_register_renaming();
170 bool opt_bank_conflicts();
171 bool register_coalesce();
172 bool compute_to_mrf();
173 bool eliminate_find_live_channel();
174 bool dead_code_eliminate();
175 bool remove_duplicate_mrf_writes();
176 bool remove_extra_rounding_modes();
178 bool opt_sampler_eot();
179 void schedule_instructions(instruction_scheduler_mode mode
);
180 void insert_gen4_send_dependency_workarounds();
181 void insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
183 void insert_gen4_post_send_dependency_workarounds(bblock_t
*block
,
185 void vfail(const char *msg
, va_list args
);
186 void fail(const char *msg
, ...);
187 void limit_dispatch_width(unsigned n
, const char *msg
);
188 void lower_uniform_pull_constant_loads();
189 bool lower_load_payload();
191 bool lower_regioning();
192 bool lower_logical_sends();
193 bool lower_integer_multiplication();
195 bool lower_simd_width();
196 bool lower_barycentrics();
197 bool lower_scoreboard();
198 bool lower_sub_sat();
199 bool opt_combine_constants();
201 void emit_dummy_fs();
202 void emit_repclear_shader();
203 void emit_fragcoord_interpolation(fs_reg wpos
);
204 fs_reg
*emit_frontfacing_interpolation();
205 fs_reg
*emit_samplepos_setup();
206 fs_reg
*emit_sampleid_setup();
207 fs_reg
*emit_samplemaskin_setup();
208 void emit_interpolation_setup_gen4();
209 void emit_interpolation_setup_gen6();
210 void compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
);
211 fs_reg
emit_mcs_fetch(const fs_reg
&coordinate
, unsigned components
,
212 const fs_reg
&texture
,
213 const fs_reg
&texture_handle
);
214 void emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
);
215 fs_reg
resolve_source_modifiers(const fs_reg
&src
);
216 void emit_discard_jump();
217 void emit_fsign(const class brw::fs_builder
&, const nir_alu_instr
*instr
,
218 fs_reg result
, fs_reg
*op
, unsigned fsign_src
);
219 void emit_shader_float_controls_execution_mode();
220 bool opt_peephole_sel();
221 bool opt_peephole_predicated_break();
222 bool opt_saturate_propagation();
223 bool opt_cmod_propagation();
224 bool opt_zero_samples();
226 void set_tcs_invocation_id();
228 void emit_nir_code();
229 void nir_setup_outputs();
230 void nir_setup_uniforms();
231 void nir_emit_system_values();
232 void nir_emit_impl(nir_function_impl
*impl
);
233 void nir_emit_cf_list(exec_list
*list
);
234 void nir_emit_if(nir_if
*if_stmt
);
235 void nir_emit_loop(nir_loop
*loop
);
236 void nir_emit_block(nir_block
*block
);
237 void nir_emit_instr(nir_instr
*instr
);
238 void nir_emit_alu(const brw::fs_builder
&bld
, nir_alu_instr
*instr
,
240 bool try_emit_b2fi_of_inot(const brw::fs_builder
&bld
, fs_reg result
,
241 nir_alu_instr
*instr
);
242 void nir_emit_load_const(const brw::fs_builder
&bld
,
243 nir_load_const_instr
*instr
);
244 void nir_emit_vs_intrinsic(const brw::fs_builder
&bld
,
245 nir_intrinsic_instr
*instr
);
246 void nir_emit_tcs_intrinsic(const brw::fs_builder
&bld
,
247 nir_intrinsic_instr
*instr
);
248 void nir_emit_gs_intrinsic(const brw::fs_builder
&bld
,
249 nir_intrinsic_instr
*instr
);
250 void nir_emit_fs_intrinsic(const brw::fs_builder
&bld
,
251 nir_intrinsic_instr
*instr
);
252 void nir_emit_cs_intrinsic(const brw::fs_builder
&bld
,
253 nir_intrinsic_instr
*instr
);
254 fs_reg
get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
255 nir_intrinsic_instr
*instr
);
256 fs_reg
get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
257 nir_intrinsic_instr
*instr
);
258 fs_reg
swizzle_nir_scratch_addr(const brw::fs_builder
&bld
,
261 void nir_emit_intrinsic(const brw::fs_builder
&bld
,
262 nir_intrinsic_instr
*instr
);
263 void nir_emit_tes_intrinsic(const brw::fs_builder
&bld
,
264 nir_intrinsic_instr
*instr
);
265 void nir_emit_ssbo_atomic(const brw::fs_builder
&bld
,
266 int op
, nir_intrinsic_instr
*instr
);
267 void nir_emit_ssbo_atomic_float(const brw::fs_builder
&bld
,
268 int op
, nir_intrinsic_instr
*instr
);
269 void nir_emit_shared_atomic(const brw::fs_builder
&bld
,
270 int op
, nir_intrinsic_instr
*instr
);
271 void nir_emit_shared_atomic_float(const brw::fs_builder
&bld
,
272 int op
, nir_intrinsic_instr
*instr
);
273 void nir_emit_global_atomic(const brw::fs_builder
&bld
,
274 int op
, nir_intrinsic_instr
*instr
);
275 void nir_emit_global_atomic_float(const brw::fs_builder
&bld
,
276 int op
, nir_intrinsic_instr
*instr
);
277 void nir_emit_texture(const brw::fs_builder
&bld
,
278 nir_tex_instr
*instr
);
279 void nir_emit_jump(const brw::fs_builder
&bld
,
280 nir_jump_instr
*instr
);
281 fs_reg
get_nir_src(const nir_src
&src
);
282 fs_reg
get_nir_src_imm(const nir_src
&src
);
283 fs_reg
get_nir_dest(const nir_dest
&dest
);
284 fs_reg
get_indirect_offset(nir_intrinsic_instr
*instr
);
285 fs_reg
get_tcs_single_patch_icp_handle(const brw::fs_builder
&bld
,
286 nir_intrinsic_instr
*instr
);
287 fs_reg
get_tcs_eight_patch_icp_handle(const brw::fs_builder
&bld
,
288 nir_intrinsic_instr
*instr
);
289 struct brw_reg
get_tcs_output_urb_handle();
291 void emit_percomp(const brw::fs_builder
&bld
, const fs_inst
&inst
,
294 bool optimize_extract_to_float(nir_alu_instr
*instr
,
295 const fs_reg
&result
);
296 bool optimize_frontfacing_ternary(nir_alu_instr
*instr
,
297 const fs_reg
&result
);
299 void emit_alpha_test();
300 fs_inst
*emit_single_fb_write(const brw::fs_builder
&bld
,
301 fs_reg color1
, fs_reg color2
,
302 fs_reg src0_alpha
, unsigned components
);
303 void emit_alpha_to_coverage_workaround(const fs_reg
&src0_alpha
);
304 void emit_fb_writes();
305 fs_inst
*emit_non_coherent_fb_read(const brw::fs_builder
&bld
,
306 const fs_reg
&dst
, unsigned target
);
307 void emit_urb_writes(const fs_reg
&gs_vertex_count
= fs_reg());
308 void set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
310 void emit_gs_control_data_bits(const fs_reg
&vertex_count
);
311 void emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
);
312 void emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
314 void emit_gs_thread_end();
315 void emit_gs_input_load(const fs_reg
&dst
, const nir_src
&vertex_src
,
316 unsigned base_offset
, const nir_src
&offset_src
,
317 unsigned num_components
, unsigned first_component
);
318 void emit_cs_terminate();
319 fs_reg
*emit_cs_work_group_id_setup();
323 void emit_shader_time_begin();
324 void emit_shader_time_end();
325 void SHADER_TIME_ADD(const brw::fs_builder
&bld
,
326 int shader_time_subindex
,
329 fs_reg
get_timestamp(const brw::fs_builder
&bld
);
331 fs_reg
interp_reg(int location
, int channel
);
333 virtual void dump_instructions() const;
334 virtual void dump_instructions(const char *name
) const;
335 void dump_instruction(const backend_instruction
*inst
) const;
336 void dump_instruction(const backend_instruction
*inst
, FILE *file
) const;
338 const brw_base_prog_key
*const key
;
339 const struct brw_sampler_prog_key_data
*key_tex
;
341 struct brw_gs_compile
*gs_compile
;
343 struct brw_stage_prog_data
*prog_data
;
345 const struct brw_vue_map
*input_vue_map
;
349 BRW_ANALYSIS(live_analysis
, brw::fs_live_variables
,
350 backend_shader
*) live_analysis
;
351 BRW_ANALYSIS(regpressure_analysis
, brw::register_pressure
,
352 fs_visitor
*) regpressure_analysis
;
353 BRW_ANALYSIS(performance_analysis
, brw::performance
,
354 fs_visitor
*) performance_analysis
;
356 /** Number of uniform variable components visited. */
359 /** Byte-offset for the next available spot in the scratch space buffer. */
360 unsigned last_scratch
;
363 * Array mapping UNIFORM register numbers to the pull parameter index,
364 * or -1 if this uniform register isn't being uploaded as a pull constant.
366 int *pull_constant_loc
;
369 * Array mapping UNIFORM register numbers to the push parameter index,
370 * or -1 if this uniform register isn't being uploaded as a push constant.
372 int *push_constant_loc
;
375 fs_reg group_size
[3];
380 fs_reg outputs
[VARYING_SLOT_MAX
];
381 fs_reg dual_src_output
;
382 int first_non_payload_grf
;
383 /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
387 fs_reg
*nir_ssa_values
;
388 fs_reg
*nir_system_values
;
393 /** Register numbers for thread payload fields. */
394 struct thread_payload
{
395 uint8_t subspan_coord_reg
[2];
396 uint8_t source_depth_reg
[2];
397 uint8_t source_w_reg
[2];
398 uint8_t aa_dest_stencil_reg
[2];
399 uint8_t dest_depth_reg
[2];
400 uint8_t sample_pos_reg
[2];
401 uint8_t sample_mask_in_reg
[2];
402 uint8_t barycentric_coord_reg
[BRW_BARYCENTRIC_MODE_COUNT
][2];
403 uint8_t local_invocation_id_reg
[2];
405 /** The number of thread payload registers the hardware will supply. */
409 bool source_depth_to_render_target
;
410 bool runtime_check_aads_emit
;
416 fs_reg delta_xy
[BRW_BARYCENTRIC_MODE_COUNT
];
417 fs_reg shader_start_time
;
418 fs_reg final_gs_vertex_count
;
419 fs_reg control_data_bits
;
420 fs_reg invocation_id
;
423 bool spilled_any_registers
;
425 const unsigned dispatch_width
; /**< 8, 16 or 32 */
426 unsigned max_dispatch_width
;
428 int shader_time_index
;
430 struct shader_stats shader_stats
;
435 fs_reg
prepare_alu_destination_and_sources(const brw::fs_builder
&bld
,
436 nir_alu_instr
*instr
,
440 void resolve_inot_sources(const brw::fs_builder
&bld
, nir_alu_instr
*instr
,
442 void lower_mul_dword_inst(fs_inst
*inst
, bblock_t
*block
);
443 void lower_mul_qword_inst(fs_inst
*inst
, bblock_t
*block
);
444 void lower_mulh_inst(fs_inst
*inst
, bblock_t
*block
);
446 unsigned workgroup_size() const;
450 * Return the flag register used in fragment shaders to keep track of live
451 * samples. On Gen7+ we use f1.0-f1.1 to allow discard jumps in SIMD32
452 * dispatch mode, while earlier generations are constrained to f0.1, which
453 * limits the dispatch width to SIMD16 for fragment shaders that use discard.
455 static inline unsigned
456 sample_mask_flag_subreg(const fs_visitor
*shader
)
458 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
459 return shader
->devinfo
->gen
>= 7 ? 2 : 1;
463 * The fragment shader code generator.
465 * Translates FS IR to actual i965 assembly code.
470 fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
472 struct brw_stage_prog_data
*prog_data
,
473 bool runtime_check_aads_emit
,
474 gl_shader_stage stage
);
477 void enable_debug(const char *shader_name
);
478 int generate_code(const cfg_t
*cfg
, int dispatch_width
,
479 struct shader_stats shader_stats
,
480 const brw::performance
&perf
,
481 struct brw_compile_stats
*stats
);
482 const unsigned *get_assembly();
485 void fire_fb_write(fs_inst
*inst
,
486 struct brw_reg payload
,
487 struct brw_reg implied_header
,
489 void generate_send(fs_inst
*inst
,
492 struct brw_reg ex_desc
,
493 struct brw_reg payload
,
494 struct brw_reg payload2
);
495 void generate_fb_write(fs_inst
*inst
, struct brw_reg payload
);
496 void generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
497 struct brw_reg payload
);
498 void generate_urb_read(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg payload
);
499 void generate_urb_write(fs_inst
*inst
, struct brw_reg payload
);
500 void generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
);
501 void generate_barrier(fs_inst
*inst
, struct brw_reg src
);
502 bool generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
503 struct brw_reg
*src
);
504 void generate_tex(fs_inst
*inst
, struct brw_reg dst
,
505 struct brw_reg surface_index
,
506 struct brw_reg sampler_index
);
507 void generate_get_buffer_size(fs_inst
*inst
, struct brw_reg dst
,
509 struct brw_reg surf_index
);
510 void generate_ddx(const fs_inst
*inst
,
511 struct brw_reg dst
, struct brw_reg src
);
512 void generate_ddy(const fs_inst
*inst
,
513 struct brw_reg dst
, struct brw_reg src
);
514 void generate_scratch_write(fs_inst
*inst
, struct brw_reg src
);
515 void generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
);
516 void generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
);
517 void generate_uniform_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
,
518 struct brw_reg index
,
519 struct brw_reg offset
);
520 void generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
522 struct brw_reg surf_index
,
523 struct brw_reg payload
);
524 void generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
526 struct brw_reg index
);
527 void generate_mov_dispatch_to_flags(fs_inst
*inst
);
529 void generate_pixel_interpolator_query(fs_inst
*inst
,
532 struct brw_reg msg_data
,
535 void generate_set_sample_id(fs_inst
*inst
,
538 struct brw_reg src1
);
540 void generate_discard_jump(fs_inst
*inst
);
542 void generate_pack_half_2x16_split(fs_inst
*inst
,
547 void generate_shader_time_add(fs_inst
*inst
,
548 struct brw_reg payload
,
549 struct brw_reg offset
,
550 struct brw_reg value
);
552 void generate_mov_indirect(fs_inst
*inst
,
555 struct brw_reg indirect_byte_offset
);
557 void generate_shuffle(fs_inst
*inst
,
562 void generate_quad_swizzle(const fs_inst
*inst
,
563 struct brw_reg dst
, struct brw_reg src
,
566 bool patch_discard_jumps_to_fb_writes();
568 const struct brw_compiler
*compiler
;
569 void *log_data
; /* Passed to compiler->*_log functions */
571 const struct gen_device_info
*devinfo
;
573 struct brw_codegen
*p
;
574 struct brw_stage_prog_data
* const prog_data
;
576 unsigned dispatch_width
; /**< 8, 16 or 32 */
578 exec_list discard_halt_patches
;
579 bool runtime_check_aads_emit
;
581 const char *shader_name
;
582 gl_shader_stage stage
;
588 fetch_payload_reg(const brw::fs_builder
&bld
, uint8_t regs
[2],
589 brw_reg_type type
= BRW_REGISTER_TYPE_F
)
594 if (bld
.dispatch_width() > 16) {
595 const fs_reg tmp
= bld
.vgrf(type
);
596 const brw::fs_builder hbld
= bld
.exec_all().group(16, 0);
597 const unsigned m
= bld
.dispatch_width() / hbld
.dispatch_width();
598 fs_reg
*const components
= new fs_reg
[m
];
600 for (unsigned g
= 0; g
< m
; g
++)
601 components
[g
] = retype(brw_vec8_grf(regs
[g
], 0), type
);
603 hbld
.LOAD_PAYLOAD(tmp
, components
, m
, 0);
609 return fs_reg(retype(brw_vec8_grf(regs
[0], 0), type
));
614 fetch_barycentric_reg(const brw::fs_builder
&bld
, uint8_t regs
[2])
619 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
620 const brw::fs_builder hbld
= bld
.exec_all().group(8, 0);
621 const unsigned m
= bld
.dispatch_width() / hbld
.dispatch_width();
622 fs_reg
*const components
= new fs_reg
[2 * m
];
624 for (unsigned c
= 0; c
< 2; c
++) {
625 for (unsigned g
= 0; g
< m
; g
++)
626 components
[c
* m
+ g
] = offset(brw_vec8_grf(regs
[g
/ 2], 0),
627 hbld
, c
+ 2 * (g
% 2));
630 hbld
.LOAD_PAYLOAD(tmp
, components
, 2 * m
, 0);
637 lower_src_modifiers(fs_visitor
*v
, bblock_t
*block
, fs_inst
*inst
, unsigned i
);
640 void shuffle_from_32bit_read(const brw::fs_builder
&bld
,
643 uint32_t first_component
,
644 uint32_t components
);
646 fs_reg
setup_imm_df(const brw::fs_builder
&bld
,
649 fs_reg
setup_imm_b(const brw::fs_builder
&bld
,
652 fs_reg
setup_imm_ub(const brw::fs_builder
&bld
,
655 enum brw_barycentric_mode
brw_barycentric_mode(enum glsl_interp_mode mode
,
656 nir_intrinsic_op op
);
658 uint32_t brw_fb_write_msg_control(const fs_inst
*inst
,
659 const struct brw_wm_prog_data
*prog_data
);
661 void brw_compute_urb_setup_index(struct brw_wm_prog_data
*wm_prog_data
);
663 #endif /* BRW_FS_H */