2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
34 static enum brw_reg_file
35 brw_file_from_reg(fs_reg
*reg
)
39 return BRW_ARCHITECTURE_REGISTER_FILE
;
42 return BRW_GENERAL_REGISTER_FILE
;
44 return BRW_MESSAGE_REGISTER_FILE
;
46 return BRW_IMMEDIATE_VALUE
;
50 unreachable("not reached");
52 return BRW_ARCHITECTURE_REGISTER_FILE
;
56 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
57 fs_reg
*reg
, bool compressed
)
59 struct brw_reg brw_reg
;
63 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
66 if (reg
->stride
== 0) {
67 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 /* From the Haswell PRM:
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
75 * The maximum width value that could satisfy this restriction is:
77 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
84 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
93 const unsigned width
= MIN2(reg_width
, phys_width
);
94 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
95 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
97 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
98 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
99 * "Each DF (Double Float) operand uses an element size of 4 rather
100 * than 8 and all regioning parameters are twice what the values
101 * would be based on the true element size: ExecSize, Width,
102 * HorzStride, and VertStride. Each DF operand uses a pair of
103 * channels and all masking and swizzing should be adjusted
106 * From the IvyBridge PRM (Special Requirements for Handling Double
107 * Precision Data Types, page 71):
108 * "In Align1 mode, all regioning parameters like stride, execution
109 * size, and width must use the syntax of a pair of packed
110 * floats. The offsets for these data types must be 64-bit
111 * aligned. The execution size and regioning parameters are in terms
114 * Summarized: when handling DF-typed arguments, ExecSize,
115 * VertStride, and Width must be doubled.
117 * It applies to BayTrail too.
119 if (type_sz(reg
->type
) == 8) {
121 if (brw_reg
.vstride
> 0)
123 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
126 /* When converting from DF->F, we set the destination stride to 2
127 * because each d2f conversion implicitly writes 2 floats, being
128 * the first one the converted value. IVB/BYT actually writes two
129 * F components per SIMD channel, and every other component is
130 * filled with garbage.
132 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
133 type_sz(inst
->dst
.type
) < 8) {
134 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
140 brw_reg
= retype(brw_reg
, reg
->type
);
141 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
142 brw_reg
.abs
= reg
->abs
;
143 brw_reg
.negate
= reg
->negate
;
148 assert(reg
->offset
== 0);
149 brw_reg
= reg
->as_brw_reg();
152 /* Probably unused. */
153 brw_reg
= brw_null_reg();
157 unreachable("not reached");
160 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
161 * region, but on IVB and BYT DF regions must be programmed in terms of
162 * floats. A <0,2,1> region accomplishes this.
164 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
165 type_sz(reg
->type
) == 8 &&
166 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
167 brw_reg
.width
== BRW_WIDTH_1
&&
168 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
169 brw_reg
.width
= BRW_WIDTH_2
;
170 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
176 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
178 struct brw_stage_prog_data
*prog_data
,
179 unsigned promoted_constants
,
180 bool runtime_check_aads_emit
,
181 gl_shader_stage stage
)
183 : compiler(compiler
), log_data(log_data
),
184 devinfo(compiler
->devinfo
),
185 prog_data(prog_data
),
186 promoted_constants(promoted_constants
),
187 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
188 stage(stage
), mem_ctx(mem_ctx
)
190 p
= rzalloc(mem_ctx
, struct brw_codegen
);
191 brw_init_codegen(devinfo
, p
, mem_ctx
);
193 /* In the FS code generator, we are very careful to ensure that we always
194 * set the right execution size so we don't need the EU code to "help" us
195 * by trying to infer it. Sometimes, it infers the wrong thing.
197 p
->automatic_exec_sizes
= false;
200 fs_generator::~fs_generator()
204 class ip_record
: public exec_node
{
206 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
217 fs_generator::patch_discard_jumps_to_fb_writes()
219 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
222 int scale
= brw_jump_scale(p
->devinfo
);
224 /* There is a somewhat strange undocumented requirement of using
225 * HALT, according to the simulator. If some channel has HALTed to
226 * a particular UIP, then by the end of the program, every channel
227 * must have HALTed to that UIP. Furthermore, the tracking is a
228 * stack, so you can't do the final halt of a UIP after starting
229 * halting to a new UIP.
231 * Symptoms of not emitting this instruction on actual hardware
232 * included GPU hangs and sparkly rendering on the piglit discard
235 brw_inst
*last_halt
= gen6_HALT(p
);
236 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
237 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
241 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
242 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
244 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
245 /* HALT takes a half-instruction distance from the pre-incremented IP. */
246 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
249 this->discard_halt_patches
.make_empty();
254 fs_generator::fire_fb_write(fs_inst
*inst
,
255 struct brw_reg payload
,
256 struct brw_reg implied_header
,
259 uint32_t msg_control
;
261 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
263 if (devinfo
->gen
< 6) {
264 brw_push_insn_state(p
);
265 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
266 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
267 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
268 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
269 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
270 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
271 brw_pop_insn_state(p
);
274 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
275 assert(inst
->group
== 0 && inst
->exec_size
== 16);
276 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
278 } else if (prog_data
->dual_src_blend
) {
279 assert(inst
->exec_size
== 8);
281 if (inst
->group
% 16 == 0)
282 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
283 else if (inst
->group
% 16 == 8)
284 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
286 unreachable("Invalid dual-source FB write instruction group");
289 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
291 if (inst
->exec_size
== 16)
292 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
293 else if (inst
->exec_size
== 8)
294 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
296 unreachable("Invalid FB write execution size");
299 /* We assume render targets start at 0, because headerless FB write
300 * messages set "Render Target Index" to 0. Using a different binding
301 * table index would make it impossible to use headerless messages.
303 const uint32_t surf_index
= inst
->target
;
305 brw_inst
*insn
= brw_fb_WRITE(p
,
307 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
314 inst
->header_size
!= 0);
316 if (devinfo
->gen
>= 6)
317 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
319 brw_mark_surface_used(&prog_data
->base
, surf_index
);
323 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
325 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
326 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
329 const struct brw_reg implied_header
=
330 devinfo
->gen
< 6 ? payload
: brw_null_reg();
332 if (inst
->base_mrf
>= 0)
333 payload
= brw_message_reg(inst
->base_mrf
);
335 if (!runtime_check_aads_emit
) {
336 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
338 /* This can only happen in gen < 6 */
339 assert(devinfo
->gen
< 6);
341 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
343 /* Check runtime bit to detect if we have to send AA data or not */
344 brw_push_insn_state(p
);
345 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
346 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
349 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
351 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
353 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
354 brw_pop_insn_state(p
);
356 /* Don't send AA data */
357 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
359 brw_land_fwd_jump(p
, jmp
);
360 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
365 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
366 struct brw_reg payload
)
368 assert(inst
->size_written
% REG_SIZE
== 0);
369 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
370 /* We assume that render targets start at binding table index 0. */
371 const unsigned surf_index
= inst
->target
;
373 gen9_fb_READ(p
, dst
, payload
, surf_index
,
374 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
375 prog_data
->persample_dispatch
);
377 brw_mark_surface_used(&prog_data
->base
, surf_index
);
381 fs_generator::generate_mov_indirect(fs_inst
*inst
,
384 struct brw_reg indirect_byte_offset
)
386 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
387 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
388 assert(!reg
.abs
&& !reg
.negate
);
389 assert(reg
.type
== dst
.type
);
391 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
393 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
394 imm_byte_offset
+= indirect_byte_offset
.ud
;
396 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
397 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
398 brw_MOV(p
, dst
, reg
);
400 /* Prior to Broadwell, there are only 8 address registers. */
401 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
403 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
404 struct brw_reg addr
= vec8(brw_address_reg(0));
406 /* The destination stride of an instruction (in bytes) must be greater
407 * than or equal to the size of the rest of the instruction. Since the
408 * address register is of type UW, we can't use a D-type instruction.
409 * In order to get around this, re retype to UW and use a stride.
411 indirect_byte_offset
=
412 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
414 /* There are a number of reasons why we don't use the base offset here.
415 * One reason is that the field is only 9 bits which means we can only
416 * use it to access the first 16 GRFs. Also, from the Haswell PRM
417 * section "Register Region Restrictions":
419 * "The lower bits of the AddressImmediate must not overflow to
420 * change the register address. The lower 5 bits of Address
421 * Immediate when added to lower 5 bits of address register gives
422 * the sub-register offset. The upper bits of Address Immediate
423 * when added to upper bits of address register gives the register
424 * address. Any overflow from sub-register offset is dropped."
426 * Since the indirect may cause us to cross a register boundary, this
427 * makes the base offset almost useless. We could try and do something
428 * clever where we use a actual base offset if base_offset % 32 == 0 but
429 * that would mean we were generating different code depending on the
430 * base offset. Instead, for the sake of consistency, we'll just do the
431 * add ourselves. This restriction is only listed in the Haswell PRM
432 * but empirical testing indicates that it applies on all older
433 * generations and is lifted on Broadwell.
435 * In the end, while base_offset is nice to look at in the generated
436 * code, using it saves us 0 instructions and would require quite a bit
437 * of case-by-case work. It's just not worth it.
439 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
441 if (type_sz(reg
.type
) > 4 &&
442 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
443 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
444 !devinfo
->has_64bit_types
)) {
445 /* IVB has an issue (which we found empirically) where it reads two
446 * address register components per channel for indirectly addressed
449 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
451 * "When source or destination datatype is 64b or operation is
452 * integer DWord multiply, indirect addressing must not be used."
454 * To work around both of these, we do two integer MOVs insead of one
455 * 64-bit MOV. Because no double value should ever cross a register
456 * boundary, it's safe to use the immediate offset in the indirect
457 * here to handle adding 4 bytes to the offset and avoid the extra
458 * ADD to the register file.
460 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
461 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
462 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
463 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
465 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
467 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
469 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
470 !inst
->get_next()->is_tail_sentinel() &&
471 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
472 /* From the Sandybridge PRM:
474 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
475 * instruction that “indexed/indirect” source AND is followed
476 * by a send, the instruction requires a “Switch”. This is to
477 * avoid race condition where send may dispatch before MRF is
480 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
487 fs_generator::generate_shuffle(fs_inst
*inst
,
492 /* Ivy bridge has some strange behavior that makes this a real pain to
493 * implement for 64-bit values so we just don't bother.
495 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
497 /* Because we're using the address register, we're limited to 8-wide
498 * execution on gen7. On gen8, we're limited to 16-wide by the address
499 * register file and 8-wide for 64-bit types. We could try and make this
500 * instruction splittable higher up in the compiler but that gets weird
501 * because it reads all of the channels regardless of execution size. It's
502 * easier just to split it here.
504 const unsigned lower_width
=
505 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
506 8 : MIN2(16, inst
->exec_size
);
508 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
509 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
510 brw_set_default_group(p
, group
);
512 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
513 idx
.file
== BRW_IMMEDIATE_VALUE
) {
514 /* Trivial, the source is already uniform or the index is a constant.
515 * We will typically not get here if the optimizer is doing its job,
516 * but asserting would be mean.
518 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
519 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
521 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
522 struct brw_reg addr
= vec8(brw_address_reg(0));
524 struct brw_reg group_idx
= suboffset(idx
, group
);
526 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
527 /* Things get grumpy if the register is too wide. */
532 assert(type_sz(group_idx
.type
) <= 4);
533 if (type_sz(group_idx
.type
) == 4) {
534 /* The destination stride of an instruction (in bytes) must be
535 * greater than or equal to the size of the rest of the
536 * instruction. Since the address register is of type UW, we
537 * can't use a D-type instruction. In order to get around this,
538 * re retype to UW and use a stride.
540 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
543 /* Take into account the component size and horizontal stride. */
544 assert(src
.vstride
== src
.hstride
+ src
.width
);
545 brw_SHL(p
, addr
, group_idx
,
546 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
549 /* Add on the register start offset */
550 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
552 if (type_sz(src
.type
) > 4 &&
553 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
554 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
555 /* IVB has an issue (which we found empirically) where it reads
556 * two address register components per channel for indirectly
557 * addressed 64-bit sources.
559 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
561 * "When source or destination datatype is 64b or operation is
562 * integer DWord multiply, indirect addressing must not be
565 * To work around both of these, we do two integer MOVs insead of
566 * one 64-bit MOV. Because no double value should ever cross a
567 * register boundary, it's safe to use the immediate offset in the
568 * indirect here to handle adding 4 bytes to the offset and avoid
569 * the extra ADD to the register file.
571 struct brw_reg gdst
= suboffset(dst
, group
);
572 struct brw_reg dst_d
= retype(spread(gdst
, 2),
573 BRW_REGISTER_TYPE_D
);
575 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
576 brw_MOV(p
, byte_offset(dst_d
, 4),
577 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
579 brw_MOV(p
, suboffset(dst
, group
),
580 retype(brw_VxH_indirect(0, 0), src
.type
));
587 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
588 struct brw_reg dst
, struct brw_reg src
,
591 /* Requires a quad. */
592 assert(inst
->exec_size
>= 4);
594 if (src
.file
== BRW_IMMEDIATE_VALUE
||
595 has_scalar_region(src
)) {
596 /* The value is uniform across all channels */
597 brw_MOV(p
, dst
, src
);
599 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
600 /* This only works on 8-wide 32-bit values */
601 assert(inst
->exec_size
== 8);
602 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
603 assert(src
.vstride
== src
.width
+ 1);
604 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
605 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
606 swiz_src
.swizzle
= swiz
;
607 brw_MOV(p
, dst
, swiz_src
);
610 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
611 assert(src
.vstride
== src
.width
+ 1);
612 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
615 case BRW_SWIZZLE_XXXX
:
616 case BRW_SWIZZLE_YYYY
:
617 case BRW_SWIZZLE_ZZZZ
:
618 case BRW_SWIZZLE_WWWW
:
619 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
622 case BRW_SWIZZLE_XXZZ
:
623 case BRW_SWIZZLE_YYWW
:
624 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
627 case BRW_SWIZZLE_XYXY
:
628 case BRW_SWIZZLE_ZWZW
:
629 assert(inst
->exec_size
== 4);
630 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
634 assert(inst
->force_writemask_all
);
635 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
637 for (unsigned c
= 0; c
< 4; c
++) {
638 brw_inst
*insn
= brw_MOV(
639 p
, stride(suboffset(dst
, c
),
640 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
641 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
643 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
644 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
653 fs_generator::generate_urb_read(fs_inst
*inst
,
655 struct brw_reg header
)
657 assert(inst
->size_written
% REG_SIZE
== 0);
658 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
659 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
661 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
662 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
663 brw_set_src0(p
, send
, header
);
664 brw_set_src1(p
, send
, brw_imm_ud(0u));
666 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
667 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
669 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
670 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
672 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
673 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
674 brw_inst_set_header_present(p
->devinfo
, send
, true);
675 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
679 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
683 /* WaClearTDRRegBeforeEOTForNonPS.
685 * WA: Clear tdr register before send EOT in all non-PS shader kernels
687 * mov(8) tdr0:ud 0x0:ud {NoMask}"
689 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
690 brw_push_insn_state(p
);
691 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
692 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
693 brw_pop_insn_state(p
);
696 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
698 brw_set_dest(p
, insn
, brw_null_reg());
699 brw_set_src0(p
, insn
, payload
);
700 brw_set_src1(p
, insn
, brw_imm_ud(0u));
702 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
703 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
705 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
706 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
707 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
709 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
710 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
711 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
713 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
714 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
715 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
716 brw_inst_set_header_present(p
->devinfo
, insn
, true);
717 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
721 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
723 struct brw_inst
*insn
;
725 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
727 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
728 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
729 brw_set_src1(p
, insn
, brw_imm_ud(0u));
731 /* Terminate a compute shader by sending a message to the thread spawner.
733 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
734 brw_inst_set_mlen(devinfo
, insn
, 1);
735 brw_inst_set_rlen(devinfo
, insn
, 0);
736 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
737 brw_inst_set_header_present(devinfo
, insn
, false);
739 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
740 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
742 /* Note that even though the thread has a URB resource associated with it,
743 * we set the "do not dereference URB" bit, because the URB resource is
744 * managed by the fixed-function unit, so it will free it automatically.
746 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
748 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
752 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
759 fs_generator::generate_linterp(fs_inst
*inst
,
760 struct brw_reg dst
, struct brw_reg
*src
)
764 * -----------------------------------
765 * | src1+0 | src1+1 | src1+2 | src1+3 |
766 * |-----------------------------------|
767 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
768 * -----------------------------------
770 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
772 * -----------------------------------
773 * | src1+0 | src1+1 | src1+2 | src1+3 |
774 * |-----------------------------------|
775 * |(x0, x1)|(y0, y1)| | | in SIMD8
776 * |-----------------------------------|
777 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
778 * -----------------------------------
780 * See also: emit_interpolation_setup_gen4().
782 struct brw_reg delta_x
= src
[0];
783 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
784 struct brw_reg interp
= src
[1];
787 if (devinfo
->gen
>= 11) {
788 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_NF
);
789 struct brw_reg dwP
= suboffset(interp
, 0);
790 struct brw_reg dwQ
= suboffset(interp
, 1);
791 struct brw_reg dwR
= suboffset(interp
, 3);
793 brw_push_insn_state(p
);
794 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
796 if (inst
->exec_size
== 8) {
797 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
798 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_y
, 0), dwQ
);
800 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
802 /* brw_set_default_saturate() is called before emitting instructions,
803 * so the saturate bit is set in each instruction, so we need to unset
804 * it on the first instruction of each pair.
806 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
808 brw_set_default_group(p
, inst
->group
);
809 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
810 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_x
, 1), dwQ
);
812 brw_set_default_group(p
, inst
->group
+ 8);
813 i
[2] = brw_MAD(p
, acc
, dwR
, offset(delta_y
, 0), dwP
);
814 i
[3] = brw_MAD(p
, offset(dst
, 1), acc
, offset(delta_y
, 1), dwQ
);
816 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
817 brw_inst_set_cond_modifier(p
->devinfo
, i
[3], inst
->conditional_mod
);
819 /* brw_set_default_saturate() is called before emitting instructions,
820 * so the saturate bit is set in each instruction, so we need to unset
821 * it on the first instruction of each pair.
823 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
824 brw_inst_set_saturate(p
->devinfo
, i
[2], false);
827 brw_pop_insn_state(p
);
830 } else if (devinfo
->has_pln
) {
831 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
832 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
834 * "[DevSNB]:<src1> must be even register aligned.
836 * This restriction is lifted on Ivy Bridge.
838 * This means that we need to split PLN into LINE+MAC on-the-fly.
839 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
840 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
841 * coordinate registers are laid out differently so we leave it as a
842 * SIMD16 instruction.
844 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
845 assert(inst
->group
% 16 == 0);
847 brw_push_insn_state(p
);
848 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
850 /* Thanks to two accumulators, we can emit all the LINEs and then all
851 * the MACs. This improves parallelism a bit.
853 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
854 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
855 offset(delta_x
, g
* 2));
856 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
858 /* LINE writes the accumulator automatically on gen4-5. On Sandy
859 * Bridge and later, we have to explicitly enable it.
861 if (devinfo
->gen
>= 6)
862 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
864 /* brw_set_default_saturate() is called before emitting
865 * instructions, so the saturate bit is set in each instruction,
866 * so we need to unset it on the LINE instructions.
868 brw_inst_set_saturate(p
->devinfo
, line
, false);
871 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
872 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
873 offset(delta_x
, g
* 2 + 1));
874 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
875 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
878 brw_pop_insn_state(p
);
882 brw_PLN(p
, dst
, interp
, delta_x
);
887 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
888 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
890 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
892 /* brw_set_default_saturate() is called before emitting instructions, so
893 * the saturate bit is set in each instruction, so we need to unset it on
894 * the first instruction.
896 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
903 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
906 struct brw_reg surf_index
)
908 assert(devinfo
->gen
>= 7);
909 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
914 switch (inst
->exec_size
) {
916 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
919 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
922 unreachable("Invalid width for texture instruction");
925 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
931 retype(dst
, BRW_REGISTER_TYPE_UW
),
936 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
937 rlen
, /* response length */
939 inst
->header_size
> 0,
941 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
943 brw_mark_surface_used(prog_data
, surf_index
.ud
);
947 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
948 struct brw_reg surface_index
,
949 struct brw_reg sampler_index
)
951 assert(inst
->size_written
% REG_SIZE
== 0);
954 uint32_t return_format
;
955 bool is_combined_send
= inst
->eot
;
957 /* Sampler EOT message of less than the dispatch width would kill the
958 * thread prematurely.
960 assert(!is_combined_send
|| inst
->exec_size
== dispatch_width
);
963 case BRW_REGISTER_TYPE_D
:
964 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
966 case BRW_REGISTER_TYPE_UD
:
967 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
970 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
974 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
975 * is set as part of the message descriptor. On gen4, the PRM seems to
976 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
977 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
978 * gone from the message descriptor entirely and you just get UINT32 all
979 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
980 * just stomp it to UINT32 all the time.
982 if (inst
->opcode
== SHADER_OPCODE_TXS
)
983 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
985 switch (inst
->exec_size
) {
987 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
990 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
993 unreachable("Invalid width for texture instruction");
996 if (devinfo
->gen
>= 5) {
997 switch (inst
->opcode
) {
998 case SHADER_OPCODE_TEX
:
999 if (inst
->shadow_compare
) {
1000 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
1002 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
1006 if (inst
->shadow_compare
) {
1007 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
1009 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
1012 case SHADER_OPCODE_TXL
:
1013 if (inst
->shadow_compare
) {
1014 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
1016 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
1019 case SHADER_OPCODE_TXL_LZ
:
1020 assert(devinfo
->gen
>= 9);
1021 if (inst
->shadow_compare
) {
1022 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
;
1024 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
1027 case SHADER_OPCODE_TXS
:
1028 case SHADER_OPCODE_IMAGE_SIZE
:
1029 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
1031 case SHADER_OPCODE_TXD
:
1032 if (inst
->shadow_compare
) {
1033 /* Gen7.5+. Otherwise, lowered in NIR */
1034 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
1035 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
1037 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1040 case SHADER_OPCODE_TXF
:
1041 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1043 case SHADER_OPCODE_TXF_LZ
:
1044 assert(devinfo
->gen
>= 9);
1045 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
1047 case SHADER_OPCODE_TXF_CMS_W
:
1048 assert(devinfo
->gen
>= 9);
1049 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
1051 case SHADER_OPCODE_TXF_CMS
:
1052 if (devinfo
->gen
>= 7)
1053 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
1055 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1057 case SHADER_OPCODE_TXF_UMS
:
1058 assert(devinfo
->gen
>= 7);
1059 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
1061 case SHADER_OPCODE_TXF_MCS
:
1062 assert(devinfo
->gen
>= 7);
1063 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
1065 case SHADER_OPCODE_LOD
:
1066 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1068 case SHADER_OPCODE_TG4
:
1069 if (inst
->shadow_compare
) {
1070 assert(devinfo
->gen
>= 7);
1071 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
1073 assert(devinfo
->gen
>= 6);
1074 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1077 case SHADER_OPCODE_TG4_OFFSET
:
1078 assert(devinfo
->gen
>= 7);
1079 if (inst
->shadow_compare
) {
1080 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
1082 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
1085 case SHADER_OPCODE_SAMPLEINFO
:
1086 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1089 unreachable("not reached");
1092 switch (inst
->opcode
) {
1093 case SHADER_OPCODE_TEX
:
1094 /* Note that G45 and older determines shadow compare and dispatch width
1095 * from message length for most messages.
1097 if (inst
->exec_size
== 8) {
1098 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1099 if (inst
->shadow_compare
) {
1100 assert(inst
->mlen
== 6);
1102 assert(inst
->mlen
<= 4);
1105 if (inst
->shadow_compare
) {
1106 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1107 assert(inst
->mlen
== 9);
1109 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1110 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1115 if (inst
->shadow_compare
) {
1116 assert(inst
->exec_size
== 8);
1117 assert(inst
->mlen
== 6);
1118 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1120 assert(inst
->mlen
== 9);
1121 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1122 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1125 case SHADER_OPCODE_TXL
:
1126 if (inst
->shadow_compare
) {
1127 assert(inst
->exec_size
== 8);
1128 assert(inst
->mlen
== 6);
1129 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1131 assert(inst
->mlen
== 9);
1132 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1133 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1136 case SHADER_OPCODE_TXD
:
1137 /* There is no sample_d_c message; comparisons are done manually */
1138 assert(inst
->exec_size
== 8);
1139 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1140 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1142 case SHADER_OPCODE_TXF
:
1143 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1144 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1145 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1147 case SHADER_OPCODE_TXS
:
1148 assert(inst
->mlen
== 3);
1149 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1150 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1153 unreachable("not reached");
1156 assert(msg_type
!= -1);
1158 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1162 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
1163 src
.file
== BRW_GENERAL_REGISTER_FILE
);
1165 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1167 /* Load the message header if present. If there's a texture offset,
1168 * we need to set it up explicitly and load the offset bitfield.
1169 * Otherwise, we can use an implied move from g0 to the first message reg.
1171 if (inst
->header_size
!= 0 && devinfo
->gen
< 7) {
1172 if (devinfo
->gen
< 6 && !inst
->offset
) {
1173 /* Set up an implied move from g0 to the MRF. */
1174 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1176 assert(inst
->base_mrf
!= -1);
1177 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1179 brw_push_insn_state(p
);
1180 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1181 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1182 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1183 /* Explicitly set up the message header by copying g0 to the MRF. */
1184 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1186 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1188 /* Set the offset bits in DWord 2. */
1189 brw_MOV(p
, get_element_ud(header_reg
, 2),
1190 brw_imm_ud(inst
->offset
));
1193 brw_pop_insn_state(p
);
1197 uint32_t base_binding_table_index
;
1198 switch (inst
->opcode
) {
1199 case SHADER_OPCODE_TG4
:
1200 case SHADER_OPCODE_TG4_OFFSET
:
1201 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1203 case SHADER_OPCODE_IMAGE_SIZE
:
1204 base_binding_table_index
= prog_data
->binding_table
.image_start
;
1207 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1211 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
1212 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
1213 uint32_t surface
= surface_index
.ud
;
1214 uint32_t sampler
= sampler_index
.ud
;
1217 retype(dst
, BRW_REGISTER_TYPE_UW
),
1220 surface
+ base_binding_table_index
,
1223 inst
->size_written
/ REG_SIZE
,
1225 inst
->header_size
!= 0,
1229 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
1231 /* Non-const sampler index */
1233 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1234 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
1235 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
1237 brw_push_insn_state(p
);
1238 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1239 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1240 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1242 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
1243 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
1245 if (sampler_reg
.file
== BRW_IMMEDIATE_VALUE
) {
1246 brw_OR(p
, addr
, surface_reg
, brw_imm_ud(sampler_reg
.ud
<< 8));
1248 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
1249 brw_OR(p
, addr
, addr
, surface_reg
);
1252 if (base_binding_table_index
)
1253 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
1254 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
1256 brw_pop_insn_state(p
);
1258 /* dst = send(offset, a0.0 | <descriptor>) */
1259 brw_send_indirect_message(
1260 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
,
1261 brw_message_desc(devinfo
, inst
->mlen
, inst
->size_written
/ REG_SIZE
,
1262 inst
->header_size
) |
1263 brw_sampler_desc(devinfo
,
1270 /* visitor knows more than we do about the surface limit required,
1271 * so has already done marking.
1275 if (is_combined_send
) {
1276 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
1277 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
1282 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1285 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1287 * Ideally, we want to produce:
1290 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1291 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1292 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1293 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1294 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1295 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1296 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1297 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1299 * and add another set of two more subspans if in 16-pixel dispatch mode.
1301 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1302 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1303 * pair. But the ideal approximation may impose a huge performance cost on
1304 * sample_d. On at least Haswell, sample_d instruction does some
1305 * optimizations if the same LOD is used for all pixels in the subspan.
1307 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1308 * appropriate swizzling.
1311 fs_generator::generate_ddx(const fs_inst
*inst
,
1312 struct brw_reg dst
, struct brw_reg src
)
1314 unsigned vstride
, width
;
1316 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1317 /* produce accurate derivatives */
1318 vstride
= BRW_VERTICAL_STRIDE_2
;
1319 width
= BRW_WIDTH_2
;
1321 /* replicate the derivative at the top-left pixel to other pixels */
1322 vstride
= BRW_VERTICAL_STRIDE_4
;
1323 width
= BRW_WIDTH_4
;
1326 struct brw_reg src0
= src
;
1327 struct brw_reg src1
= src
;
1329 src0
.subnr
= sizeof(float);
1330 src0
.vstride
= vstride
;
1332 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1333 src1
.vstride
= vstride
;
1335 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1337 brw_ADD(p
, dst
, src0
, negate(src1
));
1340 /* The negate_value boolean is used to negate the derivative computation for
1341 * FBOs, since they place the origin at the upper left instead of the lower
1345 fs_generator::generate_ddy(const fs_inst
*inst
,
1346 struct brw_reg dst
, struct brw_reg src
)
1348 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1349 /* produce accurate derivatives */
1350 if (devinfo
->gen
>= 11) {
1351 src
= stride(src
, 0, 2, 1);
1352 struct brw_reg src_0
= byte_offset(src
, 0 * sizeof(float));
1353 struct brw_reg src_2
= byte_offset(src
, 2 * sizeof(float));
1354 struct brw_reg src_4
= byte_offset(src
, 4 * sizeof(float));
1355 struct brw_reg src_6
= byte_offset(src
, 6 * sizeof(float));
1356 struct brw_reg src_8
= byte_offset(src
, 8 * sizeof(float));
1357 struct brw_reg src_10
= byte_offset(src
, 10 * sizeof(float));
1358 struct brw_reg src_12
= byte_offset(src
, 12 * sizeof(float));
1359 struct brw_reg src_14
= byte_offset(src
, 14 * sizeof(float));
1361 struct brw_reg dst_0
= byte_offset(dst
, 0 * sizeof(float));
1362 struct brw_reg dst_4
= byte_offset(dst
, 4 * sizeof(float));
1363 struct brw_reg dst_8
= byte_offset(dst
, 8 * sizeof(float));
1364 struct brw_reg dst_12
= byte_offset(dst
, 12 * sizeof(float));
1366 brw_push_insn_state(p
);
1367 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1369 brw_ADD(p
, dst_0
, negate(src_0
), src_2
);
1370 brw_ADD(p
, dst_4
, negate(src_4
), src_6
);
1372 if (inst
->exec_size
== 16) {
1373 brw_ADD(p
, dst_8
, negate(src_8
), src_10
);
1374 brw_ADD(p
, dst_12
, negate(src_12
), src_14
);
1377 brw_pop_insn_state(p
);
1379 struct brw_reg src0
= stride(src
, 4, 4, 1);
1380 struct brw_reg src1
= stride(src
, 4, 4, 1);
1381 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1382 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1384 brw_push_insn_state(p
);
1385 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1386 brw_ADD(p
, dst
, negate(src0
), src1
);
1387 brw_pop_insn_state(p
);
1390 /* replicate the derivative at the top-left pixel to other pixels */
1391 struct brw_reg src0
= stride(src
, 4, 4, 0);
1392 struct brw_reg src1
= stride(src
, 4, 4, 0);
1393 src0
.subnr
= 0 * sizeof(float);
1394 src1
.subnr
= 2 * sizeof(float);
1396 brw_ADD(p
, dst
, negate(src0
), src1
);
1401 fs_generator::generate_discard_jump(fs_inst
*)
1403 assert(devinfo
->gen
>= 6);
1405 /* This HALT will be patched up at FB write time to point UIP at the end of
1406 * the program, and at brw_uip_jip() JIP will be set to the end of the
1407 * current block (or the program).
1409 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1414 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1416 /* The 32-wide messages only respect the first 16-wide half of the channel
1417 * enable signals which are replicated identically for the second group of
1418 * 16 channels, so we cannot use them unless the write is marked
1419 * force_writemask_all.
1421 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1422 MIN2(16, inst
->exec_size
);
1423 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1424 assert(inst
->mlen
!= 0);
1426 brw_push_insn_state(p
);
1427 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1428 brw_set_default_compression(p
, lower_size
> 8);
1430 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1431 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1433 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1434 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1436 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1438 inst
->offset
+ block_size
* REG_SIZE
* i
);
1441 brw_pop_insn_state(p
);
1445 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1447 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1448 assert(inst
->mlen
!= 0);
1450 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1451 inst
->exec_size
/ 8, inst
->offset
);
1455 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1457 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1459 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1463 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1465 struct brw_reg index
,
1466 struct brw_reg offset
)
1468 assert(type_sz(dst
.type
) == 4);
1469 assert(inst
->mlen
!= 0);
1471 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1472 index
.type
== BRW_REGISTER_TYPE_UD
);
1473 uint32_t surf_index
= index
.ud
;
1475 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1476 offset
.type
== BRW_REGISTER_TYPE_UD
);
1477 uint32_t read_offset
= offset
.ud
;
1479 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1480 read_offset
, surf_index
);
1484 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1486 struct brw_reg index
,
1487 struct brw_reg payload
)
1489 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1490 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1491 assert(type_sz(dst
.type
) == 4);
1493 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1494 const uint32_t surf_index
= index
.ud
;
1496 brw_push_insn_state(p
);
1497 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1498 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1499 brw_pop_insn_state(p
);
1501 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1502 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1503 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1504 brw_set_desc(p
, send
,
1505 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1507 brw_dp_read_desc(devinfo
, surf_index
,
1508 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1509 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1510 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1513 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1515 brw_push_insn_state(p
);
1516 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1518 /* a0.0 = surf_index & 0xff */
1519 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1520 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1521 brw_set_dest(p
, insn_and
, addr
);
1522 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1523 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1525 /* dst = send(payload, a0.0 | <descriptor>) */
1526 brw_send_indirect_message(
1527 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1528 retype(dst
, BRW_REGISTER_TYPE_UD
),
1529 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1530 brw_message_desc(devinfo
, 1,
1531 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1532 brw_dp_read_desc(devinfo
, 0 /* surface */,
1533 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1534 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1535 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1537 brw_pop_insn_state(p
);
1542 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1544 struct brw_reg index
)
1546 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1547 assert(inst
->header_size
!= 0);
1550 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1551 index
.type
== BRW_REGISTER_TYPE_UD
);
1552 uint32_t surf_index
= index
.ud
;
1554 uint32_t simd_mode
, rlen
, msg_type
;
1555 if (inst
->exec_size
== 16) {
1556 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1559 assert(inst
->exec_size
== 8);
1560 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1564 if (devinfo
->gen
>= 5)
1565 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1567 /* We always use the SIMD16 message so that we only have to load U, and
1570 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1571 assert(inst
->mlen
== 3);
1572 assert(inst
->size_written
== 8 * REG_SIZE
);
1574 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1577 struct brw_reg header
= brw_vec8_grf(0, 0);
1578 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1580 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1581 brw_inst_set_compression(devinfo
, send
, false);
1582 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1583 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1584 brw_set_src0(p
, send
, header
);
1585 if (devinfo
->gen
< 6)
1586 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1588 /* Our surface is set up as floats, regardless of what actual data is
1591 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1592 brw_set_desc(p
, send
,
1593 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1594 brw_sampler_desc(devinfo
, surf_index
,
1595 0, /* sampler (unused) */
1596 msg_type
, simd_mode
, return_format
));
1600 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1602 struct brw_reg index
,
1603 struct brw_reg offset
)
1605 assert(devinfo
->gen
>= 7);
1606 /* Varying-offset pull constant loads are treated as a normal expression on
1607 * gen7, so the fact that it's a send message is hidden at the IR level.
1609 assert(inst
->header_size
== 0);
1611 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1613 uint32_t simd_mode
, rlen
;
1614 if (inst
->exec_size
== 16) {
1616 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1618 assert(inst
->exec_size
== 8);
1620 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1623 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1625 uint32_t surf_index
= index
.ud
;
1627 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1628 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1629 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1630 brw_set_src0(p
, send
, offset
);
1631 brw_set_desc(p
, send
,
1632 brw_message_desc(devinfo
, inst
->mlen
, rlen
, false) |
1633 brw_sampler_desc(devinfo
, surf_index
,
1634 0, /* LD message ignores sampler unit */
1635 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1640 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1642 brw_push_insn_state(p
);
1643 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1645 /* a0.0 = surf_index & 0xff */
1646 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1647 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1648 brw_set_dest(p
, insn_and
, addr
);
1649 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1650 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1652 brw_pop_insn_state(p
);
1654 /* dst = send(offset, a0.0 | <descriptor>) */
1655 brw_send_indirect_message(
1656 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1658 brw_message_desc(devinfo
, inst
->mlen
, rlen
, false) |
1659 brw_sampler_desc(devinfo
,
1662 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1669 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1672 struct brw_reg msg_data
,
1675 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1676 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1677 assert(inst
->size_written
% REG_SIZE
== 0);
1679 brw_pixel_interpolator_query(p
,
1680 retype(dst
, BRW_REGISTER_TYPE_UW
),
1681 /* If we don't have a payload, what we send doesn't matter */
1682 has_payload
? src
: brw_vec8_grf(0, 0),
1683 inst
->pi_noperspective
,
1686 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1687 inst
->size_written
/ REG_SIZE
);
1690 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1691 * the ADD instruction.
1694 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1696 struct brw_reg src0
,
1697 struct brw_reg src1
)
1699 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1700 dst
.type
== BRW_REGISTER_TYPE_UD
);
1701 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1702 src0
.type
== BRW_REGISTER_TYPE_UD
);
1704 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1705 const unsigned lower_size
= MIN2(inst
->exec_size
,
1706 devinfo
->gen
>= 8 ? 16 : 8);
1708 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1709 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1710 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1711 (i
* lower_size
/ (1 << src0
.width
))) *
1712 type_sz(src0
.type
) / REG_SIZE
),
1713 suboffset(reg
, i
* lower_size
/ 4));
1714 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1715 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1716 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1721 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1726 assert(devinfo
->gen
>= 7);
1727 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1728 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1729 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1731 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1733 * Because this instruction does not have a 16-bit floating-point type,
1734 * the destination data type must be Word (W).
1736 * The destination must be DWord-aligned and specify a horizontal stride
1737 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1738 * each destination channel and the upper word is not modified.
1740 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1742 /* Give each 32-bit channel of dst the form below, where "." means
1746 brw_F32TO16(p
, dst_w
, y
);
1751 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1753 /* And, finally the form of packHalf2x16's output:
1756 brw_F32TO16(p
, dst_w
, x
);
1760 fs_generator::generate_shader_time_add(fs_inst
*,
1761 struct brw_reg payload
,
1762 struct brw_reg offset
,
1763 struct brw_reg value
)
1765 assert(devinfo
->gen
>= 7);
1766 brw_push_insn_state(p
);
1767 brw_set_default_mask_control(p
, true);
1769 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1770 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1772 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1775 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1776 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1777 value
.width
= BRW_WIDTH_1
;
1778 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1779 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1781 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1784 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1785 * case, and we don't really care about squeezing every bit of performance
1786 * out of this path, so we just emit the MOVs from here.
1788 brw_MOV(p
, payload_offset
, offset
);
1789 brw_MOV(p
, payload_value
, value
);
1790 brw_shader_time_add(p
, payload
,
1791 prog_data
->binding_table
.shader_time_start
);
1792 brw_pop_insn_state(p
);
1794 brw_mark_surface_used(prog_data
,
1795 prog_data
->binding_table
.shader_time_start
);
1799 fs_generator::enable_debug(const char *shader_name
)
1802 this->shader_name
= shader_name
;
1806 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1808 /* align to 64 byte boundary. */
1809 while (p
->next_insn_offset
% 64)
1812 this->dispatch_width
= dispatch_width
;
1814 int start_offset
= p
->next_insn_offset
;
1815 int spill_count
= 0, fill_count
= 0;
1818 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1820 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1821 struct brw_reg src
[3], dst
;
1822 unsigned int last_insn_offset
= p
->next_insn_offset
;
1823 bool multiple_instructions_emitted
= false;
1825 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1826 * "Register Region Restrictions" section: for BDW, SKL:
1828 * "A POW/FDIV operation must not be followed by an instruction
1829 * that requires two destination registers."
1831 * The documentation is often lacking annotations for Atom parts,
1832 * and empirically this affects CHV as well.
1834 if (devinfo
->gen
>= 8 &&
1835 devinfo
->gen
<= 9 &&
1837 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1838 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1839 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1841 last_insn_offset
= p
->next_insn_offset
;
1844 if (unlikely(debug_flag
))
1845 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1847 /* If the instruction writes to more than one register, it needs to be
1848 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1849 * hardware figures out by itself what the right compression mode is,
1850 * but we still need to know whether the instruction is compressed to
1851 * set up the source register regions appropriately.
1853 * XXX - This is wrong for instructions that write a single register but
1854 * read more than one which should strictly speaking be treated as
1855 * compressed. For instructions that don't write any registers it
1856 * relies on the destination being a null register of the correct
1857 * type and regioning so the instruction is considered compressed
1858 * or not accordingly.
1860 const bool compressed
=
1861 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1862 brw_set_default_compression(p
, compressed
);
1863 brw_set_default_group(p
, inst
->group
);
1865 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1866 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1867 &inst
->src
[i
], compressed
);
1868 /* The accumulator result appears to get used for the
1869 * conditional modifier generation. When negating a UD
1870 * value, there is a 33rd bit generated for the sign in the
1871 * accumulator value, so now you can't check, for example,
1872 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1874 assert(!inst
->conditional_mod
||
1875 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1876 !inst
->src
[i
].negate
);
1878 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1879 &inst
->dst
, compressed
);
1881 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1882 brw_set_default_predicate_control(p
, inst
->predicate
);
1883 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1884 /* On gen7 and above, hardware automatically adds the group onto the
1885 * flag subregister number. On Sandy Bridge and older, we have to do it
1888 const unsigned flag_subreg
= inst
->flag_subreg
+
1889 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1890 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1891 brw_set_default_saturate(p
, inst
->saturate
);
1892 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1893 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1895 unsigned exec_size
= inst
->exec_size
;
1896 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1897 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1901 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1903 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1904 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1905 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1906 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1908 switch (inst
->opcode
) {
1909 case BRW_OPCODE_MOV
:
1910 brw_MOV(p
, dst
, src
[0]);
1912 case BRW_OPCODE_ADD
:
1913 brw_ADD(p
, dst
, src
[0], src
[1]);
1915 case BRW_OPCODE_MUL
:
1916 brw_MUL(p
, dst
, src
[0], src
[1]);
1918 case BRW_OPCODE_AVG
:
1919 brw_AVG(p
, dst
, src
[0], src
[1]);
1921 case BRW_OPCODE_MACH
:
1922 brw_MACH(p
, dst
, src
[0], src
[1]);
1925 case BRW_OPCODE_LINE
:
1926 brw_LINE(p
, dst
, src
[0], src
[1]);
1929 case BRW_OPCODE_MAD
:
1930 assert(devinfo
->gen
>= 6);
1931 if (devinfo
->gen
< 10)
1932 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1933 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1936 case BRW_OPCODE_LRP
:
1937 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1938 if (devinfo
->gen
< 10)
1939 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1940 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1943 case BRW_OPCODE_FRC
:
1944 brw_FRC(p
, dst
, src
[0]);
1946 case BRW_OPCODE_RNDD
:
1947 brw_RNDD(p
, dst
, src
[0]);
1949 case BRW_OPCODE_RNDE
:
1950 brw_RNDE(p
, dst
, src
[0]);
1952 case BRW_OPCODE_RNDZ
:
1953 brw_RNDZ(p
, dst
, src
[0]);
1956 case BRW_OPCODE_AND
:
1957 brw_AND(p
, dst
, src
[0], src
[1]);
1960 brw_OR(p
, dst
, src
[0], src
[1]);
1962 case BRW_OPCODE_XOR
:
1963 brw_XOR(p
, dst
, src
[0], src
[1]);
1965 case BRW_OPCODE_NOT
:
1966 brw_NOT(p
, dst
, src
[0]);
1968 case BRW_OPCODE_ASR
:
1969 brw_ASR(p
, dst
, src
[0], src
[1]);
1971 case BRW_OPCODE_SHR
:
1972 brw_SHR(p
, dst
, src
[0], src
[1]);
1974 case BRW_OPCODE_SHL
:
1975 brw_SHL(p
, dst
, src
[0], src
[1]);
1977 case BRW_OPCODE_F32TO16
:
1978 assert(devinfo
->gen
>= 7);
1979 brw_F32TO16(p
, dst
, src
[0]);
1981 case BRW_OPCODE_F16TO32
:
1982 assert(devinfo
->gen
>= 7);
1983 brw_F16TO32(p
, dst
, src
[0]);
1985 case BRW_OPCODE_CMP
:
1986 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1987 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1988 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1989 * implemented in the compiler is not sufficient. Overriding the
1990 * type when the destination is the null register is necessary but
1991 * not sufficient by itself.
1993 assert(dst
.nr
== BRW_ARF_NULL
);
1994 dst
.type
= BRW_REGISTER_TYPE_D
;
1996 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1998 case BRW_OPCODE_SEL
:
1999 brw_SEL(p
, dst
, src
[0], src
[1]);
2001 case BRW_OPCODE_CSEL
:
2002 assert(devinfo
->gen
>= 8);
2003 if (devinfo
->gen
< 10)
2004 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2005 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
2007 case BRW_OPCODE_BFREV
:
2008 assert(devinfo
->gen
>= 7);
2009 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
2010 retype(src
[0], BRW_REGISTER_TYPE_UD
));
2012 case BRW_OPCODE_FBH
:
2013 assert(devinfo
->gen
>= 7);
2014 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
2016 case BRW_OPCODE_FBL
:
2017 assert(devinfo
->gen
>= 7);
2018 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
2019 retype(src
[0], BRW_REGISTER_TYPE_UD
));
2021 case BRW_OPCODE_LZD
:
2022 brw_LZD(p
, dst
, src
[0]);
2024 case BRW_OPCODE_CBIT
:
2025 assert(devinfo
->gen
>= 7);
2026 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
2027 retype(src
[0], BRW_REGISTER_TYPE_UD
));
2029 case BRW_OPCODE_ADDC
:
2030 assert(devinfo
->gen
>= 7);
2031 brw_ADDC(p
, dst
, src
[0], src
[1]);
2033 case BRW_OPCODE_SUBB
:
2034 assert(devinfo
->gen
>= 7);
2035 brw_SUBB(p
, dst
, src
[0], src
[1]);
2037 case BRW_OPCODE_MAC
:
2038 brw_MAC(p
, dst
, src
[0], src
[1]);
2041 case BRW_OPCODE_BFE
:
2042 assert(devinfo
->gen
>= 7);
2043 if (devinfo
->gen
< 10)
2044 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2045 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
2048 case BRW_OPCODE_BFI1
:
2049 assert(devinfo
->gen
>= 7);
2050 brw_BFI1(p
, dst
, src
[0], src
[1]);
2052 case BRW_OPCODE_BFI2
:
2053 assert(devinfo
->gen
>= 7);
2054 if (devinfo
->gen
< 10)
2055 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2056 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
2060 if (inst
->src
[0].file
!= BAD_FILE
) {
2061 /* The instruction has an embedded compare (only allowed on gen6) */
2062 assert(devinfo
->gen
== 6);
2063 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
2065 brw_IF(p
, brw_get_default_exec_size(p
));
2069 case BRW_OPCODE_ELSE
:
2072 case BRW_OPCODE_ENDIF
:
2077 brw_DO(p
, brw_get_default_exec_size(p
));
2080 case BRW_OPCODE_BREAK
:
2083 case BRW_OPCODE_CONTINUE
:
2087 case BRW_OPCODE_WHILE
:
2092 case SHADER_OPCODE_RCP
:
2093 case SHADER_OPCODE_RSQ
:
2094 case SHADER_OPCODE_SQRT
:
2095 case SHADER_OPCODE_EXP2
:
2096 case SHADER_OPCODE_LOG2
:
2097 case SHADER_OPCODE_SIN
:
2098 case SHADER_OPCODE_COS
:
2099 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2100 if (devinfo
->gen
>= 6) {
2101 assert(inst
->mlen
== 0);
2102 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
2103 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
2104 src
[0], brw_null_reg());
2106 assert(inst
->mlen
>= 1);
2107 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
2109 brw_math_function(inst
->opcode
),
2110 inst
->base_mrf
, src
[0],
2111 BRW_MATH_PRECISION_FULL
);
2114 case SHADER_OPCODE_INT_QUOTIENT
:
2115 case SHADER_OPCODE_INT_REMAINDER
:
2116 case SHADER_OPCODE_POW
:
2117 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2118 if (devinfo
->gen
>= 6) {
2119 assert(inst
->mlen
== 0);
2120 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
2121 inst
->exec_size
== 8);
2122 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2124 assert(inst
->mlen
>= 1);
2125 assert(inst
->exec_size
== 8);
2126 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2127 inst
->base_mrf
, src
[0],
2128 BRW_MATH_PRECISION_FULL
);
2131 case FS_OPCODE_LINTERP
:
2132 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2134 case FS_OPCODE_PIXEL_X
:
2135 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2136 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2137 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2139 case FS_OPCODE_PIXEL_Y
:
2140 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2141 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2142 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2144 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2145 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2147 case SHADER_OPCODE_TEX
:
2149 case SHADER_OPCODE_TXD
:
2150 case SHADER_OPCODE_TXF
:
2151 case SHADER_OPCODE_TXF_LZ
:
2152 case SHADER_OPCODE_TXF_CMS
:
2153 case SHADER_OPCODE_TXF_CMS_W
:
2154 case SHADER_OPCODE_TXF_UMS
:
2155 case SHADER_OPCODE_TXF_MCS
:
2156 case SHADER_OPCODE_TXL
:
2157 case SHADER_OPCODE_TXL_LZ
:
2158 case SHADER_OPCODE_TXS
:
2159 case SHADER_OPCODE_LOD
:
2160 case SHADER_OPCODE_TG4
:
2161 case SHADER_OPCODE_TG4_OFFSET
:
2162 case SHADER_OPCODE_SAMPLEINFO
:
2163 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
2166 case SHADER_OPCODE_IMAGE_SIZE
:
2167 generate_tex(inst
, dst
, src
[0], src
[1], brw_imm_ud(0));
2170 case FS_OPCODE_DDX_COARSE
:
2171 case FS_OPCODE_DDX_FINE
:
2172 generate_ddx(inst
, dst
, src
[0]);
2174 case FS_OPCODE_DDY_COARSE
:
2175 case FS_OPCODE_DDY_FINE
:
2176 generate_ddy(inst
, dst
, src
[0]);
2179 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2180 generate_scratch_write(inst
, src
[0]);
2184 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2185 generate_scratch_read(inst
, dst
);
2189 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2190 generate_scratch_read_gen7(inst
, dst
);
2194 case SHADER_OPCODE_MOV_INDIRECT
:
2195 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2198 case SHADER_OPCODE_URB_READ_SIMD8
:
2199 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2200 generate_urb_read(inst
, dst
, src
[0]);
2203 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2204 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2205 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2206 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2207 generate_urb_write(inst
, src
[0]);
2210 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2211 assert(inst
->force_writemask_all
);
2212 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2215 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2216 assert(inst
->force_writemask_all
);
2217 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2220 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2221 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2224 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2225 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2228 case FS_OPCODE_REP_FB_WRITE
:
2229 case FS_OPCODE_FB_WRITE
:
2230 generate_fb_write(inst
, src
[0]);
2233 case FS_OPCODE_FB_READ
:
2234 generate_fb_read(inst
, dst
, src
[0]);
2237 case FS_OPCODE_DISCARD_JUMP
:
2238 generate_discard_jump(inst
);
2241 case SHADER_OPCODE_SHADER_TIME_ADD
:
2242 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2245 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2246 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2247 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2248 inst
->mlen
, !inst
->dst
.is_null(),
2252 case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT
:
2253 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2254 brw_untyped_atomic_float(p
, dst
, src
[0], src
[1], src
[2].ud
,
2255 inst
->mlen
, !inst
->dst
.is_null(),
2259 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2260 assert(!inst
->header_size
);
2261 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2262 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2263 inst
->mlen
, src
[2].ud
);
2266 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2267 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2268 brw_untyped_surface_write(p
, src
[0], src
[1],
2269 inst
->mlen
, src
[2].ud
,
2273 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
2274 assert(!inst
->header_size
);
2275 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2276 brw_byte_scattered_read(p
, dst
, src
[0], src
[1],
2277 inst
->mlen
, src
[2].ud
);
2280 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
2281 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2282 brw_byte_scattered_write(p
, src
[0], src
[1],
2283 inst
->mlen
, src
[2].ud
,
2287 case SHADER_OPCODE_TYPED_ATOMIC
:
2288 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2289 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2290 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null(),
2294 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2295 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2296 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2297 inst
->mlen
, src
[2].ud
,
2301 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2302 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2303 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
,
2307 case SHADER_OPCODE_MEMORY_FENCE
:
2308 brw_memory_fence(p
, dst
, BRW_OPCODE_SEND
);
2311 case SHADER_OPCODE_INTERLOCK
:
2312 /* The interlock is basically a memory fence issued via sendc */
2313 brw_memory_fence(p
, dst
, BRW_OPCODE_SENDC
);
2316 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2317 const struct brw_reg mask
=
2318 brw_stage_has_packed_dispatch(devinfo
, stage
,
2319 prog_data
) ? brw_imm_ud(~0u) :
2320 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2322 brw_find_live_channel(p
, dst
, mask
);
2326 case SHADER_OPCODE_BROADCAST
:
2327 assert(inst
->force_writemask_all
);
2328 brw_broadcast(p
, dst
, src
[0], src
[1]);
2331 case SHADER_OPCODE_SHUFFLE
:
2332 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2335 case SHADER_OPCODE_SEL_EXEC
:
2336 assert(inst
->force_writemask_all
);
2337 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2338 brw_MOV(p
, dst
, src
[1]);
2339 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2340 brw_MOV(p
, dst
, src
[0]);
2343 case SHADER_OPCODE_QUAD_SWIZZLE
:
2344 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2345 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2346 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2349 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2350 assert(src
[0].type
== dst
.type
);
2351 assert(!src
[0].negate
&& !src
[0].abs
);
2352 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2353 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2354 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2355 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2356 const unsigned component
= src
[1].ud
;
2357 const unsigned cluster_size
= src
[2].ud
;
2358 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2359 cluster_size
, cluster_size
, 0);
2360 if (type_sz(src
[0].type
) > 4 &&
2361 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2362 /* IVB has an issue (which we found empirically) where it reads
2363 * two address register components per channel for indirectly
2364 * addressed 64-bit sources.
2366 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2368 * "When source or destination datatype is 64b or operation is
2369 * integer DWord multiply, indirect addressing must not be
2372 * To work around both of these, we do two integer MOVs insead of
2373 * one 64-bit MOV. Because no double value should ever cross a
2374 * register boundary, it's safe to use the immediate offset in the
2375 * indirect here to handle adding 4 bytes to the offset and avoid
2376 * the extra ADD to the register file.
2378 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2379 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2380 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2381 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2383 brw_MOV(p
, dst
, strided
);
2388 case FS_OPCODE_SET_SAMPLE_ID
:
2389 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2392 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2393 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2396 case FS_OPCODE_PLACEHOLDER_HALT
:
2397 /* This is the place where the final HALT needs to be inserted if
2398 * we've emitted any discards. If not, this will emit no code.
2400 if (!patch_discard_jumps_to_fb_writes()) {
2401 if (unlikely(debug_flag
)) {
2402 disasm_info
->use_tail
= true;
2407 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2408 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2409 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2412 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2413 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2414 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2417 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2418 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2419 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2422 case CS_OPCODE_CS_TERMINATE
:
2423 generate_cs_terminate(inst
, src
[0]);
2426 case SHADER_OPCODE_BARRIER
:
2427 generate_barrier(inst
, src
[0]);
2430 case BRW_OPCODE_DIM
:
2431 assert(devinfo
->is_haswell
);
2432 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2433 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2434 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2437 case SHADER_OPCODE_RND_MODE
:
2438 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2439 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2443 unreachable("Unsupported opcode");
2445 case SHADER_OPCODE_LOAD_PAYLOAD
:
2446 unreachable("Should be lowered by lower_load_payload()");
2449 if (multiple_instructions_emitted
)
2452 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2453 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2454 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2455 "emitting more than 1 instruction");
2457 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2459 if (inst
->conditional_mod
)
2460 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2461 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2462 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2466 brw_set_uip_jip(p
, start_offset
);
2468 /* end of program sentinel */
2469 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2474 if (unlikely(debug_flag
))
2476 brw_validate_instructions(devinfo
, p
->store
,
2478 p
->next_insn_offset
,
2481 int before_size
= p
->next_insn_offset
- start_offset
;
2482 brw_compact_instructions(p
, start_offset
, disasm_info
);
2483 int after_size
= p
->next_insn_offset
- start_offset
;
2485 if (unlikely(debug_flag
)) {
2486 fprintf(stderr
, "Native code for %s\n"
2487 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2488 " bytes (%.0f%%)\n",
2489 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2490 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2491 100.0f
* (before_size
- after_size
) / before_size
);
2493 dump_assembly(p
->store
, disasm_info
);
2495 ralloc_free(disasm_info
);
2498 compiler
->shader_debug_log(log_data
,
2499 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2500 "%d:%d spills:fills, Promoted %u constants, "
2501 "compacted %d to %d bytes.",
2502 _mesa_shader_stage_to_abbrev(stage
),
2503 dispatch_width
, before_size
/ 16,
2504 loop_count
, cfg
->cycle_count
, spill_count
,
2505 fill_count
, promoted_constants
, before_size
,
2508 return start_offset
;
2512 fs_generator::get_assembly()
2514 return brw_get_program(p
, &prog_data
->program_size
);