2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
34 static enum brw_reg_file
35 brw_file_from_reg(fs_reg
*reg
)
39 return BRW_ARCHITECTURE_REGISTER_FILE
;
42 return BRW_GENERAL_REGISTER_FILE
;
44 return BRW_MESSAGE_REGISTER_FILE
;
46 return BRW_IMMEDIATE_VALUE
;
50 unreachable("not reached");
52 return BRW_ARCHITECTURE_REGISTER_FILE
;
56 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
57 fs_reg
*reg
, bool compressed
)
59 struct brw_reg brw_reg
;
63 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
66 if (reg
->stride
== 0) {
67 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 /* From the Haswell PRM:
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
75 * The maximum width value that could satisfy this restriction is:
77 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
84 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
93 const unsigned width
= MIN2(reg_width
, phys_width
);
94 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
95 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
97 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
98 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
99 * "Each DF (Double Float) operand uses an element size of 4 rather
100 * than 8 and all regioning parameters are twice what the values
101 * would be based on the true element size: ExecSize, Width,
102 * HorzStride, and VertStride. Each DF operand uses a pair of
103 * channels and all masking and swizzing should be adjusted
106 * From the IvyBridge PRM (Special Requirements for Handling Double
107 * Precision Data Types, page 71):
108 * "In Align1 mode, all regioning parameters like stride, execution
109 * size, and width must use the syntax of a pair of packed
110 * floats. The offsets for these data types must be 64-bit
111 * aligned. The execution size and regioning parameters are in terms
114 * Summarized: when handling DF-typed arguments, ExecSize,
115 * VertStride, and Width must be doubled.
117 * It applies to BayTrail too.
119 if (type_sz(reg
->type
) == 8) {
121 if (brw_reg
.vstride
> 0)
123 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
126 /* When converting from DF->F, we set the destination stride to 2
127 * because each d2f conversion implicitly writes 2 floats, being
128 * the first one the converted value. IVB/BYT actually writes two
129 * F components per SIMD channel, and every other component is
130 * filled with garbage.
132 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
133 type_sz(inst
->dst
.type
) < 8) {
134 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
140 brw_reg
= retype(brw_reg
, reg
->type
);
141 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
142 brw_reg
.abs
= reg
->abs
;
143 brw_reg
.negate
= reg
->negate
;
148 assert(reg
->offset
== 0);
149 brw_reg
= reg
->as_brw_reg();
152 /* Probably unused. */
153 brw_reg
= brw_null_reg();
157 unreachable("not reached");
160 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
161 * region, but on IVB and BYT DF regions must be programmed in terms of
162 * floats. A <0,2,1> region accomplishes this.
164 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
165 type_sz(reg
->type
) == 8 &&
166 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
167 brw_reg
.width
== BRW_WIDTH_1
&&
168 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
169 brw_reg
.width
= BRW_WIDTH_2
;
170 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
176 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
179 struct brw_stage_prog_data
*prog_data
,
180 unsigned promoted_constants
,
181 bool runtime_check_aads_emit
,
182 gl_shader_stage stage
)
184 : compiler(compiler
), log_data(log_data
),
185 devinfo(compiler
->devinfo
), key(key
),
186 prog_data(prog_data
),
187 promoted_constants(promoted_constants
),
188 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
189 stage(stage
), mem_ctx(mem_ctx
)
191 p
= rzalloc(mem_ctx
, struct brw_codegen
);
192 brw_init_codegen(devinfo
, p
, mem_ctx
);
194 /* In the FS code generator, we are very careful to ensure that we always
195 * set the right execution size so we don't need the EU code to "help" us
196 * by trying to infer it. Sometimes, it infers the wrong thing.
198 p
->automatic_exec_sizes
= false;
201 fs_generator::~fs_generator()
205 class ip_record
: public exec_node
{
207 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
218 fs_generator::patch_discard_jumps_to_fb_writes()
220 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
223 int scale
= brw_jump_scale(p
->devinfo
);
225 /* There is a somewhat strange undocumented requirement of using
226 * HALT, according to the simulator. If some channel has HALTed to
227 * a particular UIP, then by the end of the program, every channel
228 * must have HALTed to that UIP. Furthermore, the tracking is a
229 * stack, so you can't do the final halt of a UIP after starting
230 * halting to a new UIP.
232 * Symptoms of not emitting this instruction on actual hardware
233 * included GPU hangs and sparkly rendering on the piglit discard
236 brw_inst
*last_halt
= gen6_HALT(p
);
237 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
238 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
242 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
243 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
245 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
246 /* HALT takes a half-instruction distance from the pre-incremented IP. */
247 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
250 this->discard_halt_patches
.make_empty();
255 fs_generator::fire_fb_write(fs_inst
*inst
,
256 struct brw_reg payload
,
257 struct brw_reg implied_header
,
260 uint32_t msg_control
;
262 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
264 if (devinfo
->gen
< 6) {
265 brw_push_insn_state(p
);
266 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
267 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
268 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
269 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
270 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
271 brw_pop_insn_state(p
);
274 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
275 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
276 else if (prog_data
->dual_src_blend
) {
278 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
280 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
281 } else if (inst
->exec_size
== 16)
282 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
284 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
286 /* We assume render targets start at 0, because headerless FB write
287 * messages set "Render Target Index" to 0. Using a different binding
288 * table index would make it impossible to use headerless messages.
290 const uint32_t surf_index
= inst
->target
;
292 bool last_render_target
= inst
->eot
||
293 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
305 inst
->header_size
!= 0);
307 brw_mark_surface_used(&prog_data
->base
, surf_index
);
311 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
313 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
314 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
315 struct brw_reg implied_header
;
317 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
318 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
321 if (inst
->base_mrf
>= 0)
322 payload
= brw_message_reg(inst
->base_mrf
);
324 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
327 if (inst
->header_size
!= 0) {
328 brw_push_insn_state(p
);
329 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
330 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
331 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
332 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
333 brw_set_default_flag_reg(p
, 0, 0);
335 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
338 if (prog_data
->uses_kill
) {
339 struct brw_reg pixel_mask
;
341 if (devinfo
->gen
>= 6)
342 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
344 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
346 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
349 if (devinfo
->gen
>= 6) {
350 brw_push_insn_state(p
);
351 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
352 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
354 retype(payload
, BRW_REGISTER_TYPE_UD
),
355 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
356 brw_pop_insn_state(p
);
358 if (inst
->target
> 0 && key
->replicate_alpha
) {
359 /* Set "Source0 Alpha Present to RenderTarget" bit in message
363 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
364 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
365 brw_imm_ud(0x1 << 11));
368 if (inst
->target
> 0) {
369 /* Set the render target index for choosing BLEND_STATE. */
370 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
371 BRW_REGISTER_TYPE_UD
),
372 brw_imm_ud(inst
->target
));
375 /* Set computes stencil to render target */
376 if (prog_data
->computed_stencil
) {
378 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
379 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
380 brw_imm_ud(0x1 << 14));
383 implied_header
= brw_null_reg();
385 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
388 brw_pop_insn_state(p
);
390 implied_header
= brw_null_reg();
393 if (!runtime_check_aads_emit
) {
394 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
396 /* This can only happen in gen < 6 */
397 assert(devinfo
->gen
< 6);
399 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
401 /* Check runtime bit to detect if we have to send AA data or not */
402 brw_push_insn_state(p
);
403 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
404 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
407 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
409 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
411 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
412 brw_pop_insn_state(p
);
414 /* Don't send AA data */
415 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
417 brw_land_fwd_jump(p
, jmp
);
418 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
423 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
424 struct brw_reg payload
)
426 assert(inst
->size_written
% REG_SIZE
== 0);
427 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
428 /* We assume that render targets start at binding table index 0. */
429 const unsigned surf_index
= inst
->target
;
431 gen9_fb_READ(p
, dst
, payload
, surf_index
,
432 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
433 prog_data
->persample_dispatch
);
435 brw_mark_surface_used(&prog_data
->base
, surf_index
);
439 fs_generator::generate_mov_indirect(fs_inst
*inst
,
442 struct brw_reg indirect_byte_offset
)
444 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
445 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
446 assert(!reg
.abs
&& !reg
.negate
);
447 assert(reg
.type
== dst
.type
);
449 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
451 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
452 imm_byte_offset
+= indirect_byte_offset
.ud
;
454 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
455 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
456 brw_MOV(p
, dst
, reg
);
458 /* Prior to Broadwell, there are only 8 address registers. */
459 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
461 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
462 struct brw_reg addr
= vec8(brw_address_reg(0));
464 /* The destination stride of an instruction (in bytes) must be greater
465 * than or equal to the size of the rest of the instruction. Since the
466 * address register is of type UW, we can't use a D-type instruction.
467 * In order to get around this, re retype to UW and use a stride.
469 indirect_byte_offset
=
470 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
472 /* There are a number of reasons why we don't use the base offset here.
473 * One reason is that the field is only 9 bits which means we can only
474 * use it to access the first 16 GRFs. Also, from the Haswell PRM
475 * section "Register Region Restrictions":
477 * "The lower bits of the AddressImmediate must not overflow to
478 * change the register address. The lower 5 bits of Address
479 * Immediate when added to lower 5 bits of address register gives
480 * the sub-register offset. The upper bits of Address Immediate
481 * when added to upper bits of address register gives the register
482 * address. Any overflow from sub-register offset is dropped."
484 * Since the indirect may cause us to cross a register boundary, this
485 * makes the base offset almost useless. We could try and do something
486 * clever where we use a actual base offset if base_offset % 32 == 0 but
487 * that would mean we were generating different code depending on the
488 * base offset. Instead, for the sake of consistency, we'll just do the
489 * add ourselves. This restriction is only listed in the Haswell PRM
490 * but empirical testing indicates that it applies on all older
491 * generations and is lifted on Broadwell.
493 * In the end, while base_offset is nice to look at in the generated
494 * code, using it saves us 0 instructions and would require quite a bit
495 * of case-by-case work. It's just not worth it.
497 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
499 if (type_sz(reg
.type
) > 4 &&
500 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
501 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
502 /* IVB has an issue (which we found empirically) where it reads two
503 * address register components per channel for indirectly addressed
506 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
508 * "When source or destination datatype is 64b or operation is
509 * integer DWord multiply, indirect addressing must not be used."
511 * To work around both of these, we do two integer MOVs insead of one
512 * 64-bit MOV. Because no double value should ever cross a register
513 * boundary, it's safe to use the immediate offset in the indirect
514 * here to handle adding 4 bytes to the offset and avoid the extra
515 * ADD to the register file.
517 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
518 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
519 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
520 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
522 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
524 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
526 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
527 !inst
->get_next()->is_tail_sentinel() &&
528 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
529 /* From the Sandybridge PRM:
531 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
532 * instruction that “indexed/indirect” source AND is followed
533 * by a send, the instruction requires a “Switch”. This is to
534 * avoid race condition where send may dispatch before MRF is
537 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
544 fs_generator::generate_urb_read(fs_inst
*inst
,
546 struct brw_reg header
)
548 assert(inst
->size_written
% REG_SIZE
== 0);
549 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
550 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
552 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
553 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
554 brw_set_src0(p
, send
, header
);
555 brw_set_src1(p
, send
, brw_imm_ud(0u));
557 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
558 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
560 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
561 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
563 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
564 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
565 brw_inst_set_header_present(p
->devinfo
, send
, true);
566 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
570 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
574 /* WaClearTDRRegBeforeEOTForNonPS.
576 * WA: Clear tdr register before send EOT in all non-PS shader kernels
578 * mov(8) tdr0:ud 0x0:ud {NoMask}"
580 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
581 brw_push_insn_state(p
);
582 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
583 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
584 brw_pop_insn_state(p
);
587 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
589 brw_set_dest(p
, insn
, brw_null_reg());
590 brw_set_src0(p
, insn
, payload
);
591 brw_set_src1(p
, insn
, brw_imm_d(0));
593 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
594 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
596 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
597 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
598 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
600 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
601 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
602 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
604 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
605 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
606 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
607 brw_inst_set_header_present(p
->devinfo
, insn
, true);
608 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
612 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
614 struct brw_inst
*insn
;
616 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
618 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
619 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
620 brw_set_src1(p
, insn
, brw_imm_d(0));
622 /* Terminate a compute shader by sending a message to the thread spawner.
624 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
625 brw_inst_set_mlen(devinfo
, insn
, 1);
626 brw_inst_set_rlen(devinfo
, insn
, 0);
627 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
628 brw_inst_set_header_present(devinfo
, insn
, false);
630 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
631 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
633 /* Note that even though the thread has a URB resource associated with it,
634 * we set the "do not dereference URB" bit, because the URB resource is
635 * managed by the fixed-function unit, so it will free it automatically.
637 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
639 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
643 fs_generator::generate_barrier(fs_inst
*inst
, struct brw_reg src
)
650 fs_generator::generate_linterp(fs_inst
*inst
,
651 struct brw_reg dst
, struct brw_reg
*src
)
655 * -----------------------------------
656 * | src1+0 | src1+1 | src1+2 | src1+3 |
657 * |-----------------------------------|
658 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
659 * -----------------------------------
661 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
663 * -----------------------------------
664 * | src1+0 | src1+1 | src1+2 | src1+3 |
665 * |-----------------------------------|
666 * |(x0, x1)|(y0, y1)| | | in SIMD8
667 * |-----------------------------------|
668 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
669 * -----------------------------------
671 * See also: emit_interpolation_setup_gen4().
673 struct brw_reg delta_x
= src
[0];
674 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
675 struct brw_reg interp
= src
[1];
677 if (devinfo
->has_pln
&&
678 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
679 brw_PLN(p
, dst
, interp
, delta_x
);
681 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
682 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
687 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
690 struct brw_reg surf_index
)
692 assert(devinfo
->gen
>= 7);
693 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
698 switch (inst
->exec_size
) {
700 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
703 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
706 unreachable("Invalid width for texture instruction");
709 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
715 retype(dst
, BRW_REGISTER_TYPE_UW
),
720 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
721 rlen
, /* response length */
723 inst
->header_size
> 0,
725 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
727 brw_mark_surface_used(prog_data
, surf_index
.ud
);
731 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
732 struct brw_reg surface_index
,
733 struct brw_reg sampler_index
)
735 assert(inst
->size_written
% REG_SIZE
== 0);
738 uint32_t return_format
;
739 bool is_combined_send
= inst
->eot
;
742 case BRW_REGISTER_TYPE_D
:
743 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
745 case BRW_REGISTER_TYPE_UD
:
746 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
749 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
753 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
754 * is set as part of the message descriptor. On gen4, the PRM seems to
755 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
756 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
757 * gone from the message descriptor entirely and you just get UINT32 all
758 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
759 * just stomp it to UINT32 all the time.
761 if (inst
->opcode
== SHADER_OPCODE_TXS
)
762 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
764 switch (inst
->exec_size
) {
766 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
769 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
772 unreachable("Invalid width for texture instruction");
775 if (devinfo
->gen
>= 5) {
776 switch (inst
->opcode
) {
777 case SHADER_OPCODE_TEX
:
778 if (inst
->shadow_compare
) {
779 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
781 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
785 if (inst
->shadow_compare
) {
786 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
788 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
791 case SHADER_OPCODE_TXL
:
792 if (inst
->shadow_compare
) {
793 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
795 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
798 case SHADER_OPCODE_TXL_LZ
:
799 assert(devinfo
->gen
>= 9);
800 if (inst
->shadow_compare
) {
801 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
;
803 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
806 case SHADER_OPCODE_TXS
:
807 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
809 case SHADER_OPCODE_TXD
:
810 if (inst
->shadow_compare
) {
811 /* Gen7.5+. Otherwise, lowered in NIR */
812 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
813 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
815 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
818 case SHADER_OPCODE_TXF
:
819 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
821 case SHADER_OPCODE_TXF_LZ
:
822 assert(devinfo
->gen
>= 9);
823 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
825 case SHADER_OPCODE_TXF_CMS_W
:
826 assert(devinfo
->gen
>= 9);
827 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
829 case SHADER_OPCODE_TXF_CMS
:
830 if (devinfo
->gen
>= 7)
831 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
833 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
835 case SHADER_OPCODE_TXF_UMS
:
836 assert(devinfo
->gen
>= 7);
837 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
839 case SHADER_OPCODE_TXF_MCS
:
840 assert(devinfo
->gen
>= 7);
841 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
843 case SHADER_OPCODE_LOD
:
844 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
846 case SHADER_OPCODE_TG4
:
847 if (inst
->shadow_compare
) {
848 assert(devinfo
->gen
>= 7);
849 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
851 assert(devinfo
->gen
>= 6);
852 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
855 case SHADER_OPCODE_TG4_OFFSET
:
856 assert(devinfo
->gen
>= 7);
857 if (inst
->shadow_compare
) {
858 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
860 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
863 case SHADER_OPCODE_SAMPLEINFO
:
864 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
867 unreachable("not reached");
870 switch (inst
->opcode
) {
871 case SHADER_OPCODE_TEX
:
872 /* Note that G45 and older determines shadow compare and dispatch width
873 * from message length for most messages.
875 if (inst
->exec_size
== 8) {
876 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
877 if (inst
->shadow_compare
) {
878 assert(inst
->mlen
== 6);
880 assert(inst
->mlen
<= 4);
883 if (inst
->shadow_compare
) {
884 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
885 assert(inst
->mlen
== 9);
887 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
888 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
893 if (inst
->shadow_compare
) {
894 assert(inst
->exec_size
== 8);
895 assert(inst
->mlen
== 6);
896 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
898 assert(inst
->mlen
== 9);
899 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
900 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
903 case SHADER_OPCODE_TXL
:
904 if (inst
->shadow_compare
) {
905 assert(inst
->exec_size
== 8);
906 assert(inst
->mlen
== 6);
907 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
909 assert(inst
->mlen
== 9);
910 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
911 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
914 case SHADER_OPCODE_TXD
:
915 /* There is no sample_d_c message; comparisons are done manually */
916 assert(inst
->exec_size
== 8);
917 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
918 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
920 case SHADER_OPCODE_TXF
:
921 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
922 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
923 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
925 case SHADER_OPCODE_TXS
:
926 assert(inst
->mlen
== 3);
927 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
928 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
931 unreachable("not reached");
934 assert(msg_type
!= -1);
936 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
940 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
941 src
.file
== BRW_GENERAL_REGISTER_FILE
);
943 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
945 /* Load the message header if present. If there's a texture offset,
946 * we need to set it up explicitly and load the offset bitfield.
947 * Otherwise, we can use an implied move from g0 to the first message reg.
949 if (inst
->header_size
!= 0) {
950 if (devinfo
->gen
< 6 && !inst
->offset
) {
951 /* Set up an implied move from g0 to the MRF. */
952 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
954 struct brw_reg header_reg
;
956 if (devinfo
->gen
>= 7) {
959 assert(inst
->base_mrf
!= -1);
960 header_reg
= brw_message_reg(inst
->base_mrf
);
963 brw_push_insn_state(p
);
964 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
965 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
966 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
967 /* Explicitly set up the message header by copying g0 to the MRF. */
968 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
970 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
972 /* Set the offset bits in DWord 2. */
973 brw_MOV(p
, get_element_ud(header_reg
, 2),
974 brw_imm_ud(inst
->offset
));
975 } else if (stage
!= MESA_SHADER_VERTEX
&&
976 stage
!= MESA_SHADER_FRAGMENT
) {
977 /* The vertex and fragment stages have g0.2 set to 0, so
978 * header0.2 is 0 when g0 is copied. Other stages may not, so we
979 * must set it to 0 to avoid setting undesirable bits in the
982 brw_MOV(p
, get_element_ud(header_reg
, 2), brw_imm_ud(0));
985 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
986 brw_pop_insn_state(p
);
990 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
991 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
992 ? prog_data
->binding_table
.gather_texture_start
993 : prog_data
->binding_table
.texture_start
;
995 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
996 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
997 uint32_t surface
= surface_index
.ud
;
998 uint32_t sampler
= sampler_index
.ud
;
1001 retype(dst
, BRW_REGISTER_TYPE_UW
),
1004 surface
+ base_binding_table_index
,
1007 inst
->size_written
/ REG_SIZE
,
1009 inst
->header_size
!= 0,
1013 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
1015 /* Non-const sampler index */
1017 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1018 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
1019 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
1021 brw_push_insn_state(p
);
1022 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1023 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1024 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1026 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
1027 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
1029 if (sampler_reg
.file
== BRW_IMMEDIATE_VALUE
) {
1030 brw_OR(p
, addr
, surface_reg
, brw_imm_ud(sampler_reg
.ud
<< 8));
1032 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
1033 brw_OR(p
, addr
, addr
, surface_reg
);
1036 if (base_binding_table_index
)
1037 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
1038 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
1040 brw_pop_insn_state(p
);
1042 /* dst = send(offset, a0.0 | <descriptor>) */
1043 brw_inst
*insn
= brw_send_indirect_message(
1044 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1045 brw_set_sampler_message(p
, insn
,
1049 inst
->size_written
/ REG_SIZE
,
1050 inst
->mlen
/* mlen */,
1051 inst
->header_size
!= 0 /* header */,
1055 /* visitor knows more than we do about the surface limit required,
1056 * so has already done marking.
1060 if (is_combined_send
) {
1061 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
1062 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
1067 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1070 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1072 * Ideally, we want to produce:
1075 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1076 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1077 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1078 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1079 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1080 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1081 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1082 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1084 * and add another set of two more subspans if in 16-pixel dispatch mode.
1086 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1087 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1088 * pair. But the ideal approximation may impose a huge performance cost on
1089 * sample_d. On at least Haswell, sample_d instruction does some
1090 * optimizations if the same LOD is used for all pixels in the subspan.
1092 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1093 * appropriate swizzling.
1096 fs_generator::generate_ddx(enum opcode opcode
,
1097 struct brw_reg dst
, struct brw_reg src
)
1099 unsigned vstride
, width
;
1101 if (opcode
== FS_OPCODE_DDX_FINE
) {
1102 /* produce accurate derivatives */
1103 vstride
= BRW_VERTICAL_STRIDE_2
;
1104 width
= BRW_WIDTH_2
;
1106 /* replicate the derivative at the top-left pixel to other pixels */
1107 vstride
= BRW_VERTICAL_STRIDE_4
;
1108 width
= BRW_WIDTH_4
;
1111 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
1112 src
.negate
, src
.abs
,
1113 BRW_REGISTER_TYPE_F
,
1116 BRW_HORIZONTAL_STRIDE_0
,
1117 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1118 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1119 src
.negate
, src
.abs
,
1120 BRW_REGISTER_TYPE_F
,
1123 BRW_HORIZONTAL_STRIDE_0
,
1124 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1125 brw_ADD(p
, dst
, src0
, negate(src1
));
1128 /* The negate_value boolean is used to negate the derivative computation for
1129 * FBOs, since they place the origin at the upper left instead of the lower
1133 fs_generator::generate_ddy(enum opcode opcode
,
1134 struct brw_reg dst
, struct brw_reg src
)
1136 if (opcode
== FS_OPCODE_DDY_FINE
) {
1137 /* produce accurate derivatives */
1138 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1139 src
.negate
, src
.abs
,
1140 BRW_REGISTER_TYPE_F
,
1141 BRW_VERTICAL_STRIDE_4
,
1143 BRW_HORIZONTAL_STRIDE_1
,
1144 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
1145 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1146 src
.negate
, src
.abs
,
1147 BRW_REGISTER_TYPE_F
,
1148 BRW_VERTICAL_STRIDE_4
,
1150 BRW_HORIZONTAL_STRIDE_1
,
1151 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
1152 brw_push_insn_state(p
);
1153 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1154 brw_ADD(p
, dst
, negate(src0
), src1
);
1155 brw_pop_insn_state(p
);
1157 /* replicate the derivative at the top-left pixel to other pixels */
1158 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1159 src
.negate
, src
.abs
,
1160 BRW_REGISTER_TYPE_F
,
1161 BRW_VERTICAL_STRIDE_4
,
1163 BRW_HORIZONTAL_STRIDE_0
,
1164 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1165 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1166 src
.negate
, src
.abs
,
1167 BRW_REGISTER_TYPE_F
,
1168 BRW_VERTICAL_STRIDE_4
,
1170 BRW_HORIZONTAL_STRIDE_0
,
1171 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1172 brw_ADD(p
, dst
, negate(src0
), src1
);
1177 fs_generator::generate_discard_jump(fs_inst
*inst
)
1179 assert(devinfo
->gen
>= 6);
1181 /* This HALT will be patched up at FB write time to point UIP at the end of
1182 * the program, and at brw_uip_jip() JIP will be set to the end of the
1183 * current block (or the program).
1185 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1190 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1192 /* The 32-wide messages only respect the first 16-wide half of the channel
1193 * enable signals which are replicated identically for the second group of
1194 * 16 channels, so we cannot use them unless the write is marked
1195 * force_writemask_all.
1197 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1198 MIN2(16, inst
->exec_size
);
1199 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1200 assert(inst
->mlen
!= 0);
1202 brw_push_insn_state(p
);
1203 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1204 brw_set_default_compression(p
, lower_size
> 8);
1206 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1207 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1209 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1210 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1212 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1214 inst
->offset
+ block_size
* REG_SIZE
* i
);
1217 brw_pop_insn_state(p
);
1221 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1223 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1224 assert(inst
->mlen
!= 0);
1226 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1227 inst
->exec_size
/ 8, inst
->offset
);
1231 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1233 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1235 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1239 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1241 struct brw_reg index
,
1242 struct brw_reg offset
)
1244 assert(type_sz(dst
.type
) == 4);
1245 assert(inst
->mlen
!= 0);
1247 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1248 index
.type
== BRW_REGISTER_TYPE_UD
);
1249 uint32_t surf_index
= index
.ud
;
1251 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1252 offset
.type
== BRW_REGISTER_TYPE_UD
);
1253 uint32_t read_offset
= offset
.ud
;
1255 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1256 read_offset
, surf_index
);
1260 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1262 struct brw_reg index
,
1263 struct brw_reg payload
)
1265 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1266 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1267 assert(type_sz(dst
.type
) == 4);
1269 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1270 const uint32_t surf_index
= index
.ud
;
1272 brw_push_insn_state(p
);
1273 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1274 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1275 brw_pop_insn_state(p
);
1277 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1278 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1279 brw_set_dp_read_message(p
, send
, surf_index
,
1280 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1281 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1282 GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1285 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
));
1288 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1290 brw_push_insn_state(p
);
1291 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1293 /* a0.0 = surf_index & 0xff */
1294 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1295 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1296 brw_set_dest(p
, insn_and
, addr
);
1297 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1298 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1300 /* dst = send(payload, a0.0 | <descriptor>) */
1301 brw_inst
*insn
= brw_send_indirect_message(
1302 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1303 retype(dst
, BRW_REGISTER_TYPE_UD
),
1304 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
);
1305 brw_set_dp_read_message(p
, insn
, 0 /* surface */,
1306 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1307 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1308 GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1311 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
));
1313 brw_pop_insn_state(p
);
1318 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1320 struct brw_reg index
)
1322 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1323 assert(inst
->header_size
!= 0);
1326 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1327 index
.type
== BRW_REGISTER_TYPE_UD
);
1328 uint32_t surf_index
= index
.ud
;
1330 uint32_t simd_mode
, rlen
, msg_type
;
1331 if (inst
->exec_size
== 16) {
1332 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1335 assert(inst
->exec_size
== 8);
1336 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1340 if (devinfo
->gen
>= 5)
1341 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1343 /* We always use the SIMD16 message so that we only have to load U, and
1346 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1347 assert(inst
->mlen
== 3);
1348 assert(inst
->size_written
== 8 * REG_SIZE
);
1350 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1353 struct brw_reg header
= brw_vec8_grf(0, 0);
1354 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1356 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1357 brw_inst_set_compression(devinfo
, send
, false);
1358 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1359 brw_set_src0(p
, send
, header
);
1360 if (devinfo
->gen
< 6)
1361 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1363 /* Our surface is set up as floats, regardless of what actual data is
1366 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1367 brw_set_sampler_message(p
, send
,
1369 0, /* sampler (unused) */
1373 inst
->header_size
!= 0,
1379 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1381 struct brw_reg index
,
1382 struct brw_reg offset
)
1384 assert(devinfo
->gen
>= 7);
1385 /* Varying-offset pull constant loads are treated as a normal expression on
1386 * gen7, so the fact that it's a send message is hidden at the IR level.
1388 assert(inst
->header_size
== 0);
1389 assert(!inst
->mlen
);
1390 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1392 uint32_t simd_mode
, rlen
, mlen
;
1393 if (inst
->exec_size
== 16) {
1396 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1398 assert(inst
->exec_size
== 8);
1401 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1404 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1406 uint32_t surf_index
= index
.ud
;
1408 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1409 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1410 brw_set_src0(p
, send
, offset
);
1411 brw_set_sampler_message(p
, send
,
1413 0, /* LD message ignores sampler unit */
1414 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1417 false, /* no header */
1423 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1425 brw_push_insn_state(p
);
1426 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1428 /* a0.0 = surf_index & 0xff */
1429 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1430 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1431 brw_set_dest(p
, insn_and
, addr
);
1432 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1433 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1435 brw_pop_insn_state(p
);
1437 /* dst = send(offset, a0.0 | <descriptor>) */
1438 brw_inst
*insn
= brw_send_indirect_message(
1439 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1441 brw_set_sampler_message(p
, insn
,
1444 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1454 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1455 * into the flags register (f0.0).
1457 * Used only on Gen6 and above.
1460 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1462 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1463 struct brw_reg dispatch_mask
;
1465 if (devinfo
->gen
>= 6)
1466 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1468 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1470 brw_push_insn_state(p
);
1471 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1472 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1473 brw_MOV(p
, flags
, dispatch_mask
);
1474 brw_pop_insn_state(p
);
1478 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1481 struct brw_reg msg_data
,
1484 assert(inst
->size_written
% REG_SIZE
== 0);
1485 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1487 brw_pixel_interpolator_query(p
,
1488 retype(dst
, BRW_REGISTER_TYPE_UW
),
1490 inst
->pi_noperspective
,
1494 inst
->size_written
/ REG_SIZE
);
1497 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1498 * the ADD instruction.
1501 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1503 struct brw_reg src0
,
1504 struct brw_reg src1
)
1506 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1507 dst
.type
== BRW_REGISTER_TYPE_UD
);
1508 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1509 src0
.type
== BRW_REGISTER_TYPE_UD
);
1511 struct brw_reg reg
= stride(src1
, 1, 4, 0);
1512 if (devinfo
->gen
>= 8 || inst
->exec_size
== 8) {
1513 brw_ADD(p
, dst
, src0
, reg
);
1514 } else if (inst
->exec_size
== 16) {
1515 brw_push_insn_state(p
);
1516 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1517 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1518 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1519 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1520 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1521 brw_pop_insn_state(p
);
1526 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1531 assert(devinfo
->gen
>= 7);
1532 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1533 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1534 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1536 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1538 * Because this instruction does not have a 16-bit floating-point type,
1539 * the destination data type must be Word (W).
1541 * The destination must be DWord-aligned and specify a horizontal stride
1542 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1543 * each destination channel and the upper word is not modified.
1545 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1547 /* Give each 32-bit channel of dst the form below, where "." means
1551 brw_F32TO16(p
, dst_w
, y
);
1556 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1558 /* And, finally the form of packHalf2x16's output:
1561 brw_F32TO16(p
, dst_w
, x
);
1565 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1569 assert(devinfo
->gen
>= 7);
1570 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1571 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1573 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1575 * Because this instruction does not have a 16-bit floating-point type,
1576 * the source data type must be Word (W). The destination type must be
1579 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1581 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1582 * For the Y case, we wish to access only the upper word; therefore
1583 * a 16-bit subregister offset is needed.
1585 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1586 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1587 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1590 brw_F16TO32(p
, dst
, src_w
);
1594 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1595 struct brw_reg payload
,
1596 struct brw_reg offset
,
1597 struct brw_reg value
)
1599 assert(devinfo
->gen
>= 7);
1600 brw_push_insn_state(p
);
1601 brw_set_default_mask_control(p
, true);
1603 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1604 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1606 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1609 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1610 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1611 value
.width
= BRW_WIDTH_1
;
1612 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1613 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1615 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1618 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1619 * case, and we don't really care about squeezing every bit of performance
1620 * out of this path, so we just emit the MOVs from here.
1622 brw_MOV(p
, payload_offset
, offset
);
1623 brw_MOV(p
, payload_value
, value
);
1624 brw_shader_time_add(p
, payload
,
1625 prog_data
->binding_table
.shader_time_start
);
1626 brw_pop_insn_state(p
);
1628 brw_mark_surface_used(prog_data
,
1629 prog_data
->binding_table
.shader_time_start
);
1633 fs_generator::enable_debug(const char *shader_name
)
1636 this->shader_name
= shader_name
;
1640 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1642 /* align to 64 byte boundary. */
1643 while (p
->next_insn_offset
% 64)
1646 this->dispatch_width
= dispatch_width
;
1648 int start_offset
= p
->next_insn_offset
;
1649 int spill_count
= 0, fill_count
= 0;
1652 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1654 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1655 struct brw_reg src
[3], dst
;
1656 unsigned int last_insn_offset
= p
->next_insn_offset
;
1657 bool multiple_instructions_emitted
= false;
1659 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1660 * "Register Region Restrictions" section: for BDW, SKL:
1662 * "A POW/FDIV operation must not be followed by an instruction
1663 * that requires two destination registers."
1665 * The documentation is often lacking annotations for Atom parts,
1666 * and empirically this affects CHV as well.
1668 if (devinfo
->gen
>= 8 &&
1669 devinfo
->gen
<= 9 &&
1671 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1672 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1673 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1675 last_insn_offset
= p
->next_insn_offset
;
1678 if (unlikely(debug_flag
))
1679 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1681 /* If the instruction writes to more than one register, it needs to be
1682 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1683 * hardware figures out by itself what the right compression mode is,
1684 * but we still need to know whether the instruction is compressed to
1685 * set up the source register regions appropriately.
1687 * XXX - This is wrong for instructions that write a single register but
1688 * read more than one which should strictly speaking be treated as
1689 * compressed. For instructions that don't write any registers it
1690 * relies on the destination being a null register of the correct
1691 * type and regioning so the instruction is considered compressed
1692 * or not accordingly.
1694 const bool compressed
=
1695 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1696 brw_set_default_compression(p
, compressed
);
1697 brw_set_default_group(p
, inst
->group
);
1699 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1700 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1701 &inst
->src
[i
], compressed
);
1702 /* The accumulator result appears to get used for the
1703 * conditional modifier generation. When negating a UD
1704 * value, there is a 33rd bit generated for the sign in the
1705 * accumulator value, so now you can't check, for example,
1706 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1708 assert(!inst
->conditional_mod
||
1709 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1710 !inst
->src
[i
].negate
);
1712 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1713 &inst
->dst
, compressed
);
1715 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1716 brw_set_default_predicate_control(p
, inst
->predicate
);
1717 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1718 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1719 brw_set_default_saturate(p
, inst
->saturate
);
1720 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1721 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1723 unsigned exec_size
= inst
->exec_size
;
1724 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1725 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1729 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1731 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1732 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1733 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1734 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1736 switch (inst
->opcode
) {
1737 case BRW_OPCODE_MOV
:
1738 brw_MOV(p
, dst
, src
[0]);
1740 case BRW_OPCODE_ADD
:
1741 brw_ADD(p
, dst
, src
[0], src
[1]);
1743 case BRW_OPCODE_MUL
:
1744 brw_MUL(p
, dst
, src
[0], src
[1]);
1746 case BRW_OPCODE_AVG
:
1747 brw_AVG(p
, dst
, src
[0], src
[1]);
1749 case BRW_OPCODE_MACH
:
1750 brw_MACH(p
, dst
, src
[0], src
[1]);
1753 case BRW_OPCODE_LINE
:
1754 brw_LINE(p
, dst
, src
[0], src
[1]);
1757 case BRW_OPCODE_MAD
:
1758 assert(devinfo
->gen
>= 6);
1759 if (devinfo
->gen
< 10)
1760 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1761 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1764 case BRW_OPCODE_LRP
:
1765 assert(devinfo
->gen
>= 6);
1766 if (devinfo
->gen
< 10)
1767 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1768 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1771 case BRW_OPCODE_FRC
:
1772 brw_FRC(p
, dst
, src
[0]);
1774 case BRW_OPCODE_RNDD
:
1775 brw_RNDD(p
, dst
, src
[0]);
1777 case BRW_OPCODE_RNDE
:
1778 brw_RNDE(p
, dst
, src
[0]);
1780 case BRW_OPCODE_RNDZ
:
1781 brw_RNDZ(p
, dst
, src
[0]);
1784 case BRW_OPCODE_AND
:
1785 brw_AND(p
, dst
, src
[0], src
[1]);
1788 brw_OR(p
, dst
, src
[0], src
[1]);
1790 case BRW_OPCODE_XOR
:
1791 brw_XOR(p
, dst
, src
[0], src
[1]);
1793 case BRW_OPCODE_NOT
:
1794 brw_NOT(p
, dst
, src
[0]);
1796 case BRW_OPCODE_ASR
:
1797 brw_ASR(p
, dst
, src
[0], src
[1]);
1799 case BRW_OPCODE_SHR
:
1800 brw_SHR(p
, dst
, src
[0], src
[1]);
1802 case BRW_OPCODE_SHL
:
1803 brw_SHL(p
, dst
, src
[0], src
[1]);
1805 case BRW_OPCODE_F32TO16
:
1806 assert(devinfo
->gen
>= 7);
1807 brw_F32TO16(p
, dst
, src
[0]);
1809 case BRW_OPCODE_F16TO32
:
1810 assert(devinfo
->gen
>= 7);
1811 brw_F16TO32(p
, dst
, src
[0]);
1813 case BRW_OPCODE_CMP
:
1814 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1815 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1816 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1817 * implemented in the compiler is not sufficient. Overriding the
1818 * type when the destination is the null register is necessary but
1819 * not sufficient by itself.
1821 assert(dst
.nr
== BRW_ARF_NULL
);
1822 dst
.type
= BRW_REGISTER_TYPE_D
;
1824 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1826 case BRW_OPCODE_SEL
:
1827 brw_SEL(p
, dst
, src
[0], src
[1]);
1829 case BRW_OPCODE_BFREV
:
1830 assert(devinfo
->gen
>= 7);
1831 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1832 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1834 case BRW_OPCODE_FBH
:
1835 assert(devinfo
->gen
>= 7);
1836 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1838 case BRW_OPCODE_FBL
:
1839 assert(devinfo
->gen
>= 7);
1840 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1841 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1843 case BRW_OPCODE_LZD
:
1844 brw_LZD(p
, dst
, src
[0]);
1846 case BRW_OPCODE_CBIT
:
1847 assert(devinfo
->gen
>= 7);
1848 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1849 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1851 case BRW_OPCODE_ADDC
:
1852 assert(devinfo
->gen
>= 7);
1853 brw_ADDC(p
, dst
, src
[0], src
[1]);
1855 case BRW_OPCODE_SUBB
:
1856 assert(devinfo
->gen
>= 7);
1857 brw_SUBB(p
, dst
, src
[0], src
[1]);
1859 case BRW_OPCODE_MAC
:
1860 brw_MAC(p
, dst
, src
[0], src
[1]);
1863 case BRW_OPCODE_BFE
:
1864 assert(devinfo
->gen
>= 7);
1865 if (devinfo
->gen
< 10)
1866 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1867 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1870 case BRW_OPCODE_BFI1
:
1871 assert(devinfo
->gen
>= 7);
1872 brw_BFI1(p
, dst
, src
[0], src
[1]);
1874 case BRW_OPCODE_BFI2
:
1875 assert(devinfo
->gen
>= 7);
1876 if (devinfo
->gen
< 10)
1877 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1878 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1882 if (inst
->src
[0].file
!= BAD_FILE
) {
1883 /* The instruction has an embedded compare (only allowed on gen6) */
1884 assert(devinfo
->gen
== 6);
1885 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1887 brw_IF(p
, brw_inst_exec_size(devinfo
, p
->current
));
1891 case BRW_OPCODE_ELSE
:
1894 case BRW_OPCODE_ENDIF
:
1899 brw_DO(p
, brw_inst_exec_size(devinfo
, p
->current
));
1902 case BRW_OPCODE_BREAK
:
1905 case BRW_OPCODE_CONTINUE
:
1909 case BRW_OPCODE_WHILE
:
1914 case SHADER_OPCODE_RCP
:
1915 case SHADER_OPCODE_RSQ
:
1916 case SHADER_OPCODE_SQRT
:
1917 case SHADER_OPCODE_EXP2
:
1918 case SHADER_OPCODE_LOG2
:
1919 case SHADER_OPCODE_SIN
:
1920 case SHADER_OPCODE_COS
:
1921 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1922 if (devinfo
->gen
>= 6) {
1923 assert(inst
->mlen
== 0);
1924 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
1925 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
1926 src
[0], brw_null_reg());
1928 assert(inst
->mlen
>= 1);
1929 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
1931 brw_math_function(inst
->opcode
),
1932 inst
->base_mrf
, src
[0],
1933 BRW_MATH_PRECISION_FULL
);
1936 case SHADER_OPCODE_INT_QUOTIENT
:
1937 case SHADER_OPCODE_INT_REMAINDER
:
1938 case SHADER_OPCODE_POW
:
1939 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1940 if (devinfo
->gen
>= 6) {
1941 assert(inst
->mlen
== 0);
1942 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
1943 inst
->exec_size
== 8);
1944 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1946 assert(inst
->mlen
>= 1);
1947 assert(inst
->exec_size
== 8);
1948 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
1949 inst
->base_mrf
, src
[0],
1950 BRW_MATH_PRECISION_FULL
);
1953 case FS_OPCODE_CINTERP
:
1954 brw_MOV(p
, dst
, src
[0]);
1956 case FS_OPCODE_LINTERP
:
1957 generate_linterp(inst
, dst
, src
);
1959 case FS_OPCODE_PIXEL_X
:
1960 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1961 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1962 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1964 case FS_OPCODE_PIXEL_Y
:
1965 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1966 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1967 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1969 case SHADER_OPCODE_GET_BUFFER_SIZE
:
1970 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
1972 case SHADER_OPCODE_TEX
:
1974 case SHADER_OPCODE_TXD
:
1975 case SHADER_OPCODE_TXF
:
1976 case SHADER_OPCODE_TXF_LZ
:
1977 case SHADER_OPCODE_TXF_CMS
:
1978 case SHADER_OPCODE_TXF_CMS_W
:
1979 case SHADER_OPCODE_TXF_UMS
:
1980 case SHADER_OPCODE_TXF_MCS
:
1981 case SHADER_OPCODE_TXL
:
1982 case SHADER_OPCODE_TXL_LZ
:
1983 case SHADER_OPCODE_TXS
:
1984 case SHADER_OPCODE_LOD
:
1985 case SHADER_OPCODE_TG4
:
1986 case SHADER_OPCODE_TG4_OFFSET
:
1987 case SHADER_OPCODE_SAMPLEINFO
:
1988 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
1990 case FS_OPCODE_DDX_COARSE
:
1991 case FS_OPCODE_DDX_FINE
:
1992 generate_ddx(inst
->opcode
, dst
, src
[0]);
1994 case FS_OPCODE_DDY_COARSE
:
1995 case FS_OPCODE_DDY_FINE
:
1996 generate_ddy(inst
->opcode
, dst
, src
[0]);
1999 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2000 generate_scratch_write(inst
, src
[0]);
2004 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2005 generate_scratch_read(inst
, dst
);
2009 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2010 generate_scratch_read_gen7(inst
, dst
);
2014 case SHADER_OPCODE_MOV_INDIRECT
:
2015 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2018 case SHADER_OPCODE_URB_READ_SIMD8
:
2019 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2020 generate_urb_read(inst
, dst
, src
[0]);
2023 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2024 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2025 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2026 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2027 generate_urb_write(inst
, src
[0]);
2030 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2031 assert(inst
->force_writemask_all
);
2032 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2035 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2036 assert(inst
->force_writemask_all
);
2037 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2040 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2041 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2044 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2045 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2048 case FS_OPCODE_REP_FB_WRITE
:
2049 case FS_OPCODE_FB_WRITE
:
2050 generate_fb_write(inst
, src
[0]);
2053 case FS_OPCODE_FB_READ
:
2054 generate_fb_read(inst
, dst
, src
[0]);
2057 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2058 generate_mov_dispatch_to_flags(inst
);
2061 case FS_OPCODE_DISCARD_JUMP
:
2062 generate_discard_jump(inst
);
2065 case SHADER_OPCODE_SHADER_TIME_ADD
:
2066 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2069 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2070 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2071 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2072 inst
->mlen
, !inst
->dst
.is_null());
2075 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2076 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2077 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2078 inst
->mlen
, src
[2].ud
);
2081 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2082 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2083 brw_untyped_surface_write(p
, src
[0], src
[1],
2084 inst
->mlen
, src
[2].ud
);
2087 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
2088 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2089 brw_byte_scattered_read(p
, dst
, src
[0], src
[1],
2090 inst
->mlen
, src
[2].ud
);
2093 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
2094 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2095 brw_byte_scattered_write(p
, src
[0], src
[1],
2096 inst
->mlen
, src
[2].ud
);
2099 case SHADER_OPCODE_TYPED_ATOMIC
:
2100 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2101 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2102 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null());
2105 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2106 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2107 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2108 inst
->mlen
, src
[2].ud
);
2111 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2112 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2113 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
);
2116 case SHADER_OPCODE_MEMORY_FENCE
:
2117 brw_memory_fence(p
, dst
);
2120 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2121 const struct brw_reg mask
=
2122 brw_stage_has_packed_dispatch(devinfo
, stage
,
2123 prog_data
) ? brw_imm_ud(~0u) :
2124 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2126 brw_find_live_channel(p
, dst
, mask
);
2130 case SHADER_OPCODE_BROADCAST
:
2131 assert(inst
->force_writemask_all
);
2132 brw_broadcast(p
, dst
, src
[0], src
[1]);
2135 case FS_OPCODE_SET_SAMPLE_ID
:
2136 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2139 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2140 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2143 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2144 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2145 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2148 case FS_OPCODE_PLACEHOLDER_HALT
:
2149 /* This is the place where the final HALT needs to be inserted if
2150 * we've emitted any discards. If not, this will emit no code.
2152 if (!patch_discard_jumps_to_fb_writes()) {
2153 if (unlikely(debug_flag
)) {
2154 disasm_info
->use_tail
= true;
2159 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2160 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2161 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2164 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2165 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2166 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2169 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2170 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2171 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2174 case CS_OPCODE_CS_TERMINATE
:
2175 generate_cs_terminate(inst
, src
[0]);
2178 case SHADER_OPCODE_BARRIER
:
2179 generate_barrier(inst
, src
[0]);
2182 case BRW_OPCODE_DIM
:
2183 assert(devinfo
->is_haswell
);
2184 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2185 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2186 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2189 case SHADER_OPCODE_RND_MODE
:
2190 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2191 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2195 unreachable("Unsupported opcode");
2197 case SHADER_OPCODE_LOAD_PAYLOAD
:
2198 unreachable("Should be lowered by lower_load_payload()");
2201 if (multiple_instructions_emitted
)
2204 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2205 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2206 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2207 "emitting more than 1 instruction");
2209 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2211 if (inst
->conditional_mod
)
2212 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2213 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2214 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2218 brw_set_uip_jip(p
, start_offset
);
2220 /* end of program sentinel */
2221 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2226 if (unlikely(debug_flag
))
2228 brw_validate_instructions(devinfo
, p
->store
,
2230 p
->next_insn_offset
,
2233 int before_size
= p
->next_insn_offset
- start_offset
;
2234 brw_compact_instructions(p
, start_offset
, disasm_info
);
2235 int after_size
= p
->next_insn_offset
- start_offset
;
2237 if (unlikely(debug_flag
)) {
2238 fprintf(stderr
, "Native code for %s\n"
2239 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2240 " bytes (%.0f%%)\n",
2241 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2242 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2243 100.0f
* (before_size
- after_size
) / before_size
);
2245 dump_assembly(p
->store
, disasm_info
);
2247 ralloc_free(disasm_info
);
2250 compiler
->shader_debug_log(log_data
,
2251 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2252 "%d:%d spills:fills, Promoted %u constants, "
2253 "compacted %d to %d bytes.",
2254 _mesa_shader_stage_to_abbrev(stage
),
2255 dispatch_width
, before_size
/ 16,
2256 loop_count
, cfg
->cycle_count
, spill_count
,
2257 fill_count
, promoted_constants
, before_size
,
2260 return start_offset
;
2264 fs_generator::get_assembly(unsigned int *assembly_size
)
2266 return brw_get_program(p
, assembly_size
);