2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
34 static enum brw_reg_file
35 brw_file_from_reg(fs_reg
*reg
)
39 return BRW_ARCHITECTURE_REGISTER_FILE
;
42 return BRW_GENERAL_REGISTER_FILE
;
44 return BRW_MESSAGE_REGISTER_FILE
;
46 return BRW_IMMEDIATE_VALUE
;
50 unreachable("not reached");
52 return BRW_ARCHITECTURE_REGISTER_FILE
;
56 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
57 fs_reg
*reg
, bool compressed
)
59 struct brw_reg brw_reg
;
63 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
66 if (reg
->stride
== 0) {
67 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 /* From the Haswell PRM:
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
75 * The maximum width value that could satisfy this restriction is:
77 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
84 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
93 const unsigned width
= MIN2(reg_width
, phys_width
);
94 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
95 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
97 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
98 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
99 * "Each DF (Double Float) operand uses an element size of 4 rather
100 * than 8 and all regioning parameters are twice what the values
101 * would be based on the true element size: ExecSize, Width,
102 * HorzStride, and VertStride. Each DF operand uses a pair of
103 * channels and all masking and swizzing should be adjusted
106 * From the IvyBridge PRM (Special Requirements for Handling Double
107 * Precision Data Types, page 71):
108 * "In Align1 mode, all regioning parameters like stride, execution
109 * size, and width must use the syntax of a pair of packed
110 * floats. The offsets for these data types must be 64-bit
111 * aligned. The execution size and regioning parameters are in terms
114 * Summarized: when handling DF-typed arguments, ExecSize,
115 * VertStride, and Width must be doubled.
117 * It applies to BayTrail too.
119 if (type_sz(reg
->type
) == 8) {
121 if (brw_reg
.vstride
> 0)
123 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
126 /* When converting from DF->F, we set the destination stride to 2
127 * because each d2f conversion implicitly writes 2 floats, being
128 * the first one the converted value. IVB/BYT actually writes two
129 * F components per SIMD channel, and every other component is
130 * filled with garbage.
132 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
133 type_sz(inst
->dst
.type
) < 8) {
134 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
140 brw_reg
= retype(brw_reg
, reg
->type
);
141 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
142 brw_reg
.abs
= reg
->abs
;
143 brw_reg
.negate
= reg
->negate
;
148 assert(reg
->offset
== 0);
149 brw_reg
= reg
->as_brw_reg();
152 /* Probably unused. */
153 brw_reg
= brw_null_reg();
157 unreachable("not reached");
160 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
161 * region, but on IVB and BYT DF regions must be programmed in terms of
162 * floats. A <0,2,1> region accomplishes this.
164 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
165 type_sz(reg
->type
) == 8 &&
166 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
167 brw_reg
.width
== BRW_WIDTH_1
&&
168 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
169 brw_reg
.width
= BRW_WIDTH_2
;
170 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
176 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
178 struct brw_stage_prog_data
*prog_data
,
179 unsigned promoted_constants
,
180 bool runtime_check_aads_emit
,
181 gl_shader_stage stage
)
183 : compiler(compiler
), log_data(log_data
),
184 devinfo(compiler
->devinfo
),
185 prog_data(prog_data
),
186 promoted_constants(promoted_constants
),
187 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
188 stage(stage
), mem_ctx(mem_ctx
)
190 p
= rzalloc(mem_ctx
, struct brw_codegen
);
191 brw_init_codegen(devinfo
, p
, mem_ctx
);
193 /* In the FS code generator, we are very careful to ensure that we always
194 * set the right execution size so we don't need the EU code to "help" us
195 * by trying to infer it. Sometimes, it infers the wrong thing.
197 p
->automatic_exec_sizes
= false;
200 fs_generator::~fs_generator()
204 class ip_record
: public exec_node
{
206 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
217 fs_generator::patch_discard_jumps_to_fb_writes()
219 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
222 int scale
= brw_jump_scale(p
->devinfo
);
224 /* There is a somewhat strange undocumented requirement of using
225 * HALT, according to the simulator. If some channel has HALTed to
226 * a particular UIP, then by the end of the program, every channel
227 * must have HALTed to that UIP. Furthermore, the tracking is a
228 * stack, so you can't do the final halt of a UIP after starting
229 * halting to a new UIP.
231 * Symptoms of not emitting this instruction on actual hardware
232 * included GPU hangs and sparkly rendering on the piglit discard
235 brw_inst
*last_halt
= gen6_HALT(p
);
236 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
237 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
241 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
242 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
244 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
245 /* HALT takes a half-instruction distance from the pre-incremented IP. */
246 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
249 this->discard_halt_patches
.make_empty();
254 fs_generator::fire_fb_write(fs_inst
*inst
,
255 struct brw_reg payload
,
256 struct brw_reg implied_header
,
259 uint32_t msg_control
;
261 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
263 if (devinfo
->gen
< 6) {
264 brw_push_insn_state(p
);
265 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
266 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
267 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
268 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
269 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
270 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
271 brw_pop_insn_state(p
);
274 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
275 assert(inst
->group
== 0 && inst
->exec_size
== 16);
276 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
278 } else if (prog_data
->dual_src_blend
) {
279 assert(inst
->exec_size
== 8);
281 if (inst
->group
% 16 == 0)
282 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
283 else if (inst
->group
% 16 == 8)
284 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
286 unreachable("Invalid dual-source FB write instruction group");
289 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
291 if (inst
->exec_size
== 16)
292 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
293 else if (inst
->exec_size
== 8)
294 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
296 unreachable("Invalid FB write execution size");
299 /* We assume render targets start at 0, because headerless FB write
300 * messages set "Render Target Index" to 0. Using a different binding
301 * table index would make it impossible to use headerless messages.
303 const uint32_t surf_index
= inst
->target
;
305 brw_inst
*insn
= brw_fb_WRITE(p
,
307 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
314 inst
->header_size
!= 0);
316 if (devinfo
->gen
>= 6)
317 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
319 brw_mark_surface_used(&prog_data
->base
, surf_index
);
323 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
325 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
326 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
329 const struct brw_reg implied_header
=
330 devinfo
->gen
< 6 ? payload
: brw_null_reg();
332 if (inst
->base_mrf
>= 0)
333 payload
= brw_message_reg(inst
->base_mrf
);
335 if (!runtime_check_aads_emit
) {
336 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
338 /* This can only happen in gen < 6 */
339 assert(devinfo
->gen
< 6);
341 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
343 /* Check runtime bit to detect if we have to send AA data or not */
344 brw_push_insn_state(p
);
345 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
346 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
349 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
351 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
353 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
354 brw_pop_insn_state(p
);
356 /* Don't send AA data */
357 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
359 brw_land_fwd_jump(p
, jmp
);
360 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
365 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
366 struct brw_reg payload
)
368 assert(inst
->size_written
% REG_SIZE
== 0);
369 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
370 /* We assume that render targets start at binding table index 0. */
371 const unsigned surf_index
= inst
->target
;
373 gen9_fb_READ(p
, dst
, payload
, surf_index
,
374 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
375 prog_data
->persample_dispatch
);
377 brw_mark_surface_used(&prog_data
->base
, surf_index
);
381 fs_generator::generate_mov_indirect(fs_inst
*inst
,
384 struct brw_reg indirect_byte_offset
)
386 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
387 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
388 assert(!reg
.abs
&& !reg
.negate
);
389 assert(reg
.type
== dst
.type
);
391 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
393 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
394 imm_byte_offset
+= indirect_byte_offset
.ud
;
396 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
397 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
398 brw_MOV(p
, dst
, reg
);
400 /* Prior to Broadwell, there are only 8 address registers. */
401 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
403 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
404 struct brw_reg addr
= vec8(brw_address_reg(0));
406 /* The destination stride of an instruction (in bytes) must be greater
407 * than or equal to the size of the rest of the instruction. Since the
408 * address register is of type UW, we can't use a D-type instruction.
409 * In order to get around this, re retype to UW and use a stride.
411 indirect_byte_offset
=
412 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
414 /* There are a number of reasons why we don't use the base offset here.
415 * One reason is that the field is only 9 bits which means we can only
416 * use it to access the first 16 GRFs. Also, from the Haswell PRM
417 * section "Register Region Restrictions":
419 * "The lower bits of the AddressImmediate must not overflow to
420 * change the register address. The lower 5 bits of Address
421 * Immediate when added to lower 5 bits of address register gives
422 * the sub-register offset. The upper bits of Address Immediate
423 * when added to upper bits of address register gives the register
424 * address. Any overflow from sub-register offset is dropped."
426 * Since the indirect may cause us to cross a register boundary, this
427 * makes the base offset almost useless. We could try and do something
428 * clever where we use a actual base offset if base_offset % 32 == 0 but
429 * that would mean we were generating different code depending on the
430 * base offset. Instead, for the sake of consistency, we'll just do the
431 * add ourselves. This restriction is only listed in the Haswell PRM
432 * but empirical testing indicates that it applies on all older
433 * generations and is lifted on Broadwell.
435 * In the end, while base_offset is nice to look at in the generated
436 * code, using it saves us 0 instructions and would require quite a bit
437 * of case-by-case work. It's just not worth it.
439 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
441 if (type_sz(reg
.type
) > 4 &&
442 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
443 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
444 /* IVB has an issue (which we found empirically) where it reads two
445 * address register components per channel for indirectly addressed
448 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
450 * "When source or destination datatype is 64b or operation is
451 * integer DWord multiply, indirect addressing must not be used."
453 * To work around both of these, we do two integer MOVs insead of one
454 * 64-bit MOV. Because no double value should ever cross a register
455 * boundary, it's safe to use the immediate offset in the indirect
456 * here to handle adding 4 bytes to the offset and avoid the extra
457 * ADD to the register file.
459 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
460 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
461 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
462 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
464 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
466 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
468 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
469 !inst
->get_next()->is_tail_sentinel() &&
470 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
471 /* From the Sandybridge PRM:
473 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
474 * instruction that “indexed/indirect” source AND is followed
475 * by a send, the instruction requires a “Switch”. This is to
476 * avoid race condition where send may dispatch before MRF is
479 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
486 fs_generator::generate_shuffle(fs_inst
*inst
,
491 /* Ivy bridge has some strange behavior that makes this a real pain to
492 * implement for 64-bit values so we just don't bother.
494 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
496 /* Because we're using the address register, we're limited to 8-wide
497 * execution on gen7. On gen8, we're limited to 16-wide by the address
498 * register file and 8-wide for 64-bit types. We could try and make this
499 * instruction splittable higher up in the compiler but that gets weird
500 * because it reads all of the channels regardless of execution size. It's
501 * easier just to split it here.
503 const unsigned lower_width
=
504 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
505 8 : MIN2(16, inst
->exec_size
);
507 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
508 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
509 brw_set_default_group(p
, group
);
511 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
512 idx
.file
== BRW_IMMEDIATE_VALUE
) {
513 /* Trivial, the source is already uniform or the index is a constant.
514 * We will typically not get here if the optimizer is doing its job,
515 * but asserting would be mean.
517 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
518 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
520 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
521 struct brw_reg addr
= vec8(brw_address_reg(0));
523 struct brw_reg group_idx
= suboffset(idx
, group
);
525 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
526 /* Things get grumpy if the register is too wide. */
531 assert(type_sz(group_idx
.type
) <= 4);
532 if (type_sz(group_idx
.type
) == 4) {
533 /* The destination stride of an instruction (in bytes) must be
534 * greater than or equal to the size of the rest of the
535 * instruction. Since the address register is of type UW, we
536 * can't use a D-type instruction. In order to get around this,
537 * re retype to UW and use a stride.
539 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
542 /* Take into account the component size and horizontal stride. */
543 assert(src
.vstride
== src
.hstride
+ src
.width
);
544 brw_SHL(p
, addr
, group_idx
,
545 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
548 /* Add on the register start offset */
549 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
551 if (type_sz(src
.type
) > 4 &&
552 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
553 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
554 /* IVB has an issue (which we found empirically) where it reads
555 * two address register components per channel for indirectly
556 * addressed 64-bit sources.
558 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
560 * "When source or destination datatype is 64b or operation is
561 * integer DWord multiply, indirect addressing must not be
564 * To work around both of these, we do two integer MOVs insead of
565 * one 64-bit MOV. Because no double value should ever cross a
566 * register boundary, it's safe to use the immediate offset in the
567 * indirect here to handle adding 4 bytes to the offset and avoid
568 * the extra ADD to the register file.
570 struct brw_reg gdst
= suboffset(dst
, group
);
571 struct brw_reg dst_d
= retype(spread(gdst
, 2),
572 BRW_REGISTER_TYPE_D
);
574 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
575 brw_MOV(p
, byte_offset(dst_d
, 4),
576 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
578 brw_MOV(p
, suboffset(dst
, group
),
579 retype(brw_VxH_indirect(0, 0), src
.type
));
586 fs_generator::generate_urb_read(fs_inst
*inst
,
588 struct brw_reg header
)
590 assert(inst
->size_written
% REG_SIZE
== 0);
591 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
592 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
594 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
595 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
596 brw_set_src0(p
, send
, header
);
597 brw_set_src1(p
, send
, brw_imm_ud(0u));
599 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
600 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
602 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
603 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
605 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
606 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
607 brw_inst_set_header_present(p
->devinfo
, send
, true);
608 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
612 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
616 /* WaClearTDRRegBeforeEOTForNonPS.
618 * WA: Clear tdr register before send EOT in all non-PS shader kernels
620 * mov(8) tdr0:ud 0x0:ud {NoMask}"
622 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
623 brw_push_insn_state(p
);
624 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
625 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
626 brw_pop_insn_state(p
);
629 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
631 brw_set_dest(p
, insn
, brw_null_reg());
632 brw_set_src0(p
, insn
, payload
);
633 brw_set_src1(p
, insn
, brw_imm_d(0));
635 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
636 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
638 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
639 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
640 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
642 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
643 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
644 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
646 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
647 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
648 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
649 brw_inst_set_header_present(p
->devinfo
, insn
, true);
650 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
654 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
656 struct brw_inst
*insn
;
658 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
660 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
661 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
662 brw_set_src1(p
, insn
, brw_imm_d(0));
664 /* Terminate a compute shader by sending a message to the thread spawner.
666 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
667 brw_inst_set_mlen(devinfo
, insn
, 1);
668 brw_inst_set_rlen(devinfo
, insn
, 0);
669 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
670 brw_inst_set_header_present(devinfo
, insn
, false);
672 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
673 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
675 /* Note that even though the thread has a URB resource associated with it,
676 * we set the "do not dereference URB" bit, because the URB resource is
677 * managed by the fixed-function unit, so it will free it automatically.
679 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
681 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
685 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
692 fs_generator::generate_linterp(fs_inst
*inst
,
693 struct brw_reg dst
, struct brw_reg
*src
)
697 * -----------------------------------
698 * | src1+0 | src1+1 | src1+2 | src1+3 |
699 * |-----------------------------------|
700 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
701 * -----------------------------------
703 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
705 * -----------------------------------
706 * | src1+0 | src1+1 | src1+2 | src1+3 |
707 * |-----------------------------------|
708 * |(x0, x1)|(y0, y1)| | | in SIMD8
709 * |-----------------------------------|
710 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
711 * -----------------------------------
713 * See also: emit_interpolation_setup_gen4().
715 struct brw_reg delta_x
= src
[0];
716 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
717 struct brw_reg interp
= src
[1];
720 if (devinfo
->gen
>= 11) {
721 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_NF
);
722 struct brw_reg dwP
= suboffset(interp
, 0);
723 struct brw_reg dwQ
= suboffset(interp
, 1);
724 struct brw_reg dwR
= suboffset(interp
, 3);
726 brw_push_insn_state(p
);
727 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
729 if (inst
->exec_size
== 8) {
730 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
731 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_y
, 0), dwQ
);
733 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
735 /* brw_set_default_saturate() is called before emitting instructions,
736 * so the saturate bit is set in each instruction, so we need to unset
737 * it on the first instruction of each pair.
739 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
741 brw_set_default_group(p
, inst
->group
);
742 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
743 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_x
, 1), dwQ
);
745 brw_set_default_group(p
, inst
->group
+ 8);
746 i
[2] = brw_MAD(p
, acc
, dwR
, offset(delta_y
, 0), dwP
);
747 i
[3] = brw_MAD(p
, offset(dst
, 1), acc
, offset(delta_y
, 1), dwQ
);
749 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
750 brw_inst_set_cond_modifier(p
->devinfo
, i
[3], inst
->conditional_mod
);
752 /* brw_set_default_saturate() is called before emitting instructions,
753 * so the saturate bit is set in each instruction, so we need to unset
754 * it on the first instruction of each pair.
756 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
757 brw_inst_set_saturate(p
->devinfo
, i
[2], false);
760 brw_pop_insn_state(p
);
763 } else if (devinfo
->has_pln
) {
764 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
765 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
767 * "[DevSNB]:<src1> must be even register aligned.
769 * This restriction is lifted on Ivy Bridge.
771 * This means that we need to split PLN into LINE+MAC on-the-fly.
772 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
773 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
774 * coordinate registers are laid out differently so we leave it as a
775 * SIMD16 instruction.
777 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
778 assert(inst
->group
% 16 == 0);
780 brw_push_insn_state(p
);
781 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
783 /* Thanks to two accumulators, we can emit all the LINEs and then all
784 * the MACs. This improves parallelism a bit.
786 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
787 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
788 offset(delta_x
, g
* 2));
789 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
791 /* LINE writes the accumulator automatically on gen4-5. On Sandy
792 * Bridge and later, we have to explicitly enable it.
794 if (devinfo
->gen
>= 6)
795 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
797 /* brw_set_default_saturate() is called before emitting
798 * instructions, so the saturate bit is set in each instruction,
799 * so we need to unset it on the LINE instructions.
801 brw_inst_set_saturate(p
->devinfo
, line
, false);
804 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
805 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
806 offset(delta_x
, g
* 2 + 1));
807 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
808 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
811 brw_pop_insn_state(p
);
815 brw_PLN(p
, dst
, interp
, delta_x
);
820 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
821 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
823 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
825 /* brw_set_default_saturate() is called before emitting instructions, so
826 * the saturate bit is set in each instruction, so we need to unset it on
827 * the first instruction.
829 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
836 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
839 struct brw_reg surf_index
)
841 assert(devinfo
->gen
>= 7);
842 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
847 switch (inst
->exec_size
) {
849 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
852 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
855 unreachable("Invalid width for texture instruction");
858 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
864 retype(dst
, BRW_REGISTER_TYPE_UW
),
869 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
870 rlen
, /* response length */
872 inst
->header_size
> 0,
874 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
876 brw_mark_surface_used(prog_data
, surf_index
.ud
);
880 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
881 struct brw_reg surface_index
,
882 struct brw_reg sampler_index
)
884 assert(inst
->size_written
% REG_SIZE
== 0);
887 uint32_t return_format
;
888 bool is_combined_send
= inst
->eot
;
890 /* Sampler EOT message of less than the dispatch width would kill the
891 * thread prematurely.
893 assert(!is_combined_send
|| inst
->exec_size
== dispatch_width
);
896 case BRW_REGISTER_TYPE_D
:
897 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
899 case BRW_REGISTER_TYPE_UD
:
900 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
903 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
907 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
908 * is set as part of the message descriptor. On gen4, the PRM seems to
909 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
910 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
911 * gone from the message descriptor entirely and you just get UINT32 all
912 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
913 * just stomp it to UINT32 all the time.
915 if (inst
->opcode
== SHADER_OPCODE_TXS
)
916 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
918 switch (inst
->exec_size
) {
920 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
923 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
926 unreachable("Invalid width for texture instruction");
929 if (devinfo
->gen
>= 5) {
930 switch (inst
->opcode
) {
931 case SHADER_OPCODE_TEX
:
932 if (inst
->shadow_compare
) {
933 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
935 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
939 if (inst
->shadow_compare
) {
940 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
942 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
945 case SHADER_OPCODE_TXL
:
946 if (inst
->shadow_compare
) {
947 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
949 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
952 case SHADER_OPCODE_TXL_LZ
:
953 assert(devinfo
->gen
>= 9);
954 if (inst
->shadow_compare
) {
955 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
;
957 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
960 case SHADER_OPCODE_TXS
:
961 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
963 case SHADER_OPCODE_TXD
:
964 if (inst
->shadow_compare
) {
965 /* Gen7.5+. Otherwise, lowered in NIR */
966 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
967 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
969 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
972 case SHADER_OPCODE_TXF
:
973 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
975 case SHADER_OPCODE_TXF_LZ
:
976 assert(devinfo
->gen
>= 9);
977 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
979 case SHADER_OPCODE_TXF_CMS_W
:
980 assert(devinfo
->gen
>= 9);
981 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
983 case SHADER_OPCODE_TXF_CMS
:
984 if (devinfo
->gen
>= 7)
985 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
987 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
989 case SHADER_OPCODE_TXF_UMS
:
990 assert(devinfo
->gen
>= 7);
991 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
993 case SHADER_OPCODE_TXF_MCS
:
994 assert(devinfo
->gen
>= 7);
995 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
997 case SHADER_OPCODE_LOD
:
998 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1000 case SHADER_OPCODE_TG4
:
1001 if (inst
->shadow_compare
) {
1002 assert(devinfo
->gen
>= 7);
1003 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
1005 assert(devinfo
->gen
>= 6);
1006 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1009 case SHADER_OPCODE_TG4_OFFSET
:
1010 assert(devinfo
->gen
>= 7);
1011 if (inst
->shadow_compare
) {
1012 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
1014 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
1017 case SHADER_OPCODE_SAMPLEINFO
:
1018 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1021 unreachable("not reached");
1024 switch (inst
->opcode
) {
1025 case SHADER_OPCODE_TEX
:
1026 /* Note that G45 and older determines shadow compare and dispatch width
1027 * from message length for most messages.
1029 if (inst
->exec_size
== 8) {
1030 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1031 if (inst
->shadow_compare
) {
1032 assert(inst
->mlen
== 6);
1034 assert(inst
->mlen
<= 4);
1037 if (inst
->shadow_compare
) {
1038 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1039 assert(inst
->mlen
== 9);
1041 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1042 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1047 if (inst
->shadow_compare
) {
1048 assert(inst
->exec_size
== 8);
1049 assert(inst
->mlen
== 6);
1050 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1052 assert(inst
->mlen
== 9);
1053 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1054 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1057 case SHADER_OPCODE_TXL
:
1058 if (inst
->shadow_compare
) {
1059 assert(inst
->exec_size
== 8);
1060 assert(inst
->mlen
== 6);
1061 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1063 assert(inst
->mlen
== 9);
1064 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1065 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1068 case SHADER_OPCODE_TXD
:
1069 /* There is no sample_d_c message; comparisons are done manually */
1070 assert(inst
->exec_size
== 8);
1071 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1072 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1074 case SHADER_OPCODE_TXF
:
1075 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1076 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1077 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1079 case SHADER_OPCODE_TXS
:
1080 assert(inst
->mlen
== 3);
1081 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1082 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1085 unreachable("not reached");
1088 assert(msg_type
!= -1);
1090 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1094 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
1095 src
.file
== BRW_GENERAL_REGISTER_FILE
);
1097 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1099 /* Load the message header if present. If there's a texture offset,
1100 * we need to set it up explicitly and load the offset bitfield.
1101 * Otherwise, we can use an implied move from g0 to the first message reg.
1103 if (inst
->header_size
!= 0 && devinfo
->gen
< 7) {
1104 if (devinfo
->gen
< 6 && !inst
->offset
) {
1105 /* Set up an implied move from g0 to the MRF. */
1106 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1108 assert(inst
->base_mrf
!= -1);
1109 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1111 brw_push_insn_state(p
);
1112 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1113 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1114 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1115 /* Explicitly set up the message header by copying g0 to the MRF. */
1116 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1118 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1120 /* Set the offset bits in DWord 2. */
1121 brw_MOV(p
, get_element_ud(header_reg
, 2),
1122 brw_imm_ud(inst
->offset
));
1125 brw_pop_insn_state(p
);
1129 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
1130 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
1131 ? prog_data
->binding_table
.gather_texture_start
1132 : prog_data
->binding_table
.texture_start
;
1134 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
1135 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
1136 uint32_t surface
= surface_index
.ud
;
1137 uint32_t sampler
= sampler_index
.ud
;
1140 retype(dst
, BRW_REGISTER_TYPE_UW
),
1143 surface
+ base_binding_table_index
,
1146 inst
->size_written
/ REG_SIZE
,
1148 inst
->header_size
!= 0,
1152 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
1154 /* Non-const sampler index */
1156 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1157 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
1158 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
1160 brw_push_insn_state(p
);
1161 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1162 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1163 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1165 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
1166 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
1168 if (sampler_reg
.file
== BRW_IMMEDIATE_VALUE
) {
1169 brw_OR(p
, addr
, surface_reg
, brw_imm_ud(sampler_reg
.ud
<< 8));
1171 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
1172 brw_OR(p
, addr
, addr
, surface_reg
);
1175 if (base_binding_table_index
)
1176 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
1177 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
1179 brw_pop_insn_state(p
);
1181 /* dst = send(offset, a0.0 | <descriptor>) */
1182 brw_send_indirect_message(
1183 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
,
1184 brw_message_desc(devinfo
, inst
->mlen
, inst
->size_written
/ REG_SIZE
,
1185 inst
->header_size
) |
1186 brw_sampler_desc(devinfo
,
1193 /* visitor knows more than we do about the surface limit required,
1194 * so has already done marking.
1198 if (is_combined_send
) {
1199 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
1200 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
1205 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1208 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1210 * Ideally, we want to produce:
1213 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1214 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1215 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1216 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1217 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1218 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1219 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1220 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1222 * and add another set of two more subspans if in 16-pixel dispatch mode.
1224 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1225 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1226 * pair. But the ideal approximation may impose a huge performance cost on
1227 * sample_d. On at least Haswell, sample_d instruction does some
1228 * optimizations if the same LOD is used for all pixels in the subspan.
1230 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1231 * appropriate swizzling.
1234 fs_generator::generate_ddx(const fs_inst
*inst
,
1235 struct brw_reg dst
, struct brw_reg src
)
1237 unsigned vstride
, width
;
1239 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1240 /* produce accurate derivatives */
1241 vstride
= BRW_VERTICAL_STRIDE_2
;
1242 width
= BRW_WIDTH_2
;
1244 /* replicate the derivative at the top-left pixel to other pixels */
1245 vstride
= BRW_VERTICAL_STRIDE_4
;
1246 width
= BRW_WIDTH_4
;
1249 struct brw_reg src0
= src
;
1250 struct brw_reg src1
= src
;
1252 src0
.subnr
= sizeof(float);
1253 src0
.vstride
= vstride
;
1255 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1256 src1
.vstride
= vstride
;
1258 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1260 brw_ADD(p
, dst
, src0
, negate(src1
));
1263 /* The negate_value boolean is used to negate the derivative computation for
1264 * FBOs, since they place the origin at the upper left instead of the lower
1268 fs_generator::generate_ddy(const fs_inst
*inst
,
1269 struct brw_reg dst
, struct brw_reg src
)
1271 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1272 /* produce accurate derivatives */
1273 if (devinfo
->gen
>= 11) {
1274 src
= stride(src
, 0, 2, 1);
1275 struct brw_reg src_0
= byte_offset(src
, 0 * sizeof(float));
1276 struct brw_reg src_2
= byte_offset(src
, 2 * sizeof(float));
1277 struct brw_reg src_4
= byte_offset(src
, 4 * sizeof(float));
1278 struct brw_reg src_6
= byte_offset(src
, 6 * sizeof(float));
1279 struct brw_reg src_8
= byte_offset(src
, 8 * sizeof(float));
1280 struct brw_reg src_10
= byte_offset(src
, 10 * sizeof(float));
1281 struct brw_reg src_12
= byte_offset(src
, 12 * sizeof(float));
1282 struct brw_reg src_14
= byte_offset(src
, 14 * sizeof(float));
1284 struct brw_reg dst_0
= byte_offset(dst
, 0 * sizeof(float));
1285 struct brw_reg dst_4
= byte_offset(dst
, 4 * sizeof(float));
1286 struct brw_reg dst_8
= byte_offset(dst
, 8 * sizeof(float));
1287 struct brw_reg dst_12
= byte_offset(dst
, 12 * sizeof(float));
1289 brw_push_insn_state(p
);
1290 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1292 brw_ADD(p
, dst_0
, negate(src_0
), src_2
);
1293 brw_ADD(p
, dst_4
, negate(src_4
), src_6
);
1295 if (inst
->exec_size
== 16) {
1296 brw_ADD(p
, dst_8
, negate(src_8
), src_10
);
1297 brw_ADD(p
, dst_12
, negate(src_12
), src_14
);
1300 brw_pop_insn_state(p
);
1302 struct brw_reg src0
= stride(src
, 4, 4, 1);
1303 struct brw_reg src1
= stride(src
, 4, 4, 1);
1304 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1305 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1307 brw_push_insn_state(p
);
1308 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1309 brw_ADD(p
, dst
, negate(src0
), src1
);
1310 brw_pop_insn_state(p
);
1313 /* replicate the derivative at the top-left pixel to other pixels */
1314 struct brw_reg src0
= stride(src
, 4, 4, 0);
1315 struct brw_reg src1
= stride(src
, 4, 4, 0);
1316 src0
.subnr
= 0 * sizeof(float);
1317 src1
.subnr
= 2 * sizeof(float);
1319 brw_ADD(p
, dst
, negate(src0
), src1
);
1324 fs_generator::generate_discard_jump(fs_inst
*)
1326 assert(devinfo
->gen
>= 6);
1328 /* This HALT will be patched up at FB write time to point UIP at the end of
1329 * the program, and at brw_uip_jip() JIP will be set to the end of the
1330 * current block (or the program).
1332 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1337 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1339 /* The 32-wide messages only respect the first 16-wide half of the channel
1340 * enable signals which are replicated identically for the second group of
1341 * 16 channels, so we cannot use them unless the write is marked
1342 * force_writemask_all.
1344 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1345 MIN2(16, inst
->exec_size
);
1346 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1347 assert(inst
->mlen
!= 0);
1349 brw_push_insn_state(p
);
1350 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1351 brw_set_default_compression(p
, lower_size
> 8);
1353 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1354 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1356 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1357 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1359 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1361 inst
->offset
+ block_size
* REG_SIZE
* i
);
1364 brw_pop_insn_state(p
);
1368 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1370 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1371 assert(inst
->mlen
!= 0);
1373 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1374 inst
->exec_size
/ 8, inst
->offset
);
1378 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1380 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1382 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1386 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1388 struct brw_reg index
,
1389 struct brw_reg offset
)
1391 assert(type_sz(dst
.type
) == 4);
1392 assert(inst
->mlen
!= 0);
1394 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1395 index
.type
== BRW_REGISTER_TYPE_UD
);
1396 uint32_t surf_index
= index
.ud
;
1398 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1399 offset
.type
== BRW_REGISTER_TYPE_UD
);
1400 uint32_t read_offset
= offset
.ud
;
1402 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1403 read_offset
, surf_index
);
1407 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1409 struct brw_reg index
,
1410 struct brw_reg payload
)
1412 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1413 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1414 assert(type_sz(dst
.type
) == 4);
1416 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1417 const uint32_t surf_index
= index
.ud
;
1419 brw_push_insn_state(p
);
1420 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1421 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1422 brw_pop_insn_state(p
);
1424 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1425 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1426 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1427 brw_set_desc(p
, send
,
1428 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1430 brw_dp_read_desc(devinfo
, surf_index
,
1431 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1432 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1433 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1436 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1438 brw_push_insn_state(p
);
1439 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1441 /* a0.0 = surf_index & 0xff */
1442 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1443 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1444 brw_set_dest(p
, insn_and
, addr
);
1445 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1446 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1448 /* dst = send(payload, a0.0 | <descriptor>) */
1449 brw_send_indirect_message(
1450 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1451 retype(dst
, BRW_REGISTER_TYPE_UD
),
1452 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1453 brw_message_desc(devinfo
, 1,
1454 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1455 brw_dp_read_desc(devinfo
, 0 /* surface */,
1456 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1457 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1458 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1460 brw_pop_insn_state(p
);
1465 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1467 struct brw_reg index
)
1469 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1470 assert(inst
->header_size
!= 0);
1473 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1474 index
.type
== BRW_REGISTER_TYPE_UD
);
1475 uint32_t surf_index
= index
.ud
;
1477 uint32_t simd_mode
, rlen
, msg_type
;
1478 if (inst
->exec_size
== 16) {
1479 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1482 assert(inst
->exec_size
== 8);
1483 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1487 if (devinfo
->gen
>= 5)
1488 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1490 /* We always use the SIMD16 message so that we only have to load U, and
1493 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1494 assert(inst
->mlen
== 3);
1495 assert(inst
->size_written
== 8 * REG_SIZE
);
1497 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1500 struct brw_reg header
= brw_vec8_grf(0, 0);
1501 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1503 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1504 brw_inst_set_compression(devinfo
, send
, false);
1505 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1506 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1507 brw_set_src0(p
, send
, header
);
1508 if (devinfo
->gen
< 6)
1509 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1511 /* Our surface is set up as floats, regardless of what actual data is
1514 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1515 brw_set_desc(p
, send
,
1516 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1517 brw_sampler_desc(devinfo
, surf_index
,
1518 0, /* sampler (unused) */
1519 msg_type
, simd_mode
, return_format
));
1523 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1525 struct brw_reg index
,
1526 struct brw_reg offset
)
1528 assert(devinfo
->gen
>= 7);
1529 /* Varying-offset pull constant loads are treated as a normal expression on
1530 * gen7, so the fact that it's a send message is hidden at the IR level.
1532 assert(inst
->header_size
== 0);
1534 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1536 uint32_t simd_mode
, rlen
;
1537 if (inst
->exec_size
== 16) {
1539 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1541 assert(inst
->exec_size
== 8);
1543 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1546 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1548 uint32_t surf_index
= index
.ud
;
1550 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1551 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1552 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1553 brw_set_src0(p
, send
, offset
);
1554 brw_set_desc(p
, send
,
1555 brw_message_desc(devinfo
, inst
->mlen
, rlen
, false) |
1556 brw_sampler_desc(devinfo
, surf_index
,
1557 0, /* LD message ignores sampler unit */
1558 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1563 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1565 brw_push_insn_state(p
);
1566 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1568 /* a0.0 = surf_index & 0xff */
1569 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1570 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1571 brw_set_dest(p
, insn_and
, addr
);
1572 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1573 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1575 brw_pop_insn_state(p
);
1577 /* dst = send(offset, a0.0 | <descriptor>) */
1578 brw_send_indirect_message(
1579 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1581 brw_message_desc(devinfo
, inst
->mlen
, rlen
, false) |
1582 brw_sampler_desc(devinfo
,
1585 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1592 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1595 struct brw_reg msg_data
,
1598 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1599 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1600 assert(inst
->size_written
% REG_SIZE
== 0);
1602 brw_pixel_interpolator_query(p
,
1603 retype(dst
, BRW_REGISTER_TYPE_UW
),
1604 /* If we don't have a payload, what we send doesn't matter */
1605 has_payload
? src
: brw_vec8_grf(0, 0),
1606 inst
->pi_noperspective
,
1609 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1610 inst
->size_written
/ REG_SIZE
);
1613 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1614 * the ADD instruction.
1617 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1619 struct brw_reg src0
,
1620 struct brw_reg src1
)
1622 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1623 dst
.type
== BRW_REGISTER_TYPE_UD
);
1624 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1625 src0
.type
== BRW_REGISTER_TYPE_UD
);
1627 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1628 const unsigned lower_size
= MIN2(inst
->exec_size
,
1629 devinfo
->gen
>= 8 ? 16 : 8);
1631 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1632 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1633 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1634 (i
* lower_size
/ (1 << src0
.width
))) *
1635 type_sz(src0
.type
) / REG_SIZE
),
1636 suboffset(reg
, i
* lower_size
/ 4));
1637 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1638 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1639 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1644 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1649 assert(devinfo
->gen
>= 7);
1650 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1651 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1652 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1654 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1656 * Because this instruction does not have a 16-bit floating-point type,
1657 * the destination data type must be Word (W).
1659 * The destination must be DWord-aligned and specify a horizontal stride
1660 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1661 * each destination channel and the upper word is not modified.
1663 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1665 /* Give each 32-bit channel of dst the form below, where "." means
1669 brw_F32TO16(p
, dst_w
, y
);
1674 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1676 /* And, finally the form of packHalf2x16's output:
1679 brw_F32TO16(p
, dst_w
, x
);
1683 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1687 assert(devinfo
->gen
>= 7);
1688 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1689 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1691 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1693 * Because this instruction does not have a 16-bit floating-point type,
1694 * the source data type must be Word (W). The destination type must be
1697 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1699 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1700 * For the Y case, we wish to access only the upper word; therefore
1701 * a 16-bit subregister offset is needed.
1703 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1704 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1705 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1708 brw_F16TO32(p
, dst
, src_w
);
1712 fs_generator::generate_shader_time_add(fs_inst
*,
1713 struct brw_reg payload
,
1714 struct brw_reg offset
,
1715 struct brw_reg value
)
1717 assert(devinfo
->gen
>= 7);
1718 brw_push_insn_state(p
);
1719 brw_set_default_mask_control(p
, true);
1721 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1722 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1724 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1727 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1728 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1729 value
.width
= BRW_WIDTH_1
;
1730 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1731 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1733 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1736 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1737 * case, and we don't really care about squeezing every bit of performance
1738 * out of this path, so we just emit the MOVs from here.
1740 brw_MOV(p
, payload_offset
, offset
);
1741 brw_MOV(p
, payload_value
, value
);
1742 brw_shader_time_add(p
, payload
,
1743 prog_data
->binding_table
.shader_time_start
);
1744 brw_pop_insn_state(p
);
1746 brw_mark_surface_used(prog_data
,
1747 prog_data
->binding_table
.shader_time_start
);
1751 fs_generator::enable_debug(const char *shader_name
)
1754 this->shader_name
= shader_name
;
1758 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1760 /* align to 64 byte boundary. */
1761 while (p
->next_insn_offset
% 64)
1764 this->dispatch_width
= dispatch_width
;
1766 int start_offset
= p
->next_insn_offset
;
1767 int spill_count
= 0, fill_count
= 0;
1770 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1772 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1773 struct brw_reg src
[3], dst
;
1774 unsigned int last_insn_offset
= p
->next_insn_offset
;
1775 bool multiple_instructions_emitted
= false;
1777 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1778 * "Register Region Restrictions" section: for BDW, SKL:
1780 * "A POW/FDIV operation must not be followed by an instruction
1781 * that requires two destination registers."
1783 * The documentation is often lacking annotations for Atom parts,
1784 * and empirically this affects CHV as well.
1786 if (devinfo
->gen
>= 8 &&
1787 devinfo
->gen
<= 9 &&
1789 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1790 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1791 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1793 last_insn_offset
= p
->next_insn_offset
;
1796 if (unlikely(debug_flag
))
1797 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1799 /* If the instruction writes to more than one register, it needs to be
1800 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1801 * hardware figures out by itself what the right compression mode is,
1802 * but we still need to know whether the instruction is compressed to
1803 * set up the source register regions appropriately.
1805 * XXX - This is wrong for instructions that write a single register but
1806 * read more than one which should strictly speaking be treated as
1807 * compressed. For instructions that don't write any registers it
1808 * relies on the destination being a null register of the correct
1809 * type and regioning so the instruction is considered compressed
1810 * or not accordingly.
1812 const bool compressed
=
1813 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1814 brw_set_default_compression(p
, compressed
);
1815 brw_set_default_group(p
, inst
->group
);
1817 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1818 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1819 &inst
->src
[i
], compressed
);
1820 /* The accumulator result appears to get used for the
1821 * conditional modifier generation. When negating a UD
1822 * value, there is a 33rd bit generated for the sign in the
1823 * accumulator value, so now you can't check, for example,
1824 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1826 assert(!inst
->conditional_mod
||
1827 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1828 !inst
->src
[i
].negate
);
1830 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1831 &inst
->dst
, compressed
);
1833 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1834 brw_set_default_predicate_control(p
, inst
->predicate
);
1835 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1836 /* On gen7 and above, hardware automatically adds the group onto the
1837 * flag subregister number. On Sandy Bridge and older, we have to do it
1840 const unsigned flag_subreg
= inst
->flag_subreg
+
1841 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1842 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1843 brw_set_default_saturate(p
, inst
->saturate
);
1844 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1845 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1847 unsigned exec_size
= inst
->exec_size
;
1848 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1849 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1853 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1855 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1856 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1857 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1858 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1860 switch (inst
->opcode
) {
1861 case BRW_OPCODE_MOV
:
1862 brw_MOV(p
, dst
, src
[0]);
1864 case BRW_OPCODE_ADD
:
1865 brw_ADD(p
, dst
, src
[0], src
[1]);
1867 case BRW_OPCODE_MUL
:
1868 brw_MUL(p
, dst
, src
[0], src
[1]);
1870 case BRW_OPCODE_AVG
:
1871 brw_AVG(p
, dst
, src
[0], src
[1]);
1873 case BRW_OPCODE_MACH
:
1874 brw_MACH(p
, dst
, src
[0], src
[1]);
1877 case BRW_OPCODE_LINE
:
1878 brw_LINE(p
, dst
, src
[0], src
[1]);
1881 case BRW_OPCODE_MAD
:
1882 assert(devinfo
->gen
>= 6);
1883 if (devinfo
->gen
< 10)
1884 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1885 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1888 case BRW_OPCODE_LRP
:
1889 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1890 if (devinfo
->gen
< 10)
1891 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1892 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1895 case BRW_OPCODE_FRC
:
1896 brw_FRC(p
, dst
, src
[0]);
1898 case BRW_OPCODE_RNDD
:
1899 brw_RNDD(p
, dst
, src
[0]);
1901 case BRW_OPCODE_RNDE
:
1902 brw_RNDE(p
, dst
, src
[0]);
1904 case BRW_OPCODE_RNDZ
:
1905 brw_RNDZ(p
, dst
, src
[0]);
1908 case BRW_OPCODE_AND
:
1909 brw_AND(p
, dst
, src
[0], src
[1]);
1912 brw_OR(p
, dst
, src
[0], src
[1]);
1914 case BRW_OPCODE_XOR
:
1915 brw_XOR(p
, dst
, src
[0], src
[1]);
1917 case BRW_OPCODE_NOT
:
1918 brw_NOT(p
, dst
, src
[0]);
1920 case BRW_OPCODE_ASR
:
1921 brw_ASR(p
, dst
, src
[0], src
[1]);
1923 case BRW_OPCODE_SHR
:
1924 brw_SHR(p
, dst
, src
[0], src
[1]);
1926 case BRW_OPCODE_SHL
:
1927 brw_SHL(p
, dst
, src
[0], src
[1]);
1929 case BRW_OPCODE_F32TO16
:
1930 assert(devinfo
->gen
>= 7);
1931 brw_F32TO16(p
, dst
, src
[0]);
1933 case BRW_OPCODE_F16TO32
:
1934 assert(devinfo
->gen
>= 7);
1935 brw_F16TO32(p
, dst
, src
[0]);
1937 case BRW_OPCODE_CMP
:
1938 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1939 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1940 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1941 * implemented in the compiler is not sufficient. Overriding the
1942 * type when the destination is the null register is necessary but
1943 * not sufficient by itself.
1945 assert(dst
.nr
== BRW_ARF_NULL
);
1946 dst
.type
= BRW_REGISTER_TYPE_D
;
1948 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1950 case BRW_OPCODE_SEL
:
1951 brw_SEL(p
, dst
, src
[0], src
[1]);
1953 case BRW_OPCODE_CSEL
:
1954 assert(devinfo
->gen
>= 8);
1955 if (devinfo
->gen
< 10)
1956 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1957 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1959 case BRW_OPCODE_BFREV
:
1960 assert(devinfo
->gen
>= 7);
1961 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1962 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1964 case BRW_OPCODE_FBH
:
1965 assert(devinfo
->gen
>= 7);
1966 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1968 case BRW_OPCODE_FBL
:
1969 assert(devinfo
->gen
>= 7);
1970 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1971 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1973 case BRW_OPCODE_LZD
:
1974 brw_LZD(p
, dst
, src
[0]);
1976 case BRW_OPCODE_CBIT
:
1977 assert(devinfo
->gen
>= 7);
1978 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1979 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1981 case BRW_OPCODE_ADDC
:
1982 assert(devinfo
->gen
>= 7);
1983 brw_ADDC(p
, dst
, src
[0], src
[1]);
1985 case BRW_OPCODE_SUBB
:
1986 assert(devinfo
->gen
>= 7);
1987 brw_SUBB(p
, dst
, src
[0], src
[1]);
1989 case BRW_OPCODE_MAC
:
1990 brw_MAC(p
, dst
, src
[0], src
[1]);
1993 case BRW_OPCODE_BFE
:
1994 assert(devinfo
->gen
>= 7);
1995 if (devinfo
->gen
< 10)
1996 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1997 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
2000 case BRW_OPCODE_BFI1
:
2001 assert(devinfo
->gen
>= 7);
2002 brw_BFI1(p
, dst
, src
[0], src
[1]);
2004 case BRW_OPCODE_BFI2
:
2005 assert(devinfo
->gen
>= 7);
2006 if (devinfo
->gen
< 10)
2007 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2008 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
2012 if (inst
->src
[0].file
!= BAD_FILE
) {
2013 /* The instruction has an embedded compare (only allowed on gen6) */
2014 assert(devinfo
->gen
== 6);
2015 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
2017 brw_IF(p
, brw_get_default_exec_size(p
));
2021 case BRW_OPCODE_ELSE
:
2024 case BRW_OPCODE_ENDIF
:
2029 brw_DO(p
, brw_get_default_exec_size(p
));
2032 case BRW_OPCODE_BREAK
:
2035 case BRW_OPCODE_CONTINUE
:
2039 case BRW_OPCODE_WHILE
:
2044 case SHADER_OPCODE_RCP
:
2045 case SHADER_OPCODE_RSQ
:
2046 case SHADER_OPCODE_SQRT
:
2047 case SHADER_OPCODE_EXP2
:
2048 case SHADER_OPCODE_LOG2
:
2049 case SHADER_OPCODE_SIN
:
2050 case SHADER_OPCODE_COS
:
2051 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2052 if (devinfo
->gen
>= 6) {
2053 assert(inst
->mlen
== 0);
2054 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
2055 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
2056 src
[0], brw_null_reg());
2058 assert(inst
->mlen
>= 1);
2059 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
2061 brw_math_function(inst
->opcode
),
2062 inst
->base_mrf
, src
[0],
2063 BRW_MATH_PRECISION_FULL
);
2066 case SHADER_OPCODE_INT_QUOTIENT
:
2067 case SHADER_OPCODE_INT_REMAINDER
:
2068 case SHADER_OPCODE_POW
:
2069 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2070 if (devinfo
->gen
>= 6) {
2071 assert(inst
->mlen
== 0);
2072 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
2073 inst
->exec_size
== 8);
2074 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2076 assert(inst
->mlen
>= 1);
2077 assert(inst
->exec_size
== 8);
2078 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2079 inst
->base_mrf
, src
[0],
2080 BRW_MATH_PRECISION_FULL
);
2083 case FS_OPCODE_LINTERP
:
2084 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2086 case FS_OPCODE_PIXEL_X
:
2087 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2088 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2089 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2091 case FS_OPCODE_PIXEL_Y
:
2092 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2093 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2094 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2096 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2097 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2099 case SHADER_OPCODE_TEX
:
2101 case SHADER_OPCODE_TXD
:
2102 case SHADER_OPCODE_TXF
:
2103 case SHADER_OPCODE_TXF_LZ
:
2104 case SHADER_OPCODE_TXF_CMS
:
2105 case SHADER_OPCODE_TXF_CMS_W
:
2106 case SHADER_OPCODE_TXF_UMS
:
2107 case SHADER_OPCODE_TXF_MCS
:
2108 case SHADER_OPCODE_TXL
:
2109 case SHADER_OPCODE_TXL_LZ
:
2110 case SHADER_OPCODE_TXS
:
2111 case SHADER_OPCODE_LOD
:
2112 case SHADER_OPCODE_TG4
:
2113 case SHADER_OPCODE_TG4_OFFSET
:
2114 case SHADER_OPCODE_SAMPLEINFO
:
2115 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
2117 case FS_OPCODE_DDX_COARSE
:
2118 case FS_OPCODE_DDX_FINE
:
2119 generate_ddx(inst
, dst
, src
[0]);
2121 case FS_OPCODE_DDY_COARSE
:
2122 case FS_OPCODE_DDY_FINE
:
2123 generate_ddy(inst
, dst
, src
[0]);
2126 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2127 generate_scratch_write(inst
, src
[0]);
2131 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2132 generate_scratch_read(inst
, dst
);
2136 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2137 generate_scratch_read_gen7(inst
, dst
);
2141 case SHADER_OPCODE_MOV_INDIRECT
:
2142 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2145 case SHADER_OPCODE_URB_READ_SIMD8
:
2146 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2147 generate_urb_read(inst
, dst
, src
[0]);
2150 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2151 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2152 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2153 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2154 generate_urb_write(inst
, src
[0]);
2157 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2158 assert(inst
->force_writemask_all
);
2159 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2162 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2163 assert(inst
->force_writemask_all
);
2164 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2167 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2168 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2171 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2172 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2175 case FS_OPCODE_REP_FB_WRITE
:
2176 case FS_OPCODE_FB_WRITE
:
2177 generate_fb_write(inst
, src
[0]);
2180 case FS_OPCODE_FB_READ
:
2181 generate_fb_read(inst
, dst
, src
[0]);
2184 case FS_OPCODE_DISCARD_JUMP
:
2185 generate_discard_jump(inst
);
2188 case SHADER_OPCODE_SHADER_TIME_ADD
:
2189 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2192 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2193 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2194 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2195 inst
->mlen
, !inst
->dst
.is_null(),
2199 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2200 assert(!inst
->header_size
);
2201 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2202 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2203 inst
->mlen
, src
[2].ud
);
2206 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2207 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2208 brw_untyped_surface_write(p
, src
[0], src
[1],
2209 inst
->mlen
, src
[2].ud
,
2213 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
2214 assert(!inst
->header_size
);
2215 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2216 brw_byte_scattered_read(p
, dst
, src
[0], src
[1],
2217 inst
->mlen
, src
[2].ud
);
2220 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
2221 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2222 brw_byte_scattered_write(p
, src
[0], src
[1],
2223 inst
->mlen
, src
[2].ud
,
2227 case SHADER_OPCODE_TYPED_ATOMIC
:
2228 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2229 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2230 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null(),
2234 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2235 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2236 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2237 inst
->mlen
, src
[2].ud
,
2241 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2242 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2243 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
,
2247 case SHADER_OPCODE_MEMORY_FENCE
:
2248 brw_memory_fence(p
, dst
, BRW_OPCODE_SEND
);
2251 case SHADER_OPCODE_INTERLOCK
:
2252 /* The interlock is basically a memory fence issued via sendc */
2253 brw_memory_fence(p
, dst
, BRW_OPCODE_SENDC
);
2256 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2257 const struct brw_reg mask
=
2258 brw_stage_has_packed_dispatch(devinfo
, stage
,
2259 prog_data
) ? brw_imm_ud(~0u) :
2260 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2262 brw_find_live_channel(p
, dst
, mask
);
2266 case SHADER_OPCODE_BROADCAST
:
2267 assert(inst
->force_writemask_all
);
2268 brw_broadcast(p
, dst
, src
[0], src
[1]);
2271 case SHADER_OPCODE_SHUFFLE
:
2272 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2275 case SHADER_OPCODE_SEL_EXEC
:
2276 assert(inst
->force_writemask_all
);
2277 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2278 brw_MOV(p
, dst
, src
[1]);
2279 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2280 brw_MOV(p
, dst
, src
[0]);
2283 case SHADER_OPCODE_QUAD_SWIZZLE
:
2284 /* This only works on 8-wide 32-bit values */
2285 assert(inst
->exec_size
== 8);
2286 assert(type_sz(src
[0].type
) == 4);
2287 assert(inst
->force_writemask_all
);
2288 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2289 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2291 if (src
[0].file
== BRW_IMMEDIATE_VALUE
||
2292 (src
[0].vstride
== 0 && src
[0].hstride
== 0)) {
2293 /* The value is uniform across all channels */
2294 brw_MOV(p
, dst
, src
[0]);
2296 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2297 struct brw_reg swiz_src
= stride(src
[0], 4, 4, 1);
2298 swiz_src
.swizzle
= inst
->src
[1].ud
;
2299 brw_MOV(p
, dst
, swiz_src
);
2303 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2304 assert(src
[0].type
== dst
.type
);
2305 assert(!src
[0].negate
&& !src
[0].abs
);
2306 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2307 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2308 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2309 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2310 const unsigned component
= src
[1].ud
;
2311 const unsigned cluster_size
= src
[2].ud
;
2312 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2313 cluster_size
, cluster_size
, 0);
2314 if (type_sz(src
[0].type
) > 4 &&
2315 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2316 /* IVB has an issue (which we found empirically) where it reads
2317 * two address register components per channel for indirectly
2318 * addressed 64-bit sources.
2320 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2322 * "When source or destination datatype is 64b or operation is
2323 * integer DWord multiply, indirect addressing must not be
2326 * To work around both of these, we do two integer MOVs insead of
2327 * one 64-bit MOV. Because no double value should ever cross a
2328 * register boundary, it's safe to use the immediate offset in the
2329 * indirect here to handle adding 4 bytes to the offset and avoid
2330 * the extra ADD to the register file.
2332 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2333 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2334 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2335 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2337 brw_MOV(p
, dst
, strided
);
2342 case FS_OPCODE_SET_SAMPLE_ID
:
2343 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2346 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2347 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2350 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2351 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2352 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2355 case FS_OPCODE_PLACEHOLDER_HALT
:
2356 /* This is the place where the final HALT needs to be inserted if
2357 * we've emitted any discards. If not, this will emit no code.
2359 if (!patch_discard_jumps_to_fb_writes()) {
2360 if (unlikely(debug_flag
)) {
2361 disasm_info
->use_tail
= true;
2366 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2367 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2368 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2371 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2372 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2373 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2376 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2377 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2378 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2381 case CS_OPCODE_CS_TERMINATE
:
2382 generate_cs_terminate(inst
, src
[0]);
2385 case SHADER_OPCODE_BARRIER
:
2386 generate_barrier(inst
, src
[0]);
2389 case BRW_OPCODE_DIM
:
2390 assert(devinfo
->is_haswell
);
2391 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2392 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2393 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2396 case SHADER_OPCODE_RND_MODE
:
2397 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2398 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2402 unreachable("Unsupported opcode");
2404 case SHADER_OPCODE_LOAD_PAYLOAD
:
2405 unreachable("Should be lowered by lower_load_payload()");
2408 if (multiple_instructions_emitted
)
2411 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2412 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2413 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2414 "emitting more than 1 instruction");
2416 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2418 if (inst
->conditional_mod
)
2419 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2420 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2421 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2425 brw_set_uip_jip(p
, start_offset
);
2427 /* end of program sentinel */
2428 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2433 if (unlikely(debug_flag
))
2435 brw_validate_instructions(devinfo
, p
->store
,
2437 p
->next_insn_offset
,
2440 int before_size
= p
->next_insn_offset
- start_offset
;
2441 brw_compact_instructions(p
, start_offset
, disasm_info
);
2442 int after_size
= p
->next_insn_offset
- start_offset
;
2444 if (unlikely(debug_flag
)) {
2445 fprintf(stderr
, "Native code for %s\n"
2446 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2447 " bytes (%.0f%%)\n",
2448 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2449 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2450 100.0f
* (before_size
- after_size
) / before_size
);
2452 dump_assembly(p
->store
, disasm_info
);
2454 ralloc_free(disasm_info
);
2457 compiler
->shader_debug_log(log_data
,
2458 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2459 "%d:%d spills:fills, Promoted %u constants, "
2460 "compacted %d to %d bytes.",
2461 _mesa_shader_stage_to_abbrev(stage
),
2462 dispatch_width
, before_size
/ 16,
2463 loop_count
, cfg
->cycle_count
, spill_count
,
2464 fill_count
, promoted_constants
, before_size
,
2467 return start_offset
;
2471 fs_generator::get_assembly()
2473 return brw_get_program(p
, &prog_data
->program_size
);