2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
34 static enum brw_reg_file
35 brw_file_from_reg(fs_reg
*reg
)
39 return BRW_ARCHITECTURE_REGISTER_FILE
;
42 return BRW_GENERAL_REGISTER_FILE
;
44 return BRW_MESSAGE_REGISTER_FILE
;
46 return BRW_IMMEDIATE_VALUE
;
50 unreachable("not reached");
52 return BRW_ARCHITECTURE_REGISTER_FILE
;
56 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
57 fs_reg
*reg
, bool compressed
)
59 struct brw_reg brw_reg
;
63 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
66 if (reg
->stride
== 0) {
67 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 /* From the Haswell PRM:
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
75 * The maximum width value that could satisfy this restriction is:
77 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
84 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
93 const unsigned width
= MIN2(reg_width
, phys_width
);
94 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
95 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
97 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
98 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
99 * "Each DF (Double Float) operand uses an element size of 4 rather
100 * than 8 and all regioning parameters are twice what the values
101 * would be based on the true element size: ExecSize, Width,
102 * HorzStride, and VertStride. Each DF operand uses a pair of
103 * channels and all masking and swizzing should be adjusted
106 * From the IvyBridge PRM (Special Requirements for Handling Double
107 * Precision Data Types, page 71):
108 * "In Align1 mode, all regioning parameters like stride, execution
109 * size, and width must use the syntax of a pair of packed
110 * floats. The offsets for these data types must be 64-bit
111 * aligned. The execution size and regioning parameters are in terms
114 * Summarized: when handling DF-typed arguments, ExecSize,
115 * VertStride, and Width must be doubled.
117 * It applies to BayTrail too.
119 if (type_sz(reg
->type
) == 8) {
121 if (brw_reg
.vstride
> 0)
123 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
126 /* When converting from DF->F, we set the destination stride to 2
127 * because each d2f conversion implicitly writes 2 floats, being
128 * the first one the converted value. IVB/BYT actually writes two
129 * F components per SIMD channel, and every other component is
130 * filled with garbage.
132 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
133 type_sz(inst
->dst
.type
) < 8) {
134 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
140 brw_reg
= retype(brw_reg
, reg
->type
);
141 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
142 brw_reg
.abs
= reg
->abs
;
143 brw_reg
.negate
= reg
->negate
;
148 assert(reg
->offset
== 0);
149 brw_reg
= reg
->as_brw_reg();
152 /* Probably unused. */
153 brw_reg
= brw_null_reg();
157 unreachable("not reached");
160 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
161 * region, but on IVB and BYT DF regions must be programmed in terms of
162 * floats. A <0,2,1> region accomplishes this.
164 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
165 type_sz(reg
->type
) == 8 &&
166 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
167 brw_reg
.width
== BRW_WIDTH_1
&&
168 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
169 brw_reg
.width
= BRW_WIDTH_2
;
170 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
176 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
179 struct brw_stage_prog_data
*prog_data
,
180 unsigned promoted_constants
,
181 bool runtime_check_aads_emit
,
182 gl_shader_stage stage
)
184 : compiler(compiler
), log_data(log_data
),
185 devinfo(compiler
->devinfo
), key(key
),
186 prog_data(prog_data
),
187 promoted_constants(promoted_constants
),
188 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
189 stage(stage
), mem_ctx(mem_ctx
)
191 p
= rzalloc(mem_ctx
, struct brw_codegen
);
192 brw_init_codegen(devinfo
, p
, mem_ctx
);
194 /* In the FS code generator, we are very careful to ensure that we always
195 * set the right execution size so we don't need the EU code to "help" us
196 * by trying to infer it. Sometimes, it infers the wrong thing.
198 p
->automatic_exec_sizes
= false;
201 fs_generator::~fs_generator()
205 class ip_record
: public exec_node
{
207 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
218 fs_generator::patch_discard_jumps_to_fb_writes()
220 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
223 int scale
= brw_jump_scale(p
->devinfo
);
225 /* There is a somewhat strange undocumented requirement of using
226 * HALT, according to the simulator. If some channel has HALTed to
227 * a particular UIP, then by the end of the program, every channel
228 * must have HALTed to that UIP. Furthermore, the tracking is a
229 * stack, so you can't do the final halt of a UIP after starting
230 * halting to a new UIP.
232 * Symptoms of not emitting this instruction on actual hardware
233 * included GPU hangs and sparkly rendering on the piglit discard
236 brw_inst
*last_halt
= gen6_HALT(p
);
237 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
238 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
242 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
243 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
245 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
246 /* HALT takes a half-instruction distance from the pre-incremented IP. */
247 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
250 this->discard_halt_patches
.make_empty();
255 fs_generator::fire_fb_write(fs_inst
*inst
,
256 struct brw_reg payload
,
257 struct brw_reg implied_header
,
260 uint32_t msg_control
;
262 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
264 if (devinfo
->gen
< 6) {
265 brw_push_insn_state(p
);
266 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
267 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
268 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
269 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
270 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
271 brw_pop_insn_state(p
);
274 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
275 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
276 else if (prog_data
->dual_src_blend
) {
278 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
280 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
281 } else if (inst
->exec_size
== 16)
282 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
284 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
286 /* We assume render targets start at 0, because headerless FB write
287 * messages set "Render Target Index" to 0. Using a different binding
288 * table index would make it impossible to use headerless messages.
290 assert(prog_data
->binding_table
.render_target_start
== 0);
292 const uint32_t surf_index
= inst
->target
;
294 bool last_render_target
= inst
->eot
||
295 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
307 inst
->header_size
!= 0);
309 brw_mark_surface_used(&prog_data
->base
, surf_index
);
313 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
315 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
316 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
317 struct brw_reg implied_header
;
319 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
320 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
323 if (inst
->base_mrf
>= 0)
324 payload
= brw_message_reg(inst
->base_mrf
);
326 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
329 if (inst
->header_size
!= 0) {
330 brw_push_insn_state(p
);
331 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
332 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
333 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
334 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
335 brw_set_default_flag_reg(p
, 0, 0);
337 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
340 if (prog_data
->uses_kill
) {
341 struct brw_reg pixel_mask
;
343 if (devinfo
->gen
>= 6)
344 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
346 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
348 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
351 if (devinfo
->gen
>= 6) {
352 brw_push_insn_state(p
);
353 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
354 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
356 retype(payload
, BRW_REGISTER_TYPE_UD
),
357 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
358 brw_pop_insn_state(p
);
360 if (inst
->target
> 0 && key
->replicate_alpha
) {
361 /* Set "Source0 Alpha Present to RenderTarget" bit in message
365 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
366 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
367 brw_imm_ud(0x1 << 11));
370 if (inst
->target
> 0) {
371 /* Set the render target index for choosing BLEND_STATE. */
372 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
373 BRW_REGISTER_TYPE_UD
),
374 brw_imm_ud(inst
->target
));
377 /* Set computes stencil to render target */
378 if (prog_data
->computed_stencil
) {
380 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
381 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
382 brw_imm_ud(0x1 << 14));
385 implied_header
= brw_null_reg();
387 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
390 brw_pop_insn_state(p
);
392 implied_header
= brw_null_reg();
395 if (!runtime_check_aads_emit
) {
396 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
398 /* This can only happen in gen < 6 */
399 assert(devinfo
->gen
< 6);
401 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
403 /* Check runtime bit to detect if we have to send AA data or not */
404 brw_push_insn_state(p
);
405 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
406 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
409 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
411 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
413 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
414 brw_pop_insn_state(p
);
416 /* Don't send AA data */
417 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
419 brw_land_fwd_jump(p
, jmp
);
420 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
425 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
426 struct brw_reg payload
)
428 assert(inst
->size_written
% REG_SIZE
== 0);
429 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
430 const unsigned surf_index
=
431 prog_data
->binding_table
.render_target_start
+ inst
->target
;
433 gen9_fb_READ(p
, dst
, payload
, surf_index
,
434 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
435 prog_data
->persample_dispatch
);
437 brw_mark_surface_used(&prog_data
->base
, surf_index
);
441 fs_generator::generate_mov_indirect(fs_inst
*inst
,
444 struct brw_reg indirect_byte_offset
)
446 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
447 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
448 assert(!reg
.abs
&& !reg
.negate
);
449 assert(reg
.type
== dst
.type
);
451 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
453 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
454 imm_byte_offset
+= indirect_byte_offset
.ud
;
456 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
457 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
458 brw_MOV(p
, dst
, reg
);
460 /* Prior to Broadwell, there are only 8 address registers. */
461 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
463 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
464 struct brw_reg addr
= vec8(brw_address_reg(0));
466 /* The destination stride of an instruction (in bytes) must be greater
467 * than or equal to the size of the rest of the instruction. Since the
468 * address register is of type UW, we can't use a D-type instruction.
469 * In order to get around this, re retype to UW and use a stride.
471 indirect_byte_offset
=
472 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
474 /* There are a number of reasons why we don't use the base offset here.
475 * One reason is that the field is only 9 bits which means we can only
476 * use it to access the first 16 GRFs. Also, from the Haswell PRM
477 * section "Register Region Restrictions":
479 * "The lower bits of the AddressImmediate must not overflow to
480 * change the register address. The lower 5 bits of Address
481 * Immediate when added to lower 5 bits of address register gives
482 * the sub-register offset. The upper bits of Address Immediate
483 * when added to upper bits of address register gives the register
484 * address. Any overflow from sub-register offset is dropped."
486 * Since the indirect may cause us to cross a register boundary, this
487 * makes the base offset almost useless. We could try and do something
488 * clever where we use a actual base offset if base_offset % 32 == 0 but
489 * that would mean we were generating different code depending on the
490 * base offset. Instead, for the sake of consistency, we'll just do the
491 * add ourselves. This restriction is only listed in the Haswell PRM
492 * but empirical testing indicates that it applies on all older
493 * generations and is lifted on Broadwell.
495 * In the end, while base_offset is nice to look at in the generated
496 * code, using it saves us 0 instructions and would require quite a bit
497 * of case-by-case work. It's just not worth it.
499 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
501 if (type_sz(reg
.type
) > 4 &&
502 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
503 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
504 /* IVB has an issue (which we found empirically) where it reads two
505 * address register components per channel for indirectly addressed
508 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
510 * "When source or destination datatype is 64b or operation is
511 * integer DWord multiply, indirect addressing must not be used."
513 * To work around both of these, we do two integer MOVs insead of one
514 * 64-bit MOV. Because no double value should ever cross a register
515 * boundary, it's safe to use the immediate offset in the indirect
516 * here to handle adding 4 bytes to the offset and avoid the extra
517 * ADD to the register file.
519 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
520 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
521 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
522 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
524 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
526 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
528 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
529 !inst
->get_next()->is_tail_sentinel() &&
530 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
531 /* From the Sandybridge PRM:
533 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
534 * instruction that “indexed/indirect” source AND is followed
535 * by a send, the instruction requires a “Switch”. This is to
536 * avoid race condition where send may dispatch before MRF is
539 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
546 fs_generator::generate_urb_read(fs_inst
*inst
,
548 struct brw_reg header
)
550 assert(inst
->size_written
% REG_SIZE
== 0);
551 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
552 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
554 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
555 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
556 brw_set_src0(p
, send
, header
);
557 brw_set_src1(p
, send
, brw_imm_ud(0u));
559 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
560 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
562 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
563 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
565 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
566 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
567 brw_inst_set_header_present(p
->devinfo
, send
, true);
568 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
572 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
576 /* WaClearTDRRegBeforeEOTForNonPS.
578 * WA: Clear tdr register before send EOT in all non-PS shader kernels
580 * mov(8) tdr0:ud 0x0:ud {NoMask}"
582 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
583 brw_push_insn_state(p
);
584 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
585 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
586 brw_pop_insn_state(p
);
589 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
591 brw_set_dest(p
, insn
, brw_null_reg());
592 brw_set_src0(p
, insn
, payload
);
593 brw_set_src1(p
, insn
, brw_imm_d(0));
595 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
596 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
598 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
599 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
600 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
602 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
603 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
604 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
606 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
607 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
608 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
609 brw_inst_set_header_present(p
->devinfo
, insn
, true);
610 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
614 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
616 struct brw_inst
*insn
;
618 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
620 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
621 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
622 brw_set_src1(p
, insn
, brw_imm_d(0));
624 /* Terminate a compute shader by sending a message to the thread spawner.
626 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
627 brw_inst_set_mlen(devinfo
, insn
, 1);
628 brw_inst_set_rlen(devinfo
, insn
, 0);
629 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
630 brw_inst_set_header_present(devinfo
, insn
, false);
632 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
633 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
635 /* Note that even though the thread has a URB resource associated with it,
636 * we set the "do not dereference URB" bit, because the URB resource is
637 * managed by the fixed-function unit, so it will free it automatically.
639 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
641 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
645 fs_generator::generate_barrier(fs_inst
*inst
, struct brw_reg src
)
652 fs_generator::generate_linterp(fs_inst
*inst
,
653 struct brw_reg dst
, struct brw_reg
*src
)
657 * -----------------------------------
658 * | src1+0 | src1+1 | src1+2 | src1+3 |
659 * |-----------------------------------|
660 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
661 * -----------------------------------
663 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
665 * -----------------------------------
666 * | src1+0 | src1+1 | src1+2 | src1+3 |
667 * |-----------------------------------|
668 * |(x0, x1)|(y0, y1)| | | in SIMD8
669 * |-----------------------------------|
670 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
671 * -----------------------------------
673 * See also: emit_interpolation_setup_gen4().
675 struct brw_reg delta_x
= src
[0];
676 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
677 struct brw_reg interp
= src
[1];
679 if (devinfo
->has_pln
&&
680 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
681 brw_PLN(p
, dst
, interp
, delta_x
);
683 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
684 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
689 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
692 struct brw_reg surf_index
)
694 assert(devinfo
->gen
>= 7);
695 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
700 switch (inst
->exec_size
) {
702 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
705 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
708 unreachable("Invalid width for texture instruction");
711 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
717 retype(dst
, BRW_REGISTER_TYPE_UW
),
722 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
723 rlen
, /* response length */
725 inst
->header_size
> 0,
727 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
729 brw_mark_surface_used(prog_data
, surf_index
.ud
);
733 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
734 struct brw_reg surface_index
,
735 struct brw_reg sampler_index
)
737 assert(inst
->size_written
% REG_SIZE
== 0);
740 uint32_t return_format
;
741 bool is_combined_send
= inst
->eot
;
744 case BRW_REGISTER_TYPE_D
:
745 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
747 case BRW_REGISTER_TYPE_UD
:
748 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
751 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
755 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
756 * is set as part of the message descriptor. On gen4, the PRM seems to
757 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
758 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
759 * gone from the message descriptor entirely and you just get UINT32 all
760 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
761 * just stomp it to UINT32 all the time.
763 if (inst
->opcode
== SHADER_OPCODE_TXS
)
764 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
766 switch (inst
->exec_size
) {
768 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
771 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
774 unreachable("Invalid width for texture instruction");
777 if (devinfo
->gen
>= 5) {
778 switch (inst
->opcode
) {
779 case SHADER_OPCODE_TEX
:
780 if (inst
->shadow_compare
) {
781 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
783 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
787 if (inst
->shadow_compare
) {
788 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
790 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
793 case SHADER_OPCODE_TXL
:
794 if (inst
->shadow_compare
) {
795 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
797 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
800 case SHADER_OPCODE_TXL_LZ
:
801 assert(devinfo
->gen
>= 9);
802 if (inst
->shadow_compare
) {
803 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
;
805 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
808 case SHADER_OPCODE_TXS
:
809 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
811 case SHADER_OPCODE_TXD
:
812 if (inst
->shadow_compare
) {
813 /* Gen7.5+. Otherwise, lowered in NIR */
814 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
815 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
817 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
820 case SHADER_OPCODE_TXF
:
821 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
823 case SHADER_OPCODE_TXF_LZ
:
824 assert(devinfo
->gen
>= 9);
825 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
827 case SHADER_OPCODE_TXF_CMS_W
:
828 assert(devinfo
->gen
>= 9);
829 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
831 case SHADER_OPCODE_TXF_CMS
:
832 if (devinfo
->gen
>= 7)
833 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
835 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
837 case SHADER_OPCODE_TXF_UMS
:
838 assert(devinfo
->gen
>= 7);
839 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
841 case SHADER_OPCODE_TXF_MCS
:
842 assert(devinfo
->gen
>= 7);
843 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
845 case SHADER_OPCODE_LOD
:
846 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
848 case SHADER_OPCODE_TG4
:
849 if (inst
->shadow_compare
) {
850 assert(devinfo
->gen
>= 7);
851 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
853 assert(devinfo
->gen
>= 6);
854 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
857 case SHADER_OPCODE_TG4_OFFSET
:
858 assert(devinfo
->gen
>= 7);
859 if (inst
->shadow_compare
) {
860 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
862 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
865 case SHADER_OPCODE_SAMPLEINFO
:
866 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
869 unreachable("not reached");
872 switch (inst
->opcode
) {
873 case SHADER_OPCODE_TEX
:
874 /* Note that G45 and older determines shadow compare and dispatch width
875 * from message length for most messages.
877 if (inst
->exec_size
== 8) {
878 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
879 if (inst
->shadow_compare
) {
880 assert(inst
->mlen
== 6);
882 assert(inst
->mlen
<= 4);
885 if (inst
->shadow_compare
) {
886 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
887 assert(inst
->mlen
== 9);
889 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
890 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
895 if (inst
->shadow_compare
) {
896 assert(inst
->exec_size
== 8);
897 assert(inst
->mlen
== 6);
898 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
900 assert(inst
->mlen
== 9);
901 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
902 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
905 case SHADER_OPCODE_TXL
:
906 if (inst
->shadow_compare
) {
907 assert(inst
->exec_size
== 8);
908 assert(inst
->mlen
== 6);
909 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
911 assert(inst
->mlen
== 9);
912 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
913 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
916 case SHADER_OPCODE_TXD
:
917 /* There is no sample_d_c message; comparisons are done manually */
918 assert(inst
->exec_size
== 8);
919 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
920 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
922 case SHADER_OPCODE_TXF
:
923 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
924 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
925 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
927 case SHADER_OPCODE_TXS
:
928 assert(inst
->mlen
== 3);
929 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
930 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
933 unreachable("not reached");
936 assert(msg_type
!= -1);
938 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
942 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
943 src
.file
== BRW_GENERAL_REGISTER_FILE
);
945 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
947 /* Load the message header if present. If there's a texture offset,
948 * we need to set it up explicitly and load the offset bitfield.
949 * Otherwise, we can use an implied move from g0 to the first message reg.
951 if (inst
->header_size
!= 0) {
952 if (devinfo
->gen
< 6 && !inst
->offset
) {
953 /* Set up an implied move from g0 to the MRF. */
954 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
956 struct brw_reg header_reg
;
958 if (devinfo
->gen
>= 7) {
961 assert(inst
->base_mrf
!= -1);
962 header_reg
= brw_message_reg(inst
->base_mrf
);
965 brw_push_insn_state(p
);
966 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
967 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
968 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
969 /* Explicitly set up the message header by copying g0 to the MRF. */
970 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
972 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
974 /* Set the offset bits in DWord 2. */
975 brw_MOV(p
, get_element_ud(header_reg
, 2),
976 brw_imm_ud(inst
->offset
));
977 } else if (stage
!= MESA_SHADER_VERTEX
&&
978 stage
!= MESA_SHADER_FRAGMENT
) {
979 /* The vertex and fragment stages have g0.2 set to 0, so
980 * header0.2 is 0 when g0 is copied. Other stages may not, so we
981 * must set it to 0 to avoid setting undesirable bits in the
984 brw_MOV(p
, get_element_ud(header_reg
, 2), brw_imm_ud(0));
987 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
988 brw_pop_insn_state(p
);
992 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
993 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
994 ? prog_data
->binding_table
.gather_texture_start
995 : prog_data
->binding_table
.texture_start
;
997 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
998 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
999 uint32_t surface
= surface_index
.ud
;
1000 uint32_t sampler
= sampler_index
.ud
;
1003 retype(dst
, BRW_REGISTER_TYPE_UW
),
1006 surface
+ base_binding_table_index
,
1009 inst
->size_written
/ REG_SIZE
,
1011 inst
->header_size
!= 0,
1015 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
1017 /* Non-const sampler index */
1019 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1020 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
1021 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
1023 brw_push_insn_state(p
);
1024 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1025 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1026 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1028 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
1029 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
1031 if (sampler_reg
.file
== BRW_IMMEDIATE_VALUE
) {
1032 brw_OR(p
, addr
, surface_reg
, brw_imm_ud(sampler_reg
.ud
<< 8));
1034 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
1035 brw_OR(p
, addr
, addr
, surface_reg
);
1038 if (base_binding_table_index
)
1039 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
1040 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
1042 brw_pop_insn_state(p
);
1044 /* dst = send(offset, a0.0 | <descriptor>) */
1045 brw_inst
*insn
= brw_send_indirect_message(
1046 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1047 brw_set_sampler_message(p
, insn
,
1051 inst
->size_written
/ REG_SIZE
,
1052 inst
->mlen
/* mlen */,
1053 inst
->header_size
!= 0 /* header */,
1057 /* visitor knows more than we do about the surface limit required,
1058 * so has already done marking.
1062 if (is_combined_send
) {
1063 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
1064 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
1069 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1072 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1074 * Ideally, we want to produce:
1077 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1078 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1079 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1080 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1081 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1082 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1083 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1084 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1086 * and add another set of two more subspans if in 16-pixel dispatch mode.
1088 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1089 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1090 * pair. But the ideal approximation may impose a huge performance cost on
1091 * sample_d. On at least Haswell, sample_d instruction does some
1092 * optimizations if the same LOD is used for all pixels in the subspan.
1094 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1095 * appropriate swizzling.
1098 fs_generator::generate_ddx(enum opcode opcode
,
1099 struct brw_reg dst
, struct brw_reg src
)
1101 unsigned vstride
, width
;
1103 if (opcode
== FS_OPCODE_DDX_FINE
) {
1104 /* produce accurate derivatives */
1105 vstride
= BRW_VERTICAL_STRIDE_2
;
1106 width
= BRW_WIDTH_2
;
1108 /* replicate the derivative at the top-left pixel to other pixels */
1109 vstride
= BRW_VERTICAL_STRIDE_4
;
1110 width
= BRW_WIDTH_4
;
1113 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
1114 src
.negate
, src
.abs
,
1115 BRW_REGISTER_TYPE_F
,
1118 BRW_HORIZONTAL_STRIDE_0
,
1119 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1120 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1121 src
.negate
, src
.abs
,
1122 BRW_REGISTER_TYPE_F
,
1125 BRW_HORIZONTAL_STRIDE_0
,
1126 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1127 brw_ADD(p
, dst
, src0
, negate(src1
));
1130 /* The negate_value boolean is used to negate the derivative computation for
1131 * FBOs, since they place the origin at the upper left instead of the lower
1135 fs_generator::generate_ddy(enum opcode opcode
,
1136 struct brw_reg dst
, struct brw_reg src
)
1138 if (opcode
== FS_OPCODE_DDY_FINE
) {
1139 /* produce accurate derivatives */
1140 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1141 src
.negate
, src
.abs
,
1142 BRW_REGISTER_TYPE_F
,
1143 BRW_VERTICAL_STRIDE_4
,
1145 BRW_HORIZONTAL_STRIDE_1
,
1146 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
1147 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1148 src
.negate
, src
.abs
,
1149 BRW_REGISTER_TYPE_F
,
1150 BRW_VERTICAL_STRIDE_4
,
1152 BRW_HORIZONTAL_STRIDE_1
,
1153 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
1154 brw_push_insn_state(p
);
1155 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1156 brw_ADD(p
, dst
, negate(src0
), src1
);
1157 brw_pop_insn_state(p
);
1159 /* replicate the derivative at the top-left pixel to other pixels */
1160 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1161 src
.negate
, src
.abs
,
1162 BRW_REGISTER_TYPE_F
,
1163 BRW_VERTICAL_STRIDE_4
,
1165 BRW_HORIZONTAL_STRIDE_0
,
1166 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1167 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1168 src
.negate
, src
.abs
,
1169 BRW_REGISTER_TYPE_F
,
1170 BRW_VERTICAL_STRIDE_4
,
1172 BRW_HORIZONTAL_STRIDE_0
,
1173 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1174 brw_ADD(p
, dst
, negate(src0
), src1
);
1179 fs_generator::generate_discard_jump(fs_inst
*inst
)
1181 assert(devinfo
->gen
>= 6);
1183 /* This HALT will be patched up at FB write time to point UIP at the end of
1184 * the program, and at brw_uip_jip() JIP will be set to the end of the
1185 * current block (or the program).
1187 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1192 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1194 /* The 32-wide messages only respect the first 16-wide half of the channel
1195 * enable signals which are replicated identically for the second group of
1196 * 16 channels, so we cannot use them unless the write is marked
1197 * force_writemask_all.
1199 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1200 MIN2(16, inst
->exec_size
);
1201 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1202 assert(inst
->mlen
!= 0);
1204 brw_push_insn_state(p
);
1205 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1206 brw_set_default_compression(p
, lower_size
> 8);
1208 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1209 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1211 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1212 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1214 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1216 inst
->offset
+ block_size
* REG_SIZE
* i
);
1219 brw_pop_insn_state(p
);
1223 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1225 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1226 assert(inst
->mlen
!= 0);
1228 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1229 inst
->exec_size
/ 8, inst
->offset
);
1233 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1235 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1237 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1241 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1243 struct brw_reg index
,
1244 struct brw_reg offset
)
1246 assert(type_sz(dst
.type
) == 4);
1247 assert(inst
->mlen
!= 0);
1249 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1250 index
.type
== BRW_REGISTER_TYPE_UD
);
1251 uint32_t surf_index
= index
.ud
;
1253 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1254 offset
.type
== BRW_REGISTER_TYPE_UD
);
1255 uint32_t read_offset
= offset
.ud
;
1257 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1258 read_offset
, surf_index
);
1262 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1264 struct brw_reg index
,
1265 struct brw_reg payload
)
1267 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1268 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1269 assert(type_sz(dst
.type
) == 4);
1271 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1272 const uint32_t surf_index
= index
.ud
;
1274 brw_push_insn_state(p
);
1275 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1276 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1277 brw_pop_insn_state(p
);
1279 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1280 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1281 brw_set_dp_read_message(p
, send
, surf_index
,
1282 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1283 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1284 GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1287 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
));
1290 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1292 brw_push_insn_state(p
);
1293 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1295 /* a0.0 = surf_index & 0xff */
1296 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1297 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1298 brw_set_dest(p
, insn_and
, addr
);
1299 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1300 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1302 /* dst = send(payload, a0.0 | <descriptor>) */
1303 brw_inst
*insn
= brw_send_indirect_message(
1304 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1305 retype(dst
, BRW_REGISTER_TYPE_UD
),
1306 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
);
1307 brw_set_dp_read_message(p
, insn
, 0 /* surface */,
1308 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1309 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1310 GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1313 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
));
1315 brw_pop_insn_state(p
);
1320 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1322 struct brw_reg index
)
1324 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1325 assert(inst
->header_size
!= 0);
1328 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1329 index
.type
== BRW_REGISTER_TYPE_UD
);
1330 uint32_t surf_index
= index
.ud
;
1332 uint32_t simd_mode
, rlen
, msg_type
;
1333 if (inst
->exec_size
== 16) {
1334 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1337 assert(inst
->exec_size
== 8);
1338 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1342 if (devinfo
->gen
>= 5)
1343 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1345 /* We always use the SIMD16 message so that we only have to load U, and
1348 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1349 assert(inst
->mlen
== 3);
1350 assert(inst
->size_written
== 8 * REG_SIZE
);
1352 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1355 struct brw_reg header
= brw_vec8_grf(0, 0);
1356 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1358 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1359 brw_inst_set_compression(devinfo
, send
, false);
1360 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1361 brw_set_src0(p
, send
, header
);
1362 if (devinfo
->gen
< 6)
1363 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1365 /* Our surface is set up as floats, regardless of what actual data is
1368 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1369 brw_set_sampler_message(p
, send
,
1371 0, /* sampler (unused) */
1375 inst
->header_size
!= 0,
1381 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1383 struct brw_reg index
,
1384 struct brw_reg offset
)
1386 assert(devinfo
->gen
>= 7);
1387 /* Varying-offset pull constant loads are treated as a normal expression on
1388 * gen7, so the fact that it's a send message is hidden at the IR level.
1390 assert(inst
->header_size
== 0);
1391 assert(!inst
->mlen
);
1392 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1394 uint32_t simd_mode
, rlen
, mlen
;
1395 if (inst
->exec_size
== 16) {
1398 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1400 assert(inst
->exec_size
== 8);
1403 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1406 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1408 uint32_t surf_index
= index
.ud
;
1410 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1411 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1412 brw_set_src0(p
, send
, offset
);
1413 brw_set_sampler_message(p
, send
,
1415 0, /* LD message ignores sampler unit */
1416 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1419 false, /* no header */
1425 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1427 brw_push_insn_state(p
);
1428 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1430 /* a0.0 = surf_index & 0xff */
1431 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1432 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1433 brw_set_dest(p
, insn_and
, addr
);
1434 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1435 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1437 brw_pop_insn_state(p
);
1439 /* dst = send(offset, a0.0 | <descriptor>) */
1440 brw_inst
*insn
= brw_send_indirect_message(
1441 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1443 brw_set_sampler_message(p
, insn
,
1446 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1456 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1457 * into the flags register (f0.0).
1459 * Used only on Gen6 and above.
1462 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1464 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1465 struct brw_reg dispatch_mask
;
1467 if (devinfo
->gen
>= 6)
1468 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1470 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1472 brw_push_insn_state(p
);
1473 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1474 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1475 brw_MOV(p
, flags
, dispatch_mask
);
1476 brw_pop_insn_state(p
);
1480 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1483 struct brw_reg msg_data
,
1486 assert(inst
->size_written
% REG_SIZE
== 0);
1487 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1489 brw_pixel_interpolator_query(p
,
1490 retype(dst
, BRW_REGISTER_TYPE_UW
),
1492 inst
->pi_noperspective
,
1496 inst
->size_written
/ REG_SIZE
);
1499 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1500 * the ADD instruction.
1503 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1505 struct brw_reg src0
,
1506 struct brw_reg src1
)
1508 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1509 dst
.type
== BRW_REGISTER_TYPE_UD
);
1510 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1511 src0
.type
== BRW_REGISTER_TYPE_UD
);
1513 struct brw_reg reg
= stride(src1
, 1, 4, 0);
1514 if (devinfo
->gen
>= 8 || inst
->exec_size
== 8) {
1515 brw_ADD(p
, dst
, src0
, reg
);
1516 } else if (inst
->exec_size
== 16) {
1517 brw_push_insn_state(p
);
1518 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1519 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1520 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1521 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1522 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1523 brw_pop_insn_state(p
);
1528 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1533 assert(devinfo
->gen
>= 7);
1534 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1535 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1536 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1538 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1540 * Because this instruction does not have a 16-bit floating-point type,
1541 * the destination data type must be Word (W).
1543 * The destination must be DWord-aligned and specify a horizontal stride
1544 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1545 * each destination channel and the upper word is not modified.
1547 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1549 /* Give each 32-bit channel of dst the form below, where "." means
1553 brw_F32TO16(p
, dst_w
, y
);
1558 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1560 /* And, finally the form of packHalf2x16's output:
1563 brw_F32TO16(p
, dst_w
, x
);
1567 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1571 assert(devinfo
->gen
>= 7);
1572 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1573 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1575 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1577 * Because this instruction does not have a 16-bit floating-point type,
1578 * the source data type must be Word (W). The destination type must be
1581 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1583 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1584 * For the Y case, we wish to access only the upper word; therefore
1585 * a 16-bit subregister offset is needed.
1587 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1588 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1589 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1592 brw_F16TO32(p
, dst
, src_w
);
1596 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1597 struct brw_reg payload
,
1598 struct brw_reg offset
,
1599 struct brw_reg value
)
1601 assert(devinfo
->gen
>= 7);
1602 brw_push_insn_state(p
);
1603 brw_set_default_mask_control(p
, true);
1605 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1606 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1608 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1611 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1612 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1613 value
.width
= BRW_WIDTH_1
;
1614 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1615 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1617 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1620 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1621 * case, and we don't really care about squeezing every bit of performance
1622 * out of this path, so we just emit the MOVs from here.
1624 brw_MOV(p
, payload_offset
, offset
);
1625 brw_MOV(p
, payload_value
, value
);
1626 brw_shader_time_add(p
, payload
,
1627 prog_data
->binding_table
.shader_time_start
);
1628 brw_pop_insn_state(p
);
1630 brw_mark_surface_used(prog_data
,
1631 prog_data
->binding_table
.shader_time_start
);
1635 fs_generator::enable_debug(const char *shader_name
)
1638 this->shader_name
= shader_name
;
1642 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1644 /* align to 64 byte boundary. */
1645 while (p
->next_insn_offset
% 64)
1648 this->dispatch_width
= dispatch_width
;
1650 int start_offset
= p
->next_insn_offset
;
1651 int spill_count
= 0, fill_count
= 0;
1654 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1656 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1657 struct brw_reg src
[3], dst
;
1658 unsigned int last_insn_offset
= p
->next_insn_offset
;
1659 bool multiple_instructions_emitted
= false;
1661 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1662 * "Register Region Restrictions" section: for BDW, SKL:
1664 * "A POW/FDIV operation must not be followed by an instruction
1665 * that requires two destination registers."
1667 * The documentation is often lacking annotations for Atom parts,
1668 * and empirically this affects CHV as well.
1670 if (devinfo
->gen
>= 8 &&
1671 devinfo
->gen
<= 9 &&
1673 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1674 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1675 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1677 last_insn_offset
= p
->next_insn_offset
;
1680 if (unlikely(debug_flag
))
1681 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1683 /* If the instruction writes to more than one register, it needs to be
1684 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1685 * hardware figures out by itself what the right compression mode is,
1686 * but we still need to know whether the instruction is compressed to
1687 * set up the source register regions appropriately.
1689 * XXX - This is wrong for instructions that write a single register but
1690 * read more than one which should strictly speaking be treated as
1691 * compressed. For instructions that don't write any registers it
1692 * relies on the destination being a null register of the correct
1693 * type and regioning so the instruction is considered compressed
1694 * or not accordingly.
1696 const bool compressed
=
1697 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1698 brw_set_default_compression(p
, compressed
);
1699 brw_set_default_group(p
, inst
->group
);
1701 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1702 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1703 &inst
->src
[i
], compressed
);
1704 /* The accumulator result appears to get used for the
1705 * conditional modifier generation. When negating a UD
1706 * value, there is a 33rd bit generated for the sign in the
1707 * accumulator value, so now you can't check, for example,
1708 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1710 assert(!inst
->conditional_mod
||
1711 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1712 !inst
->src
[i
].negate
);
1714 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1715 &inst
->dst
, compressed
);
1717 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1718 brw_set_default_predicate_control(p
, inst
->predicate
);
1719 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1720 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1721 brw_set_default_saturate(p
, inst
->saturate
);
1722 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1723 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1725 unsigned exec_size
= inst
->exec_size
;
1726 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1727 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1731 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1733 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1734 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1735 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1736 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1738 switch (inst
->opcode
) {
1739 case BRW_OPCODE_MOV
:
1740 brw_MOV(p
, dst
, src
[0]);
1742 case BRW_OPCODE_ADD
:
1743 brw_ADD(p
, dst
, src
[0], src
[1]);
1745 case BRW_OPCODE_MUL
:
1746 brw_MUL(p
, dst
, src
[0], src
[1]);
1748 case BRW_OPCODE_AVG
:
1749 brw_AVG(p
, dst
, src
[0], src
[1]);
1751 case BRW_OPCODE_MACH
:
1752 brw_MACH(p
, dst
, src
[0], src
[1]);
1755 case BRW_OPCODE_LINE
:
1756 brw_LINE(p
, dst
, src
[0], src
[1]);
1759 case BRW_OPCODE_MAD
:
1760 assert(devinfo
->gen
>= 6);
1761 if (devinfo
->gen
< 10)
1762 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1763 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1766 case BRW_OPCODE_LRP
:
1767 assert(devinfo
->gen
>= 6);
1768 if (devinfo
->gen
< 10)
1769 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1770 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1773 case BRW_OPCODE_FRC
:
1774 brw_FRC(p
, dst
, src
[0]);
1776 case BRW_OPCODE_RNDD
:
1777 brw_RNDD(p
, dst
, src
[0]);
1779 case BRW_OPCODE_RNDE
:
1780 brw_RNDE(p
, dst
, src
[0]);
1782 case BRW_OPCODE_RNDZ
:
1783 brw_RNDZ(p
, dst
, src
[0]);
1786 case BRW_OPCODE_AND
:
1787 brw_AND(p
, dst
, src
[0], src
[1]);
1790 brw_OR(p
, dst
, src
[0], src
[1]);
1792 case BRW_OPCODE_XOR
:
1793 brw_XOR(p
, dst
, src
[0], src
[1]);
1795 case BRW_OPCODE_NOT
:
1796 brw_NOT(p
, dst
, src
[0]);
1798 case BRW_OPCODE_ASR
:
1799 brw_ASR(p
, dst
, src
[0], src
[1]);
1801 case BRW_OPCODE_SHR
:
1802 brw_SHR(p
, dst
, src
[0], src
[1]);
1804 case BRW_OPCODE_SHL
:
1805 brw_SHL(p
, dst
, src
[0], src
[1]);
1807 case BRW_OPCODE_F32TO16
:
1808 assert(devinfo
->gen
>= 7);
1809 brw_F32TO16(p
, dst
, src
[0]);
1811 case BRW_OPCODE_F16TO32
:
1812 assert(devinfo
->gen
>= 7);
1813 brw_F16TO32(p
, dst
, src
[0]);
1815 case BRW_OPCODE_CMP
:
1816 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1817 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1818 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1819 * implemented in the compiler is not sufficient. Overriding the
1820 * type when the destination is the null register is necessary but
1821 * not sufficient by itself.
1823 assert(dst
.nr
== BRW_ARF_NULL
);
1824 dst
.type
= BRW_REGISTER_TYPE_D
;
1826 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1828 case BRW_OPCODE_SEL
:
1829 brw_SEL(p
, dst
, src
[0], src
[1]);
1831 case BRW_OPCODE_BFREV
:
1832 assert(devinfo
->gen
>= 7);
1833 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1834 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1836 case BRW_OPCODE_FBH
:
1837 assert(devinfo
->gen
>= 7);
1838 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1840 case BRW_OPCODE_FBL
:
1841 assert(devinfo
->gen
>= 7);
1842 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1843 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1845 case BRW_OPCODE_LZD
:
1846 brw_LZD(p
, dst
, src
[0]);
1848 case BRW_OPCODE_CBIT
:
1849 assert(devinfo
->gen
>= 7);
1850 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1851 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1853 case BRW_OPCODE_ADDC
:
1854 assert(devinfo
->gen
>= 7);
1855 brw_ADDC(p
, dst
, src
[0], src
[1]);
1857 case BRW_OPCODE_SUBB
:
1858 assert(devinfo
->gen
>= 7);
1859 brw_SUBB(p
, dst
, src
[0], src
[1]);
1861 case BRW_OPCODE_MAC
:
1862 brw_MAC(p
, dst
, src
[0], src
[1]);
1865 case BRW_OPCODE_BFE
:
1866 assert(devinfo
->gen
>= 7);
1867 if (devinfo
->gen
< 10)
1868 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1869 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1872 case BRW_OPCODE_BFI1
:
1873 assert(devinfo
->gen
>= 7);
1874 brw_BFI1(p
, dst
, src
[0], src
[1]);
1876 case BRW_OPCODE_BFI2
:
1877 assert(devinfo
->gen
>= 7);
1878 if (devinfo
->gen
< 10)
1879 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1880 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1884 if (inst
->src
[0].file
!= BAD_FILE
) {
1885 /* The instruction has an embedded compare (only allowed on gen6) */
1886 assert(devinfo
->gen
== 6);
1887 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1889 brw_IF(p
, brw_inst_exec_size(devinfo
, p
->current
));
1893 case BRW_OPCODE_ELSE
:
1896 case BRW_OPCODE_ENDIF
:
1901 brw_DO(p
, brw_inst_exec_size(devinfo
, p
->current
));
1904 case BRW_OPCODE_BREAK
:
1907 case BRW_OPCODE_CONTINUE
:
1911 case BRW_OPCODE_WHILE
:
1916 case SHADER_OPCODE_RCP
:
1917 case SHADER_OPCODE_RSQ
:
1918 case SHADER_OPCODE_SQRT
:
1919 case SHADER_OPCODE_EXP2
:
1920 case SHADER_OPCODE_LOG2
:
1921 case SHADER_OPCODE_SIN
:
1922 case SHADER_OPCODE_COS
:
1923 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1924 if (devinfo
->gen
>= 6) {
1925 assert(inst
->mlen
== 0);
1926 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
1927 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
1928 src
[0], brw_null_reg());
1930 assert(inst
->mlen
>= 1);
1931 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
1933 brw_math_function(inst
->opcode
),
1934 inst
->base_mrf
, src
[0],
1935 BRW_MATH_PRECISION_FULL
);
1938 case SHADER_OPCODE_INT_QUOTIENT
:
1939 case SHADER_OPCODE_INT_REMAINDER
:
1940 case SHADER_OPCODE_POW
:
1941 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1942 if (devinfo
->gen
>= 6) {
1943 assert(inst
->mlen
== 0);
1944 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
1945 inst
->exec_size
== 8);
1946 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1948 assert(inst
->mlen
>= 1);
1949 assert(inst
->exec_size
== 8);
1950 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
1951 inst
->base_mrf
, src
[0],
1952 BRW_MATH_PRECISION_FULL
);
1955 case FS_OPCODE_CINTERP
:
1956 brw_MOV(p
, dst
, src
[0]);
1958 case FS_OPCODE_LINTERP
:
1959 generate_linterp(inst
, dst
, src
);
1961 case FS_OPCODE_PIXEL_X
:
1962 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1963 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1964 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1966 case FS_OPCODE_PIXEL_Y
:
1967 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1968 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1969 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1971 case FS_OPCODE_GET_BUFFER_SIZE
:
1972 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
1974 case SHADER_OPCODE_TEX
:
1976 case SHADER_OPCODE_TXD
:
1977 case SHADER_OPCODE_TXF
:
1978 case SHADER_OPCODE_TXF_LZ
:
1979 case SHADER_OPCODE_TXF_CMS
:
1980 case SHADER_OPCODE_TXF_CMS_W
:
1981 case SHADER_OPCODE_TXF_UMS
:
1982 case SHADER_OPCODE_TXF_MCS
:
1983 case SHADER_OPCODE_TXL
:
1984 case SHADER_OPCODE_TXL_LZ
:
1985 case SHADER_OPCODE_TXS
:
1986 case SHADER_OPCODE_LOD
:
1987 case SHADER_OPCODE_TG4
:
1988 case SHADER_OPCODE_TG4_OFFSET
:
1989 case SHADER_OPCODE_SAMPLEINFO
:
1990 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
1992 case FS_OPCODE_DDX_COARSE
:
1993 case FS_OPCODE_DDX_FINE
:
1994 generate_ddx(inst
->opcode
, dst
, src
[0]);
1996 case FS_OPCODE_DDY_COARSE
:
1997 case FS_OPCODE_DDY_FINE
:
1998 generate_ddy(inst
->opcode
, dst
, src
[0]);
2001 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2002 generate_scratch_write(inst
, src
[0]);
2006 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2007 generate_scratch_read(inst
, dst
);
2011 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2012 generate_scratch_read_gen7(inst
, dst
);
2016 case SHADER_OPCODE_MOV_INDIRECT
:
2017 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2020 case SHADER_OPCODE_URB_READ_SIMD8
:
2021 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2022 generate_urb_read(inst
, dst
, src
[0]);
2025 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2026 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2027 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2028 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2029 generate_urb_write(inst
, src
[0]);
2032 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2033 assert(inst
->force_writemask_all
);
2034 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2037 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2038 assert(inst
->force_writemask_all
);
2039 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2042 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2043 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2046 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2047 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2050 case FS_OPCODE_REP_FB_WRITE
:
2051 case FS_OPCODE_FB_WRITE
:
2052 generate_fb_write(inst
, src
[0]);
2055 case FS_OPCODE_FB_READ
:
2056 generate_fb_read(inst
, dst
, src
[0]);
2059 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2060 generate_mov_dispatch_to_flags(inst
);
2063 case FS_OPCODE_DISCARD_JUMP
:
2064 generate_discard_jump(inst
);
2067 case SHADER_OPCODE_SHADER_TIME_ADD
:
2068 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2071 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2072 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2073 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2074 inst
->mlen
, !inst
->dst
.is_null());
2077 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2078 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2079 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2080 inst
->mlen
, src
[2].ud
);
2083 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2084 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2085 brw_untyped_surface_write(p
, src
[0], src
[1],
2086 inst
->mlen
, src
[2].ud
);
2089 case SHADER_OPCODE_BYTE_SCATTERED_READ
:
2090 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2091 brw_byte_scattered_read(p
, dst
, src
[0], src
[1],
2092 inst
->mlen
, src
[2].ud
);
2095 case SHADER_OPCODE_BYTE_SCATTERED_WRITE
:
2096 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2097 brw_byte_scattered_write(p
, src
[0], src
[1],
2098 inst
->mlen
, src
[2].ud
);
2101 case SHADER_OPCODE_TYPED_ATOMIC
:
2102 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2103 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2104 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null());
2107 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2108 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2109 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2110 inst
->mlen
, src
[2].ud
);
2113 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2114 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2115 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
);
2118 case SHADER_OPCODE_MEMORY_FENCE
:
2119 brw_memory_fence(p
, dst
);
2122 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2123 const struct brw_reg mask
=
2124 brw_stage_has_packed_dispatch(devinfo
, stage
,
2125 prog_data
) ? brw_imm_ud(~0u) :
2126 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2128 brw_find_live_channel(p
, dst
, mask
);
2132 case SHADER_OPCODE_BROADCAST
:
2133 assert(inst
->force_writemask_all
);
2134 brw_broadcast(p
, dst
, src
[0], src
[1]);
2137 case FS_OPCODE_SET_SAMPLE_ID
:
2138 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2141 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2142 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2145 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2146 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2147 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2150 case FS_OPCODE_PLACEHOLDER_HALT
:
2151 /* This is the place where the final HALT needs to be inserted if
2152 * we've emitted any discards. If not, this will emit no code.
2154 if (!patch_discard_jumps_to_fb_writes()) {
2155 if (unlikely(debug_flag
)) {
2156 disasm_info
->use_tail
= true;
2161 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2162 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2163 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2166 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2167 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2168 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2171 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2172 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2173 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2176 case CS_OPCODE_CS_TERMINATE
:
2177 generate_cs_terminate(inst
, src
[0]);
2180 case SHADER_OPCODE_BARRIER
:
2181 generate_barrier(inst
, src
[0]);
2184 case BRW_OPCODE_DIM
:
2185 assert(devinfo
->is_haswell
);
2186 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2187 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2188 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2191 case SHADER_OPCODE_RND_MODE
:
2192 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2193 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2197 unreachable("Unsupported opcode");
2199 case SHADER_OPCODE_LOAD_PAYLOAD
:
2200 unreachable("Should be lowered by lower_load_payload()");
2203 if (multiple_instructions_emitted
)
2206 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2207 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2208 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2209 "emitting more than 1 instruction");
2211 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2213 if (inst
->conditional_mod
)
2214 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2215 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2216 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2220 brw_set_uip_jip(p
, start_offset
);
2222 /* end of program sentinel */
2223 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2228 if (unlikely(debug_flag
))
2230 brw_validate_instructions(devinfo
, p
->store
,
2232 p
->next_insn_offset
,
2235 int before_size
= p
->next_insn_offset
- start_offset
;
2236 brw_compact_instructions(p
, start_offset
, disasm_info
);
2237 int after_size
= p
->next_insn_offset
- start_offset
;
2239 if (unlikely(debug_flag
)) {
2240 fprintf(stderr
, "Native code for %s\n"
2241 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2242 " bytes (%.0f%%)\n",
2243 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2244 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2245 100.0f
* (before_size
- after_size
) / before_size
);
2247 dump_assembly(p
->store
, disasm_info
);
2249 ralloc_free(disasm_info
);
2252 compiler
->shader_debug_log(log_data
,
2253 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2254 "%d:%d spills:fills, Promoted %u constants, "
2255 "compacted %d to %d bytes.",
2256 _mesa_shader_stage_to_abbrev(stage
),
2257 dispatch_width
, before_size
/ 16,
2258 loop_count
, cfg
->cycle_count
, spill_count
,
2259 fill_count
, promoted_constants
, before_size
,
2262 return start_offset
;
2266 fs_generator::get_assembly(unsigned int *assembly_size
)
2268 return brw_get_program(p
, assembly_size
);