2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "util/mesa-sha1.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
58 fs_reg
*reg
, bool compressed
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
70 /* From the Haswell PRM:
72 * "VertStride must be used to cross GRF register boundaries. This
73 * rule implies that elements within a 'Width' cannot cross GRF
76 * The maximum width value that could satisfy this restriction is:
78 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
80 /* Because the hardware can only split source regions at a whole
81 * multiple of width during decompression (i.e. vertically), clamp
82 * the value obtained above to the physical execution size of a
83 * single decompressed chunk of the instruction:
85 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
88 const unsigned max_hw_width
= 16;
90 /* XXX - The equation above is strictly speaking not correct on
91 * hardware that supports unbalanced GRF writes -- On Gen9+
92 * each decompressed chunk of the instruction may have a
93 * different execution size when the number of components
94 * written to each destination GRF is not the same.
96 if (reg
->stride
> 4) {
97 assert(reg
!= &inst
->dst
);
98 assert(reg
->stride
* type_sz(reg
->type
) <= REG_SIZE
);
99 brw_reg
= brw_vecn_reg(1, brw_file_from_reg(reg
), reg
->nr
, 0);
100 brw_reg
= stride(brw_reg
, reg
->stride
, 1, 0);
102 const unsigned width
= MIN3(reg_width
, phys_width
, max_hw_width
);
103 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
104 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
107 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
108 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
109 * "Each DF (Double Float) operand uses an element size of 4 rather
110 * than 8 and all regioning parameters are twice what the values
111 * would be based on the true element size: ExecSize, Width,
112 * HorzStride, and VertStride. Each DF operand uses a pair of
113 * channels and all masking and swizzing should be adjusted
116 * From the IvyBridge PRM (Special Requirements for Handling Double
117 * Precision Data Types, page 71):
118 * "In Align1 mode, all regioning parameters like stride, execution
119 * size, and width must use the syntax of a pair of packed
120 * floats. The offsets for these data types must be 64-bit
121 * aligned. The execution size and regioning parameters are in terms
124 * Summarized: when handling DF-typed arguments, ExecSize,
125 * VertStride, and Width must be doubled.
127 * It applies to BayTrail too.
129 if (type_sz(reg
->type
) == 8) {
131 if (brw_reg
.vstride
> 0)
133 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
136 /* When converting from DF->F, we set the destination stride to 2
137 * because each d2f conversion implicitly writes 2 floats, being
138 * the first one the converted value. IVB/BYT actually writes two
139 * F components per SIMD channel, and every other component is
140 * filled with garbage.
142 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
143 type_sz(inst
->dst
.type
) < 8) {
144 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
150 brw_reg
= retype(brw_reg
, reg
->type
);
151 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
152 brw_reg
.abs
= reg
->abs
;
153 brw_reg
.negate
= reg
->negate
;
158 assert(reg
->offset
== 0);
159 brw_reg
= reg
->as_brw_reg();
162 /* Probably unused. */
163 brw_reg
= brw_null_reg();
167 unreachable("not reached");
170 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
171 * region, but on IVB and BYT DF regions must be programmed in terms of
172 * floats. A <0,2,1> region accomplishes this.
174 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
175 type_sz(reg
->type
) == 8 &&
176 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
177 brw_reg
.width
== BRW_WIDTH_1
&&
178 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
179 brw_reg
.width
= BRW_WIDTH_2
;
180 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
186 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
188 struct brw_stage_prog_data
*prog_data
,
189 struct shader_stats shader_stats
,
190 bool runtime_check_aads_emit
,
191 gl_shader_stage stage
)
193 : compiler(compiler
), log_data(log_data
),
194 devinfo(compiler
->devinfo
),
195 prog_data(prog_data
),
196 shader_stats(shader_stats
),
197 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
198 stage(stage
), mem_ctx(mem_ctx
)
200 p
= rzalloc(mem_ctx
, struct brw_codegen
);
201 brw_init_codegen(devinfo
, p
, mem_ctx
);
203 /* In the FS code generator, we are very careful to ensure that we always
204 * set the right execution size so we don't need the EU code to "help" us
205 * by trying to infer it. Sometimes, it infers the wrong thing.
207 p
->automatic_exec_sizes
= false;
210 fs_generator::~fs_generator()
214 class ip_record
: public exec_node
{
216 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
227 fs_generator::patch_discard_jumps_to_fb_writes()
229 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
232 int scale
= brw_jump_scale(p
->devinfo
);
234 /* There is a somewhat strange undocumented requirement of using
235 * HALT, according to the simulator. If some channel has HALTed to
236 * a particular UIP, then by the end of the program, every channel
237 * must have HALTed to that UIP. Furthermore, the tracking is a
238 * stack, so you can't do the final halt of a UIP after starting
239 * halting to a new UIP.
241 * Symptoms of not emitting this instruction on actual hardware
242 * included GPU hangs and sparkly rendering on the piglit discard
245 brw_inst
*last_halt
= gen6_HALT(p
);
246 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
247 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
251 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
252 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
254 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
255 /* HALT takes a half-instruction distance from the pre-incremented IP. */
256 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
259 this->discard_halt_patches
.make_empty();
264 fs_generator::generate_send(fs_inst
*inst
,
267 struct brw_reg ex_desc
,
268 struct brw_reg payload
,
269 struct brw_reg payload2
)
271 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
272 dst
.nr
== BRW_ARF_NULL
;
273 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
275 uint32_t desc_imm
= inst
->desc
|
276 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
278 uint32_t ex_desc_imm
= brw_message_ex_desc(devinfo
, inst
->ex_mlen
);
280 if (ex_desc
.file
!= BRW_IMMEDIATE_VALUE
|| ex_desc
.ud
|| ex_desc_imm
) {
281 /* If we have any sort of extended descriptor, then we need SENDS. This
282 * also covers the dual-payload case because ex_mlen goes in ex_desc.
284 brw_send_indirect_split_message(p
, inst
->sfid
, dst
, payload
, payload2
,
285 desc
, desc_imm
, ex_desc
, ex_desc_imm
,
288 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDSC
);
290 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
,
293 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
298 fs_generator::fire_fb_write(fs_inst
*inst
,
299 struct brw_reg payload
,
300 struct brw_reg implied_header
,
303 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
305 if (devinfo
->gen
< 6) {
306 brw_push_insn_state(p
);
307 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
308 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
309 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
310 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
311 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
312 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
313 brw_pop_insn_state(p
);
316 uint32_t msg_control
= brw_fb_write_msg_control(inst
, prog_data
);
318 /* We assume render targets start at 0, because headerless FB write
319 * messages set "Render Target Index" to 0. Using a different binding
320 * table index would make it impossible to use headerless messages.
322 const uint32_t surf_index
= inst
->target
;
324 brw_inst
*insn
= brw_fb_WRITE(p
,
326 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
333 inst
->header_size
!= 0);
335 if (devinfo
->gen
>= 6)
336 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
340 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
342 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
343 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
344 brw_set_default_flag_reg(p
, 0, 0);
347 const struct brw_reg implied_header
=
348 devinfo
->gen
< 6 ? payload
: brw_null_reg();
350 if (inst
->base_mrf
>= 0)
351 payload
= brw_message_reg(inst
->base_mrf
);
353 if (!runtime_check_aads_emit
) {
354 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
356 /* This can only happen in gen < 6 */
357 assert(devinfo
->gen
< 6);
359 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
361 /* Check runtime bit to detect if we have to send AA data or not */
362 brw_push_insn_state(p
);
363 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
364 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
367 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
369 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
371 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
372 brw_pop_insn_state(p
);
374 /* Don't send AA data */
375 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
377 brw_land_fwd_jump(p
, jmp
);
378 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
383 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
384 struct brw_reg payload
)
386 assert(inst
->size_written
% REG_SIZE
== 0);
387 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
388 /* We assume that render targets start at binding table index 0. */
389 const unsigned surf_index
= inst
->target
;
391 gen9_fb_READ(p
, dst
, payload
, surf_index
,
392 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
393 prog_data
->persample_dispatch
);
397 fs_generator::generate_mov_indirect(fs_inst
*inst
,
400 struct brw_reg indirect_byte_offset
)
402 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
403 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
404 assert(!reg
.abs
&& !reg
.negate
);
405 assert(reg
.type
== dst
.type
);
407 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
409 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
410 imm_byte_offset
+= indirect_byte_offset
.ud
;
412 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
413 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
414 brw_MOV(p
, dst
, reg
);
416 /* Prior to Broadwell, there are only 8 address registers. */
417 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
419 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
420 struct brw_reg addr
= vec8(brw_address_reg(0));
422 /* The destination stride of an instruction (in bytes) must be greater
423 * than or equal to the size of the rest of the instruction. Since the
424 * address register is of type UW, we can't use a D-type instruction.
425 * In order to get around this, re retype to UW and use a stride.
427 indirect_byte_offset
=
428 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
430 /* There are a number of reasons why we don't use the base offset here.
431 * One reason is that the field is only 9 bits which means we can only
432 * use it to access the first 16 GRFs. Also, from the Haswell PRM
433 * section "Register Region Restrictions":
435 * "The lower bits of the AddressImmediate must not overflow to
436 * change the register address. The lower 5 bits of Address
437 * Immediate when added to lower 5 bits of address register gives
438 * the sub-register offset. The upper bits of Address Immediate
439 * when added to upper bits of address register gives the register
440 * address. Any overflow from sub-register offset is dropped."
442 * Since the indirect may cause us to cross a register boundary, this
443 * makes the base offset almost useless. We could try and do something
444 * clever where we use a actual base offset if base_offset % 32 == 0 but
445 * that would mean we were generating different code depending on the
446 * base offset. Instead, for the sake of consistency, we'll just do the
447 * add ourselves. This restriction is only listed in the Haswell PRM
448 * but empirical testing indicates that it applies on all older
449 * generations and is lifted on Broadwell.
451 * In the end, while base_offset is nice to look at in the generated
452 * code, using it saves us 0 instructions and would require quite a bit
453 * of case-by-case work. It's just not worth it.
455 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
457 if (type_sz(reg
.type
) > 4 &&
458 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
459 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
460 !devinfo
->has_64bit_types
)) {
461 /* IVB has an issue (which we found empirically) where it reads two
462 * address register components per channel for indirectly addressed
465 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
467 * "When source or destination datatype is 64b or operation is
468 * integer DWord multiply, indirect addressing must not be used."
470 * To work around both of these, we do two integer MOVs insead of one
471 * 64-bit MOV. Because no double value should ever cross a register
472 * boundary, it's safe to use the immediate offset in the indirect
473 * here to handle adding 4 bytes to the offset and avoid the extra
474 * ADD to the register file.
476 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
477 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
478 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
479 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
481 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
483 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
485 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
486 !inst
->get_next()->is_tail_sentinel() &&
487 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
488 /* From the Sandybridge PRM:
490 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
491 * instruction that “indexed/indirect” source AND is followed
492 * by a send, the instruction requires a “Switch”. This is to
493 * avoid race condition where send may dispatch before MRF is
496 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
503 fs_generator::generate_shuffle(fs_inst
*inst
,
508 /* Ivy bridge has some strange behavior that makes this a real pain to
509 * implement for 64-bit values so we just don't bother.
511 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
513 /* Because we're using the address register, we're limited to 8-wide
514 * execution on gen7. On gen8, we're limited to 16-wide by the address
515 * register file and 8-wide for 64-bit types. We could try and make this
516 * instruction splittable higher up in the compiler but that gets weird
517 * because it reads all of the channels regardless of execution size. It's
518 * easier just to split it here.
520 const unsigned lower_width
=
521 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
522 8 : MIN2(16, inst
->exec_size
);
524 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
525 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
526 brw_set_default_group(p
, group
);
528 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
529 idx
.file
== BRW_IMMEDIATE_VALUE
) {
530 /* Trivial, the source is already uniform or the index is a constant.
531 * We will typically not get here if the optimizer is doing its job,
532 * but asserting would be mean.
534 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
535 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
537 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
538 struct brw_reg addr
= vec8(brw_address_reg(0));
540 struct brw_reg group_idx
= suboffset(idx
, group
);
542 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
543 /* Things get grumpy if the register is too wide. */
548 assert(type_sz(group_idx
.type
) <= 4);
549 if (type_sz(group_idx
.type
) == 4) {
550 /* The destination stride of an instruction (in bytes) must be
551 * greater than or equal to the size of the rest of the
552 * instruction. Since the address register is of type UW, we
553 * can't use a D-type instruction. In order to get around this,
554 * re retype to UW and use a stride.
556 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
559 /* Take into account the component size and horizontal stride. */
560 assert(src
.vstride
== src
.hstride
+ src
.width
);
561 brw_SHL(p
, addr
, group_idx
,
562 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
565 /* Add on the register start offset */
566 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
568 if (type_sz(src
.type
) > 4 &&
569 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
570 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
571 /* IVB has an issue (which we found empirically) where it reads
572 * two address register components per channel for indirectly
573 * addressed 64-bit sources.
575 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
577 * "When source or destination datatype is 64b or operation is
578 * integer DWord multiply, indirect addressing must not be
581 * To work around both of these, we do two integer MOVs insead of
582 * one 64-bit MOV. Because no double value should ever cross a
583 * register boundary, it's safe to use the immediate offset in the
584 * indirect here to handle adding 4 bytes to the offset and avoid
585 * the extra ADD to the register file.
587 struct brw_reg gdst
= suboffset(dst
, group
);
588 struct brw_reg dst_d
= retype(spread(gdst
, 2),
589 BRW_REGISTER_TYPE_D
);
591 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
592 brw_MOV(p
, byte_offset(dst_d
, 4),
593 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
595 brw_MOV(p
, suboffset(dst
, group
),
596 retype(brw_VxH_indirect(0, 0), src
.type
));
603 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
604 struct brw_reg dst
, struct brw_reg src
,
607 /* Requires a quad. */
608 assert(inst
->exec_size
>= 4);
610 if (src
.file
== BRW_IMMEDIATE_VALUE
||
611 has_scalar_region(src
)) {
612 /* The value is uniform across all channels */
613 brw_MOV(p
, dst
, src
);
615 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
616 /* This only works on 8-wide 32-bit values */
617 assert(inst
->exec_size
== 8);
618 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
619 assert(src
.vstride
== src
.width
+ 1);
620 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
621 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
622 swiz_src
.swizzle
= swiz
;
623 brw_MOV(p
, dst
, swiz_src
);
626 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
627 assert(src
.vstride
== src
.width
+ 1);
628 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
631 case BRW_SWIZZLE_XXXX
:
632 case BRW_SWIZZLE_YYYY
:
633 case BRW_SWIZZLE_ZZZZ
:
634 case BRW_SWIZZLE_WWWW
:
635 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
638 case BRW_SWIZZLE_XXZZ
:
639 case BRW_SWIZZLE_YYWW
:
640 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
643 case BRW_SWIZZLE_XYXY
:
644 case BRW_SWIZZLE_ZWZW
:
645 assert(inst
->exec_size
== 4);
646 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
650 assert(inst
->force_writemask_all
);
651 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
653 for (unsigned c
= 0; c
< 4; c
++) {
654 brw_inst
*insn
= brw_MOV(
655 p
, stride(suboffset(dst
, c
),
656 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
657 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
659 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
660 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
669 fs_generator::generate_urb_read(fs_inst
*inst
,
671 struct brw_reg header
)
673 assert(inst
->size_written
% REG_SIZE
== 0);
674 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
675 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
677 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
678 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
679 brw_set_src0(p
, send
, header
);
680 brw_set_src1(p
, send
, brw_imm_ud(0u));
682 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
683 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
685 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
686 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
688 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
689 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
690 brw_inst_set_header_present(p
->devinfo
, send
, true);
691 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
695 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
699 /* WaClearTDRRegBeforeEOTForNonPS.
701 * WA: Clear tdr register before send EOT in all non-PS shader kernels
703 * mov(8) tdr0:ud 0x0:ud {NoMask}"
705 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
706 brw_push_insn_state(p
);
707 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
708 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
709 brw_pop_insn_state(p
);
712 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
714 brw_set_dest(p
, insn
, brw_null_reg());
715 brw_set_src0(p
, insn
, payload
);
716 brw_set_src1(p
, insn
, brw_imm_ud(0u));
718 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
719 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
721 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
722 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
723 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
725 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
726 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
727 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
729 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
730 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
731 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
732 brw_inst_set_header_present(p
->devinfo
, insn
, true);
733 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
737 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
739 struct brw_inst
*insn
;
741 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
743 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
744 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
745 brw_set_src1(p
, insn
, brw_imm_ud(0u));
747 /* Terminate a compute shader by sending a message to the thread spawner.
749 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
750 brw_inst_set_mlen(devinfo
, insn
, 1);
751 brw_inst_set_rlen(devinfo
, insn
, 0);
752 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
753 brw_inst_set_header_present(devinfo
, insn
, false);
755 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
756 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
758 /* Note that even though the thread has a URB resource associated with it,
759 * we set the "do not dereference URB" bit, because the URB resource is
760 * managed by the fixed-function unit, so it will free it automatically.
762 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
764 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
768 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
775 fs_generator::generate_linterp(fs_inst
*inst
,
776 struct brw_reg dst
, struct brw_reg
*src
)
780 * -----------------------------------
781 * | src1+0 | src1+1 | src1+2 | src1+3 |
782 * |-----------------------------------|
783 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
784 * -----------------------------------
786 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
788 * -----------------------------------
789 * | src1+0 | src1+1 | src1+2 | src1+3 |
790 * |-----------------------------------|
791 * |(x0, x1)|(y0, y1)| | | in SIMD8
792 * |-----------------------------------|
793 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
794 * -----------------------------------
796 * See also: emit_interpolation_setup_gen4().
798 struct brw_reg delta_x
= src
[0];
799 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
800 struct brw_reg interp
= src
[1];
803 /* nir_lower_interpolation() will do the lowering to MAD instructions for
806 assert(devinfo
->gen
< 11);
808 if (devinfo
->has_pln
) {
809 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
810 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
812 * "[DevSNB]:<src1> must be even register aligned.
814 * This restriction is lifted on Ivy Bridge.
816 * This means that we need to split PLN into LINE+MAC on-the-fly.
817 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
818 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
819 * coordinate registers are laid out differently so we leave it as a
820 * SIMD16 instruction.
822 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
823 assert(inst
->group
% 16 == 0);
825 brw_push_insn_state(p
);
826 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
828 /* Thanks to two accumulators, we can emit all the LINEs and then all
829 * the MACs. This improves parallelism a bit.
831 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
832 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
833 offset(delta_x
, g
* 2));
834 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
836 /* LINE writes the accumulator automatically on gen4-5. On Sandy
837 * Bridge and later, we have to explicitly enable it.
839 if (devinfo
->gen
>= 6)
840 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
842 /* brw_set_default_saturate() is called before emitting
843 * instructions, so the saturate bit is set in each instruction,
844 * so we need to unset it on the LINE instructions.
846 brw_inst_set_saturate(p
->devinfo
, line
, false);
849 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
850 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
851 offset(delta_x
, g
* 2 + 1));
852 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
853 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
856 brw_pop_insn_state(p
);
860 brw_PLN(p
, dst
, interp
, delta_x
);
865 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
866 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
868 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
870 /* brw_set_default_saturate() is called before emitting instructions, so
871 * the saturate bit is set in each instruction, so we need to unset it on
872 * the first instruction.
874 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
881 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
884 struct brw_reg surf_index
)
886 assert(devinfo
->gen
>= 7);
887 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
892 switch (inst
->exec_size
) {
894 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
897 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
900 unreachable("Invalid width for texture instruction");
903 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
909 retype(dst
, BRW_REGISTER_TYPE_UW
),
914 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
915 rlen
, /* response length */
917 inst
->header_size
> 0,
919 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
923 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
924 struct brw_reg surface_index
,
925 struct brw_reg sampler_index
)
927 assert(devinfo
->gen
< 7);
928 assert(inst
->size_written
% REG_SIZE
== 0);
931 uint32_t return_format
;
933 /* Sampler EOT message of less than the dispatch width would kill the
934 * thread prematurely.
936 assert(!inst
->eot
|| inst
->exec_size
== dispatch_width
);
939 case BRW_REGISTER_TYPE_D
:
940 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
942 case BRW_REGISTER_TYPE_UD
:
943 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
946 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
950 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
951 * is set as part of the message descriptor. On gen4, the PRM seems to
952 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
953 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
954 * gone from the message descriptor entirely and you just get UINT32 all
955 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
956 * just stomp it to UINT32 all the time.
958 if (inst
->opcode
== SHADER_OPCODE_TXS
)
959 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
961 switch (inst
->exec_size
) {
963 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
966 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
969 unreachable("Invalid width for texture instruction");
972 if (devinfo
->gen
>= 5) {
973 switch (inst
->opcode
) {
974 case SHADER_OPCODE_TEX
:
975 if (inst
->shadow_compare
) {
976 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
978 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
982 if (inst
->shadow_compare
) {
983 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
985 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
988 case SHADER_OPCODE_TXL
:
989 if (inst
->shadow_compare
) {
990 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
992 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
995 case SHADER_OPCODE_TXS
:
996 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
998 case SHADER_OPCODE_TXD
:
999 assert(!inst
->shadow_compare
);
1000 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1002 case SHADER_OPCODE_TXF
:
1003 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1005 case SHADER_OPCODE_TXF_CMS
:
1006 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1008 case SHADER_OPCODE_LOD
:
1009 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1011 case SHADER_OPCODE_TG4
:
1012 assert(devinfo
->gen
== 6);
1013 assert(!inst
->shadow_compare
);
1014 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1016 case SHADER_OPCODE_SAMPLEINFO
:
1017 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1020 unreachable("not reached");
1023 switch (inst
->opcode
) {
1024 case SHADER_OPCODE_TEX
:
1025 /* Note that G45 and older determines shadow compare and dispatch width
1026 * from message length for most messages.
1028 if (inst
->exec_size
== 8) {
1029 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1030 if (inst
->shadow_compare
) {
1031 assert(inst
->mlen
== 6);
1033 assert(inst
->mlen
<= 4);
1036 if (inst
->shadow_compare
) {
1037 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1038 assert(inst
->mlen
== 9);
1040 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1041 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1046 if (inst
->shadow_compare
) {
1047 assert(inst
->exec_size
== 8);
1048 assert(inst
->mlen
== 6);
1049 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1051 assert(inst
->mlen
== 9);
1052 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1053 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1056 case SHADER_OPCODE_TXL
:
1057 if (inst
->shadow_compare
) {
1058 assert(inst
->exec_size
== 8);
1059 assert(inst
->mlen
== 6);
1060 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1062 assert(inst
->mlen
== 9);
1063 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1064 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1067 case SHADER_OPCODE_TXD
:
1068 /* There is no sample_d_c message; comparisons are done manually */
1069 assert(inst
->exec_size
== 8);
1070 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1071 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1073 case SHADER_OPCODE_TXF
:
1074 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1075 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1076 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1078 case SHADER_OPCODE_TXS
:
1079 assert(inst
->mlen
== 3);
1080 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1081 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1084 unreachable("not reached");
1087 assert(msg_type
!= -1);
1089 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1093 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1095 /* Load the message header if present. If there's a texture offset,
1096 * we need to set it up explicitly and load the offset bitfield.
1097 * Otherwise, we can use an implied move from g0 to the first message reg.
1099 struct brw_reg src
= brw_null_reg();
1100 if (inst
->header_size
!= 0) {
1101 if (devinfo
->gen
< 6 && !inst
->offset
) {
1102 /* Set up an implied move from g0 to the MRF. */
1103 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1105 assert(inst
->base_mrf
!= -1);
1106 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1108 brw_push_insn_state(p
);
1109 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1110 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1111 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1112 /* Explicitly set up the message header by copying g0 to the MRF. */
1113 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1115 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1117 /* Set the offset bits in DWord 2. */
1118 brw_MOV(p
, get_element_ud(header_reg
, 2),
1119 brw_imm_ud(inst
->offset
));
1122 brw_pop_insn_state(p
);
1126 uint32_t base_binding_table_index
;
1127 switch (inst
->opcode
) {
1128 case SHADER_OPCODE_TG4
:
1129 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1132 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1136 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1137 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1140 retype(dst
, BRW_REGISTER_TYPE_UW
),
1143 surface_index
.ud
+ base_binding_table_index
,
1144 sampler_index
.ud
% 16,
1146 inst
->size_written
/ REG_SIZE
,
1148 inst
->header_size
!= 0,
1154 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1157 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1159 * Ideally, we want to produce:
1162 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1163 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1164 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1165 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1166 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1167 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1168 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1169 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1171 * and add another set of two more subspans if in 16-pixel dispatch mode.
1173 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1174 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1175 * pair. But the ideal approximation may impose a huge performance cost on
1176 * sample_d. On at least Haswell, sample_d instruction does some
1177 * optimizations if the same LOD is used for all pixels in the subspan.
1179 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1180 * appropriate swizzling.
1183 fs_generator::generate_ddx(const fs_inst
*inst
,
1184 struct brw_reg dst
, struct brw_reg src
)
1186 unsigned vstride
, width
;
1188 if (devinfo
->gen
>= 8) {
1189 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1190 /* produce accurate derivatives */
1191 vstride
= BRW_VERTICAL_STRIDE_2
;
1192 width
= BRW_WIDTH_2
;
1194 /* replicate the derivative at the top-left pixel to other pixels */
1195 vstride
= BRW_VERTICAL_STRIDE_4
;
1196 width
= BRW_WIDTH_4
;
1199 struct brw_reg src0
= byte_offset(src
, type_sz(src
.type
));;
1200 struct brw_reg src1
= src
;
1202 src0
.vstride
= vstride
;
1204 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1205 src1
.vstride
= vstride
;
1207 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1209 brw_ADD(p
, dst
, src0
, negate(src1
));
1211 /* On Haswell and earlier, the region used above appears to not work
1212 * correctly for compressed instructions. At least on Haswell and
1213 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1214 * would have to split to SIMD8 no matter which method we choose, we
1215 * may as well use ALIGN16 on all platforms gen7 and earlier.
1217 struct brw_reg src0
= stride(src
, 4, 4, 1);
1218 struct brw_reg src1
= stride(src
, 4, 4, 1);
1219 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1220 src0
.swizzle
= BRW_SWIZZLE_XXZZ
;
1221 src1
.swizzle
= BRW_SWIZZLE_YYWW
;
1223 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1224 src1
.swizzle
= BRW_SWIZZLE_YYYY
;
1227 brw_push_insn_state(p
);
1228 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1229 brw_ADD(p
, dst
, negate(src0
), src1
);
1230 brw_pop_insn_state(p
);
1234 /* The negate_value boolean is used to negate the derivative computation for
1235 * FBOs, since they place the origin at the upper left instead of the lower
1239 fs_generator::generate_ddy(const fs_inst
*inst
,
1240 struct brw_reg dst
, struct brw_reg src
)
1242 const uint32_t type_size
= type_sz(src
.type
);
1244 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1245 /* produce accurate derivatives.
1247 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1248 * "Register Region Restrictions", Section "1. Special Restrictions":
1250 * "In Align16 mode, the channel selects and channel enables apply to
1251 * a pair of half-floats, because these parameters are defined for
1252 * DWord elements ONLY. This is applicable when both source and
1253 * destination are half-floats."
1255 * So for half-float operations we use the Gen11+ Align1 path. CHV
1256 * inherits its FP16 hardware from SKL, so it is not affected.
1258 if (devinfo
->gen
>= 11 ||
1259 (devinfo
->is_broadwell
&& src
.type
== BRW_REGISTER_TYPE_HF
)) {
1260 src
= stride(src
, 0, 2, 1);
1262 brw_push_insn_state(p
);
1263 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1264 for (uint32_t g
= 0; g
< inst
->exec_size
; g
+= 4) {
1265 brw_set_default_group(p
, inst
->group
+ g
);
1266 brw_ADD(p
, byte_offset(dst
, g
* type_size
),
1267 negate(byte_offset(src
, g
* type_size
)),
1268 byte_offset(src
, (g
+ 2) * type_size
));
1270 brw_pop_insn_state(p
);
1272 struct brw_reg src0
= stride(src
, 4, 4, 1);
1273 struct brw_reg src1
= stride(src
, 4, 4, 1);
1274 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1275 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1277 brw_push_insn_state(p
);
1278 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1279 brw_ADD(p
, dst
, negate(src0
), src1
);
1280 brw_pop_insn_state(p
);
1283 /* replicate the derivative at the top-left pixel to other pixels */
1284 if (devinfo
->gen
>= 8) {
1285 struct brw_reg src0
= byte_offset(stride(src
, 4, 4, 0), 0 * type_size
);
1286 struct brw_reg src1
= byte_offset(stride(src
, 4, 4, 0), 2 * type_size
);
1288 brw_ADD(p
, dst
, negate(src0
), src1
);
1290 /* On Haswell and earlier, the region used above appears to not work
1291 * correctly for compressed instructions. At least on Haswell and
1292 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1293 * would have to split to SIMD8 no matter which method we choose, we
1294 * may as well use ALIGN16 on all platforms gen7 and earlier.
1296 struct brw_reg src0
= stride(src
, 4, 4, 1);
1297 struct brw_reg src1
= stride(src
, 4, 4, 1);
1298 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1299 src1
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1301 brw_push_insn_state(p
);
1302 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1303 brw_ADD(p
, dst
, negate(src0
), src1
);
1304 brw_pop_insn_state(p
);
1310 fs_generator::generate_discard_jump(fs_inst
*)
1312 assert(devinfo
->gen
>= 6);
1314 /* This HALT will be patched up at FB write time to point UIP at the end of
1315 * the program, and at brw_uip_jip() JIP will be set to the end of the
1316 * current block (or the program).
1318 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1323 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1325 /* The 32-wide messages only respect the first 16-wide half of the channel
1326 * enable signals which are replicated identically for the second group of
1327 * 16 channels, so we cannot use them unless the write is marked
1328 * force_writemask_all.
1330 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1331 MIN2(16, inst
->exec_size
);
1332 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1333 assert(inst
->mlen
!= 0);
1335 brw_push_insn_state(p
);
1336 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1337 brw_set_default_compression(p
, lower_size
> 8);
1339 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1340 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1342 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1343 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1345 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1347 inst
->offset
+ block_size
* REG_SIZE
* i
);
1350 brw_pop_insn_state(p
);
1354 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1356 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1357 assert(inst
->mlen
!= 0);
1359 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1360 inst
->exec_size
/ 8, inst
->offset
);
1364 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1366 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1368 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1372 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1374 struct brw_reg index
,
1375 struct brw_reg offset
)
1377 assert(type_sz(dst
.type
) == 4);
1378 assert(inst
->mlen
!= 0);
1380 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1381 index
.type
== BRW_REGISTER_TYPE_UD
);
1382 uint32_t surf_index
= index
.ud
;
1384 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1385 offset
.type
== BRW_REGISTER_TYPE_UD
);
1386 uint32_t read_offset
= offset
.ud
;
1388 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1389 read_offset
, surf_index
);
1393 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1395 struct brw_reg index
,
1396 struct brw_reg payload
)
1398 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1399 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1400 assert(type_sz(dst
.type
) == 4);
1402 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1403 const uint32_t surf_index
= index
.ud
;
1405 brw_push_insn_state(p
);
1406 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1407 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1408 brw_pop_insn_state(p
);
1410 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1411 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1412 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1413 brw_set_desc(p
, send
,
1414 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1416 brw_dp_read_desc(devinfo
, surf_index
,
1417 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1418 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1419 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1422 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1424 brw_push_insn_state(p
);
1425 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1427 /* a0.0 = surf_index & 0xff */
1428 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1429 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1430 brw_set_dest(p
, insn_and
, addr
);
1431 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1432 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1434 /* dst = send(payload, a0.0 | <descriptor>) */
1435 brw_send_indirect_message(
1436 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1437 retype(dst
, BRW_REGISTER_TYPE_UD
),
1438 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1439 brw_message_desc(devinfo
, 1,
1440 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1441 brw_dp_read_desc(devinfo
, 0 /* surface */,
1442 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1443 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1444 BRW_DATAPORT_READ_TARGET_DATA_CACHE
),
1447 brw_pop_insn_state(p
);
1452 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1454 struct brw_reg index
)
1456 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1457 assert(inst
->header_size
!= 0);
1460 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1461 index
.type
== BRW_REGISTER_TYPE_UD
);
1462 uint32_t surf_index
= index
.ud
;
1464 uint32_t simd_mode
, rlen
, msg_type
;
1465 if (inst
->exec_size
== 16) {
1466 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1469 assert(inst
->exec_size
== 8);
1470 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1474 if (devinfo
->gen
>= 5)
1475 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1477 /* We always use the SIMD16 message so that we only have to load U, and
1480 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1481 assert(inst
->mlen
== 3);
1482 assert(inst
->size_written
== 8 * REG_SIZE
);
1484 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1487 struct brw_reg header
= brw_vec8_grf(0, 0);
1488 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1490 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1491 brw_inst_set_compression(devinfo
, send
, false);
1492 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1493 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1494 brw_set_src0(p
, send
, header
);
1495 if (devinfo
->gen
< 6)
1496 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1498 /* Our surface is set up as floats, regardless of what actual data is
1501 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1502 brw_set_desc(p
, send
,
1503 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1504 brw_sampler_desc(devinfo
, surf_index
,
1505 0, /* sampler (unused) */
1506 msg_type
, simd_mode
, return_format
));
1510 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1513 struct brw_reg msg_data
,
1516 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1517 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1518 assert(inst
->size_written
% REG_SIZE
== 0);
1520 brw_pixel_interpolator_query(p
,
1521 retype(dst
, BRW_REGISTER_TYPE_UW
),
1522 /* If we don't have a payload, what we send doesn't matter */
1523 has_payload
? src
: brw_vec8_grf(0, 0),
1524 inst
->pi_noperspective
,
1527 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1528 inst
->size_written
/ REG_SIZE
);
1531 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1532 * the ADD instruction.
1535 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1537 struct brw_reg src0
,
1538 struct brw_reg src1
)
1540 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1541 dst
.type
== BRW_REGISTER_TYPE_UD
);
1542 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1543 src0
.type
== BRW_REGISTER_TYPE_UD
);
1545 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1546 const unsigned lower_size
= MIN2(inst
->exec_size
,
1547 devinfo
->gen
>= 8 ? 16 : 8);
1549 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1550 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1551 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1552 (i
* lower_size
/ (1 << src0
.width
))) *
1553 type_sz(src0
.type
) / REG_SIZE
),
1554 suboffset(reg
, i
* lower_size
/ 4));
1555 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1556 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1557 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1562 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1567 assert(devinfo
->gen
>= 7);
1568 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1569 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1570 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1572 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1574 * Because this instruction does not have a 16-bit floating-point type,
1575 * the destination data type must be Word (W).
1577 * The destination must be DWord-aligned and specify a horizontal stride
1578 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1579 * each destination channel and the upper word is not modified.
1581 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1583 /* Give each 32-bit channel of dst the form below, where "." means
1587 brw_F32TO16(p
, dst_w
, y
);
1592 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1594 /* And, finally the form of packHalf2x16's output:
1597 brw_F32TO16(p
, dst_w
, x
);
1601 fs_generator::generate_shader_time_add(fs_inst
*,
1602 struct brw_reg payload
,
1603 struct brw_reg offset
,
1604 struct brw_reg value
)
1606 assert(devinfo
->gen
>= 7);
1607 brw_push_insn_state(p
);
1608 brw_set_default_mask_control(p
, true);
1610 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1611 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1613 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1616 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1617 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1618 value
.width
= BRW_WIDTH_1
;
1619 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1620 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1622 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1625 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1626 * case, and we don't really care about squeezing every bit of performance
1627 * out of this path, so we just emit the MOVs from here.
1629 brw_MOV(p
, payload_offset
, offset
);
1630 brw_MOV(p
, payload_value
, value
);
1631 brw_shader_time_add(p
, payload
,
1632 prog_data
->binding_table
.shader_time_start
);
1633 brw_pop_insn_state(p
);
1637 fs_generator::enable_debug(const char *shader_name
)
1640 this->shader_name
= shader_name
;
1644 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
,
1645 struct brw_compile_stats
*stats
)
1647 /* align to 64 byte boundary. */
1648 while (p
->next_insn_offset
% 64)
1651 this->dispatch_width
= dispatch_width
;
1653 int start_offset
= p
->next_insn_offset
;
1654 int spill_count
= 0, fill_count
= 0;
1657 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1659 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1660 if (inst
->opcode
== SHADER_OPCODE_UNDEF
)
1663 struct brw_reg src
[4], dst
;
1664 unsigned int last_insn_offset
= p
->next_insn_offset
;
1665 bool multiple_instructions_emitted
= false;
1667 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1668 * "Register Region Restrictions" section: for BDW, SKL:
1670 * "A POW/FDIV operation must not be followed by an instruction
1671 * that requires two destination registers."
1673 * The documentation is often lacking annotations for Atom parts,
1674 * and empirically this affects CHV as well.
1676 if (devinfo
->gen
>= 8 &&
1677 devinfo
->gen
<= 9 &&
1679 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1680 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1681 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1683 last_insn_offset
= p
->next_insn_offset
;
1686 if (unlikely(debug_flag
))
1687 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1689 /* If the instruction writes to more than one register, it needs to be
1690 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1691 * hardware figures out by itself what the right compression mode is,
1692 * but we still need to know whether the instruction is compressed to
1693 * set up the source register regions appropriately.
1695 * XXX - This is wrong for instructions that write a single register but
1696 * read more than one which should strictly speaking be treated as
1697 * compressed. For instructions that don't write any registers it
1698 * relies on the destination being a null register of the correct
1699 * type and regioning so the instruction is considered compressed
1700 * or not accordingly.
1702 const bool compressed
=
1703 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1704 brw_set_default_compression(p
, compressed
);
1705 brw_set_default_group(p
, inst
->group
);
1707 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1708 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1709 &inst
->src
[i
], compressed
);
1710 /* The accumulator result appears to get used for the
1711 * conditional modifier generation. When negating a UD
1712 * value, there is a 33rd bit generated for the sign in the
1713 * accumulator value, so now you can't check, for example,
1714 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1716 assert(!inst
->conditional_mod
||
1717 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1718 !inst
->src
[i
].negate
);
1720 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1721 &inst
->dst
, compressed
);
1723 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1724 brw_set_default_predicate_control(p
, inst
->predicate
);
1725 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1726 /* On gen7 and above, hardware automatically adds the group onto the
1727 * flag subregister number. On Sandy Bridge and older, we have to do it
1730 const unsigned flag_subreg
= inst
->flag_subreg
+
1731 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1732 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1733 brw_set_default_saturate(p
, inst
->saturate
);
1734 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1735 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1737 unsigned exec_size
= inst
->exec_size
;
1738 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1739 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1743 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1745 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1746 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1747 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1748 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1750 switch (inst
->opcode
) {
1751 case BRW_OPCODE_MOV
:
1752 brw_MOV(p
, dst
, src
[0]);
1754 case BRW_OPCODE_ADD
:
1755 brw_ADD(p
, dst
, src
[0], src
[1]);
1757 case BRW_OPCODE_MUL
:
1758 brw_MUL(p
, dst
, src
[0], src
[1]);
1760 case BRW_OPCODE_AVG
:
1761 brw_AVG(p
, dst
, src
[0], src
[1]);
1763 case BRW_OPCODE_MACH
:
1764 brw_MACH(p
, dst
, src
[0], src
[1]);
1767 case BRW_OPCODE_LINE
:
1768 brw_LINE(p
, dst
, src
[0], src
[1]);
1771 case BRW_OPCODE_MAD
:
1772 assert(devinfo
->gen
>= 6);
1773 if (devinfo
->gen
< 10)
1774 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1775 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1778 case BRW_OPCODE_LRP
:
1779 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1780 if (devinfo
->gen
< 10)
1781 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1782 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1785 case BRW_OPCODE_FRC
:
1786 brw_FRC(p
, dst
, src
[0]);
1788 case BRW_OPCODE_RNDD
:
1789 brw_RNDD(p
, dst
, src
[0]);
1791 case BRW_OPCODE_RNDE
:
1792 brw_RNDE(p
, dst
, src
[0]);
1794 case BRW_OPCODE_RNDZ
:
1795 brw_RNDZ(p
, dst
, src
[0]);
1798 case BRW_OPCODE_AND
:
1799 brw_AND(p
, dst
, src
[0], src
[1]);
1802 brw_OR(p
, dst
, src
[0], src
[1]);
1804 case BRW_OPCODE_XOR
:
1805 brw_XOR(p
, dst
, src
[0], src
[1]);
1807 case BRW_OPCODE_NOT
:
1808 brw_NOT(p
, dst
, src
[0]);
1810 case BRW_OPCODE_ASR
:
1811 brw_ASR(p
, dst
, src
[0], src
[1]);
1813 case BRW_OPCODE_SHR
:
1814 brw_SHR(p
, dst
, src
[0], src
[1]);
1816 case BRW_OPCODE_SHL
:
1817 brw_SHL(p
, dst
, src
[0], src
[1]);
1819 case BRW_OPCODE_ROL
:
1820 assert(devinfo
->gen
>= 11);
1821 assert(src
[0].type
== dst
.type
);
1822 brw_ROL(p
, dst
, src
[0], src
[1]);
1824 case BRW_OPCODE_ROR
:
1825 assert(devinfo
->gen
>= 11);
1826 assert(src
[0].type
== dst
.type
);
1827 brw_ROR(p
, dst
, src
[0], src
[1]);
1829 case BRW_OPCODE_F32TO16
:
1830 assert(devinfo
->gen
>= 7);
1831 brw_F32TO16(p
, dst
, src
[0]);
1833 case BRW_OPCODE_F16TO32
:
1834 assert(devinfo
->gen
>= 7);
1835 brw_F16TO32(p
, dst
, src
[0]);
1837 case BRW_OPCODE_CMP
:
1838 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1839 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1840 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1841 * implemented in the compiler is not sufficient. Overriding the
1842 * type when the destination is the null register is necessary but
1843 * not sufficient by itself.
1845 assert(dst
.nr
== BRW_ARF_NULL
);
1846 dst
.type
= BRW_REGISTER_TYPE_D
;
1848 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1850 case BRW_OPCODE_SEL
:
1851 brw_SEL(p
, dst
, src
[0], src
[1]);
1853 case BRW_OPCODE_CSEL
:
1854 assert(devinfo
->gen
>= 8);
1855 if (devinfo
->gen
< 10)
1856 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1857 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1859 case BRW_OPCODE_BFREV
:
1860 assert(devinfo
->gen
>= 7);
1861 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1862 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1864 case BRW_OPCODE_FBH
:
1865 assert(devinfo
->gen
>= 7);
1866 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1868 case BRW_OPCODE_FBL
:
1869 assert(devinfo
->gen
>= 7);
1870 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1871 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1873 case BRW_OPCODE_LZD
:
1874 brw_LZD(p
, dst
, src
[0]);
1876 case BRW_OPCODE_CBIT
:
1877 assert(devinfo
->gen
>= 7);
1878 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1879 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1881 case BRW_OPCODE_ADDC
:
1882 assert(devinfo
->gen
>= 7);
1883 brw_ADDC(p
, dst
, src
[0], src
[1]);
1885 case BRW_OPCODE_SUBB
:
1886 assert(devinfo
->gen
>= 7);
1887 brw_SUBB(p
, dst
, src
[0], src
[1]);
1889 case BRW_OPCODE_MAC
:
1890 brw_MAC(p
, dst
, src
[0], src
[1]);
1893 case BRW_OPCODE_BFE
:
1894 assert(devinfo
->gen
>= 7);
1895 if (devinfo
->gen
< 10)
1896 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1897 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1900 case BRW_OPCODE_BFI1
:
1901 assert(devinfo
->gen
>= 7);
1902 brw_BFI1(p
, dst
, src
[0], src
[1]);
1904 case BRW_OPCODE_BFI2
:
1905 assert(devinfo
->gen
>= 7);
1906 if (devinfo
->gen
< 10)
1907 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1908 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1912 if (inst
->src
[0].file
!= BAD_FILE
) {
1913 /* The instruction has an embedded compare (only allowed on gen6) */
1914 assert(devinfo
->gen
== 6);
1915 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1917 brw_IF(p
, brw_get_default_exec_size(p
));
1921 case BRW_OPCODE_ELSE
:
1924 case BRW_OPCODE_ENDIF
:
1929 brw_DO(p
, brw_get_default_exec_size(p
));
1932 case BRW_OPCODE_BREAK
:
1935 case BRW_OPCODE_CONTINUE
:
1939 case BRW_OPCODE_WHILE
:
1944 case SHADER_OPCODE_RCP
:
1945 case SHADER_OPCODE_RSQ
:
1946 case SHADER_OPCODE_SQRT
:
1947 case SHADER_OPCODE_EXP2
:
1948 case SHADER_OPCODE_LOG2
:
1949 case SHADER_OPCODE_SIN
:
1950 case SHADER_OPCODE_COS
:
1951 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1952 if (devinfo
->gen
>= 6) {
1953 assert(inst
->mlen
== 0);
1954 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
1955 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
1956 src
[0], brw_null_reg());
1958 assert(inst
->mlen
>= 1);
1959 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
1961 brw_math_function(inst
->opcode
),
1962 inst
->base_mrf
, src
[0],
1963 BRW_MATH_PRECISION_FULL
);
1966 case SHADER_OPCODE_INT_QUOTIENT
:
1967 case SHADER_OPCODE_INT_REMAINDER
:
1968 case SHADER_OPCODE_POW
:
1969 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1970 if (devinfo
->gen
>= 6) {
1971 assert(inst
->mlen
== 0);
1972 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
1973 inst
->exec_size
== 8);
1974 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1976 assert(inst
->mlen
>= 1);
1977 assert(inst
->exec_size
== 8);
1978 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
1979 inst
->base_mrf
, src
[0],
1980 BRW_MATH_PRECISION_FULL
);
1983 case FS_OPCODE_LINTERP
:
1984 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
1986 case FS_OPCODE_PIXEL_X
:
1987 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1988 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1989 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1991 case FS_OPCODE_PIXEL_Y
:
1992 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1993 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1994 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1997 case SHADER_OPCODE_SEND
:
1998 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
1999 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2002 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2003 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2005 case SHADER_OPCODE_TEX
:
2007 case SHADER_OPCODE_TXD
:
2008 case SHADER_OPCODE_TXF
:
2009 case SHADER_OPCODE_TXF_CMS
:
2010 case SHADER_OPCODE_TXL
:
2011 case SHADER_OPCODE_TXS
:
2012 case SHADER_OPCODE_LOD
:
2013 case SHADER_OPCODE_TG4
:
2014 case SHADER_OPCODE_SAMPLEINFO
:
2015 assert(inst
->src
[0].file
== BAD_FILE
);
2016 generate_tex(inst
, dst
, src
[1], src
[2]);
2019 case FS_OPCODE_DDX_COARSE
:
2020 case FS_OPCODE_DDX_FINE
:
2021 generate_ddx(inst
, dst
, src
[0]);
2023 case FS_OPCODE_DDY_COARSE
:
2024 case FS_OPCODE_DDY_FINE
:
2025 generate_ddy(inst
, dst
, src
[0]);
2028 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2029 generate_scratch_write(inst
, src
[0]);
2033 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2034 generate_scratch_read(inst
, dst
);
2038 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2039 generate_scratch_read_gen7(inst
, dst
);
2043 case SHADER_OPCODE_MOV_INDIRECT
:
2044 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2047 case SHADER_OPCODE_URB_READ_SIMD8
:
2048 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2049 generate_urb_read(inst
, dst
, src
[0]);
2052 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2053 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2054 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2055 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2056 generate_urb_write(inst
, src
[0]);
2059 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2060 assert(inst
->force_writemask_all
);
2061 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2064 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2065 assert(inst
->force_writemask_all
);
2066 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2069 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2070 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2073 case FS_OPCODE_REP_FB_WRITE
:
2074 case FS_OPCODE_FB_WRITE
:
2075 generate_fb_write(inst
, src
[0]);
2078 case FS_OPCODE_FB_READ
:
2079 generate_fb_read(inst
, dst
, src
[0]);
2082 case FS_OPCODE_DISCARD_JUMP
:
2083 generate_discard_jump(inst
);
2086 case SHADER_OPCODE_SHADER_TIME_ADD
:
2087 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2090 case SHADER_OPCODE_MEMORY_FENCE
:
2091 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2092 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2093 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SEND
, src
[1].ud
, src
[2].ud
);
2096 case SHADER_OPCODE_INTERLOCK
:
2097 assert(devinfo
->gen
>= 9);
2098 /* The interlock is basically a memory fence issued via sendc */
2099 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SENDC
, false, /* bti */ 0);
2102 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2103 const struct brw_reg mask
=
2104 brw_stage_has_packed_dispatch(devinfo
, stage
,
2105 prog_data
) ? brw_imm_ud(~0u) :
2106 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2108 brw_find_live_channel(p
, dst
, mask
);
2112 case SHADER_OPCODE_BROADCAST
:
2113 assert(inst
->force_writemask_all
);
2114 brw_broadcast(p
, dst
, src
[0], src
[1]);
2117 case SHADER_OPCODE_SHUFFLE
:
2118 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2121 case SHADER_OPCODE_SEL_EXEC
:
2122 assert(inst
->force_writemask_all
);
2123 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2124 brw_MOV(p
, dst
, src
[1]);
2125 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2126 brw_MOV(p
, dst
, src
[0]);
2129 case SHADER_OPCODE_QUAD_SWIZZLE
:
2130 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2131 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2132 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2135 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2136 assert(src
[0].type
== dst
.type
);
2137 assert(!src
[0].negate
&& !src
[0].abs
);
2138 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2139 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2140 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2141 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2142 const unsigned component
= src
[1].ud
;
2143 const unsigned cluster_size
= src
[2].ud
;
2144 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2145 cluster_size
, cluster_size
, 0);
2146 if (type_sz(src
[0].type
) > 4 &&
2147 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2148 /* IVB has an issue (which we found empirically) where it reads
2149 * two address register components per channel for indirectly
2150 * addressed 64-bit sources.
2152 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2154 * "When source or destination datatype is 64b or operation is
2155 * integer DWord multiply, indirect addressing must not be
2158 * To work around both of these, we do two integer MOVs insead of
2159 * one 64-bit MOV. Because no double value should ever cross a
2160 * register boundary, it's safe to use the immediate offset in the
2161 * indirect here to handle adding 4 bytes to the offset and avoid
2162 * the extra ADD to the register file.
2164 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2165 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2166 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2167 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2169 brw_MOV(p
, dst
, strided
);
2174 case FS_OPCODE_SET_SAMPLE_ID
:
2175 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2178 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2179 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2182 case FS_OPCODE_PLACEHOLDER_HALT
:
2183 /* This is the place where the final HALT needs to be inserted if
2184 * we've emitted any discards. If not, this will emit no code.
2186 if (!patch_discard_jumps_to_fb_writes()) {
2187 if (unlikely(debug_flag
)) {
2188 disasm_info
->use_tail
= true;
2193 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2194 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2195 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2198 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2199 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2200 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2203 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2204 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2205 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2208 case CS_OPCODE_CS_TERMINATE
:
2209 generate_cs_terminate(inst
, src
[0]);
2212 case SHADER_OPCODE_BARRIER
:
2213 generate_barrier(inst
, src
[0]);
2216 case BRW_OPCODE_DIM
:
2217 assert(devinfo
->is_haswell
);
2218 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2219 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2220 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2223 case SHADER_OPCODE_RND_MODE
: {
2224 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2226 * Changes the floating point rounding mode updating the control
2227 * register field defined at cr0.0[5-6] bits.
2229 enum brw_rnd_mode mode
=
2230 (enum brw_rnd_mode
) (src
[0].d
<< BRW_CR0_RND_MODE_SHIFT
);
2231 brw_float_controls_mode(p
, mode
, BRW_CR0_RND_MODE_MASK
);
2235 case SHADER_OPCODE_FLOAT_CONTROL_MODE
:
2236 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2237 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2238 brw_float_controls_mode(p
, src
[0].d
, src
[1].d
);
2242 unreachable("Unsupported opcode");
2244 case SHADER_OPCODE_LOAD_PAYLOAD
:
2245 unreachable("Should be lowered by lower_load_payload()");
2248 if (multiple_instructions_emitted
)
2251 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2252 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2253 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2254 "emitting more than 1 instruction");
2256 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2258 if (inst
->conditional_mod
)
2259 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2260 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2261 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2265 brw_set_uip_jip(p
, start_offset
);
2267 /* end of program sentinel */
2268 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2273 if (unlikely(debug_flag
))
2275 brw_validate_instructions(devinfo
, p
->store
,
2277 p
->next_insn_offset
,
2280 int before_size
= p
->next_insn_offset
- start_offset
;
2281 brw_compact_instructions(p
, start_offset
, disasm_info
);
2282 int after_size
= p
->next_insn_offset
- start_offset
;
2284 if (unlikely(debug_flag
)) {
2285 unsigned char sha1
[21];
2288 _mesa_sha1_compute(p
->store
+ start_offset
/ sizeof(brw_inst
),
2290 _mesa_sha1_format(sha1buf
, sha1
);
2292 fprintf(stderr
, "Native code for %s (sha1 %s)\n"
2293 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2294 "%d:%d spills:fills. "
2295 "scheduled with mode %s. "
2296 "Promoted %u constants. "
2297 "Compacted %d to %d bytes (%.0f%%)\n",
2298 shader_name
, sha1buf
,
2299 dispatch_width
, before_size
/ 16,
2300 loop_count
, cfg
->cycle_count
,
2301 spill_count
, fill_count
,
2302 shader_stats
.scheduler_mode
,
2303 shader_stats
.promoted_constants
,
2304 before_size
, after_size
,
2305 100.0f
* (before_size
- after_size
) / before_size
);
2307 /* overriding the shader makes disasm_info invalid */
2308 if (!brw_try_override_assembly(p
, start_offset
, sha1buf
)) {
2309 dump_assembly(p
->store
, disasm_info
);
2311 fprintf(stderr
, "Successfully overrode shader with sha1 %s\n\n", sha1buf
);
2314 ralloc_free(disasm_info
);
2317 compiler
->shader_debug_log(log_data
,
2318 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2319 "%d:%d spills:fills, "
2320 "scheduled with mode %s, "
2321 "Promoted %u constants, "
2322 "compacted %d to %d bytes.",
2323 _mesa_shader_stage_to_abbrev(stage
),
2324 dispatch_width
, before_size
/ 16,
2325 loop_count
, cfg
->cycle_count
,
2326 spill_count
, fill_count
,
2327 shader_stats
.scheduler_mode
,
2328 shader_stats
.promoted_constants
,
2329 before_size
, after_size
);
2331 stats
->dispatch_width
= dispatch_width
;
2332 stats
->instructions
= before_size
/ 16;
2333 stats
->loops
= loop_count
;
2334 stats
->cycles
= cfg
->cycle_count
;
2335 stats
->spills
= spill_count
;
2336 stats
->fills
= fill_count
;
2339 return start_offset
;
2343 fs_generator::get_assembly()
2345 return brw_get_program(p
, &prog_data
->program_size
);