2 * Copyright © 2010 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "util/mesa-sha1.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
58 fs_reg
*reg
, bool compressed
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
70 /* From the Haswell PRM:
72 * "VertStride must be used to cross GRF register boundaries. This
73 * rule implies that elements within a 'Width' cannot cross GRF
76 * The maximum width value that could satisfy this restriction is:
78 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
80 /* Because the hardware can only split source regions at a whole
81 * multiple of width during decompression (i.e. vertically), clamp
82 * the value obtained above to the physical execution size of a
83 * single decompressed chunk of the instruction:
85 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
88 const unsigned max_hw_width
= 16;
90 /* XXX - The equation above is strictly speaking not correct on
91 * hardware that supports unbalanced GRF writes -- On Gen9+
92 * each decompressed chunk of the instruction may have a
93 * different execution size when the number of components
94 * written to each destination GRF is not the same.
96 if (reg
->stride
> 4) {
97 assert(reg
!= &inst
->dst
);
98 assert(reg
->stride
* type_sz(reg
->type
) <= REG_SIZE
);
99 brw_reg
= brw_vecn_reg(1, brw_file_from_reg(reg
), reg
->nr
, 0);
100 brw_reg
= stride(brw_reg
, reg
->stride
, 1, 0);
102 const unsigned width
= MIN3(reg_width
, phys_width
, max_hw_width
);
103 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
104 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
107 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
108 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
109 * "Each DF (Double Float) operand uses an element size of 4 rather
110 * than 8 and all regioning parameters are twice what the values
111 * would be based on the true element size: ExecSize, Width,
112 * HorzStride, and VertStride. Each DF operand uses a pair of
113 * channels and all masking and swizzing should be adjusted
116 * From the IvyBridge PRM (Special Requirements for Handling Double
117 * Precision Data Types, page 71):
118 * "In Align1 mode, all regioning parameters like stride, execution
119 * size, and width must use the syntax of a pair of packed
120 * floats. The offsets for these data types must be 64-bit
121 * aligned. The execution size and regioning parameters are in terms
124 * Summarized: when handling DF-typed arguments, ExecSize,
125 * VertStride, and Width must be doubled.
127 * It applies to BayTrail too.
129 if (type_sz(reg
->type
) == 8) {
131 if (brw_reg
.vstride
> 0)
133 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
136 /* When converting from DF->F, we set the destination stride to 2
137 * because each d2f conversion implicitly writes 2 floats, being
138 * the first one the converted value. IVB/BYT actually writes two
139 * F components per SIMD channel, and every other component is
140 * filled with garbage.
142 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
143 type_sz(inst
->dst
.type
) < 8) {
144 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
150 brw_reg
= retype(brw_reg
, reg
->type
);
151 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
152 brw_reg
.abs
= reg
->abs
;
153 brw_reg
.negate
= reg
->negate
;
158 assert(reg
->offset
== 0);
159 brw_reg
= reg
->as_brw_reg();
162 /* Probably unused. */
163 brw_reg
= brw_null_reg();
167 unreachable("not reached");
170 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
171 * region, but on IVB and BYT DF regions must be programmed in terms of
172 * floats. A <0,2,1> region accomplishes this.
174 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
175 type_sz(reg
->type
) == 8 &&
176 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
177 brw_reg
.width
== BRW_WIDTH_1
&&
178 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
179 brw_reg
.width
= BRW_WIDTH_2
;
180 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
186 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
188 struct brw_stage_prog_data
*prog_data
,
189 struct shader_stats shader_stats
,
190 bool runtime_check_aads_emit
,
191 gl_shader_stage stage
)
193 : compiler(compiler
), log_data(log_data
),
194 devinfo(compiler
->devinfo
),
195 prog_data(prog_data
),
196 shader_stats(shader_stats
),
197 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
198 stage(stage
), mem_ctx(mem_ctx
)
200 p
= rzalloc(mem_ctx
, struct brw_codegen
);
201 brw_init_codegen(devinfo
, p
, mem_ctx
);
203 /* In the FS code generator, we are very careful to ensure that we always
204 * set the right execution size so we don't need the EU code to "help" us
205 * by trying to infer it. Sometimes, it infers the wrong thing.
207 p
->automatic_exec_sizes
= false;
210 fs_generator::~fs_generator()
214 class ip_record
: public exec_node
{
216 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
227 fs_generator::patch_discard_jumps_to_fb_writes()
229 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
232 int scale
= brw_jump_scale(p
->devinfo
);
234 /* There is a somewhat strange undocumented requirement of using
235 * HALT, according to the simulator. If some channel has HALTed to
236 * a particular UIP, then by the end of the program, every channel
237 * must have HALTed to that UIP. Furthermore, the tracking is a
238 * stack, so you can't do the final halt of a UIP after starting
239 * halting to a new UIP.
241 * Symptoms of not emitting this instruction on actual hardware
242 * included GPU hangs and sparkly rendering on the piglit discard
245 brw_inst
*last_halt
= gen6_HALT(p
);
246 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
247 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
251 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
252 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
254 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
255 /* HALT takes a half-instruction distance from the pre-incremented IP. */
256 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
259 this->discard_halt_patches
.make_empty();
264 fs_generator::generate_send(fs_inst
*inst
,
267 struct brw_reg ex_desc
,
268 struct brw_reg payload
,
269 struct brw_reg payload2
)
271 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
272 dst
.nr
== BRW_ARF_NULL
;
273 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
275 uint32_t desc_imm
= inst
->desc
|
276 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
278 uint32_t ex_desc_imm
= brw_message_ex_desc(devinfo
, inst
->ex_mlen
);
280 if (ex_desc
.file
!= BRW_IMMEDIATE_VALUE
|| ex_desc
.ud
|| ex_desc_imm
) {
281 /* If we have any sort of extended descriptor, then we need SENDS. This
282 * also covers the dual-payload case because ex_mlen goes in ex_desc.
284 brw_send_indirect_split_message(p
, inst
->sfid
, dst
, payload
, payload2
,
285 desc
, desc_imm
, ex_desc
, ex_desc_imm
,
288 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
,
289 devinfo
->gen
>= 12 ? BRW_OPCODE_SENDC
: BRW_OPCODE_SENDSC
);
291 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
,
294 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
299 fs_generator::fire_fb_write(fs_inst
*inst
,
300 struct brw_reg payload
,
301 struct brw_reg implied_header
,
304 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
306 if (devinfo
->gen
< 6) {
307 brw_push_insn_state(p
);
308 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
309 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
310 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
311 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
312 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
313 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
314 brw_pop_insn_state(p
);
317 uint32_t msg_control
= brw_fb_write_msg_control(inst
, prog_data
);
319 /* We assume render targets start at 0, because headerless FB write
320 * messages set "Render Target Index" to 0. Using a different binding
321 * table index would make it impossible to use headerless messages.
323 const uint32_t surf_index
= inst
->target
;
325 brw_inst
*insn
= brw_fb_WRITE(p
,
327 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
334 inst
->header_size
!= 0);
336 if (devinfo
->gen
>= 6)
337 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
341 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
343 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
344 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
345 brw_set_default_flag_reg(p
, 0, 0);
348 const struct brw_reg implied_header
=
349 devinfo
->gen
< 6 ? payload
: brw_null_reg();
351 if (inst
->base_mrf
>= 0)
352 payload
= brw_message_reg(inst
->base_mrf
);
354 if (!runtime_check_aads_emit
) {
355 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
357 /* This can only happen in gen < 6 */
358 assert(devinfo
->gen
< 6);
360 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
362 /* Check runtime bit to detect if we have to send AA data or not */
363 brw_push_insn_state(p
);
364 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
365 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
368 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
370 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
372 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
373 brw_pop_insn_state(p
);
375 /* Don't send AA data */
376 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
378 brw_land_fwd_jump(p
, jmp
);
379 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
384 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
385 struct brw_reg payload
)
387 assert(inst
->size_written
% REG_SIZE
== 0);
388 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
389 /* We assume that render targets start at binding table index 0. */
390 const unsigned surf_index
= inst
->target
;
392 gen9_fb_READ(p
, dst
, payload
, surf_index
,
393 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
394 prog_data
->persample_dispatch
);
398 fs_generator::generate_mov_indirect(fs_inst
*inst
,
401 struct brw_reg indirect_byte_offset
)
403 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
404 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
405 assert(!reg
.abs
&& !reg
.negate
);
406 assert(reg
.type
== dst
.type
);
408 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
410 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
411 imm_byte_offset
+= indirect_byte_offset
.ud
;
413 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
414 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
415 brw_MOV(p
, dst
, reg
);
417 /* Prior to Broadwell, there are only 8 address registers. */
418 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
420 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
421 struct brw_reg addr
= vec8(brw_address_reg(0));
423 /* The destination stride of an instruction (in bytes) must be greater
424 * than or equal to the size of the rest of the instruction. Since the
425 * address register is of type UW, we can't use a D-type instruction.
426 * In order to get around this, re retype to UW and use a stride.
428 indirect_byte_offset
=
429 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
431 /* There are a number of reasons why we don't use the base offset here.
432 * One reason is that the field is only 9 bits which means we can only
433 * use it to access the first 16 GRFs. Also, from the Haswell PRM
434 * section "Register Region Restrictions":
436 * "The lower bits of the AddressImmediate must not overflow to
437 * change the register address. The lower 5 bits of Address
438 * Immediate when added to lower 5 bits of address register gives
439 * the sub-register offset. The upper bits of Address Immediate
440 * when added to upper bits of address register gives the register
441 * address. Any overflow from sub-register offset is dropped."
443 * Since the indirect may cause us to cross a register boundary, this
444 * makes the base offset almost useless. We could try and do something
445 * clever where we use a actual base offset if base_offset % 32 == 0 but
446 * that would mean we were generating different code depending on the
447 * base offset. Instead, for the sake of consistency, we'll just do the
448 * add ourselves. This restriction is only listed in the Haswell PRM
449 * but empirical testing indicates that it applies on all older
450 * generations and is lifted on Broadwell.
452 * In the end, while base_offset is nice to look at in the generated
453 * code, using it saves us 0 instructions and would require quite a bit
454 * of case-by-case work. It's just not worth it.
456 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
457 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
459 if (type_sz(reg
.type
) > 4 &&
460 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
461 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
462 !devinfo
->has_64bit_types
)) {
463 /* IVB has an issue (which we found empirically) where it reads two
464 * address register components per channel for indirectly addressed
467 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
469 * "When source or destination datatype is 64b or operation is
470 * integer DWord multiply, indirect addressing must not be used."
472 * To work around both of these, we do two integer MOVs insead of one
473 * 64-bit MOV. Because no double value should ever cross a register
474 * boundary, it's safe to use the immediate offset in the indirect
475 * here to handle adding 4 bytes to the offset and avoid the extra
476 * ADD to the register file.
478 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
479 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
480 brw_set_default_swsb(p
, tgl_swsb_null());
481 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
482 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
484 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
486 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
488 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
489 !inst
->get_next()->is_tail_sentinel() &&
490 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
491 /* From the Sandybridge PRM:
493 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
494 * instruction that “indexed/indirect” source AND is followed
495 * by a send, the instruction requires a “Switch”. This is to
496 * avoid race condition where send may dispatch before MRF is
499 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
506 fs_generator::generate_shuffle(fs_inst
*inst
,
511 /* Ivy bridge has some strange behavior that makes this a real pain to
512 * implement for 64-bit values so we just don't bother.
514 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
516 /* Because we're using the address register, we're limited to 8-wide
517 * execution on gen7. On gen8, we're limited to 16-wide by the address
518 * register file and 8-wide for 64-bit types. We could try and make this
519 * instruction splittable higher up in the compiler but that gets weird
520 * because it reads all of the channels regardless of execution size. It's
521 * easier just to split it here.
523 const unsigned lower_width
=
524 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
525 8 : MIN2(16, inst
->exec_size
);
527 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
528 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
529 brw_set_default_group(p
, group
);
531 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
532 idx
.file
== BRW_IMMEDIATE_VALUE
) {
533 /* Trivial, the source is already uniform or the index is a constant.
534 * We will typically not get here if the optimizer is doing its job,
535 * but asserting would be mean.
537 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
538 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
540 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
541 struct brw_reg addr
= vec8(brw_address_reg(0));
543 struct brw_reg group_idx
= suboffset(idx
, group
);
545 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
546 /* Things get grumpy if the register is too wide. */
551 assert(type_sz(group_idx
.type
) <= 4);
552 if (type_sz(group_idx
.type
) == 4) {
553 /* The destination stride of an instruction (in bytes) must be
554 * greater than or equal to the size of the rest of the
555 * instruction. Since the address register is of type UW, we
556 * can't use a D-type instruction. In order to get around this,
557 * re retype to UW and use a stride.
559 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
562 /* Take into account the component size and horizontal stride. */
563 assert(src
.vstride
== src
.hstride
+ src
.width
);
564 brw_SHL(p
, addr
, group_idx
,
565 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
568 /* Add on the register start offset */
569 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
570 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
572 if (type_sz(src
.type
) > 4 &&
573 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
574 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
575 /* IVB has an issue (which we found empirically) where it reads
576 * two address register components per channel for indirectly
577 * addressed 64-bit sources.
579 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
581 * "When source or destination datatype is 64b or operation is
582 * integer DWord multiply, indirect addressing must not be
585 * To work around both of these, we do two integer MOVs insead of
586 * one 64-bit MOV. Because no double value should ever cross a
587 * register boundary, it's safe to use the immediate offset in the
588 * indirect here to handle adding 4 bytes to the offset and avoid
589 * the extra ADD to the register file.
591 struct brw_reg gdst
= suboffset(dst
, group
);
592 struct brw_reg dst_d
= retype(spread(gdst
, 2),
593 BRW_REGISTER_TYPE_D
);
594 assert(dst
.hstride
== 1);
596 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
597 brw_set_default_swsb(p
, tgl_swsb_null());
598 brw_MOV(p
, byte_offset(dst_d
, 4),
599 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
601 brw_MOV(p
, suboffset(dst
, group
* dst
.hstride
),
602 retype(brw_VxH_indirect(0, 0), src
.type
));
606 brw_set_default_swsb(p
, tgl_swsb_null());
611 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
612 struct brw_reg dst
, struct brw_reg src
,
615 /* Requires a quad. */
616 assert(inst
->exec_size
>= 4);
618 if (src
.file
== BRW_IMMEDIATE_VALUE
||
619 has_scalar_region(src
)) {
620 /* The value is uniform across all channels */
621 brw_MOV(p
, dst
, src
);
623 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
624 /* This only works on 8-wide 32-bit values */
625 assert(inst
->exec_size
== 8);
626 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
627 assert(src
.vstride
== src
.width
+ 1);
628 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
629 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
630 swiz_src
.swizzle
= swiz
;
631 brw_MOV(p
, dst
, swiz_src
);
634 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
635 assert(src
.vstride
== src
.width
+ 1);
636 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
639 case BRW_SWIZZLE_XXXX
:
640 case BRW_SWIZZLE_YYYY
:
641 case BRW_SWIZZLE_ZZZZ
:
642 case BRW_SWIZZLE_WWWW
:
643 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
646 case BRW_SWIZZLE_XXZZ
:
647 case BRW_SWIZZLE_YYWW
:
648 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
651 case BRW_SWIZZLE_XYXY
:
652 case BRW_SWIZZLE_ZWZW
:
653 assert(inst
->exec_size
== 4);
654 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
658 assert(inst
->force_writemask_all
);
659 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
661 for (unsigned c
= 0; c
< 4; c
++) {
662 brw_inst
*insn
= brw_MOV(
663 p
, stride(suboffset(dst
, c
),
664 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
665 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
667 if (devinfo
->gen
< 12) {
668 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
669 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
672 brw_set_default_swsb(p
, tgl_swsb_null());
681 fs_generator::generate_urb_read(fs_inst
*inst
,
683 struct brw_reg header
)
685 assert(inst
->size_written
% REG_SIZE
== 0);
686 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
687 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
689 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
690 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
691 brw_set_src0(p
, send
, header
);
692 if (devinfo
->gen
< 12)
693 brw_set_src1(p
, send
, brw_imm_ud(0u));
695 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
696 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
698 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
699 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
701 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
702 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
703 brw_inst_set_header_present(p
->devinfo
, send
, true);
704 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
708 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
712 /* WaClearTDRRegBeforeEOTForNonPS.
714 * WA: Clear tdr register before send EOT in all non-PS shader kernels
716 * mov(8) tdr0:ud 0x0:ud {NoMask}"
718 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
719 brw_push_insn_state(p
);
720 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
721 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
722 brw_pop_insn_state(p
);
725 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
727 brw_set_dest(p
, insn
, brw_null_reg());
728 brw_set_src0(p
, insn
, payload
);
729 if (devinfo
->gen
< 12)
730 brw_set_src1(p
, insn
, brw_imm_ud(0u));
732 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
733 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
735 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
736 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
737 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
739 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
740 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
741 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
743 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
744 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
745 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
746 brw_inst_set_header_present(p
->devinfo
, insn
, true);
747 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
751 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
753 struct brw_inst
*insn
;
755 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
757 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
758 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
759 if (devinfo
->gen
< 12)
760 brw_set_src1(p
, insn
, brw_imm_ud(0u));
762 /* Terminate a compute shader by sending a message to the thread spawner.
764 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
765 brw_inst_set_mlen(devinfo
, insn
, 1);
766 brw_inst_set_rlen(devinfo
, insn
, 0);
767 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
768 brw_inst_set_header_present(devinfo
, insn
, false);
770 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
772 if (devinfo
->gen
< 11) {
773 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
775 /* Note that even though the thread has a URB resource associated with it,
776 * we set the "do not dereference URB" bit, because the URB resource is
777 * managed by the fixed-function unit, so it will free it automatically.
779 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
782 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
786 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
789 if (devinfo
->gen
>= 12) {
790 brw_set_default_swsb(p
, tgl_swsb_null());
791 brw_SYNC(p
, TGL_SYNC_BAR
);
798 fs_generator::generate_linterp(fs_inst
*inst
,
799 struct brw_reg dst
, struct brw_reg
*src
)
803 * -----------------------------------
804 * | src1+0 | src1+1 | src1+2 | src1+3 |
805 * |-----------------------------------|
806 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
807 * -----------------------------------
809 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
811 * -----------------------------------
812 * | src1+0 | src1+1 | src1+2 | src1+3 |
813 * |-----------------------------------|
814 * |(x0, x1)|(y0, y1)| | | in SIMD8
815 * |-----------------------------------|
816 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
817 * -----------------------------------
819 * See also: emit_interpolation_setup_gen4().
821 struct brw_reg delta_x
= src
[0];
822 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
823 struct brw_reg interp
= src
[1];
826 /* nir_lower_interpolation() will do the lowering to MAD instructions for
829 assert(devinfo
->gen
< 11);
831 if (devinfo
->has_pln
) {
832 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
833 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
835 * "[DevSNB]:<src1> must be even register aligned.
837 * This restriction is lifted on Ivy Bridge.
839 * This means that we need to split PLN into LINE+MAC on-the-fly.
840 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
841 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
842 * coordinate registers are laid out differently so we leave it as a
843 * SIMD16 instruction.
845 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
846 assert(inst
->group
% 16 == 0);
848 brw_push_insn_state(p
);
849 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
851 /* Thanks to two accumulators, we can emit all the LINEs and then all
852 * the MACs. This improves parallelism a bit.
854 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
855 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
856 offset(delta_x
, g
* 2));
857 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
859 /* LINE writes the accumulator automatically on gen4-5. On Sandy
860 * Bridge and later, we have to explicitly enable it.
862 if (devinfo
->gen
>= 6)
863 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
865 /* brw_set_default_saturate() is called before emitting
866 * instructions, so the saturate bit is set in each instruction,
867 * so we need to unset it on the LINE instructions.
869 brw_inst_set_saturate(p
->devinfo
, line
, false);
872 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
873 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
874 offset(delta_x
, g
* 2 + 1));
875 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
876 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
879 brw_pop_insn_state(p
);
883 brw_PLN(p
, dst
, interp
, delta_x
);
888 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
889 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
891 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
893 /* brw_set_default_saturate() is called before emitting instructions, so
894 * the saturate bit is set in each instruction, so we need to unset it on
895 * the first instruction.
897 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
904 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
907 struct brw_reg surf_index
)
909 assert(devinfo
->gen
>= 7);
910 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
915 switch (inst
->exec_size
) {
917 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
920 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
923 unreachable("Invalid width for texture instruction");
926 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
932 retype(dst
, BRW_REGISTER_TYPE_UW
),
937 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
938 rlen
, /* response length */
940 inst
->header_size
> 0,
942 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
946 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
947 struct brw_reg surface_index
,
948 struct brw_reg sampler_index
)
950 assert(devinfo
->gen
< 7);
951 assert(inst
->size_written
% REG_SIZE
== 0);
954 uint32_t return_format
;
956 /* Sampler EOT message of less than the dispatch width would kill the
957 * thread prematurely.
959 assert(!inst
->eot
|| inst
->exec_size
== dispatch_width
);
962 case BRW_REGISTER_TYPE_D
:
963 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
965 case BRW_REGISTER_TYPE_UD
:
966 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
969 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
973 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
974 * is set as part of the message descriptor. On gen4, the PRM seems to
975 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
976 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
977 * gone from the message descriptor entirely and you just get UINT32 all
978 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
979 * just stomp it to UINT32 all the time.
981 if (inst
->opcode
== SHADER_OPCODE_TXS
)
982 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
984 switch (inst
->exec_size
) {
986 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
989 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
992 unreachable("Invalid width for texture instruction");
995 if (devinfo
->gen
>= 5) {
996 switch (inst
->opcode
) {
997 case SHADER_OPCODE_TEX
:
998 if (inst
->shadow_compare
) {
999 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
1001 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
1005 if (inst
->shadow_compare
) {
1006 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
1008 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
1011 case SHADER_OPCODE_TXL
:
1012 if (inst
->shadow_compare
) {
1013 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
1015 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
1018 case SHADER_OPCODE_TXS
:
1019 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
1021 case SHADER_OPCODE_TXD
:
1022 assert(!inst
->shadow_compare
);
1023 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1025 case SHADER_OPCODE_TXF
:
1026 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1028 case SHADER_OPCODE_TXF_CMS
:
1029 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1031 case SHADER_OPCODE_LOD
:
1032 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1034 case SHADER_OPCODE_TG4
:
1035 assert(devinfo
->gen
== 6);
1036 assert(!inst
->shadow_compare
);
1037 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1039 case SHADER_OPCODE_SAMPLEINFO
:
1040 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1043 unreachable("not reached");
1046 switch (inst
->opcode
) {
1047 case SHADER_OPCODE_TEX
:
1048 /* Note that G45 and older determines shadow compare and dispatch width
1049 * from message length for most messages.
1051 if (inst
->exec_size
== 8) {
1052 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1053 if (inst
->shadow_compare
) {
1054 assert(inst
->mlen
== 6);
1056 assert(inst
->mlen
<= 4);
1059 if (inst
->shadow_compare
) {
1060 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1061 assert(inst
->mlen
== 9);
1063 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1064 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1069 if (inst
->shadow_compare
) {
1070 assert(inst
->exec_size
== 8);
1071 assert(inst
->mlen
== 6);
1072 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1074 assert(inst
->mlen
== 9);
1075 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1076 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1079 case SHADER_OPCODE_TXL
:
1080 if (inst
->shadow_compare
) {
1081 assert(inst
->exec_size
== 8);
1082 assert(inst
->mlen
== 6);
1083 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1085 assert(inst
->mlen
== 9);
1086 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1087 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1090 case SHADER_OPCODE_TXD
:
1091 /* There is no sample_d_c message; comparisons are done manually */
1092 assert(inst
->exec_size
== 8);
1093 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1094 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1096 case SHADER_OPCODE_TXF
:
1097 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1098 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1099 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1101 case SHADER_OPCODE_TXS
:
1102 assert(inst
->mlen
== 3);
1103 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1104 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1107 unreachable("not reached");
1110 assert(msg_type
!= -1);
1112 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1116 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1118 /* Load the message header if present. If there's a texture offset,
1119 * we need to set it up explicitly and load the offset bitfield.
1120 * Otherwise, we can use an implied move from g0 to the first message reg.
1122 struct brw_reg src
= brw_null_reg();
1123 if (inst
->header_size
!= 0) {
1124 if (devinfo
->gen
< 6 && !inst
->offset
) {
1125 /* Set up an implied move from g0 to the MRF. */
1126 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1128 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1129 assert(inst
->base_mrf
!= -1);
1130 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1132 brw_push_insn_state(p
);
1133 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1134 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1135 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1136 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1137 /* Explicitly set up the message header by copying g0 to the MRF. */
1138 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1139 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
1141 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1143 /* Set the offset bits in DWord 2. */
1144 brw_MOV(p
, get_element_ud(header_reg
, 2),
1145 brw_imm_ud(inst
->offset
));
1148 brw_pop_insn_state(p
);
1149 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1153 uint32_t base_binding_table_index
;
1154 switch (inst
->opcode
) {
1155 case SHADER_OPCODE_TG4
:
1156 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1159 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1163 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1164 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1167 retype(dst
, BRW_REGISTER_TYPE_UW
),
1170 surface_index
.ud
+ base_binding_table_index
,
1171 sampler_index
.ud
% 16,
1173 inst
->size_written
/ REG_SIZE
,
1175 inst
->header_size
!= 0,
1181 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1184 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1186 * Ideally, we want to produce:
1189 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1190 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1191 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1192 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1193 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1194 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1195 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1196 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1198 * and add another set of two more subspans if in 16-pixel dispatch mode.
1200 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1201 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1202 * pair. But the ideal approximation may impose a huge performance cost on
1203 * sample_d. On at least Haswell, sample_d instruction does some
1204 * optimizations if the same LOD is used for all pixels in the subspan.
1206 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1207 * appropriate swizzling.
1210 fs_generator::generate_ddx(const fs_inst
*inst
,
1211 struct brw_reg dst
, struct brw_reg src
)
1213 unsigned vstride
, width
;
1215 if (devinfo
->gen
>= 8) {
1216 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1217 /* produce accurate derivatives */
1218 vstride
= BRW_VERTICAL_STRIDE_2
;
1219 width
= BRW_WIDTH_2
;
1221 /* replicate the derivative at the top-left pixel to other pixels */
1222 vstride
= BRW_VERTICAL_STRIDE_4
;
1223 width
= BRW_WIDTH_4
;
1226 struct brw_reg src0
= byte_offset(src
, type_sz(src
.type
));;
1227 struct brw_reg src1
= src
;
1229 src0
.vstride
= vstride
;
1231 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1232 src1
.vstride
= vstride
;
1234 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1236 brw_ADD(p
, dst
, src0
, negate(src1
));
1238 /* On Haswell and earlier, the region used above appears to not work
1239 * correctly for compressed instructions. At least on Haswell and
1240 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1241 * would have to split to SIMD8 no matter which method we choose, we
1242 * may as well use ALIGN16 on all platforms gen7 and earlier.
1244 struct brw_reg src0
= stride(src
, 4, 4, 1);
1245 struct brw_reg src1
= stride(src
, 4, 4, 1);
1246 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1247 src0
.swizzle
= BRW_SWIZZLE_XXZZ
;
1248 src1
.swizzle
= BRW_SWIZZLE_YYWW
;
1250 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1251 src1
.swizzle
= BRW_SWIZZLE_YYYY
;
1254 brw_push_insn_state(p
);
1255 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1256 brw_ADD(p
, dst
, negate(src0
), src1
);
1257 brw_pop_insn_state(p
);
1261 /* The negate_value boolean is used to negate the derivative computation for
1262 * FBOs, since they place the origin at the upper left instead of the lower
1266 fs_generator::generate_ddy(const fs_inst
*inst
,
1267 struct brw_reg dst
, struct brw_reg src
)
1269 const uint32_t type_size
= type_sz(src
.type
);
1271 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1272 /* produce accurate derivatives.
1274 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1275 * "Register Region Restrictions", Section "1. Special Restrictions":
1277 * "In Align16 mode, the channel selects and channel enables apply to
1278 * a pair of half-floats, because these parameters are defined for
1279 * DWord elements ONLY. This is applicable when both source and
1280 * destination are half-floats."
1282 * So for half-float operations we use the Gen11+ Align1 path. CHV
1283 * inherits its FP16 hardware from SKL, so it is not affected.
1285 if (devinfo
->gen
>= 11 ||
1286 (devinfo
->is_broadwell
&& src
.type
== BRW_REGISTER_TYPE_HF
)) {
1287 src
= stride(src
, 0, 2, 1);
1289 brw_push_insn_state(p
);
1290 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1291 for (uint32_t g
= 0; g
< inst
->exec_size
; g
+= 4) {
1292 brw_set_default_group(p
, inst
->group
+ g
);
1293 brw_ADD(p
, byte_offset(dst
, g
* type_size
),
1294 negate(byte_offset(src
, g
* type_size
)),
1295 byte_offset(src
, (g
+ 2) * type_size
));
1296 brw_set_default_swsb(p
, tgl_swsb_null());
1298 brw_pop_insn_state(p
);
1300 struct brw_reg src0
= stride(src
, 4, 4, 1);
1301 struct brw_reg src1
= stride(src
, 4, 4, 1);
1302 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1303 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1305 brw_push_insn_state(p
);
1306 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1307 brw_ADD(p
, dst
, negate(src0
), src1
);
1308 brw_pop_insn_state(p
);
1311 /* replicate the derivative at the top-left pixel to other pixels */
1312 if (devinfo
->gen
>= 8) {
1313 struct brw_reg src0
= byte_offset(stride(src
, 4, 4, 0), 0 * type_size
);
1314 struct brw_reg src1
= byte_offset(stride(src
, 4, 4, 0), 2 * type_size
);
1316 brw_ADD(p
, dst
, negate(src0
), src1
);
1318 /* On Haswell and earlier, the region used above appears to not work
1319 * correctly for compressed instructions. At least on Haswell and
1320 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1321 * would have to split to SIMD8 no matter which method we choose, we
1322 * may as well use ALIGN16 on all platforms gen7 and earlier.
1324 struct brw_reg src0
= stride(src
, 4, 4, 1);
1325 struct brw_reg src1
= stride(src
, 4, 4, 1);
1326 src0
.swizzle
= BRW_SWIZZLE_XXXX
;
1327 src1
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1329 brw_push_insn_state(p
);
1330 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1331 brw_ADD(p
, dst
, negate(src0
), src1
);
1332 brw_pop_insn_state(p
);
1338 fs_generator::generate_discard_jump(fs_inst
*)
1340 assert(devinfo
->gen
>= 6);
1342 /* This HALT will be patched up at FB write time to point UIP at the end of
1343 * the program, and at brw_uip_jip() JIP will be set to the end of the
1344 * current block (or the program).
1346 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1351 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1353 /* The 32-wide messages only respect the first 16-wide half of the channel
1354 * enable signals which are replicated identically for the second group of
1355 * 16 channels, so we cannot use them unless the write is marked
1356 * force_writemask_all.
1358 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1359 MIN2(16, inst
->exec_size
);
1360 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1361 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1362 assert(inst
->mlen
!= 0);
1364 brw_push_insn_state(p
);
1365 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1366 brw_set_default_compression(p
, lower_size
> 8);
1368 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1369 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1372 brw_set_default_swsb(p
, tgl_swsb_null());
1373 brw_SYNC(p
, TGL_SYNC_ALLRD
);
1375 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1378 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1379 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1381 if (i
+ 1 < inst
->exec_size
/ lower_size
)
1382 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
1384 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1386 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1388 inst
->offset
+ block_size
* REG_SIZE
* i
);
1391 brw_pop_insn_state(p
);
1395 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1397 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1398 assert(inst
->mlen
!= 0);
1400 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1401 inst
->exec_size
/ 8, inst
->offset
);
1405 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1407 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1409 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1413 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1415 struct brw_reg index
,
1416 struct brw_reg offset
)
1418 assert(type_sz(dst
.type
) == 4);
1419 assert(inst
->mlen
!= 0);
1421 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1422 index
.type
== BRW_REGISTER_TYPE_UD
);
1423 uint32_t surf_index
= index
.ud
;
1425 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1426 offset
.type
== BRW_REGISTER_TYPE_UD
);
1427 uint32_t read_offset
= offset
.ud
;
1429 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1430 read_offset
, surf_index
);
1434 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1436 struct brw_reg index
,
1437 struct brw_reg payload
)
1439 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1440 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1441 assert(type_sz(dst
.type
) == 4);
1443 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1444 const uint32_t surf_index
= index
.ud
;
1446 brw_push_insn_state(p
);
1447 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1448 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1449 brw_pop_insn_state(p
);
1451 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1452 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1453 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1454 brw_set_desc(p
, send
,
1455 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1457 brw_dp_read_desc(devinfo
, surf_index
,
1458 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1459 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1460 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1463 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1464 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1466 brw_push_insn_state(p
);
1467 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1469 /* a0.0 = surf_index & 0xff */
1470 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1471 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1472 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1473 brw_set_dest(p
, insn_and
, addr
);
1474 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1475 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1477 /* dst = send(payload, a0.0 | <descriptor>) */
1478 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1479 brw_send_indirect_message(
1480 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1481 retype(dst
, BRW_REGISTER_TYPE_UD
),
1482 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1483 brw_message_desc(devinfo
, 1,
1484 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1485 brw_dp_read_desc(devinfo
, 0 /* surface */,
1486 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1487 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1488 BRW_DATAPORT_READ_TARGET_DATA_CACHE
),
1491 brw_pop_insn_state(p
);
1496 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1498 struct brw_reg index
)
1500 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1501 assert(inst
->header_size
!= 0);
1504 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1505 index
.type
== BRW_REGISTER_TYPE_UD
);
1506 uint32_t surf_index
= index
.ud
;
1508 uint32_t simd_mode
, rlen
, msg_type
;
1509 if (inst
->exec_size
== 16) {
1510 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1513 assert(inst
->exec_size
== 8);
1514 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1518 if (devinfo
->gen
>= 5)
1519 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1521 /* We always use the SIMD16 message so that we only have to load U, and
1524 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1525 assert(inst
->mlen
== 3);
1526 assert(inst
->size_written
== 8 * REG_SIZE
);
1528 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1531 struct brw_reg header
= brw_vec8_grf(0, 0);
1532 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1534 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1535 brw_inst_set_compression(devinfo
, send
, false);
1536 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1537 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1538 brw_set_src0(p
, send
, header
);
1539 if (devinfo
->gen
< 6)
1540 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1542 /* Our surface is set up as floats, regardless of what actual data is
1545 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1546 brw_set_desc(p
, send
,
1547 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1548 brw_sampler_desc(devinfo
, surf_index
,
1549 0, /* sampler (unused) */
1550 msg_type
, simd_mode
, return_format
));
1554 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1557 struct brw_reg msg_data
,
1560 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1561 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1562 assert(inst
->size_written
% REG_SIZE
== 0);
1564 brw_pixel_interpolator_query(p
,
1565 retype(dst
, BRW_REGISTER_TYPE_UW
),
1566 /* If we don't have a payload, what we send doesn't matter */
1567 has_payload
? src
: brw_vec8_grf(0, 0),
1568 inst
->pi_noperspective
,
1571 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1572 inst
->size_written
/ REG_SIZE
);
1575 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1576 * the ADD instruction.
1579 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1581 struct brw_reg src0
,
1582 struct brw_reg src1
)
1584 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1585 dst
.type
== BRW_REGISTER_TYPE_UD
);
1586 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1587 src0
.type
== BRW_REGISTER_TYPE_UD
);
1589 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1590 const unsigned lower_size
= MIN2(inst
->exec_size
,
1591 devinfo
->gen
>= 8 ? 16 : 8);
1593 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1594 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1595 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1596 (i
* lower_size
/ (1 << src0
.width
))) *
1597 type_sz(src0
.type
) / REG_SIZE
),
1598 suboffset(reg
, i
* lower_size
/ 4));
1599 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1600 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1601 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1602 brw_set_default_swsb(p
, tgl_swsb_null());
1607 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1612 assert(devinfo
->gen
>= 7);
1613 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1614 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1615 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1617 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1619 * Because this instruction does not have a 16-bit floating-point type,
1620 * the destination data type must be Word (W).
1622 * The destination must be DWord-aligned and specify a horizontal stride
1623 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1624 * each destination channel and the upper word is not modified.
1626 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1628 /* Give each 32-bit channel of dst the form below, where "." means
1632 brw_F32TO16(p
, dst_w
, y
);
1637 brw_set_default_swsb(p
, tgl_swsb_regdist(1));
1638 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1640 /* And, finally the form of packHalf2x16's output:
1643 brw_F32TO16(p
, dst_w
, x
);
1647 fs_generator::generate_shader_time_add(fs_inst
*,
1648 struct brw_reg payload
,
1649 struct brw_reg offset
,
1650 struct brw_reg value
)
1652 const tgl_swsb swsb
= brw_get_default_swsb(p
);
1654 assert(devinfo
->gen
>= 7);
1655 brw_push_insn_state(p
);
1656 brw_set_default_mask_control(p
, true);
1657 brw_set_default_swsb(p
, tgl_swsb_src_dep(swsb
));
1659 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1660 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1662 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1665 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1666 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1667 value
.width
= BRW_WIDTH_1
;
1668 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1669 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1671 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1674 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1675 * case, and we don't really care about squeezing every bit of performance
1676 * out of this path, so we just emit the MOVs from here.
1678 brw_MOV(p
, payload_offset
, offset
);
1679 brw_set_default_swsb(p
, tgl_swsb_null());
1680 brw_MOV(p
, payload_value
, value
);
1681 brw_set_default_swsb(p
, tgl_swsb_dst_dep(swsb
, 1));
1682 brw_shader_time_add(p
, payload
,
1683 prog_data
->binding_table
.shader_time_start
);
1684 brw_pop_insn_state(p
);
1688 fs_generator::enable_debug(const char *shader_name
)
1691 this->shader_name
= shader_name
;
1695 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
,
1696 struct brw_compile_stats
*stats
)
1698 /* align to 64 byte boundary. */
1699 while (p
->next_insn_offset
% 64)
1702 this->dispatch_width
= dispatch_width
;
1704 int start_offset
= p
->next_insn_offset
;
1705 int spill_count
= 0, fill_count
= 0;
1708 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1710 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1711 if (inst
->opcode
== SHADER_OPCODE_UNDEF
)
1714 struct brw_reg src
[4], dst
;
1715 unsigned int last_insn_offset
= p
->next_insn_offset
;
1716 bool multiple_instructions_emitted
= false;
1718 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1719 * "Register Region Restrictions" section: for BDW, SKL:
1721 * "A POW/FDIV operation must not be followed by an instruction
1722 * that requires two destination registers."
1724 * The documentation is often lacking annotations for Atom parts,
1725 * and empirically this affects CHV as well.
1727 if (devinfo
->gen
>= 8 &&
1728 devinfo
->gen
<= 9 &&
1730 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1731 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1732 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1734 last_insn_offset
= p
->next_insn_offset
;
1737 if (unlikely(debug_flag
))
1738 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1740 /* If the instruction writes to more than one register, it needs to be
1741 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1742 * hardware figures out by itself what the right compression mode is,
1743 * but we still need to know whether the instruction is compressed to
1744 * set up the source register regions appropriately.
1746 * XXX - This is wrong for instructions that write a single register but
1747 * read more than one which should strictly speaking be treated as
1748 * compressed. For instructions that don't write any registers it
1749 * relies on the destination being a null register of the correct
1750 * type and regioning so the instruction is considered compressed
1751 * or not accordingly.
1753 const bool compressed
=
1754 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1755 brw_set_default_compression(p
, compressed
);
1756 brw_set_default_group(p
, inst
->group
);
1758 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1759 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1760 &inst
->src
[i
], compressed
);
1761 /* The accumulator result appears to get used for the
1762 * conditional modifier generation. When negating a UD
1763 * value, there is a 33rd bit generated for the sign in the
1764 * accumulator value, so now you can't check, for example,
1765 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1767 assert(!inst
->conditional_mod
||
1768 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1769 !inst
->src
[i
].negate
);
1771 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1772 &inst
->dst
, compressed
);
1774 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1775 brw_set_default_predicate_control(p
, inst
->predicate
);
1776 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1777 /* On gen7 and above, hardware automatically adds the group onto the
1778 * flag subregister number. On Sandy Bridge and older, we have to do it
1781 const unsigned flag_subreg
= inst
->flag_subreg
+
1782 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1783 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1784 brw_set_default_saturate(p
, inst
->saturate
);
1785 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1786 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1787 brw_set_default_swsb(p
, inst
->sched
);
1789 unsigned exec_size
= inst
->exec_size
;
1790 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1791 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1795 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1797 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1798 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1799 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1800 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1802 switch (inst
->opcode
) {
1803 case BRW_OPCODE_SYNC
:
1804 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
1805 brw_SYNC(p
, tgl_sync_function(src
[0].ud
));
1807 case BRW_OPCODE_MOV
:
1808 brw_MOV(p
, dst
, src
[0]);
1810 case BRW_OPCODE_ADD
:
1811 brw_ADD(p
, dst
, src
[0], src
[1]);
1813 case BRW_OPCODE_MUL
:
1814 brw_MUL(p
, dst
, src
[0], src
[1]);
1816 case BRW_OPCODE_AVG
:
1817 brw_AVG(p
, dst
, src
[0], src
[1]);
1819 case BRW_OPCODE_MACH
:
1820 brw_MACH(p
, dst
, src
[0], src
[1]);
1823 case BRW_OPCODE_LINE
:
1824 brw_LINE(p
, dst
, src
[0], src
[1]);
1827 case BRW_OPCODE_MAD
:
1828 assert(devinfo
->gen
>= 6);
1829 if (devinfo
->gen
< 10)
1830 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1831 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1834 case BRW_OPCODE_LRP
:
1835 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1836 if (devinfo
->gen
< 10)
1837 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1838 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1841 case BRW_OPCODE_FRC
:
1842 brw_FRC(p
, dst
, src
[0]);
1844 case BRW_OPCODE_RNDD
:
1845 brw_RNDD(p
, dst
, src
[0]);
1847 case BRW_OPCODE_RNDE
:
1848 brw_RNDE(p
, dst
, src
[0]);
1850 case BRW_OPCODE_RNDZ
:
1851 brw_RNDZ(p
, dst
, src
[0]);
1854 case BRW_OPCODE_AND
:
1855 brw_AND(p
, dst
, src
[0], src
[1]);
1858 brw_OR(p
, dst
, src
[0], src
[1]);
1860 case BRW_OPCODE_XOR
:
1861 brw_XOR(p
, dst
, src
[0], src
[1]);
1863 case BRW_OPCODE_NOT
:
1864 brw_NOT(p
, dst
, src
[0]);
1866 case BRW_OPCODE_ASR
:
1867 brw_ASR(p
, dst
, src
[0], src
[1]);
1869 case BRW_OPCODE_SHR
:
1870 brw_SHR(p
, dst
, src
[0], src
[1]);
1872 case BRW_OPCODE_SHL
:
1873 brw_SHL(p
, dst
, src
[0], src
[1]);
1875 case BRW_OPCODE_ROL
:
1876 assert(devinfo
->gen
>= 11);
1877 assert(src
[0].type
== dst
.type
);
1878 brw_ROL(p
, dst
, src
[0], src
[1]);
1880 case BRW_OPCODE_ROR
:
1881 assert(devinfo
->gen
>= 11);
1882 assert(src
[0].type
== dst
.type
);
1883 brw_ROR(p
, dst
, src
[0], src
[1]);
1885 case BRW_OPCODE_F32TO16
:
1886 assert(devinfo
->gen
>= 7);
1887 brw_F32TO16(p
, dst
, src
[0]);
1889 case BRW_OPCODE_F16TO32
:
1890 assert(devinfo
->gen
>= 7);
1891 brw_F16TO32(p
, dst
, src
[0]);
1893 case BRW_OPCODE_CMP
:
1894 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1895 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1896 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1897 * implemented in the compiler is not sufficient. Overriding the
1898 * type when the destination is the null register is necessary but
1899 * not sufficient by itself.
1901 assert(dst
.nr
== BRW_ARF_NULL
);
1902 dst
.type
= BRW_REGISTER_TYPE_D
;
1904 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1906 case BRW_OPCODE_SEL
:
1907 brw_SEL(p
, dst
, src
[0], src
[1]);
1909 case BRW_OPCODE_CSEL
:
1910 assert(devinfo
->gen
>= 8);
1911 if (devinfo
->gen
< 10)
1912 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1913 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1915 case BRW_OPCODE_BFREV
:
1916 assert(devinfo
->gen
>= 7);
1917 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1918 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1920 case BRW_OPCODE_FBH
:
1921 assert(devinfo
->gen
>= 7);
1922 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1924 case BRW_OPCODE_FBL
:
1925 assert(devinfo
->gen
>= 7);
1926 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1927 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1929 case BRW_OPCODE_LZD
:
1930 brw_LZD(p
, dst
, src
[0]);
1932 case BRW_OPCODE_CBIT
:
1933 assert(devinfo
->gen
>= 7);
1934 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1935 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1937 case BRW_OPCODE_ADDC
:
1938 assert(devinfo
->gen
>= 7);
1939 brw_ADDC(p
, dst
, src
[0], src
[1]);
1941 case BRW_OPCODE_SUBB
:
1942 assert(devinfo
->gen
>= 7);
1943 brw_SUBB(p
, dst
, src
[0], src
[1]);
1945 case BRW_OPCODE_MAC
:
1946 brw_MAC(p
, dst
, src
[0], src
[1]);
1949 case BRW_OPCODE_BFE
:
1950 assert(devinfo
->gen
>= 7);
1951 if (devinfo
->gen
< 10)
1952 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1953 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1956 case BRW_OPCODE_BFI1
:
1957 assert(devinfo
->gen
>= 7);
1958 brw_BFI1(p
, dst
, src
[0], src
[1]);
1960 case BRW_OPCODE_BFI2
:
1961 assert(devinfo
->gen
>= 7);
1962 if (devinfo
->gen
< 10)
1963 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1964 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1968 if (inst
->src
[0].file
!= BAD_FILE
) {
1969 /* The instruction has an embedded compare (only allowed on gen6) */
1970 assert(devinfo
->gen
== 6);
1971 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1973 brw_IF(p
, brw_get_default_exec_size(p
));
1977 case BRW_OPCODE_ELSE
:
1980 case BRW_OPCODE_ENDIF
:
1985 brw_DO(p
, brw_get_default_exec_size(p
));
1988 case BRW_OPCODE_BREAK
:
1991 case BRW_OPCODE_CONTINUE
:
1995 case BRW_OPCODE_WHILE
:
2000 case SHADER_OPCODE_RCP
:
2001 case SHADER_OPCODE_RSQ
:
2002 case SHADER_OPCODE_SQRT
:
2003 case SHADER_OPCODE_EXP2
:
2004 case SHADER_OPCODE_LOG2
:
2005 case SHADER_OPCODE_SIN
:
2006 case SHADER_OPCODE_COS
:
2007 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2008 if (devinfo
->gen
>= 6) {
2009 assert(inst
->mlen
== 0);
2010 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
2011 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
2012 src
[0], brw_null_reg());
2014 assert(inst
->mlen
>= 1);
2015 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
2017 brw_math_function(inst
->opcode
),
2018 inst
->base_mrf
, src
[0],
2019 BRW_MATH_PRECISION_FULL
);
2022 case SHADER_OPCODE_INT_QUOTIENT
:
2023 case SHADER_OPCODE_INT_REMAINDER
:
2024 case SHADER_OPCODE_POW
:
2025 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2026 if (devinfo
->gen
>= 6) {
2027 assert(inst
->mlen
== 0);
2028 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
2029 inst
->exec_size
== 8);
2030 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2032 assert(inst
->mlen
>= 1);
2033 assert(inst
->exec_size
== 8);
2034 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
2035 inst
->base_mrf
, src
[0],
2036 BRW_MATH_PRECISION_FULL
);
2039 case FS_OPCODE_LINTERP
:
2040 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
2042 case FS_OPCODE_PIXEL_X
:
2043 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2044 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2045 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2047 case FS_OPCODE_PIXEL_Y
:
2048 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2049 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2050 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2053 case SHADER_OPCODE_SEND
:
2054 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
2055 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2058 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2059 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2061 case SHADER_OPCODE_TEX
:
2063 case SHADER_OPCODE_TXD
:
2064 case SHADER_OPCODE_TXF
:
2065 case SHADER_OPCODE_TXF_CMS
:
2066 case SHADER_OPCODE_TXL
:
2067 case SHADER_OPCODE_TXS
:
2068 case SHADER_OPCODE_LOD
:
2069 case SHADER_OPCODE_TG4
:
2070 case SHADER_OPCODE_SAMPLEINFO
:
2071 assert(inst
->src
[0].file
== BAD_FILE
);
2072 generate_tex(inst
, dst
, src
[1], src
[2]);
2075 case FS_OPCODE_DDX_COARSE
:
2076 case FS_OPCODE_DDX_FINE
:
2077 generate_ddx(inst
, dst
, src
[0]);
2079 case FS_OPCODE_DDY_COARSE
:
2080 case FS_OPCODE_DDY_FINE
:
2081 generate_ddy(inst
, dst
, src
[0]);
2084 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2085 generate_scratch_write(inst
, src
[0]);
2089 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2090 generate_scratch_read(inst
, dst
);
2094 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2095 generate_scratch_read_gen7(inst
, dst
);
2099 case SHADER_OPCODE_MOV_INDIRECT
:
2100 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2103 case SHADER_OPCODE_URB_READ_SIMD8
:
2104 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2105 generate_urb_read(inst
, dst
, src
[0]);
2108 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2109 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2110 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2111 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2112 generate_urb_write(inst
, src
[0]);
2115 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2116 assert(inst
->force_writemask_all
);
2117 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2120 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2121 assert(inst
->force_writemask_all
);
2122 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2125 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2126 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2129 case FS_OPCODE_REP_FB_WRITE
:
2130 case FS_OPCODE_FB_WRITE
:
2131 generate_fb_write(inst
, src
[0]);
2134 case FS_OPCODE_FB_READ
:
2135 generate_fb_read(inst
, dst
, src
[0]);
2138 case FS_OPCODE_DISCARD_JUMP
:
2139 generate_discard_jump(inst
);
2142 case SHADER_OPCODE_SHADER_TIME_ADD
:
2143 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2146 case SHADER_OPCODE_MEMORY_FENCE
:
2147 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2148 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2149 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SEND
, src
[1].ud
, src
[2].ud
);
2152 case SHADER_OPCODE_INTERLOCK
:
2153 assert(devinfo
->gen
>= 9);
2154 /* The interlock is basically a memory fence issued via sendc */
2155 brw_memory_fence(p
, dst
, src
[0], BRW_OPCODE_SENDC
, false, /* bti */ 0);
2158 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2159 const struct brw_reg mask
=
2160 brw_stage_has_packed_dispatch(devinfo
, stage
,
2161 prog_data
) ? brw_imm_ud(~0u) :
2162 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2164 brw_find_live_channel(p
, dst
, mask
);
2168 case SHADER_OPCODE_BROADCAST
:
2169 assert(inst
->force_writemask_all
);
2170 brw_broadcast(p
, dst
, src
[0], src
[1]);
2173 case SHADER_OPCODE_SHUFFLE
:
2174 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2177 case SHADER_OPCODE_SEL_EXEC
:
2178 assert(inst
->force_writemask_all
);
2179 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2180 brw_MOV(p
, dst
, src
[1]);
2181 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2182 brw_set_default_swsb(p
, tgl_swsb_null());
2183 brw_MOV(p
, dst
, src
[0]);
2186 case SHADER_OPCODE_QUAD_SWIZZLE
:
2187 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2188 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2189 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2192 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2193 assert(!src
[0].negate
&& !src
[0].abs
);
2194 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2195 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2196 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2197 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2198 const unsigned component
= src
[1].ud
;
2199 const unsigned cluster_size
= src
[2].ud
;
2200 unsigned vstride
= cluster_size
;
2201 unsigned width
= cluster_size
;
2203 /* The maximum exec_size is 32, but the maximum width is only 16. */
2204 if (inst
->exec_size
== width
) {
2209 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2211 if (type_sz(src
[0].type
) > 4 &&
2212 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2213 /* IVB has an issue (which we found empirically) where it reads
2214 * two address register components per channel for indirectly
2215 * addressed 64-bit sources.
2217 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2219 * "When source or destination datatype is 64b or operation is
2220 * integer DWord multiply, indirect addressing must not be
2223 * To work around both of these, we do two integer MOVs insead of
2224 * one 64-bit MOV. Because no double value should ever cross a
2225 * register boundary, it's safe to use the immediate offset in the
2226 * indirect here to handle adding 4 bytes to the offset and avoid
2227 * the extra ADD to the register file.
2229 assert(src
[0].type
== dst
.type
);
2230 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2231 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2232 brw_set_default_swsb(p
, tgl_swsb_null());
2233 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2234 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2236 brw_MOV(p
, dst
, strided
);
2241 case FS_OPCODE_SET_SAMPLE_ID
:
2242 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2245 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2246 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2249 case FS_OPCODE_PLACEHOLDER_HALT
:
2250 /* This is the place where the final HALT needs to be inserted if
2251 * we've emitted any discards. If not, this will emit no code.
2253 if (!patch_discard_jumps_to_fb_writes()) {
2254 if (unlikely(debug_flag
)) {
2255 disasm_info
->use_tail
= true;
2260 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2261 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2262 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2265 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2266 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2267 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2270 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2271 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2272 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2275 case CS_OPCODE_CS_TERMINATE
:
2276 generate_cs_terminate(inst
, src
[0]);
2279 case SHADER_OPCODE_BARRIER
:
2280 generate_barrier(inst
, src
[0]);
2283 case BRW_OPCODE_DIM
:
2284 assert(devinfo
->is_haswell
);
2285 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2286 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2287 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2290 case SHADER_OPCODE_RND_MODE
: {
2291 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2293 * Changes the floating point rounding mode updating the control
2294 * register field defined at cr0.0[5-6] bits.
2296 enum brw_rnd_mode mode
=
2297 (enum brw_rnd_mode
) (src
[0].d
<< BRW_CR0_RND_MODE_SHIFT
);
2298 brw_float_controls_mode(p
, mode
, BRW_CR0_RND_MODE_MASK
);
2302 case SHADER_OPCODE_FLOAT_CONTROL_MODE
:
2303 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2304 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2305 brw_float_controls_mode(p
, src
[0].d
, src
[1].d
);
2309 unreachable("Unsupported opcode");
2311 case SHADER_OPCODE_LOAD_PAYLOAD
:
2312 unreachable("Should be lowered by lower_load_payload()");
2315 if (multiple_instructions_emitted
)
2318 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2319 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2320 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2321 "emitting more than 1 instruction");
2323 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2325 if (inst
->conditional_mod
)
2326 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2327 if (devinfo
->gen
< 12) {
2328 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2329 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2334 brw_set_uip_jip(p
, start_offset
);
2336 /* end of program sentinel */
2337 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2342 if (unlikely(debug_flag
))
2344 brw_validate_instructions(devinfo
, p
->store
,
2346 p
->next_insn_offset
,
2349 int before_size
= p
->next_insn_offset
- start_offset
;
2350 brw_compact_instructions(p
, start_offset
, disasm_info
);
2351 int after_size
= p
->next_insn_offset
- start_offset
;
2353 if (unlikely(debug_flag
)) {
2354 unsigned char sha1
[21];
2357 _mesa_sha1_compute(p
->store
+ start_offset
/ sizeof(brw_inst
),
2359 _mesa_sha1_format(sha1buf
, sha1
);
2361 fprintf(stderr
, "Native code for %s (sha1 %s)\n"
2362 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2363 "%d:%d spills:fills. "
2364 "scheduled with mode %s. "
2365 "Promoted %u constants. "
2366 "Compacted %d to %d bytes (%.0f%%)\n",
2367 shader_name
, sha1buf
,
2368 dispatch_width
, before_size
/ 16,
2369 loop_count
, cfg
->cycle_count
,
2370 spill_count
, fill_count
,
2371 shader_stats
.scheduler_mode
,
2372 shader_stats
.promoted_constants
,
2373 before_size
, after_size
,
2374 100.0f
* (before_size
- after_size
) / before_size
);
2376 /* overriding the shader makes disasm_info invalid */
2377 if (!brw_try_override_assembly(p
, start_offset
, sha1buf
)) {
2378 dump_assembly(p
->store
, disasm_info
);
2380 fprintf(stderr
, "Successfully overrode shader with sha1 %s\n\n", sha1buf
);
2383 ralloc_free(disasm_info
);
2386 compiler
->shader_debug_log(log_data
,
2387 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2388 "%d:%d spills:fills, "
2389 "scheduled with mode %s, "
2390 "Promoted %u constants, "
2391 "compacted %d to %d bytes.",
2392 _mesa_shader_stage_to_abbrev(stage
),
2393 dispatch_width
, before_size
/ 16,
2394 loop_count
, cfg
->cycle_count
,
2395 spill_count
, fill_count
,
2396 shader_stats
.scheduler_mode
,
2397 shader_stats
.promoted_constants
,
2398 before_size
, after_size
);
2400 stats
->dispatch_width
= dispatch_width
;
2401 stats
->instructions
= before_size
/ 16;
2402 stats
->loops
= loop_count
;
2403 stats
->cycles
= cfg
->cycle_count
;
2404 stats
->spills
= spill_count
;
2405 stats
->fills
= fill_count
;
2408 return start_offset
;
2412 fs_generator::get_assembly()
2414 return brw_get_program(p
, &prog_data
->program_size
);