2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
34 static enum brw_reg_file
35 brw_file_from_reg(fs_reg
*reg
)
39 return BRW_ARCHITECTURE_REGISTER_FILE
;
42 return BRW_GENERAL_REGISTER_FILE
;
44 return BRW_MESSAGE_REGISTER_FILE
;
46 return BRW_IMMEDIATE_VALUE
;
50 unreachable("not reached");
52 return BRW_ARCHITECTURE_REGISTER_FILE
;
56 brw_reg_from_fs_reg(const struct gen_device_info
*devinfo
, fs_inst
*inst
,
57 fs_reg
*reg
, bool compressed
)
59 struct brw_reg brw_reg
;
63 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
66 if (reg
->stride
== 0) {
67 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 /* From the Haswell PRM:
71 * "VertStride must be used to cross GRF register boundaries. This
72 * rule implies that elements within a 'Width' cannot cross GRF
75 * The maximum width value that could satisfy this restriction is:
77 const unsigned reg_width
= REG_SIZE
/ (reg
->stride
* type_sz(reg
->type
));
79 /* Because the hardware can only split source regions at a whole
80 * multiple of width during decompression (i.e. vertically), clamp
81 * the value obtained above to the physical execution size of a
82 * single decompressed chunk of the instruction:
84 const unsigned phys_width
= compressed
? inst
->exec_size
/ 2 :
87 /* XXX - The equation above is strictly speaking not correct on
88 * hardware that supports unbalanced GRF writes -- On Gen9+
89 * each decompressed chunk of the instruction may have a
90 * different execution size when the number of components
91 * written to each destination GRF is not the same.
93 const unsigned width
= MIN2(reg_width
, phys_width
);
94 brw_reg
= brw_vecn_reg(width
, brw_file_from_reg(reg
), reg
->nr
, 0);
95 brw_reg
= stride(brw_reg
, width
* reg
->stride
, width
, reg
->stride
);
97 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
98 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
99 * "Each DF (Double Float) operand uses an element size of 4 rather
100 * than 8 and all regioning parameters are twice what the values
101 * would be based on the true element size: ExecSize, Width,
102 * HorzStride, and VertStride. Each DF operand uses a pair of
103 * channels and all masking and swizzing should be adjusted
106 * From the IvyBridge PRM (Special Requirements for Handling Double
107 * Precision Data Types, page 71):
108 * "In Align1 mode, all regioning parameters like stride, execution
109 * size, and width must use the syntax of a pair of packed
110 * floats. The offsets for these data types must be 64-bit
111 * aligned. The execution size and regioning parameters are in terms
114 * Summarized: when handling DF-typed arguments, ExecSize,
115 * VertStride, and Width must be doubled.
117 * It applies to BayTrail too.
119 if (type_sz(reg
->type
) == 8) {
121 if (brw_reg
.vstride
> 0)
123 assert(brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
126 /* When converting from DF->F, we set the destination stride to 2
127 * because each d2f conversion implicitly writes 2 floats, being
128 * the first one the converted value. IVB/BYT actually writes two
129 * F components per SIMD channel, and every other component is
130 * filled with garbage.
132 if (reg
== &inst
->dst
&& get_exec_type_size(inst
) == 8 &&
133 type_sz(inst
->dst
.type
) < 8) {
134 assert(brw_reg
.hstride
> BRW_HORIZONTAL_STRIDE_1
);
140 brw_reg
= retype(brw_reg
, reg
->type
);
141 brw_reg
= byte_offset(brw_reg
, reg
->offset
);
142 brw_reg
.abs
= reg
->abs
;
143 brw_reg
.negate
= reg
->negate
;
148 assert(reg
->offset
== 0);
149 brw_reg
= reg
->as_brw_reg();
152 /* Probably unused. */
153 brw_reg
= brw_null_reg();
157 unreachable("not reached");
160 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
161 * region, but on IVB and BYT DF regions must be programmed in terms of
162 * floats. A <0,2,1> region accomplishes this.
164 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
165 type_sz(reg
->type
) == 8 &&
166 brw_reg
.vstride
== BRW_VERTICAL_STRIDE_0
&&
167 brw_reg
.width
== BRW_WIDTH_1
&&
168 brw_reg
.hstride
== BRW_HORIZONTAL_STRIDE_0
) {
169 brw_reg
.width
= BRW_WIDTH_2
;
170 brw_reg
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
176 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
178 struct brw_stage_prog_data
*prog_data
,
179 unsigned promoted_constants
,
180 bool runtime_check_aads_emit
,
181 gl_shader_stage stage
)
183 : compiler(compiler
), log_data(log_data
),
184 devinfo(compiler
->devinfo
),
185 prog_data(prog_data
),
186 promoted_constants(promoted_constants
),
187 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
188 stage(stage
), mem_ctx(mem_ctx
)
190 p
= rzalloc(mem_ctx
, struct brw_codegen
);
191 brw_init_codegen(devinfo
, p
, mem_ctx
);
193 /* In the FS code generator, we are very careful to ensure that we always
194 * set the right execution size so we don't need the EU code to "help" us
195 * by trying to infer it. Sometimes, it infers the wrong thing.
197 p
->automatic_exec_sizes
= false;
200 fs_generator::~fs_generator()
204 class ip_record
: public exec_node
{
206 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
217 fs_generator::patch_discard_jumps_to_fb_writes()
219 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
222 int scale
= brw_jump_scale(p
->devinfo
);
224 /* There is a somewhat strange undocumented requirement of using
225 * HALT, according to the simulator. If some channel has HALTed to
226 * a particular UIP, then by the end of the program, every channel
227 * must have HALTed to that UIP. Furthermore, the tracking is a
228 * stack, so you can't do the final halt of a UIP after starting
229 * halting to a new UIP.
231 * Symptoms of not emitting this instruction on actual hardware
232 * included GPU hangs and sparkly rendering on the piglit discard
235 brw_inst
*last_halt
= gen6_HALT(p
);
236 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
237 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
241 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
242 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
244 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
245 /* HALT takes a half-instruction distance from the pre-incremented IP. */
246 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
249 this->discard_halt_patches
.make_empty();
254 fs_generator::generate_send(fs_inst
*inst
,
257 struct brw_reg ex_desc
,
258 struct brw_reg payload
,
259 struct brw_reg payload2
)
261 const bool dst_is_null
= dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
262 dst
.nr
== BRW_ARF_NULL
;
263 const unsigned rlen
= dst_is_null
? 0 : inst
->size_written
/ REG_SIZE
;
265 uint32_t desc_imm
= inst
->desc
|
266 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
);
268 uint32_t ex_desc_imm
= brw_message_ex_desc(devinfo
, inst
->ex_mlen
);
270 if (ex_desc
.file
!= BRW_IMMEDIATE_VALUE
|| ex_desc
.ud
|| ex_desc_imm
) {
271 /* If we have any sort of extended descriptor, then we need SENDS. This
272 * also covers the dual-payload case because ex_mlen goes in ex_desc.
274 brw_send_indirect_split_message(p
, inst
->sfid
, dst
, payload
, payload2
,
275 desc
, desc_imm
, ex_desc
, ex_desc_imm
);
277 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDSC
);
279 brw_send_indirect_message(p
, inst
->sfid
, dst
, payload
, desc
, desc_imm
);
281 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
284 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, inst
->eot
);
288 fs_generator::fire_fb_write(fs_inst
*inst
,
289 struct brw_reg payload
,
290 struct brw_reg implied_header
,
293 uint32_t msg_control
;
295 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
297 if (devinfo
->gen
< 6) {
298 brw_push_insn_state(p
);
299 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
300 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
301 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
302 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
303 brw_MOV(p
, offset(retype(payload
, BRW_REGISTER_TYPE_UD
), 1),
304 offset(retype(implied_header
, BRW_REGISTER_TYPE_UD
), 1));
305 brw_pop_insn_state(p
);
308 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
) {
309 assert(inst
->group
== 0 && inst
->exec_size
== 16);
310 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
312 } else if (prog_data
->dual_src_blend
) {
313 assert(inst
->exec_size
== 8);
315 if (inst
->group
% 16 == 0)
316 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
317 else if (inst
->group
% 16 == 8)
318 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
320 unreachable("Invalid dual-source FB write instruction group");
323 assert(inst
->group
== 0 || (inst
->group
== 16 && inst
->exec_size
== 16));
325 if (inst
->exec_size
== 16)
326 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
327 else if (inst
->exec_size
== 8)
328 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
330 unreachable("Invalid FB write execution size");
333 /* We assume render targets start at 0, because headerless FB write
334 * messages set "Render Target Index" to 0. Using a different binding
335 * table index would make it impossible to use headerless messages.
337 const uint32_t surf_index
= inst
->target
;
339 brw_inst
*insn
= brw_fb_WRITE(p
,
341 retype(implied_header
, BRW_REGISTER_TYPE_UW
),
348 inst
->header_size
!= 0);
350 if (devinfo
->gen
>= 6)
351 brw_inst_set_rt_slot_group(devinfo
, insn
, inst
->group
/ 16);
355 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
357 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
358 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
361 const struct brw_reg implied_header
=
362 devinfo
->gen
< 6 ? payload
: brw_null_reg();
364 if (inst
->base_mrf
>= 0)
365 payload
= brw_message_reg(inst
->base_mrf
);
367 if (!runtime_check_aads_emit
) {
368 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
370 /* This can only happen in gen < 6 */
371 assert(devinfo
->gen
< 6);
373 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
375 /* Check runtime bit to detect if we have to send AA data or not */
376 brw_push_insn_state(p
);
377 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
378 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
381 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
383 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
385 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
386 brw_pop_insn_state(p
);
388 /* Don't send AA data */
389 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
391 brw_land_fwd_jump(p
, jmp
);
392 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
397 fs_generator::generate_fb_read(fs_inst
*inst
, struct brw_reg dst
,
398 struct brw_reg payload
)
400 assert(inst
->size_written
% REG_SIZE
== 0);
401 struct brw_wm_prog_data
*prog_data
= brw_wm_prog_data(this->prog_data
);
402 /* We assume that render targets start at binding table index 0. */
403 const unsigned surf_index
= inst
->target
;
405 gen9_fb_READ(p
, dst
, payload
, surf_index
,
406 inst
->header_size
, inst
->size_written
/ REG_SIZE
,
407 prog_data
->persample_dispatch
);
411 fs_generator::generate_mov_indirect(fs_inst
*inst
,
414 struct brw_reg indirect_byte_offset
)
416 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
417 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
418 assert(!reg
.abs
&& !reg
.negate
);
419 assert(reg
.type
== dst
.type
);
421 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
423 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
424 imm_byte_offset
+= indirect_byte_offset
.ud
;
426 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
427 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
428 brw_MOV(p
, dst
, reg
);
430 /* Prior to Broadwell, there are only 8 address registers. */
431 assert(inst
->exec_size
<= 8 || devinfo
->gen
>= 8);
433 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
434 struct brw_reg addr
= vec8(brw_address_reg(0));
436 /* The destination stride of an instruction (in bytes) must be greater
437 * than or equal to the size of the rest of the instruction. Since the
438 * address register is of type UW, we can't use a D-type instruction.
439 * In order to get around this, re retype to UW and use a stride.
441 indirect_byte_offset
=
442 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
444 /* There are a number of reasons why we don't use the base offset here.
445 * One reason is that the field is only 9 bits which means we can only
446 * use it to access the first 16 GRFs. Also, from the Haswell PRM
447 * section "Register Region Restrictions":
449 * "The lower bits of the AddressImmediate must not overflow to
450 * change the register address. The lower 5 bits of Address
451 * Immediate when added to lower 5 bits of address register gives
452 * the sub-register offset. The upper bits of Address Immediate
453 * when added to upper bits of address register gives the register
454 * address. Any overflow from sub-register offset is dropped."
456 * Since the indirect may cause us to cross a register boundary, this
457 * makes the base offset almost useless. We could try and do something
458 * clever where we use a actual base offset if base_offset % 32 == 0 but
459 * that would mean we were generating different code depending on the
460 * base offset. Instead, for the sake of consistency, we'll just do the
461 * add ourselves. This restriction is only listed in the Haswell PRM
462 * but empirical testing indicates that it applies on all older
463 * generations and is lifted on Broadwell.
465 * In the end, while base_offset is nice to look at in the generated
466 * code, using it saves us 0 instructions and would require quite a bit
467 * of case-by-case work. It's just not worth it.
469 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
471 if (type_sz(reg
.type
) > 4 &&
472 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
473 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
) ||
474 !devinfo
->has_64bit_types
)) {
475 /* IVB has an issue (which we found empirically) where it reads two
476 * address register components per channel for indirectly addressed
479 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
481 * "When source or destination datatype is 64b or operation is
482 * integer DWord multiply, indirect addressing must not be used."
484 * To work around both of these, we do two integer MOVs insead of one
485 * 64-bit MOV. Because no double value should ever cross a register
486 * boundary, it's safe to use the immediate offset in the indirect
487 * here to handle adding 4 bytes to the offset and avoid the extra
488 * ADD to the register file.
490 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
491 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
492 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
493 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
495 struct brw_reg ind_src
= brw_VxH_indirect(0, 0);
497 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, reg
.type
));
499 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
500 !inst
->get_next()->is_tail_sentinel() &&
501 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
502 /* From the Sandybridge PRM:
504 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
505 * instruction that “indexed/indirect” source AND is followed
506 * by a send, the instruction requires a “Switch”. This is to
507 * avoid race condition where send may dispatch before MRF is
510 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
517 fs_generator::generate_shuffle(fs_inst
*inst
,
522 /* Ivy bridge has some strange behavior that makes this a real pain to
523 * implement for 64-bit values so we just don't bother.
525 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
|| type_sz(src
.type
) <= 4);
527 /* Because we're using the address register, we're limited to 8-wide
528 * execution on gen7. On gen8, we're limited to 16-wide by the address
529 * register file and 8-wide for 64-bit types. We could try and make this
530 * instruction splittable higher up in the compiler but that gets weird
531 * because it reads all of the channels regardless of execution size. It's
532 * easier just to split it here.
534 const unsigned lower_width
=
535 (devinfo
->gen
<= 7 || type_sz(src
.type
) > 4) ?
536 8 : MIN2(16, inst
->exec_size
);
538 brw_set_default_exec_size(p
, cvt(lower_width
) - 1);
539 for (unsigned group
= 0; group
< inst
->exec_size
; group
+= lower_width
) {
540 brw_set_default_group(p
, group
);
542 if ((src
.vstride
== 0 && src
.hstride
== 0) ||
543 idx
.file
== BRW_IMMEDIATE_VALUE
) {
544 /* Trivial, the source is already uniform or the index is a constant.
545 * We will typically not get here if the optimizer is doing its job,
546 * but asserting would be mean.
548 const unsigned i
= idx
.file
== BRW_IMMEDIATE_VALUE
? idx
.ud
: 0;
549 brw_MOV(p
, suboffset(dst
, group
), stride(suboffset(src
, i
), 0, 1, 0));
551 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
552 struct brw_reg addr
= vec8(brw_address_reg(0));
554 struct brw_reg group_idx
= suboffset(idx
, group
);
556 if (lower_width
== 8 && group_idx
.width
== BRW_WIDTH_16
) {
557 /* Things get grumpy if the register is too wide. */
562 assert(type_sz(group_idx
.type
) <= 4);
563 if (type_sz(group_idx
.type
) == 4) {
564 /* The destination stride of an instruction (in bytes) must be
565 * greater than or equal to the size of the rest of the
566 * instruction. Since the address register is of type UW, we
567 * can't use a D-type instruction. In order to get around this,
568 * re retype to UW and use a stride.
570 group_idx
= retype(spread(group_idx
, 2), BRW_REGISTER_TYPE_W
);
573 /* Take into account the component size and horizontal stride. */
574 assert(src
.vstride
== src
.hstride
+ src
.width
);
575 brw_SHL(p
, addr
, group_idx
,
576 brw_imm_uw(_mesa_logbase2(type_sz(src
.type
)) +
579 /* Add on the register start offset */
580 brw_ADD(p
, addr
, addr
, brw_imm_uw(src
.nr
* REG_SIZE
+ src
.subnr
));
582 if (type_sz(src
.type
) > 4 &&
583 ((devinfo
->gen
== 7 && !devinfo
->is_haswell
) ||
584 devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
585 /* IVB has an issue (which we found empirically) where it reads
586 * two address register components per channel for indirectly
587 * addressed 64-bit sources.
589 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
591 * "When source or destination datatype is 64b or operation is
592 * integer DWord multiply, indirect addressing must not be
595 * To work around both of these, we do two integer MOVs insead of
596 * one 64-bit MOV. Because no double value should ever cross a
597 * register boundary, it's safe to use the immediate offset in the
598 * indirect here to handle adding 4 bytes to the offset and avoid
599 * the extra ADD to the register file.
601 struct brw_reg gdst
= suboffset(dst
, group
);
602 struct brw_reg dst_d
= retype(spread(gdst
, 2),
603 BRW_REGISTER_TYPE_D
);
605 retype(brw_VxH_indirect(0, 0), BRW_REGISTER_TYPE_D
));
606 brw_MOV(p
, byte_offset(dst_d
, 4),
607 retype(brw_VxH_indirect(0, 4), BRW_REGISTER_TYPE_D
));
609 brw_MOV(p
, suboffset(dst
, group
),
610 retype(brw_VxH_indirect(0, 0), src
.type
));
617 fs_generator::generate_quad_swizzle(const fs_inst
*inst
,
618 struct brw_reg dst
, struct brw_reg src
,
621 /* Requires a quad. */
622 assert(inst
->exec_size
>= 4);
624 if (src
.file
== BRW_IMMEDIATE_VALUE
||
625 has_scalar_region(src
)) {
626 /* The value is uniform across all channels */
627 brw_MOV(p
, dst
, src
);
629 } else if (devinfo
->gen
< 11 && type_sz(src
.type
) == 4) {
630 /* This only works on 8-wide 32-bit values */
631 assert(inst
->exec_size
== 8);
632 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
633 assert(src
.vstride
== src
.width
+ 1);
634 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
635 struct brw_reg swiz_src
= stride(src
, 4, 4, 1);
636 swiz_src
.swizzle
= swiz
;
637 brw_MOV(p
, dst
, swiz_src
);
640 assert(src
.hstride
== BRW_HORIZONTAL_STRIDE_1
);
641 assert(src
.vstride
== src
.width
+ 1);
642 const struct brw_reg src_0
= suboffset(src
, BRW_GET_SWZ(swiz
, 0));
645 case BRW_SWIZZLE_XXXX
:
646 case BRW_SWIZZLE_YYYY
:
647 case BRW_SWIZZLE_ZZZZ
:
648 case BRW_SWIZZLE_WWWW
:
649 brw_MOV(p
, dst
, stride(src_0
, 4, 4, 0));
652 case BRW_SWIZZLE_XXZZ
:
653 case BRW_SWIZZLE_YYWW
:
654 brw_MOV(p
, dst
, stride(src_0
, 2, 2, 0));
657 case BRW_SWIZZLE_XYXY
:
658 case BRW_SWIZZLE_ZWZW
:
659 assert(inst
->exec_size
== 4);
660 brw_MOV(p
, dst
, stride(src_0
, 0, 2, 1));
664 assert(inst
->force_writemask_all
);
665 brw_set_default_exec_size(p
, cvt(inst
->exec_size
/ 4) - 1);
667 for (unsigned c
= 0; c
< 4; c
++) {
668 brw_inst
*insn
= brw_MOV(
669 p
, stride(suboffset(dst
, c
),
670 4 * inst
->dst
.stride
, 1, 4 * inst
->dst
.stride
),
671 stride(suboffset(src
, BRW_GET_SWZ(swiz
, c
)), 4, 1, 0));
673 brw_inst_set_no_dd_clear(devinfo
, insn
, c
< 3);
674 brw_inst_set_no_dd_check(devinfo
, insn
, c
> 0);
683 fs_generator::generate_urb_read(fs_inst
*inst
,
685 struct brw_reg header
)
687 assert(inst
->size_written
% REG_SIZE
== 0);
688 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
689 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
691 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
692 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
693 brw_set_src0(p
, send
, header
);
694 brw_set_src1(p
, send
, brw_imm_ud(0u));
696 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
697 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
699 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
700 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
702 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
703 brw_inst_set_rlen(p
->devinfo
, send
, inst
->size_written
/ REG_SIZE
);
704 brw_inst_set_header_present(p
->devinfo
, send
, true);
705 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
709 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
713 /* WaClearTDRRegBeforeEOTForNonPS.
715 * WA: Clear tdr register before send EOT in all non-PS shader kernels
717 * mov(8) tdr0:ud 0x0:ud {NoMask}"
719 if (inst
->eot
&& p
->devinfo
->gen
== 10) {
720 brw_push_insn_state(p
);
721 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
722 brw_MOV(p
, brw_tdr_reg(), brw_imm_uw(0));
723 brw_pop_insn_state(p
);
726 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
728 brw_set_dest(p
, insn
, brw_null_reg());
729 brw_set_src0(p
, insn
, payload
);
730 brw_set_src1(p
, insn
, brw_imm_ud(0u));
732 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
733 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
735 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
736 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
737 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
739 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
740 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
741 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
743 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
744 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
745 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
746 brw_inst_set_header_present(p
->devinfo
, insn
, true);
747 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
751 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
753 struct brw_inst
*insn
;
755 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
757 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
758 brw_set_src0(p
, insn
, retype(payload
, BRW_REGISTER_TYPE_UW
));
759 brw_set_src1(p
, insn
, brw_imm_ud(0u));
761 /* Terminate a compute shader by sending a message to the thread spawner.
763 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
764 brw_inst_set_mlen(devinfo
, insn
, 1);
765 brw_inst_set_rlen(devinfo
, insn
, 0);
766 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
767 brw_inst_set_header_present(devinfo
, insn
, false);
769 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
770 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
772 /* Note that even though the thread has a URB resource associated with it,
773 * we set the "do not dereference URB" bit, because the URB resource is
774 * managed by the fixed-function unit, so it will free it automatically.
776 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
778 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
782 fs_generator::generate_barrier(fs_inst
*, struct brw_reg src
)
789 fs_generator::generate_linterp(fs_inst
*inst
,
790 struct brw_reg dst
, struct brw_reg
*src
)
794 * -----------------------------------
795 * | src1+0 | src1+1 | src1+2 | src1+3 |
796 * |-----------------------------------|
797 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
798 * -----------------------------------
800 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
802 * -----------------------------------
803 * | src1+0 | src1+1 | src1+2 | src1+3 |
804 * |-----------------------------------|
805 * |(x0, x1)|(y0, y1)| | | in SIMD8
806 * |-----------------------------------|
807 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
808 * -----------------------------------
810 * See also: emit_interpolation_setup_gen4().
812 struct brw_reg delta_x
= src
[0];
813 struct brw_reg delta_y
= offset(src
[0], inst
->exec_size
/ 8);
814 struct brw_reg interp
= src
[1];
817 if (devinfo
->gen
>= 11) {
818 struct brw_reg acc
= retype(brw_acc_reg(8), BRW_REGISTER_TYPE_NF
);
819 struct brw_reg dwP
= suboffset(interp
, 0);
820 struct brw_reg dwQ
= suboffset(interp
, 1);
821 struct brw_reg dwR
= suboffset(interp
, 3);
823 brw_push_insn_state(p
);
824 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
826 if (inst
->exec_size
== 8) {
827 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
828 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_y
, 0), dwQ
);
830 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
832 /* brw_set_default_saturate() is called before emitting instructions,
833 * so the saturate bit is set in each instruction, so we need to unset
834 * it on the first instruction of each pair.
836 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
838 brw_set_default_group(p
, inst
->group
);
839 i
[0] = brw_MAD(p
, acc
, dwR
, offset(delta_x
, 0), dwP
);
840 i
[1] = brw_MAD(p
, offset(dst
, 0), acc
, offset(delta_x
, 1), dwQ
);
842 brw_set_default_group(p
, inst
->group
+ 8);
843 i
[2] = brw_MAD(p
, acc
, dwR
, offset(delta_y
, 0), dwP
);
844 i
[3] = brw_MAD(p
, offset(dst
, 1), acc
, offset(delta_y
, 1), dwQ
);
846 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
847 brw_inst_set_cond_modifier(p
->devinfo
, i
[3], inst
->conditional_mod
);
849 /* brw_set_default_saturate() is called before emitting instructions,
850 * so the saturate bit is set in each instruction, so we need to unset
851 * it on the first instruction of each pair.
853 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
854 brw_inst_set_saturate(p
->devinfo
, i
[2], false);
857 brw_pop_insn_state(p
);
860 } else if (devinfo
->has_pln
) {
861 if (devinfo
->gen
<= 6 && (delta_x
.nr
& 1) != 0) {
862 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
864 * "[DevSNB]:<src1> must be even register aligned.
866 * This restriction is lifted on Ivy Bridge.
868 * This means that we need to split PLN into LINE+MAC on-the-fly.
869 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
870 * we have to split into SIMD8 pieces. For gen4 (!has_pln), the
871 * coordinate registers are laid out differently so we leave it as a
872 * SIMD16 instruction.
874 assert(inst
->exec_size
== 8 || inst
->exec_size
== 16);
875 assert(inst
->group
% 16 == 0);
877 brw_push_insn_state(p
);
878 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
880 /* Thanks to two accumulators, we can emit all the LINEs and then all
881 * the MACs. This improves parallelism a bit.
883 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
884 brw_inst
*line
= brw_LINE(p
, brw_null_reg(), interp
,
885 offset(delta_x
, g
* 2));
886 brw_inst_set_group(devinfo
, line
, inst
->group
+ g
* 8);
888 /* LINE writes the accumulator automatically on gen4-5. On Sandy
889 * Bridge and later, we have to explicitly enable it.
891 if (devinfo
->gen
>= 6)
892 brw_inst_set_acc_wr_control(p
->devinfo
, line
, true);
894 /* brw_set_default_saturate() is called before emitting
895 * instructions, so the saturate bit is set in each instruction,
896 * so we need to unset it on the LINE instructions.
898 brw_inst_set_saturate(p
->devinfo
, line
, false);
901 for (unsigned g
= 0; g
< inst
->exec_size
/ 8; g
++) {
902 brw_inst
*mac
= brw_MAC(p
, offset(dst
, g
), suboffset(interp
, 1),
903 offset(delta_x
, g
* 2 + 1));
904 brw_inst_set_group(devinfo
, mac
, inst
->group
+ g
* 8);
905 brw_inst_set_cond_modifier(p
->devinfo
, mac
, inst
->conditional_mod
);
908 brw_pop_insn_state(p
);
912 brw_PLN(p
, dst
, interp
, delta_x
);
917 i
[0] = brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
918 i
[1] = brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
920 brw_inst_set_cond_modifier(p
->devinfo
, i
[1], inst
->conditional_mod
);
922 /* brw_set_default_saturate() is called before emitting instructions, so
923 * the saturate bit is set in each instruction, so we need to unset it on
924 * the first instruction.
926 brw_inst_set_saturate(p
->devinfo
, i
[0], false);
933 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
936 struct brw_reg surf_index
)
938 assert(devinfo
->gen
>= 7);
939 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
944 switch (inst
->exec_size
) {
946 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
949 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
952 unreachable("Invalid width for texture instruction");
955 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
961 retype(dst
, BRW_REGISTER_TYPE_UW
),
966 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
967 rlen
, /* response length */
969 inst
->header_size
> 0,
971 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
975 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
,
976 struct brw_reg surface_index
,
977 struct brw_reg sampler_index
)
979 assert(devinfo
->gen
< 7);
980 assert(inst
->size_written
% REG_SIZE
== 0);
983 uint32_t return_format
;
984 bool is_combined_send
= inst
->eot
;
986 /* Sampler EOT message of less than the dispatch width would kill the
987 * thread prematurely.
989 assert(!is_combined_send
|| inst
->exec_size
== dispatch_width
);
992 case BRW_REGISTER_TYPE_D
:
993 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
995 case BRW_REGISTER_TYPE_UD
:
996 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
999 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1003 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
1004 * is set as part of the message descriptor. On gen4, the PRM seems to
1005 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
1006 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
1007 * gone from the message descriptor entirely and you just get UINT32 all
1008 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
1009 * just stomp it to UINT32 all the time.
1011 if (inst
->opcode
== SHADER_OPCODE_TXS
)
1012 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
1014 switch (inst
->exec_size
) {
1016 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1019 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1022 unreachable("Invalid width for texture instruction");
1025 if (devinfo
->gen
>= 5) {
1026 switch (inst
->opcode
) {
1027 case SHADER_OPCODE_TEX
:
1028 if (inst
->shadow_compare
) {
1029 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
1031 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
1035 if (inst
->shadow_compare
) {
1036 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
1038 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
1041 case SHADER_OPCODE_TXL
:
1042 if (inst
->shadow_compare
) {
1043 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
1045 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
1048 case SHADER_OPCODE_TXS
:
1049 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
1051 case SHADER_OPCODE_TXD
:
1052 assert(!inst
->shadow_compare
);
1053 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
1055 case SHADER_OPCODE_TXF
:
1056 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1058 case SHADER_OPCODE_TXF_CMS
:
1059 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1061 case SHADER_OPCODE_LOD
:
1062 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
1064 case SHADER_OPCODE_TG4
:
1065 assert(devinfo
->gen
== 6);
1066 assert(!inst
->shadow_compare
);
1067 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
1069 case SHADER_OPCODE_SAMPLEINFO
:
1070 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
1073 unreachable("not reached");
1076 switch (inst
->opcode
) {
1077 case SHADER_OPCODE_TEX
:
1078 /* Note that G45 and older determines shadow compare and dispatch width
1079 * from message length for most messages.
1081 if (inst
->exec_size
== 8) {
1082 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1083 if (inst
->shadow_compare
) {
1084 assert(inst
->mlen
== 6);
1086 assert(inst
->mlen
<= 4);
1089 if (inst
->shadow_compare
) {
1090 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
1091 assert(inst
->mlen
== 9);
1093 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
1094 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
1099 if (inst
->shadow_compare
) {
1100 assert(inst
->exec_size
== 8);
1101 assert(inst
->mlen
== 6);
1102 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
1104 assert(inst
->mlen
== 9);
1105 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
1106 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1109 case SHADER_OPCODE_TXL
:
1110 if (inst
->shadow_compare
) {
1111 assert(inst
->exec_size
== 8);
1112 assert(inst
->mlen
== 6);
1113 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
1115 assert(inst
->mlen
== 9);
1116 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
1117 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1120 case SHADER_OPCODE_TXD
:
1121 /* There is no sample_d_c message; comparisons are done manually */
1122 assert(inst
->exec_size
== 8);
1123 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
1124 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
1126 case SHADER_OPCODE_TXF
:
1127 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
1128 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1129 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1131 case SHADER_OPCODE_TXS
:
1132 assert(inst
->mlen
== 3);
1133 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
1134 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1137 unreachable("not reached");
1140 assert(msg_type
!= -1);
1142 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
1146 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
1148 /* Load the message header if present. If there's a texture offset,
1149 * we need to set it up explicitly and load the offset bitfield.
1150 * Otherwise, we can use an implied move from g0 to the first message reg.
1152 struct brw_reg src
= brw_null_reg();
1153 if (inst
->header_size
!= 0) {
1154 if (devinfo
->gen
< 6 && !inst
->offset
) {
1155 /* Set up an implied move from g0 to the MRF. */
1156 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1158 assert(inst
->base_mrf
!= -1);
1159 struct brw_reg header_reg
= brw_message_reg(inst
->base_mrf
);
1161 brw_push_insn_state(p
);
1162 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1163 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1164 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1165 /* Explicitly set up the message header by copying g0 to the MRF. */
1166 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
1168 brw_set_default_exec_size(p
, BRW_EXECUTE_1
);
1170 /* Set the offset bits in DWord 2. */
1171 brw_MOV(p
, get_element_ud(header_reg
, 2),
1172 brw_imm_ud(inst
->offset
));
1175 brw_pop_insn_state(p
);
1179 uint32_t base_binding_table_index
;
1180 switch (inst
->opcode
) {
1181 case SHADER_OPCODE_TG4
:
1182 base_binding_table_index
= prog_data
->binding_table
.gather_texture_start
;
1185 base_binding_table_index
= prog_data
->binding_table
.texture_start
;
1189 assert(surface_index
.file
== BRW_IMMEDIATE_VALUE
);
1190 assert(sampler_index
.file
== BRW_IMMEDIATE_VALUE
);
1193 retype(dst
, BRW_REGISTER_TYPE_UW
),
1196 surface_index
.ud
+ base_binding_table_index
,
1197 sampler_index
.ud
% 16,
1199 inst
->size_written
/ REG_SIZE
,
1201 inst
->header_size
!= 0,
1207 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1210 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1212 * Ideally, we want to produce:
1215 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1216 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1217 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1218 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1219 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1220 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1221 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1222 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1224 * and add another set of two more subspans if in 16-pixel dispatch mode.
1226 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1227 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1228 * pair. But the ideal approximation may impose a huge performance cost on
1229 * sample_d. On at least Haswell, sample_d instruction does some
1230 * optimizations if the same LOD is used for all pixels in the subspan.
1232 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1233 * appropriate swizzling.
1236 fs_generator::generate_ddx(const fs_inst
*inst
,
1237 struct brw_reg dst
, struct brw_reg src
)
1239 unsigned vstride
, width
;
1241 if (inst
->opcode
== FS_OPCODE_DDX_FINE
) {
1242 /* produce accurate derivatives */
1243 vstride
= BRW_VERTICAL_STRIDE_2
;
1244 width
= BRW_WIDTH_2
;
1246 /* replicate the derivative at the top-left pixel to other pixels */
1247 vstride
= BRW_VERTICAL_STRIDE_4
;
1248 width
= BRW_WIDTH_4
;
1251 struct brw_reg src0
= src
;
1252 struct brw_reg src1
= src
;
1254 src0
.subnr
= sizeof(float);
1255 src0
.vstride
= vstride
;
1257 src0
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1258 src1
.vstride
= vstride
;
1260 src1
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1262 brw_ADD(p
, dst
, src0
, negate(src1
));
1265 /* The negate_value boolean is used to negate the derivative computation for
1266 * FBOs, since they place the origin at the upper left instead of the lower
1270 fs_generator::generate_ddy(const fs_inst
*inst
,
1271 struct brw_reg dst
, struct brw_reg src
)
1273 if (inst
->opcode
== FS_OPCODE_DDY_FINE
) {
1274 /* produce accurate derivatives */
1275 if (devinfo
->gen
>= 11) {
1276 src
= stride(src
, 0, 2, 1);
1277 struct brw_reg src_0
= byte_offset(src
, 0 * sizeof(float));
1278 struct brw_reg src_2
= byte_offset(src
, 2 * sizeof(float));
1279 struct brw_reg src_4
= byte_offset(src
, 4 * sizeof(float));
1280 struct brw_reg src_6
= byte_offset(src
, 6 * sizeof(float));
1281 struct brw_reg src_8
= byte_offset(src
, 8 * sizeof(float));
1282 struct brw_reg src_10
= byte_offset(src
, 10 * sizeof(float));
1283 struct brw_reg src_12
= byte_offset(src
, 12 * sizeof(float));
1284 struct brw_reg src_14
= byte_offset(src
, 14 * sizeof(float));
1286 struct brw_reg dst_0
= byte_offset(dst
, 0 * sizeof(float));
1287 struct brw_reg dst_4
= byte_offset(dst
, 4 * sizeof(float));
1288 struct brw_reg dst_8
= byte_offset(dst
, 8 * sizeof(float));
1289 struct brw_reg dst_12
= byte_offset(dst
, 12 * sizeof(float));
1291 brw_push_insn_state(p
);
1292 brw_set_default_exec_size(p
, BRW_EXECUTE_4
);
1294 brw_ADD(p
, dst_0
, negate(src_0
), src_2
);
1295 brw_ADD(p
, dst_4
, negate(src_4
), src_6
);
1297 if (inst
->exec_size
== 16) {
1298 brw_ADD(p
, dst_8
, negate(src_8
), src_10
);
1299 brw_ADD(p
, dst_12
, negate(src_12
), src_14
);
1302 brw_pop_insn_state(p
);
1304 struct brw_reg src0
= stride(src
, 4, 4, 1);
1305 struct brw_reg src1
= stride(src
, 4, 4, 1);
1306 src0
.swizzle
= BRW_SWIZZLE_XYXY
;
1307 src1
.swizzle
= BRW_SWIZZLE_ZWZW
;
1309 brw_push_insn_state(p
);
1310 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1311 brw_ADD(p
, dst
, negate(src0
), src1
);
1312 brw_pop_insn_state(p
);
1315 /* replicate the derivative at the top-left pixel to other pixels */
1316 struct brw_reg src0
= stride(src
, 4, 4, 0);
1317 struct brw_reg src1
= stride(src
, 4, 4, 0);
1318 src0
.subnr
= 0 * sizeof(float);
1319 src1
.subnr
= 2 * sizeof(float);
1321 brw_ADD(p
, dst
, negate(src0
), src1
);
1326 fs_generator::generate_discard_jump(fs_inst
*)
1328 assert(devinfo
->gen
>= 6);
1330 /* This HALT will be patched up at FB write time to point UIP at the end of
1331 * the program, and at brw_uip_jip() JIP will be set to the end of the
1332 * current block (or the program).
1334 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1339 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1341 /* The 32-wide messages only respect the first 16-wide half of the channel
1342 * enable signals which are replicated identically for the second group of
1343 * 16 channels, so we cannot use them unless the write is marked
1344 * force_writemask_all.
1346 const unsigned lower_size
= inst
->force_writemask_all
? inst
->exec_size
:
1347 MIN2(16, inst
->exec_size
);
1348 const unsigned block_size
= 4 * lower_size
/ REG_SIZE
;
1349 assert(inst
->mlen
!= 0);
1351 brw_push_insn_state(p
);
1352 brw_set_default_exec_size(p
, cvt(lower_size
) - 1);
1353 brw_set_default_compression(p
, lower_size
> 8);
1355 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1356 brw_set_default_group(p
, inst
->group
+ lower_size
* i
);
1358 brw_MOV(p
, brw_uvec_mrf(lower_size
, inst
->base_mrf
+ 1, 0),
1359 retype(offset(src
, block_size
* i
), BRW_REGISTER_TYPE_UD
));
1361 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1363 inst
->offset
+ block_size
* REG_SIZE
* i
);
1366 brw_pop_insn_state(p
);
1370 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1372 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1373 assert(inst
->mlen
!= 0);
1375 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1376 inst
->exec_size
/ 8, inst
->offset
);
1380 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1382 assert(inst
->exec_size
<= 16 || inst
->force_writemask_all
);
1384 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1388 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1390 struct brw_reg index
,
1391 struct brw_reg offset
)
1393 assert(type_sz(dst
.type
) == 4);
1394 assert(inst
->mlen
!= 0);
1396 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1397 index
.type
== BRW_REGISTER_TYPE_UD
);
1398 uint32_t surf_index
= index
.ud
;
1400 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1401 offset
.type
== BRW_REGISTER_TYPE_UD
);
1402 uint32_t read_offset
= offset
.ud
;
1404 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1405 read_offset
, surf_index
);
1409 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1411 struct brw_reg index
,
1412 struct brw_reg payload
)
1414 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1415 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1416 assert(type_sz(dst
.type
) == 4);
1418 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1419 const uint32_t surf_index
= index
.ud
;
1421 brw_push_insn_state(p
);
1422 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1423 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1424 brw_pop_insn_state(p
);
1426 brw_inst_set_sfid(devinfo
, send
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
);
1427 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UD
));
1428 brw_set_src0(p
, send
, retype(payload
, BRW_REGISTER_TYPE_UD
));
1429 brw_set_desc(p
, send
,
1430 brw_message_desc(devinfo
, 1, DIV_ROUND_UP(inst
->size_written
,
1432 brw_dp_read_desc(devinfo
, surf_index
,
1433 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1434 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1435 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1438 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1440 brw_push_insn_state(p
);
1441 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1443 /* a0.0 = surf_index & 0xff */
1444 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1445 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1446 brw_set_dest(p
, insn_and
, addr
);
1447 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1448 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1450 /* dst = send(payload, a0.0 | <descriptor>) */
1451 brw_send_indirect_message(
1452 p
, GEN6_SFID_DATAPORT_CONSTANT_CACHE
,
1453 retype(dst
, BRW_REGISTER_TYPE_UD
),
1454 retype(payload
, BRW_REGISTER_TYPE_UD
), addr
,
1455 brw_message_desc(devinfo
, 1,
1456 DIV_ROUND_UP(inst
->size_written
, REG_SIZE
), true) |
1457 brw_dp_read_desc(devinfo
, 0 /* surface */,
1458 BRW_DATAPORT_OWORD_BLOCK_DWORDS(inst
->exec_size
),
1459 GEN7_DATAPORT_DC_OWORD_BLOCK_READ
,
1460 BRW_DATAPORT_READ_TARGET_DATA_CACHE
));
1462 brw_pop_insn_state(p
);
1467 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst
*inst
,
1469 struct brw_reg index
)
1471 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1472 assert(inst
->header_size
!= 0);
1475 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1476 index
.type
== BRW_REGISTER_TYPE_UD
);
1477 uint32_t surf_index
= index
.ud
;
1479 uint32_t simd_mode
, rlen
, msg_type
;
1480 if (inst
->exec_size
== 16) {
1481 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1484 assert(inst
->exec_size
== 8);
1485 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1489 if (devinfo
->gen
>= 5)
1490 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1492 /* We always use the SIMD16 message so that we only have to load U, and
1495 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1496 assert(inst
->mlen
== 3);
1497 assert(inst
->size_written
== 8 * REG_SIZE
);
1499 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1502 struct brw_reg header
= brw_vec8_grf(0, 0);
1503 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1505 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1506 brw_inst_set_compression(devinfo
, send
, false);
1507 brw_inst_set_sfid(devinfo
, send
, BRW_SFID_SAMPLER
);
1508 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1509 brw_set_src0(p
, send
, header
);
1510 if (devinfo
->gen
< 6)
1511 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1513 /* Our surface is set up as floats, regardless of what actual data is
1516 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1517 brw_set_desc(p
, send
,
1518 brw_message_desc(devinfo
, inst
->mlen
, rlen
, inst
->header_size
) |
1519 brw_sampler_desc(devinfo
, surf_index
,
1520 0, /* sampler (unused) */
1521 msg_type
, simd_mode
, return_format
));
1525 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1528 struct brw_reg msg_data
,
1531 const bool has_payload
= inst
->src
[0].file
!= BAD_FILE
;
1532 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1533 assert(inst
->size_written
% REG_SIZE
== 0);
1535 brw_pixel_interpolator_query(p
,
1536 retype(dst
, BRW_REGISTER_TYPE_UW
),
1537 /* If we don't have a payload, what we send doesn't matter */
1538 has_payload
? src
: brw_vec8_grf(0, 0),
1539 inst
->pi_noperspective
,
1542 has_payload
? 2 * inst
->exec_size
/ 8 : 1,
1543 inst
->size_written
/ REG_SIZE
);
1546 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1547 * the ADD instruction.
1550 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1552 struct brw_reg src0
,
1553 struct brw_reg src1
)
1555 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1556 dst
.type
== BRW_REGISTER_TYPE_UD
);
1557 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1558 src0
.type
== BRW_REGISTER_TYPE_UD
);
1560 const struct brw_reg reg
= stride(src1
, 1, 4, 0);
1561 const unsigned lower_size
= MIN2(inst
->exec_size
,
1562 devinfo
->gen
>= 8 ? 16 : 8);
1564 for (unsigned i
= 0; i
< inst
->exec_size
/ lower_size
; i
++) {
1565 brw_inst
*insn
= brw_ADD(p
, offset(dst
, i
* lower_size
/ 8),
1566 offset(src0
, (src0
.vstride
== 0 ? 0 : (1 << (src0
.vstride
- 1)) *
1567 (i
* lower_size
/ (1 << src0
.width
))) *
1568 type_sz(src0
.type
) / REG_SIZE
),
1569 suboffset(reg
, i
* lower_size
/ 4));
1570 brw_inst_set_exec_size(devinfo
, insn
, cvt(lower_size
) - 1);
1571 brw_inst_set_group(devinfo
, insn
, inst
->group
+ lower_size
* i
);
1572 brw_inst_set_compression(devinfo
, insn
, lower_size
> 8);
1577 fs_generator::generate_pack_half_2x16_split(fs_inst
*,
1582 assert(devinfo
->gen
>= 7);
1583 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1584 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1585 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1587 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1589 * Because this instruction does not have a 16-bit floating-point type,
1590 * the destination data type must be Word (W).
1592 * The destination must be DWord-aligned and specify a horizontal stride
1593 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1594 * each destination channel and the upper word is not modified.
1596 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1598 /* Give each 32-bit channel of dst the form below, where "." means
1602 brw_F32TO16(p
, dst_w
, y
);
1607 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1609 /* And, finally the form of packHalf2x16's output:
1612 brw_F32TO16(p
, dst_w
, x
);
1616 fs_generator::generate_shader_time_add(fs_inst
*,
1617 struct brw_reg payload
,
1618 struct brw_reg offset
,
1619 struct brw_reg value
)
1621 assert(devinfo
->gen
>= 7);
1622 brw_push_insn_state(p
);
1623 brw_set_default_mask_control(p
, true);
1625 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1626 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1628 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1631 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1632 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1633 value
.width
= BRW_WIDTH_1
;
1634 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1635 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1637 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1640 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1641 * case, and we don't really care about squeezing every bit of performance
1642 * out of this path, so we just emit the MOVs from here.
1644 brw_MOV(p
, payload_offset
, offset
);
1645 brw_MOV(p
, payload_value
, value
);
1646 brw_shader_time_add(p
, payload
,
1647 prog_data
->binding_table
.shader_time_start
);
1648 brw_pop_insn_state(p
);
1652 fs_generator::enable_debug(const char *shader_name
)
1655 this->shader_name
= shader_name
;
1659 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1661 /* align to 64 byte boundary. */
1662 while (p
->next_insn_offset
% 64)
1665 this->dispatch_width
= dispatch_width
;
1667 int start_offset
= p
->next_insn_offset
;
1668 int spill_count
= 0, fill_count
= 0;
1671 struct disasm_info
*disasm_info
= disasm_initialize(devinfo
, cfg
);
1673 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1674 struct brw_reg src
[4], dst
;
1675 unsigned int last_insn_offset
= p
->next_insn_offset
;
1676 bool multiple_instructions_emitted
= false;
1678 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1679 * "Register Region Restrictions" section: for BDW, SKL:
1681 * "A POW/FDIV operation must not be followed by an instruction
1682 * that requires two destination registers."
1684 * The documentation is often lacking annotations for Atom parts,
1685 * and empirically this affects CHV as well.
1687 if (devinfo
->gen
>= 8 &&
1688 devinfo
->gen
<= 9 &&
1690 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1691 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1692 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1694 last_insn_offset
= p
->next_insn_offset
;
1697 if (unlikely(debug_flag
))
1698 disasm_annotate(disasm_info
, inst
, p
->next_insn_offset
);
1700 /* If the instruction writes to more than one register, it needs to be
1701 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1702 * hardware figures out by itself what the right compression mode is,
1703 * but we still need to know whether the instruction is compressed to
1704 * set up the source register regions appropriately.
1706 * XXX - This is wrong for instructions that write a single register but
1707 * read more than one which should strictly speaking be treated as
1708 * compressed. For instructions that don't write any registers it
1709 * relies on the destination being a null register of the correct
1710 * type and regioning so the instruction is considered compressed
1711 * or not accordingly.
1713 const bool compressed
=
1714 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
;
1715 brw_set_default_compression(p
, compressed
);
1716 brw_set_default_group(p
, inst
->group
);
1718 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1719 src
[i
] = brw_reg_from_fs_reg(devinfo
, inst
,
1720 &inst
->src
[i
], compressed
);
1721 /* The accumulator result appears to get used for the
1722 * conditional modifier generation. When negating a UD
1723 * value, there is a 33rd bit generated for the sign in the
1724 * accumulator value, so now you can't check, for example,
1725 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1727 assert(!inst
->conditional_mod
||
1728 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1729 !inst
->src
[i
].negate
);
1731 dst
= brw_reg_from_fs_reg(devinfo
, inst
,
1732 &inst
->dst
, compressed
);
1734 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1735 brw_set_default_predicate_control(p
, inst
->predicate
);
1736 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1737 /* On gen7 and above, hardware automatically adds the group onto the
1738 * flag subregister number. On Sandy Bridge and older, we have to do it
1741 const unsigned flag_subreg
= inst
->flag_subreg
+
1742 (devinfo
->gen
>= 7 ? 0 : inst
->group
/ 16);
1743 brw_set_default_flag_reg(p
, flag_subreg
/ 2, flag_subreg
% 2);
1744 brw_set_default_saturate(p
, inst
->saturate
);
1745 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1746 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1748 unsigned exec_size
= inst
->exec_size
;
1749 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1750 (get_exec_type_size(inst
) == 8 || type_sz(inst
->dst
.type
) == 8)) {
1754 brw_set_default_exec_size(p
, cvt(exec_size
) - 1);
1756 assert(inst
->force_writemask_all
|| inst
->exec_size
>= 4);
1757 assert(inst
->force_writemask_all
|| inst
->group
% inst
->exec_size
== 0);
1758 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1759 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1761 switch (inst
->opcode
) {
1762 case BRW_OPCODE_MOV
:
1763 brw_MOV(p
, dst
, src
[0]);
1765 case BRW_OPCODE_ADD
:
1766 brw_ADD(p
, dst
, src
[0], src
[1]);
1768 case BRW_OPCODE_MUL
:
1769 brw_MUL(p
, dst
, src
[0], src
[1]);
1771 case BRW_OPCODE_AVG
:
1772 brw_AVG(p
, dst
, src
[0], src
[1]);
1774 case BRW_OPCODE_MACH
:
1775 brw_MACH(p
, dst
, src
[0], src
[1]);
1778 case BRW_OPCODE_LINE
:
1779 brw_LINE(p
, dst
, src
[0], src
[1]);
1782 case BRW_OPCODE_MAD
:
1783 assert(devinfo
->gen
>= 6);
1784 if (devinfo
->gen
< 10)
1785 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1786 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1789 case BRW_OPCODE_LRP
:
1790 assert(devinfo
->gen
>= 6 && devinfo
->gen
<= 10);
1791 if (devinfo
->gen
< 10)
1792 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1793 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1796 case BRW_OPCODE_FRC
:
1797 brw_FRC(p
, dst
, src
[0]);
1799 case BRW_OPCODE_RNDD
:
1800 brw_RNDD(p
, dst
, src
[0]);
1802 case BRW_OPCODE_RNDE
:
1803 brw_RNDE(p
, dst
, src
[0]);
1805 case BRW_OPCODE_RNDZ
:
1806 brw_RNDZ(p
, dst
, src
[0]);
1809 case BRW_OPCODE_AND
:
1810 brw_AND(p
, dst
, src
[0], src
[1]);
1813 brw_OR(p
, dst
, src
[0], src
[1]);
1815 case BRW_OPCODE_XOR
:
1816 brw_XOR(p
, dst
, src
[0], src
[1]);
1818 case BRW_OPCODE_NOT
:
1819 brw_NOT(p
, dst
, src
[0]);
1821 case BRW_OPCODE_ASR
:
1822 brw_ASR(p
, dst
, src
[0], src
[1]);
1824 case BRW_OPCODE_SHR
:
1825 brw_SHR(p
, dst
, src
[0], src
[1]);
1827 case BRW_OPCODE_SHL
:
1828 brw_SHL(p
, dst
, src
[0], src
[1]);
1830 case BRW_OPCODE_F32TO16
:
1831 assert(devinfo
->gen
>= 7);
1832 brw_F32TO16(p
, dst
, src
[0]);
1834 case BRW_OPCODE_F16TO32
:
1835 assert(devinfo
->gen
>= 7);
1836 brw_F16TO32(p
, dst
, src
[0]);
1838 case BRW_OPCODE_CMP
:
1839 if (inst
->exec_size
>= 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
1840 dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1841 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1842 * implemented in the compiler is not sufficient. Overriding the
1843 * type when the destination is the null register is necessary but
1844 * not sufficient by itself.
1846 assert(dst
.nr
== BRW_ARF_NULL
);
1847 dst
.type
= BRW_REGISTER_TYPE_D
;
1849 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1851 case BRW_OPCODE_SEL
:
1852 brw_SEL(p
, dst
, src
[0], src
[1]);
1854 case BRW_OPCODE_CSEL
:
1855 assert(devinfo
->gen
>= 8);
1856 if (devinfo
->gen
< 10)
1857 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1858 brw_CSEL(p
, dst
, src
[0], src
[1], src
[2]);
1860 case BRW_OPCODE_BFREV
:
1861 assert(devinfo
->gen
>= 7);
1862 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1863 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1865 case BRW_OPCODE_FBH
:
1866 assert(devinfo
->gen
>= 7);
1867 brw_FBH(p
, retype(dst
, src
[0].type
), src
[0]);
1869 case BRW_OPCODE_FBL
:
1870 assert(devinfo
->gen
>= 7);
1871 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1872 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1874 case BRW_OPCODE_LZD
:
1875 brw_LZD(p
, dst
, src
[0]);
1877 case BRW_OPCODE_CBIT
:
1878 assert(devinfo
->gen
>= 7);
1879 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1880 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1882 case BRW_OPCODE_ADDC
:
1883 assert(devinfo
->gen
>= 7);
1884 brw_ADDC(p
, dst
, src
[0], src
[1]);
1886 case BRW_OPCODE_SUBB
:
1887 assert(devinfo
->gen
>= 7);
1888 brw_SUBB(p
, dst
, src
[0], src
[1]);
1890 case BRW_OPCODE_MAC
:
1891 brw_MAC(p
, dst
, src
[0], src
[1]);
1894 case BRW_OPCODE_BFE
:
1895 assert(devinfo
->gen
>= 7);
1896 if (devinfo
->gen
< 10)
1897 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1898 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1901 case BRW_OPCODE_BFI1
:
1902 assert(devinfo
->gen
>= 7);
1903 brw_BFI1(p
, dst
, src
[0], src
[1]);
1905 case BRW_OPCODE_BFI2
:
1906 assert(devinfo
->gen
>= 7);
1907 if (devinfo
->gen
< 10)
1908 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1909 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
1913 if (inst
->src
[0].file
!= BAD_FILE
) {
1914 /* The instruction has an embedded compare (only allowed on gen6) */
1915 assert(devinfo
->gen
== 6);
1916 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
1918 brw_IF(p
, brw_get_default_exec_size(p
));
1922 case BRW_OPCODE_ELSE
:
1925 case BRW_OPCODE_ENDIF
:
1930 brw_DO(p
, brw_get_default_exec_size(p
));
1933 case BRW_OPCODE_BREAK
:
1936 case BRW_OPCODE_CONTINUE
:
1940 case BRW_OPCODE_WHILE
:
1945 case SHADER_OPCODE_RCP
:
1946 case SHADER_OPCODE_RSQ
:
1947 case SHADER_OPCODE_SQRT
:
1948 case SHADER_OPCODE_EXP2
:
1949 case SHADER_OPCODE_LOG2
:
1950 case SHADER_OPCODE_SIN
:
1951 case SHADER_OPCODE_COS
:
1952 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1953 if (devinfo
->gen
>= 6) {
1954 assert(inst
->mlen
== 0);
1955 assert(devinfo
->gen
>= 7 || inst
->exec_size
== 8);
1956 gen6_math(p
, dst
, brw_math_function(inst
->opcode
),
1957 src
[0], brw_null_reg());
1959 assert(inst
->mlen
>= 1);
1960 assert(devinfo
->gen
== 5 || devinfo
->is_g4x
|| inst
->exec_size
== 8);
1962 brw_math_function(inst
->opcode
),
1963 inst
->base_mrf
, src
[0],
1964 BRW_MATH_PRECISION_FULL
);
1967 case SHADER_OPCODE_INT_QUOTIENT
:
1968 case SHADER_OPCODE_INT_REMAINDER
:
1969 case SHADER_OPCODE_POW
:
1970 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
1971 if (devinfo
->gen
>= 6) {
1972 assert(inst
->mlen
== 0);
1973 assert((devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) ||
1974 inst
->exec_size
== 8);
1975 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
1977 assert(inst
->mlen
>= 1);
1978 assert(inst
->exec_size
== 8);
1979 gen4_math(p
, dst
, brw_math_function(inst
->opcode
),
1980 inst
->base_mrf
, src
[0],
1981 BRW_MATH_PRECISION_FULL
);
1984 case FS_OPCODE_LINTERP
:
1985 multiple_instructions_emitted
= generate_linterp(inst
, dst
, src
);
1987 case FS_OPCODE_PIXEL_X
:
1988 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1989 src
[0].subnr
= 0 * type_sz(src
[0].type
);
1990 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1992 case FS_OPCODE_PIXEL_Y
:
1993 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
1994 src
[0].subnr
= 4 * type_sz(src
[0].type
);
1995 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
1998 case SHADER_OPCODE_SEND
:
1999 generate_send(inst
, dst
, src
[0], src
[1], src
[2],
2000 inst
->ex_mlen
> 0 ? src
[3] : brw_null_reg());
2003 case SHADER_OPCODE_GET_BUFFER_SIZE
:
2004 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2006 case SHADER_OPCODE_TEX
:
2008 case SHADER_OPCODE_TXD
:
2009 case SHADER_OPCODE_TXF
:
2010 case SHADER_OPCODE_TXF_CMS
:
2011 case SHADER_OPCODE_TXL
:
2012 case SHADER_OPCODE_TXS
:
2013 case SHADER_OPCODE_LOD
:
2014 case SHADER_OPCODE_TG4
:
2015 case SHADER_OPCODE_SAMPLEINFO
:
2016 assert(inst
->src
[0].file
== BAD_FILE
);
2017 generate_tex(inst
, dst
, src
[1], src
[2]);
2020 case FS_OPCODE_DDX_COARSE
:
2021 case FS_OPCODE_DDX_FINE
:
2022 generate_ddx(inst
, dst
, src
[0]);
2024 case FS_OPCODE_DDY_COARSE
:
2025 case FS_OPCODE_DDY_FINE
:
2026 generate_ddy(inst
, dst
, src
[0]);
2029 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2030 generate_scratch_write(inst
, src
[0]);
2034 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2035 generate_scratch_read(inst
, dst
);
2039 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2040 generate_scratch_read_gen7(inst
, dst
);
2044 case SHADER_OPCODE_MOV_INDIRECT
:
2045 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2048 case SHADER_OPCODE_URB_READ_SIMD8
:
2049 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2050 generate_urb_read(inst
, dst
, src
[0]);
2053 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2054 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2055 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2056 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2057 generate_urb_write(inst
, src
[0]);
2060 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2061 assert(inst
->force_writemask_all
);
2062 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2065 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2066 assert(inst
->force_writemask_all
);
2067 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2070 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
2071 generate_varying_pull_constant_load_gen4(inst
, dst
, src
[0]);
2074 case FS_OPCODE_REP_FB_WRITE
:
2075 case FS_OPCODE_FB_WRITE
:
2076 generate_fb_write(inst
, src
[0]);
2079 case FS_OPCODE_FB_READ
:
2080 generate_fb_read(inst
, dst
, src
[0]);
2083 case FS_OPCODE_DISCARD_JUMP
:
2084 generate_discard_jump(inst
);
2087 case SHADER_OPCODE_SHADER_TIME_ADD
:
2088 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2091 case SHADER_OPCODE_MEMORY_FENCE
:
2092 brw_memory_fence(p
, dst
, BRW_OPCODE_SEND
);
2095 case SHADER_OPCODE_INTERLOCK
:
2096 /* The interlock is basically a memory fence issued via sendc */
2097 brw_memory_fence(p
, dst
, BRW_OPCODE_SENDC
);
2100 case SHADER_OPCODE_FIND_LIVE_CHANNEL
: {
2101 const struct brw_reg mask
=
2102 brw_stage_has_packed_dispatch(devinfo
, stage
,
2103 prog_data
) ? brw_imm_ud(~0u) :
2104 stage
== MESA_SHADER_FRAGMENT
? brw_vmask_reg() :
2106 brw_find_live_channel(p
, dst
, mask
);
2110 case SHADER_OPCODE_BROADCAST
:
2111 assert(inst
->force_writemask_all
);
2112 brw_broadcast(p
, dst
, src
[0], src
[1]);
2115 case SHADER_OPCODE_SHUFFLE
:
2116 generate_shuffle(inst
, dst
, src
[0], src
[1]);
2119 case SHADER_OPCODE_SEL_EXEC
:
2120 assert(inst
->force_writemask_all
);
2121 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
2122 brw_MOV(p
, dst
, src
[1]);
2123 brw_set_default_mask_control(p
, BRW_MASK_ENABLE
);
2124 brw_MOV(p
, dst
, src
[0]);
2127 case SHADER_OPCODE_QUAD_SWIZZLE
:
2128 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2129 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2130 generate_quad_swizzle(inst
, dst
, src
[0], src
[1].ud
);
2133 case SHADER_OPCODE_CLUSTER_BROADCAST
: {
2134 assert(src
[0].type
== dst
.type
);
2135 assert(!src
[0].negate
&& !src
[0].abs
);
2136 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2137 assert(src
[1].type
== BRW_REGISTER_TYPE_UD
);
2138 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2139 assert(src
[2].type
== BRW_REGISTER_TYPE_UD
);
2140 const unsigned component
= src
[1].ud
;
2141 const unsigned cluster_size
= src
[2].ud
;
2142 struct brw_reg strided
= stride(suboffset(src
[0], component
),
2143 cluster_size
, cluster_size
, 0);
2144 if (type_sz(src
[0].type
) > 4 &&
2145 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
2146 /* IVB has an issue (which we found empirically) where it reads
2147 * two address register components per channel for indirectly
2148 * addressed 64-bit sources.
2150 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
2152 * "When source or destination datatype is 64b or operation is
2153 * integer DWord multiply, indirect addressing must not be
2156 * To work around both of these, we do two integer MOVs insead of
2157 * one 64-bit MOV. Because no double value should ever cross a
2158 * register boundary, it's safe to use the immediate offset in the
2159 * indirect here to handle adding 4 bytes to the offset and avoid
2160 * the extra ADD to the register file.
2162 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 0),
2163 subscript(strided
, BRW_REGISTER_TYPE_D
, 0));
2164 brw_MOV(p
, subscript(dst
, BRW_REGISTER_TYPE_D
, 1),
2165 subscript(strided
, BRW_REGISTER_TYPE_D
, 1));
2167 brw_MOV(p
, dst
, strided
);
2172 case FS_OPCODE_SET_SAMPLE_ID
:
2173 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2176 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2177 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2180 case FS_OPCODE_PLACEHOLDER_HALT
:
2181 /* This is the place where the final HALT needs to be inserted if
2182 * we've emitted any discards. If not, this will emit no code.
2184 if (!patch_discard_jumps_to_fb_writes()) {
2185 if (unlikely(debug_flag
)) {
2186 disasm_info
->use_tail
= true;
2191 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2192 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2193 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2196 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2197 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2198 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2201 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2202 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2203 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2206 case CS_OPCODE_CS_TERMINATE
:
2207 generate_cs_terminate(inst
, src
[0]);
2210 case SHADER_OPCODE_BARRIER
:
2211 generate_barrier(inst
, src
[0]);
2214 case BRW_OPCODE_DIM
:
2215 assert(devinfo
->is_haswell
);
2216 assert(src
[0].type
== BRW_REGISTER_TYPE_DF
);
2217 assert(dst
.type
== BRW_REGISTER_TYPE_DF
);
2218 brw_DIM(p
, dst
, retype(src
[0], BRW_REGISTER_TYPE_F
));
2221 case SHADER_OPCODE_RND_MODE
:
2222 assert(src
[0].file
== BRW_IMMEDIATE_VALUE
);
2223 brw_rounding_mode(p
, (brw_rnd_mode
) src
[0].d
);
2227 unreachable("Unsupported opcode");
2229 case SHADER_OPCODE_LOAD_PAYLOAD
:
2230 unreachable("Should be lowered by lower_load_payload()");
2233 if (multiple_instructions_emitted
)
2236 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2237 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2238 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2239 "emitting more than 1 instruction");
2241 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2243 if (inst
->conditional_mod
)
2244 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2245 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2246 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2250 brw_set_uip_jip(p
, start_offset
);
2252 /* end of program sentinel */
2253 disasm_new_inst_group(disasm_info
, p
->next_insn_offset
);
2258 if (unlikely(debug_flag
))
2260 brw_validate_instructions(devinfo
, p
->store
,
2262 p
->next_insn_offset
,
2265 int before_size
= p
->next_insn_offset
- start_offset
;
2266 brw_compact_instructions(p
, start_offset
, disasm_info
);
2267 int after_size
= p
->next_insn_offset
- start_offset
;
2269 if (unlikely(debug_flag
)) {
2270 fprintf(stderr
, "Native code for %s\n"
2271 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2272 " bytes (%.0f%%)\n",
2273 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2274 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2275 100.0f
* (before_size
- after_size
) / before_size
);
2277 dump_assembly(p
->store
, disasm_info
);
2279 ralloc_free(disasm_info
);
2282 compiler
->shader_debug_log(log_data
,
2283 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2284 "%d:%d spills:fills, Promoted %u constants, "
2285 "compacted %d to %d bytes.",
2286 _mesa_shader_stage_to_abbrev(stage
),
2287 dispatch_width
, before_size
/ 16,
2288 loop_count
, cfg
->cycle_count
, spill_count
,
2289 fill_count
, promoted_constants
, before_size
,
2292 return start_offset
;
2296 fs_generator::get_assembly()
2298 return brw_get_program(p
, &prog_data
->program_size
);