2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
) {
104 /* Add a uniform for the thread local id. It must be the last uniform
107 assert(uniforms
== prog_data
->nr_params
);
108 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
109 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
110 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
115 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
119 nir_foreach_instr(instr
, block
) {
120 if (instr
->type
!= nir_instr_type_intrinsic
)
123 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
124 switch (intrin
->intrinsic
) {
125 case nir_intrinsic_load_vertex_id
:
126 case nir_intrinsic_load_base_vertex
:
127 unreachable("should be lowered by nir_lower_system_values().");
129 case nir_intrinsic_load_vertex_id_zero_base
:
130 case nir_intrinsic_load_is_indexed_draw
:
131 case nir_intrinsic_load_first_vertex
:
132 case nir_intrinsic_load_instance_id
:
133 case nir_intrinsic_load_base_instance
:
134 case nir_intrinsic_load_draw_id
:
135 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
137 case nir_intrinsic_load_invocation_id
:
138 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
140 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
141 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
142 if (reg
->file
== BAD_FILE
) {
143 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
144 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
145 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
146 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
151 case nir_intrinsic_load_sample_pos
:
152 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
153 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
154 if (reg
->file
== BAD_FILE
)
155 *reg
= *v
->emit_samplepos_setup();
158 case nir_intrinsic_load_sample_id
:
159 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
160 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
161 if (reg
->file
== BAD_FILE
)
162 *reg
= *v
->emit_sampleid_setup();
165 case nir_intrinsic_load_sample_mask_in
:
166 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
167 assert(v
->devinfo
->gen
>= 7);
168 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
169 if (reg
->file
== BAD_FILE
)
170 *reg
= *v
->emit_samplemaskin_setup();
173 case nir_intrinsic_load_work_group_id
:
174 assert(v
->stage
== MESA_SHADER_COMPUTE
);
175 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
176 if (reg
->file
== BAD_FILE
)
177 *reg
= *v
->emit_cs_work_group_id_setup();
180 case nir_intrinsic_load_helper_invocation
:
181 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
182 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
183 if (reg
->file
== BAD_FILE
) {
184 const fs_builder abld
=
185 v
->bld
.annotate("gl_HelperInvocation", NULL
);
187 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
188 * pixel mask is in g1.7 of the thread payload.
190 * We move the per-channel pixel enable bit to the low bit of each
191 * channel by shifting the byte containing the pixel mask by the
192 * vector immediate 0x76543210UV.
194 * The region of <1,8,0> reads only 1 byte (the pixel masks for
195 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
196 * masks for 2 and 3) in SIMD16.
198 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
200 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
201 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
202 hbld
.SHR(offset(shifted
, hbld
, i
),
203 stride(retype(brw_vec1_grf(1 + i
, 7),
204 BRW_REGISTER_TYPE_UB
),
206 brw_imm_v(0x76543210));
209 /* A set bit in the pixel mask means the channel is enabled, but
210 * that is the opposite of gl_HelperInvocation so we need to invert
213 * The negate source-modifier bit of logical instructions on Gen8+
214 * performs 1's complement negation, so we can use that instead of
217 fs_reg inverted
= negate(shifted
);
218 if (v
->devinfo
->gen
< 8) {
219 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
220 abld
.NOT(inverted
, shifted
);
223 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
224 * with 1 and negating.
226 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
227 abld
.AND(anded
, inverted
, brw_imm_uw(1));
229 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
230 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
244 fs_visitor::nir_emit_system_values()
246 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
247 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
248 nir_system_values
[i
] = fs_reg();
251 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
252 * never end up using it.
255 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
256 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
257 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
259 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
260 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
261 if (dispatch_width
> 8)
262 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
263 if (dispatch_width
> 16) {
264 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
265 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
269 nir_foreach_function(function
, nir
) {
270 assert(strcmp(function
->name
, "main") == 0);
271 assert(function
->impl
);
272 nir_foreach_block(block
, function
->impl
) {
273 emit_system_values_block(block
, this);
279 * Returns a type based on a reference_type (word, float, half-float) and a
282 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
284 * @FIXME: 64-bit return types are always DF on integer types to maintain
285 * compability with uses of DF previously to the introduction of int64
289 brw_reg_type_from_bit_size(const unsigned bit_size
,
290 const brw_reg_type reference_type
)
292 switch(reference_type
) {
293 case BRW_REGISTER_TYPE_HF
:
294 case BRW_REGISTER_TYPE_F
:
295 case BRW_REGISTER_TYPE_DF
:
298 return BRW_REGISTER_TYPE_HF
;
300 return BRW_REGISTER_TYPE_F
;
302 return BRW_REGISTER_TYPE_DF
;
304 unreachable("Invalid bit size");
306 case BRW_REGISTER_TYPE_W
:
307 case BRW_REGISTER_TYPE_D
:
308 case BRW_REGISTER_TYPE_Q
:
311 return BRW_REGISTER_TYPE_W
;
313 return BRW_REGISTER_TYPE_D
;
315 return BRW_REGISTER_TYPE_Q
;
317 unreachable("Invalid bit size");
319 case BRW_REGISTER_TYPE_UW
:
320 case BRW_REGISTER_TYPE_UD
:
321 case BRW_REGISTER_TYPE_UQ
:
324 return BRW_REGISTER_TYPE_UW
;
326 return BRW_REGISTER_TYPE_UD
;
328 return BRW_REGISTER_TYPE_UQ
;
330 unreachable("Invalid bit size");
333 unreachable("Unknown type");
338 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
340 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
341 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
342 nir_locals
[i
] = fs_reg();
345 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
346 unsigned array_elems
=
347 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
348 unsigned size
= array_elems
* reg
->num_components
;
349 const brw_reg_type reg_type
=
350 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
351 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
354 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
357 nir_emit_cf_list(&impl
->body
);
361 fs_visitor::nir_emit_cf_list(exec_list
*list
)
363 exec_list_validate(list
);
364 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
365 switch (node
->type
) {
367 nir_emit_if(nir_cf_node_as_if(node
));
370 case nir_cf_node_loop
:
371 nir_emit_loop(nir_cf_node_as_loop(node
));
374 case nir_cf_node_block
:
375 nir_emit_block(nir_cf_node_as_block(node
));
379 unreachable("Invalid CFG node block");
385 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
387 /* first, put the condition into f0 */
388 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
389 retype(get_nir_src(if_stmt
->condition
),
390 BRW_REGISTER_TYPE_D
));
391 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
393 bld
.IF(BRW_PREDICATE_NORMAL
);
395 nir_emit_cf_list(&if_stmt
->then_list
);
397 /* note: if the else is empty, dead CF elimination will remove it */
398 bld
.emit(BRW_OPCODE_ELSE
);
400 nir_emit_cf_list(&if_stmt
->else_list
);
402 bld
.emit(BRW_OPCODE_ENDIF
);
404 if (devinfo
->gen
< 7)
405 limit_dispatch_width(16, "Non-uniform control flow unsupported "
410 fs_visitor::nir_emit_loop(nir_loop
*loop
)
412 bld
.emit(BRW_OPCODE_DO
);
414 nir_emit_cf_list(&loop
->body
);
416 bld
.emit(BRW_OPCODE_WHILE
);
418 if (devinfo
->gen
< 7)
419 limit_dispatch_width(16, "Non-uniform control flow unsupported "
424 fs_visitor::nir_emit_block(nir_block
*block
)
426 nir_foreach_instr(instr
, block
) {
427 nir_emit_instr(instr
);
432 fs_visitor::nir_emit_instr(nir_instr
*instr
)
434 const fs_builder abld
= bld
.annotate(NULL
, instr
);
436 switch (instr
->type
) {
437 case nir_instr_type_alu
:
438 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
441 case nir_instr_type_deref
:
442 /* Derefs can exist for images but they do nothing */
445 case nir_instr_type_intrinsic
:
447 case MESA_SHADER_VERTEX
:
448 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
450 case MESA_SHADER_TESS_CTRL
:
451 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
453 case MESA_SHADER_TESS_EVAL
:
454 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_GEOMETRY
:
457 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_FRAGMENT
:
460 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case MESA_SHADER_COMPUTE
:
463 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
466 unreachable("unsupported shader stage");
470 case nir_instr_type_tex
:
471 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
474 case nir_instr_type_load_const
:
475 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
478 case nir_instr_type_ssa_undef
:
479 /* We create a new VGRF for undefs on every use (by handling
480 * them in get_nir_src()), rather than for each definition.
481 * This helps register coalescing eliminate MOVs from undef.
485 case nir_instr_type_jump
:
486 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
490 unreachable("unknown instruction type");
495 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
499 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
500 const fs_reg
&result
)
502 if (!instr
->src
[0].src
.is_ssa
||
503 !instr
->src
[0].src
.ssa
->parent_instr
)
506 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
509 nir_alu_instr
*src0
=
510 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
512 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
513 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
516 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
517 assert(element
!= NULL
);
519 /* Element type to extract.*/
520 const brw_reg_type type
= brw_int_type(
521 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
522 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
524 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
525 op0
.type
= brw_type_for_nir_type(devinfo
,
526 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
527 nir_src_bit_size(src0
->src
[0].src
)));
528 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
530 set_saturate(instr
->dest
.saturate
,
531 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
536 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
537 const fs_reg
&result
)
539 if (!instr
->src
[0].src
.is_ssa
||
540 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
543 nir_intrinsic_instr
*src0
=
544 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
546 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
549 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
550 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
553 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
554 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
557 fs_reg tmp
= vgrf(glsl_type::int_type
);
559 if (devinfo
->gen
>= 6) {
560 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
561 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
563 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
565 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
566 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
568 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
570 * This negation looks like it's safe in practice, because bits 0:4 will
571 * surely be TRIANGLES
574 if (value1
->f32
[0] == -1.0f
) {
578 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
579 g0
, brw_imm_uw(0x3f80));
581 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
582 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
584 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
586 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
587 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
589 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
591 * This negation looks like it's safe in practice, because bits 0:4 will
592 * surely be TRIANGLES
595 if (value1
->f32
[0] == -1.0f
) {
599 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
601 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
607 emit_find_msb_using_lzd(const fs_builder
&bld
,
608 const fs_reg
&result
,
616 /* LZD of an absolute value source almost always does the right
617 * thing. There are two problem values:
619 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
620 * 0. However, findMSB(int(0x80000000)) == 30.
622 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
623 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
625 * For a value of zero or negative one, -1 will be returned.
627 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
628 * findMSB(-(1<<x)) should return x-1.
630 * For all negative number cases, including 0x80000000 and
631 * 0xffffffff, the correct value is obtained from LZD if instead of
632 * negating the (already negative) value the logical-not is used. A
633 * conditonal logical-not can be achieved in two instructions.
635 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
637 bld
.ASR(temp
, src
, brw_imm_d(31));
638 bld
.XOR(temp
, temp
, src
);
641 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
642 retype(temp
, BRW_REGISTER_TYPE_UD
));
644 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
645 * from the LSB side. Subtract the result from 31 to convert the MSB
646 * count into an LSB count. If no bits are set, LZD will return 32.
647 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
649 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
650 inst
->src
[0].negate
= true;
654 brw_rnd_mode_from_nir_op (const nir_op op
) {
656 case nir_op_f2f16_rtz
:
657 return BRW_RND_MODE_RTZ
;
658 case nir_op_f2f16_rtne
:
659 return BRW_RND_MODE_RTNE
;
661 unreachable("Operation doesn't support rounding mode");
666 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
668 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
671 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
672 result
.type
= brw_type_for_nir_type(devinfo
,
673 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
674 nir_dest_bit_size(instr
->dest
.dest
)));
677 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
678 op
[i
] = get_nir_src(instr
->src
[i
].src
);
679 op
[i
].type
= brw_type_for_nir_type(devinfo
,
680 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
681 nir_src_bit_size(instr
->src
[i
].src
)));
682 op
[i
].abs
= instr
->src
[i
].abs
;
683 op
[i
].negate
= instr
->src
[i
].negate
;
686 /* We get a bunch of mov's out of the from_ssa pass and they may still
687 * be vectorized. We'll handle them as a special-case. We'll also
688 * handle vecN here because it's basically the same thing.
696 fs_reg temp
= result
;
697 bool need_extra_copy
= false;
698 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
699 if (!instr
->src
[i
].src
.is_ssa
&&
700 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
701 need_extra_copy
= true;
702 temp
= bld
.vgrf(result
.type
, 4);
707 for (unsigned i
= 0; i
< 4; i
++) {
708 if (!(instr
->dest
.write_mask
& (1 << i
)))
711 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
712 inst
= bld
.MOV(offset(temp
, bld
, i
),
713 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
715 inst
= bld
.MOV(offset(temp
, bld
, i
),
716 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
718 inst
->saturate
= instr
->dest
.saturate
;
721 /* In this case the source and destination registers were the same,
722 * so we need to insert an extra set of moves in order to deal with
725 if (need_extra_copy
) {
726 for (unsigned i
= 0; i
< 4; i
++) {
727 if (!(instr
->dest
.write_mask
& (1 << i
)))
730 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
739 /* At this point, we have dealt with any instruction that operates on
740 * more than a single channel. Therefore, we can just adjust the source
741 * and destination registers for that channel and emit the instruction.
743 unsigned channel
= 0;
744 if (nir_op_infos
[instr
->op
].output_size
== 0) {
745 /* Since NIR is doing the scalarizing for us, we should only ever see
746 * vectorized operations with a single channel.
748 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
749 channel
= ffs(instr
->dest
.write_mask
) - 1;
751 result
= offset(result
, bld
, channel
);
754 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
755 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
756 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
762 if (optimize_extract_to_float(instr
, result
))
764 inst
= bld
.MOV(result
, op
[0]);
765 inst
->saturate
= instr
->dest
.saturate
;
768 case nir_op_f2f16_rtne
:
769 case nir_op_f2f16_rtz
:
770 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
771 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
774 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
775 * on the HW gen, it is a special hw opcode or just a MOV, and
776 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
778 * But if we want to use that opcode, we need to provide support on
779 * different optimizations and lowerings. As right now HF support is
780 * only for gen8+, it will be better to use directly the MOV, and use
781 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
784 case nir_op_f2f16_undef
:
785 inst
= bld
.MOV(result
, op
[0]);
786 inst
->saturate
= instr
->dest
.saturate
;
796 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
798 * "When source or destination is 64b (...), regioning in Align1
799 * must follow these rules:
801 * 1. Source and destination horizontal stride must be aligned to
805 * This means that conversions from bit-sizes smaller than 64-bit to
806 * 64-bit need to have the source data elements aligned to 64-bit.
807 * This restriction does not apply to BDW and later.
809 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
810 nir_src_bit_size(instr
->src
[0].src
) < 64 &&
811 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
812 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
813 tmp
= subscript(tmp
, op
[0].type
, 0);
814 inst
= bld
.MOV(tmp
, op
[0]);
815 inst
= bld
.MOV(result
, tmp
);
816 inst
->saturate
= instr
->dest
.saturate
;
831 inst
= bld
.MOV(result
, op
[0]);
832 inst
->saturate
= instr
->dest
.saturate
;
837 /* Straightforward since the source can be assumed to be either
838 * strictly >= 0 or strictly <= 0 depending on the setting of the
841 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
843 inst
= (op
[0].negate
)
844 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
845 : bld
.MOV(result
, brw_imm_f(1.0f
));
847 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
849 if (instr
->dest
.saturate
)
850 inst
->saturate
= true;
852 } else if (type_sz(op
[0].type
) < 8) {
853 /* AND(val, 0x80000000) gives the sign bit.
855 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
858 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
860 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
861 op
[0].type
= BRW_REGISTER_TYPE_UD
;
862 result
.type
= BRW_REGISTER_TYPE_UD
;
863 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
865 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
866 inst
->predicate
= BRW_PREDICATE_NORMAL
;
867 if (instr
->dest
.saturate
) {
868 inst
= bld
.MOV(result
, result
);
869 inst
->saturate
= true;
872 /* For doubles we do the same but we need to consider:
874 * - 2-src instructions can't operate with 64-bit immediates
875 * - The sign is encoded in the high 32-bit of each DF
876 * - We need to produce a DF result.
879 fs_reg zero
= vgrf(glsl_type::double_type
);
880 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
881 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
883 bld
.MOV(result
, zero
);
885 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
886 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
887 brw_imm_ud(0x80000000u
));
889 set_predicate(BRW_PREDICATE_NORMAL
,
890 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
892 if (instr
->dest
.saturate
) {
893 inst
= bld
.MOV(result
, result
);
894 inst
->saturate
= true;
901 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
902 * -> non-negative val generates 0x00000000.
903 * Predicated OR sets 1 if val is positive.
905 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
906 assert(bit_size
== 32 || bit_size
== 16);
908 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
909 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
910 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
912 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
913 bld
.ASR(result
, op
[0], shift
);
914 inst
= bld
.OR(result
, result
, one
);
915 inst
->predicate
= BRW_PREDICATE_NORMAL
;
920 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
921 inst
->saturate
= instr
->dest
.saturate
;
925 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
926 inst
->saturate
= instr
->dest
.saturate
;
930 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
931 inst
->saturate
= instr
->dest
.saturate
;
935 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
936 inst
->saturate
= instr
->dest
.saturate
;
940 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
941 inst
->saturate
= instr
->dest
.saturate
;
945 if (fs_key
->high_quality_derivatives
) {
946 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
948 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
950 inst
->saturate
= instr
->dest
.saturate
;
952 case nir_op_fddx_fine
:
953 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
954 inst
->saturate
= instr
->dest
.saturate
;
956 case nir_op_fddx_coarse
:
957 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
958 inst
->saturate
= instr
->dest
.saturate
;
961 if (fs_key
->high_quality_derivatives
) {
962 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
964 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
966 inst
->saturate
= instr
->dest
.saturate
;
968 case nir_op_fddy_fine
:
969 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
970 inst
->saturate
= instr
->dest
.saturate
;
972 case nir_op_fddy_coarse
:
973 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
974 inst
->saturate
= instr
->dest
.saturate
;
979 inst
= bld
.ADD(result
, op
[0], op
[1]);
980 inst
->saturate
= instr
->dest
.saturate
;
984 inst
= bld
.MUL(result
, op
[0], op
[1]);
985 inst
->saturate
= instr
->dest
.saturate
;
989 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
990 bld
.MUL(result
, op
[0], op
[1]);
993 case nir_op_imul_high
:
994 case nir_op_umul_high
:
995 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
996 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1001 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1002 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1005 case nir_op_uadd_carry
:
1006 unreachable("Should have been lowered by carry_to_arith().");
1008 case nir_op_usub_borrow
:
1009 unreachable("Should have been lowered by borrow_to_arith().");
1013 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1014 * appears that our hardware just does the right thing for signed
1017 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1018 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1022 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1023 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1025 /* Math instructions don't support conditional mod */
1026 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1027 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1029 /* Now, we need to determine if signs of the sources are different.
1030 * When we XOR the sources, the top bit is 0 if they are the same and 1
1031 * if they are different. We can then use a conditional modifier to
1032 * turn that into a predicate. This leads us to an XOR.l instruction.
1034 * Technically, according to the PRM, you're not allowed to use .l on a
1035 * XOR instruction. However, emperical experiments and Curro's reading
1036 * of the simulator source both indicate that it's safe.
1038 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1039 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1040 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1041 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1043 /* If the result of the initial remainder operation is non-zero and the
1044 * two sources have different signs, add in a copy of op[1] to get the
1045 * final integer modulus value.
1047 inst
= bld
.ADD(result
, result
, op
[1]);
1048 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1056 fs_reg dest
= result
;
1058 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1060 dest
= bld
.vgrf(op
[0].type
, 1);
1062 brw_conditional_mod cond
;
1063 switch (instr
->op
) {
1065 cond
= BRW_CONDITIONAL_L
;
1068 cond
= BRW_CONDITIONAL_GE
;
1071 cond
= BRW_CONDITIONAL_Z
;
1074 cond
= BRW_CONDITIONAL_NZ
;
1077 unreachable("bad opcode");
1080 bld
.CMP(dest
, op
[0], op
[1], cond
);
1082 if (bit_size
> 32) {
1083 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1084 } else if(bit_size
< 32) {
1085 /* When we convert the result to 32-bit we need to be careful and do
1086 * it as a signed conversion to get sign extension (for 32-bit true)
1088 const brw_reg_type src_type
=
1089 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1091 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1102 fs_reg dest
= result
;
1104 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1106 dest
= bld
.vgrf(op
[0].type
, 1);
1108 brw_conditional_mod cond
;
1109 switch (instr
->op
) {
1112 cond
= BRW_CONDITIONAL_L
;
1116 cond
= BRW_CONDITIONAL_GE
;
1119 cond
= BRW_CONDITIONAL_Z
;
1122 cond
= BRW_CONDITIONAL_NZ
;
1125 unreachable("bad opcode");
1127 bld
.CMP(dest
, op
[0], op
[1], cond
);
1129 if (bit_size
> 32) {
1130 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1131 } else if (bit_size
< 32) {
1132 /* When we convert the result to 32-bit we need to be careful and do
1133 * it as a signed conversion to get sign extension (for 32-bit true)
1135 const brw_reg_type src_type
=
1136 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1138 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1144 if (devinfo
->gen
>= 8) {
1145 op
[0] = resolve_source_modifiers(op
[0]);
1147 bld
.NOT(result
, op
[0]);
1150 if (devinfo
->gen
>= 8) {
1151 op
[0] = resolve_source_modifiers(op
[0]);
1152 op
[1] = resolve_source_modifiers(op
[1]);
1154 bld
.XOR(result
, op
[0], op
[1]);
1157 if (devinfo
->gen
>= 8) {
1158 op
[0] = resolve_source_modifiers(op
[0]);
1159 op
[1] = resolve_source_modifiers(op
[1]);
1161 bld
.OR(result
, op
[0], op
[1]);
1164 if (devinfo
->gen
>= 8) {
1165 op
[0] = resolve_source_modifiers(op
[0]);
1166 op
[1] = resolve_source_modifiers(op
[1]);
1168 bld
.AND(result
, op
[0], op
[1]);
1174 case nir_op_ball_fequal2
:
1175 case nir_op_ball_iequal2
:
1176 case nir_op_ball_fequal3
:
1177 case nir_op_ball_iequal3
:
1178 case nir_op_ball_fequal4
:
1179 case nir_op_ball_iequal4
:
1180 case nir_op_bany_fnequal2
:
1181 case nir_op_bany_inequal2
:
1182 case nir_op_bany_fnequal3
:
1183 case nir_op_bany_inequal3
:
1184 case nir_op_bany_fnequal4
:
1185 case nir_op_bany_inequal4
:
1186 unreachable("Lowered by nir_lower_alu_reductions");
1188 case nir_op_fnoise1_1
:
1189 case nir_op_fnoise1_2
:
1190 case nir_op_fnoise1_3
:
1191 case nir_op_fnoise1_4
:
1192 case nir_op_fnoise2_1
:
1193 case nir_op_fnoise2_2
:
1194 case nir_op_fnoise2_3
:
1195 case nir_op_fnoise2_4
:
1196 case nir_op_fnoise3_1
:
1197 case nir_op_fnoise3_2
:
1198 case nir_op_fnoise3_3
:
1199 case nir_op_fnoise3_4
:
1200 case nir_op_fnoise4_1
:
1201 case nir_op_fnoise4_2
:
1202 case nir_op_fnoise4_3
:
1203 case nir_op_fnoise4_4
:
1204 unreachable("not reached: should be handled by lower_noise");
1207 unreachable("not reached: should be handled by ldexp_to_arith()");
1210 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1211 inst
->saturate
= instr
->dest
.saturate
;
1215 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1216 inst
->saturate
= instr
->dest
.saturate
;
1221 bld
.MOV(result
, negate(op
[0]));
1226 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1227 if (bit_size
== 64) {
1228 /* two-argument instructions can't take 64-bit immediates */
1232 if (instr
->op
== nir_op_f2b
) {
1233 zero
= vgrf(glsl_type::double_type
);
1234 tmp
= vgrf(glsl_type::double_type
);
1235 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1237 zero
= vgrf(glsl_type::int64_t_type
);
1238 tmp
= vgrf(glsl_type::int64_t_type
);
1239 bld
.MOV(zero
, brw_imm_q(0));
1242 /* A SIMD16 execution needs to be split in two instructions, so use
1243 * a vgrf instead of the flag register as dst so instruction splitting
1246 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1247 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1250 if (bit_size
== 32) {
1251 zero
= instr
->op
== nir_op_f2b
? brw_imm_f(0.0f
) : brw_imm_d(0);
1253 assert(bit_size
== 16);
1254 zero
= instr
->op
== nir_op_f2b
?
1255 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1257 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1263 inst
= bld
.RNDZ(result
, op
[0]);
1264 inst
->saturate
= instr
->dest
.saturate
;
1267 case nir_op_fceil
: {
1268 op
[0].negate
= !op
[0].negate
;
1269 fs_reg temp
= vgrf(glsl_type::float_type
);
1270 bld
.RNDD(temp
, op
[0]);
1272 inst
= bld
.MOV(result
, temp
);
1273 inst
->saturate
= instr
->dest
.saturate
;
1277 inst
= bld
.RNDD(result
, op
[0]);
1278 inst
->saturate
= instr
->dest
.saturate
;
1281 inst
= bld
.FRC(result
, op
[0]);
1282 inst
->saturate
= instr
->dest
.saturate
;
1284 case nir_op_fround_even
:
1285 inst
= bld
.RNDE(result
, op
[0]);
1286 inst
->saturate
= instr
->dest
.saturate
;
1289 case nir_op_fquantize2f16
: {
1290 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1291 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1292 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1294 /* The destination stride must be at least as big as the source stride. */
1295 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1298 /* Check for denormal */
1299 fs_reg abs_src0
= op
[0];
1300 abs_src0
.abs
= true;
1301 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1303 /* Get the appropriately signed zero */
1304 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1305 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1306 brw_imm_ud(0x80000000));
1307 /* Do the actual F32 -> F16 -> F32 conversion */
1308 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1309 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1310 /* Select that or zero based on normal status */
1311 inst
= bld
.SEL(result
, zero
, tmp32
);
1312 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1313 inst
->saturate
= instr
->dest
.saturate
;
1320 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1321 inst
->saturate
= instr
->dest
.saturate
;
1327 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1328 inst
->saturate
= instr
->dest
.saturate
;
1331 case nir_op_pack_snorm_2x16
:
1332 case nir_op_pack_snorm_4x8
:
1333 case nir_op_pack_unorm_2x16
:
1334 case nir_op_pack_unorm_4x8
:
1335 case nir_op_unpack_snorm_2x16
:
1336 case nir_op_unpack_snorm_4x8
:
1337 case nir_op_unpack_unorm_2x16
:
1338 case nir_op_unpack_unorm_4x8
:
1339 case nir_op_unpack_half_2x16
:
1340 case nir_op_pack_half_2x16
:
1341 unreachable("not reached: should be handled by lower_packing_builtins");
1343 case nir_op_unpack_half_2x16_split_x
:
1344 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1345 inst
->saturate
= instr
->dest
.saturate
;
1347 case nir_op_unpack_half_2x16_split_y
:
1348 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1349 inst
->saturate
= instr
->dest
.saturate
;
1352 case nir_op_pack_64_2x32_split
:
1353 case nir_op_pack_32_2x16_split
:
1354 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1357 case nir_op_unpack_64_2x32_split_x
:
1358 case nir_op_unpack_64_2x32_split_y
: {
1359 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1360 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1362 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1366 case nir_op_unpack_32_2x16_split_x
:
1367 case nir_op_unpack_32_2x16_split_y
: {
1368 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1369 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1371 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1376 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1377 inst
->saturate
= instr
->dest
.saturate
;
1380 case nir_op_bitfield_reverse
:
1381 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1382 bld
.BFREV(result
, op
[0]);
1385 case nir_op_bit_count
:
1386 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1387 bld
.CBIT(result
, op
[0]);
1390 case nir_op_ufind_msb
: {
1391 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1392 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1396 case nir_op_ifind_msb
: {
1397 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1399 if (devinfo
->gen
< 7) {
1400 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1402 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1404 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1405 * count from the LSB side. If FBH didn't return an error
1406 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1407 * count into an LSB count.
1409 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1411 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1412 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1413 inst
->src
[0].negate
= true;
1418 case nir_op_find_lsb
:
1419 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1421 if (devinfo
->gen
< 7) {
1422 fs_reg temp
= vgrf(glsl_type::int_type
);
1424 /* (x & -x) generates a value that consists of only the LSB of x.
1425 * For all powers of 2, findMSB(y) == findLSB(y).
1427 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1428 fs_reg negated_src
= src
;
1430 /* One must be negated, and the other must be non-negated. It
1431 * doesn't matter which is which.
1433 negated_src
.negate
= true;
1436 bld
.AND(temp
, src
, negated_src
);
1437 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1439 bld
.FBL(result
, op
[0]);
1443 case nir_op_ubitfield_extract
:
1444 case nir_op_ibitfield_extract
:
1445 unreachable("should have been lowered");
1448 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1449 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1452 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1453 bld
.BFI1(result
, op
[0], op
[1]);
1456 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1457 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1460 case nir_op_bitfield_insert
:
1461 unreachable("not reached: should have been lowered");
1466 fs_reg shift_count
= op
[1];
1468 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1469 if (op
[1].file
== VGRF
&&
1470 (result
.type
== BRW_REGISTER_TYPE_Q
||
1471 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1472 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1473 BRW_REGISTER_TYPE_UD
);
1474 shift_count
.stride
= 2;
1475 bld
.MOV(shift_count
, op
[1]);
1479 switch (instr
->op
) {
1481 bld
.SHL(result
, op
[0], shift_count
);
1484 bld
.ASR(result
, op
[0], shift_count
);
1487 bld
.SHR(result
, op
[0], shift_count
);
1490 unreachable("not reached");
1495 case nir_op_pack_half_2x16_split
:
1496 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1500 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1501 inst
->saturate
= instr
->dest
.saturate
;
1505 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1506 inst
->saturate
= instr
->dest
.saturate
;
1510 if (optimize_frontfacing_ternary(instr
, result
))
1513 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1514 inst
= bld
.SEL(result
, op
[1], op
[2]);
1515 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1518 case nir_op_extract_u8
:
1519 case nir_op_extract_i8
: {
1520 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1521 assert(byte
!= NULL
);
1526 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1527 * Use two instructions and a word or DWord intermediate integer type.
1529 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1530 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1532 if (instr
->op
== nir_op_extract_i8
) {
1533 /* If we need to sign extend, extract to a word first */
1534 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1535 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
->u32
[0]));
1536 bld
.MOV(result
, w_temp
);
1538 /* Otherwise use an AND with 0xff and a word type */
1539 bld
.AND(result
, subscript(op
[0], type
, byte
->u32
[0] / 2), brw_imm_uw(0xff));
1542 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1543 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1548 case nir_op_extract_u16
:
1549 case nir_op_extract_i16
: {
1550 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1551 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1552 assert(word
!= NULL
);
1553 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1558 unreachable("unhandled instruction");
1561 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1562 * to sign extend the low bit to 0/~0
1564 if (devinfo
->gen
<= 5 &&
1565 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1566 fs_reg masked
= vgrf(glsl_type::int_type
);
1567 bld
.AND(masked
, result
, brw_imm_d(1));
1568 masked
.negate
= true;
1569 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1574 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1575 nir_load_const_instr
*instr
)
1577 const brw_reg_type reg_type
=
1578 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1579 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1581 switch (instr
->def
.bit_size
) {
1583 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1584 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1588 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1589 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1593 assert(devinfo
->gen
>= 7);
1594 if (devinfo
->gen
== 7) {
1595 /* We don't get 64-bit integer types until gen8 */
1596 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1597 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1598 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1601 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1602 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1607 unreachable("Invalid bit size");
1610 nir_ssa_values
[instr
->def
.index
] = reg
;
1614 fs_visitor::get_nir_src(const nir_src
&src
)
1618 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1619 const brw_reg_type reg_type
=
1620 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1621 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1623 reg
= nir_ssa_values
[src
.ssa
->index
];
1626 /* We don't handle indirects on locals */
1627 assert(src
.reg
.indirect
== NULL
);
1628 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1629 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1632 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1633 /* The only 64-bit type available on gen7 is DF, so use that. */
1634 reg
.type
= BRW_REGISTER_TYPE_DF
;
1636 /* To avoid floating-point denorm flushing problems, set the type by
1637 * default to an integer type - instructions that need floating point
1638 * semantics will set this to F if they need to
1640 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1641 BRW_REGISTER_TYPE_D
);
1648 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1650 * This function should not be called on any value which may be 64 bits.
1651 * We could theoretically support 64-bit on gen8+ but we choose not to
1652 * because it wouldn't work in general (no gen7 support) and there are
1653 * enough restrictions in 64-bit immediates that you can't take the return
1654 * value and treat it the same as the result of get_nir_src().
1657 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1659 nir_const_value
*val
= nir_src_as_const_value(src
);
1660 assert(nir_src_bit_size(src
) == 32);
1661 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1665 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1668 const brw_reg_type reg_type
=
1669 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1670 nir_ssa_values
[dest
.ssa
.index
] =
1671 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1672 return nir_ssa_values
[dest
.ssa
.index
];
1674 /* We don't handle indirects on locals */
1675 assert(dest
.reg
.indirect
== NULL
);
1676 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1677 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1682 fs_visitor::get_nir_image_deref(nir_deref_instr
*deref
)
1684 fs_reg arr_offset
= brw_imm_ud(0);
1685 unsigned array_size
= BRW_IMAGE_PARAM_SIZE
* 4;
1686 nir_deref_instr
*head
= deref
;
1687 while (head
->deref_type
!= nir_deref_type_var
) {
1688 assert(head
->deref_type
== nir_deref_type_array
);
1690 /* This level's element size is the previous level's array size */
1691 const unsigned elem_size
= array_size
;
1693 fs_reg index
= retype(get_nir_src_imm(head
->arr
.index
),
1694 BRW_REGISTER_TYPE_UD
);
1695 if (arr_offset
.file
== BRW_IMMEDIATE_VALUE
&&
1696 index
.file
== BRW_IMMEDIATE_VALUE
) {
1697 arr_offset
.ud
+= index
.ud
* elem_size
;
1698 } else if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1699 bld
.ADD(arr_offset
, arr_offset
, brw_imm_ud(index
.ud
* elem_size
));
1701 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
1702 bld
.MUL(tmp
, index
, brw_imm_ud(elem_size
));
1703 bld
.ADD(tmp
, tmp
, arr_offset
);
1707 head
= nir_deref_instr_parent(head
);
1708 assert(glsl_type_is_array(head
->type
));
1709 array_size
= elem_size
* glsl_get_length(head
->type
);
1712 assert(head
->deref_type
== nir_deref_type_var
);
1713 const unsigned max_arr_offset
= array_size
- (BRW_IMAGE_PARAM_SIZE
* 4);
1714 fs_reg
image(UNIFORM
, head
->var
->data
.driver_location
/ 4,
1715 BRW_REGISTER_TYPE_UD
);
1717 if (arr_offset
.file
== BRW_IMMEDIATE_VALUE
) {
1718 /* The offset is in bytes but we want it in dwords */
1719 return offset(image
, bld
, MIN2(arr_offset
.ud
, max_arr_offset
) / 4);
1721 /* Accessing an invalid surface index with the dataport can result
1722 * in a hang. According to the spec "if the index used to
1723 * select an individual element is negative or greater than or
1724 * equal to the size of the array, the results of the operation
1725 * are undefined but may not lead to termination" -- which is one
1726 * of the possible outcomes of the hang. Clamp the index to
1727 * prevent access outside of the array bounds.
1729 bld
.emit_minmax(arr_offset
, arr_offset
, brw_imm_ud(max_arr_offset
),
1732 /* Emit a pile of MOVs to load the uniform into a temporary. The
1733 * dead-code elimination pass will get rid of what we don't use.
1735 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1736 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1737 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1738 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1739 arr_offset
, brw_imm_ud(max_arr_offset
+ 4));
1746 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1749 for (unsigned i
= 0; i
< 4; i
++) {
1750 if (!((wr_mask
>> i
) & 1))
1753 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1754 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1755 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1756 if (new_inst
->src
[j
].file
== VGRF
)
1757 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1764 * Get the matching channel register datatype for an image intrinsic of the
1765 * specified GLSL image type.
1768 get_image_base_type(const glsl_type
*type
)
1770 switch ((glsl_base_type
)type
->sampled_type
) {
1771 case GLSL_TYPE_UINT
:
1772 return BRW_REGISTER_TYPE_UD
;
1774 return BRW_REGISTER_TYPE_D
;
1775 case GLSL_TYPE_FLOAT
:
1776 return BRW_REGISTER_TYPE_F
;
1778 unreachable("Not reached.");
1783 * Get the appropriate atomic op for an image atomic intrinsic.
1786 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1789 case nir_intrinsic_image_deref_atomic_add
:
1791 case nir_intrinsic_image_deref_atomic_min
:
1792 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1793 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1794 case nir_intrinsic_image_deref_atomic_max
:
1795 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1796 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1797 case nir_intrinsic_image_deref_atomic_and
:
1799 case nir_intrinsic_image_deref_atomic_or
:
1801 case nir_intrinsic_image_deref_atomic_xor
:
1803 case nir_intrinsic_image_deref_atomic_exchange
:
1805 case nir_intrinsic_image_deref_atomic_comp_swap
:
1806 return BRW_AOP_CMPWR
;
1808 unreachable("Not reachable.");
1813 emit_pixel_interpolater_send(const fs_builder
&bld
,
1818 glsl_interp_mode interpolation
)
1820 struct brw_wm_prog_data
*wm_prog_data
=
1821 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1823 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1824 /* 2 floats per slot returned */
1825 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1826 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1828 wm_prog_data
->pulls_bary
= true;
1834 * Computes 1 << x, given a D/UD register containing some value x.
1837 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1839 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1841 fs_reg result
= bld
.vgrf(x
.type
, 1);
1842 fs_reg one
= bld
.vgrf(x
.type
, 1);
1844 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1845 bld
.SHL(result
, one
, x
);
1850 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1852 assert(stage
== MESA_SHADER_GEOMETRY
);
1854 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1856 if (gs_compile
->control_data_header_size_bits
== 0)
1859 /* We can only do EndPrimitive() functionality when the control data
1860 * consists of cut bits. Fortunately, the only time it isn't is when the
1861 * output type is points, in which case EndPrimitive() is a no-op.
1863 if (gs_prog_data
->control_data_format
!=
1864 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1868 /* Cut bits use one bit per vertex. */
1869 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1871 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1872 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1874 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1875 * vertex n, 0 otherwise. So all we need to do here is mark bit
1876 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1877 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1878 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1880 * Note that if EndPrimitive() is called before emitting any vertices, this
1881 * will cause us to set bit 31 of the control_data_bits register to 1.
1882 * That's fine because:
1884 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1885 * output, so the hardware will ignore cut bit 31.
1887 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1888 * last vertex, so setting cut bit 31 has no effect (since the primitive
1889 * is automatically ended when the GS terminates).
1891 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1892 * control_data_bits register to 0 when the first vertex is emitted.
1895 const fs_builder abld
= bld
.annotate("end primitive");
1897 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1898 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1899 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1900 fs_reg mask
= intexp2(abld
, prev_count
);
1901 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1902 * attention to the lower 5 bits of its second source argument, so on this
1903 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1904 * ((vertex_count - 1) % 32).
1906 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1910 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1912 assert(stage
== MESA_SHADER_GEOMETRY
);
1913 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1915 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1917 const fs_builder abld
= bld
.annotate("emit control data bits");
1918 const fs_builder fwa_bld
= bld
.exec_all();
1920 /* We use a single UD register to accumulate control data bits (32 bits
1921 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1924 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1925 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1926 * use the Channel Mask phase to enable/disable which DWord within that
1927 * group to write. (Remember, different SIMD8 channels may have emitted
1928 * different numbers of vertices, so we may need per-slot offsets.)
1930 * Channel masking presents an annoying problem: we may have to replicate
1931 * the data up to 4 times:
1933 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1935 * To avoid penalizing shaders that emit a small number of vertices, we
1936 * can avoid these sometimes: if the size of the control data header is
1937 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1938 * land in the same 128-bit group, so we can skip per-slot offsets.
1940 * Similarly, if the control data header is <= 32 bits, there is only one
1941 * DWord, so we can skip channel masks.
1943 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1945 fs_reg channel_mask
, per_slot_offset
;
1947 if (gs_compile
->control_data_header_size_bits
> 32) {
1948 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1949 channel_mask
= vgrf(glsl_type::uint_type
);
1952 if (gs_compile
->control_data_header_size_bits
> 128) {
1953 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1954 per_slot_offset
= vgrf(glsl_type::uint_type
);
1957 /* Figure out which DWord we're trying to write to using the formula:
1959 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1961 * Since bits_per_vertex is a power of two, and is known at compile
1962 * time, this can be optimized to:
1964 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1966 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1967 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1968 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1969 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1970 unsigned log2_bits_per_vertex
=
1971 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1972 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1974 if (per_slot_offset
.file
!= BAD_FILE
) {
1975 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1976 * the appropriate OWord within the control data header.
1978 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1981 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1982 * write to the appropriate DWORD within the OWORD.
1984 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1985 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1986 channel_mask
= intexp2(fwa_bld
, channel
);
1987 /* Then the channel masks need to be in bits 23:16. */
1988 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1991 /* Store the control data bits in the message payload and send it. */
1993 if (channel_mask
.file
!= BAD_FILE
)
1994 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1995 if (per_slot_offset
.file
!= BAD_FILE
)
1998 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1999 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2001 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2002 if (per_slot_offset
.file
!= BAD_FILE
)
2003 sources
[i
++] = per_slot_offset
;
2004 if (channel_mask
.file
!= BAD_FILE
)
2005 sources
[i
++] = channel_mask
;
2007 sources
[i
++] = this->control_data_bits
;
2010 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2011 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2013 /* We need to increment Global Offset by 256-bits to make room for
2014 * Broadwell's extra "Vertex Count" payload at the beginning of the
2015 * URB entry. Since this is an OWord message, Global Offset is counted
2016 * in 128-bit units, so we must set it to 2.
2018 if (gs_prog_data
->static_vertex_count
== -1)
2023 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2026 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2028 /* Note: we are calling this *before* increasing vertex_count, so
2029 * this->vertex_count == vertex_count - 1 in the formula above.
2032 /* Stream mode uses 2 bits per vertex */
2033 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2035 /* Must be a valid stream */
2036 assert(stream_id
< MAX_VERTEX_STREAMS
);
2038 /* Control data bits are initialized to 0 so we don't have to set any
2039 * bits when sending vertices to stream 0.
2044 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2046 /* reg::sid = stream_id */
2047 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2048 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2050 /* reg:shift_count = 2 * (vertex_count - 1) */
2051 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2052 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2054 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2055 * attention to the lower 5 bits of its second source argument, so on this
2056 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2057 * stream_id << ((2 * (vertex_count - 1)) % 32).
2059 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2060 abld
.SHL(mask
, sid
, shift_count
);
2061 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2065 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2068 assert(stage
== MESA_SHADER_GEOMETRY
);
2070 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2072 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2073 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2075 /* Haswell and later hardware ignores the "Render Stream Select" bits
2076 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2077 * and instead sends all primitives down the pipeline for rasterization.
2078 * If the SOL stage is enabled, "Render Stream Select" is honored and
2079 * primitives bound to non-zero streams are discarded after stream output.
2081 * Since the only purpose of primives sent to non-zero streams is to
2082 * be recorded by transform feedback, we can simply discard all geometry
2083 * bound to these streams when transform feedback is disabled.
2085 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2088 /* If we're outputting 32 control data bits or less, then we can wait
2089 * until the shader is over to output them all. Otherwise we need to
2090 * output them as we go. Now is the time to do it, since we're about to
2091 * output the vertex_count'th vertex, so it's guaranteed that the
2092 * control data bits associated with the (vertex_count - 1)th vertex are
2095 if (gs_compile
->control_data_header_size_bits
> 32) {
2096 const fs_builder abld
=
2097 bld
.annotate("emit vertex: emit control data bits");
2099 /* Only emit control data bits if we've finished accumulating a batch
2100 * of 32 bits. This is the case when:
2102 * (vertex_count * bits_per_vertex) % 32 == 0
2104 * (in other words, when the last 5 bits of vertex_count *
2105 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2106 * integer n (which is always the case, since bits_per_vertex is
2107 * always 1 or 2), this is equivalent to requiring that the last 5-n
2108 * bits of vertex_count are 0:
2110 * vertex_count & (2^(5-n) - 1) == 0
2112 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2115 * vertex_count & (32 / bits_per_vertex - 1) == 0
2117 * TODO: If vertex_count is an immediate, we could do some of this math
2118 * at compile time...
2121 abld
.AND(bld
.null_reg_d(), vertex_count
,
2122 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2123 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2125 abld
.IF(BRW_PREDICATE_NORMAL
);
2126 /* If vertex_count is 0, then no control data bits have been
2127 * accumulated yet, so we can skip emitting them.
2129 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2130 BRW_CONDITIONAL_NEQ
);
2131 abld
.IF(BRW_PREDICATE_NORMAL
);
2132 emit_gs_control_data_bits(vertex_count
);
2133 abld
.emit(BRW_OPCODE_ENDIF
);
2135 /* Reset control_data_bits to 0 so we can start accumulating a new
2138 * Note: in the case where vertex_count == 0, this neutralizes the
2139 * effect of any call to EndPrimitive() that the shader may have
2140 * made before outputting its first vertex.
2142 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2143 inst
->force_writemask_all
= true;
2144 abld
.emit(BRW_OPCODE_ENDIF
);
2147 emit_urb_writes(vertex_count
);
2149 /* In stream mode we have to set control data bits for all vertices
2150 * unless we have disabled control data bits completely (which we do
2151 * do for GL_POINTS outputs that don't use streams).
2153 if (gs_compile
->control_data_header_size_bits
> 0 &&
2154 gs_prog_data
->control_data_format
==
2155 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2156 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2161 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2162 const nir_src
&vertex_src
,
2163 unsigned base_offset
,
2164 const nir_src
&offset_src
,
2165 unsigned num_components
,
2166 unsigned first_component
)
2168 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2170 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2171 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2172 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2174 /* TODO: figure out push input layout for invocations == 1 */
2175 /* TODO: make this work with 64-bit inputs */
2176 if (gs_prog_data
->invocations
== 1 &&
2177 type_sz(dst
.type
) <= 4 &&
2178 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2179 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2180 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2181 vertex_const
->u32
[0] * push_reg_count
;
2182 for (unsigned i
= 0; i
< num_components
; i
++) {
2183 bld
.MOV(offset(dst
, bld
, i
),
2184 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2189 /* Resort to the pull model. Ensure the VUE handles are provided. */
2190 assert(gs_prog_data
->base
.include_vue_handles
);
2192 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2193 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2195 if (gs_prog_data
->invocations
== 1) {
2197 /* The vertex index is constant; just select the proper URB handle. */
2199 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2200 BRW_REGISTER_TYPE_UD
);
2202 /* The vertex index is non-constant. We need to use indirect
2203 * addressing to fetch the proper URB handle.
2205 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2206 * indicating that channel <n> should read the handle from
2207 * DWord <n>. We convert that to bytes by multiplying by 4.
2209 * Next, we convert the vertex index to bytes by multiplying
2210 * by 32 (shifting by 5), and add the two together. This is
2211 * the final indirect byte offset.
2213 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2214 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2215 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2216 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2218 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2219 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2220 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2221 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2222 /* Convert vertex_index to bytes (multiply by 32) */
2223 bld
.SHL(vertex_offset_bytes
,
2224 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2226 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2228 /* Use first_icp_handle as the base offset. There is one register
2229 * of URB handles per vertex, so inform the register allocator that
2230 * we might read up to nir->info.gs.vertices_in registers.
2232 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2233 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2234 fs_reg(icp_offset_bytes
),
2235 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2238 assert(gs_prog_data
->invocations
> 1);
2241 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2243 retype(brw_vec1_grf(first_icp_handle
+
2244 vertex_const
->i32
[0] / 8,
2245 vertex_const
->i32
[0] % 8),
2246 BRW_REGISTER_TYPE_UD
));
2248 /* The vertex index is non-constant. We need to use indirect
2249 * addressing to fetch the proper URB handle.
2252 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2254 /* Convert vertex_index to bytes (multiply by 4) */
2255 bld
.SHL(icp_offset_bytes
,
2256 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2259 /* Use first_icp_handle as the base offset. There is one DWord
2260 * of URB handles per vertex, so inform the register allocator that
2261 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2263 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2264 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2265 fs_reg(icp_offset_bytes
),
2266 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2273 fs_reg tmp_dst
= dst
;
2274 fs_reg indirect_offset
= get_nir_src(offset_src
);
2275 unsigned num_iterations
= 1;
2276 unsigned orig_num_components
= num_components
;
2278 if (type_sz(dst
.type
) == 8) {
2279 if (num_components
> 2) {
2283 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2285 first_component
= first_component
/ 2;
2288 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2290 /* Constant indexing - use global offset. */
2291 if (first_component
!= 0) {
2292 unsigned read_components
= num_components
+ first_component
;
2293 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2294 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2295 inst
->size_written
= read_components
*
2296 tmp
.component_size(inst
->exec_size
);
2297 for (unsigned i
= 0; i
< num_components
; i
++) {
2298 bld
.MOV(offset(tmp_dst
, bld
, i
),
2299 offset(tmp
, bld
, i
+ first_component
));
2302 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2304 inst
->size_written
= num_components
*
2305 tmp_dst
.component_size(inst
->exec_size
);
2307 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2310 /* Indirect indexing - use per-slot offsets as well. */
2311 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2312 unsigned read_components
= num_components
+ first_component
;
2313 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2314 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2315 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2316 if (first_component
!= 0) {
2317 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2319 inst
->size_written
= read_components
*
2320 tmp
.component_size(inst
->exec_size
);
2321 for (unsigned i
= 0; i
< num_components
; i
++) {
2322 bld
.MOV(offset(tmp_dst
, bld
, i
),
2323 offset(tmp
, bld
, i
+ first_component
));
2326 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2328 inst
->size_written
= num_components
*
2329 tmp_dst
.component_size(inst
->exec_size
);
2331 inst
->offset
= base_offset
;
2335 if (type_sz(dst
.type
) == 8) {
2336 shuffle_from_32bit_read(bld
,
2337 offset(dst
, bld
, iter
* 2),
2338 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2343 if (num_iterations
> 1) {
2344 num_components
= orig_num_components
- 2;
2348 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2349 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2350 indirect_offset
= new_indirect
;
2357 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2359 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2360 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2363 /* The only constant offset we should find is 0. brw_nir.c's
2364 * add_const_offset_to_base() will fold other constant offsets
2365 * into instr->const_index[0].
2367 assert(const_value
->u32
[0] == 0);
2371 return get_nir_src(*offset_src
);
2375 do_untyped_vector_read(const fs_builder
&bld
,
2377 const fs_reg surf_index
,
2378 const fs_reg offset_reg
,
2379 unsigned num_components
)
2381 if (type_sz(dest
.type
) <= 2) {
2382 assert(dest
.stride
== 1);
2383 boolean is_const_offset
= offset_reg
.file
== BRW_IMMEDIATE_VALUE
;
2385 if (is_const_offset
) {
2386 uint32_t start
= offset_reg
.ud
& ~3;
2387 uint32_t end
= offset_reg
.ud
+ num_components
* type_sz(dest
.type
);
2388 end
= ALIGN(end
, 4);
2389 assert (end
- start
<= 16);
2391 /* At this point we have 16-bit component/s that have constant
2392 * offset aligned to 4-bytes that can be read with untyped_reads.
2393 * untyped_read message requires 32-bit aligned offsets.
2395 unsigned first_component
= (offset_reg
.ud
& 3) / type_sz(dest
.type
);
2396 unsigned num_components_32bit
= (end
- start
) / 4;
2398 fs_reg read_result
=
2399 emit_untyped_read(bld
, surf_index
, brw_imm_ud(start
),
2401 num_components_32bit
,
2402 BRW_PREDICATE_NONE
);
2403 shuffle_from_32bit_read(bld
, dest
, read_result
, first_component
,
2406 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2407 for (unsigned i
= 0; i
< num_components
; i
++) {
2409 bld
.MOV(read_offset
, offset_reg
);
2411 bld
.ADD(read_offset
, offset_reg
,
2412 brw_imm_ud(i
* type_sz(dest
.type
)));
2414 /* Non constant offsets are not guaranteed to be aligned 32-bits
2415 * so they are read using one byte_scattered_read message
2416 * for each component.
2418 fs_reg read_result
=
2419 emit_byte_scattered_read(bld
, surf_index
, read_offset
,
2421 type_sz(dest
.type
) * 8 /* bit_size */,
2422 BRW_PREDICATE_NONE
);
2423 bld
.MOV(offset(dest
, bld
, i
),
2424 subscript (read_result
, dest
.type
, 0));
2427 } else if (type_sz(dest
.type
) == 4) {
2428 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2431 BRW_PREDICATE_NONE
);
2432 read_result
.type
= dest
.type
;
2433 for (unsigned i
= 0; i
< num_components
; i
++)
2434 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2435 } else if (type_sz(dest
.type
) == 8) {
2436 /* Reading a dvec, so we need to:
2438 * 1. Multiply num_components by 2, to account for the fact that we
2439 * need to read 64-bit components.
2440 * 2. Shuffle the result of the load to form valid 64-bit elements
2441 * 3. Emit a second load (for components z/w) if needed.
2443 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2444 bld
.MOV(read_offset
, offset_reg
);
2446 int iters
= num_components
<= 2 ? 1 : 2;
2448 /* Load the dvec, the first iteration loads components x/y, the second
2449 * iteration, if needed, loads components z/w
2451 for (int it
= 0; it
< iters
; it
++) {
2452 /* Compute number of components to read in this iteration */
2453 int iter_components
= MIN2(2, num_components
);
2454 num_components
-= iter_components
;
2456 /* Read. Since this message reads 32-bit components, we need to
2457 * read twice as many components.
2459 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2461 iter_components
* 2,
2462 BRW_PREDICATE_NONE
);
2464 /* Shuffle the 32-bit load result into valid 64-bit data */
2465 shuffle_from_32bit_read(bld
, offset(dest
, bld
, it
* 2),
2466 read_result
, 0, iter_components
);
2468 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2471 unreachable("Unsupported type");
2476 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2477 nir_intrinsic_instr
*instr
)
2479 assert(stage
== MESA_SHADER_VERTEX
);
2482 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2483 dest
= get_nir_dest(instr
->dest
);
2485 switch (instr
->intrinsic
) {
2486 case nir_intrinsic_load_vertex_id
:
2487 case nir_intrinsic_load_base_vertex
:
2488 unreachable("should be lowered by nir_lower_system_values()");
2490 case nir_intrinsic_load_vertex_id_zero_base
:
2491 case nir_intrinsic_load_instance_id
:
2492 case nir_intrinsic_load_base_instance
:
2493 case nir_intrinsic_load_draw_id
: {
2494 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2495 fs_reg val
= nir_system_values
[sv
];
2496 assert(val
.file
!= BAD_FILE
);
2497 dest
.type
= val
.type
;
2502 case nir_intrinsic_load_input
: {
2503 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2504 unsigned first_component
= nir_intrinsic_component(instr
);
2505 unsigned num_components
= instr
->num_components
;
2507 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2508 assert(const_offset
&& "Indirect input loads not allowed");
2509 src
= offset(src
, bld
, const_offset
->u32
[0]);
2511 if (type_sz(dest
.type
) == 8)
2512 first_component
/= 2;
2514 /* For 16-bit support maybe a temporary will be needed to copy from
2517 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2518 first_component
, num_components
);
2522 case nir_intrinsic_load_first_vertex
:
2523 case nir_intrinsic_load_is_indexed_draw
:
2524 unreachable("lowered by brw_nir_lower_vs_inputs");
2527 nir_emit_intrinsic(bld
, instr
);
2533 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2534 nir_intrinsic_instr
*instr
)
2536 assert(stage
== MESA_SHADER_TESS_CTRL
);
2537 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2538 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2541 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2542 dst
= get_nir_dest(instr
->dest
);
2544 switch (instr
->intrinsic
) {
2545 case nir_intrinsic_load_primitive_id
:
2546 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2548 case nir_intrinsic_load_invocation_id
:
2549 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2551 case nir_intrinsic_load_patch_vertices_in
:
2552 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2553 brw_imm_d(tcs_key
->input_vertices
));
2556 case nir_intrinsic_barrier
: {
2557 if (tcs_prog_data
->instances
== 1)
2560 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2561 fs_reg m0_2
= component(m0
, 2);
2563 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2565 /* Zero the message header */
2566 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2568 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2569 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2570 brw_imm_ud(INTEL_MASK(16, 13)));
2572 /* Shift it up to bits 27:24. */
2573 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2575 /* Set the Barrier Count and the enable bit */
2576 chanbld
.OR(m0_2
, m0_2
,
2577 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2579 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2583 case nir_intrinsic_load_input
:
2584 unreachable("nir_lower_io should never give us these.");
2587 case nir_intrinsic_load_per_vertex_input
: {
2588 fs_reg indirect_offset
= get_indirect_offset(instr
);
2589 unsigned imm_offset
= instr
->const_index
[0];
2591 const nir_src
&vertex_src
= instr
->src
[0];
2592 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2599 /* Emit a MOV to resolve <0,1,0> regioning. */
2600 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2602 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2603 vertex_const
->i32
[0] & 7),
2604 BRW_REGISTER_TYPE_UD
));
2605 } else if (tcs_prog_data
->instances
== 1 &&
2606 vertex_src
.is_ssa
&&
2607 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2608 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2609 /* For the common case of only 1 instance, an array index of
2610 * gl_InvocationID means reading g1. Skip all the indirect work.
2612 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2614 /* The vertex index is non-constant. We need to use indirect
2615 * addressing to fetch the proper URB handle.
2617 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2619 /* Each ICP handle is a single DWord (4 bytes) */
2620 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2621 bld
.SHL(vertex_offset_bytes
,
2622 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2625 /* Start at g1. We might read up to 4 registers. */
2626 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2627 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2628 brw_imm_ud(4 * REG_SIZE
));
2631 /* We can only read two double components with each URB read, so
2632 * we send two read messages in that case, each one loading up to
2633 * two double components.
2635 unsigned num_iterations
= 1;
2636 unsigned num_components
= instr
->num_components
;
2637 unsigned first_component
= nir_intrinsic_component(instr
);
2638 fs_reg orig_dst
= dst
;
2639 if (type_sz(dst
.type
) == 8) {
2640 first_component
= first_component
/ 2;
2641 if (instr
->num_components
> 2) {
2646 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2650 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2651 if (indirect_offset
.file
== BAD_FILE
) {
2652 /* Constant indexing - use global offset. */
2653 if (first_component
!= 0) {
2654 unsigned read_components
= num_components
+ first_component
;
2655 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2656 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2657 for (unsigned i
= 0; i
< num_components
; i
++) {
2658 bld
.MOV(offset(dst
, bld
, i
),
2659 offset(tmp
, bld
, i
+ first_component
));
2662 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2664 inst
->offset
= imm_offset
;
2667 /* Indirect indexing - use per-slot offsets as well. */
2668 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2669 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2670 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2671 if (first_component
!= 0) {
2672 unsigned read_components
= num_components
+ first_component
;
2673 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2674 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2676 for (unsigned i
= 0; i
< num_components
; i
++) {
2677 bld
.MOV(offset(dst
, bld
, i
),
2678 offset(tmp
, bld
, i
+ first_component
));
2681 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2684 inst
->offset
= imm_offset
;
2687 inst
->size_written
= (num_components
+ first_component
) *
2688 inst
->dst
.component_size(inst
->exec_size
);
2690 /* If we are reading 64-bit data using 32-bit read messages we need
2691 * build proper 64-bit data elements by shuffling the low and high
2692 * 32-bit components around like we do for other things like UBOs
2695 if (type_sz(dst
.type
) == 8) {
2696 shuffle_from_32bit_read(bld
,
2697 offset(orig_dst
, bld
, iter
* 2),
2698 retype(dst
, BRW_REGISTER_TYPE_D
),
2702 /* Copy the temporary to the destination to deal with writemasking.
2704 * Also attempt to deal with gl_PointSize being in the .w component.
2706 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2707 assert(type_sz(dst
.type
) < 8);
2708 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2709 inst
->size_written
= 4 * REG_SIZE
;
2710 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2713 /* If we are loading double data and we need a second read message
2714 * adjust the write offset
2716 if (num_iterations
> 1) {
2717 num_components
= instr
->num_components
- 2;
2724 case nir_intrinsic_load_output
:
2725 case nir_intrinsic_load_per_vertex_output
: {
2726 fs_reg indirect_offset
= get_indirect_offset(instr
);
2727 unsigned imm_offset
= instr
->const_index
[0];
2728 unsigned first_component
= nir_intrinsic_component(instr
);
2731 if (indirect_offset
.file
== BAD_FILE
) {
2732 /* Replicate the patch handle to all enabled channels */
2733 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2734 bld
.MOV(patch_handle
,
2735 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2738 if (first_component
!= 0) {
2739 unsigned read_components
=
2740 instr
->num_components
+ first_component
;
2741 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2742 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2744 inst
->size_written
= read_components
* REG_SIZE
;
2745 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2746 bld
.MOV(offset(dst
, bld
, i
),
2747 offset(tmp
, bld
, i
+ first_component
));
2750 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2752 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2754 inst
->offset
= imm_offset
;
2758 /* Indirect indexing - use per-slot offsets as well. */
2759 const fs_reg srcs
[] = {
2760 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2763 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2764 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2765 if (first_component
!= 0) {
2766 unsigned read_components
=
2767 instr
->num_components
+ first_component
;
2768 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2769 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2771 inst
->size_written
= read_components
* REG_SIZE
;
2772 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2773 bld
.MOV(offset(dst
, bld
, i
),
2774 offset(tmp
, bld
, i
+ first_component
));
2777 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2779 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2781 inst
->offset
= imm_offset
;
2787 case nir_intrinsic_store_output
:
2788 case nir_intrinsic_store_per_vertex_output
: {
2789 fs_reg value
= get_nir_src(instr
->src
[0]);
2790 bool is_64bit
= (instr
->src
[0].is_ssa
?
2791 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2792 fs_reg indirect_offset
= get_indirect_offset(instr
);
2793 unsigned imm_offset
= instr
->const_index
[0];
2794 unsigned mask
= instr
->const_index
[1];
2795 unsigned header_regs
= 0;
2797 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2799 if (indirect_offset
.file
!= BAD_FILE
) {
2800 srcs
[header_regs
++] = indirect_offset
;
2806 unsigned num_components
= util_last_bit(mask
);
2809 /* We can only pack two 64-bit components in a single message, so send
2810 * 2 messages if we have more components
2812 unsigned num_iterations
= 1;
2813 unsigned iter_components
= num_components
;
2814 unsigned first_component
= nir_intrinsic_component(instr
);
2816 first_component
= first_component
/ 2;
2817 if (instr
->num_components
> 2) {
2819 iter_components
= 2;
2823 mask
= mask
<< first_component
;
2825 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2826 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2827 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2828 opcode
= indirect_offset
.file
!= BAD_FILE
?
2829 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2830 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2831 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2832 /* Expand the 64-bit mask to 32-bit channels. We only handle
2833 * two channels in each iteration, so we only care about X/Y.
2835 unsigned mask32
= 0;
2836 if (mask
& WRITEMASK_X
)
2837 mask32
|= WRITEMASK_XY
;
2838 if (mask
& WRITEMASK_Y
)
2839 mask32
|= WRITEMASK_ZW
;
2841 /* If the mask does not include any of the channels X or Y there
2842 * is nothing to do in this iteration. Move on to the next couple
2843 * of 64-bit channels.
2851 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2852 opcode
= indirect_offset
.file
!= BAD_FILE
?
2853 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2854 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2856 opcode
= indirect_offset
.file
!= BAD_FILE
?
2857 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2858 SHADER_OPCODE_URB_WRITE_SIMD8
;
2861 for (unsigned i
= 0; i
< iter_components
; i
++) {
2862 if (!(mask
& (1 << (i
+ first_component
))))
2866 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2868 /* We need to shuffle the 64-bit data to match the layout
2869 * expected by our 32-bit URB write messages. We use a temporary
2872 unsigned channel
= iter
* 2 + i
;
2873 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2875 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2876 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2877 offset(dest
, bld
, 1);
2882 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2883 (is_64bit
? 2 * first_component
: first_component
);
2885 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2886 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2888 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2889 inst
->offset
= imm_offset
;
2892 /* If this is a 64-bit attribute, select the next two 64-bit channels
2893 * to be handled in the next iteration.
2904 nir_emit_intrinsic(bld
, instr
);
2910 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2911 nir_intrinsic_instr
*instr
)
2913 assert(stage
== MESA_SHADER_TESS_EVAL
);
2914 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2917 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2918 dest
= get_nir_dest(instr
->dest
);
2920 switch (instr
->intrinsic
) {
2921 case nir_intrinsic_load_primitive_id
:
2922 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2924 case nir_intrinsic_load_tess_coord
:
2925 /* gl_TessCoord is part of the payload in g1-3 */
2926 for (unsigned i
= 0; i
< 3; i
++) {
2927 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2931 case nir_intrinsic_load_input
:
2932 case nir_intrinsic_load_per_vertex_input
: {
2933 fs_reg indirect_offset
= get_indirect_offset(instr
);
2934 unsigned imm_offset
= instr
->const_index
[0];
2935 unsigned first_component
= nir_intrinsic_component(instr
);
2937 if (type_sz(dest
.type
) == 8) {
2938 first_component
= first_component
/ 2;
2942 if (indirect_offset
.file
== BAD_FILE
) {
2943 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2944 * which is 16 registers (since each holds 2 vec4 slots).
2946 unsigned slot_count
= 1;
2947 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2950 const unsigned max_push_slots
= 32;
2951 if (imm_offset
+ slot_count
<= max_push_slots
) {
2952 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2953 for (int i
= 0; i
< instr
->num_components
; i
++) {
2954 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2955 i
+ first_component
;
2956 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2959 tes_prog_data
->base
.urb_read_length
=
2960 MAX2(tes_prog_data
->base
.urb_read_length
,
2961 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2963 /* Replicate the patch handle to all enabled channels */
2964 const fs_reg srcs
[] = {
2965 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2967 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2968 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2970 if (first_component
!= 0) {
2971 unsigned read_components
=
2972 instr
->num_components
+ first_component
;
2973 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2974 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2976 inst
->size_written
= read_components
* REG_SIZE
;
2977 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2978 bld
.MOV(offset(dest
, bld
, i
),
2979 offset(tmp
, bld
, i
+ first_component
));
2982 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2984 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2987 inst
->offset
= imm_offset
;
2990 /* Indirect indexing - use per-slot offsets as well. */
2992 /* We can only read two double components with each URB read, so
2993 * we send two read messages in that case, each one loading up to
2994 * two double components.
2996 unsigned num_iterations
= 1;
2997 unsigned num_components
= instr
->num_components
;
2998 fs_reg orig_dest
= dest
;
2999 if (type_sz(dest
.type
) == 8) {
3000 if (instr
->num_components
> 2) {
3004 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3008 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3009 const fs_reg srcs
[] = {
3010 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3013 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3014 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3016 if (first_component
!= 0) {
3017 unsigned read_components
=
3018 num_components
+ first_component
;
3019 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3020 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3022 for (unsigned i
= 0; i
< num_components
; i
++) {
3023 bld
.MOV(offset(dest
, bld
, i
),
3024 offset(tmp
, bld
, i
+ first_component
));
3027 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3031 inst
->offset
= imm_offset
;
3032 inst
->size_written
= (num_components
+ first_component
) *
3033 inst
->dst
.component_size(inst
->exec_size
);
3035 /* If we are reading 64-bit data using 32-bit read messages we need
3036 * build proper 64-bit data elements by shuffling the low and high
3037 * 32-bit components around like we do for other things like UBOs
3040 if (type_sz(dest
.type
) == 8) {
3041 shuffle_from_32bit_read(bld
,
3042 offset(orig_dest
, bld
, iter
* 2),
3043 retype(dest
, BRW_REGISTER_TYPE_D
),
3047 /* If we are loading double data and we need a second read message
3050 if (num_iterations
> 1) {
3051 num_components
= instr
->num_components
- 2;
3059 nir_emit_intrinsic(bld
, instr
);
3065 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3066 nir_intrinsic_instr
*instr
)
3068 assert(stage
== MESA_SHADER_GEOMETRY
);
3069 fs_reg indirect_offset
;
3072 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3073 dest
= get_nir_dest(instr
->dest
);
3075 switch (instr
->intrinsic
) {
3076 case nir_intrinsic_load_primitive_id
:
3077 assert(stage
== MESA_SHADER_GEOMETRY
);
3078 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3079 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3080 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3083 case nir_intrinsic_load_input
:
3084 unreachable("load_input intrinsics are invalid for the GS stage");
3086 case nir_intrinsic_load_per_vertex_input
:
3087 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3088 instr
->src
[1], instr
->num_components
,
3089 nir_intrinsic_component(instr
));
3092 case nir_intrinsic_emit_vertex_with_counter
:
3093 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3096 case nir_intrinsic_end_primitive_with_counter
:
3097 emit_gs_end_primitive(instr
->src
[0]);
3100 case nir_intrinsic_set_vertex_count
:
3101 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3104 case nir_intrinsic_load_invocation_id
: {
3105 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3106 assert(val
.file
!= BAD_FILE
);
3107 dest
.type
= val
.type
;
3113 nir_emit_intrinsic(bld
, instr
);
3119 * Fetch the current render target layer index.
3122 fetch_render_target_array_index(const fs_builder
&bld
)
3124 if (bld
.shader
->devinfo
->gen
>= 6) {
3125 /* The render target array index is provided in the thread payload as
3126 * bits 26:16 of r0.0.
3128 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3129 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3133 /* Pre-SNB we only ever render into the first layer of the framebuffer
3134 * since layered rendering is not implemented.
3136 return brw_imm_ud(0);
3141 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3142 * framebuffer at the current fragment coordinates and sample index.
3145 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3148 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3150 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3151 const brw_wm_prog_key
*wm_key
=
3152 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3153 assert(!wm_key
->coherent_fb_fetch
);
3154 const struct brw_wm_prog_data
*wm_prog_data
=
3155 brw_wm_prog_data(stage_prog_data
);
3157 /* Calculate the surface index relative to the start of the texture binding
3158 * table block, since that's what the texturing messages expect.
3160 const unsigned surface
= target
+
3161 wm_prog_data
->binding_table
.render_target_read_start
-
3162 wm_prog_data
->base
.binding_table
.texture_start
;
3164 brw_mark_surface_used(
3165 bld
.shader
->stage_prog_data
,
3166 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3168 /* Calculate the fragment coordinates. */
3169 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3170 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3171 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3172 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3174 /* Calculate the sample index and MCS payload when multisampling. Luckily
3175 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3176 * shouldn't be necessary to recompile based on whether the framebuffer is
3179 if (wm_key
->multisample_fbo
&&
3180 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3181 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3183 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3184 const fs_reg mcs
= wm_key
->multisample_fbo
?
3185 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3187 /* Use either a normal or a CMS texel fetch message depending on whether
3188 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3189 * message just in case the framebuffer uses 16x multisampling, it should
3190 * be equivalent to the normal CMS fetch for lower multisampling modes.
3192 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3193 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3194 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3196 /* Emit the instruction. */
3197 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3199 brw_imm_ud(surface
), brw_imm_ud(0),
3200 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3201 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3203 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3204 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3210 * Actual coherent framebuffer read implemented using the native render target
3211 * read message. Requires SKL+.
3214 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3216 assert(bld
.shader
->devinfo
->gen
>= 9);
3217 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3218 inst
->target
= target
;
3219 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3225 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3227 if (n
&& regs
[0].file
!= BAD_FILE
) {
3231 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3233 for (unsigned i
= 0; i
< n
; i
++)
3241 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3243 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3244 const brw_wm_prog_key
*const key
=
3245 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3246 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3247 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3249 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3250 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3252 else if (l
== FRAG_RESULT_COLOR
)
3253 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3254 MAX2(key
->nr_color_regions
, 1));
3256 else if (l
== FRAG_RESULT_DEPTH
)
3257 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3259 else if (l
== FRAG_RESULT_STENCIL
)
3260 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3262 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3263 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3265 else if (l
>= FRAG_RESULT_DATA0
&&
3266 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3267 return alloc_temporary(v
->bld
, 4,
3268 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3271 unreachable("Invalid location");
3275 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3276 nir_intrinsic_instr
*instr
)
3278 assert(stage
== MESA_SHADER_FRAGMENT
);
3281 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3282 dest
= get_nir_dest(instr
->dest
);
3284 switch (instr
->intrinsic
) {
3285 case nir_intrinsic_load_front_face
:
3286 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3287 *emit_frontfacing_interpolation());
3290 case nir_intrinsic_load_sample_pos
: {
3291 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3292 assert(sample_pos
.file
!= BAD_FILE
);
3293 dest
.type
= sample_pos
.type
;
3294 bld
.MOV(dest
, sample_pos
);
3295 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3299 case nir_intrinsic_load_layer_id
:
3300 dest
.type
= BRW_REGISTER_TYPE_UD
;
3301 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3304 case nir_intrinsic_load_helper_invocation
:
3305 case nir_intrinsic_load_sample_mask_in
:
3306 case nir_intrinsic_load_sample_id
: {
3307 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3308 fs_reg val
= nir_system_values
[sv
];
3309 assert(val
.file
!= BAD_FILE
);
3310 dest
.type
= val
.type
;
3315 case nir_intrinsic_store_output
: {
3316 const fs_reg src
= get_nir_src(instr
->src
[0]);
3317 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3318 assert(const_offset
&& "Indirect output stores not allowed");
3319 const unsigned location
= nir_intrinsic_base(instr
) +
3320 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3321 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3324 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3325 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3326 offset(src
, bld
, j
));
3331 case nir_intrinsic_load_output
: {
3332 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3333 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3334 assert(l
>= FRAG_RESULT_DATA0
);
3335 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3336 assert(const_offset
&& "Indirect output loads not allowed");
3337 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3338 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3340 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3341 emit_coherent_fb_read(bld
, tmp
, target
);
3343 emit_non_coherent_fb_read(bld
, tmp
, target
);
3345 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3346 bld
.MOV(offset(dest
, bld
, j
),
3347 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3353 case nir_intrinsic_discard
:
3354 case nir_intrinsic_discard_if
: {
3355 /* We track our discarded pixels in f0.1. By predicating on it, we can
3356 * update just the flag bits that aren't yet discarded. If there's no
3357 * condition, we emit a CMP of g0 != g0, so all currently executing
3358 * channels will get turned off.
3361 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3362 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3363 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3365 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3366 BRW_REGISTER_TYPE_UW
));
3367 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3369 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3370 cmp
->flag_subreg
= 1;
3372 if (devinfo
->gen
>= 6) {
3373 emit_discard_jump();
3376 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3380 case nir_intrinsic_load_input
: {
3381 /* load_input is only used for flat inputs */
3382 unsigned base
= nir_intrinsic_base(instr
);
3383 unsigned comp
= nir_intrinsic_component(instr
);
3384 unsigned num_components
= instr
->num_components
;
3385 fs_reg orig_dest
= dest
;
3386 enum brw_reg_type type
= dest
.type
;
3388 /* Special case fields in the VUE header */
3389 if (base
== VARYING_SLOT_LAYER
)
3391 else if (base
== VARYING_SLOT_VIEWPORT
)
3394 if (nir_dest_bit_size(instr
->dest
) == 64) {
3395 /* const_index is in 32-bit type size units that could not be aligned
3396 * with DF. We need to read the double vector as if it was a float
3397 * vector of twice the number of components to fetch the right data.
3399 type
= BRW_REGISTER_TYPE_F
;
3400 num_components
*= 2;
3401 dest
= bld
.vgrf(type
, num_components
);
3404 for (unsigned int i
= 0; i
< num_components
; i
++) {
3405 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3406 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3409 if (nir_dest_bit_size(instr
->dest
) == 64) {
3410 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3411 instr
->num_components
);
3416 case nir_intrinsic_load_barycentric_pixel
:
3417 case nir_intrinsic_load_barycentric_centroid
:
3418 case nir_intrinsic_load_barycentric_sample
:
3419 /* Do nothing - load_interpolated_input handling will handle it later. */
3422 case nir_intrinsic_load_barycentric_at_sample
: {
3423 const glsl_interp_mode interpolation
=
3424 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3426 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3429 unsigned msg_data
= const_sample
->i32
[0] << 4;
3431 emit_pixel_interpolater_send(bld
,
3432 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3435 brw_imm_ud(msg_data
),
3438 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3439 BRW_REGISTER_TYPE_UD
);
3441 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3442 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3443 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3444 bld
.exec_all().group(1, 0)
3445 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3446 emit_pixel_interpolater_send(bld
,
3447 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3453 /* Make a loop that sends a message to the pixel interpolater
3454 * for the sample number in each live channel. If there are
3455 * multiple channels with the same sample number then these
3456 * will be handled simultaneously with a single interation of
3459 bld
.emit(BRW_OPCODE_DO
);
3461 /* Get the next live sample number into sample_id_reg */
3462 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3464 /* Set the flag register so that we can perform the send
3465 * message on all channels that have the same sample number
3467 bld
.CMP(bld
.null_reg_ud(),
3468 sample_src
, sample_id
,
3469 BRW_CONDITIONAL_EQ
);
3470 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3471 bld
.exec_all().group(1, 0)
3472 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3474 emit_pixel_interpolater_send(bld
,
3475 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3478 component(msg_data
, 0),
3480 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3482 /* Continue the loop if there are any live channels left */
3483 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3485 bld
.emit(BRW_OPCODE_WHILE
));
3491 case nir_intrinsic_load_barycentric_at_offset
: {
3492 const glsl_interp_mode interpolation
=
3493 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3495 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3498 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3499 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3501 emit_pixel_interpolater_send(bld
,
3502 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3505 brw_imm_ud(off_x
| (off_y
<< 4)),
3508 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3509 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3510 BRW_REGISTER_TYPE_F
);
3511 for (int i
= 0; i
< 2; i
++) {
3512 fs_reg temp
= vgrf(glsl_type::float_type
);
3513 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3514 fs_reg itemp
= vgrf(glsl_type::int_type
);
3516 bld
.MOV(itemp
, temp
);
3518 /* Clamp the upper end of the range to +7/16.
3519 * ARB_gpu_shader5 requires that we support a maximum offset
3520 * of +0.5, which isn't representable in a S0.4 value -- if
3521 * we didn't clamp it, we'd end up with -8/16, which is the
3522 * opposite of what the shader author wanted.
3524 * This is legal due to ARB_gpu_shader5's quantization
3527 * "Not all values of <offset> may be supported; x and y
3528 * offsets may be rounded to fixed-point values with the
3529 * number of fraction bits given by the
3530 * implementation-dependent constant
3531 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3533 set_condmod(BRW_CONDITIONAL_L
,
3534 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3537 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3538 emit_pixel_interpolater_send(bld
,
3548 case nir_intrinsic_load_interpolated_input
: {
3549 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3550 emit_fragcoord_interpolation(dest
);
3554 assert(instr
->src
[0].ssa
&&
3555 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3556 nir_intrinsic_instr
*bary_intrinsic
=
3557 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3558 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3559 enum glsl_interp_mode interp_mode
=
3560 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3563 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3564 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3565 /* Use the result of the PI message */
3566 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3568 /* Use the delta_xy values computed from the payload */
3569 enum brw_barycentric_mode bary
=
3570 brw_barycentric_mode(interp_mode
, bary_intrin
);
3572 dst_xy
= this->delta_xy
[bary
];
3575 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3577 component(interp_reg(nir_intrinsic_base(instr
),
3578 nir_intrinsic_component(instr
) + i
), 0);
3579 interp
.type
= BRW_REGISTER_TYPE_F
;
3580 dest
.type
= BRW_REGISTER_TYPE_F
;
3582 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3583 fs_reg tmp
= vgrf(glsl_type::float_type
);
3584 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3585 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3587 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3594 nir_emit_intrinsic(bld
, instr
);
3600 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3601 nir_intrinsic_instr
*instr
)
3603 assert(stage
== MESA_SHADER_COMPUTE
);
3604 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3607 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3608 dest
= get_nir_dest(instr
->dest
);
3610 switch (instr
->intrinsic
) {
3611 case nir_intrinsic_barrier
:
3613 cs_prog_data
->uses_barrier
= true;
3616 case nir_intrinsic_load_subgroup_id
:
3617 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3620 case nir_intrinsic_load_local_invocation_id
:
3621 case nir_intrinsic_load_work_group_id
: {
3622 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3623 fs_reg val
= nir_system_values
[sv
];
3624 assert(val
.file
!= BAD_FILE
);
3625 dest
.type
= val
.type
;
3626 for (unsigned i
= 0; i
< 3; i
++)
3627 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3631 case nir_intrinsic_load_num_work_groups
: {
3632 const unsigned surface
=
3633 cs_prog_data
->binding_table
.work_groups_start
;
3635 cs_prog_data
->uses_num_work_groups
= true;
3637 fs_reg surf_index
= brw_imm_ud(surface
);
3638 brw_mark_surface_used(prog_data
, surface
);
3640 /* Read the 3 GLuint components of gl_NumWorkGroups */
3641 for (unsigned i
= 0; i
< 3; i
++) {
3642 fs_reg read_result
=
3643 emit_untyped_read(bld
, surf_index
,
3645 1 /* dims */, 1 /* size */,
3646 BRW_PREDICATE_NONE
);
3647 read_result
.type
= dest
.type
;
3648 bld
.MOV(dest
, read_result
);
3649 dest
= offset(dest
, bld
, 1);
3654 case nir_intrinsic_shared_atomic_add
:
3655 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3657 case nir_intrinsic_shared_atomic_imin
:
3658 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3660 case nir_intrinsic_shared_atomic_umin
:
3661 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3663 case nir_intrinsic_shared_atomic_imax
:
3664 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3666 case nir_intrinsic_shared_atomic_umax
:
3667 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3669 case nir_intrinsic_shared_atomic_and
:
3670 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3672 case nir_intrinsic_shared_atomic_or
:
3673 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3675 case nir_intrinsic_shared_atomic_xor
:
3676 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3678 case nir_intrinsic_shared_atomic_exchange
:
3679 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3681 case nir_intrinsic_shared_atomic_comp_swap
:
3682 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3685 case nir_intrinsic_load_shared
: {
3686 assert(devinfo
->gen
>= 7);
3688 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3690 /* Get the offset to read from */
3692 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3694 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3696 offset_reg
= vgrf(glsl_type::uint_type
);
3698 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3699 brw_imm_ud(instr
->const_index
[0]));
3702 /* Read the vector */
3703 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3704 instr
->num_components
);
3708 case nir_intrinsic_store_shared
: {
3709 assert(devinfo
->gen
>= 7);
3712 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3715 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3718 unsigned writemask
= instr
->const_index
[1];
3720 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3721 * since the untyped writes below operate in units of 32-bits, which
3722 * means that we need to write twice as many components each time.
3723 * Also, we have to suffle 64-bit data to be in the appropriate layout
3724 * expected by our 32-bit write messages.
3726 unsigned type_size
= 4;
3727 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3729 val_reg
= shuffle_for_32bit_write(bld
, val_reg
, 0,
3730 instr
->num_components
);
3733 unsigned type_slots
= type_size
/ 4;
3735 /* Combine groups of consecutive enabled channels in one write
3736 * message. We use ffs to find the first enabled channel and then ffs on
3737 * the bit-inverse, down-shifted writemask to determine the length of
3738 * the block of enabled bits.
3741 unsigned first_component
= ffs(writemask
) - 1;
3742 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3744 /* We can't write more than 2 64-bit components at once. Limit the
3745 * length of the write to what we can do and let the next iteration
3749 length
= MIN2(2, length
);
3752 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3754 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3755 type_size
* first_component
);
3757 offset_reg
= vgrf(glsl_type::uint_type
);
3759 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3760 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3763 emit_untyped_write(bld
, surf_index
, offset_reg
,
3764 offset(val_reg
, bld
, first_component
* type_slots
),
3765 1 /* dims */, length
* type_slots
,
3766 BRW_PREDICATE_NONE
);
3768 /* Clear the bits in the writemask that we just wrote, then try
3769 * again to see if more channels are left.
3771 writemask
&= (15 << (first_component
+ length
));
3778 nir_emit_intrinsic(bld
, instr
);
3784 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3785 nir_op op
, brw_reg_type type
)
3787 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3788 switch (type_sz(type
)) {
3790 assert(type
!= BRW_REGISTER_TYPE_HF
);
3791 return retype(brw_imm_uw(value
.u16
[0]), type
);
3793 return retype(brw_imm_ud(value
.u32
[0]), type
);
3795 if (type
== BRW_REGISTER_TYPE_DF
)
3796 return setup_imm_df(bld
, value
.f64
[0]);
3798 return retype(brw_imm_u64(value
.u64
[0]), type
);
3800 unreachable("Invalid type size");
3805 brw_op_for_nir_reduction_op(nir_op op
)
3808 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3809 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3810 case nir_op_imul
: return BRW_OPCODE_MUL
;
3811 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3812 case nir_op_imin
: return BRW_OPCODE_SEL
;
3813 case nir_op_umin
: return BRW_OPCODE_SEL
;
3814 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3815 case nir_op_imax
: return BRW_OPCODE_SEL
;
3816 case nir_op_umax
: return BRW_OPCODE_SEL
;
3817 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3818 case nir_op_iand
: return BRW_OPCODE_AND
;
3819 case nir_op_ior
: return BRW_OPCODE_OR
;
3820 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3822 unreachable("Invalid reduction operation");
3826 static brw_conditional_mod
3827 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3830 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3831 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3832 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3833 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3834 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3835 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3836 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3837 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3838 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3839 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3840 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3841 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3842 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3844 unreachable("Invalid reduction operation");
3849 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3852 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3853 dest
= get_nir_dest(instr
->dest
);
3855 switch (instr
->intrinsic
) {
3856 case nir_intrinsic_image_deref_load
:
3857 case nir_intrinsic_image_deref_store
:
3858 case nir_intrinsic_image_deref_atomic_add
:
3859 case nir_intrinsic_image_deref_atomic_min
:
3860 case nir_intrinsic_image_deref_atomic_max
:
3861 case nir_intrinsic_image_deref_atomic_and
:
3862 case nir_intrinsic_image_deref_atomic_or
:
3863 case nir_intrinsic_image_deref_atomic_xor
:
3864 case nir_intrinsic_image_deref_atomic_exchange
:
3865 case nir_intrinsic_image_deref_atomic_comp_swap
: {
3866 using namespace image_access
;
3868 if (stage
== MESA_SHADER_FRAGMENT
&&
3869 instr
->intrinsic
!= nir_intrinsic_image_deref_load
)
3870 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3872 /* Get the referenced image variable and type. */
3873 nir_deref_instr
*deref
= nir_src_as_deref(instr
->src
[0]);
3874 const nir_variable
*var
= nir_deref_instr_get_variable(deref
);
3875 const glsl_type
*type
= var
->type
->without_array();
3876 const brw_reg_type base_type
= get_image_base_type(type
);
3878 /* Get some metadata from the image intrinsic. */
3879 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3880 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3881 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3882 const unsigned format
= var
->data
.image
.format
;
3883 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3885 /* Get the arguments of the image intrinsic. */
3886 const fs_reg image
= get_nir_image_deref(deref
);
3887 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3888 BRW_REGISTER_TYPE_UD
);
3889 const fs_reg src0
= (info
->num_srcs
>= 4 ?
3890 retype(get_nir_src(instr
->src
[3]), base_type
) :
3892 const fs_reg src1
= (info
->num_srcs
>= 5 ?
3893 retype(get_nir_src(instr
->src
[4]), base_type
) :
3897 /* Emit an image load, store or atomic op. */
3898 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
)
3899 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3901 else if (instr
->intrinsic
== nir_intrinsic_image_deref_store
)
3902 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3903 var
->data
.image
.write_only
? GL_NONE
: format
);
3906 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3907 surf_dims
, arr_dims
, dest_components
,
3908 get_image_atomic_op(instr
->intrinsic
, type
));
3910 /* Assign the result. */
3911 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3912 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3913 offset(tmp
, bld
, c
));
3918 case nir_intrinsic_memory_barrier_atomic_counter
:
3919 case nir_intrinsic_memory_barrier_buffer
:
3920 case nir_intrinsic_memory_barrier_image
:
3921 case nir_intrinsic_memory_barrier
: {
3922 const fs_builder ubld
= bld
.group(8, 0);
3923 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3924 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3925 ->size_written
= 2 * REG_SIZE
;
3929 case nir_intrinsic_group_memory_barrier
:
3930 case nir_intrinsic_memory_barrier_shared
:
3931 /* We treat these workgroup-level barriers as no-ops. This should be
3932 * safe at present and as long as:
3934 * - Memory access instructions are not subsequently reordered by the
3935 * compiler back-end.
3937 * - All threads from a given compute shader workgroup fit within a
3938 * single subslice and therefore talk to the same HDC shared unit
3939 * what supposedly guarantees ordering and coherency between threads
3940 * from the same workgroup. This may change in the future when we
3941 * start splitting workgroups across multiple subslices.
3943 * - The context is not in fault-and-stream mode, which could cause
3944 * memory transactions (including to SLM) prior to the barrier to be
3945 * replayed after the barrier if a pagefault occurs. This shouldn't
3946 * be a problem up to and including SKL because fault-and-stream is
3947 * not usable due to hardware issues, but that's likely to change in
3952 case nir_intrinsic_shader_clock
: {
3953 /* We cannot do anything if there is an event, so ignore it for now */
3954 const fs_reg shader_clock
= get_timestamp(bld
);
3955 const fs_reg srcs
[] = { component(shader_clock
, 0),
3956 component(shader_clock
, 1) };
3957 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3961 case nir_intrinsic_image_deref_size
: {
3962 /* Get the referenced image variable and type. */
3963 nir_deref_instr
*deref
= nir_src_as_deref(instr
->src
[0]);
3964 const nir_variable
*var
= nir_deref_instr_get_variable(deref
);
3965 const glsl_type
*type
= var
->type
->without_array();
3967 /* Get the size of the image. */
3968 const fs_reg image
= get_nir_image_deref(deref
);
3969 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3971 /* For 1DArray image types, the array index is stored in the Z component.
3972 * Fix this by swizzling the Z component to the Y component.
3974 const bool is_1d_array_image
=
3975 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3976 type
->sampler_array
;
3978 /* For CubeArray images, we should count the number of cubes instead
3979 * of the number of faces. Fix it by dividing the (Z component) by 6.
3981 const bool is_cube_array_image
=
3982 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3983 type
->sampler_array
;
3985 /* Copy all the components. */
3986 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3987 if ((int)c
>= type
->coordinate_components()) {
3988 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3990 } else if (c
== 1 && is_1d_array_image
) {
3991 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3992 offset(size
, bld
, 2));
3993 } else if (c
== 2 && is_cube_array_image
) {
3994 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3995 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3996 offset(size
, bld
, c
), brw_imm_d(6));
3998 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3999 offset(size
, bld
, c
));
4006 case nir_intrinsic_image_deref_samples
:
4007 /* The driver does not support multi-sampled images. */
4008 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4011 case nir_intrinsic_load_uniform
: {
4012 /* Offsets are in bytes but they should always aligned to
4015 assert(instr
->const_index
[0] % 4 == 0 ||
4016 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4018 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4020 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4022 assert(const_offset
->u32
[0] % type_sz(dest
.type
) == 0);
4023 /* For 16-bit types we add the module of the const_index[0]
4024 * offset to access to not 32-bit aligned element
4026 src
.offset
= const_offset
->u32
[0] + instr
->const_index
[0] % 4;
4028 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4029 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4032 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4033 BRW_REGISTER_TYPE_UD
);
4035 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4036 * go past the end of the uniform. In order to keep the n'th
4037 * component from running past, we subtract off the size of all but
4038 * one component of the vector.
4040 assert(instr
->const_index
[1] >=
4041 instr
->num_components
* (int) type_sz(dest
.type
));
4042 unsigned read_size
= instr
->const_index
[1] -
4043 (instr
->num_components
- 1) * type_sz(dest
.type
);
4045 bool supports_64bit_indirects
=
4046 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4048 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4049 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4050 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4051 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4052 indirect
, brw_imm_ud(read_size
));
4055 const unsigned num_mov_indirects
=
4056 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4057 /* We read a little bit less per MOV INDIRECT, as they are now
4058 * 32-bits ones instead of 64-bit. Fix read_size then.
4060 const unsigned read_size_32bit
= read_size
-
4061 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4062 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4063 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4064 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4065 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4066 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4067 indirect
, brw_imm_ud(read_size_32bit
));
4075 case nir_intrinsic_load_ubo
: {
4076 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4080 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4081 const_index
->u32
[0];
4082 surf_index
= brw_imm_ud(index
);
4083 brw_mark_surface_used(prog_data
, index
);
4085 /* The block index is not a constant. Evaluate the index expression
4086 * per-channel and add the base UBO index; we have to select a value
4087 * from any live channel.
4089 surf_index
= vgrf(glsl_type::uint_type
);
4090 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4091 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4092 surf_index
= bld
.emit_uniformize(surf_index
);
4094 /* Assume this may touch any UBO. It would be nice to provide
4095 * a tighter bound, but the array information is already lowered away.
4097 brw_mark_surface_used(prog_data
,
4098 stage_prog_data
->binding_table
.ubo_start
+
4099 nir
->info
.num_ubos
- 1);
4102 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4103 if (const_offset
== NULL
) {
4104 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4105 BRW_REGISTER_TYPE_UD
);
4107 for (int i
= 0; i
< instr
->num_components
; i
++)
4108 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4109 base_offset
, i
* type_sz(dest
.type
));
4111 /* Even if we are loading doubles, a pull constant load will load
4112 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4113 * need to load a full dvec4 we will have to emit 2 loads. This is
4114 * similar to demote_pull_constants(), except that in that case we
4115 * see individual accesses to each component of the vector and then
4116 * we let CSE deal with duplicate loads. Here we see a vector access
4117 * and we have to split it if necessary.
4119 const unsigned type_size
= type_sz(dest
.type
);
4121 /* See if we've selected this as a push constant candidate */
4123 const unsigned ubo_block
= const_index
->u32
[0];
4124 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
4127 for (int i
= 0; i
< 4; i
++) {
4128 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4129 if (range
->block
== ubo_block
&&
4130 offset_256b
>= range
->start
&&
4131 offset_256b
< range
->start
+ range
->length
) {
4133 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4134 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
4139 if (push_reg
.file
!= BAD_FILE
) {
4140 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4141 bld
.MOV(offset(dest
, bld
, i
),
4142 byte_offset(push_reg
, i
* type_size
));
4148 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4149 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4150 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4152 for (unsigned c
= 0; c
< instr
->num_components
;) {
4153 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4154 /* Number of usable components in the next block-aligned load. */
4155 const unsigned count
= MIN2(instr
->num_components
- c
,
4156 (block_sz
- base
% block_sz
) / type_size
);
4158 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4159 packed_consts
, surf_index
,
4160 brw_imm_ud(base
& ~(block_sz
- 1)));
4162 const fs_reg consts
=
4163 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4166 for (unsigned d
= 0; d
< count
; d
++)
4167 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4175 case nir_intrinsic_load_ssbo
: {
4176 assert(devinfo
->gen
>= 7);
4178 nir_const_value
*const_uniform_block
=
4179 nir_src_as_const_value(instr
->src
[0]);
4182 if (const_uniform_block
) {
4183 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4184 const_uniform_block
->u32
[0];
4185 surf_index
= brw_imm_ud(index
);
4186 brw_mark_surface_used(prog_data
, index
);
4188 surf_index
= vgrf(glsl_type::uint_type
);
4189 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4190 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4192 /* Assume this may touch any UBO. It would be nice to provide
4193 * a tighter bound, but the array information is already lowered away.
4195 brw_mark_surface_used(prog_data
,
4196 stage_prog_data
->binding_table
.ssbo_start
+
4197 nir
->info
.num_ssbos
- 1);
4201 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4203 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4205 offset_reg
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
);
4208 /* Read the vector */
4209 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4210 instr
->num_components
);
4215 case nir_intrinsic_store_ssbo
: {
4216 assert(devinfo
->gen
>= 7);
4218 if (stage
== MESA_SHADER_FRAGMENT
)
4219 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4223 nir_const_value
*const_uniform_block
=
4224 nir_src_as_const_value(instr
->src
[1]);
4225 if (const_uniform_block
) {
4226 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4227 const_uniform_block
->u32
[0];
4228 surf_index
= brw_imm_ud(index
);
4229 brw_mark_surface_used(prog_data
, index
);
4231 surf_index
= vgrf(glsl_type::uint_type
);
4232 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4233 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4235 brw_mark_surface_used(prog_data
,
4236 stage_prog_data
->binding_table
.ssbo_start
+
4237 nir
->info
.num_ssbos
- 1);
4241 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4244 unsigned writemask
= instr
->const_index
[0];
4246 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4247 * since the untyped writes below operate in units of 32-bits, which
4248 * means that we need to write twice as many components each time.
4249 * Also, we have to suffle 64-bit data to be in the appropriate layout
4250 * expected by our 32-bit write messages.
4252 unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4253 unsigned type_size
= bit_size
/ 8;
4255 /* Combine groups of consecutive enabled channels in one write
4256 * message. We use ffs to find the first enabled channel and then ffs on
4257 * the bit-inverse, down-shifted writemask to determine the num_components
4258 * of the block of enabled bits.
4261 unsigned first_component
= ffs(writemask
) - 1;
4262 unsigned num_components
= ffs(~(writemask
>> first_component
)) - 1;
4263 fs_reg write_src
= offset(val_reg
, bld
, first_component
);
4265 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4267 if (type_size
> 4) {
4268 /* We can't write more than 2 64-bit components at once. Limit
4269 * the num_components of the write to what we can do and let the next
4270 * iteration handle the rest.
4272 num_components
= MIN2(2, num_components
);
4273 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4275 } else if (type_size
< 4) {
4276 assert(type_size
== 2);
4277 /* For 16-bit types we pack two consecutive values into a 32-bit
4278 * word and use an untyped write message. For single values or not
4279 * 32-bit-aligned we need to use byte-scattered writes because
4280 * untyped writes works with 32-bit components with 32-bit
4281 * alignment. byte_scattered_write messages only support one
4282 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4283 * could be enabled we can not guarantee that not constant offsets
4284 * to be 32-bit aligned for 16-bit types. For example an array, of
4285 * 16-bit vec3 with array element stride of 6.
4287 * In the case of 32-bit aligned constant offsets if there is
4288 * a 3-components vector we submit one untyped-write message
4289 * of 32-bit (first two components), and one byte-scattered
4290 * write message (the last component).
4293 if ( !const_offset
|| ((const_offset
->u32
[0] +
4294 type_size
* first_component
) % 4)) {
4295 /* If we use a .yz writemask we also need to emit 2
4296 * byte-scattered write messages because of y-component not
4297 * being aligned to 32-bit.
4300 } else if (num_components
> 2 && (num_components
% 2)) {
4301 /* If there is an odd number of consecutive components we left
4302 * the not paired component for a following emit of length == 1
4303 * with byte_scattered_write.
4307 /* For num_components == 1 we are also shuffling the component
4308 * because byte scattered writes of 16-bit need values to be dword
4309 * aligned. Shuffling only one component would be the same as
4312 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4319 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4320 type_size
* first_component
);
4322 offset_reg
= vgrf(glsl_type::uint_type
);
4324 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4325 brw_imm_ud(type_size
* first_component
));
4328 if (type_size
< 4 && num_components
== 1) {
4329 assert(type_size
== 2);
4330 /* Untyped Surface messages have a fixed 32-bit size, so we need
4331 * to rely on byte scattered in order to write 16-bit elements.
4332 * The byte_scattered_write message needs that every written 16-bit
4333 * type to be aligned 32-bits (stride=2).
4335 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4339 BRW_PREDICATE_NONE
);
4341 assert(num_components
* type_size
<= 16);
4342 assert((num_components
* type_size
) % 4 == 0);
4343 assert(offset_reg
.file
!= BRW_IMMEDIATE_VALUE
||
4344 offset_reg
.ud
% 4 == 0);
4345 unsigned num_slots
= (num_components
* type_size
) / 4;
4347 emit_untyped_write(bld
, surf_index
, offset_reg
,
4349 1 /* dims */, num_slots
,
4350 BRW_PREDICATE_NONE
);
4353 /* Clear the bits in the writemask that we just wrote, then try
4354 * again to see if more channels are left.
4356 writemask
&= (15 << (first_component
+ num_components
));
4361 case nir_intrinsic_store_output
: {
4362 fs_reg src
= get_nir_src(instr
->src
[0]);
4364 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4365 assert(const_offset
&& "Indirect output stores not allowed");
4367 unsigned num_components
= instr
->num_components
;
4368 unsigned first_component
= nir_intrinsic_component(instr
);
4369 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4370 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4371 num_components
*= 2;
4374 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4375 4 * const_offset
->u32
[0]), src
.type
);
4376 for (unsigned j
= 0; j
< num_components
; j
++) {
4377 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4378 offset(src
, bld
, j
));
4383 case nir_intrinsic_ssbo_atomic_add
:
4384 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4386 case nir_intrinsic_ssbo_atomic_imin
:
4387 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4389 case nir_intrinsic_ssbo_atomic_umin
:
4390 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4392 case nir_intrinsic_ssbo_atomic_imax
:
4393 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4395 case nir_intrinsic_ssbo_atomic_umax
:
4396 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4398 case nir_intrinsic_ssbo_atomic_and
:
4399 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4401 case nir_intrinsic_ssbo_atomic_or
:
4402 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4404 case nir_intrinsic_ssbo_atomic_xor
:
4405 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4407 case nir_intrinsic_ssbo_atomic_exchange
:
4408 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4410 case nir_intrinsic_ssbo_atomic_comp_swap
:
4411 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4414 case nir_intrinsic_get_buffer_size
: {
4415 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4416 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4418 /* A resinfo's sampler message is used to get the buffer size. The
4419 * SIMD8's writeback message consists of four registers and SIMD16's
4420 * writeback message consists of 8 destination registers (two per each
4421 * component). Because we are only interested on the first channel of
4422 * the first returned component, where resinfo returns the buffer size
4423 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4424 * the dispatch width.
4426 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4427 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4428 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4431 ubld
.MOV(src_payload
, brw_imm_d(0));
4433 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4434 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4435 src_payload
, brw_imm_ud(index
));
4436 inst
->header_size
= 0;
4438 inst
->size_written
= 4 * REG_SIZE
;
4440 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4442 * "Out-of-bounds checking is always performed at a DWord granularity. If
4443 * any part of the DWord is out-of-bounds then the whole DWord is
4444 * considered out-of-bounds."
4446 * This implies that types with size smaller than 4-bytes need to be
4447 * padded if they don't complete the last dword of the buffer. But as we
4448 * need to maintain the original size we need to reverse the padding
4449 * calculation to return the correct size to know the number of elements
4450 * of an unsized array. As we stored in the last two bits of the surface
4451 * size the needed padding for the buffer, we calculate here the
4452 * original buffer_size reversing the surface_size calculation:
4454 * surface_size = isl_align(buffer_size, 4) +
4455 * (isl_align(buffer_size) - buffer_size)
4457 * buffer_size = surface_size & ~3 - surface_size & 3
4460 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4461 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4462 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4464 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4465 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4466 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4468 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4470 brw_mark_surface_used(prog_data
, index
);
4474 case nir_intrinsic_load_subgroup_invocation
:
4475 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4476 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4479 case nir_intrinsic_load_subgroup_eq_mask
:
4480 case nir_intrinsic_load_subgroup_ge_mask
:
4481 case nir_intrinsic_load_subgroup_gt_mask
:
4482 case nir_intrinsic_load_subgroup_le_mask
:
4483 case nir_intrinsic_load_subgroup_lt_mask
:
4484 unreachable("not reached");
4486 case nir_intrinsic_vote_any
: {
4487 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4489 /* The any/all predicates do not consider channel enables. To prevent
4490 * dead channels from affecting the result, we initialize the flag with
4491 * with the identity value for the logical operation.
4493 if (dispatch_width
== 32) {
4494 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4495 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4498 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4500 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4502 /* For some reason, the any/all predicates don't work properly with
4503 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4504 * doesn't read the correct subset of the flag register and you end up
4505 * getting garbage in the second half. Work around this by using a pair
4506 * of 1-wide MOVs and scattering the result.
4508 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4509 ubld
.MOV(res1
, brw_imm_d(0));
4510 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4511 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4512 BRW_PREDICATE_ALIGN1_ANY32H
,
4513 ubld
.MOV(res1
, brw_imm_d(-1)));
4515 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4518 case nir_intrinsic_vote_all
: {
4519 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4521 /* The any/all predicates do not consider channel enables. To prevent
4522 * dead channels from affecting the result, we initialize the flag with
4523 * with the identity value for the logical operation.
4525 if (dispatch_width
== 32) {
4526 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4527 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4528 brw_imm_ud(0xffffffff));
4530 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4532 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4534 /* For some reason, the any/all predicates don't work properly with
4535 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4536 * doesn't read the correct subset of the flag register and you end up
4537 * getting garbage in the second half. Work around this by using a pair
4538 * of 1-wide MOVs and scattering the result.
4540 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4541 ubld
.MOV(res1
, brw_imm_d(0));
4542 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4543 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4544 BRW_PREDICATE_ALIGN1_ALL32H
,
4545 ubld
.MOV(res1
, brw_imm_d(-1)));
4547 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4550 case nir_intrinsic_vote_feq
:
4551 case nir_intrinsic_vote_ieq
: {
4552 fs_reg value
= get_nir_src(instr
->src
[0]);
4553 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4554 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4555 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4558 fs_reg uniformized
= bld
.emit_uniformize(value
);
4559 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4561 /* The any/all predicates do not consider channel enables. To prevent
4562 * dead channels from affecting the result, we initialize the flag with
4563 * with the identity value for the logical operation.
4565 if (dispatch_width
== 32) {
4566 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4567 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4568 brw_imm_ud(0xffffffff));
4570 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4572 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4574 /* For some reason, the any/all predicates don't work properly with
4575 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4576 * doesn't read the correct subset of the flag register and you end up
4577 * getting garbage in the second half. Work around this by using a pair
4578 * of 1-wide MOVs and scattering the result.
4580 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4581 ubld
.MOV(res1
, brw_imm_d(0));
4582 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4583 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4584 BRW_PREDICATE_ALIGN1_ALL32H
,
4585 ubld
.MOV(res1
, brw_imm_d(-1)));
4587 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4591 case nir_intrinsic_ballot
: {
4592 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4593 BRW_REGISTER_TYPE_UD
);
4594 struct brw_reg flag
= brw_flag_reg(0, 0);
4595 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4596 * as f0.0. This is a problem for fragment programs as we currently use
4597 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4598 * programs yet so this isn't a problem. When we do, something will
4601 if (dispatch_width
== 32)
4602 flag
.type
= BRW_REGISTER_TYPE_UD
;
4604 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4605 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4607 if (instr
->dest
.ssa
.bit_size
> 32) {
4608 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4610 dest
.type
= BRW_REGISTER_TYPE_UD
;
4612 bld
.MOV(dest
, flag
);
4616 case nir_intrinsic_read_invocation
: {
4617 const fs_reg value
= get_nir_src(instr
->src
[0]);
4618 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4619 fs_reg tmp
= bld
.vgrf(value
.type
);
4621 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4622 bld
.emit_uniformize(invocation
));
4624 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4628 case nir_intrinsic_read_first_invocation
: {
4629 const fs_reg value
= get_nir_src(instr
->src
[0]);
4630 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4634 case nir_intrinsic_shuffle
: {
4635 const fs_reg value
= get_nir_src(instr
->src
[0]);
4636 const fs_reg index
= get_nir_src(instr
->src
[1]);
4638 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4642 case nir_intrinsic_first_invocation
: {
4643 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4644 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4645 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4646 fs_reg(component(tmp
, 0)));
4650 case nir_intrinsic_quad_broadcast
: {
4651 const fs_reg value
= get_nir_src(instr
->src
[0]);
4652 nir_const_value
*index
= nir_src_as_const_value(instr
->src
[1]);
4653 assert(nir_src_bit_size(instr
->src
[1]) == 32);
4655 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4656 value
, brw_imm_ud(index
->u32
[0]), brw_imm_ud(4));
4660 case nir_intrinsic_quad_swap_horizontal
: {
4661 const fs_reg value
= get_nir_src(instr
->src
[0]);
4662 const fs_reg tmp
= bld
.vgrf(value
.type
);
4663 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4665 const fs_reg src_left
= horiz_stride(value
, 2);
4666 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4667 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4668 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4670 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4672 * "When source or destination datatype is 64b or operation is
4673 * integer DWord multiply, regioning in Align1 must follow
4678 * 3. Source and Destination offset must be the same, except
4679 * the case of scalar source."
4681 * In order to work around this, we have to emit two 32-bit MOVs instead
4682 * of a single 64-bit MOV to do the shuffle.
4684 if (type_sz(value
.type
) > 4 &&
4685 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4686 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4687 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4688 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4689 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4690 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4691 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4692 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4693 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4695 ubld
.MOV(tmp_left
, src_right
);
4696 ubld
.MOV(tmp_right
, src_left
);
4698 bld
.MOV(retype(dest
, value
.type
), tmp
);
4702 case nir_intrinsic_quad_swap_vertical
: {
4703 const fs_reg value
= get_nir_src(instr
->src
[0]);
4704 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4705 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4706 const fs_reg tmp
= bld
.vgrf(value
.type
);
4707 const fs_builder ubld
= bld
.exec_all();
4708 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4709 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4710 bld
.MOV(retype(dest
, value
.type
), tmp
);
4712 /* For larger data types, we have to either emit dispatch_width many
4713 * MOVs or else fall back to doing indirects.
4715 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4716 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4718 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4723 case nir_intrinsic_quad_swap_diagonal
: {
4724 const fs_reg value
= get_nir_src(instr
->src
[0]);
4725 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4726 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4727 const fs_reg tmp
= bld
.vgrf(value
.type
);
4728 const fs_builder ubld
= bld
.exec_all();
4729 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4730 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4731 bld
.MOV(retype(dest
, value
.type
), tmp
);
4733 /* For larger data types, we have to either emit dispatch_width many
4734 * MOVs or else fall back to doing indirects.
4736 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4737 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4739 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4744 case nir_intrinsic_reduce
: {
4745 fs_reg src
= get_nir_src(instr
->src
[0]);
4746 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4747 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4748 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4749 cluster_size
= dispatch_width
;
4751 /* Figure out the source type */
4752 src
.type
= brw_type_for_nir_type(devinfo
,
4753 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4754 nir_src_bit_size(instr
->src
[0])));
4756 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4757 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4758 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4760 /* Set up a register for all of our scratching around and initialize it
4761 * to reduction operation's identity value.
4763 fs_reg scan
= bld
.vgrf(src
.type
);
4764 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4766 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4768 dest
.type
= src
.type
;
4769 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4770 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4771 * the distance between clusters is at least 2 GRFs. In this case,
4772 * we don't need the weird striding of the CLUSTER_BROADCAST
4773 * instruction and can just do regular MOVs.
4775 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4776 const unsigned groups
=
4777 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4778 const unsigned group_size
= dispatch_width
/ groups
;
4779 for (unsigned i
= 0; i
< groups
; i
++) {
4780 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4781 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4782 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4783 component(scan
, comp
));
4786 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4787 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4792 case nir_intrinsic_inclusive_scan
:
4793 case nir_intrinsic_exclusive_scan
: {
4794 fs_reg src
= get_nir_src(instr
->src
[0]);
4795 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4797 /* Figure out the source type */
4798 src
.type
= brw_type_for_nir_type(devinfo
,
4799 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4800 nir_src_bit_size(instr
->src
[0])));
4802 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4803 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4804 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4806 /* Set up a register for all of our scratching around and initialize it
4807 * to reduction operation's identity value.
4809 fs_reg scan
= bld
.vgrf(src
.type
);
4810 const fs_builder allbld
= bld
.exec_all();
4811 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4813 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4814 /* Exclusive scan is a bit harder because we have to do an annoying
4815 * shift of the contents before we can begin. To make things worse,
4816 * we can't do this with a normal stride; we have to use indirects.
4818 fs_reg shifted
= bld
.vgrf(src
.type
);
4819 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4820 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4822 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4823 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4827 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4829 bld
.MOV(retype(dest
, src
.type
), scan
);
4833 case nir_intrinsic_begin_invocation_interlock
: {
4834 const fs_builder ubld
= bld
.group(8, 0);
4835 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4837 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4843 case nir_intrinsic_end_invocation_interlock
: {
4844 /* We don't need to do anything here */
4849 unreachable("unknown intrinsic");
4854 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4855 int op
, nir_intrinsic_instr
*instr
)
4857 if (stage
== MESA_SHADER_FRAGMENT
)
4858 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4861 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4862 dest
= get_nir_dest(instr
->dest
);
4865 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4866 if (const_surface
) {
4867 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4868 const_surface
->u32
[0];
4869 surface
= brw_imm_ud(surf_index
);
4870 brw_mark_surface_used(prog_data
, surf_index
);
4872 surface
= vgrf(glsl_type::uint_type
);
4873 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4874 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4876 /* Assume this may touch any SSBO. This is the same we do for other
4877 * UBO/SSBO accesses with non-constant surface.
4879 brw_mark_surface_used(prog_data
,
4880 stage_prog_data
->binding_table
.ssbo_start
+
4881 nir
->info
.num_ssbos
- 1);
4884 fs_reg offset
= get_nir_src(instr
->src
[1]);
4885 fs_reg data1
= get_nir_src(instr
->src
[2]);
4887 if (op
== BRW_AOP_CMPWR
)
4888 data2
= get_nir_src(instr
->src
[3]);
4890 /* Emit the actual atomic operation */
4892 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4894 1 /* dims */, 1 /* rsize */,
4896 BRW_PREDICATE_NONE
);
4897 dest
.type
= atomic_result
.type
;
4898 bld
.MOV(dest
, atomic_result
);
4902 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4903 int op
, nir_intrinsic_instr
*instr
)
4906 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4907 dest
= get_nir_dest(instr
->dest
);
4909 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4911 fs_reg data1
= get_nir_src(instr
->src
[1]);
4913 if (op
== BRW_AOP_CMPWR
)
4914 data2
= get_nir_src(instr
->src
[2]);
4916 /* Get the offset */
4917 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4919 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4921 offset
= vgrf(glsl_type::uint_type
);
4923 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4924 brw_imm_ud(instr
->const_index
[0]));
4927 /* Emit the actual atomic operation operation */
4929 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4931 1 /* dims */, 1 /* rsize */,
4933 BRW_PREDICATE_NONE
);
4934 dest
.type
= atomic_result
.type
;
4935 bld
.MOV(dest
, atomic_result
);
4939 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4941 unsigned texture
= instr
->texture_index
;
4942 unsigned sampler
= instr
->sampler_index
;
4944 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4946 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4947 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4949 int lod_components
= 0;
4951 /* The hardware requires a LOD for buffer textures */
4952 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4953 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4955 uint32_t header_bits
= 0;
4956 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4957 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4958 switch (instr
->src
[i
].src_type
) {
4959 case nir_tex_src_bias
:
4960 srcs
[TEX_LOGICAL_SRC_LOD
] =
4961 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4963 case nir_tex_src_comparator
:
4964 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4966 case nir_tex_src_coord
:
4967 switch (instr
->op
) {
4969 case nir_texop_txf_ms
:
4970 case nir_texop_txf_ms_mcs
:
4971 case nir_texop_samples_identical
:
4972 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4975 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4979 case nir_tex_src_ddx
:
4980 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4981 lod_components
= nir_tex_instr_src_size(instr
, i
);
4983 case nir_tex_src_ddy
:
4984 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4986 case nir_tex_src_lod
:
4987 switch (instr
->op
) {
4989 srcs
[TEX_LOGICAL_SRC_LOD
] =
4990 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4993 srcs
[TEX_LOGICAL_SRC_LOD
] =
4994 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4997 srcs
[TEX_LOGICAL_SRC_LOD
] =
4998 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5002 case nir_tex_src_ms_index
:
5003 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5006 case nir_tex_src_offset
: {
5007 nir_const_value
*const_offset
=
5008 nir_src_as_const_value(instr
->src
[i
].src
);
5009 unsigned offset_bits
= 0;
5011 brw_texture_offset(const_offset
->i32
,
5012 nir_tex_instr_src_size(instr
, i
),
5014 header_bits
|= offset_bits
;
5016 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5017 retype(src
, BRW_REGISTER_TYPE_D
);
5022 case nir_tex_src_projector
:
5023 unreachable("should be lowered");
5025 case nir_tex_src_texture_offset
: {
5026 /* Figure out the highest possible texture index and mark it as used */
5027 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
5028 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
5029 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
5031 max_used
+= stage_prog_data
->binding_table
.texture_start
;
5033 brw_mark_surface_used(prog_data
, max_used
);
5035 /* Emit code to evaluate the actual indexing expression */
5036 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5037 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5038 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5042 case nir_tex_src_sampler_offset
: {
5043 /* Emit code to evaluate the actual indexing expression */
5044 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5045 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5046 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5050 case nir_tex_src_ms_mcs
:
5051 assert(instr
->op
== nir_texop_txf_ms
);
5052 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5055 case nir_tex_src_plane
: {
5056 nir_const_value
*const_plane
=
5057 nir_src_as_const_value(instr
->src
[i
].src
);
5058 const uint32_t plane
= const_plane
->u32
[0];
5059 const uint32_t texture_index
=
5060 instr
->texture_index
+
5061 stage_prog_data
->binding_table
.plane_start
[plane
] -
5062 stage_prog_data
->binding_table
.texture_start
;
5064 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5069 unreachable("unknown texture source");
5073 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5074 (instr
->op
== nir_texop_txf_ms
||
5075 instr
->op
== nir_texop_samples_identical
)) {
5076 if (devinfo
->gen
>= 7 &&
5077 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5078 srcs
[TEX_LOGICAL_SRC_MCS
] =
5079 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5080 instr
->coord_components
,
5081 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5083 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5087 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5088 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5091 switch (instr
->op
) {
5093 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5094 SHADER_OPCODE_TXL_LOGICAL
);
5097 opcode
= FS_OPCODE_TXB_LOGICAL
;
5100 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5103 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5106 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5108 case nir_texop_txf_ms
:
5109 if ((key_tex
->msaa_16
& (1 << sampler
)))
5110 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5112 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5114 case nir_texop_txf_ms_mcs
:
5115 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5117 case nir_texop_query_levels
:
5119 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5122 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5125 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5126 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5128 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5130 case nir_texop_texture_samples
:
5131 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5133 case nir_texop_samples_identical
: {
5134 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5136 /* If mcs is an immediate value, it means there is no MCS. In that case
5137 * just return false.
5139 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5140 bld
.MOV(dst
, brw_imm_ud(0u));
5141 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5142 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5143 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5144 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5145 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5147 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5148 BRW_CONDITIONAL_EQ
);
5153 unreachable("unknown texture opcode");
5156 if (instr
->op
== nir_texop_tg4
) {
5157 if (instr
->component
== 1 &&
5158 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5159 /* gather4 sampler is broken for green channel on RG32F --
5160 * we must ask for blue instead.
5162 header_bits
|= 2 << 16;
5164 header_bits
|= instr
->component
<< 16;
5168 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5169 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5170 inst
->offset
= header_bits
;
5172 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5173 if (devinfo
->gen
>= 9 &&
5174 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5175 unsigned write_mask
= instr
->dest
.is_ssa
?
5176 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5177 (1 << dest_size
) - 1;
5178 assert(write_mask
!= 0); /* dead code should have been eliminated */
5179 inst
->size_written
= util_last_bit(write_mask
) *
5180 inst
->dst
.component_size(inst
->exec_size
);
5182 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5185 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5186 inst
->shadow_compare
= true;
5188 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5189 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5192 for (unsigned i
= 0; i
< dest_size
; i
++)
5193 nir_dest
[i
] = offset(dst
, bld
, i
);
5195 if (instr
->op
== nir_texop_query_levels
) {
5196 /* # levels is in .w */
5197 nir_dest
[0] = offset(dst
, bld
, 3);
5198 } else if (instr
->op
== nir_texop_txs
&&
5199 dest_size
>= 3 && devinfo
->gen
< 7) {
5200 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5201 fs_reg depth
= offset(dst
, bld
, 2);
5202 nir_dest
[2] = vgrf(glsl_type::int_type
);
5203 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5206 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5210 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5212 switch (instr
->type
) {
5213 case nir_jump_break
:
5214 bld
.emit(BRW_OPCODE_BREAK
);
5216 case nir_jump_continue
:
5217 bld
.emit(BRW_OPCODE_CONTINUE
);
5219 case nir_jump_return
:
5221 unreachable("unknown jump");
5226 * This helper takes a source register and un/shuffles it into the destination
5229 * If source type size is smaller than destination type size the operation
5230 * needed is a component shuffle. The opposite case would be an unshuffle. If
5231 * source/destination type size is equal a shuffle is done that would be
5232 * equivalent to a simple MOV.
5234 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5235 * components .xyz 16-bit vector on SIMD8 would be.
5237 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5238 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5240 * This helper will return the following 2 32-bit components with the 16-bit
5243 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5244 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5246 * For unshuffle, the example would be the opposite, a 64-bit type source
5247 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5250 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5251 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5252 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5253 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5255 * The returned result would be the following 4 32-bit components unshuffled:
5257 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5258 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5259 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5260 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5262 * - Source and destination register must not be overlapped.
5263 * - components units are measured in terms of the smaller type between
5264 * source and destination because we are un/shuffling the smaller
5265 * components from/into the bigger ones.
5266 * - first_component parameter allows skipping source components.
5269 shuffle_src_to_dst(const fs_builder
&bld
,
5272 uint32_t first_component
,
5273 uint32_t components
)
5275 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5276 assert(!regions_overlap(dst
,
5277 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5278 offset(src
, bld
, first_component
),
5279 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5280 for (unsigned i
= 0; i
< components
; i
++) {
5281 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5282 offset(src
, bld
, i
+ first_component
));
5284 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5285 /* Source is shuffled into destination */
5286 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5287 assert(!regions_overlap(dst
,
5288 type_sz(dst
.type
) * bld
.dispatch_width() *
5289 DIV_ROUND_UP(components
, size_ratio
),
5290 offset(src
, bld
, first_component
),
5291 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5293 brw_reg_type shuffle_type
=
5294 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5295 BRW_REGISTER_TYPE_D
);
5296 for (unsigned i
= 0; i
< components
; i
++) {
5297 fs_reg shuffle_component_i
=
5298 subscript(offset(dst
, bld
, i
/ size_ratio
),
5299 shuffle_type
, i
% size_ratio
);
5300 bld
.MOV(shuffle_component_i
,
5301 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5304 /* Source is unshuffled into destination */
5305 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5306 assert(!regions_overlap(dst
,
5307 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5308 offset(src
, bld
, first_component
/ size_ratio
),
5309 type_sz(src
.type
) * bld
.dispatch_width() *
5310 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5313 brw_reg_type shuffle_type
=
5314 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5315 BRW_REGISTER_TYPE_D
);
5316 for (unsigned i
= 0; i
< components
; i
++) {
5317 fs_reg shuffle_component_i
=
5318 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5319 shuffle_type
, (first_component
+ i
) % size_ratio
);
5320 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5321 shuffle_component_i
);
5327 shuffle_from_32bit_read(const fs_builder
&bld
,
5330 uint32_t first_component
,
5331 uint32_t components
)
5333 assert(type_sz(src
.type
) == 4);
5335 /* This function takes components in units of the destination type while
5336 * shuffle_src_to_dst takes components in units of the smallest type
5338 if (type_sz(dst
.type
) > 4) {
5339 assert(type_sz(dst
.type
) == 8);
5340 first_component
*= 2;
5344 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5348 shuffle_for_32bit_write(const fs_builder
&bld
,
5350 uint32_t first_component
,
5351 uint32_t components
)
5353 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5354 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5355 /* This function takes components in units of the source type while
5356 * shuffle_src_to_dst takes components in units of the smallest type
5358 if (type_sz(src
.type
) > 4) {
5359 assert(type_sz(src
.type
) == 8);
5360 first_component
*= 2;
5364 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5370 setup_imm_df(const fs_builder
&bld
, double v
)
5372 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5373 assert(devinfo
->gen
>= 7);
5375 if (devinfo
->gen
>= 8)
5376 return brw_imm_df(v
);
5378 /* gen7.5 does not support DF immediates straighforward but the DIM
5379 * instruction allows to set the 64-bit immediate value.
5381 if (devinfo
->is_haswell
) {
5382 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5383 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5384 ubld
.DIM(dst
, brw_imm_df(v
));
5385 return component(dst
, 0);
5388 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5389 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5390 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5392 * Alternatively, we could also produce a normal VGRF (without stride 0)
5393 * by writing to all the channels in the VGRF, however, that would hit the
5394 * gen7 bug where we have to split writes that span more than 1 register
5395 * into instructions with a width of 4 (otherwise the write to the second
5396 * register written runs into an execmask hardware bug) which isn't very
5409 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5410 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5411 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5412 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5414 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);