2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "util/u_math.h"
28 #include "util/bitscan.h"
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
46 fs_visitor::nir_setup_outputs()
48 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
51 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
53 /* Calculate the size of output registers in a separate pass, before
54 * allocating them. With ARB_enhanced_layouts, multiple output variables
55 * may occupy the same slot, but have different type sizes.
57 nir_foreach_variable(var
, &nir
->outputs
) {
58 const int loc
= var
->data
.driver_location
;
59 const unsigned var_vec4s
=
60 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
61 : type_size_vec4(var
->type
);
62 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
65 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
66 if (vec4s
[loc
] == 0) {
71 unsigned reg_size
= vec4s
[loc
];
73 /* Check if there are any ranges that start within this range and extend
74 * past it. If so, include them in this allocation.
76 for (unsigned i
= 1; i
< reg_size
; i
++)
77 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
79 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
80 for (unsigned i
= 0; i
< reg_size
; i
++)
81 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
88 fs_visitor::nir_setup_uniforms()
90 /* Only the first compile gets to set up uniforms. */
91 if (push_constant_loc
) {
92 assert(pull_constant_loc
);
96 uniforms
= nir
->num_uniforms
/ 4;
98 if (stage
== MESA_SHADER_COMPUTE
) {
99 /* Add a uniform for the thread local id. It must be the last uniform
102 assert(uniforms
== prog_data
->nr_params
);
103 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
104 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
105 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
110 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
114 nir_foreach_instr(instr
, block
) {
115 if (instr
->type
!= nir_instr_type_intrinsic
)
118 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
119 switch (intrin
->intrinsic
) {
120 case nir_intrinsic_load_vertex_id
:
121 case nir_intrinsic_load_base_vertex
:
122 unreachable("should be lowered by nir_lower_system_values().");
124 case nir_intrinsic_load_vertex_id_zero_base
:
125 case nir_intrinsic_load_is_indexed_draw
:
126 case nir_intrinsic_load_first_vertex
:
127 case nir_intrinsic_load_instance_id
:
128 case nir_intrinsic_load_base_instance
:
129 case nir_intrinsic_load_draw_id
:
130 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
132 case nir_intrinsic_load_invocation_id
:
133 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
135 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
136 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
137 if (reg
->file
== BAD_FILE
) {
138 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
139 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
140 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
141 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
146 case nir_intrinsic_load_sample_pos
:
147 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
148 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
149 if (reg
->file
== BAD_FILE
)
150 *reg
= *v
->emit_samplepos_setup();
153 case nir_intrinsic_load_sample_id
:
154 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_sampleid_setup();
160 case nir_intrinsic_load_sample_mask_in
:
161 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
162 assert(v
->devinfo
->gen
>= 7);
163 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
164 if (reg
->file
== BAD_FILE
)
165 *reg
= *v
->emit_samplemaskin_setup();
168 case nir_intrinsic_load_work_group_id
:
169 assert(v
->stage
== MESA_SHADER_COMPUTE
);
170 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
171 if (reg
->file
== BAD_FILE
)
172 *reg
= *v
->emit_cs_work_group_id_setup();
175 case nir_intrinsic_load_helper_invocation
:
176 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
177 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
178 if (reg
->file
== BAD_FILE
) {
179 const fs_builder abld
=
180 v
->bld
.annotate("gl_HelperInvocation", NULL
);
182 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
183 * pixel mask is in g1.7 of the thread payload.
185 * We move the per-channel pixel enable bit to the low bit of each
186 * channel by shifting the byte containing the pixel mask by the
187 * vector immediate 0x76543210UV.
189 * The region of <1,8,0> reads only 1 byte (the pixel masks for
190 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
191 * masks for 2 and 3) in SIMD16.
193 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
195 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
196 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
197 hbld
.SHR(offset(shifted
, hbld
, i
),
198 stride(retype(brw_vec1_grf(1 + i
, 7),
199 BRW_REGISTER_TYPE_UB
),
201 brw_imm_v(0x76543210));
204 /* A set bit in the pixel mask means the channel is enabled, but
205 * that is the opposite of gl_HelperInvocation so we need to invert
208 * The negate source-modifier bit of logical instructions on Gen8+
209 * performs 1's complement negation, so we can use that instead of
212 fs_reg inverted
= negate(shifted
);
213 if (v
->devinfo
->gen
< 8) {
214 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
215 abld
.NOT(inverted
, shifted
);
218 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
219 * with 1 and negating.
221 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
222 abld
.AND(anded
, inverted
, brw_imm_uw(1));
224 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
225 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
239 fs_visitor::nir_emit_system_values()
241 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
242 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
243 nir_system_values
[i
] = fs_reg();
246 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
247 * never end up using it.
250 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
251 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
252 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
254 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
255 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
256 if (dispatch_width
> 8)
257 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
258 if (dispatch_width
> 16) {
259 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
260 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
264 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
265 nir_foreach_block(block
, impl
)
266 emit_system_values_block(block
, this);
270 * Returns a type based on a reference_type (word, float, half-float) and a
273 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
275 * @FIXME: 64-bit return types are always DF on integer types to maintain
276 * compability with uses of DF previously to the introduction of int64
280 brw_reg_type_from_bit_size(const unsigned bit_size
,
281 const brw_reg_type reference_type
)
283 switch(reference_type
) {
284 case BRW_REGISTER_TYPE_HF
:
285 case BRW_REGISTER_TYPE_F
:
286 case BRW_REGISTER_TYPE_DF
:
289 return BRW_REGISTER_TYPE_HF
;
291 return BRW_REGISTER_TYPE_F
;
293 return BRW_REGISTER_TYPE_DF
;
295 unreachable("Invalid bit size");
297 case BRW_REGISTER_TYPE_B
:
298 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_D
:
300 case BRW_REGISTER_TYPE_Q
:
303 return BRW_REGISTER_TYPE_B
;
305 return BRW_REGISTER_TYPE_W
;
307 return BRW_REGISTER_TYPE_D
;
309 return BRW_REGISTER_TYPE_Q
;
311 unreachable("Invalid bit size");
313 case BRW_REGISTER_TYPE_UB
:
314 case BRW_REGISTER_TYPE_UW
:
315 case BRW_REGISTER_TYPE_UD
:
316 case BRW_REGISTER_TYPE_UQ
:
319 return BRW_REGISTER_TYPE_UB
;
321 return BRW_REGISTER_TYPE_UW
;
323 return BRW_REGISTER_TYPE_UD
;
325 return BRW_REGISTER_TYPE_UQ
;
327 unreachable("Invalid bit size");
330 unreachable("Unknown type");
335 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
337 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
338 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
339 nir_locals
[i
] = fs_reg();
342 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
343 unsigned array_elems
=
344 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
345 unsigned size
= array_elems
* reg
->num_components
;
346 const brw_reg_type reg_type
=
347 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
348 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
351 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
354 nir_emit_cf_list(&impl
->body
);
358 fs_visitor::nir_emit_cf_list(exec_list
*list
)
360 exec_list_validate(list
);
361 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
362 switch (node
->type
) {
364 nir_emit_if(nir_cf_node_as_if(node
));
367 case nir_cf_node_loop
:
368 nir_emit_loop(nir_cf_node_as_loop(node
));
371 case nir_cf_node_block
:
372 nir_emit_block(nir_cf_node_as_block(node
));
376 unreachable("Invalid CFG node block");
382 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
387 /* If the condition has the form !other_condition, use other_condition as
388 * the source, but invert the predicate on the if instruction.
390 nir_alu_instr
*const cond
= nir_src_as_alu_instr(&if_stmt
->condition
);
391 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
392 assert(!cond
->src
[0].negate
);
393 assert(!cond
->src
[0].abs
);
396 cond_reg
= get_nir_src(cond
->src
[0].src
);
399 cond_reg
= get_nir_src(if_stmt
->condition
);
402 /* first, put the condition into f0 */
403 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
404 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
405 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
407 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
409 nir_emit_cf_list(&if_stmt
->then_list
);
411 /* note: if the else is empty, dead CF elimination will remove it */
412 bld
.emit(BRW_OPCODE_ELSE
);
414 nir_emit_cf_list(&if_stmt
->else_list
);
416 bld
.emit(BRW_OPCODE_ENDIF
);
418 if (devinfo
->gen
< 7)
419 limit_dispatch_width(16, "Non-uniform control flow unsupported "
424 fs_visitor::nir_emit_loop(nir_loop
*loop
)
426 bld
.emit(BRW_OPCODE_DO
);
428 nir_emit_cf_list(&loop
->body
);
430 bld
.emit(BRW_OPCODE_WHILE
);
432 if (devinfo
->gen
< 7)
433 limit_dispatch_width(16, "Non-uniform control flow unsupported "
438 fs_visitor::nir_emit_block(nir_block
*block
)
440 nir_foreach_instr(instr
, block
) {
441 nir_emit_instr(instr
);
446 fs_visitor::nir_emit_instr(nir_instr
*instr
)
448 const fs_builder abld
= bld
.annotate(NULL
, instr
);
450 switch (instr
->type
) {
451 case nir_instr_type_alu
:
452 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
455 case nir_instr_type_deref
:
456 /* Derefs can exist for images but they do nothing */
459 case nir_instr_type_intrinsic
:
461 case MESA_SHADER_VERTEX
:
462 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
464 case MESA_SHADER_TESS_CTRL
:
465 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
467 case MESA_SHADER_TESS_EVAL
:
468 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
470 case MESA_SHADER_GEOMETRY
:
471 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
473 case MESA_SHADER_FRAGMENT
:
474 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
476 case MESA_SHADER_COMPUTE
:
477 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
480 unreachable("unsupported shader stage");
484 case nir_instr_type_tex
:
485 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
488 case nir_instr_type_load_const
:
489 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
492 case nir_instr_type_ssa_undef
:
493 /* We create a new VGRF for undefs on every use (by handling
494 * them in get_nir_src()), rather than for each definition.
495 * This helps register coalescing eliminate MOVs from undef.
499 case nir_instr_type_jump
:
500 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
504 unreachable("unknown instruction type");
509 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
513 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
514 const fs_reg
&result
)
516 if (!instr
->src
[0].src
.is_ssa
||
517 !instr
->src
[0].src
.ssa
->parent_instr
)
520 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
523 nir_alu_instr
*src0
=
524 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
526 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
527 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
530 /* If either opcode has source modifiers, bail.
532 * TODO: We can potentially handle source modifiers if both of the opcodes
533 * we're combining are signed integers.
535 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
536 src0
->src
[0].abs
|| src0
->src
[0].negate
)
539 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
541 /* Element type to extract.*/
542 const brw_reg_type type
= brw_int_type(
543 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
544 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
546 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
547 op0
.type
= brw_type_for_nir_type(devinfo
,
548 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
549 nir_src_bit_size(src0
->src
[0].src
)));
550 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
552 set_saturate(instr
->dest
.saturate
,
553 bld
.MOV(result
, subscript(op0
, type
, element
)));
558 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
559 const fs_reg
&result
)
561 if (!instr
->src
[0].src
.is_ssa
||
562 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
565 nir_intrinsic_instr
*src0
=
566 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
568 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
571 if (!nir_src_is_const(instr
->src
[1].src
) ||
572 !nir_src_is_const(instr
->src
[2].src
))
575 const float value1
= nir_src_as_float(instr
->src
[1].src
);
576 const float value2
= nir_src_as_float(instr
->src
[2].src
);
577 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
580 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
581 assert(value1
== -value2
);
583 fs_reg tmp
= vgrf(glsl_type::int_type
);
585 if (devinfo
->gen
>= 6) {
586 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
587 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
589 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
591 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
592 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
594 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
596 * This negation looks like it's safe in practice, because bits 0:4 will
597 * surely be TRIANGLES
600 if (value1
== -1.0f
) {
604 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
605 g0
, brw_imm_uw(0x3f80));
607 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
608 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
610 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
612 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
613 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
615 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
617 * This negation looks like it's safe in practice, because bits 0:4 will
618 * surely be TRIANGLES
621 if (value1
== -1.0f
) {
625 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
627 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
633 emit_find_msb_using_lzd(const fs_builder
&bld
,
634 const fs_reg
&result
,
642 /* LZD of an absolute value source almost always does the right
643 * thing. There are two problem values:
645 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
646 * 0. However, findMSB(int(0x80000000)) == 30.
648 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
649 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
651 * For a value of zero or negative one, -1 will be returned.
653 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
654 * findMSB(-(1<<x)) should return x-1.
656 * For all negative number cases, including 0x80000000 and
657 * 0xffffffff, the correct value is obtained from LZD if instead of
658 * negating the (already negative) value the logical-not is used. A
659 * conditonal logical-not can be achieved in two instructions.
661 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
663 bld
.ASR(temp
, src
, brw_imm_d(31));
664 bld
.XOR(temp
, temp
, src
);
667 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
668 retype(temp
, BRW_REGISTER_TYPE_UD
));
670 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
671 * from the LSB side. Subtract the result from 31 to convert the MSB
672 * count into an LSB count. If no bits are set, LZD will return 32.
673 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
675 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
676 inst
->src
[0].negate
= true;
680 brw_rnd_mode_from_nir_op (const nir_op op
) {
682 case nir_op_f2f16_rtz
:
683 return BRW_RND_MODE_RTZ
;
684 case nir_op_f2f16_rtne
:
685 return BRW_RND_MODE_RTNE
;
687 unreachable("Operation doesn't support rounding mode");
692 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
693 nir_alu_instr
*instr
,
698 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
700 result
.type
= brw_type_for_nir_type(devinfo
,
701 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
702 nir_dest_bit_size(instr
->dest
.dest
)));
704 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
705 op
[i
] = get_nir_src(instr
->src
[i
].src
);
706 op
[i
].type
= brw_type_for_nir_type(devinfo
,
707 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
708 nir_src_bit_size(instr
->src
[i
].src
)));
709 op
[i
].abs
= instr
->src
[i
].abs
;
710 op
[i
].negate
= instr
->src
[i
].negate
;
713 /* Move and vecN instrutions may still be vectored. Return the raw,
714 * vectored source and destination so that fs_visitor::nir_emit_alu can
715 * handle it. Other callers should not have to handle these kinds of
729 /* At this point, we have dealt with any instruction that operates on
730 * more than a single channel. Therefore, we can just adjust the source
731 * and destination registers for that channel and emit the instruction.
733 unsigned channel
= 0;
734 if (nir_op_infos
[instr
->op
].output_size
== 0) {
735 /* Since NIR is doing the scalarizing for us, we should only ever see
736 * vectorized operations with a single channel.
738 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
739 channel
= ffs(instr
->dest
.write_mask
) - 1;
741 result
= offset(result
, bld
, channel
);
744 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
745 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
746 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
753 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
756 for (unsigned i
= 0; i
< 2; i
++) {
757 nir_alu_instr
*const inot_instr
=
758 nir_src_as_alu_instr(&instr
->src
[i
].src
);
760 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
761 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
762 /* The source of the inot is now the source of instr. */
763 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
765 assert(!op
[i
].negate
);
768 op
[i
] = resolve_source_modifiers(op
[i
]);
774 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
776 nir_alu_instr
*instr
)
778 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
781 nir_alu_instr
*const inot_instr
= nir_src_as_alu_instr(&instr
->src
[0].src
);
783 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
786 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
787 * of valid size-changing combinations is a bit more complex.
789 * The source restriction is just because I was lazy about generating the
792 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
793 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
796 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
797 * this is float(1 + a).
801 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
803 /* Ignore the saturate modifier, if there is one. The result of the
804 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
806 bld
.ADD(result
, op
, brw_imm_d(1));
812 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
814 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
818 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, true);
826 fs_reg temp
= result
;
827 bool need_extra_copy
= false;
828 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
829 if (!instr
->src
[i
].src
.is_ssa
&&
830 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
831 need_extra_copy
= true;
832 temp
= bld
.vgrf(result
.type
, 4);
837 for (unsigned i
= 0; i
< 4; i
++) {
838 if (!(instr
->dest
.write_mask
& (1 << i
)))
841 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
842 inst
= bld
.MOV(offset(temp
, bld
, i
),
843 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
845 inst
= bld
.MOV(offset(temp
, bld
, i
),
846 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
848 inst
->saturate
= instr
->dest
.saturate
;
851 /* In this case the source and destination registers were the same,
852 * so we need to insert an extra set of moves in order to deal with
855 if (need_extra_copy
) {
856 for (unsigned i
= 0; i
< 4; i
++) {
857 if (!(instr
->dest
.write_mask
& (1 << i
)))
860 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
868 if (optimize_extract_to_float(instr
, result
))
870 inst
= bld
.MOV(result
, op
[0]);
871 inst
->saturate
= instr
->dest
.saturate
;
874 case nir_op_f2f16_rtne
:
875 case nir_op_f2f16_rtz
:
876 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
877 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
880 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
881 * on the HW gen, it is a special hw opcode or just a MOV, and
882 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
884 * But if we want to use that opcode, we need to provide support on
885 * different optimizations and lowerings. As right now HF support is
886 * only for gen8+, it will be better to use directly the MOV, and use
887 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
891 inst
= bld
.MOV(result
, op
[0]);
892 inst
->saturate
= instr
->dest
.saturate
;
902 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
904 op
[0].type
= BRW_REGISTER_TYPE_D
;
905 op
[0].negate
= !op
[0].negate
;
927 inst
= bld
.MOV(result
, op
[0]);
928 inst
->saturate
= instr
->dest
.saturate
;
932 assert(!instr
->dest
.saturate
);
934 /* Straightforward since the source can be assumed to be either
935 * strictly >= 0 or strictly <= 0 depending on the setting of the
938 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
940 inst
= (op
[0].negate
)
941 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
942 : bld
.MOV(result
, brw_imm_f(1.0f
));
944 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
945 } else if (type_sz(op
[0].type
) < 8) {
946 /* AND(val, 0x80000000) gives the sign bit.
948 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
951 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
953 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
954 op
[0].type
= BRW_REGISTER_TYPE_UD
;
955 result
.type
= BRW_REGISTER_TYPE_UD
;
956 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
958 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
959 inst
->predicate
= BRW_PREDICATE_NORMAL
;
961 /* For doubles we do the same but we need to consider:
963 * - 2-src instructions can't operate with 64-bit immediates
964 * - The sign is encoded in the high 32-bit of each DF
965 * - We need to produce a DF result.
968 fs_reg zero
= vgrf(glsl_type::double_type
);
969 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
970 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
972 bld
.MOV(result
, zero
);
974 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
975 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
976 brw_imm_ud(0x80000000u
));
978 set_predicate(BRW_PREDICATE_NORMAL
,
979 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
985 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
986 inst
->saturate
= instr
->dest
.saturate
;
990 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
991 inst
->saturate
= instr
->dest
.saturate
;
995 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
996 inst
->saturate
= instr
->dest
.saturate
;
1000 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1001 inst
->saturate
= instr
->dest
.saturate
;
1005 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1006 inst
->saturate
= instr
->dest
.saturate
;
1010 if (fs_key
->high_quality_derivatives
) {
1011 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1013 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1015 inst
->saturate
= instr
->dest
.saturate
;
1017 case nir_op_fddx_fine
:
1018 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1019 inst
->saturate
= instr
->dest
.saturate
;
1021 case nir_op_fddx_coarse
:
1022 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1023 inst
->saturate
= instr
->dest
.saturate
;
1026 if (fs_key
->high_quality_derivatives
) {
1027 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1029 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1031 inst
->saturate
= instr
->dest
.saturate
;
1033 case nir_op_fddy_fine
:
1034 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1035 inst
->saturate
= instr
->dest
.saturate
;
1037 case nir_op_fddy_coarse
:
1038 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1039 inst
->saturate
= instr
->dest
.saturate
;
1044 inst
= bld
.ADD(result
, op
[0], op
[1]);
1045 inst
->saturate
= instr
->dest
.saturate
;
1048 case nir_op_uadd_sat
:
1049 inst
= bld
.ADD(result
, op
[0], op
[1]);
1050 inst
->saturate
= true;
1054 inst
= bld
.MUL(result
, op
[0], op
[1]);
1055 inst
->saturate
= instr
->dest
.saturate
;
1058 case nir_op_imul_2x32_64
:
1059 case nir_op_umul_2x32_64
:
1060 bld
.MUL(result
, op
[0], op
[1]);
1064 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1065 bld
.MUL(result
, op
[0], op
[1]);
1068 case nir_op_imul_high
:
1069 case nir_op_umul_high
:
1070 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1071 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1076 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1077 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1080 case nir_op_uadd_carry
:
1081 unreachable("Should have been lowered by carry_to_arith().");
1083 case nir_op_usub_borrow
:
1084 unreachable("Should have been lowered by borrow_to_arith().");
1088 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1089 * appears that our hardware just does the right thing for signed
1092 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1093 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1097 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1098 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1100 /* Math instructions don't support conditional mod */
1101 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1102 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1104 /* Now, we need to determine if signs of the sources are different.
1105 * When we XOR the sources, the top bit is 0 if they are the same and 1
1106 * if they are different. We can then use a conditional modifier to
1107 * turn that into a predicate. This leads us to an XOR.l instruction.
1109 * Technically, according to the PRM, you're not allowed to use .l on a
1110 * XOR instruction. However, emperical experiments and Curro's reading
1111 * of the simulator source both indicate that it's safe.
1113 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1114 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1115 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1116 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1118 /* If the result of the initial remainder operation is non-zero and the
1119 * two sources have different signs, add in a copy of op[1] to get the
1120 * final integer modulus value.
1122 inst
= bld
.ADD(result
, result
, op
[1]);
1123 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1130 case nir_op_fne32
: {
1131 fs_reg dest
= result
;
1133 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1135 dest
= bld
.vgrf(op
[0].type
, 1);
1137 brw_conditional_mod cond
;
1138 switch (instr
->op
) {
1140 cond
= BRW_CONDITIONAL_L
;
1143 cond
= BRW_CONDITIONAL_GE
;
1146 cond
= BRW_CONDITIONAL_Z
;
1149 cond
= BRW_CONDITIONAL_NZ
;
1152 unreachable("bad opcode");
1155 bld
.CMP(dest
, op
[0], op
[1], cond
);
1157 if (bit_size
> 32) {
1158 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1159 } else if(bit_size
< 32) {
1160 /* When we convert the result to 32-bit we need to be careful and do
1161 * it as a signed conversion to get sign extension (for 32-bit true)
1163 const brw_reg_type src_type
=
1164 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1166 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1176 case nir_op_ine32
: {
1177 fs_reg dest
= result
;
1179 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1181 dest
= bld
.vgrf(op
[0].type
, 1);
1183 brw_conditional_mod cond
;
1184 switch (instr
->op
) {
1187 cond
= BRW_CONDITIONAL_L
;
1191 cond
= BRW_CONDITIONAL_GE
;
1194 cond
= BRW_CONDITIONAL_Z
;
1197 cond
= BRW_CONDITIONAL_NZ
;
1200 unreachable("bad opcode");
1202 bld
.CMP(dest
, op
[0], op
[1], cond
);
1204 if (bit_size
> 32) {
1205 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1206 } else if (bit_size
< 32) {
1207 /* When we convert the result to 32-bit we need to be careful and do
1208 * it as a signed conversion to get sign extension (for 32-bit true)
1210 const brw_reg_type src_type
=
1211 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1213 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1219 if (devinfo
->gen
>= 8) {
1220 nir_alu_instr
*const inot_src_instr
=
1221 nir_src_as_alu_instr(&instr
->src
[0].src
);
1223 if (inot_src_instr
!= NULL
&&
1224 (inot_src_instr
->op
== nir_op_ior
||
1225 inot_src_instr
->op
== nir_op_ixor
||
1226 inot_src_instr
->op
== nir_op_iand
) &&
1227 !inot_src_instr
->src
[0].abs
&&
1228 !inot_src_instr
->src
[0].negate
&&
1229 !inot_src_instr
->src
[1].abs
&&
1230 !inot_src_instr
->src
[1].negate
) {
1231 /* The sources of the source logical instruction are now the
1232 * sources of the instruction that will be generated.
1234 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1235 resolve_inot_sources(bld
, inot_src_instr
, op
);
1237 /* Smash all of the sources and destination to be signed. This
1238 * doesn't matter for the operation of the instruction, but cmod
1239 * propagation fails on unsigned sources with negation (due to
1240 * fs_inst::can_do_cmod returning false).
1243 brw_type_for_nir_type(devinfo
,
1244 (nir_alu_type
)(nir_type_int
|
1245 nir_dest_bit_size(instr
->dest
.dest
)));
1247 brw_type_for_nir_type(devinfo
,
1248 (nir_alu_type
)(nir_type_int
|
1249 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1251 brw_type_for_nir_type(devinfo
,
1252 (nir_alu_type
)(nir_type_int
|
1253 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1255 /* For XOR, only invert one of the sources. Arbitrarily choose
1258 op
[0].negate
= !op
[0].negate
;
1259 if (inot_src_instr
->op
!= nir_op_ixor
)
1260 op
[1].negate
= !op
[1].negate
;
1262 switch (inot_src_instr
->op
) {
1264 bld
.AND(result
, op
[0], op
[1]);
1268 bld
.OR(result
, op
[0], op
[1]);
1272 bld
.XOR(result
, op
[0], op
[1]);
1276 unreachable("impossible opcode");
1279 op
[0] = resolve_source_modifiers(op
[0]);
1281 bld
.NOT(result
, op
[0]);
1284 if (devinfo
->gen
>= 8) {
1285 resolve_inot_sources(bld
, instr
, op
);
1287 bld
.XOR(result
, op
[0], op
[1]);
1290 if (devinfo
->gen
>= 8) {
1291 resolve_inot_sources(bld
, instr
, op
);
1293 bld
.OR(result
, op
[0], op
[1]);
1296 if (devinfo
->gen
>= 8) {
1297 resolve_inot_sources(bld
, instr
, op
);
1299 bld
.AND(result
, op
[0], op
[1]);
1305 case nir_op_b32all_fequal2
:
1306 case nir_op_b32all_iequal2
:
1307 case nir_op_b32all_fequal3
:
1308 case nir_op_b32all_iequal3
:
1309 case nir_op_b32all_fequal4
:
1310 case nir_op_b32all_iequal4
:
1311 case nir_op_b32any_fnequal2
:
1312 case nir_op_b32any_inequal2
:
1313 case nir_op_b32any_fnequal3
:
1314 case nir_op_b32any_inequal3
:
1315 case nir_op_b32any_fnequal4
:
1316 case nir_op_b32any_inequal4
:
1317 unreachable("Lowered by nir_lower_alu_reductions");
1319 case nir_op_fnoise1_1
:
1320 case nir_op_fnoise1_2
:
1321 case nir_op_fnoise1_3
:
1322 case nir_op_fnoise1_4
:
1323 case nir_op_fnoise2_1
:
1324 case nir_op_fnoise2_2
:
1325 case nir_op_fnoise2_3
:
1326 case nir_op_fnoise2_4
:
1327 case nir_op_fnoise3_1
:
1328 case nir_op_fnoise3_2
:
1329 case nir_op_fnoise3_3
:
1330 case nir_op_fnoise3_4
:
1331 case nir_op_fnoise4_1
:
1332 case nir_op_fnoise4_2
:
1333 case nir_op_fnoise4_3
:
1334 case nir_op_fnoise4_4
:
1335 unreachable("not reached: should be handled by lower_noise");
1338 unreachable("not reached: should be handled by ldexp_to_arith()");
1341 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1342 inst
->saturate
= instr
->dest
.saturate
;
1346 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1347 inst
->saturate
= instr
->dest
.saturate
;
1351 case nir_op_f2b32
: {
1352 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1353 if (bit_size
== 64) {
1354 /* two-argument instructions can't take 64-bit immediates */
1358 if (instr
->op
== nir_op_f2b32
) {
1359 zero
= vgrf(glsl_type::double_type
);
1360 tmp
= vgrf(glsl_type::double_type
);
1361 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1363 zero
= vgrf(glsl_type::int64_t_type
);
1364 tmp
= vgrf(glsl_type::int64_t_type
);
1365 bld
.MOV(zero
, brw_imm_q(0));
1368 /* A SIMD16 execution needs to be split in two instructions, so use
1369 * a vgrf instead of the flag register as dst so instruction splitting
1372 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1373 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1376 if (bit_size
== 32) {
1377 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1379 assert(bit_size
== 16);
1380 zero
= instr
->op
== nir_op_f2b32
?
1381 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1383 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1389 inst
= bld
.RNDZ(result
, op
[0]);
1390 inst
->saturate
= instr
->dest
.saturate
;
1393 case nir_op_fceil
: {
1394 op
[0].negate
= !op
[0].negate
;
1395 fs_reg temp
= vgrf(glsl_type::float_type
);
1396 bld
.RNDD(temp
, op
[0]);
1398 inst
= bld
.MOV(result
, temp
);
1399 inst
->saturate
= instr
->dest
.saturate
;
1403 inst
= bld
.RNDD(result
, op
[0]);
1404 inst
->saturate
= instr
->dest
.saturate
;
1407 inst
= bld
.FRC(result
, op
[0]);
1408 inst
->saturate
= instr
->dest
.saturate
;
1410 case nir_op_fround_even
:
1411 inst
= bld
.RNDE(result
, op
[0]);
1412 inst
->saturate
= instr
->dest
.saturate
;
1415 case nir_op_fquantize2f16
: {
1416 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1417 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1418 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1420 /* The destination stride must be at least as big as the source stride. */
1421 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1424 /* Check for denormal */
1425 fs_reg abs_src0
= op
[0];
1426 abs_src0
.abs
= true;
1427 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1429 /* Get the appropriately signed zero */
1430 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1431 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1432 brw_imm_ud(0x80000000));
1433 /* Do the actual F32 -> F16 -> F32 conversion */
1434 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1435 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1436 /* Select that or zero based on normal status */
1437 inst
= bld
.SEL(result
, zero
, tmp32
);
1438 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1439 inst
->saturate
= instr
->dest
.saturate
;
1446 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1447 inst
->saturate
= instr
->dest
.saturate
;
1453 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1454 inst
->saturate
= instr
->dest
.saturate
;
1457 case nir_op_pack_snorm_2x16
:
1458 case nir_op_pack_snorm_4x8
:
1459 case nir_op_pack_unorm_2x16
:
1460 case nir_op_pack_unorm_4x8
:
1461 case nir_op_unpack_snorm_2x16
:
1462 case nir_op_unpack_snorm_4x8
:
1463 case nir_op_unpack_unorm_2x16
:
1464 case nir_op_unpack_unorm_4x8
:
1465 case nir_op_unpack_half_2x16
:
1466 case nir_op_pack_half_2x16
:
1467 unreachable("not reached: should be handled by lower_packing_builtins");
1469 case nir_op_unpack_half_2x16_split_x
:
1470 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1471 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1472 inst
->saturate
= instr
->dest
.saturate
;
1474 case nir_op_unpack_half_2x16_split_y
:
1475 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1476 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1477 inst
->saturate
= instr
->dest
.saturate
;
1480 case nir_op_pack_64_2x32_split
:
1481 case nir_op_pack_32_2x16_split
:
1482 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1485 case nir_op_unpack_64_2x32_split_x
:
1486 case nir_op_unpack_64_2x32_split_y
: {
1487 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1488 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1490 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1494 case nir_op_unpack_32_2x16_split_x
:
1495 case nir_op_unpack_32_2x16_split_y
: {
1496 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1497 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1499 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1504 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1505 inst
->saturate
= instr
->dest
.saturate
;
1508 case nir_op_bitfield_reverse
:
1509 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1510 bld
.BFREV(result
, op
[0]);
1513 case nir_op_bit_count
:
1514 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1515 bld
.CBIT(result
, op
[0]);
1518 case nir_op_ufind_msb
: {
1519 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1520 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1524 case nir_op_ifind_msb
: {
1525 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1527 if (devinfo
->gen
< 7) {
1528 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1530 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1532 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1533 * count from the LSB side. If FBH didn't return an error
1534 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1535 * count into an LSB count.
1537 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1539 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1540 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1541 inst
->src
[0].negate
= true;
1546 case nir_op_find_lsb
:
1547 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1549 if (devinfo
->gen
< 7) {
1550 fs_reg temp
= vgrf(glsl_type::int_type
);
1552 /* (x & -x) generates a value that consists of only the LSB of x.
1553 * For all powers of 2, findMSB(y) == findLSB(y).
1555 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1556 fs_reg negated_src
= src
;
1558 /* One must be negated, and the other must be non-negated. It
1559 * doesn't matter which is which.
1561 negated_src
.negate
= true;
1564 bld
.AND(temp
, src
, negated_src
);
1565 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1567 bld
.FBL(result
, op
[0]);
1571 case nir_op_ubitfield_extract
:
1572 case nir_op_ibitfield_extract
:
1573 unreachable("should have been lowered");
1576 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1577 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1580 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1581 bld
.BFI1(result
, op
[0], op
[1]);
1584 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1585 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1588 case nir_op_bitfield_insert
:
1589 unreachable("not reached: should have been lowered");
1592 bld
.SHL(result
, op
[0], op
[1]);
1595 bld
.ASR(result
, op
[0], op
[1]);
1598 bld
.SHR(result
, op
[0], op
[1]);
1601 case nir_op_pack_half_2x16_split
:
1602 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1606 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1607 inst
->saturate
= instr
->dest
.saturate
;
1611 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1612 inst
->saturate
= instr
->dest
.saturate
;
1615 case nir_op_b32csel
:
1616 if (optimize_frontfacing_ternary(instr
, result
))
1619 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1620 inst
= bld
.SEL(result
, op
[1], op
[2]);
1621 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1624 case nir_op_extract_u8
:
1625 case nir_op_extract_i8
: {
1626 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1631 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1632 * Use two instructions and a word or DWord intermediate integer type.
1634 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1635 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1637 if (instr
->op
== nir_op_extract_i8
) {
1638 /* If we need to sign extend, extract to a word first */
1639 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1640 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1641 bld
.MOV(result
, w_temp
);
1643 /* Otherwise use an AND with 0xff and a word type */
1644 bld
.AND(result
, subscript(op
[0], type
, byte
/ 2), brw_imm_uw(0xff));
1647 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1648 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1653 case nir_op_extract_u16
:
1654 case nir_op_extract_i16
: {
1655 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1656 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1657 bld
.MOV(result
, subscript(op
[0], type
, word
));
1662 unreachable("unhandled instruction");
1665 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1666 * to sign extend the low bit to 0/~0
1668 if (devinfo
->gen
<= 5 &&
1669 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1670 fs_reg masked
= vgrf(glsl_type::int_type
);
1671 bld
.AND(masked
, result
, brw_imm_d(1));
1672 masked
.negate
= true;
1673 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1678 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1679 nir_load_const_instr
*instr
)
1681 const brw_reg_type reg_type
=
1682 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1683 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1685 switch (instr
->def
.bit_size
) {
1687 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1688 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1692 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1693 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1697 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1698 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1702 assert(devinfo
->gen
>= 7);
1703 if (devinfo
->gen
== 7) {
1704 /* We don't get 64-bit integer types until gen8 */
1705 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1706 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1707 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1710 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1711 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1716 unreachable("Invalid bit size");
1719 nir_ssa_values
[instr
->def
.index
] = reg
;
1723 fs_visitor::get_nir_src(const nir_src
&src
)
1727 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1728 const brw_reg_type reg_type
=
1729 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1730 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1732 reg
= nir_ssa_values
[src
.ssa
->index
];
1735 /* We don't handle indirects on locals */
1736 assert(src
.reg
.indirect
== NULL
);
1737 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1738 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1741 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1742 /* The only 64-bit type available on gen7 is DF, so use that. */
1743 reg
.type
= BRW_REGISTER_TYPE_DF
;
1745 /* To avoid floating-point denorm flushing problems, set the type by
1746 * default to an integer type - instructions that need floating point
1747 * semantics will set this to F if they need to
1749 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1750 BRW_REGISTER_TYPE_D
);
1757 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1759 * This function should not be called on any value which may be 64 bits.
1760 * We could theoretically support 64-bit on gen8+ but we choose not to
1761 * because it wouldn't work in general (no gen7 support) and there are
1762 * enough restrictions in 64-bit immediates that you can't take the return
1763 * value and treat it the same as the result of get_nir_src().
1766 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1768 assert(nir_src_bit_size(src
) == 32);
1769 return nir_src_is_const(src
) ?
1770 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1774 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1777 const brw_reg_type reg_type
=
1778 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1779 dest
.ssa
.bit_size
== 8 ?
1780 BRW_REGISTER_TYPE_D
:
1781 BRW_REGISTER_TYPE_F
);
1782 nir_ssa_values
[dest
.ssa
.index
] =
1783 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1784 return nir_ssa_values
[dest
.ssa
.index
];
1786 /* We don't handle indirects on locals */
1787 assert(dest
.reg
.indirect
== NULL
);
1788 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1789 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1794 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1797 for (unsigned i
= 0; i
< 4; i
++) {
1798 if (!((wr_mask
>> i
) & 1))
1801 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1802 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1803 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1804 if (new_inst
->src
[j
].file
== VGRF
)
1805 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1812 emit_pixel_interpolater_send(const fs_builder
&bld
,
1817 glsl_interp_mode interpolation
)
1819 struct brw_wm_prog_data
*wm_prog_data
=
1820 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1822 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1823 /* 2 floats per slot returned */
1824 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1825 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1827 wm_prog_data
->pulls_bary
= true;
1833 * Computes 1 << x, given a D/UD register containing some value x.
1836 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1838 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1840 fs_reg result
= bld
.vgrf(x
.type
, 1);
1841 fs_reg one
= bld
.vgrf(x
.type
, 1);
1843 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1844 bld
.SHL(result
, one
, x
);
1849 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1851 assert(stage
== MESA_SHADER_GEOMETRY
);
1853 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1855 if (gs_compile
->control_data_header_size_bits
== 0)
1858 /* We can only do EndPrimitive() functionality when the control data
1859 * consists of cut bits. Fortunately, the only time it isn't is when the
1860 * output type is points, in which case EndPrimitive() is a no-op.
1862 if (gs_prog_data
->control_data_format
!=
1863 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1867 /* Cut bits use one bit per vertex. */
1868 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1870 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1871 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1873 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1874 * vertex n, 0 otherwise. So all we need to do here is mark bit
1875 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1876 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1877 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1879 * Note that if EndPrimitive() is called before emitting any vertices, this
1880 * will cause us to set bit 31 of the control_data_bits register to 1.
1881 * That's fine because:
1883 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1884 * output, so the hardware will ignore cut bit 31.
1886 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1887 * last vertex, so setting cut bit 31 has no effect (since the primitive
1888 * is automatically ended when the GS terminates).
1890 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1891 * control_data_bits register to 0 when the first vertex is emitted.
1894 const fs_builder abld
= bld
.annotate("end primitive");
1896 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1897 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1898 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1899 fs_reg mask
= intexp2(abld
, prev_count
);
1900 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1901 * attention to the lower 5 bits of its second source argument, so on this
1902 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1903 * ((vertex_count - 1) % 32).
1905 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1909 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1911 assert(stage
== MESA_SHADER_GEOMETRY
);
1912 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1914 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1916 const fs_builder abld
= bld
.annotate("emit control data bits");
1917 const fs_builder fwa_bld
= bld
.exec_all();
1919 /* We use a single UD register to accumulate control data bits (32 bits
1920 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1923 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1924 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1925 * use the Channel Mask phase to enable/disable which DWord within that
1926 * group to write. (Remember, different SIMD8 channels may have emitted
1927 * different numbers of vertices, so we may need per-slot offsets.)
1929 * Channel masking presents an annoying problem: we may have to replicate
1930 * the data up to 4 times:
1932 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1934 * To avoid penalizing shaders that emit a small number of vertices, we
1935 * can avoid these sometimes: if the size of the control data header is
1936 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1937 * land in the same 128-bit group, so we can skip per-slot offsets.
1939 * Similarly, if the control data header is <= 32 bits, there is only one
1940 * DWord, so we can skip channel masks.
1942 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1944 fs_reg channel_mask
, per_slot_offset
;
1946 if (gs_compile
->control_data_header_size_bits
> 32) {
1947 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1948 channel_mask
= vgrf(glsl_type::uint_type
);
1951 if (gs_compile
->control_data_header_size_bits
> 128) {
1952 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1953 per_slot_offset
= vgrf(glsl_type::uint_type
);
1956 /* Figure out which DWord we're trying to write to using the formula:
1958 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1960 * Since bits_per_vertex is a power of two, and is known at compile
1961 * time, this can be optimized to:
1963 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1965 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1966 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1967 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1968 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1969 unsigned log2_bits_per_vertex
=
1970 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1971 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1973 if (per_slot_offset
.file
!= BAD_FILE
) {
1974 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1975 * the appropriate OWord within the control data header.
1977 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1980 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1981 * write to the appropriate DWORD within the OWORD.
1983 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1984 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1985 channel_mask
= intexp2(fwa_bld
, channel
);
1986 /* Then the channel masks need to be in bits 23:16. */
1987 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1990 /* Store the control data bits in the message payload and send it. */
1992 if (channel_mask
.file
!= BAD_FILE
)
1993 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1994 if (per_slot_offset
.file
!= BAD_FILE
)
1997 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1998 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2000 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2001 if (per_slot_offset
.file
!= BAD_FILE
)
2002 sources
[i
++] = per_slot_offset
;
2003 if (channel_mask
.file
!= BAD_FILE
)
2004 sources
[i
++] = channel_mask
;
2006 sources
[i
++] = this->control_data_bits
;
2009 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2010 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2012 /* We need to increment Global Offset by 256-bits to make room for
2013 * Broadwell's extra "Vertex Count" payload at the beginning of the
2014 * URB entry. Since this is an OWord message, Global Offset is counted
2015 * in 128-bit units, so we must set it to 2.
2017 if (gs_prog_data
->static_vertex_count
== -1)
2022 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2025 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2027 /* Note: we are calling this *before* increasing vertex_count, so
2028 * this->vertex_count == vertex_count - 1 in the formula above.
2031 /* Stream mode uses 2 bits per vertex */
2032 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2034 /* Must be a valid stream */
2035 assert(stream_id
< MAX_VERTEX_STREAMS
);
2037 /* Control data bits are initialized to 0 so we don't have to set any
2038 * bits when sending vertices to stream 0.
2043 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2045 /* reg::sid = stream_id */
2046 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2047 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2049 /* reg:shift_count = 2 * (vertex_count - 1) */
2050 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2051 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2053 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2054 * attention to the lower 5 bits of its second source argument, so on this
2055 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2056 * stream_id << ((2 * (vertex_count - 1)) % 32).
2058 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2059 abld
.SHL(mask
, sid
, shift_count
);
2060 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2064 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2067 assert(stage
== MESA_SHADER_GEOMETRY
);
2069 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2071 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2072 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2074 /* Haswell and later hardware ignores the "Render Stream Select" bits
2075 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2076 * and instead sends all primitives down the pipeline for rasterization.
2077 * If the SOL stage is enabled, "Render Stream Select" is honored and
2078 * primitives bound to non-zero streams are discarded after stream output.
2080 * Since the only purpose of primives sent to non-zero streams is to
2081 * be recorded by transform feedback, we can simply discard all geometry
2082 * bound to these streams when transform feedback is disabled.
2084 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2087 /* If we're outputting 32 control data bits or less, then we can wait
2088 * until the shader is over to output them all. Otherwise we need to
2089 * output them as we go. Now is the time to do it, since we're about to
2090 * output the vertex_count'th vertex, so it's guaranteed that the
2091 * control data bits associated with the (vertex_count - 1)th vertex are
2094 if (gs_compile
->control_data_header_size_bits
> 32) {
2095 const fs_builder abld
=
2096 bld
.annotate("emit vertex: emit control data bits");
2098 /* Only emit control data bits if we've finished accumulating a batch
2099 * of 32 bits. This is the case when:
2101 * (vertex_count * bits_per_vertex) % 32 == 0
2103 * (in other words, when the last 5 bits of vertex_count *
2104 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2105 * integer n (which is always the case, since bits_per_vertex is
2106 * always 1 or 2), this is equivalent to requiring that the last 5-n
2107 * bits of vertex_count are 0:
2109 * vertex_count & (2^(5-n) - 1) == 0
2111 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2114 * vertex_count & (32 / bits_per_vertex - 1) == 0
2116 * TODO: If vertex_count is an immediate, we could do some of this math
2117 * at compile time...
2120 abld
.AND(bld
.null_reg_d(), vertex_count
,
2121 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2122 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2124 abld
.IF(BRW_PREDICATE_NORMAL
);
2125 /* If vertex_count is 0, then no control data bits have been
2126 * accumulated yet, so we can skip emitting them.
2128 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2129 BRW_CONDITIONAL_NEQ
);
2130 abld
.IF(BRW_PREDICATE_NORMAL
);
2131 emit_gs_control_data_bits(vertex_count
);
2132 abld
.emit(BRW_OPCODE_ENDIF
);
2134 /* Reset control_data_bits to 0 so we can start accumulating a new
2137 * Note: in the case where vertex_count == 0, this neutralizes the
2138 * effect of any call to EndPrimitive() that the shader may have
2139 * made before outputting its first vertex.
2141 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2142 inst
->force_writemask_all
= true;
2143 abld
.emit(BRW_OPCODE_ENDIF
);
2146 emit_urb_writes(vertex_count
);
2148 /* In stream mode we have to set control data bits for all vertices
2149 * unless we have disabled control data bits completely (which we do
2150 * do for GL_POINTS outputs that don't use streams).
2152 if (gs_compile
->control_data_header_size_bits
> 0 &&
2153 gs_prog_data
->control_data_format
==
2154 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2155 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2160 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2161 const nir_src
&vertex_src
,
2162 unsigned base_offset
,
2163 const nir_src
&offset_src
,
2164 unsigned num_components
,
2165 unsigned first_component
)
2167 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2168 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2170 /* TODO: figure out push input layout for invocations == 1 */
2171 /* TODO: make this work with 64-bit inputs */
2172 if (gs_prog_data
->invocations
== 1 &&
2173 type_sz(dst
.type
) <= 4 &&
2174 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2175 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2176 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2177 nir_src_as_uint(vertex_src
) * push_reg_count
;
2178 for (unsigned i
= 0; i
< num_components
; i
++) {
2179 bld
.MOV(offset(dst
, bld
, i
),
2180 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2185 /* Resort to the pull model. Ensure the VUE handles are provided. */
2186 assert(gs_prog_data
->base
.include_vue_handles
);
2188 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2189 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2191 if (gs_prog_data
->invocations
== 1) {
2192 if (nir_src_is_const(vertex_src
)) {
2193 /* The vertex index is constant; just select the proper URB handle. */
2195 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2196 BRW_REGISTER_TYPE_UD
);
2198 /* The vertex index is non-constant. We need to use indirect
2199 * addressing to fetch the proper URB handle.
2201 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2202 * indicating that channel <n> should read the handle from
2203 * DWord <n>. We convert that to bytes by multiplying by 4.
2205 * Next, we convert the vertex index to bytes by multiplying
2206 * by 32 (shifting by 5), and add the two together. This is
2207 * the final indirect byte offset.
2209 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2210 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2211 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2212 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2214 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2215 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2216 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2217 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2218 /* Convert vertex_index to bytes (multiply by 32) */
2219 bld
.SHL(vertex_offset_bytes
,
2220 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2222 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2224 /* Use first_icp_handle as the base offset. There is one register
2225 * of URB handles per vertex, so inform the register allocator that
2226 * we might read up to nir->info.gs.vertices_in registers.
2228 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2229 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2230 fs_reg(icp_offset_bytes
),
2231 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2234 assert(gs_prog_data
->invocations
> 1);
2236 if (nir_src_is_const(vertex_src
)) {
2237 unsigned vertex
= nir_src_as_uint(vertex_src
);
2238 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2240 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2241 BRW_REGISTER_TYPE_UD
));
2243 /* The vertex index is non-constant. We need to use indirect
2244 * addressing to fetch the proper URB handle.
2247 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2249 /* Convert vertex_index to bytes (multiply by 4) */
2250 bld
.SHL(icp_offset_bytes
,
2251 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2254 /* Use first_icp_handle as the base offset. There is one DWord
2255 * of URB handles per vertex, so inform the register allocator that
2256 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2258 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2259 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2260 fs_reg(icp_offset_bytes
),
2261 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2268 fs_reg tmp_dst
= dst
;
2269 fs_reg indirect_offset
= get_nir_src(offset_src
);
2270 unsigned num_iterations
= 1;
2271 unsigned orig_num_components
= num_components
;
2273 if (type_sz(dst
.type
) == 8) {
2274 if (num_components
> 2) {
2278 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2280 first_component
= first_component
/ 2;
2283 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2284 if (nir_src_is_const(offset_src
)) {
2285 /* Constant indexing - use global offset. */
2286 if (first_component
!= 0) {
2287 unsigned read_components
= num_components
+ first_component
;
2288 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2289 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2290 inst
->size_written
= read_components
*
2291 tmp
.component_size(inst
->exec_size
);
2292 for (unsigned i
= 0; i
< num_components
; i
++) {
2293 bld
.MOV(offset(tmp_dst
, bld
, i
),
2294 offset(tmp
, bld
, i
+ first_component
));
2297 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2299 inst
->size_written
= num_components
*
2300 tmp_dst
.component_size(inst
->exec_size
);
2302 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2305 /* Indirect indexing - use per-slot offsets as well. */
2306 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2307 unsigned read_components
= num_components
+ first_component
;
2308 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2309 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2310 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2311 if (first_component
!= 0) {
2312 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2314 inst
->size_written
= read_components
*
2315 tmp
.component_size(inst
->exec_size
);
2316 for (unsigned i
= 0; i
< num_components
; i
++) {
2317 bld
.MOV(offset(tmp_dst
, bld
, i
),
2318 offset(tmp
, bld
, i
+ first_component
));
2321 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2323 inst
->size_written
= num_components
*
2324 tmp_dst
.component_size(inst
->exec_size
);
2326 inst
->offset
= base_offset
;
2330 if (type_sz(dst
.type
) == 8) {
2331 shuffle_from_32bit_read(bld
,
2332 offset(dst
, bld
, iter
* 2),
2333 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2338 if (num_iterations
> 1) {
2339 num_components
= orig_num_components
- 2;
2340 if(nir_src_is_const(offset_src
)) {
2343 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2344 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2345 indirect_offset
= new_indirect
;
2352 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2354 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2356 if (nir_src_is_const(*offset_src
)) {
2357 /* The only constant offset we should find is 0. brw_nir.c's
2358 * add_const_offset_to_base() will fold other constant offsets
2359 * into instr->const_index[0].
2361 assert(nir_src_as_uint(*offset_src
) == 0);
2365 return get_nir_src(*offset_src
);
2369 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2370 nir_intrinsic_instr
*instr
)
2372 assert(stage
== MESA_SHADER_VERTEX
);
2375 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2376 dest
= get_nir_dest(instr
->dest
);
2378 switch (instr
->intrinsic
) {
2379 case nir_intrinsic_load_vertex_id
:
2380 case nir_intrinsic_load_base_vertex
:
2381 unreachable("should be lowered by nir_lower_system_values()");
2383 case nir_intrinsic_load_input
: {
2384 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2385 unsigned first_component
= nir_intrinsic_component(instr
);
2386 unsigned num_components
= instr
->num_components
;
2388 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2390 if (type_sz(dest
.type
) == 8)
2391 first_component
/= 2;
2393 /* For 16-bit support maybe a temporary will be needed to copy from
2396 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2397 first_component
, num_components
);
2401 case nir_intrinsic_load_vertex_id_zero_base
:
2402 case nir_intrinsic_load_instance_id
:
2403 case nir_intrinsic_load_base_instance
:
2404 case nir_intrinsic_load_draw_id
:
2405 case nir_intrinsic_load_first_vertex
:
2406 case nir_intrinsic_load_is_indexed_draw
:
2407 unreachable("lowered by brw_nir_lower_vs_inputs");
2410 nir_emit_intrinsic(bld
, instr
);
2416 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2417 nir_intrinsic_instr
*instr
)
2419 assert(stage
== MESA_SHADER_TESS_CTRL
);
2420 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2421 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2424 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2425 dst
= get_nir_dest(instr
->dest
);
2427 switch (instr
->intrinsic
) {
2428 case nir_intrinsic_load_primitive_id
:
2429 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2431 case nir_intrinsic_load_invocation_id
:
2432 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2434 case nir_intrinsic_load_patch_vertices_in
:
2435 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2436 brw_imm_d(tcs_key
->input_vertices
));
2439 case nir_intrinsic_barrier
: {
2440 if (tcs_prog_data
->instances
== 1)
2443 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2444 fs_reg m0_2
= component(m0
, 2);
2446 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2448 /* Zero the message header */
2449 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2451 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2452 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2453 brw_imm_ud(INTEL_MASK(16, 13)));
2455 /* Shift it up to bits 27:24. */
2456 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2458 /* Set the Barrier Count and the enable bit */
2459 chanbld
.OR(m0_2
, m0_2
,
2460 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2462 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2466 case nir_intrinsic_load_input
:
2467 unreachable("nir_lower_io should never give us these.");
2470 case nir_intrinsic_load_per_vertex_input
: {
2471 fs_reg indirect_offset
= get_indirect_offset(instr
);
2472 unsigned imm_offset
= instr
->const_index
[0];
2474 const nir_src
&vertex_src
= instr
->src
[0];
2480 if (nir_src_is_const(vertex_src
)) {
2481 /* Emit a MOV to resolve <0,1,0> regioning. */
2482 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2483 unsigned vertex
= nir_src_as_uint(vertex_src
);
2485 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2486 BRW_REGISTER_TYPE_UD
));
2487 } else if (tcs_prog_data
->instances
== 1 &&
2488 vertex_src
.is_ssa
&&
2489 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2490 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2491 /* For the common case of only 1 instance, an array index of
2492 * gl_InvocationID means reading g1. Skip all the indirect work.
2494 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2496 /* The vertex index is non-constant. We need to use indirect
2497 * addressing to fetch the proper URB handle.
2499 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2501 /* Each ICP handle is a single DWord (4 bytes) */
2502 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2503 bld
.SHL(vertex_offset_bytes
,
2504 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2507 /* Start at g1. We might read up to 4 registers. */
2508 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2509 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2510 brw_imm_ud(4 * REG_SIZE
));
2513 /* We can only read two double components with each URB read, so
2514 * we send two read messages in that case, each one loading up to
2515 * two double components.
2517 unsigned num_iterations
= 1;
2518 unsigned num_components
= instr
->num_components
;
2519 unsigned first_component
= nir_intrinsic_component(instr
);
2520 fs_reg orig_dst
= dst
;
2521 if (type_sz(dst
.type
) == 8) {
2522 first_component
= first_component
/ 2;
2523 if (instr
->num_components
> 2) {
2528 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2532 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2533 if (indirect_offset
.file
== BAD_FILE
) {
2534 /* Constant indexing - use global offset. */
2535 if (first_component
!= 0) {
2536 unsigned read_components
= num_components
+ first_component
;
2537 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2538 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2539 for (unsigned i
= 0; i
< num_components
; i
++) {
2540 bld
.MOV(offset(dst
, bld
, i
),
2541 offset(tmp
, bld
, i
+ first_component
));
2544 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2546 inst
->offset
= imm_offset
;
2549 /* Indirect indexing - use per-slot offsets as well. */
2550 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2551 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2552 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2553 if (first_component
!= 0) {
2554 unsigned read_components
= num_components
+ first_component
;
2555 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2556 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2558 for (unsigned i
= 0; i
< num_components
; i
++) {
2559 bld
.MOV(offset(dst
, bld
, i
),
2560 offset(tmp
, bld
, i
+ first_component
));
2563 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2566 inst
->offset
= imm_offset
;
2569 inst
->size_written
= (num_components
+ first_component
) *
2570 inst
->dst
.component_size(inst
->exec_size
);
2572 /* If we are reading 64-bit data using 32-bit read messages we need
2573 * build proper 64-bit data elements by shuffling the low and high
2574 * 32-bit components around like we do for other things like UBOs
2577 if (type_sz(dst
.type
) == 8) {
2578 shuffle_from_32bit_read(bld
,
2579 offset(orig_dst
, bld
, iter
* 2),
2580 retype(dst
, BRW_REGISTER_TYPE_D
),
2584 /* Copy the temporary to the destination to deal with writemasking.
2586 * Also attempt to deal with gl_PointSize being in the .w component.
2588 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2589 assert(type_sz(dst
.type
) < 8);
2590 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2591 inst
->size_written
= 4 * REG_SIZE
;
2592 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2595 /* If we are loading double data and we need a second read message
2596 * adjust the write offset
2598 if (num_iterations
> 1) {
2599 num_components
= instr
->num_components
- 2;
2606 case nir_intrinsic_load_output
:
2607 case nir_intrinsic_load_per_vertex_output
: {
2608 fs_reg indirect_offset
= get_indirect_offset(instr
);
2609 unsigned imm_offset
= instr
->const_index
[0];
2610 unsigned first_component
= nir_intrinsic_component(instr
);
2613 if (indirect_offset
.file
== BAD_FILE
) {
2614 /* Replicate the patch handle to all enabled channels */
2615 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2616 bld
.MOV(patch_handle
,
2617 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2620 if (first_component
!= 0) {
2621 unsigned read_components
=
2622 instr
->num_components
+ first_component
;
2623 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2624 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2626 inst
->size_written
= read_components
* REG_SIZE
;
2627 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2628 bld
.MOV(offset(dst
, bld
, i
),
2629 offset(tmp
, bld
, i
+ first_component
));
2632 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2634 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2636 inst
->offset
= imm_offset
;
2640 /* Indirect indexing - use per-slot offsets as well. */
2641 const fs_reg srcs
[] = {
2642 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2645 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2646 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2647 if (first_component
!= 0) {
2648 unsigned read_components
=
2649 instr
->num_components
+ first_component
;
2650 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2651 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2653 inst
->size_written
= read_components
* REG_SIZE
;
2654 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2655 bld
.MOV(offset(dst
, bld
, i
),
2656 offset(tmp
, bld
, i
+ first_component
));
2659 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2661 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2663 inst
->offset
= imm_offset
;
2669 case nir_intrinsic_store_output
:
2670 case nir_intrinsic_store_per_vertex_output
: {
2671 fs_reg value
= get_nir_src(instr
->src
[0]);
2672 bool is_64bit
= (instr
->src
[0].is_ssa
?
2673 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2674 fs_reg indirect_offset
= get_indirect_offset(instr
);
2675 unsigned imm_offset
= instr
->const_index
[0];
2676 unsigned mask
= instr
->const_index
[1];
2677 unsigned header_regs
= 0;
2679 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2681 if (indirect_offset
.file
!= BAD_FILE
) {
2682 srcs
[header_regs
++] = indirect_offset
;
2688 unsigned num_components
= util_last_bit(mask
);
2691 /* We can only pack two 64-bit components in a single message, so send
2692 * 2 messages if we have more components
2694 unsigned num_iterations
= 1;
2695 unsigned iter_components
= num_components
;
2696 unsigned first_component
= nir_intrinsic_component(instr
);
2698 first_component
= first_component
/ 2;
2699 if (instr
->num_components
> 2) {
2701 iter_components
= 2;
2705 mask
= mask
<< first_component
;
2707 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2708 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2709 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2710 opcode
= indirect_offset
.file
!= BAD_FILE
?
2711 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2712 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2713 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2714 /* Expand the 64-bit mask to 32-bit channels. We only handle
2715 * two channels in each iteration, so we only care about X/Y.
2717 unsigned mask32
= 0;
2718 if (mask
& WRITEMASK_X
)
2719 mask32
|= WRITEMASK_XY
;
2720 if (mask
& WRITEMASK_Y
)
2721 mask32
|= WRITEMASK_ZW
;
2723 /* If the mask does not include any of the channels X or Y there
2724 * is nothing to do in this iteration. Move on to the next couple
2725 * of 64-bit channels.
2733 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2734 opcode
= indirect_offset
.file
!= BAD_FILE
?
2735 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2736 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2738 opcode
= indirect_offset
.file
!= BAD_FILE
?
2739 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2740 SHADER_OPCODE_URB_WRITE_SIMD8
;
2743 for (unsigned i
= 0; i
< iter_components
; i
++) {
2744 if (!(mask
& (1 << (i
+ first_component
))))
2748 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2750 /* We need to shuffle the 64-bit data to match the layout
2751 * expected by our 32-bit URB write messages. We use a temporary
2754 unsigned channel
= iter
* 2 + i
;
2755 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2757 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2758 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2759 offset(dest
, bld
, 1);
2764 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2765 (is_64bit
? 2 * first_component
: first_component
);
2767 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2768 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2770 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2771 inst
->offset
= imm_offset
;
2774 /* If this is a 64-bit attribute, select the next two 64-bit channels
2775 * to be handled in the next iteration.
2786 nir_emit_intrinsic(bld
, instr
);
2792 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2793 nir_intrinsic_instr
*instr
)
2795 assert(stage
== MESA_SHADER_TESS_EVAL
);
2796 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2799 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2800 dest
= get_nir_dest(instr
->dest
);
2802 switch (instr
->intrinsic
) {
2803 case nir_intrinsic_load_primitive_id
:
2804 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2806 case nir_intrinsic_load_tess_coord
:
2807 /* gl_TessCoord is part of the payload in g1-3 */
2808 for (unsigned i
= 0; i
< 3; i
++) {
2809 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2813 case nir_intrinsic_load_input
:
2814 case nir_intrinsic_load_per_vertex_input
: {
2815 fs_reg indirect_offset
= get_indirect_offset(instr
);
2816 unsigned imm_offset
= instr
->const_index
[0];
2817 unsigned first_component
= nir_intrinsic_component(instr
);
2819 if (type_sz(dest
.type
) == 8) {
2820 first_component
= first_component
/ 2;
2824 if (indirect_offset
.file
== BAD_FILE
) {
2825 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2826 * which is 16 registers (since each holds 2 vec4 slots).
2828 unsigned slot_count
= 1;
2829 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2832 const unsigned max_push_slots
= 32;
2833 if (imm_offset
+ slot_count
<= max_push_slots
) {
2834 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2835 for (int i
= 0; i
< instr
->num_components
; i
++) {
2836 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2837 i
+ first_component
;
2838 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2841 tes_prog_data
->base
.urb_read_length
=
2842 MAX2(tes_prog_data
->base
.urb_read_length
,
2843 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2845 /* Replicate the patch handle to all enabled channels */
2846 const fs_reg srcs
[] = {
2847 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2849 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2850 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2852 if (first_component
!= 0) {
2853 unsigned read_components
=
2854 instr
->num_components
+ first_component
;
2855 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2856 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2858 inst
->size_written
= read_components
* REG_SIZE
;
2859 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2860 bld
.MOV(offset(dest
, bld
, i
),
2861 offset(tmp
, bld
, i
+ first_component
));
2864 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2866 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2869 inst
->offset
= imm_offset
;
2872 /* Indirect indexing - use per-slot offsets as well. */
2874 /* We can only read two double components with each URB read, so
2875 * we send two read messages in that case, each one loading up to
2876 * two double components.
2878 unsigned num_iterations
= 1;
2879 unsigned num_components
= instr
->num_components
;
2880 fs_reg orig_dest
= dest
;
2881 if (type_sz(dest
.type
) == 8) {
2882 if (instr
->num_components
> 2) {
2886 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2890 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2891 const fs_reg srcs
[] = {
2892 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2895 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2896 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2898 if (first_component
!= 0) {
2899 unsigned read_components
=
2900 num_components
+ first_component
;
2901 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2902 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2904 for (unsigned i
= 0; i
< num_components
; i
++) {
2905 bld
.MOV(offset(dest
, bld
, i
),
2906 offset(tmp
, bld
, i
+ first_component
));
2909 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2913 inst
->offset
= imm_offset
;
2914 inst
->size_written
= (num_components
+ first_component
) *
2915 inst
->dst
.component_size(inst
->exec_size
);
2917 /* If we are reading 64-bit data using 32-bit read messages we need
2918 * build proper 64-bit data elements by shuffling the low and high
2919 * 32-bit components around like we do for other things like UBOs
2922 if (type_sz(dest
.type
) == 8) {
2923 shuffle_from_32bit_read(bld
,
2924 offset(orig_dest
, bld
, iter
* 2),
2925 retype(dest
, BRW_REGISTER_TYPE_D
),
2929 /* If we are loading double data and we need a second read message
2932 if (num_iterations
> 1) {
2933 num_components
= instr
->num_components
- 2;
2941 nir_emit_intrinsic(bld
, instr
);
2947 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2948 nir_intrinsic_instr
*instr
)
2950 assert(stage
== MESA_SHADER_GEOMETRY
);
2951 fs_reg indirect_offset
;
2954 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2955 dest
= get_nir_dest(instr
->dest
);
2957 switch (instr
->intrinsic
) {
2958 case nir_intrinsic_load_primitive_id
:
2959 assert(stage
== MESA_SHADER_GEOMETRY
);
2960 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2961 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2962 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2965 case nir_intrinsic_load_input
:
2966 unreachable("load_input intrinsics are invalid for the GS stage");
2968 case nir_intrinsic_load_per_vertex_input
:
2969 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2970 instr
->src
[1], instr
->num_components
,
2971 nir_intrinsic_component(instr
));
2974 case nir_intrinsic_emit_vertex_with_counter
:
2975 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2978 case nir_intrinsic_end_primitive_with_counter
:
2979 emit_gs_end_primitive(instr
->src
[0]);
2982 case nir_intrinsic_set_vertex_count
:
2983 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2986 case nir_intrinsic_load_invocation_id
: {
2987 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2988 assert(val
.file
!= BAD_FILE
);
2989 dest
.type
= val
.type
;
2995 nir_emit_intrinsic(bld
, instr
);
3001 * Fetch the current render target layer index.
3004 fetch_render_target_array_index(const fs_builder
&bld
)
3006 if (bld
.shader
->devinfo
->gen
>= 6) {
3007 /* The render target array index is provided in the thread payload as
3008 * bits 26:16 of r0.0.
3010 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3011 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3015 /* Pre-SNB we only ever render into the first layer of the framebuffer
3016 * since layered rendering is not implemented.
3018 return brw_imm_ud(0);
3023 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3024 * framebuffer at the current fragment coordinates and sample index.
3027 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3030 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3032 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3033 const brw_wm_prog_key
*wm_key
=
3034 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3035 assert(!wm_key
->coherent_fb_fetch
);
3036 const struct brw_wm_prog_data
*wm_prog_data
=
3037 brw_wm_prog_data(stage_prog_data
);
3039 /* Calculate the surface index relative to the start of the texture binding
3040 * table block, since that's what the texturing messages expect.
3042 const unsigned surface
= target
+
3043 wm_prog_data
->binding_table
.render_target_read_start
-
3044 wm_prog_data
->base
.binding_table
.texture_start
;
3046 /* Calculate the fragment coordinates. */
3047 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3048 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3049 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3050 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3052 /* Calculate the sample index and MCS payload when multisampling. Luckily
3053 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3054 * shouldn't be necessary to recompile based on whether the framebuffer is
3057 if (wm_key
->multisample_fbo
&&
3058 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3059 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3061 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3062 const fs_reg mcs
= wm_key
->multisample_fbo
?
3063 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3065 /* Use either a normal or a CMS texel fetch message depending on whether
3066 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3067 * message just in case the framebuffer uses 16x multisampling, it should
3068 * be equivalent to the normal CMS fetch for lower multisampling modes.
3070 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3071 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3072 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3074 /* Emit the instruction. */
3075 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3076 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3077 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3078 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3079 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3080 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3081 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3082 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3083 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3085 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3086 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3092 * Actual coherent framebuffer read implemented using the native render target
3093 * read message. Requires SKL+.
3096 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3098 assert(bld
.shader
->devinfo
->gen
>= 9);
3099 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3100 inst
->target
= target
;
3101 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3107 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3109 if (n
&& regs
[0].file
!= BAD_FILE
) {
3113 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3115 for (unsigned i
= 0; i
< n
; i
++)
3123 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3125 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3126 const brw_wm_prog_key
*const key
=
3127 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3128 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3129 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3131 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3132 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3134 else if (l
== FRAG_RESULT_COLOR
)
3135 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3136 MAX2(key
->nr_color_regions
, 1));
3138 else if (l
== FRAG_RESULT_DEPTH
)
3139 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3141 else if (l
== FRAG_RESULT_STENCIL
)
3142 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3144 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3145 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3147 else if (l
>= FRAG_RESULT_DATA0
&&
3148 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3149 return alloc_temporary(v
->bld
, 4,
3150 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3153 unreachable("Invalid location");
3157 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3158 nir_intrinsic_instr
*instr
)
3160 assert(stage
== MESA_SHADER_FRAGMENT
);
3163 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3164 dest
= get_nir_dest(instr
->dest
);
3166 switch (instr
->intrinsic
) {
3167 case nir_intrinsic_load_front_face
:
3168 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3169 *emit_frontfacing_interpolation());
3172 case nir_intrinsic_load_sample_pos
: {
3173 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3174 assert(sample_pos
.file
!= BAD_FILE
);
3175 dest
.type
= sample_pos
.type
;
3176 bld
.MOV(dest
, sample_pos
);
3177 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3181 case nir_intrinsic_load_layer_id
:
3182 dest
.type
= BRW_REGISTER_TYPE_UD
;
3183 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3186 case nir_intrinsic_load_helper_invocation
:
3187 case nir_intrinsic_load_sample_mask_in
:
3188 case nir_intrinsic_load_sample_id
: {
3189 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3190 fs_reg val
= nir_system_values
[sv
];
3191 assert(val
.file
!= BAD_FILE
);
3192 dest
.type
= val
.type
;
3197 case nir_intrinsic_store_output
: {
3198 const fs_reg src
= get_nir_src(instr
->src
[0]);
3199 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3200 const unsigned location
= nir_intrinsic_base(instr
) +
3201 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3202 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3205 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3206 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3207 offset(src
, bld
, j
));
3212 case nir_intrinsic_load_output
: {
3213 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3214 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3215 assert(l
>= FRAG_RESULT_DATA0
);
3216 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3217 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3218 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3220 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3221 emit_coherent_fb_read(bld
, tmp
, target
);
3223 emit_non_coherent_fb_read(bld
, tmp
, target
);
3225 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3226 bld
.MOV(offset(dest
, bld
, j
),
3227 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3233 case nir_intrinsic_discard
:
3234 case nir_intrinsic_discard_if
: {
3235 /* We track our discarded pixels in f0.1. By predicating on it, we can
3236 * update just the flag bits that aren't yet discarded. If there's no
3237 * condition, we emit a CMP of g0 != g0, so all currently executing
3238 * channels will get turned off.
3241 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3242 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3243 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3245 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3246 BRW_REGISTER_TYPE_UW
));
3247 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3249 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3250 cmp
->flag_subreg
= 1;
3252 if (devinfo
->gen
>= 6) {
3253 emit_discard_jump();
3256 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3260 case nir_intrinsic_load_input
: {
3261 /* load_input is only used for flat inputs */
3262 unsigned base
= nir_intrinsic_base(instr
);
3263 unsigned comp
= nir_intrinsic_component(instr
);
3264 unsigned num_components
= instr
->num_components
;
3265 fs_reg orig_dest
= dest
;
3266 enum brw_reg_type type
= dest
.type
;
3268 /* Special case fields in the VUE header */
3269 if (base
== VARYING_SLOT_LAYER
)
3271 else if (base
== VARYING_SLOT_VIEWPORT
)
3274 if (nir_dest_bit_size(instr
->dest
) == 64) {
3275 /* const_index is in 32-bit type size units that could not be aligned
3276 * with DF. We need to read the double vector as if it was a float
3277 * vector of twice the number of components to fetch the right data.
3279 type
= BRW_REGISTER_TYPE_F
;
3280 num_components
*= 2;
3281 dest
= bld
.vgrf(type
, num_components
);
3284 for (unsigned int i
= 0; i
< num_components
; i
++) {
3285 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3286 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3289 if (nir_dest_bit_size(instr
->dest
) == 64) {
3290 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3291 instr
->num_components
);
3296 case nir_intrinsic_load_barycentric_pixel
:
3297 case nir_intrinsic_load_barycentric_centroid
:
3298 case nir_intrinsic_load_barycentric_sample
:
3299 /* Do nothing - load_interpolated_input handling will handle it later. */
3302 case nir_intrinsic_load_barycentric_at_sample
: {
3303 const glsl_interp_mode interpolation
=
3304 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3306 if (nir_src_is_const(instr
->src
[0])) {
3307 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3309 emit_pixel_interpolater_send(bld
,
3310 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3313 brw_imm_ud(msg_data
),
3316 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3317 BRW_REGISTER_TYPE_UD
);
3319 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3320 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3321 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3322 bld
.exec_all().group(1, 0)
3323 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3324 emit_pixel_interpolater_send(bld
,
3325 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3331 /* Make a loop that sends a message to the pixel interpolater
3332 * for the sample number in each live channel. If there are
3333 * multiple channels with the same sample number then these
3334 * will be handled simultaneously with a single interation of
3337 bld
.emit(BRW_OPCODE_DO
);
3339 /* Get the next live sample number into sample_id_reg */
3340 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3342 /* Set the flag register so that we can perform the send
3343 * message on all channels that have the same sample number
3345 bld
.CMP(bld
.null_reg_ud(),
3346 sample_src
, sample_id
,
3347 BRW_CONDITIONAL_EQ
);
3348 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3349 bld
.exec_all().group(1, 0)
3350 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3352 emit_pixel_interpolater_send(bld
,
3353 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3356 component(msg_data
, 0),
3358 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3360 /* Continue the loop if there are any live channels left */
3361 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3363 bld
.emit(BRW_OPCODE_WHILE
));
3369 case nir_intrinsic_load_barycentric_at_offset
: {
3370 const glsl_interp_mode interpolation
=
3371 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3373 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3376 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3377 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3378 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3380 emit_pixel_interpolater_send(bld
,
3381 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3384 brw_imm_ud(off_x
| (off_y
<< 4)),
3387 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3388 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3389 BRW_REGISTER_TYPE_F
);
3390 for (int i
= 0; i
< 2; i
++) {
3391 fs_reg temp
= vgrf(glsl_type::float_type
);
3392 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3393 fs_reg itemp
= vgrf(glsl_type::int_type
);
3395 bld
.MOV(itemp
, temp
);
3397 /* Clamp the upper end of the range to +7/16.
3398 * ARB_gpu_shader5 requires that we support a maximum offset
3399 * of +0.5, which isn't representable in a S0.4 value -- if
3400 * we didn't clamp it, we'd end up with -8/16, which is the
3401 * opposite of what the shader author wanted.
3403 * This is legal due to ARB_gpu_shader5's quantization
3406 * "Not all values of <offset> may be supported; x and y
3407 * offsets may be rounded to fixed-point values with the
3408 * number of fraction bits given by the
3409 * implementation-dependent constant
3410 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3412 set_condmod(BRW_CONDITIONAL_L
,
3413 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3416 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3417 emit_pixel_interpolater_send(bld
,
3427 case nir_intrinsic_load_interpolated_input
: {
3428 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3429 emit_fragcoord_interpolation(dest
);
3433 assert(instr
->src
[0].ssa
&&
3434 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3435 nir_intrinsic_instr
*bary_intrinsic
=
3436 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3437 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3438 enum glsl_interp_mode interp_mode
=
3439 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3442 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3443 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3444 /* Use the result of the PI message */
3445 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3447 /* Use the delta_xy values computed from the payload */
3448 enum brw_barycentric_mode bary
=
3449 brw_barycentric_mode(interp_mode
, bary_intrin
);
3451 dst_xy
= this->delta_xy
[bary
];
3454 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3456 component(interp_reg(nir_intrinsic_base(instr
),
3457 nir_intrinsic_component(instr
) + i
), 0);
3458 interp
.type
= BRW_REGISTER_TYPE_F
;
3459 dest
.type
= BRW_REGISTER_TYPE_F
;
3461 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3462 fs_reg tmp
= vgrf(glsl_type::float_type
);
3463 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3464 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3466 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3473 nir_emit_intrinsic(bld
, instr
);
3479 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3481 if (nir_src_is_const(instr
->src
[src
])) {
3482 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3485 else if (add_val
== -1)
3493 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3494 nir_intrinsic_instr
*instr
)
3496 assert(stage
== MESA_SHADER_COMPUTE
);
3497 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3500 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3501 dest
= get_nir_dest(instr
->dest
);
3503 switch (instr
->intrinsic
) {
3504 case nir_intrinsic_barrier
:
3506 cs_prog_data
->uses_barrier
= true;
3509 case nir_intrinsic_load_subgroup_id
:
3510 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3513 case nir_intrinsic_load_local_invocation_id
:
3514 case nir_intrinsic_load_work_group_id
: {
3515 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3516 fs_reg val
= nir_system_values
[sv
];
3517 assert(val
.file
!= BAD_FILE
);
3518 dest
.type
= val
.type
;
3519 for (unsigned i
= 0; i
< 3; i
++)
3520 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3524 case nir_intrinsic_load_num_work_groups
: {
3525 const unsigned surface
=
3526 cs_prog_data
->binding_table
.work_groups_start
;
3528 cs_prog_data
->uses_num_work_groups
= true;
3530 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3531 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3532 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3533 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3535 /* Read the 3 GLuint components of gl_NumWorkGroups */
3536 for (unsigned i
= 0; i
< 3; i
++) {
3537 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3538 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3539 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3544 case nir_intrinsic_shared_atomic_add
:
3545 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3547 case nir_intrinsic_shared_atomic_imin
:
3548 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3550 case nir_intrinsic_shared_atomic_umin
:
3551 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3553 case nir_intrinsic_shared_atomic_imax
:
3554 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3556 case nir_intrinsic_shared_atomic_umax
:
3557 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3559 case nir_intrinsic_shared_atomic_and
:
3560 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3562 case nir_intrinsic_shared_atomic_or
:
3563 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3565 case nir_intrinsic_shared_atomic_xor
:
3566 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3568 case nir_intrinsic_shared_atomic_exchange
:
3569 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3571 case nir_intrinsic_shared_atomic_comp_swap
:
3572 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3574 case nir_intrinsic_shared_atomic_fmin
:
3575 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3577 case nir_intrinsic_shared_atomic_fmax
:
3578 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3580 case nir_intrinsic_shared_atomic_fcomp_swap
:
3581 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3584 case nir_intrinsic_load_shared
: {
3585 assert(devinfo
->gen
>= 7);
3586 assert(stage
== MESA_SHADER_COMPUTE
);
3588 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3589 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3590 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3591 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3592 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3594 /* Make dest unsigned because that's what the temporary will be */
3595 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3597 /* Read the vector */
3598 if (nir_intrinsic_align(instr
) >= 4) {
3599 assert(nir_dest_bit_size(instr
->dest
) == 32);
3600 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3602 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3603 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3604 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3606 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3607 assert(nir_dest_num_components(instr
->dest
) == 1);
3608 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3610 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3611 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3612 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3613 bld
.MOV(dest
, read_result
);
3618 case nir_intrinsic_store_shared
: {
3619 assert(devinfo
->gen
>= 7);
3620 assert(stage
== MESA_SHADER_COMPUTE
);
3622 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3623 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3624 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3625 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3626 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3628 fs_reg data
= get_nir_src(instr
->src
[0]);
3629 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3631 assert(nir_intrinsic_write_mask(instr
) ==
3632 (1u << instr
->num_components
) - 1);
3633 if (nir_intrinsic_align(instr
) >= 4) {
3634 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3635 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3636 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3637 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3638 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3639 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3641 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3642 assert(nir_src_num_components(instr
->src
[0]) == 1);
3643 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3645 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3646 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3648 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3649 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3655 nir_emit_intrinsic(bld
, instr
);
3661 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3662 nir_op op
, brw_reg_type type
)
3664 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3665 switch (type_sz(type
)) {
3667 assert(type
!= BRW_REGISTER_TYPE_HF
);
3668 return retype(brw_imm_uw(value
.u16
[0]), type
);
3670 return retype(brw_imm_ud(value
.u32
[0]), type
);
3672 if (type
== BRW_REGISTER_TYPE_DF
)
3673 return setup_imm_df(bld
, value
.f64
[0]);
3675 return retype(brw_imm_u64(value
.u64
[0]), type
);
3677 unreachable("Invalid type size");
3682 brw_op_for_nir_reduction_op(nir_op op
)
3685 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3686 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3687 case nir_op_imul
: return BRW_OPCODE_MUL
;
3688 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3689 case nir_op_imin
: return BRW_OPCODE_SEL
;
3690 case nir_op_umin
: return BRW_OPCODE_SEL
;
3691 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3692 case nir_op_imax
: return BRW_OPCODE_SEL
;
3693 case nir_op_umax
: return BRW_OPCODE_SEL
;
3694 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3695 case nir_op_iand
: return BRW_OPCODE_AND
;
3696 case nir_op_ior
: return BRW_OPCODE_OR
;
3697 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3699 unreachable("Invalid reduction operation");
3703 static brw_conditional_mod
3704 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3707 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3708 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3709 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3710 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3711 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3712 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3713 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3714 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3715 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3716 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3717 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3718 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3719 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3721 unreachable("Invalid reduction operation");
3726 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3727 nir_intrinsic_instr
*instr
)
3729 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3731 if (stage_prog_data
->binding_table
.image_start
> 0) {
3732 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3733 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3735 bld
.ADD(image
, image
,
3736 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3740 return bld
.emit_uniformize(image
);
3744 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3745 nir_intrinsic_instr
*instr
)
3747 /* SSBO stores are weird in that their index is in src[1] */
3748 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3751 if (nir_src_is_const(instr
->src
[src
])) {
3752 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3753 nir_src_as_uint(instr
->src
[src
]);
3754 surf_index
= brw_imm_ud(index
);
3756 surf_index
= vgrf(glsl_type::uint_type
);
3757 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3758 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3761 return bld
.emit_uniformize(surf_index
);
3765 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3767 switch (nir_intrinsic_image_dim(instr
)) {
3768 case GLSL_SAMPLER_DIM_1D
:
3769 return 1 + nir_intrinsic_image_array(instr
);
3770 case GLSL_SAMPLER_DIM_2D
:
3771 case GLSL_SAMPLER_DIM_RECT
:
3772 return 2 + nir_intrinsic_image_array(instr
);
3773 case GLSL_SAMPLER_DIM_3D
:
3774 case GLSL_SAMPLER_DIM_CUBE
:
3776 case GLSL_SAMPLER_DIM_BUF
:
3778 case GLSL_SAMPLER_DIM_MS
:
3779 return 2 + nir_intrinsic_image_array(instr
);
3781 unreachable("Invalid image dimension");
3786 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3789 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3790 dest
= get_nir_dest(instr
->dest
);
3792 switch (instr
->intrinsic
) {
3793 case nir_intrinsic_image_load
:
3794 case nir_intrinsic_image_store
:
3795 case nir_intrinsic_image_atomic_add
:
3796 case nir_intrinsic_image_atomic_min
:
3797 case nir_intrinsic_image_atomic_max
:
3798 case nir_intrinsic_image_atomic_and
:
3799 case nir_intrinsic_image_atomic_or
:
3800 case nir_intrinsic_image_atomic_xor
:
3801 case nir_intrinsic_image_atomic_exchange
:
3802 case nir_intrinsic_image_atomic_comp_swap
: {
3803 if (stage
== MESA_SHADER_FRAGMENT
&&
3804 instr
->intrinsic
!= nir_intrinsic_image_load
)
3805 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3807 /* Get some metadata from the image intrinsic. */
3808 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3809 const GLenum format
= nir_intrinsic_format(instr
);
3811 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3812 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3813 get_nir_image_intrinsic_image(bld
, instr
);
3814 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3815 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
3816 brw_imm_ud(image_intrinsic_coord_components(instr
));
3818 /* Emit an image load, store or atomic op. */
3819 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3820 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3822 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
3823 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3824 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3825 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3826 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3827 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
3828 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
3829 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3832 unsigned num_srcs
= info
->num_srcs
;
3834 switch (instr
->intrinsic
) {
3835 case nir_intrinsic_image_atomic_add
:
3836 assert(num_srcs
== 4);
3838 op
= get_op_for_atomic_add(instr
, 3);
3840 if (op
!= BRW_AOP_ADD
)
3843 case nir_intrinsic_image_atomic_min
:
3844 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3845 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3847 case nir_intrinsic_image_atomic_max
:
3848 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3849 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3851 case nir_intrinsic_image_atomic_and
:
3854 case nir_intrinsic_image_atomic_or
:
3857 case nir_intrinsic_image_atomic_xor
:
3860 case nir_intrinsic_image_atomic_exchange
:
3863 case nir_intrinsic_image_atomic_comp_swap
:
3867 unreachable("Not reachable.");
3870 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
3874 data
= get_nir_src(instr
->src
[3]);
3875 if (num_srcs
>= 5) {
3876 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
3877 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
3878 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
3881 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3883 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
3884 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3889 case nir_intrinsic_image_size
: {
3890 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3891 * into will handle the binding table index for us in the geneerator.
3893 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3894 BRW_REGISTER_TYPE_UD
);
3895 image
= bld
.emit_uniformize(image
);
3897 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3898 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
3899 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
3900 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
3901 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
3903 /* Since the image size is always uniform, we can just emit a SIMD8
3904 * query instruction and splat the result out.
3906 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3908 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3909 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
3910 tmp
, srcs
, ARRAY_SIZE(srcs
));
3911 inst
->size_written
= 4 * REG_SIZE
;
3913 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3914 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3915 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3916 offset(retype(dest
, tmp
.type
), bld
, c
),
3917 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3919 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3920 component(offset(tmp
, ubld
, c
), 0));
3926 case nir_intrinsic_image_load_raw_intel
: {
3927 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3928 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3929 get_nir_image_intrinsic_image(bld
, instr
);
3930 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3931 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3932 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3935 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3936 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3937 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3941 case nir_intrinsic_image_store_raw_intel
: {
3942 if (stage
== MESA_SHADER_FRAGMENT
)
3943 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3945 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3946 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3947 get_nir_image_intrinsic_image(bld
, instr
);
3948 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3949 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
3950 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3951 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3953 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3954 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3958 case nir_intrinsic_group_memory_barrier
:
3959 case nir_intrinsic_memory_barrier_shared
:
3960 case nir_intrinsic_memory_barrier_atomic_counter
:
3961 case nir_intrinsic_memory_barrier_buffer
:
3962 case nir_intrinsic_memory_barrier_image
:
3963 case nir_intrinsic_memory_barrier
: {
3964 const fs_builder ubld
= bld
.group(8, 0);
3965 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3966 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3967 ->size_written
= 2 * REG_SIZE
;
3971 case nir_intrinsic_shader_clock
: {
3972 /* We cannot do anything if there is an event, so ignore it for now */
3973 const fs_reg shader_clock
= get_timestamp(bld
);
3974 const fs_reg srcs
[] = { component(shader_clock
, 0),
3975 component(shader_clock
, 1) };
3976 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3980 case nir_intrinsic_image_samples
:
3981 /* The driver does not support multi-sampled images. */
3982 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3985 case nir_intrinsic_load_uniform
: {
3986 /* Offsets are in bytes but they should always aligned to
3989 assert(instr
->const_index
[0] % 4 == 0 ||
3990 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3992 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3994 if (nir_src_is_const(instr
->src
[0])) {
3995 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3996 assert(load_offset
% type_sz(dest
.type
) == 0);
3997 /* For 16-bit types we add the module of the const_index[0]
3998 * offset to access to not 32-bit aligned element
4000 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4002 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4003 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4006 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4007 BRW_REGISTER_TYPE_UD
);
4009 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4010 * go past the end of the uniform. In order to keep the n'th
4011 * component from running past, we subtract off the size of all but
4012 * one component of the vector.
4014 assert(instr
->const_index
[1] >=
4015 instr
->num_components
* (int) type_sz(dest
.type
));
4016 unsigned read_size
= instr
->const_index
[1] -
4017 (instr
->num_components
- 1) * type_sz(dest
.type
);
4019 bool supports_64bit_indirects
=
4020 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4022 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4023 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4024 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4025 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4026 indirect
, brw_imm_ud(read_size
));
4029 const unsigned num_mov_indirects
=
4030 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4031 /* We read a little bit less per MOV INDIRECT, as they are now
4032 * 32-bits ones instead of 64-bit. Fix read_size then.
4034 const unsigned read_size_32bit
= read_size
-
4035 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4036 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4037 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4038 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4039 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4040 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4041 indirect
, brw_imm_ud(read_size_32bit
));
4049 case nir_intrinsic_load_ubo
: {
4051 if (nir_src_is_const(instr
->src
[0])) {
4052 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4053 nir_src_as_uint(instr
->src
[0]);
4054 surf_index
= brw_imm_ud(index
);
4056 /* The block index is not a constant. Evaluate the index expression
4057 * per-channel and add the base UBO index; we have to select a value
4058 * from any live channel.
4060 surf_index
= vgrf(glsl_type::uint_type
);
4061 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4062 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4063 surf_index
= bld
.emit_uniformize(surf_index
);
4066 if (!nir_src_is_const(instr
->src
[1])) {
4067 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4068 BRW_REGISTER_TYPE_UD
);
4070 for (int i
= 0; i
< instr
->num_components
; i
++)
4071 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4072 base_offset
, i
* type_sz(dest
.type
));
4074 /* Even if we are loading doubles, a pull constant load will load
4075 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4076 * need to load a full dvec4 we will have to emit 2 loads. This is
4077 * similar to demote_pull_constants(), except that in that case we
4078 * see individual accesses to each component of the vector and then
4079 * we let CSE deal with duplicate loads. Here we see a vector access
4080 * and we have to split it if necessary.
4082 const unsigned type_size
= type_sz(dest
.type
);
4083 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4085 /* See if we've selected this as a push constant candidate */
4086 if (nir_src_is_const(instr
->src
[0])) {
4087 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4088 const unsigned offset_256b
= load_offset
/ 32;
4091 for (int i
= 0; i
< 4; i
++) {
4092 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4093 if (range
->block
== ubo_block
&&
4094 offset_256b
>= range
->start
&&
4095 offset_256b
< range
->start
+ range
->length
) {
4097 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4098 push_reg
.offset
= load_offset
- 32 * range
->start
;
4103 if (push_reg
.file
!= BAD_FILE
) {
4104 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4105 bld
.MOV(offset(dest
, bld
, i
),
4106 byte_offset(push_reg
, i
* type_size
));
4112 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4113 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4114 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4116 for (unsigned c
= 0; c
< instr
->num_components
;) {
4117 const unsigned base
= load_offset
+ c
* type_size
;
4118 /* Number of usable components in the next block-aligned load. */
4119 const unsigned count
= MIN2(instr
->num_components
- c
,
4120 (block_sz
- base
% block_sz
) / type_size
);
4122 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4123 packed_consts
, surf_index
,
4124 brw_imm_ud(base
& ~(block_sz
- 1)));
4126 const fs_reg consts
=
4127 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4130 for (unsigned d
= 0; d
< count
; d
++)
4131 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4139 case nir_intrinsic_load_global
: {
4140 assert(devinfo
->gen
>= 8);
4142 if (nir_intrinsic_align(instr
) >= 4) {
4143 assert(nir_dest_bit_size(instr
->dest
) == 32);
4144 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4146 get_nir_src(instr
->src
[0]), /* Address */
4147 fs_reg(), /* No source data */
4148 brw_imm_ud(instr
->num_components
));
4149 inst
->size_written
= instr
->num_components
*
4150 inst
->dst
.component_size(inst
->exec_size
);
4152 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4153 assert(bit_size
<= 32);
4154 assert(nir_dest_num_components(instr
->dest
) == 1);
4155 brw_reg_type data_type
=
4156 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4157 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4158 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4160 get_nir_src(instr
->src
[0]), /* Address */
4161 fs_reg(), /* No source data */
4162 brw_imm_ud(bit_size
));
4163 bld
.MOV(retype(dest
, data_type
), tmp
);
4168 case nir_intrinsic_store_global
:
4169 assert(devinfo
->gen
>= 8);
4171 if (stage
== MESA_SHADER_FRAGMENT
)
4172 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4174 if (nir_intrinsic_align(instr
) >= 4) {
4175 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4176 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4178 get_nir_src(instr
->src
[1]), /* Address */
4179 get_nir_src(instr
->src
[0]), /* Data */
4180 brw_imm_ud(instr
->num_components
));
4182 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4183 assert(bit_size
<= 32);
4184 assert(nir_src_num_components(instr
->src
[0]) == 1);
4185 brw_reg_type data_type
=
4186 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4187 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4188 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4189 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4191 get_nir_src(instr
->src
[1]), /* Address */
4193 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4197 case nir_intrinsic_global_atomic_add
:
4198 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4200 case nir_intrinsic_global_atomic_imin
:
4201 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4203 case nir_intrinsic_global_atomic_umin
:
4204 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4206 case nir_intrinsic_global_atomic_imax
:
4207 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4209 case nir_intrinsic_global_atomic_umax
:
4210 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4212 case nir_intrinsic_global_atomic_and
:
4213 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4215 case nir_intrinsic_global_atomic_or
:
4216 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4218 case nir_intrinsic_global_atomic_xor
:
4219 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4221 case nir_intrinsic_global_atomic_exchange
:
4222 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4224 case nir_intrinsic_global_atomic_comp_swap
:
4225 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4227 case nir_intrinsic_global_atomic_fmin
:
4228 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4230 case nir_intrinsic_global_atomic_fmax
:
4231 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4233 case nir_intrinsic_global_atomic_fcomp_swap
:
4234 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4237 case nir_intrinsic_load_ssbo
: {
4238 assert(devinfo
->gen
>= 7);
4240 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4241 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4242 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4243 get_nir_ssbo_intrinsic_index(bld
, instr
);
4244 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4245 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4247 /* Make dest unsigned because that's what the temporary will be */
4248 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4250 /* Read the vector */
4251 if (nir_intrinsic_align(instr
) >= 4) {
4252 assert(nir_dest_bit_size(instr
->dest
) == 32);
4253 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4255 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4256 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4257 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4259 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4260 assert(nir_dest_num_components(instr
->dest
) == 1);
4261 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4263 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4264 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4265 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4266 bld
.MOV(dest
, read_result
);
4271 case nir_intrinsic_store_ssbo
: {
4272 assert(devinfo
->gen
>= 7);
4274 if (stage
== MESA_SHADER_FRAGMENT
)
4275 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4277 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4278 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4279 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4280 get_nir_ssbo_intrinsic_index(bld
, instr
);
4281 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4282 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4284 fs_reg data
= get_nir_src(instr
->src
[0]);
4285 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4287 assert(nir_intrinsic_write_mask(instr
) ==
4288 (1u << instr
->num_components
) - 1);
4289 if (nir_intrinsic_align(instr
) >= 4) {
4290 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4291 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4292 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4293 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4294 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4295 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4297 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4298 assert(nir_src_num_components(instr
->src
[0]) == 1);
4299 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4301 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4302 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4304 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4305 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4310 case nir_intrinsic_store_output
: {
4311 fs_reg src
= get_nir_src(instr
->src
[0]);
4313 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4314 unsigned num_components
= instr
->num_components
;
4315 unsigned first_component
= nir_intrinsic_component(instr
);
4316 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4317 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4318 num_components
*= 2;
4321 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4322 4 * store_offset
), src
.type
);
4323 for (unsigned j
= 0; j
< num_components
; j
++) {
4324 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4325 offset(src
, bld
, j
));
4330 case nir_intrinsic_ssbo_atomic_add
:
4331 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4333 case nir_intrinsic_ssbo_atomic_imin
:
4334 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4336 case nir_intrinsic_ssbo_atomic_umin
:
4337 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4339 case nir_intrinsic_ssbo_atomic_imax
:
4340 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4342 case nir_intrinsic_ssbo_atomic_umax
:
4343 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4345 case nir_intrinsic_ssbo_atomic_and
:
4346 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4348 case nir_intrinsic_ssbo_atomic_or
:
4349 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4351 case nir_intrinsic_ssbo_atomic_xor
:
4352 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4354 case nir_intrinsic_ssbo_atomic_exchange
:
4355 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4357 case nir_intrinsic_ssbo_atomic_comp_swap
:
4358 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4360 case nir_intrinsic_ssbo_atomic_fmin
:
4361 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4363 case nir_intrinsic_ssbo_atomic_fmax
:
4364 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4366 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4367 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4370 case nir_intrinsic_get_buffer_size
: {
4371 assert(nir_src_num_components(instr
->src
[0]) == 1);
4372 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4373 nir_src_as_uint(instr
->src
[0]) : 0;
4375 /* A resinfo's sampler message is used to get the buffer size. The
4376 * SIMD8's writeback message consists of four registers and SIMD16's
4377 * writeback message consists of 8 destination registers (two per each
4378 * component). Because we are only interested on the first channel of
4379 * the first returned component, where resinfo returns the buffer size
4380 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4381 * the dispatch width.
4383 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4384 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4385 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4388 ubld
.MOV(src_payload
, brw_imm_d(0));
4390 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4391 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4392 src_payload
, brw_imm_ud(index
));
4393 inst
->header_size
= 0;
4395 inst
->size_written
= 4 * REG_SIZE
;
4397 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4399 * "Out-of-bounds checking is always performed at a DWord granularity. If
4400 * any part of the DWord is out-of-bounds then the whole DWord is
4401 * considered out-of-bounds."
4403 * This implies that types with size smaller than 4-bytes need to be
4404 * padded if they don't complete the last dword of the buffer. But as we
4405 * need to maintain the original size we need to reverse the padding
4406 * calculation to return the correct size to know the number of elements
4407 * of an unsized array. As we stored in the last two bits of the surface
4408 * size the needed padding for the buffer, we calculate here the
4409 * original buffer_size reversing the surface_size calculation:
4411 * surface_size = isl_align(buffer_size, 4) +
4412 * (isl_align(buffer_size) - buffer_size)
4414 * buffer_size = surface_size & ~3 - surface_size & 3
4417 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4418 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4419 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4421 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4422 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4423 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4425 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4429 case nir_intrinsic_load_subgroup_invocation
:
4430 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4431 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4434 case nir_intrinsic_load_subgroup_eq_mask
:
4435 case nir_intrinsic_load_subgroup_ge_mask
:
4436 case nir_intrinsic_load_subgroup_gt_mask
:
4437 case nir_intrinsic_load_subgroup_le_mask
:
4438 case nir_intrinsic_load_subgroup_lt_mask
:
4439 unreachable("not reached");
4441 case nir_intrinsic_vote_any
: {
4442 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4444 /* The any/all predicates do not consider channel enables. To prevent
4445 * dead channels from affecting the result, we initialize the flag with
4446 * with the identity value for the logical operation.
4448 if (dispatch_width
== 32) {
4449 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4450 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4453 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4455 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4457 /* For some reason, the any/all predicates don't work properly with
4458 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4459 * doesn't read the correct subset of the flag register and you end up
4460 * getting garbage in the second half. Work around this by using a pair
4461 * of 1-wide MOVs and scattering the result.
4463 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4464 ubld
.MOV(res1
, brw_imm_d(0));
4465 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4466 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4467 BRW_PREDICATE_ALIGN1_ANY32H
,
4468 ubld
.MOV(res1
, brw_imm_d(-1)));
4470 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4473 case nir_intrinsic_vote_all
: {
4474 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4476 /* The any/all predicates do not consider channel enables. To prevent
4477 * dead channels from affecting the result, we initialize the flag with
4478 * with the identity value for the logical operation.
4480 if (dispatch_width
== 32) {
4481 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4482 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4483 brw_imm_ud(0xffffffff));
4485 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4487 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4489 /* For some reason, the any/all predicates don't work properly with
4490 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4491 * doesn't read the correct subset of the flag register and you end up
4492 * getting garbage in the second half. Work around this by using a pair
4493 * of 1-wide MOVs and scattering the result.
4495 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4496 ubld
.MOV(res1
, brw_imm_d(0));
4497 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4498 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4499 BRW_PREDICATE_ALIGN1_ALL32H
,
4500 ubld
.MOV(res1
, brw_imm_d(-1)));
4502 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4505 case nir_intrinsic_vote_feq
:
4506 case nir_intrinsic_vote_ieq
: {
4507 fs_reg value
= get_nir_src(instr
->src
[0]);
4508 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4509 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4510 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4513 fs_reg uniformized
= bld
.emit_uniformize(value
);
4514 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4516 /* The any/all predicates do not consider channel enables. To prevent
4517 * dead channels from affecting the result, we initialize the flag with
4518 * with the identity value for the logical operation.
4520 if (dispatch_width
== 32) {
4521 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4522 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4523 brw_imm_ud(0xffffffff));
4525 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4527 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4529 /* For some reason, the any/all predicates don't work properly with
4530 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4531 * doesn't read the correct subset of the flag register and you end up
4532 * getting garbage in the second half. Work around this by using a pair
4533 * of 1-wide MOVs and scattering the result.
4535 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4536 ubld
.MOV(res1
, brw_imm_d(0));
4537 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4538 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4539 BRW_PREDICATE_ALIGN1_ALL32H
,
4540 ubld
.MOV(res1
, brw_imm_d(-1)));
4542 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4546 case nir_intrinsic_ballot
: {
4547 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4548 BRW_REGISTER_TYPE_UD
);
4549 struct brw_reg flag
= brw_flag_reg(0, 0);
4550 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4551 * as f0.0. This is a problem for fragment programs as we currently use
4552 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4553 * programs yet so this isn't a problem. When we do, something will
4556 if (dispatch_width
== 32)
4557 flag
.type
= BRW_REGISTER_TYPE_UD
;
4559 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4560 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4562 if (instr
->dest
.ssa
.bit_size
> 32) {
4563 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4565 dest
.type
= BRW_REGISTER_TYPE_UD
;
4567 bld
.MOV(dest
, flag
);
4571 case nir_intrinsic_read_invocation
: {
4572 const fs_reg value
= get_nir_src(instr
->src
[0]);
4573 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4574 fs_reg tmp
= bld
.vgrf(value
.type
);
4576 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4577 bld
.emit_uniformize(invocation
));
4579 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4583 case nir_intrinsic_read_first_invocation
: {
4584 const fs_reg value
= get_nir_src(instr
->src
[0]);
4585 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4589 case nir_intrinsic_shuffle
: {
4590 const fs_reg value
= get_nir_src(instr
->src
[0]);
4591 const fs_reg index
= get_nir_src(instr
->src
[1]);
4593 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4597 case nir_intrinsic_first_invocation
: {
4598 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4599 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4600 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4601 fs_reg(component(tmp
, 0)));
4605 case nir_intrinsic_quad_broadcast
: {
4606 const fs_reg value
= get_nir_src(instr
->src
[0]);
4607 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4609 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4610 value
, brw_imm_ud(index
), brw_imm_ud(4));
4614 case nir_intrinsic_quad_swap_horizontal
: {
4615 const fs_reg value
= get_nir_src(instr
->src
[0]);
4616 const fs_reg tmp
= bld
.vgrf(value
.type
);
4617 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4619 const fs_reg src_left
= horiz_stride(value
, 2);
4620 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4621 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4622 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4624 ubld
.MOV(tmp_left
, src_right
);
4625 ubld
.MOV(tmp_right
, src_left
);
4627 bld
.MOV(retype(dest
, value
.type
), tmp
);
4631 case nir_intrinsic_quad_swap_vertical
: {
4632 const fs_reg value
= get_nir_src(instr
->src
[0]);
4633 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4634 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4635 const fs_reg tmp
= bld
.vgrf(value
.type
);
4636 const fs_builder ubld
= bld
.exec_all();
4637 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4638 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4639 bld
.MOV(retype(dest
, value
.type
), tmp
);
4641 /* For larger data types, we have to either emit dispatch_width many
4642 * MOVs or else fall back to doing indirects.
4644 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4645 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4647 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4652 case nir_intrinsic_quad_swap_diagonal
: {
4653 const fs_reg value
= get_nir_src(instr
->src
[0]);
4654 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4655 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4656 const fs_reg tmp
= bld
.vgrf(value
.type
);
4657 const fs_builder ubld
= bld
.exec_all();
4658 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4659 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4660 bld
.MOV(retype(dest
, value
.type
), tmp
);
4662 /* For larger data types, we have to either emit dispatch_width many
4663 * MOVs or else fall back to doing indirects.
4665 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4666 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4668 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4673 case nir_intrinsic_reduce
: {
4674 fs_reg src
= get_nir_src(instr
->src
[0]);
4675 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4676 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4677 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4678 cluster_size
= dispatch_width
;
4680 /* Figure out the source type */
4681 src
.type
= brw_type_for_nir_type(devinfo
,
4682 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4683 nir_src_bit_size(instr
->src
[0])));
4685 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4686 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4687 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4689 /* Set up a register for all of our scratching around and initialize it
4690 * to reduction operation's identity value.
4692 fs_reg scan
= bld
.vgrf(src
.type
);
4693 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4695 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4697 dest
.type
= src
.type
;
4698 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4699 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4700 * the distance between clusters is at least 2 GRFs. In this case,
4701 * we don't need the weird striding of the CLUSTER_BROADCAST
4702 * instruction and can just do regular MOVs.
4704 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4705 const unsigned groups
=
4706 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4707 const unsigned group_size
= dispatch_width
/ groups
;
4708 for (unsigned i
= 0; i
< groups
; i
++) {
4709 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4710 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4711 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4712 component(scan
, comp
));
4715 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4716 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4721 case nir_intrinsic_inclusive_scan
:
4722 case nir_intrinsic_exclusive_scan
: {
4723 fs_reg src
= get_nir_src(instr
->src
[0]);
4724 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4726 /* Figure out the source type */
4727 src
.type
= brw_type_for_nir_type(devinfo
,
4728 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4729 nir_src_bit_size(instr
->src
[0])));
4731 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4732 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4733 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4735 /* Set up a register for all of our scratching around and initialize it
4736 * to reduction operation's identity value.
4738 fs_reg scan
= bld
.vgrf(src
.type
);
4739 const fs_builder allbld
= bld
.exec_all();
4740 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4742 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4743 /* Exclusive scan is a bit harder because we have to do an annoying
4744 * shift of the contents before we can begin. To make things worse,
4745 * we can't do this with a normal stride; we have to use indirects.
4747 fs_reg shifted
= bld
.vgrf(src
.type
);
4748 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4749 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4751 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4752 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4756 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4758 bld
.MOV(retype(dest
, src
.type
), scan
);
4762 case nir_intrinsic_begin_invocation_interlock
: {
4763 const fs_builder ubld
= bld
.group(8, 0);
4764 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4766 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4772 case nir_intrinsic_end_invocation_interlock
: {
4773 /* We don't need to do anything here */
4778 unreachable("unknown intrinsic");
4783 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4784 int op
, nir_intrinsic_instr
*instr
)
4786 if (stage
== MESA_SHADER_FRAGMENT
)
4787 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4790 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4791 dest
= get_nir_dest(instr
->dest
);
4793 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4794 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4795 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4796 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4797 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4800 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4801 data
= get_nir_src(instr
->src
[2]);
4803 if (op
== BRW_AOP_CMPWR
) {
4804 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4805 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4806 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4809 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4811 /* Emit the actual atomic operation */
4813 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4814 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4818 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4819 int op
, nir_intrinsic_instr
*instr
)
4821 if (stage
== MESA_SHADER_FRAGMENT
)
4822 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4825 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4826 dest
= get_nir_dest(instr
->dest
);
4828 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4829 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4830 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4831 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4832 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4834 fs_reg data
= get_nir_src(instr
->src
[2]);
4835 if (op
== BRW_AOP_FCMPWR
) {
4836 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4837 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4838 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4841 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4843 /* Emit the actual atomic operation */
4845 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4846 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4850 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4851 int op
, nir_intrinsic_instr
*instr
)
4854 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4855 dest
= get_nir_dest(instr
->dest
);
4857 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4858 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4859 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4860 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4863 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4864 data
= get_nir_src(instr
->src
[1]);
4865 if (op
== BRW_AOP_CMPWR
) {
4866 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4867 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4868 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4871 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4873 /* Get the offset */
4874 if (nir_src_is_const(instr
->src
[0])) {
4875 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4876 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4878 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4879 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4880 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4881 brw_imm_ud(instr
->const_index
[0]));
4884 /* Emit the actual atomic operation operation */
4886 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4887 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4891 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4892 int op
, nir_intrinsic_instr
*instr
)
4895 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4896 dest
= get_nir_dest(instr
->dest
);
4898 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4899 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4900 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4901 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4903 fs_reg data
= get_nir_src(instr
->src
[1]);
4904 if (op
== BRW_AOP_FCMPWR
) {
4905 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4906 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4907 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4910 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4912 /* Get the offset */
4913 if (nir_src_is_const(instr
->src
[0])) {
4914 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4915 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4917 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4918 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4919 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4920 brw_imm_ud(instr
->const_index
[0]));
4923 /* Emit the actual atomic operation operation */
4925 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4926 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4930 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
4931 int op
, nir_intrinsic_instr
*instr
)
4933 if (stage
== MESA_SHADER_FRAGMENT
)
4934 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4937 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4938 dest
= get_nir_dest(instr
->dest
);
4940 fs_reg addr
= get_nir_src(instr
->src
[0]);
4943 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4944 data
= get_nir_src(instr
->src
[1]);
4946 if (op
== BRW_AOP_CMPWR
) {
4947 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4948 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4949 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4953 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4954 dest
, addr
, data
, brw_imm_ud(op
));
4958 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
4959 int op
, nir_intrinsic_instr
*instr
)
4961 if (stage
== MESA_SHADER_FRAGMENT
)
4962 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4964 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
4965 fs_reg dest
= get_nir_dest(instr
->dest
);
4967 fs_reg addr
= get_nir_src(instr
->src
[0]);
4969 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
4970 fs_reg data
= get_nir_src(instr
->src
[1]);
4972 if (op
== BRW_AOP_FCMPWR
) {
4973 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4974 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4975 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4979 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4980 dest
, addr
, data
, brw_imm_ud(op
));
4984 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4986 unsigned texture
= instr
->texture_index
;
4987 unsigned sampler
= instr
->sampler_index
;
4989 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4991 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4992 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4994 int lod_components
= 0;
4996 /* The hardware requires a LOD for buffer textures */
4997 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4998 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5000 uint32_t header_bits
= 0;
5001 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5002 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5003 switch (instr
->src
[i
].src_type
) {
5004 case nir_tex_src_bias
:
5005 srcs
[TEX_LOGICAL_SRC_LOD
] =
5006 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5008 case nir_tex_src_comparator
:
5009 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5011 case nir_tex_src_coord
:
5012 switch (instr
->op
) {
5014 case nir_texop_txf_ms
:
5015 case nir_texop_txf_ms_mcs
:
5016 case nir_texop_samples_identical
:
5017 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5020 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5024 case nir_tex_src_ddx
:
5025 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5026 lod_components
= nir_tex_instr_src_size(instr
, i
);
5028 case nir_tex_src_ddy
:
5029 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5031 case nir_tex_src_lod
:
5032 switch (instr
->op
) {
5034 srcs
[TEX_LOGICAL_SRC_LOD
] =
5035 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5038 srcs
[TEX_LOGICAL_SRC_LOD
] =
5039 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5042 srcs
[TEX_LOGICAL_SRC_LOD
] =
5043 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5047 case nir_tex_src_min_lod
:
5048 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5049 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5051 case nir_tex_src_ms_index
:
5052 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5055 case nir_tex_src_offset
: {
5056 nir_const_value
*const_offset
=
5057 nir_src_as_const_value(instr
->src
[i
].src
);
5058 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
5059 unsigned offset_bits
= 0;
5061 brw_texture_offset(const_offset
->i32
,
5062 nir_tex_instr_src_size(instr
, i
),
5064 header_bits
|= offset_bits
;
5066 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5067 retype(src
, BRW_REGISTER_TYPE_D
);
5072 case nir_tex_src_projector
:
5073 unreachable("should be lowered");
5075 case nir_tex_src_texture_offset
: {
5076 /* Emit code to evaluate the actual indexing expression */
5077 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5078 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5079 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5083 case nir_tex_src_sampler_offset
: {
5084 /* Emit code to evaluate the actual indexing expression */
5085 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5086 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5087 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5091 case nir_tex_src_ms_mcs
:
5092 assert(instr
->op
== nir_texop_txf_ms
);
5093 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5096 case nir_tex_src_plane
: {
5097 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5098 const uint32_t texture_index
=
5099 instr
->texture_index
+
5100 stage_prog_data
->binding_table
.plane_start
[plane
] -
5101 stage_prog_data
->binding_table
.texture_start
;
5103 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5108 unreachable("unknown texture source");
5112 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5113 (instr
->op
== nir_texop_txf_ms
||
5114 instr
->op
== nir_texop_samples_identical
)) {
5115 if (devinfo
->gen
>= 7 &&
5116 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5117 srcs
[TEX_LOGICAL_SRC_MCS
] =
5118 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5119 instr
->coord_components
,
5120 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5122 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5126 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5127 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5130 switch (instr
->op
) {
5132 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5133 SHADER_OPCODE_TXL_LOGICAL
);
5136 opcode
= FS_OPCODE_TXB_LOGICAL
;
5139 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5142 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5145 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5147 case nir_texop_txf_ms
:
5148 if ((key_tex
->msaa_16
& (1 << sampler
)))
5149 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5151 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5153 case nir_texop_txf_ms_mcs
:
5154 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5156 case nir_texop_query_levels
:
5158 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5161 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5164 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5165 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5167 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5169 case nir_texop_texture_samples
:
5170 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5172 case nir_texop_samples_identical
: {
5173 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5175 /* If mcs is an immediate value, it means there is no MCS. In that case
5176 * just return false.
5178 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5179 bld
.MOV(dst
, brw_imm_ud(0u));
5180 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5181 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5182 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5183 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5184 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5186 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5187 BRW_CONDITIONAL_EQ
);
5192 unreachable("unknown texture opcode");
5195 if (instr
->op
== nir_texop_tg4
) {
5196 if (instr
->component
== 1 &&
5197 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5198 /* gather4 sampler is broken for green channel on RG32F --
5199 * we must ask for blue instead.
5201 header_bits
|= 2 << 16;
5203 header_bits
|= instr
->component
<< 16;
5207 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5208 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5209 inst
->offset
= header_bits
;
5211 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5212 if (devinfo
->gen
>= 9 &&
5213 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5214 unsigned write_mask
= instr
->dest
.is_ssa
?
5215 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5216 (1 << dest_size
) - 1;
5217 assert(write_mask
!= 0); /* dead code should have been eliminated */
5218 inst
->size_written
= util_last_bit(write_mask
) *
5219 inst
->dst
.component_size(inst
->exec_size
);
5221 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5224 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5225 inst
->shadow_compare
= true;
5227 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5228 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5231 for (unsigned i
= 0; i
< dest_size
; i
++)
5232 nir_dest
[i
] = offset(dst
, bld
, i
);
5234 if (instr
->op
== nir_texop_query_levels
) {
5235 /* # levels is in .w */
5236 nir_dest
[0] = offset(dst
, bld
, 3);
5237 } else if (instr
->op
== nir_texop_txs
&&
5238 dest_size
>= 3 && devinfo
->gen
< 7) {
5239 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5240 fs_reg depth
= offset(dst
, bld
, 2);
5241 nir_dest
[2] = vgrf(glsl_type::int_type
);
5242 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5245 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5249 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5251 switch (instr
->type
) {
5252 case nir_jump_break
:
5253 bld
.emit(BRW_OPCODE_BREAK
);
5255 case nir_jump_continue
:
5256 bld
.emit(BRW_OPCODE_CONTINUE
);
5258 case nir_jump_return
:
5260 unreachable("unknown jump");
5265 * This helper takes a source register and un/shuffles it into the destination
5268 * If source type size is smaller than destination type size the operation
5269 * needed is a component shuffle. The opposite case would be an unshuffle. If
5270 * source/destination type size is equal a shuffle is done that would be
5271 * equivalent to a simple MOV.
5273 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5274 * components .xyz 16-bit vector on SIMD8 would be.
5276 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5277 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5279 * This helper will return the following 2 32-bit components with the 16-bit
5282 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5283 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5285 * For unshuffle, the example would be the opposite, a 64-bit type source
5286 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5289 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5290 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5291 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5292 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5294 * The returned result would be the following 4 32-bit components unshuffled:
5296 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5297 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5298 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5299 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5301 * - Source and destination register must not be overlapped.
5302 * - components units are measured in terms of the smaller type between
5303 * source and destination because we are un/shuffling the smaller
5304 * components from/into the bigger ones.
5305 * - first_component parameter allows skipping source components.
5308 shuffle_src_to_dst(const fs_builder
&bld
,
5311 uint32_t first_component
,
5312 uint32_t components
)
5314 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5315 assert(!regions_overlap(dst
,
5316 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5317 offset(src
, bld
, first_component
),
5318 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5319 for (unsigned i
= 0; i
< components
; i
++) {
5320 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5321 offset(src
, bld
, i
+ first_component
));
5323 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5324 /* Source is shuffled into destination */
5325 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5326 assert(!regions_overlap(dst
,
5327 type_sz(dst
.type
) * bld
.dispatch_width() *
5328 DIV_ROUND_UP(components
, size_ratio
),
5329 offset(src
, bld
, first_component
),
5330 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5332 brw_reg_type shuffle_type
=
5333 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5334 BRW_REGISTER_TYPE_D
);
5335 for (unsigned i
= 0; i
< components
; i
++) {
5336 fs_reg shuffle_component_i
=
5337 subscript(offset(dst
, bld
, i
/ size_ratio
),
5338 shuffle_type
, i
% size_ratio
);
5339 bld
.MOV(shuffle_component_i
,
5340 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5343 /* Source is unshuffled into destination */
5344 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5345 assert(!regions_overlap(dst
,
5346 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5347 offset(src
, bld
, first_component
/ size_ratio
),
5348 type_sz(src
.type
) * bld
.dispatch_width() *
5349 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5352 brw_reg_type shuffle_type
=
5353 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5354 BRW_REGISTER_TYPE_D
);
5355 for (unsigned i
= 0; i
< components
; i
++) {
5356 fs_reg shuffle_component_i
=
5357 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5358 shuffle_type
, (first_component
+ i
) % size_ratio
);
5359 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5360 shuffle_component_i
);
5366 shuffle_from_32bit_read(const fs_builder
&bld
,
5369 uint32_t first_component
,
5370 uint32_t components
)
5372 assert(type_sz(src
.type
) == 4);
5374 /* This function takes components in units of the destination type while
5375 * shuffle_src_to_dst takes components in units of the smallest type
5377 if (type_sz(dst
.type
) > 4) {
5378 assert(type_sz(dst
.type
) == 8);
5379 first_component
*= 2;
5383 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5387 shuffle_for_32bit_write(const fs_builder
&bld
,
5389 uint32_t first_component
,
5390 uint32_t components
)
5392 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5393 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5394 /* This function takes components in units of the source type while
5395 * shuffle_src_to_dst takes components in units of the smallest type
5397 if (type_sz(src
.type
) > 4) {
5398 assert(type_sz(src
.type
) == 8);
5399 first_component
*= 2;
5403 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5409 setup_imm_df(const fs_builder
&bld
, double v
)
5411 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5412 assert(devinfo
->gen
>= 7);
5414 if (devinfo
->gen
>= 8)
5415 return brw_imm_df(v
);
5417 /* gen7.5 does not support DF immediates straighforward but the DIM
5418 * instruction allows to set the 64-bit immediate value.
5420 if (devinfo
->is_haswell
) {
5421 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5422 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5423 ubld
.DIM(dst
, brw_imm_df(v
));
5424 return component(dst
, 0);
5427 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5428 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5429 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5431 * Alternatively, we could also produce a normal VGRF (without stride 0)
5432 * by writing to all the channels in the VGRF, however, that would hit the
5433 * gen7 bug where we have to split writes that span more than 1 register
5434 * into instructions with a width of 4 (otherwise the write to the second
5435 * register written runs into an execmask hardware bug) which isn't very
5448 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5449 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5450 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5451 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5453 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5457 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5459 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5460 bld
.MOV(tmp
, brw_imm_w(v
));
5465 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5467 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5468 bld
.MOV(tmp
, brw_imm_uw(v
));