2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "nir_search_helpers.h"
28 #include "util/u_math.h"
29 #include "util/bitscan.h"
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
47 fs_visitor::nir_setup_outputs()
49 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
52 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
54 /* Calculate the size of output registers in a separate pass, before
55 * allocating them. With ARB_enhanced_layouts, multiple output variables
56 * may occupy the same slot, but have different type sizes.
58 nir_foreach_variable(var
, &nir
->outputs
) {
59 const int loc
= var
->data
.driver_location
;
60 const unsigned var_vec4s
=
61 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
62 : type_size_vec4(var
->type
, true);
63 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
66 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
67 if (vec4s
[loc
] == 0) {
72 unsigned reg_size
= vec4s
[loc
];
74 /* Check if there are any ranges that start within this range and extend
75 * past it. If so, include them in this allocation.
77 for (unsigned i
= 1; i
< reg_size
; i
++)
78 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
80 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
81 for (unsigned i
= 0; i
< reg_size
; i
++)
82 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
89 fs_visitor::nir_setup_uniforms()
91 /* Only the first compile gets to set up uniforms. */
92 if (push_constant_loc
) {
93 assert(pull_constant_loc
);
97 uniforms
= nir
->num_uniforms
/ 4;
99 if (stage
== MESA_SHADER_COMPUTE
) {
100 /* Add a uniform for the thread local id. It must be the last uniform
103 assert(uniforms
== prog_data
->nr_params
);
104 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
105 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
106 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
111 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
115 nir_foreach_instr(instr
, block
) {
116 if (instr
->type
!= nir_instr_type_intrinsic
)
119 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
120 switch (intrin
->intrinsic
) {
121 case nir_intrinsic_load_vertex_id
:
122 case nir_intrinsic_load_base_vertex
:
123 unreachable("should be lowered by nir_lower_system_values().");
125 case nir_intrinsic_load_vertex_id_zero_base
:
126 case nir_intrinsic_load_is_indexed_draw
:
127 case nir_intrinsic_load_first_vertex
:
128 case nir_intrinsic_load_instance_id
:
129 case nir_intrinsic_load_base_instance
:
130 case nir_intrinsic_load_draw_id
:
131 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
133 case nir_intrinsic_load_invocation_id
:
134 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
136 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
137 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
138 if (reg
->file
== BAD_FILE
) {
139 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
140 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
141 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
142 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
147 case nir_intrinsic_load_sample_pos
:
148 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_samplepos_setup();
154 case nir_intrinsic_load_sample_id
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
157 if (reg
->file
== BAD_FILE
)
158 *reg
= *v
->emit_sampleid_setup();
161 case nir_intrinsic_load_sample_mask_in
:
162 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
163 assert(v
->devinfo
->gen
>= 7);
164 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
165 if (reg
->file
== BAD_FILE
)
166 *reg
= *v
->emit_samplemaskin_setup();
169 case nir_intrinsic_load_work_group_id
:
170 assert(v
->stage
== MESA_SHADER_COMPUTE
);
171 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
172 if (reg
->file
== BAD_FILE
)
173 *reg
= *v
->emit_cs_work_group_id_setup();
176 case nir_intrinsic_load_helper_invocation
:
177 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
178 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
179 if (reg
->file
== BAD_FILE
) {
180 const fs_builder abld
=
181 v
->bld
.annotate("gl_HelperInvocation", NULL
);
183 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
184 * pixel mask is in g1.7 of the thread payload.
186 * We move the per-channel pixel enable bit to the low bit of each
187 * channel by shifting the byte containing the pixel mask by the
188 * vector immediate 0x76543210UV.
190 * The region of <1,8,0> reads only 1 byte (the pixel masks for
191 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
192 * masks for 2 and 3) in SIMD16.
194 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
196 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
197 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
198 hbld
.SHR(offset(shifted
, hbld
, i
),
199 stride(retype(brw_vec1_grf(1 + i
, 7),
200 BRW_REGISTER_TYPE_UB
),
202 brw_imm_v(0x76543210));
205 /* A set bit in the pixel mask means the channel is enabled, but
206 * that is the opposite of gl_HelperInvocation so we need to invert
209 * The negate source-modifier bit of logical instructions on Gen8+
210 * performs 1's complement negation, so we can use that instead of
213 fs_reg inverted
= negate(shifted
);
214 if (v
->devinfo
->gen
< 8) {
215 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
216 abld
.NOT(inverted
, shifted
);
219 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
220 * with 1 and negating.
222 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
223 abld
.AND(anded
, inverted
, brw_imm_uw(1));
225 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
226 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
240 fs_visitor::nir_emit_system_values()
242 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
243 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
244 nir_system_values
[i
] = fs_reg();
247 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
248 * never end up using it.
251 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
252 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
253 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
255 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
256 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
257 if (dispatch_width
> 8)
258 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
259 if (dispatch_width
> 16) {
260 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
261 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
265 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
266 nir_foreach_block(block
, impl
)
267 emit_system_values_block(block
, this);
271 * Returns a type based on a reference_type (word, float, half-float) and a
274 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
276 * @FIXME: 64-bit return types are always DF on integer types to maintain
277 * compability with uses of DF previously to the introduction of int64
281 brw_reg_type_from_bit_size(const unsigned bit_size
,
282 const brw_reg_type reference_type
)
284 switch(reference_type
) {
285 case BRW_REGISTER_TYPE_HF
:
286 case BRW_REGISTER_TYPE_F
:
287 case BRW_REGISTER_TYPE_DF
:
290 return BRW_REGISTER_TYPE_HF
;
292 return BRW_REGISTER_TYPE_F
;
294 return BRW_REGISTER_TYPE_DF
;
296 unreachable("Invalid bit size");
298 case BRW_REGISTER_TYPE_B
:
299 case BRW_REGISTER_TYPE_W
:
300 case BRW_REGISTER_TYPE_D
:
301 case BRW_REGISTER_TYPE_Q
:
304 return BRW_REGISTER_TYPE_B
;
306 return BRW_REGISTER_TYPE_W
;
308 return BRW_REGISTER_TYPE_D
;
310 return BRW_REGISTER_TYPE_Q
;
312 unreachable("Invalid bit size");
314 case BRW_REGISTER_TYPE_UB
:
315 case BRW_REGISTER_TYPE_UW
:
316 case BRW_REGISTER_TYPE_UD
:
317 case BRW_REGISTER_TYPE_UQ
:
320 return BRW_REGISTER_TYPE_UB
;
322 return BRW_REGISTER_TYPE_UW
;
324 return BRW_REGISTER_TYPE_UD
;
326 return BRW_REGISTER_TYPE_UQ
;
328 unreachable("Invalid bit size");
331 unreachable("Unknown type");
336 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
338 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
339 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
340 nir_locals
[i
] = fs_reg();
343 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
344 unsigned array_elems
=
345 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
346 unsigned size
= array_elems
* reg
->num_components
;
347 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
348 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
349 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
352 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
355 nir_emit_cf_list(&impl
->body
);
359 fs_visitor::nir_emit_cf_list(exec_list
*list
)
361 exec_list_validate(list
);
362 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
363 switch (node
->type
) {
365 nir_emit_if(nir_cf_node_as_if(node
));
368 case nir_cf_node_loop
:
369 nir_emit_loop(nir_cf_node_as_loop(node
));
372 case nir_cf_node_block
:
373 nir_emit_block(nir_cf_node_as_block(node
));
377 unreachable("Invalid CFG node block");
383 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
388 /* If the condition has the form !other_condition, use other_condition as
389 * the source, but invert the predicate on the if instruction.
391 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
392 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
393 assert(!cond
->src
[0].negate
);
394 assert(!cond
->src
[0].abs
);
397 cond_reg
= get_nir_src(cond
->src
[0].src
);
400 cond_reg
= get_nir_src(if_stmt
->condition
);
403 /* first, put the condition into f0 */
404 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
405 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
406 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
408 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
410 nir_emit_cf_list(&if_stmt
->then_list
);
412 /* note: if the else is empty, dead CF elimination will remove it */
413 bld
.emit(BRW_OPCODE_ELSE
);
415 nir_emit_cf_list(&if_stmt
->else_list
);
417 bld
.emit(BRW_OPCODE_ENDIF
);
419 if (devinfo
->gen
< 7)
420 limit_dispatch_width(16, "Non-uniform control flow unsupported "
425 fs_visitor::nir_emit_loop(nir_loop
*loop
)
427 bld
.emit(BRW_OPCODE_DO
);
429 nir_emit_cf_list(&loop
->body
);
431 bld
.emit(BRW_OPCODE_WHILE
);
433 if (devinfo
->gen
< 7)
434 limit_dispatch_width(16, "Non-uniform control flow unsupported "
439 fs_visitor::nir_emit_block(nir_block
*block
)
441 nir_foreach_instr(instr
, block
) {
442 nir_emit_instr(instr
);
447 fs_visitor::nir_emit_instr(nir_instr
*instr
)
449 const fs_builder abld
= bld
.annotate(NULL
, instr
);
451 switch (instr
->type
) {
452 case nir_instr_type_alu
:
453 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
456 case nir_instr_type_deref
:
457 /* Derefs can exist for images but they do nothing */
460 case nir_instr_type_intrinsic
:
462 case MESA_SHADER_VERTEX
:
463 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_TESS_CTRL
:
466 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_TESS_EVAL
:
469 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_GEOMETRY
:
472 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_FRAGMENT
:
475 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
477 case MESA_SHADER_COMPUTE
:
478 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
481 unreachable("unsupported shader stage");
485 case nir_instr_type_tex
:
486 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
489 case nir_instr_type_load_const
:
490 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
493 case nir_instr_type_ssa_undef
:
494 /* We create a new VGRF for undefs on every use (by handling
495 * them in get_nir_src()), rather than for each definition.
496 * This helps register coalescing eliminate MOVs from undef.
500 case nir_instr_type_jump
:
501 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
505 unreachable("unknown instruction type");
510 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
514 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
515 const fs_reg
&result
)
517 if (!instr
->src
[0].src
.is_ssa
||
518 !instr
->src
[0].src
.ssa
->parent_instr
)
521 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
524 nir_alu_instr
*src0
=
525 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
527 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
528 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
531 /* If either opcode has source modifiers, bail.
533 * TODO: We can potentially handle source modifiers if both of the opcodes
534 * we're combining are signed integers.
536 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
537 src0
->src
[0].abs
|| src0
->src
[0].negate
)
540 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
542 /* Element type to extract.*/
543 const brw_reg_type type
= brw_int_type(
544 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
545 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
547 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
548 op0
.type
= brw_type_for_nir_type(devinfo
,
549 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
550 nir_src_bit_size(src0
->src
[0].src
)));
551 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
553 set_saturate(instr
->dest
.saturate
,
554 bld
.MOV(result
, subscript(op0
, type
, element
)));
559 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
560 const fs_reg
&result
)
562 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
563 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
566 if (!nir_src_is_const(instr
->src
[1].src
) ||
567 !nir_src_is_const(instr
->src
[2].src
))
570 const float value1
= nir_src_as_float(instr
->src
[1].src
);
571 const float value2
= nir_src_as_float(instr
->src
[2].src
);
572 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
575 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
576 assert(value1
== -value2
);
578 fs_reg tmp
= vgrf(glsl_type::int_type
);
580 if (devinfo
->gen
>= 6) {
581 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
582 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
584 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
586 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
587 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
589 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
591 * This negation looks like it's safe in practice, because bits 0:4 will
592 * surely be TRIANGLES
595 if (value1
== -1.0f
) {
599 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
600 g0
, brw_imm_uw(0x3f80));
602 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
603 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
605 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
607 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
608 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
610 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
612 * This negation looks like it's safe in practice, because bits 0:4 will
613 * surely be TRIANGLES
616 if (value1
== -1.0f
) {
620 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
622 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
628 emit_find_msb_using_lzd(const fs_builder
&bld
,
629 const fs_reg
&result
,
637 /* LZD of an absolute value source almost always does the right
638 * thing. There are two problem values:
640 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
641 * 0. However, findMSB(int(0x80000000)) == 30.
643 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
644 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
646 * For a value of zero or negative one, -1 will be returned.
648 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
649 * findMSB(-(1<<x)) should return x-1.
651 * For all negative number cases, including 0x80000000 and
652 * 0xffffffff, the correct value is obtained from LZD if instead of
653 * negating the (already negative) value the logical-not is used. A
654 * conditonal logical-not can be achieved in two instructions.
656 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
658 bld
.ASR(temp
, src
, brw_imm_d(31));
659 bld
.XOR(temp
, temp
, src
);
662 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
663 retype(temp
, BRW_REGISTER_TYPE_UD
));
665 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
666 * from the LSB side. Subtract the result from 31 to convert the MSB
667 * count into an LSB count. If no bits are set, LZD will return 32.
668 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
670 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
671 inst
->src
[0].negate
= true;
675 brw_rnd_mode_from_nir_op (const nir_op op
) {
677 case nir_op_f2f16_rtz
:
678 return BRW_RND_MODE_RTZ
;
679 case nir_op_f2f16_rtne
:
680 return BRW_RND_MODE_RTNE
;
682 unreachable("Operation doesn't support rounding mode");
687 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
688 nir_alu_instr
*instr
,
693 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
695 result
.type
= brw_type_for_nir_type(devinfo
,
696 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
697 nir_dest_bit_size(instr
->dest
.dest
)));
699 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
700 op
[i
] = get_nir_src(instr
->src
[i
].src
);
701 op
[i
].type
= brw_type_for_nir_type(devinfo
,
702 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
703 nir_src_bit_size(instr
->src
[i
].src
)));
704 op
[i
].abs
= instr
->src
[i
].abs
;
705 op
[i
].negate
= instr
->src
[i
].negate
;
708 /* Move and vecN instrutions may still be vectored. Return the raw,
709 * vectored source and destination so that fs_visitor::nir_emit_alu can
710 * handle it. Other callers should not have to handle these kinds of
724 /* At this point, we have dealt with any instruction that operates on
725 * more than a single channel. Therefore, we can just adjust the source
726 * and destination registers for that channel and emit the instruction.
728 unsigned channel
= 0;
729 if (nir_op_infos
[instr
->op
].output_size
== 0) {
730 /* Since NIR is doing the scalarizing for us, we should only ever see
731 * vectorized operations with a single channel.
733 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
734 channel
= ffs(instr
->dest
.write_mask
) - 1;
736 result
= offset(result
, bld
, channel
);
739 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
740 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
741 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
748 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
751 for (unsigned i
= 0; i
< 2; i
++) {
752 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
754 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
755 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
756 /* The source of the inot is now the source of instr. */
757 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
759 assert(!op
[i
].negate
);
762 op
[i
] = resolve_source_modifiers(op
[i
]);
768 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
770 nir_alu_instr
*instr
)
772 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
775 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
777 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
780 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
781 * of valid size-changing combinations is a bit more complex.
783 * The source restriction is just because I was lazy about generating the
786 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
787 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
790 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
791 * this is float(1 + a).
795 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
797 /* Ignore the saturate modifier, if there is one. The result of the
798 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
800 bld
.ADD(result
, op
, brw_imm_d(1));
806 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
808 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
809 * the source of \c instr that is a \c nir_op_fsign.
812 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
813 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
817 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
818 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
820 if (instr
->op
!= nir_op_fsign
) {
821 const nir_alu_instr
*const fsign_instr
=
822 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
824 assert(!fsign_instr
->dest
.saturate
);
826 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
827 * fsign_src] has the other multiply source. This must be rearranged so
828 * that op[0] is the source of the fsign op[1] is the other multiply
834 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
836 const nir_alu_type t
=
837 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
838 nir_src_bit_size(fsign_instr
->src
[0].src
));
840 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
841 op
[0].abs
= fsign_instr
->src
[0].abs
;
842 op
[0].negate
= fsign_instr
->src
[0].negate
;
844 unsigned channel
= 0;
845 if (nir_op_infos
[instr
->op
].output_size
== 0) {
846 /* Since NIR is doing the scalarizing for us, we should only ever see
847 * vectorized operations with a single channel.
849 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
850 channel
= ffs(instr
->dest
.write_mask
) - 1;
853 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
855 assert(!instr
->dest
.saturate
);
859 /* Straightforward since the source can be assumed to be either strictly
860 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
862 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
864 if (instr
->op
== nir_op_fsign
) {
865 inst
= (op
[0].negate
)
866 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
867 : bld
.MOV(result
, brw_imm_f(1.0f
));
869 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
870 inst
= bld
.MOV(result
, op
[1]);
873 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
874 } else if (type_sz(op
[0].type
) < 8) {
875 /* AND(val, 0x80000000) gives the sign bit.
877 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
880 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
882 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
883 op
[0].type
= BRW_REGISTER_TYPE_UD
;
884 result
.type
= BRW_REGISTER_TYPE_UD
;
885 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
887 if (instr
->op
== nir_op_fsign
)
888 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
890 /* Use XOR here to get the result sign correct. */
891 inst
= bld
.XOR(result_int
, result_int
,
892 retype(op
[1], BRW_REGISTER_TYPE_UD
));
895 inst
->predicate
= BRW_PREDICATE_NORMAL
;
897 /* For doubles we do the same but we need to consider:
899 * - 2-src instructions can't operate with 64-bit immediates
900 * - The sign is encoded in the high 32-bit of each DF
901 * - We need to produce a DF result.
904 fs_reg zero
= vgrf(glsl_type::double_type
);
905 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
906 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
908 bld
.MOV(result
, zero
);
910 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
911 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
912 brw_imm_ud(0x80000000u
));
914 if (instr
->op
== nir_op_fsign
) {
915 set_predicate(BRW_PREDICATE_NORMAL
,
916 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
918 /* This could be done better in some cases. If the scale is an
919 * immediate with the low 32-bits all 0, emitting a separate XOR and
920 * OR would allow an algebraic optimization to remove the OR. There
921 * are currently zero instances of fsign(double(x))*IMM in shader-db
922 * or any test suite, so it is hard to care at this time.
924 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
925 inst
= bld
.XOR(result_int64
, result_int64
,
926 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
932 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
934 * Checks the operands of a \c nir_op_fmul to determine whether or not
935 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
937 * \param instr The multiplication instruction
939 * \param fsign_src The source of \c instr that may or may not be a
943 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
945 assert(instr
->op
== nir_op_fmul
);
947 nir_alu_instr
*const fsign_instr
=
948 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
952 * 1. instr->src[fsign_src] must be a nir_op_fsign.
953 * 2. The nir_op_fsign can only be used by this multiplication.
954 * 3. The source that is the nir_op_fsign does not have source modifiers.
955 * \c emit_fsign only examines the source modifiers of the source of the
958 * The nir_op_fsign must also not have the saturate modifier, but steps
959 * have already been taken (in nir_opt_algebraic) to ensure that.
961 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
962 is_used_once(fsign_instr
) &&
963 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
967 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
969 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
973 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, true);
981 fs_reg temp
= result
;
982 bool need_extra_copy
= false;
983 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
984 if (!instr
->src
[i
].src
.is_ssa
&&
985 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
986 need_extra_copy
= true;
987 temp
= bld
.vgrf(result
.type
, 4);
992 for (unsigned i
= 0; i
< 4; i
++) {
993 if (!(instr
->dest
.write_mask
& (1 << i
)))
996 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
997 inst
= bld
.MOV(offset(temp
, bld
, i
),
998 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1000 inst
= bld
.MOV(offset(temp
, bld
, i
),
1001 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1003 inst
->saturate
= instr
->dest
.saturate
;
1006 /* In this case the source and destination registers were the same,
1007 * so we need to insert an extra set of moves in order to deal with
1010 if (need_extra_copy
) {
1011 for (unsigned i
= 0; i
< 4; i
++) {
1012 if (!(instr
->dest
.write_mask
& (1 << i
)))
1015 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1023 if (optimize_extract_to_float(instr
, result
))
1025 inst
= bld
.MOV(result
, op
[0]);
1026 inst
->saturate
= instr
->dest
.saturate
;
1029 case nir_op_f2f16_rtne
:
1030 case nir_op_f2f16_rtz
:
1031 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1032 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
1035 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1036 * on the HW gen, it is a special hw opcode or just a MOV, and
1037 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1039 * But if we want to use that opcode, we need to provide support on
1040 * different optimizations and lowerings. As right now HF support is
1041 * only for gen8+, it will be better to use directly the MOV, and use
1042 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1044 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1045 inst
= bld
.MOV(result
, op
[0]);
1046 inst
->saturate
= instr
->dest
.saturate
;
1056 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1058 op
[0].type
= BRW_REGISTER_TYPE_D
;
1059 op
[0].negate
= !op
[0].negate
;
1083 if (result
.type
== BRW_REGISTER_TYPE_B
||
1084 result
.type
== BRW_REGISTER_TYPE_UB
||
1085 result
.type
== BRW_REGISTER_TYPE_HF
)
1086 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1088 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1089 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1090 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1091 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1093 inst
= bld
.MOV(result
, op
[0]);
1094 inst
->saturate
= instr
->dest
.saturate
;
1098 emit_fsign(bld
, instr
, result
, op
, 0);
1102 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1103 inst
->saturate
= instr
->dest
.saturate
;
1107 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1108 inst
->saturate
= instr
->dest
.saturate
;
1112 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1113 inst
->saturate
= instr
->dest
.saturate
;
1117 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1118 inst
->saturate
= instr
->dest
.saturate
;
1122 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1123 inst
->saturate
= instr
->dest
.saturate
;
1127 if (fs_key
->high_quality_derivatives
) {
1128 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1130 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1132 inst
->saturate
= instr
->dest
.saturate
;
1134 case nir_op_fddx_fine
:
1135 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1136 inst
->saturate
= instr
->dest
.saturate
;
1138 case nir_op_fddx_coarse
:
1139 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1140 inst
->saturate
= instr
->dest
.saturate
;
1143 if (fs_key
->high_quality_derivatives
) {
1144 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1146 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1148 inst
->saturate
= instr
->dest
.saturate
;
1150 case nir_op_fddy_fine
:
1151 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1152 inst
->saturate
= instr
->dest
.saturate
;
1154 case nir_op_fddy_coarse
:
1155 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1156 inst
->saturate
= instr
->dest
.saturate
;
1161 inst
= bld
.ADD(result
, op
[0], op
[1]);
1162 inst
->saturate
= instr
->dest
.saturate
;
1165 case nir_op_uadd_sat
:
1166 inst
= bld
.ADD(result
, op
[0], op
[1]);
1167 inst
->saturate
= true;
1171 for (unsigned i
= 0; i
< 2; i
++) {
1172 if (can_fuse_fmul_fsign(instr
, i
)) {
1173 emit_fsign(bld
, instr
, result
, op
, i
);
1178 inst
= bld
.MUL(result
, op
[0], op
[1]);
1179 inst
->saturate
= instr
->dest
.saturate
;
1182 case nir_op_imul_2x32_64
:
1183 case nir_op_umul_2x32_64
:
1184 bld
.MUL(result
, op
[0], op
[1]);
1188 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1189 bld
.MUL(result
, op
[0], op
[1]);
1192 case nir_op_imul_high
:
1193 case nir_op_umul_high
:
1194 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1195 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1200 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1201 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1204 case nir_op_uadd_carry
:
1205 unreachable("Should have been lowered by carry_to_arith().");
1207 case nir_op_usub_borrow
:
1208 unreachable("Should have been lowered by borrow_to_arith().");
1212 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1213 * appears that our hardware just does the right thing for signed
1216 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1217 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1221 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1222 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1224 /* Math instructions don't support conditional mod */
1225 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1226 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1228 /* Now, we need to determine if signs of the sources are different.
1229 * When we XOR the sources, the top bit is 0 if they are the same and 1
1230 * if they are different. We can then use a conditional modifier to
1231 * turn that into a predicate. This leads us to an XOR.l instruction.
1233 * Technically, according to the PRM, you're not allowed to use .l on a
1234 * XOR instruction. However, emperical experiments and Curro's reading
1235 * of the simulator source both indicate that it's safe.
1237 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1238 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1239 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1240 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1242 /* If the result of the initial remainder operation is non-zero and the
1243 * two sources have different signs, add in a copy of op[1] to get the
1244 * final integer modulus value.
1246 inst
= bld
.ADD(result
, result
, op
[1]);
1247 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1254 case nir_op_fne32
: {
1255 fs_reg dest
= result
;
1257 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1259 dest
= bld
.vgrf(op
[0].type
, 1);
1261 brw_conditional_mod cond
;
1262 switch (instr
->op
) {
1264 cond
= BRW_CONDITIONAL_L
;
1267 cond
= BRW_CONDITIONAL_GE
;
1270 cond
= BRW_CONDITIONAL_Z
;
1273 cond
= BRW_CONDITIONAL_NZ
;
1276 unreachable("bad opcode");
1279 bld
.CMP(dest
, op
[0], op
[1], cond
);
1281 if (bit_size
> 32) {
1282 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1283 } else if(bit_size
< 32) {
1284 /* When we convert the result to 32-bit we need to be careful and do
1285 * it as a signed conversion to get sign extension (for 32-bit true)
1287 const brw_reg_type src_type
=
1288 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1290 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1300 case nir_op_ine32
: {
1301 fs_reg dest
= result
;
1303 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1305 dest
= bld
.vgrf(op
[0].type
, 1);
1307 brw_conditional_mod cond
;
1308 switch (instr
->op
) {
1311 cond
= BRW_CONDITIONAL_L
;
1315 cond
= BRW_CONDITIONAL_GE
;
1318 cond
= BRW_CONDITIONAL_Z
;
1321 cond
= BRW_CONDITIONAL_NZ
;
1324 unreachable("bad opcode");
1326 bld
.CMP(dest
, op
[0], op
[1], cond
);
1328 if (bit_size
> 32) {
1329 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1330 } else if (bit_size
< 32) {
1331 /* When we convert the result to 32-bit we need to be careful and do
1332 * it as a signed conversion to get sign extension (for 32-bit true)
1334 const brw_reg_type src_type
=
1335 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1337 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1343 if (devinfo
->gen
>= 8) {
1344 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1346 if (inot_src_instr
!= NULL
&&
1347 (inot_src_instr
->op
== nir_op_ior
||
1348 inot_src_instr
->op
== nir_op_ixor
||
1349 inot_src_instr
->op
== nir_op_iand
) &&
1350 !inot_src_instr
->src
[0].abs
&&
1351 !inot_src_instr
->src
[0].negate
&&
1352 !inot_src_instr
->src
[1].abs
&&
1353 !inot_src_instr
->src
[1].negate
) {
1354 /* The sources of the source logical instruction are now the
1355 * sources of the instruction that will be generated.
1357 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1358 resolve_inot_sources(bld
, inot_src_instr
, op
);
1360 /* Smash all of the sources and destination to be signed. This
1361 * doesn't matter for the operation of the instruction, but cmod
1362 * propagation fails on unsigned sources with negation (due to
1363 * fs_inst::can_do_cmod returning false).
1366 brw_type_for_nir_type(devinfo
,
1367 (nir_alu_type
)(nir_type_int
|
1368 nir_dest_bit_size(instr
->dest
.dest
)));
1370 brw_type_for_nir_type(devinfo
,
1371 (nir_alu_type
)(nir_type_int
|
1372 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1374 brw_type_for_nir_type(devinfo
,
1375 (nir_alu_type
)(nir_type_int
|
1376 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1378 /* For XOR, only invert one of the sources. Arbitrarily choose
1381 op
[0].negate
= !op
[0].negate
;
1382 if (inot_src_instr
->op
!= nir_op_ixor
)
1383 op
[1].negate
= !op
[1].negate
;
1385 switch (inot_src_instr
->op
) {
1387 bld
.AND(result
, op
[0], op
[1]);
1391 bld
.OR(result
, op
[0], op
[1]);
1395 bld
.XOR(result
, op
[0], op
[1]);
1399 unreachable("impossible opcode");
1402 op
[0] = resolve_source_modifiers(op
[0]);
1404 bld
.NOT(result
, op
[0]);
1407 if (devinfo
->gen
>= 8) {
1408 resolve_inot_sources(bld
, instr
, op
);
1410 bld
.XOR(result
, op
[0], op
[1]);
1413 if (devinfo
->gen
>= 8) {
1414 resolve_inot_sources(bld
, instr
, op
);
1416 bld
.OR(result
, op
[0], op
[1]);
1419 if (devinfo
->gen
>= 8) {
1420 resolve_inot_sources(bld
, instr
, op
);
1422 bld
.AND(result
, op
[0], op
[1]);
1428 case nir_op_b32all_fequal2
:
1429 case nir_op_b32all_iequal2
:
1430 case nir_op_b32all_fequal3
:
1431 case nir_op_b32all_iequal3
:
1432 case nir_op_b32all_fequal4
:
1433 case nir_op_b32all_iequal4
:
1434 case nir_op_b32any_fnequal2
:
1435 case nir_op_b32any_inequal2
:
1436 case nir_op_b32any_fnequal3
:
1437 case nir_op_b32any_inequal3
:
1438 case nir_op_b32any_fnequal4
:
1439 case nir_op_b32any_inequal4
:
1440 unreachable("Lowered by nir_lower_alu_reductions");
1442 case nir_op_fnoise1_1
:
1443 case nir_op_fnoise1_2
:
1444 case nir_op_fnoise1_3
:
1445 case nir_op_fnoise1_4
:
1446 case nir_op_fnoise2_1
:
1447 case nir_op_fnoise2_2
:
1448 case nir_op_fnoise2_3
:
1449 case nir_op_fnoise2_4
:
1450 case nir_op_fnoise3_1
:
1451 case nir_op_fnoise3_2
:
1452 case nir_op_fnoise3_3
:
1453 case nir_op_fnoise3_4
:
1454 case nir_op_fnoise4_1
:
1455 case nir_op_fnoise4_2
:
1456 case nir_op_fnoise4_3
:
1457 case nir_op_fnoise4_4
:
1458 unreachable("not reached: should be handled by lower_noise");
1461 unreachable("not reached: should be handled by ldexp_to_arith()");
1464 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1465 inst
->saturate
= instr
->dest
.saturate
;
1469 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1470 inst
->saturate
= instr
->dest
.saturate
;
1474 case nir_op_f2b32
: {
1475 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1476 if (bit_size
== 64) {
1477 /* two-argument instructions can't take 64-bit immediates */
1481 if (instr
->op
== nir_op_f2b32
) {
1482 zero
= vgrf(glsl_type::double_type
);
1483 tmp
= vgrf(glsl_type::double_type
);
1484 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1486 zero
= vgrf(glsl_type::int64_t_type
);
1487 tmp
= vgrf(glsl_type::int64_t_type
);
1488 bld
.MOV(zero
, brw_imm_q(0));
1491 /* A SIMD16 execution needs to be split in two instructions, so use
1492 * a vgrf instead of the flag register as dst so instruction splitting
1495 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1496 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1499 if (bit_size
== 32) {
1500 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1502 assert(bit_size
== 16);
1503 zero
= instr
->op
== nir_op_f2b32
?
1504 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1506 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1512 inst
= bld
.RNDZ(result
, op
[0]);
1513 inst
->saturate
= instr
->dest
.saturate
;
1516 case nir_op_fceil
: {
1517 op
[0].negate
= !op
[0].negate
;
1518 fs_reg temp
= vgrf(glsl_type::float_type
);
1519 bld
.RNDD(temp
, op
[0]);
1521 inst
= bld
.MOV(result
, temp
);
1522 inst
->saturate
= instr
->dest
.saturate
;
1526 inst
= bld
.RNDD(result
, op
[0]);
1527 inst
->saturate
= instr
->dest
.saturate
;
1530 inst
= bld
.FRC(result
, op
[0]);
1531 inst
->saturate
= instr
->dest
.saturate
;
1533 case nir_op_fround_even
:
1534 inst
= bld
.RNDE(result
, op
[0]);
1535 inst
->saturate
= instr
->dest
.saturate
;
1538 case nir_op_fquantize2f16
: {
1539 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1540 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1541 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1543 /* The destination stride must be at least as big as the source stride. */
1544 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1547 /* Check for denormal */
1548 fs_reg abs_src0
= op
[0];
1549 abs_src0
.abs
= true;
1550 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1552 /* Get the appropriately signed zero */
1553 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1554 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1555 brw_imm_ud(0x80000000));
1556 /* Do the actual F32 -> F16 -> F32 conversion */
1557 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1558 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1559 /* Select that or zero based on normal status */
1560 inst
= bld
.SEL(result
, zero
, tmp32
);
1561 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1562 inst
->saturate
= instr
->dest
.saturate
;
1569 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1570 inst
->saturate
= instr
->dest
.saturate
;
1576 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1577 inst
->saturate
= instr
->dest
.saturate
;
1580 case nir_op_pack_snorm_2x16
:
1581 case nir_op_pack_snorm_4x8
:
1582 case nir_op_pack_unorm_2x16
:
1583 case nir_op_pack_unorm_4x8
:
1584 case nir_op_unpack_snorm_2x16
:
1585 case nir_op_unpack_snorm_4x8
:
1586 case nir_op_unpack_unorm_2x16
:
1587 case nir_op_unpack_unorm_4x8
:
1588 case nir_op_unpack_half_2x16
:
1589 case nir_op_pack_half_2x16
:
1590 unreachable("not reached: should be handled by lower_packing_builtins");
1592 case nir_op_unpack_half_2x16_split_x
:
1593 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1594 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1595 inst
->saturate
= instr
->dest
.saturate
;
1597 case nir_op_unpack_half_2x16_split_y
:
1598 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1599 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1600 inst
->saturate
= instr
->dest
.saturate
;
1603 case nir_op_pack_64_2x32_split
:
1604 case nir_op_pack_32_2x16_split
:
1605 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1608 case nir_op_unpack_64_2x32_split_x
:
1609 case nir_op_unpack_64_2x32_split_y
: {
1610 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1611 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1613 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1617 case nir_op_unpack_32_2x16_split_x
:
1618 case nir_op_unpack_32_2x16_split_y
: {
1619 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1620 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1622 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1627 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1628 inst
->saturate
= instr
->dest
.saturate
;
1631 case nir_op_bitfield_reverse
:
1632 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1633 bld
.BFREV(result
, op
[0]);
1636 case nir_op_bit_count
:
1637 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1638 bld
.CBIT(result
, op
[0]);
1641 case nir_op_ufind_msb
: {
1642 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1643 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1647 case nir_op_ifind_msb
: {
1648 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1650 if (devinfo
->gen
< 7) {
1651 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1653 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1655 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1656 * count from the LSB side. If FBH didn't return an error
1657 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1658 * count into an LSB count.
1660 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1662 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1663 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1664 inst
->src
[0].negate
= true;
1669 case nir_op_find_lsb
:
1670 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1672 if (devinfo
->gen
< 7) {
1673 fs_reg temp
= vgrf(glsl_type::int_type
);
1675 /* (x & -x) generates a value that consists of only the LSB of x.
1676 * For all powers of 2, findMSB(y) == findLSB(y).
1678 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1679 fs_reg negated_src
= src
;
1681 /* One must be negated, and the other must be non-negated. It
1682 * doesn't matter which is which.
1684 negated_src
.negate
= true;
1687 bld
.AND(temp
, src
, negated_src
);
1688 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1690 bld
.FBL(result
, op
[0]);
1694 case nir_op_ubitfield_extract
:
1695 case nir_op_ibitfield_extract
:
1696 unreachable("should have been lowered");
1699 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1700 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1703 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1704 bld
.BFI1(result
, op
[0], op
[1]);
1707 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1708 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1711 case nir_op_bitfield_insert
:
1712 unreachable("not reached: should have been lowered");
1715 bld
.SHL(result
, op
[0], op
[1]);
1718 bld
.ASR(result
, op
[0], op
[1]);
1721 bld
.SHR(result
, op
[0], op
[1]);
1724 case nir_op_pack_half_2x16_split
:
1725 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1729 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1730 inst
->saturate
= instr
->dest
.saturate
;
1734 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1735 inst
->saturate
= instr
->dest
.saturate
;
1738 case nir_op_b32csel
:
1739 if (optimize_frontfacing_ternary(instr
, result
))
1742 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1743 inst
= bld
.SEL(result
, op
[1], op
[2]);
1744 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1747 case nir_op_extract_u8
:
1748 case nir_op_extract_i8
: {
1749 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1754 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1755 * Use two instructions and a word or DWord intermediate integer type.
1757 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1758 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1760 if (instr
->op
== nir_op_extract_i8
) {
1761 /* If we need to sign extend, extract to a word first */
1762 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1763 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1764 bld
.MOV(result
, w_temp
);
1765 } else if (byte
& 1) {
1766 /* Extract the high byte from the word containing the desired byte
1770 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1773 /* Otherwise use an AND with 0xff and a word type */
1775 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1779 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1780 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1785 case nir_op_extract_u16
:
1786 case nir_op_extract_i16
: {
1787 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1788 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1789 bld
.MOV(result
, subscript(op
[0], type
, word
));
1794 unreachable("unhandled instruction");
1797 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1798 * to sign extend the low bit to 0/~0
1800 if (devinfo
->gen
<= 5 &&
1801 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1802 fs_reg masked
= vgrf(glsl_type::int_type
);
1803 bld
.AND(masked
, result
, brw_imm_d(1));
1804 masked
.negate
= true;
1805 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1810 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1811 nir_load_const_instr
*instr
)
1813 const brw_reg_type reg_type
=
1814 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1815 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1817 switch (instr
->def
.bit_size
) {
1819 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1820 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1824 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1825 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1829 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1830 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1834 assert(devinfo
->gen
>= 7);
1835 if (devinfo
->gen
== 7) {
1836 /* We don't get 64-bit integer types until gen8 */
1837 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1838 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1839 setup_imm_df(bld
, instr
->value
[i
].f64
));
1842 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1843 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1848 unreachable("Invalid bit size");
1851 nir_ssa_values
[instr
->def
.index
] = reg
;
1855 fs_visitor::get_nir_src(const nir_src
&src
)
1859 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1860 const brw_reg_type reg_type
=
1861 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1862 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1864 reg
= nir_ssa_values
[src
.ssa
->index
];
1867 /* We don't handle indirects on locals */
1868 assert(src
.reg
.indirect
== NULL
);
1869 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1870 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1873 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1874 /* The only 64-bit type available on gen7 is DF, so use that. */
1875 reg
.type
= BRW_REGISTER_TYPE_DF
;
1877 /* To avoid floating-point denorm flushing problems, set the type by
1878 * default to an integer type - instructions that need floating point
1879 * semantics will set this to F if they need to
1881 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1882 BRW_REGISTER_TYPE_D
);
1889 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1891 * This function should not be called on any value which may be 64 bits.
1892 * We could theoretically support 64-bit on gen8+ but we choose not to
1893 * because it wouldn't work in general (no gen7 support) and there are
1894 * enough restrictions in 64-bit immediates that you can't take the return
1895 * value and treat it the same as the result of get_nir_src().
1898 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1900 assert(nir_src_bit_size(src
) == 32);
1901 return nir_src_is_const(src
) ?
1902 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1906 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1909 const brw_reg_type reg_type
=
1910 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1911 dest
.ssa
.bit_size
== 8 ?
1912 BRW_REGISTER_TYPE_D
:
1913 BRW_REGISTER_TYPE_F
);
1914 nir_ssa_values
[dest
.ssa
.index
] =
1915 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1916 return nir_ssa_values
[dest
.ssa
.index
];
1918 /* We don't handle indirects on locals */
1919 assert(dest
.reg
.indirect
== NULL
);
1920 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1921 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1926 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1929 for (unsigned i
= 0; i
< 4; i
++) {
1930 if (!((wr_mask
>> i
) & 1))
1933 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1934 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1935 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1936 if (new_inst
->src
[j
].file
== VGRF
)
1937 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1944 emit_pixel_interpolater_send(const fs_builder
&bld
,
1949 glsl_interp_mode interpolation
)
1951 struct brw_wm_prog_data
*wm_prog_data
=
1952 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1954 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1955 /* 2 floats per slot returned */
1956 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1957 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1959 wm_prog_data
->pulls_bary
= true;
1965 * Computes 1 << x, given a D/UD register containing some value x.
1968 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1970 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1972 fs_reg result
= bld
.vgrf(x
.type
, 1);
1973 fs_reg one
= bld
.vgrf(x
.type
, 1);
1975 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1976 bld
.SHL(result
, one
, x
);
1981 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1983 assert(stage
== MESA_SHADER_GEOMETRY
);
1985 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1987 if (gs_compile
->control_data_header_size_bits
== 0)
1990 /* We can only do EndPrimitive() functionality when the control data
1991 * consists of cut bits. Fortunately, the only time it isn't is when the
1992 * output type is points, in which case EndPrimitive() is a no-op.
1994 if (gs_prog_data
->control_data_format
!=
1995 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1999 /* Cut bits use one bit per vertex. */
2000 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2002 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2003 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2005 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2006 * vertex n, 0 otherwise. So all we need to do here is mark bit
2007 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2008 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2009 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2011 * Note that if EndPrimitive() is called before emitting any vertices, this
2012 * will cause us to set bit 31 of the control_data_bits register to 1.
2013 * That's fine because:
2015 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2016 * output, so the hardware will ignore cut bit 31.
2018 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2019 * last vertex, so setting cut bit 31 has no effect (since the primitive
2020 * is automatically ended when the GS terminates).
2022 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2023 * control_data_bits register to 0 when the first vertex is emitted.
2026 const fs_builder abld
= bld
.annotate("end primitive");
2028 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2029 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2030 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2031 fs_reg mask
= intexp2(abld
, prev_count
);
2032 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2033 * attention to the lower 5 bits of its second source argument, so on this
2034 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2035 * ((vertex_count - 1) % 32).
2037 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2041 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2043 assert(stage
== MESA_SHADER_GEOMETRY
);
2044 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2046 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2048 const fs_builder abld
= bld
.annotate("emit control data bits");
2049 const fs_builder fwa_bld
= bld
.exec_all();
2051 /* We use a single UD register to accumulate control data bits (32 bits
2052 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2055 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2056 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2057 * use the Channel Mask phase to enable/disable which DWord within that
2058 * group to write. (Remember, different SIMD8 channels may have emitted
2059 * different numbers of vertices, so we may need per-slot offsets.)
2061 * Channel masking presents an annoying problem: we may have to replicate
2062 * the data up to 4 times:
2064 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2066 * To avoid penalizing shaders that emit a small number of vertices, we
2067 * can avoid these sometimes: if the size of the control data header is
2068 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2069 * land in the same 128-bit group, so we can skip per-slot offsets.
2071 * Similarly, if the control data header is <= 32 bits, there is only one
2072 * DWord, so we can skip channel masks.
2074 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2076 fs_reg channel_mask
, per_slot_offset
;
2078 if (gs_compile
->control_data_header_size_bits
> 32) {
2079 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2080 channel_mask
= vgrf(glsl_type::uint_type
);
2083 if (gs_compile
->control_data_header_size_bits
> 128) {
2084 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2085 per_slot_offset
= vgrf(glsl_type::uint_type
);
2088 /* Figure out which DWord we're trying to write to using the formula:
2090 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2092 * Since bits_per_vertex is a power of two, and is known at compile
2093 * time, this can be optimized to:
2095 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2097 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2098 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2099 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2100 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2101 unsigned log2_bits_per_vertex
=
2102 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2103 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2105 if (per_slot_offset
.file
!= BAD_FILE
) {
2106 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2107 * the appropriate OWord within the control data header.
2109 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2112 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2113 * write to the appropriate DWORD within the OWORD.
2115 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2116 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2117 channel_mask
= intexp2(fwa_bld
, channel
);
2118 /* Then the channel masks need to be in bits 23:16. */
2119 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2122 /* Store the control data bits in the message payload and send it. */
2124 if (channel_mask
.file
!= BAD_FILE
)
2125 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2126 if (per_slot_offset
.file
!= BAD_FILE
)
2129 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2130 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2132 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2133 if (per_slot_offset
.file
!= BAD_FILE
)
2134 sources
[i
++] = per_slot_offset
;
2135 if (channel_mask
.file
!= BAD_FILE
)
2136 sources
[i
++] = channel_mask
;
2138 sources
[i
++] = this->control_data_bits
;
2141 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2142 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2144 /* We need to increment Global Offset by 256-bits to make room for
2145 * Broadwell's extra "Vertex Count" payload at the beginning of the
2146 * URB entry. Since this is an OWord message, Global Offset is counted
2147 * in 128-bit units, so we must set it to 2.
2149 if (gs_prog_data
->static_vertex_count
== -1)
2154 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2157 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2159 /* Note: we are calling this *before* increasing vertex_count, so
2160 * this->vertex_count == vertex_count - 1 in the formula above.
2163 /* Stream mode uses 2 bits per vertex */
2164 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2166 /* Must be a valid stream */
2167 assert(stream_id
< MAX_VERTEX_STREAMS
);
2169 /* Control data bits are initialized to 0 so we don't have to set any
2170 * bits when sending vertices to stream 0.
2175 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2177 /* reg::sid = stream_id */
2178 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2179 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2181 /* reg:shift_count = 2 * (vertex_count - 1) */
2182 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2183 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2185 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2186 * attention to the lower 5 bits of its second source argument, so on this
2187 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2188 * stream_id << ((2 * (vertex_count - 1)) % 32).
2190 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2191 abld
.SHL(mask
, sid
, shift_count
);
2192 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2196 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2199 assert(stage
== MESA_SHADER_GEOMETRY
);
2201 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2203 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2204 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2206 /* Haswell and later hardware ignores the "Render Stream Select" bits
2207 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2208 * and instead sends all primitives down the pipeline for rasterization.
2209 * If the SOL stage is enabled, "Render Stream Select" is honored and
2210 * primitives bound to non-zero streams are discarded after stream output.
2212 * Since the only purpose of primives sent to non-zero streams is to
2213 * be recorded by transform feedback, we can simply discard all geometry
2214 * bound to these streams when transform feedback is disabled.
2216 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2219 /* If we're outputting 32 control data bits or less, then we can wait
2220 * until the shader is over to output them all. Otherwise we need to
2221 * output them as we go. Now is the time to do it, since we're about to
2222 * output the vertex_count'th vertex, so it's guaranteed that the
2223 * control data bits associated with the (vertex_count - 1)th vertex are
2226 if (gs_compile
->control_data_header_size_bits
> 32) {
2227 const fs_builder abld
=
2228 bld
.annotate("emit vertex: emit control data bits");
2230 /* Only emit control data bits if we've finished accumulating a batch
2231 * of 32 bits. This is the case when:
2233 * (vertex_count * bits_per_vertex) % 32 == 0
2235 * (in other words, when the last 5 bits of vertex_count *
2236 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2237 * integer n (which is always the case, since bits_per_vertex is
2238 * always 1 or 2), this is equivalent to requiring that the last 5-n
2239 * bits of vertex_count are 0:
2241 * vertex_count & (2^(5-n) - 1) == 0
2243 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2246 * vertex_count & (32 / bits_per_vertex - 1) == 0
2248 * TODO: If vertex_count is an immediate, we could do some of this math
2249 * at compile time...
2252 abld
.AND(bld
.null_reg_d(), vertex_count
,
2253 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2254 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2256 abld
.IF(BRW_PREDICATE_NORMAL
);
2257 /* If vertex_count is 0, then no control data bits have been
2258 * accumulated yet, so we can skip emitting them.
2260 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2261 BRW_CONDITIONAL_NEQ
);
2262 abld
.IF(BRW_PREDICATE_NORMAL
);
2263 emit_gs_control_data_bits(vertex_count
);
2264 abld
.emit(BRW_OPCODE_ENDIF
);
2266 /* Reset control_data_bits to 0 so we can start accumulating a new
2269 * Note: in the case where vertex_count == 0, this neutralizes the
2270 * effect of any call to EndPrimitive() that the shader may have
2271 * made before outputting its first vertex.
2273 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2274 inst
->force_writemask_all
= true;
2275 abld
.emit(BRW_OPCODE_ENDIF
);
2278 emit_urb_writes(vertex_count
);
2280 /* In stream mode we have to set control data bits for all vertices
2281 * unless we have disabled control data bits completely (which we do
2282 * do for GL_POINTS outputs that don't use streams).
2284 if (gs_compile
->control_data_header_size_bits
> 0 &&
2285 gs_prog_data
->control_data_format
==
2286 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2287 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2292 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2293 const nir_src
&vertex_src
,
2294 unsigned base_offset
,
2295 const nir_src
&offset_src
,
2296 unsigned num_components
,
2297 unsigned first_component
)
2299 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2300 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2302 /* TODO: figure out push input layout for invocations == 1 */
2303 /* TODO: make this work with 64-bit inputs */
2304 if (gs_prog_data
->invocations
== 1 &&
2305 type_sz(dst
.type
) <= 4 &&
2306 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2307 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2308 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2309 nir_src_as_uint(vertex_src
) * push_reg_count
;
2310 for (unsigned i
= 0; i
< num_components
; i
++) {
2311 bld
.MOV(offset(dst
, bld
, i
),
2312 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2317 /* Resort to the pull model. Ensure the VUE handles are provided. */
2318 assert(gs_prog_data
->base
.include_vue_handles
);
2320 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2321 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2323 if (gs_prog_data
->invocations
== 1) {
2324 if (nir_src_is_const(vertex_src
)) {
2325 /* The vertex index is constant; just select the proper URB handle. */
2327 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2328 BRW_REGISTER_TYPE_UD
);
2330 /* The vertex index is non-constant. We need to use indirect
2331 * addressing to fetch the proper URB handle.
2333 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2334 * indicating that channel <n> should read the handle from
2335 * DWord <n>. We convert that to bytes by multiplying by 4.
2337 * Next, we convert the vertex index to bytes by multiplying
2338 * by 32 (shifting by 5), and add the two together. This is
2339 * the final indirect byte offset.
2341 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2342 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2343 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2344 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2346 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2347 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2348 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2349 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2350 /* Convert vertex_index to bytes (multiply by 32) */
2351 bld
.SHL(vertex_offset_bytes
,
2352 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2354 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2356 /* Use first_icp_handle as the base offset. There is one register
2357 * of URB handles per vertex, so inform the register allocator that
2358 * we might read up to nir->info.gs.vertices_in registers.
2360 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2361 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2362 fs_reg(icp_offset_bytes
),
2363 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2366 assert(gs_prog_data
->invocations
> 1);
2368 if (nir_src_is_const(vertex_src
)) {
2369 unsigned vertex
= nir_src_as_uint(vertex_src
);
2370 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2372 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2373 BRW_REGISTER_TYPE_UD
));
2375 /* The vertex index is non-constant. We need to use indirect
2376 * addressing to fetch the proper URB handle.
2379 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2381 /* Convert vertex_index to bytes (multiply by 4) */
2382 bld
.SHL(icp_offset_bytes
,
2383 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2386 /* Use first_icp_handle as the base offset. There is one DWord
2387 * of URB handles per vertex, so inform the register allocator that
2388 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2390 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2391 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2392 fs_reg(icp_offset_bytes
),
2393 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2400 fs_reg tmp_dst
= dst
;
2401 fs_reg indirect_offset
= get_nir_src(offset_src
);
2402 unsigned num_iterations
= 1;
2403 unsigned orig_num_components
= num_components
;
2405 if (type_sz(dst
.type
) == 8) {
2406 if (num_components
> 2) {
2410 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2412 first_component
= first_component
/ 2;
2415 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2416 if (nir_src_is_const(offset_src
)) {
2417 /* Constant indexing - use global offset. */
2418 if (first_component
!= 0) {
2419 unsigned read_components
= num_components
+ first_component
;
2420 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2421 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2422 inst
->size_written
= read_components
*
2423 tmp
.component_size(inst
->exec_size
);
2424 for (unsigned i
= 0; i
< num_components
; i
++) {
2425 bld
.MOV(offset(tmp_dst
, bld
, i
),
2426 offset(tmp
, bld
, i
+ first_component
));
2429 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2431 inst
->size_written
= num_components
*
2432 tmp_dst
.component_size(inst
->exec_size
);
2434 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2437 /* Indirect indexing - use per-slot offsets as well. */
2438 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2439 unsigned read_components
= num_components
+ first_component
;
2440 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2441 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2442 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2443 if (first_component
!= 0) {
2444 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2446 inst
->size_written
= read_components
*
2447 tmp
.component_size(inst
->exec_size
);
2448 for (unsigned i
= 0; i
< num_components
; i
++) {
2449 bld
.MOV(offset(tmp_dst
, bld
, i
),
2450 offset(tmp
, bld
, i
+ first_component
));
2453 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2455 inst
->size_written
= num_components
*
2456 tmp_dst
.component_size(inst
->exec_size
);
2458 inst
->offset
= base_offset
;
2462 if (type_sz(dst
.type
) == 8) {
2463 shuffle_from_32bit_read(bld
,
2464 offset(dst
, bld
, iter
* 2),
2465 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2470 if (num_iterations
> 1) {
2471 num_components
= orig_num_components
- 2;
2472 if(nir_src_is_const(offset_src
)) {
2475 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2476 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2477 indirect_offset
= new_indirect
;
2484 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2486 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2488 if (nir_src_is_const(*offset_src
)) {
2489 /* The only constant offset we should find is 0. brw_nir.c's
2490 * add_const_offset_to_base() will fold other constant offsets
2491 * into instr->const_index[0].
2493 assert(nir_src_as_uint(*offset_src
) == 0);
2497 return get_nir_src(*offset_src
);
2501 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2502 nir_intrinsic_instr
*instr
)
2504 assert(stage
== MESA_SHADER_VERTEX
);
2507 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2508 dest
= get_nir_dest(instr
->dest
);
2510 switch (instr
->intrinsic
) {
2511 case nir_intrinsic_load_vertex_id
:
2512 case nir_intrinsic_load_base_vertex
:
2513 unreachable("should be lowered by nir_lower_system_values()");
2515 case nir_intrinsic_load_input
: {
2516 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2517 unsigned first_component
= nir_intrinsic_component(instr
);
2518 unsigned num_components
= instr
->num_components
;
2520 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2522 if (type_sz(dest
.type
) == 8)
2523 first_component
/= 2;
2525 /* For 16-bit support maybe a temporary will be needed to copy from
2528 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2529 first_component
, num_components
);
2533 case nir_intrinsic_load_vertex_id_zero_base
:
2534 case nir_intrinsic_load_instance_id
:
2535 case nir_intrinsic_load_base_instance
:
2536 case nir_intrinsic_load_draw_id
:
2537 case nir_intrinsic_load_first_vertex
:
2538 case nir_intrinsic_load_is_indexed_draw
:
2539 unreachable("lowered by brw_nir_lower_vs_inputs");
2542 nir_emit_intrinsic(bld
, instr
);
2548 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2549 nir_intrinsic_instr
*instr
)
2551 assert(stage
== MESA_SHADER_TESS_CTRL
);
2552 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2553 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2556 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2557 dst
= get_nir_dest(instr
->dest
);
2559 switch (instr
->intrinsic
) {
2560 case nir_intrinsic_load_primitive_id
:
2561 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2563 case nir_intrinsic_load_invocation_id
:
2564 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2566 case nir_intrinsic_load_patch_vertices_in
:
2567 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2568 brw_imm_d(tcs_key
->input_vertices
));
2571 case nir_intrinsic_barrier
: {
2572 if (tcs_prog_data
->instances
== 1)
2575 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2576 fs_reg m0_2
= component(m0
, 2);
2578 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2580 /* Zero the message header */
2581 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2583 if (devinfo
->gen
< 11) {
2584 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2585 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2586 brw_imm_ud(INTEL_MASK(16, 13)));
2588 /* Shift it up to bits 27:24. */
2589 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2591 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2592 brw_imm_ud(INTEL_MASK(30, 24)));
2595 /* Set the Barrier Count and the enable bit */
2596 if (devinfo
->gen
< 11) {
2597 chanbld
.OR(m0_2
, m0_2
,
2598 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2600 chanbld
.OR(m0_2
, m0_2
,
2601 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2604 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2608 case nir_intrinsic_load_input
:
2609 unreachable("nir_lower_io should never give us these.");
2612 case nir_intrinsic_load_per_vertex_input
: {
2613 fs_reg indirect_offset
= get_indirect_offset(instr
);
2614 unsigned imm_offset
= instr
->const_index
[0];
2616 const nir_src
&vertex_src
= instr
->src
[0];
2622 if (nir_src_is_const(vertex_src
)) {
2623 /* Emit a MOV to resolve <0,1,0> regioning. */
2624 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2625 unsigned vertex
= nir_src_as_uint(vertex_src
);
2627 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2628 BRW_REGISTER_TYPE_UD
));
2629 } else if (tcs_prog_data
->instances
== 1 &&
2630 nir_src_as_intrinsic(vertex_src
) != NULL
&&
2631 nir_src_as_intrinsic(vertex_src
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2632 /* For the common case of only 1 instance, an array index of
2633 * gl_InvocationID means reading g1. Skip all the indirect work.
2635 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2637 /* The vertex index is non-constant. We need to use indirect
2638 * addressing to fetch the proper URB handle.
2640 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2642 /* Each ICP handle is a single DWord (4 bytes) */
2643 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2644 bld
.SHL(vertex_offset_bytes
,
2645 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2648 /* Start at g1. We might read up to 4 registers. */
2649 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2650 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2651 brw_imm_ud(4 * REG_SIZE
));
2654 /* We can only read two double components with each URB read, so
2655 * we send two read messages in that case, each one loading up to
2656 * two double components.
2658 unsigned num_iterations
= 1;
2659 unsigned num_components
= instr
->num_components
;
2660 unsigned first_component
= nir_intrinsic_component(instr
);
2661 fs_reg orig_dst
= dst
;
2662 if (type_sz(dst
.type
) == 8) {
2663 first_component
= first_component
/ 2;
2664 if (instr
->num_components
> 2) {
2669 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2673 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2674 if (indirect_offset
.file
== BAD_FILE
) {
2675 /* Constant indexing - use global offset. */
2676 if (first_component
!= 0) {
2677 unsigned read_components
= num_components
+ first_component
;
2678 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2679 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2680 for (unsigned i
= 0; i
< num_components
; i
++) {
2681 bld
.MOV(offset(dst
, bld
, i
),
2682 offset(tmp
, bld
, i
+ first_component
));
2685 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2687 inst
->offset
= imm_offset
;
2690 /* Indirect indexing - use per-slot offsets as well. */
2691 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2692 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2693 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2694 if (first_component
!= 0) {
2695 unsigned read_components
= num_components
+ first_component
;
2696 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2697 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2699 for (unsigned i
= 0; i
< num_components
; i
++) {
2700 bld
.MOV(offset(dst
, bld
, i
),
2701 offset(tmp
, bld
, i
+ first_component
));
2704 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2707 inst
->offset
= imm_offset
;
2710 inst
->size_written
= (num_components
+ first_component
) *
2711 inst
->dst
.component_size(inst
->exec_size
);
2713 /* If we are reading 64-bit data using 32-bit read messages we need
2714 * build proper 64-bit data elements by shuffling the low and high
2715 * 32-bit components around like we do for other things like UBOs
2718 if (type_sz(dst
.type
) == 8) {
2719 shuffle_from_32bit_read(bld
,
2720 offset(orig_dst
, bld
, iter
* 2),
2721 retype(dst
, BRW_REGISTER_TYPE_D
),
2725 /* Copy the temporary to the destination to deal with writemasking.
2727 * Also attempt to deal with gl_PointSize being in the .w component.
2729 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2730 assert(type_sz(dst
.type
) < 8);
2731 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2732 inst
->size_written
= 4 * REG_SIZE
;
2733 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2736 /* If we are loading double data and we need a second read message
2737 * adjust the write offset
2739 if (num_iterations
> 1) {
2740 num_components
= instr
->num_components
- 2;
2747 case nir_intrinsic_load_output
:
2748 case nir_intrinsic_load_per_vertex_output
: {
2749 fs_reg indirect_offset
= get_indirect_offset(instr
);
2750 unsigned imm_offset
= instr
->const_index
[0];
2751 unsigned first_component
= nir_intrinsic_component(instr
);
2754 if (indirect_offset
.file
== BAD_FILE
) {
2755 /* Replicate the patch handle to all enabled channels */
2756 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2757 bld
.MOV(patch_handle
,
2758 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2761 if (first_component
!= 0) {
2762 unsigned read_components
=
2763 instr
->num_components
+ first_component
;
2764 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2765 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2767 inst
->size_written
= read_components
* REG_SIZE
;
2768 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2769 bld
.MOV(offset(dst
, bld
, i
),
2770 offset(tmp
, bld
, i
+ first_component
));
2773 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2775 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2777 inst
->offset
= imm_offset
;
2781 /* Indirect indexing - use per-slot offsets as well. */
2782 const fs_reg srcs
[] = {
2783 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2786 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2787 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2788 if (first_component
!= 0) {
2789 unsigned read_components
=
2790 instr
->num_components
+ first_component
;
2791 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2792 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2794 inst
->size_written
= read_components
* REG_SIZE
;
2795 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2796 bld
.MOV(offset(dst
, bld
, i
),
2797 offset(tmp
, bld
, i
+ first_component
));
2800 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2802 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2804 inst
->offset
= imm_offset
;
2810 case nir_intrinsic_store_output
:
2811 case nir_intrinsic_store_per_vertex_output
: {
2812 fs_reg value
= get_nir_src(instr
->src
[0]);
2813 bool is_64bit
= (instr
->src
[0].is_ssa
?
2814 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2815 fs_reg indirect_offset
= get_indirect_offset(instr
);
2816 unsigned imm_offset
= instr
->const_index
[0];
2817 unsigned mask
= instr
->const_index
[1];
2818 unsigned header_regs
= 0;
2820 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2822 if (indirect_offset
.file
!= BAD_FILE
) {
2823 srcs
[header_regs
++] = indirect_offset
;
2829 unsigned num_components
= util_last_bit(mask
);
2832 /* We can only pack two 64-bit components in a single message, so send
2833 * 2 messages if we have more components
2835 unsigned num_iterations
= 1;
2836 unsigned iter_components
= num_components
;
2837 unsigned first_component
= nir_intrinsic_component(instr
);
2839 first_component
= first_component
/ 2;
2840 if (instr
->num_components
> 2) {
2842 iter_components
= 2;
2846 mask
= mask
<< first_component
;
2848 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2849 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2850 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2851 opcode
= indirect_offset
.file
!= BAD_FILE
?
2852 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2853 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2854 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2855 /* Expand the 64-bit mask to 32-bit channels. We only handle
2856 * two channels in each iteration, so we only care about X/Y.
2858 unsigned mask32
= 0;
2859 if (mask
& WRITEMASK_X
)
2860 mask32
|= WRITEMASK_XY
;
2861 if (mask
& WRITEMASK_Y
)
2862 mask32
|= WRITEMASK_ZW
;
2864 /* If the mask does not include any of the channels X or Y there
2865 * is nothing to do in this iteration. Move on to the next couple
2866 * of 64-bit channels.
2874 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2875 opcode
= indirect_offset
.file
!= BAD_FILE
?
2876 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2877 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2879 opcode
= indirect_offset
.file
!= BAD_FILE
?
2880 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2881 SHADER_OPCODE_URB_WRITE_SIMD8
;
2884 for (unsigned i
= 0; i
< iter_components
; i
++) {
2885 if (!(mask
& (1 << (i
+ first_component
))))
2889 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2891 /* We need to shuffle the 64-bit data to match the layout
2892 * expected by our 32-bit URB write messages. We use a temporary
2895 unsigned channel
= iter
* 2 + i
;
2896 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2898 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2899 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2900 offset(dest
, bld
, 1);
2905 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2906 (is_64bit
? 2 * first_component
: first_component
);
2908 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2909 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2911 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2912 inst
->offset
= imm_offset
;
2915 /* If this is a 64-bit attribute, select the next two 64-bit channels
2916 * to be handled in the next iteration.
2927 nir_emit_intrinsic(bld
, instr
);
2933 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2934 nir_intrinsic_instr
*instr
)
2936 assert(stage
== MESA_SHADER_TESS_EVAL
);
2937 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2940 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2941 dest
= get_nir_dest(instr
->dest
);
2943 switch (instr
->intrinsic
) {
2944 case nir_intrinsic_load_primitive_id
:
2945 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2947 case nir_intrinsic_load_tess_coord
:
2948 /* gl_TessCoord is part of the payload in g1-3 */
2949 for (unsigned i
= 0; i
< 3; i
++) {
2950 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2954 case nir_intrinsic_load_input
:
2955 case nir_intrinsic_load_per_vertex_input
: {
2956 fs_reg indirect_offset
= get_indirect_offset(instr
);
2957 unsigned imm_offset
= instr
->const_index
[0];
2958 unsigned first_component
= nir_intrinsic_component(instr
);
2960 if (type_sz(dest
.type
) == 8) {
2961 first_component
= first_component
/ 2;
2965 if (indirect_offset
.file
== BAD_FILE
) {
2966 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2967 * which is 16 registers (since each holds 2 vec4 slots).
2969 unsigned slot_count
= 1;
2970 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2973 const unsigned max_push_slots
= 32;
2974 if (imm_offset
+ slot_count
<= max_push_slots
) {
2975 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2976 for (int i
= 0; i
< instr
->num_components
; i
++) {
2977 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2978 i
+ first_component
;
2979 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2982 tes_prog_data
->base
.urb_read_length
=
2983 MAX2(tes_prog_data
->base
.urb_read_length
,
2984 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2986 /* Replicate the patch handle to all enabled channels */
2987 const fs_reg srcs
[] = {
2988 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2990 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2991 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2993 if (first_component
!= 0) {
2994 unsigned read_components
=
2995 instr
->num_components
+ first_component
;
2996 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2997 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2999 inst
->size_written
= read_components
* REG_SIZE
;
3000 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3001 bld
.MOV(offset(dest
, bld
, i
),
3002 offset(tmp
, bld
, i
+ first_component
));
3005 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3007 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3010 inst
->offset
= imm_offset
;
3013 /* Indirect indexing - use per-slot offsets as well. */
3015 /* We can only read two double components with each URB read, so
3016 * we send two read messages in that case, each one loading up to
3017 * two double components.
3019 unsigned num_iterations
= 1;
3020 unsigned num_components
= instr
->num_components
;
3021 fs_reg orig_dest
= dest
;
3022 if (type_sz(dest
.type
) == 8) {
3023 if (instr
->num_components
> 2) {
3027 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3031 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3032 const fs_reg srcs
[] = {
3033 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3036 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3037 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3039 if (first_component
!= 0) {
3040 unsigned read_components
=
3041 num_components
+ first_component
;
3042 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3043 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3045 for (unsigned i
= 0; i
< num_components
; i
++) {
3046 bld
.MOV(offset(dest
, bld
, i
),
3047 offset(tmp
, bld
, i
+ first_component
));
3050 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3054 inst
->offset
= imm_offset
;
3055 inst
->size_written
= (num_components
+ first_component
) *
3056 inst
->dst
.component_size(inst
->exec_size
);
3058 /* If we are reading 64-bit data using 32-bit read messages we need
3059 * build proper 64-bit data elements by shuffling the low and high
3060 * 32-bit components around like we do for other things like UBOs
3063 if (type_sz(dest
.type
) == 8) {
3064 shuffle_from_32bit_read(bld
,
3065 offset(orig_dest
, bld
, iter
* 2),
3066 retype(dest
, BRW_REGISTER_TYPE_D
),
3070 /* If we are loading double data and we need a second read message
3073 if (num_iterations
> 1) {
3074 num_components
= instr
->num_components
- 2;
3082 nir_emit_intrinsic(bld
, instr
);
3088 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3089 nir_intrinsic_instr
*instr
)
3091 assert(stage
== MESA_SHADER_GEOMETRY
);
3092 fs_reg indirect_offset
;
3095 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3096 dest
= get_nir_dest(instr
->dest
);
3098 switch (instr
->intrinsic
) {
3099 case nir_intrinsic_load_primitive_id
:
3100 assert(stage
== MESA_SHADER_GEOMETRY
);
3101 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3102 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3103 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3106 case nir_intrinsic_load_input
:
3107 unreachable("load_input intrinsics are invalid for the GS stage");
3109 case nir_intrinsic_load_per_vertex_input
:
3110 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3111 instr
->src
[1], instr
->num_components
,
3112 nir_intrinsic_component(instr
));
3115 case nir_intrinsic_emit_vertex_with_counter
:
3116 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3119 case nir_intrinsic_end_primitive_with_counter
:
3120 emit_gs_end_primitive(instr
->src
[0]);
3123 case nir_intrinsic_set_vertex_count
:
3124 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3127 case nir_intrinsic_load_invocation_id
: {
3128 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3129 assert(val
.file
!= BAD_FILE
);
3130 dest
.type
= val
.type
;
3136 nir_emit_intrinsic(bld
, instr
);
3142 * Fetch the current render target layer index.
3145 fetch_render_target_array_index(const fs_builder
&bld
)
3147 if (bld
.shader
->devinfo
->gen
>= 6) {
3148 /* The render target array index is provided in the thread payload as
3149 * bits 26:16 of r0.0.
3151 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3152 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3156 /* Pre-SNB we only ever render into the first layer of the framebuffer
3157 * since layered rendering is not implemented.
3159 return brw_imm_ud(0);
3164 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3165 * framebuffer at the current fragment coordinates and sample index.
3168 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3171 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3173 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3174 const brw_wm_prog_key
*wm_key
=
3175 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3176 assert(!wm_key
->coherent_fb_fetch
);
3177 const struct brw_wm_prog_data
*wm_prog_data
=
3178 brw_wm_prog_data(stage_prog_data
);
3180 /* Calculate the surface index relative to the start of the texture binding
3181 * table block, since that's what the texturing messages expect.
3183 const unsigned surface
= target
+
3184 wm_prog_data
->binding_table
.render_target_read_start
-
3185 wm_prog_data
->base
.binding_table
.texture_start
;
3187 /* Calculate the fragment coordinates. */
3188 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3189 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3190 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3191 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3193 /* Calculate the sample index and MCS payload when multisampling. Luckily
3194 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3195 * shouldn't be necessary to recompile based on whether the framebuffer is
3198 if (wm_key
->multisample_fbo
&&
3199 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3200 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3202 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3203 const fs_reg mcs
= wm_key
->multisample_fbo
?
3204 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3206 /* Use either a normal or a CMS texel fetch message depending on whether
3207 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3208 * message just in case the framebuffer uses 16x multisampling, it should
3209 * be equivalent to the normal CMS fetch for lower multisampling modes.
3211 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3212 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3213 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3215 /* Emit the instruction. */
3216 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3217 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3218 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3219 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3220 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3221 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3222 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3223 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3224 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3226 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3227 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3233 * Actual coherent framebuffer read implemented using the native render target
3234 * read message. Requires SKL+.
3237 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3239 assert(bld
.shader
->devinfo
->gen
>= 9);
3240 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3241 inst
->target
= target
;
3242 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3248 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3250 if (n
&& regs
[0].file
!= BAD_FILE
) {
3254 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3256 for (unsigned i
= 0; i
< n
; i
++)
3264 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3266 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3267 const brw_wm_prog_key
*const key
=
3268 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3269 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3270 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3272 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3273 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3275 else if (l
== FRAG_RESULT_COLOR
)
3276 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3277 MAX2(key
->nr_color_regions
, 1));
3279 else if (l
== FRAG_RESULT_DEPTH
)
3280 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3282 else if (l
== FRAG_RESULT_STENCIL
)
3283 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3285 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3286 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3288 else if (l
>= FRAG_RESULT_DATA0
&&
3289 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3290 return alloc_temporary(v
->bld
, 4,
3291 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3294 unreachable("Invalid location");
3298 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3299 nir_intrinsic_instr
*instr
)
3301 assert(stage
== MESA_SHADER_FRAGMENT
);
3304 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3305 dest
= get_nir_dest(instr
->dest
);
3307 switch (instr
->intrinsic
) {
3308 case nir_intrinsic_load_front_face
:
3309 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3310 *emit_frontfacing_interpolation());
3313 case nir_intrinsic_load_sample_pos
: {
3314 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3315 assert(sample_pos
.file
!= BAD_FILE
);
3316 dest
.type
= sample_pos
.type
;
3317 bld
.MOV(dest
, sample_pos
);
3318 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3322 case nir_intrinsic_load_layer_id
:
3323 dest
.type
= BRW_REGISTER_TYPE_UD
;
3324 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3327 case nir_intrinsic_load_helper_invocation
:
3328 case nir_intrinsic_load_sample_mask_in
:
3329 case nir_intrinsic_load_sample_id
: {
3330 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3331 fs_reg val
= nir_system_values
[sv
];
3332 assert(val
.file
!= BAD_FILE
);
3333 dest
.type
= val
.type
;
3338 case nir_intrinsic_store_output
: {
3339 const fs_reg src
= get_nir_src(instr
->src
[0]);
3340 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3341 const unsigned location
= nir_intrinsic_base(instr
) +
3342 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3343 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3346 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3347 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3348 offset(src
, bld
, j
));
3353 case nir_intrinsic_load_output
: {
3354 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3355 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3356 assert(l
>= FRAG_RESULT_DATA0
);
3357 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3358 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3359 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3361 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3362 emit_coherent_fb_read(bld
, tmp
, target
);
3364 emit_non_coherent_fb_read(bld
, tmp
, target
);
3366 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3367 bld
.MOV(offset(dest
, bld
, j
),
3368 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3374 case nir_intrinsic_discard
:
3375 case nir_intrinsic_discard_if
: {
3376 /* We track our discarded pixels in f0.1. By predicating on it, we can
3377 * update just the flag bits that aren't yet discarded. If there's no
3378 * condition, we emit a CMP of g0 != g0, so all currently executing
3379 * channels will get turned off.
3382 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3383 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3384 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3386 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3387 BRW_REGISTER_TYPE_UW
));
3388 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3390 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3391 cmp
->flag_subreg
= 1;
3393 if (devinfo
->gen
>= 6) {
3394 emit_discard_jump();
3397 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3401 case nir_intrinsic_load_input
: {
3402 /* load_input is only used for flat inputs */
3403 unsigned base
= nir_intrinsic_base(instr
);
3404 unsigned comp
= nir_intrinsic_component(instr
);
3405 unsigned num_components
= instr
->num_components
;
3406 fs_reg orig_dest
= dest
;
3407 enum brw_reg_type type
= dest
.type
;
3409 /* Special case fields in the VUE header */
3410 if (base
== VARYING_SLOT_LAYER
)
3412 else if (base
== VARYING_SLOT_VIEWPORT
)
3415 if (nir_dest_bit_size(instr
->dest
) == 64) {
3416 /* const_index is in 32-bit type size units that could not be aligned
3417 * with DF. We need to read the double vector as if it was a float
3418 * vector of twice the number of components to fetch the right data.
3420 type
= BRW_REGISTER_TYPE_F
;
3421 num_components
*= 2;
3422 dest
= bld
.vgrf(type
, num_components
);
3425 for (unsigned int i
= 0; i
< num_components
; i
++) {
3426 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3427 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3430 if (nir_dest_bit_size(instr
->dest
) == 64) {
3431 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3432 instr
->num_components
);
3437 case nir_intrinsic_load_barycentric_pixel
:
3438 case nir_intrinsic_load_barycentric_centroid
:
3439 case nir_intrinsic_load_barycentric_sample
:
3440 /* Do nothing - load_interpolated_input handling will handle it later. */
3443 case nir_intrinsic_load_barycentric_at_sample
: {
3444 const glsl_interp_mode interpolation
=
3445 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3447 if (nir_src_is_const(instr
->src
[0])) {
3448 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3450 emit_pixel_interpolater_send(bld
,
3451 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3454 brw_imm_ud(msg_data
),
3457 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3458 BRW_REGISTER_TYPE_UD
);
3460 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3461 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3462 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3463 bld
.exec_all().group(1, 0)
3464 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3465 emit_pixel_interpolater_send(bld
,
3466 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3472 /* Make a loop that sends a message to the pixel interpolater
3473 * for the sample number in each live channel. If there are
3474 * multiple channels with the same sample number then these
3475 * will be handled simultaneously with a single interation of
3478 bld
.emit(BRW_OPCODE_DO
);
3480 /* Get the next live sample number into sample_id_reg */
3481 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3483 /* Set the flag register so that we can perform the send
3484 * message on all channels that have the same sample number
3486 bld
.CMP(bld
.null_reg_ud(),
3487 sample_src
, sample_id
,
3488 BRW_CONDITIONAL_EQ
);
3489 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3490 bld
.exec_all().group(1, 0)
3491 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3493 emit_pixel_interpolater_send(bld
,
3494 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3497 component(msg_data
, 0),
3499 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3501 /* Continue the loop if there are any live channels left */
3502 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3504 bld
.emit(BRW_OPCODE_WHILE
));
3510 case nir_intrinsic_load_barycentric_at_offset
: {
3511 const glsl_interp_mode interpolation
=
3512 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3514 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3517 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3518 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3519 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3521 emit_pixel_interpolater_send(bld
,
3522 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3525 brw_imm_ud(off_x
| (off_y
<< 4)),
3528 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3529 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3530 BRW_REGISTER_TYPE_F
);
3531 for (int i
= 0; i
< 2; i
++) {
3532 fs_reg temp
= vgrf(glsl_type::float_type
);
3533 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3534 fs_reg itemp
= vgrf(glsl_type::int_type
);
3536 bld
.MOV(itemp
, temp
);
3538 /* Clamp the upper end of the range to +7/16.
3539 * ARB_gpu_shader5 requires that we support a maximum offset
3540 * of +0.5, which isn't representable in a S0.4 value -- if
3541 * we didn't clamp it, we'd end up with -8/16, which is the
3542 * opposite of what the shader author wanted.
3544 * This is legal due to ARB_gpu_shader5's quantization
3547 * "Not all values of <offset> may be supported; x and y
3548 * offsets may be rounded to fixed-point values with the
3549 * number of fraction bits given by the
3550 * implementation-dependent constant
3551 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3553 set_condmod(BRW_CONDITIONAL_L
,
3554 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3557 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3558 emit_pixel_interpolater_send(bld
,
3568 case nir_intrinsic_load_interpolated_input
: {
3569 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3570 emit_fragcoord_interpolation(dest
);
3574 assert(instr
->src
[0].ssa
&&
3575 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3576 nir_intrinsic_instr
*bary_intrinsic
=
3577 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3578 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3579 enum glsl_interp_mode interp_mode
=
3580 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3583 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3584 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3585 /* Use the result of the PI message */
3586 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3588 /* Use the delta_xy values computed from the payload */
3589 enum brw_barycentric_mode bary
=
3590 brw_barycentric_mode(interp_mode
, bary_intrin
);
3592 dst_xy
= this->delta_xy
[bary
];
3595 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3597 component(interp_reg(nir_intrinsic_base(instr
),
3598 nir_intrinsic_component(instr
) + i
), 0);
3599 interp
.type
= BRW_REGISTER_TYPE_F
;
3600 dest
.type
= BRW_REGISTER_TYPE_F
;
3602 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3603 fs_reg tmp
= vgrf(glsl_type::float_type
);
3604 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3605 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3607 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3614 nir_emit_intrinsic(bld
, instr
);
3620 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3622 if (nir_src_is_const(instr
->src
[src
])) {
3623 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3626 else if (add_val
== -1)
3634 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3635 nir_intrinsic_instr
*instr
)
3637 assert(stage
== MESA_SHADER_COMPUTE
);
3638 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3641 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3642 dest
= get_nir_dest(instr
->dest
);
3644 switch (instr
->intrinsic
) {
3645 case nir_intrinsic_barrier
:
3647 cs_prog_data
->uses_barrier
= true;
3650 case nir_intrinsic_load_subgroup_id
:
3651 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3654 case nir_intrinsic_load_local_invocation_id
:
3655 case nir_intrinsic_load_work_group_id
: {
3656 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3657 fs_reg val
= nir_system_values
[sv
];
3658 assert(val
.file
!= BAD_FILE
);
3659 dest
.type
= val
.type
;
3660 for (unsigned i
= 0; i
< 3; i
++)
3661 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3665 case nir_intrinsic_load_num_work_groups
: {
3666 const unsigned surface
=
3667 cs_prog_data
->binding_table
.work_groups_start
;
3669 cs_prog_data
->uses_num_work_groups
= true;
3671 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3672 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3673 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3674 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3676 /* Read the 3 GLuint components of gl_NumWorkGroups */
3677 for (unsigned i
= 0; i
< 3; i
++) {
3678 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3679 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3680 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3685 case nir_intrinsic_shared_atomic_add
:
3686 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3688 case nir_intrinsic_shared_atomic_imin
:
3689 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3691 case nir_intrinsic_shared_atomic_umin
:
3692 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3694 case nir_intrinsic_shared_atomic_imax
:
3695 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3697 case nir_intrinsic_shared_atomic_umax
:
3698 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3700 case nir_intrinsic_shared_atomic_and
:
3701 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3703 case nir_intrinsic_shared_atomic_or
:
3704 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3706 case nir_intrinsic_shared_atomic_xor
:
3707 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3709 case nir_intrinsic_shared_atomic_exchange
:
3710 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3712 case nir_intrinsic_shared_atomic_comp_swap
:
3713 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3715 case nir_intrinsic_shared_atomic_fmin
:
3716 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3718 case nir_intrinsic_shared_atomic_fmax
:
3719 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3721 case nir_intrinsic_shared_atomic_fcomp_swap
:
3722 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3725 case nir_intrinsic_load_shared
: {
3726 assert(devinfo
->gen
>= 7);
3727 assert(stage
== MESA_SHADER_COMPUTE
);
3729 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3730 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3731 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3732 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3733 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3735 /* Make dest unsigned because that's what the temporary will be */
3736 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3738 /* Read the vector */
3739 if (nir_intrinsic_align(instr
) >= 4) {
3740 assert(nir_dest_bit_size(instr
->dest
) == 32);
3741 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3743 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3744 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3745 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3747 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3748 assert(nir_dest_num_components(instr
->dest
) == 1);
3749 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3751 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3752 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3753 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3754 bld
.MOV(dest
, read_result
);
3759 case nir_intrinsic_store_shared
: {
3760 assert(devinfo
->gen
>= 7);
3761 assert(stage
== MESA_SHADER_COMPUTE
);
3763 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3764 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3765 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3766 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3767 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3769 fs_reg data
= get_nir_src(instr
->src
[0]);
3770 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3772 assert(nir_intrinsic_write_mask(instr
) ==
3773 (1u << instr
->num_components
) - 1);
3774 if (nir_intrinsic_align(instr
) >= 4) {
3775 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3776 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3777 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3778 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3779 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3780 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3782 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3783 assert(nir_src_num_components(instr
->src
[0]) == 1);
3784 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3786 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3787 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3789 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3790 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3796 nir_emit_intrinsic(bld
, instr
);
3802 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3803 nir_op op
, brw_reg_type type
)
3805 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3806 switch (type_sz(type
)) {
3808 assert(type
!= BRW_REGISTER_TYPE_HF
);
3809 return retype(brw_imm_uw(value
.u16
), type
);
3811 return retype(brw_imm_ud(value
.u32
), type
);
3813 if (type
== BRW_REGISTER_TYPE_DF
)
3814 return setup_imm_df(bld
, value
.f64
);
3816 return retype(brw_imm_u64(value
.u64
), type
);
3818 unreachable("Invalid type size");
3823 brw_op_for_nir_reduction_op(nir_op op
)
3826 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3827 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3828 case nir_op_imul
: return BRW_OPCODE_MUL
;
3829 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3830 case nir_op_imin
: return BRW_OPCODE_SEL
;
3831 case nir_op_umin
: return BRW_OPCODE_SEL
;
3832 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3833 case nir_op_imax
: return BRW_OPCODE_SEL
;
3834 case nir_op_umax
: return BRW_OPCODE_SEL
;
3835 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3836 case nir_op_iand
: return BRW_OPCODE_AND
;
3837 case nir_op_ior
: return BRW_OPCODE_OR
;
3838 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3840 unreachable("Invalid reduction operation");
3844 static brw_conditional_mod
3845 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3848 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3849 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3850 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3851 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3852 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3853 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3854 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3855 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3856 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3857 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3858 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3859 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3860 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3862 unreachable("Invalid reduction operation");
3867 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3868 nir_intrinsic_instr
*instr
)
3870 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3872 if (stage_prog_data
->binding_table
.image_start
> 0) {
3873 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3874 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3876 bld
.ADD(image
, image
,
3877 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3881 return bld
.emit_uniformize(image
);
3885 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3886 nir_intrinsic_instr
*instr
)
3888 /* SSBO stores are weird in that their index is in src[1] */
3889 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3892 if (nir_src_is_const(instr
->src
[src
])) {
3893 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3894 nir_src_as_uint(instr
->src
[src
]);
3895 surf_index
= brw_imm_ud(index
);
3897 surf_index
= vgrf(glsl_type::uint_type
);
3898 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3899 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3902 return bld
.emit_uniformize(surf_index
);
3906 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3908 switch (nir_intrinsic_image_dim(instr
)) {
3909 case GLSL_SAMPLER_DIM_1D
:
3910 return 1 + nir_intrinsic_image_array(instr
);
3911 case GLSL_SAMPLER_DIM_2D
:
3912 case GLSL_SAMPLER_DIM_RECT
:
3913 return 2 + nir_intrinsic_image_array(instr
);
3914 case GLSL_SAMPLER_DIM_3D
:
3915 case GLSL_SAMPLER_DIM_CUBE
:
3917 case GLSL_SAMPLER_DIM_BUF
:
3919 case GLSL_SAMPLER_DIM_MS
:
3920 return 2 + nir_intrinsic_image_array(instr
);
3922 unreachable("Invalid image dimension");
3927 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3930 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3931 dest
= get_nir_dest(instr
->dest
);
3933 switch (instr
->intrinsic
) {
3934 case nir_intrinsic_image_load
:
3935 case nir_intrinsic_image_store
:
3936 case nir_intrinsic_image_atomic_add
:
3937 case nir_intrinsic_image_atomic_min
:
3938 case nir_intrinsic_image_atomic_max
:
3939 case nir_intrinsic_image_atomic_and
:
3940 case nir_intrinsic_image_atomic_or
:
3941 case nir_intrinsic_image_atomic_xor
:
3942 case nir_intrinsic_image_atomic_exchange
:
3943 case nir_intrinsic_image_atomic_comp_swap
: {
3944 if (stage
== MESA_SHADER_FRAGMENT
&&
3945 instr
->intrinsic
!= nir_intrinsic_image_load
)
3946 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3948 /* Get some metadata from the image intrinsic. */
3949 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3950 const GLenum format
= nir_intrinsic_format(instr
);
3952 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3953 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3954 get_nir_image_intrinsic_image(bld
, instr
);
3955 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3956 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
3957 brw_imm_ud(image_intrinsic_coord_components(instr
));
3959 /* Emit an image load, store or atomic op. */
3960 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3961 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3963 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
3964 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3965 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3966 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3967 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3968 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
3969 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
3970 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3973 unsigned num_srcs
= info
->num_srcs
;
3975 switch (instr
->intrinsic
) {
3976 case nir_intrinsic_image_atomic_add
:
3977 assert(num_srcs
== 4);
3979 op
= get_op_for_atomic_add(instr
, 3);
3981 if (op
!= BRW_AOP_ADD
)
3984 case nir_intrinsic_image_atomic_min
:
3985 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3986 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3988 case nir_intrinsic_image_atomic_max
:
3989 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3990 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3992 case nir_intrinsic_image_atomic_and
:
3995 case nir_intrinsic_image_atomic_or
:
3998 case nir_intrinsic_image_atomic_xor
:
4001 case nir_intrinsic_image_atomic_exchange
:
4004 case nir_intrinsic_image_atomic_comp_swap
:
4008 unreachable("Not reachable.");
4011 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4015 data
= get_nir_src(instr
->src
[3]);
4016 if (num_srcs
>= 5) {
4017 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4018 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4019 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4022 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4024 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4025 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4030 case nir_intrinsic_image_size
: {
4031 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4032 * into will handle the binding table index for us in the geneerator.
4034 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4035 BRW_REGISTER_TYPE_UD
);
4036 image
= bld
.emit_uniformize(image
);
4038 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4039 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4040 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4041 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4042 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4044 /* Since the image size is always uniform, we can just emit a SIMD8
4045 * query instruction and splat the result out.
4047 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4049 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4050 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4051 tmp
, srcs
, ARRAY_SIZE(srcs
));
4052 inst
->size_written
= 4 * REG_SIZE
;
4054 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4055 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4056 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4057 offset(retype(dest
, tmp
.type
), bld
, c
),
4058 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4060 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4061 component(offset(tmp
, ubld
, c
), 0));
4067 case nir_intrinsic_image_load_raw_intel
: {
4068 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4069 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4070 get_nir_image_intrinsic_image(bld
, instr
);
4071 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4072 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4073 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4076 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4077 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4078 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4082 case nir_intrinsic_image_store_raw_intel
: {
4083 if (stage
== MESA_SHADER_FRAGMENT
)
4084 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4086 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4087 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4088 get_nir_image_intrinsic_image(bld
, instr
);
4089 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4090 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4091 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4092 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4094 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4095 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4099 case nir_intrinsic_group_memory_barrier
:
4100 case nir_intrinsic_memory_barrier_shared
:
4101 case nir_intrinsic_memory_barrier_atomic_counter
:
4102 case nir_intrinsic_memory_barrier_buffer
:
4103 case nir_intrinsic_memory_barrier_image
:
4104 case nir_intrinsic_memory_barrier
: {
4105 const fs_builder ubld
= bld
.group(8, 0);
4106 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4107 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
4108 ->size_written
= 2 * REG_SIZE
;
4112 case nir_intrinsic_shader_clock
: {
4113 /* We cannot do anything if there is an event, so ignore it for now */
4114 const fs_reg shader_clock
= get_timestamp(bld
);
4115 const fs_reg srcs
[] = { component(shader_clock
, 0),
4116 component(shader_clock
, 1) };
4117 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4121 case nir_intrinsic_image_samples
:
4122 /* The driver does not support multi-sampled images. */
4123 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4126 case nir_intrinsic_load_uniform
: {
4127 /* Offsets are in bytes but they should always aligned to
4130 assert(instr
->const_index
[0] % 4 == 0 ||
4131 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4133 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4135 if (nir_src_is_const(instr
->src
[0])) {
4136 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4137 assert(load_offset
% type_sz(dest
.type
) == 0);
4138 /* For 16-bit types we add the module of the const_index[0]
4139 * offset to access to not 32-bit aligned element
4141 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4143 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4144 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4147 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4148 BRW_REGISTER_TYPE_UD
);
4150 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4151 * go past the end of the uniform. In order to keep the n'th
4152 * component from running past, we subtract off the size of all but
4153 * one component of the vector.
4155 assert(instr
->const_index
[1] >=
4156 instr
->num_components
* (int) type_sz(dest
.type
));
4157 unsigned read_size
= instr
->const_index
[1] -
4158 (instr
->num_components
- 1) * type_sz(dest
.type
);
4160 bool supports_64bit_indirects
=
4161 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4163 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4164 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4165 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4166 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4167 indirect
, brw_imm_ud(read_size
));
4170 const unsigned num_mov_indirects
=
4171 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4172 /* We read a little bit less per MOV INDIRECT, as they are now
4173 * 32-bits ones instead of 64-bit. Fix read_size then.
4175 const unsigned read_size_32bit
= read_size
-
4176 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4177 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4178 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4179 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4180 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4181 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4182 indirect
, brw_imm_ud(read_size_32bit
));
4190 case nir_intrinsic_load_ubo
: {
4192 if (nir_src_is_const(instr
->src
[0])) {
4193 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4194 nir_src_as_uint(instr
->src
[0]);
4195 surf_index
= brw_imm_ud(index
);
4197 /* The block index is not a constant. Evaluate the index expression
4198 * per-channel and add the base UBO index; we have to select a value
4199 * from any live channel.
4201 surf_index
= vgrf(glsl_type::uint_type
);
4202 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4203 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4204 surf_index
= bld
.emit_uniformize(surf_index
);
4207 if (!nir_src_is_const(instr
->src
[1])) {
4208 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4209 BRW_REGISTER_TYPE_UD
);
4211 for (int i
= 0; i
< instr
->num_components
; i
++)
4212 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4213 base_offset
, i
* type_sz(dest
.type
));
4215 /* Even if we are loading doubles, a pull constant load will load
4216 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4217 * need to load a full dvec4 we will have to emit 2 loads. This is
4218 * similar to demote_pull_constants(), except that in that case we
4219 * see individual accesses to each component of the vector and then
4220 * we let CSE deal with duplicate loads. Here we see a vector access
4221 * and we have to split it if necessary.
4223 const unsigned type_size
= type_sz(dest
.type
);
4224 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4226 /* See if we've selected this as a push constant candidate */
4227 if (nir_src_is_const(instr
->src
[0])) {
4228 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4229 const unsigned offset_256b
= load_offset
/ 32;
4232 for (int i
= 0; i
< 4; i
++) {
4233 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4234 if (range
->block
== ubo_block
&&
4235 offset_256b
>= range
->start
&&
4236 offset_256b
< range
->start
+ range
->length
) {
4238 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4239 push_reg
.offset
= load_offset
- 32 * range
->start
;
4244 if (push_reg
.file
!= BAD_FILE
) {
4245 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4246 bld
.MOV(offset(dest
, bld
, i
),
4247 byte_offset(push_reg
, i
* type_size
));
4253 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4254 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4255 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4257 for (unsigned c
= 0; c
< instr
->num_components
;) {
4258 const unsigned base
= load_offset
+ c
* type_size
;
4259 /* Number of usable components in the next block-aligned load. */
4260 const unsigned count
= MIN2(instr
->num_components
- c
,
4261 (block_sz
- base
% block_sz
) / type_size
);
4263 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4264 packed_consts
, surf_index
,
4265 brw_imm_ud(base
& ~(block_sz
- 1)));
4267 const fs_reg consts
=
4268 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4271 for (unsigned d
= 0; d
< count
; d
++)
4272 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4280 case nir_intrinsic_load_global
: {
4281 assert(devinfo
->gen
>= 8);
4283 if (nir_intrinsic_align(instr
) >= 4) {
4284 assert(nir_dest_bit_size(instr
->dest
) == 32);
4285 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4287 get_nir_src(instr
->src
[0]), /* Address */
4288 fs_reg(), /* No source data */
4289 brw_imm_ud(instr
->num_components
));
4290 inst
->size_written
= instr
->num_components
*
4291 inst
->dst
.component_size(inst
->exec_size
);
4293 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4294 assert(bit_size
<= 32);
4295 assert(nir_dest_num_components(instr
->dest
) == 1);
4296 brw_reg_type data_type
=
4297 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4298 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4299 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4301 get_nir_src(instr
->src
[0]), /* Address */
4302 fs_reg(), /* No source data */
4303 brw_imm_ud(bit_size
));
4304 bld
.MOV(retype(dest
, data_type
), tmp
);
4309 case nir_intrinsic_store_global
:
4310 assert(devinfo
->gen
>= 8);
4312 if (stage
== MESA_SHADER_FRAGMENT
)
4313 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4315 if (nir_intrinsic_align(instr
) >= 4) {
4316 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4317 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4319 get_nir_src(instr
->src
[1]), /* Address */
4320 get_nir_src(instr
->src
[0]), /* Data */
4321 brw_imm_ud(instr
->num_components
));
4323 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4324 assert(bit_size
<= 32);
4325 assert(nir_src_num_components(instr
->src
[0]) == 1);
4326 brw_reg_type data_type
=
4327 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4328 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4329 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4330 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4332 get_nir_src(instr
->src
[1]), /* Address */
4334 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4338 case nir_intrinsic_global_atomic_add
:
4339 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4341 case nir_intrinsic_global_atomic_imin
:
4342 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4344 case nir_intrinsic_global_atomic_umin
:
4345 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4347 case nir_intrinsic_global_atomic_imax
:
4348 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4350 case nir_intrinsic_global_atomic_umax
:
4351 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4353 case nir_intrinsic_global_atomic_and
:
4354 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4356 case nir_intrinsic_global_atomic_or
:
4357 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4359 case nir_intrinsic_global_atomic_xor
:
4360 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4362 case nir_intrinsic_global_atomic_exchange
:
4363 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4365 case nir_intrinsic_global_atomic_comp_swap
:
4366 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4368 case nir_intrinsic_global_atomic_fmin
:
4369 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4371 case nir_intrinsic_global_atomic_fmax
:
4372 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4374 case nir_intrinsic_global_atomic_fcomp_swap
:
4375 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4378 case nir_intrinsic_load_ssbo
: {
4379 assert(devinfo
->gen
>= 7);
4381 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4382 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4383 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4384 get_nir_ssbo_intrinsic_index(bld
, instr
);
4385 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4386 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4388 /* Make dest unsigned because that's what the temporary will be */
4389 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4391 /* Read the vector */
4392 if (nir_intrinsic_align(instr
) >= 4) {
4393 assert(nir_dest_bit_size(instr
->dest
) == 32);
4394 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4396 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4397 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4398 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4400 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4401 assert(nir_dest_num_components(instr
->dest
) == 1);
4402 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4404 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4405 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4406 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4407 bld
.MOV(dest
, read_result
);
4412 case nir_intrinsic_store_ssbo
: {
4413 assert(devinfo
->gen
>= 7);
4415 if (stage
== MESA_SHADER_FRAGMENT
)
4416 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4418 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4419 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4420 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4421 get_nir_ssbo_intrinsic_index(bld
, instr
);
4422 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4423 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4425 fs_reg data
= get_nir_src(instr
->src
[0]);
4426 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4428 assert(nir_intrinsic_write_mask(instr
) ==
4429 (1u << instr
->num_components
) - 1);
4430 if (nir_intrinsic_align(instr
) >= 4) {
4431 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4432 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4433 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4434 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4435 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4436 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4438 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4439 assert(nir_src_num_components(instr
->src
[0]) == 1);
4440 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4442 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4443 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4445 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4446 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4451 case nir_intrinsic_store_output
: {
4452 fs_reg src
= get_nir_src(instr
->src
[0]);
4454 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4455 unsigned num_components
= instr
->num_components
;
4456 unsigned first_component
= nir_intrinsic_component(instr
);
4457 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4458 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4459 num_components
*= 2;
4462 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4463 4 * store_offset
), src
.type
);
4464 for (unsigned j
= 0; j
< num_components
; j
++) {
4465 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4466 offset(src
, bld
, j
));
4471 case nir_intrinsic_ssbo_atomic_add
:
4472 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4474 case nir_intrinsic_ssbo_atomic_imin
:
4475 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4477 case nir_intrinsic_ssbo_atomic_umin
:
4478 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4480 case nir_intrinsic_ssbo_atomic_imax
:
4481 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4483 case nir_intrinsic_ssbo_atomic_umax
:
4484 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4486 case nir_intrinsic_ssbo_atomic_and
:
4487 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4489 case nir_intrinsic_ssbo_atomic_or
:
4490 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4492 case nir_intrinsic_ssbo_atomic_xor
:
4493 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4495 case nir_intrinsic_ssbo_atomic_exchange
:
4496 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4498 case nir_intrinsic_ssbo_atomic_comp_swap
:
4499 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4501 case nir_intrinsic_ssbo_atomic_fmin
:
4502 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4504 case nir_intrinsic_ssbo_atomic_fmax
:
4505 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4507 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4508 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4511 case nir_intrinsic_get_buffer_size
: {
4512 assert(nir_src_num_components(instr
->src
[0]) == 1);
4513 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4514 nir_src_as_uint(instr
->src
[0]) : 0;
4516 /* A resinfo's sampler message is used to get the buffer size. The
4517 * SIMD8's writeback message consists of four registers and SIMD16's
4518 * writeback message consists of 8 destination registers (two per each
4519 * component). Because we are only interested on the first channel of
4520 * the first returned component, where resinfo returns the buffer size
4521 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4522 * the dispatch width.
4524 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4525 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4526 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4529 ubld
.MOV(src_payload
, brw_imm_d(0));
4531 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4532 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4533 src_payload
, brw_imm_ud(index
));
4534 inst
->header_size
= 0;
4536 inst
->size_written
= 4 * REG_SIZE
;
4538 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4540 * "Out-of-bounds checking is always performed at a DWord granularity. If
4541 * any part of the DWord is out-of-bounds then the whole DWord is
4542 * considered out-of-bounds."
4544 * This implies that types with size smaller than 4-bytes need to be
4545 * padded if they don't complete the last dword of the buffer. But as we
4546 * need to maintain the original size we need to reverse the padding
4547 * calculation to return the correct size to know the number of elements
4548 * of an unsized array. As we stored in the last two bits of the surface
4549 * size the needed padding for the buffer, we calculate here the
4550 * original buffer_size reversing the surface_size calculation:
4552 * surface_size = isl_align(buffer_size, 4) +
4553 * (isl_align(buffer_size) - buffer_size)
4555 * buffer_size = surface_size & ~3 - surface_size & 3
4558 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4559 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4560 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4562 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4563 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4564 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4566 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4570 case nir_intrinsic_load_subgroup_invocation
:
4571 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4572 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4575 case nir_intrinsic_load_subgroup_eq_mask
:
4576 case nir_intrinsic_load_subgroup_ge_mask
:
4577 case nir_intrinsic_load_subgroup_gt_mask
:
4578 case nir_intrinsic_load_subgroup_le_mask
:
4579 case nir_intrinsic_load_subgroup_lt_mask
:
4580 unreachable("not reached");
4582 case nir_intrinsic_vote_any
: {
4583 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4585 /* The any/all predicates do not consider channel enables. To prevent
4586 * dead channels from affecting the result, we initialize the flag with
4587 * with the identity value for the logical operation.
4589 if (dispatch_width
== 32) {
4590 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4591 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4594 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4596 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4598 /* For some reason, the any/all predicates don't work properly with
4599 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4600 * doesn't read the correct subset of the flag register and you end up
4601 * getting garbage in the second half. Work around this by using a pair
4602 * of 1-wide MOVs and scattering the result.
4604 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4605 ubld
.MOV(res1
, brw_imm_d(0));
4606 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4607 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4608 BRW_PREDICATE_ALIGN1_ANY32H
,
4609 ubld
.MOV(res1
, brw_imm_d(-1)));
4611 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4614 case nir_intrinsic_vote_all
: {
4615 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4617 /* The any/all predicates do not consider channel enables. To prevent
4618 * dead channels from affecting the result, we initialize the flag with
4619 * with the identity value for the logical operation.
4621 if (dispatch_width
== 32) {
4622 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4623 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4624 brw_imm_ud(0xffffffff));
4626 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4628 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4630 /* For some reason, the any/all predicates don't work properly with
4631 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4632 * doesn't read the correct subset of the flag register and you end up
4633 * getting garbage in the second half. Work around this by using a pair
4634 * of 1-wide MOVs and scattering the result.
4636 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4637 ubld
.MOV(res1
, brw_imm_d(0));
4638 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4639 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4640 BRW_PREDICATE_ALIGN1_ALL32H
,
4641 ubld
.MOV(res1
, brw_imm_d(-1)));
4643 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4646 case nir_intrinsic_vote_feq
:
4647 case nir_intrinsic_vote_ieq
: {
4648 fs_reg value
= get_nir_src(instr
->src
[0]);
4649 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4650 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4651 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4652 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4655 fs_reg uniformized
= bld
.emit_uniformize(value
);
4656 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4658 /* The any/all predicates do not consider channel enables. To prevent
4659 * dead channels from affecting the result, we initialize the flag with
4660 * with the identity value for the logical operation.
4662 if (dispatch_width
== 32) {
4663 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4664 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4665 brw_imm_ud(0xffffffff));
4667 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4669 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4671 /* For some reason, the any/all predicates don't work properly with
4672 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4673 * doesn't read the correct subset of the flag register and you end up
4674 * getting garbage in the second half. Work around this by using a pair
4675 * of 1-wide MOVs and scattering the result.
4677 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4678 ubld
.MOV(res1
, brw_imm_d(0));
4679 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4680 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4681 BRW_PREDICATE_ALIGN1_ALL32H
,
4682 ubld
.MOV(res1
, brw_imm_d(-1)));
4684 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4688 case nir_intrinsic_ballot
: {
4689 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4690 BRW_REGISTER_TYPE_UD
);
4691 struct brw_reg flag
= brw_flag_reg(0, 0);
4692 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4693 * as f0.0. This is a problem for fragment programs as we currently use
4694 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4695 * programs yet so this isn't a problem. When we do, something will
4698 if (dispatch_width
== 32)
4699 flag
.type
= BRW_REGISTER_TYPE_UD
;
4701 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4702 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4704 if (instr
->dest
.ssa
.bit_size
> 32) {
4705 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4707 dest
.type
= BRW_REGISTER_TYPE_UD
;
4709 bld
.MOV(dest
, flag
);
4713 case nir_intrinsic_read_invocation
: {
4714 const fs_reg value
= get_nir_src(instr
->src
[0]);
4715 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4716 fs_reg tmp
= bld
.vgrf(value
.type
);
4718 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4719 bld
.emit_uniformize(invocation
));
4721 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4725 case nir_intrinsic_read_first_invocation
: {
4726 const fs_reg value
= get_nir_src(instr
->src
[0]);
4727 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4731 case nir_intrinsic_shuffle
: {
4732 const fs_reg value
= get_nir_src(instr
->src
[0]);
4733 const fs_reg index
= get_nir_src(instr
->src
[1]);
4735 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4739 case nir_intrinsic_first_invocation
: {
4740 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4741 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4742 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4743 fs_reg(component(tmp
, 0)));
4747 case nir_intrinsic_quad_broadcast
: {
4748 const fs_reg value
= get_nir_src(instr
->src
[0]);
4749 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4751 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4752 value
, brw_imm_ud(index
), brw_imm_ud(4));
4756 case nir_intrinsic_quad_swap_horizontal
: {
4757 const fs_reg value
= get_nir_src(instr
->src
[0]);
4758 const fs_reg tmp
= bld
.vgrf(value
.type
);
4759 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4761 const fs_reg src_left
= horiz_stride(value
, 2);
4762 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4763 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4764 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4766 ubld
.MOV(tmp_left
, src_right
);
4767 ubld
.MOV(tmp_right
, src_left
);
4769 bld
.MOV(retype(dest
, value
.type
), tmp
);
4773 case nir_intrinsic_quad_swap_vertical
: {
4774 const fs_reg value
= get_nir_src(instr
->src
[0]);
4775 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4776 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4777 const fs_reg tmp
= bld
.vgrf(value
.type
);
4778 const fs_builder ubld
= bld
.exec_all();
4779 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4780 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4781 bld
.MOV(retype(dest
, value
.type
), tmp
);
4783 /* For larger data types, we have to either emit dispatch_width many
4784 * MOVs or else fall back to doing indirects.
4786 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4787 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4789 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4794 case nir_intrinsic_quad_swap_diagonal
: {
4795 const fs_reg value
= get_nir_src(instr
->src
[0]);
4796 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4797 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4798 const fs_reg tmp
= bld
.vgrf(value
.type
);
4799 const fs_builder ubld
= bld
.exec_all();
4800 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4801 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4802 bld
.MOV(retype(dest
, value
.type
), tmp
);
4804 /* For larger data types, we have to either emit dispatch_width many
4805 * MOVs or else fall back to doing indirects.
4807 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4808 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4810 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4815 case nir_intrinsic_reduce
: {
4816 fs_reg src
= get_nir_src(instr
->src
[0]);
4817 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4818 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4819 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4820 cluster_size
= dispatch_width
;
4822 /* Figure out the source type */
4823 src
.type
= brw_type_for_nir_type(devinfo
,
4824 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4825 nir_src_bit_size(instr
->src
[0])));
4827 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4828 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4829 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4831 /* Set up a register for all of our scratching around and initialize it
4832 * to reduction operation's identity value.
4834 fs_reg scan
= bld
.vgrf(src
.type
);
4835 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4837 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4839 dest
.type
= src
.type
;
4840 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4841 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4842 * the distance between clusters is at least 2 GRFs. In this case,
4843 * we don't need the weird striding of the CLUSTER_BROADCAST
4844 * instruction and can just do regular MOVs.
4846 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4847 const unsigned groups
=
4848 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4849 const unsigned group_size
= dispatch_width
/ groups
;
4850 for (unsigned i
= 0; i
< groups
; i
++) {
4851 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4852 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4853 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4854 component(scan
, comp
));
4857 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4858 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4863 case nir_intrinsic_inclusive_scan
:
4864 case nir_intrinsic_exclusive_scan
: {
4865 fs_reg src
= get_nir_src(instr
->src
[0]);
4866 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4868 /* Figure out the source type */
4869 src
.type
= brw_type_for_nir_type(devinfo
,
4870 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4871 nir_src_bit_size(instr
->src
[0])));
4873 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4874 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4875 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4877 /* Set up a register for all of our scratching around and initialize it
4878 * to reduction operation's identity value.
4880 fs_reg scan
= bld
.vgrf(src
.type
);
4881 const fs_builder allbld
= bld
.exec_all();
4882 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4884 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4885 /* Exclusive scan is a bit harder because we have to do an annoying
4886 * shift of the contents before we can begin. To make things worse,
4887 * we can't do this with a normal stride; we have to use indirects.
4889 fs_reg shifted
= bld
.vgrf(src
.type
);
4890 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4891 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4893 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4894 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4898 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4900 bld
.MOV(retype(dest
, src
.type
), scan
);
4904 case nir_intrinsic_begin_invocation_interlock
: {
4905 const fs_builder ubld
= bld
.group(8, 0);
4906 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4908 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4914 case nir_intrinsic_end_invocation_interlock
: {
4915 /* We don't need to do anything here */
4920 unreachable("unknown intrinsic");
4925 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4926 int op
, nir_intrinsic_instr
*instr
)
4928 if (stage
== MESA_SHADER_FRAGMENT
)
4929 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4931 /* The BTI untyped atomic messages only support 32-bit atomics. If you
4932 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
4933 * appear to exist. However, if you look at Vol 2a, there are no message
4934 * descriptors provided for Qword atomic ops except for A64 messages.
4936 assert(nir_dest_bit_size(instr
->dest
) == 32);
4939 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4940 dest
= get_nir_dest(instr
->dest
);
4942 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4943 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4944 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4945 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4946 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4949 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4950 data
= get_nir_src(instr
->src
[2]);
4952 if (op
== BRW_AOP_CMPWR
) {
4953 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4954 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4955 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4958 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4960 /* Emit the actual atomic operation */
4962 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4963 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4967 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4968 int op
, nir_intrinsic_instr
*instr
)
4970 if (stage
== MESA_SHADER_FRAGMENT
)
4971 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4974 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4975 dest
= get_nir_dest(instr
->dest
);
4977 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4978 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4979 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4980 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4981 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4983 fs_reg data
= get_nir_src(instr
->src
[2]);
4984 if (op
== BRW_AOP_FCMPWR
) {
4985 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4986 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4987 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4990 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4992 /* Emit the actual atomic operation */
4994 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4995 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4999 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5000 int op
, nir_intrinsic_instr
*instr
)
5003 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5004 dest
= get_nir_dest(instr
->dest
);
5006 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5007 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5008 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5009 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5012 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5013 data
= get_nir_src(instr
->src
[1]);
5014 if (op
== BRW_AOP_CMPWR
) {
5015 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5016 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5017 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5020 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5022 /* Get the offset */
5023 if (nir_src_is_const(instr
->src
[0])) {
5024 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5025 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5027 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5028 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5029 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5030 brw_imm_ud(instr
->const_index
[0]));
5033 /* Emit the actual atomic operation operation */
5035 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5036 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5040 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5041 int op
, nir_intrinsic_instr
*instr
)
5044 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5045 dest
= get_nir_dest(instr
->dest
);
5047 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5048 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5049 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5050 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5052 fs_reg data
= get_nir_src(instr
->src
[1]);
5053 if (op
== BRW_AOP_FCMPWR
) {
5054 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5055 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5056 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5059 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5061 /* Get the offset */
5062 if (nir_src_is_const(instr
->src
[0])) {
5063 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5064 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5066 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5067 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5068 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5069 brw_imm_ud(instr
->const_index
[0]));
5072 /* Emit the actual atomic operation operation */
5074 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5075 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5079 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5080 int op
, nir_intrinsic_instr
*instr
)
5082 if (stage
== MESA_SHADER_FRAGMENT
)
5083 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5086 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5087 dest
= get_nir_dest(instr
->dest
);
5089 fs_reg addr
= get_nir_src(instr
->src
[0]);
5092 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5093 data
= get_nir_src(instr
->src
[1]);
5095 if (op
== BRW_AOP_CMPWR
) {
5096 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5097 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5098 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5102 if (nir_dest_bit_size(instr
->dest
) == 64) {
5103 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5104 dest
, addr
, data
, brw_imm_ud(op
));
5106 assert(nir_dest_bit_size(instr
->dest
) == 32);
5107 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5108 dest
, addr
, data
, brw_imm_ud(op
));
5113 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5114 int op
, nir_intrinsic_instr
*instr
)
5116 if (stage
== MESA_SHADER_FRAGMENT
)
5117 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5119 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5120 fs_reg dest
= get_nir_dest(instr
->dest
);
5122 fs_reg addr
= get_nir_src(instr
->src
[0]);
5124 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5125 fs_reg data
= get_nir_src(instr
->src
[1]);
5127 if (op
== BRW_AOP_FCMPWR
) {
5128 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5129 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5130 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5134 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5135 dest
, addr
, data
, brw_imm_ud(op
));
5139 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5141 unsigned texture
= instr
->texture_index
;
5142 unsigned sampler
= instr
->sampler_index
;
5144 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5146 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5147 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5149 int lod_components
= 0;
5151 /* The hardware requires a LOD for buffer textures */
5152 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5153 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5155 uint32_t header_bits
= 0;
5156 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5157 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5158 switch (instr
->src
[i
].src_type
) {
5159 case nir_tex_src_bias
:
5160 srcs
[TEX_LOGICAL_SRC_LOD
] =
5161 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5163 case nir_tex_src_comparator
:
5164 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5166 case nir_tex_src_coord
:
5167 switch (instr
->op
) {
5169 case nir_texop_txf_ms
:
5170 case nir_texop_txf_ms_mcs
:
5171 case nir_texop_samples_identical
:
5172 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5175 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5179 case nir_tex_src_ddx
:
5180 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5181 lod_components
= nir_tex_instr_src_size(instr
, i
);
5183 case nir_tex_src_ddy
:
5184 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5186 case nir_tex_src_lod
:
5187 switch (instr
->op
) {
5189 srcs
[TEX_LOGICAL_SRC_LOD
] =
5190 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5193 srcs
[TEX_LOGICAL_SRC_LOD
] =
5194 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5197 srcs
[TEX_LOGICAL_SRC_LOD
] =
5198 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5202 case nir_tex_src_min_lod
:
5203 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5204 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5206 case nir_tex_src_ms_index
:
5207 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5210 case nir_tex_src_offset
: {
5211 uint32_t offset_bits
= 0;
5212 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5213 header_bits
|= offset_bits
;
5215 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5216 retype(src
, BRW_REGISTER_TYPE_D
);
5221 case nir_tex_src_projector
:
5222 unreachable("should be lowered");
5224 case nir_tex_src_texture_offset
: {
5225 /* Emit code to evaluate the actual indexing expression */
5226 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5227 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5228 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5232 case nir_tex_src_sampler_offset
: {
5233 /* Emit code to evaluate the actual indexing expression */
5234 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5235 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5236 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5240 case nir_tex_src_texture_handle
:
5241 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5242 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5243 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5246 case nir_tex_src_sampler_handle
:
5247 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5248 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5249 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5252 case nir_tex_src_ms_mcs
:
5253 assert(instr
->op
== nir_texop_txf_ms
);
5254 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5257 case nir_tex_src_plane
: {
5258 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5259 const uint32_t texture_index
=
5260 instr
->texture_index
+
5261 stage_prog_data
->binding_table
.plane_start
[plane
] -
5262 stage_prog_data
->binding_table
.texture_start
;
5264 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5269 unreachable("unknown texture source");
5273 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5274 (instr
->op
== nir_texop_txf_ms
||
5275 instr
->op
== nir_texop_samples_identical
)) {
5276 if (devinfo
->gen
>= 7 &&
5277 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5278 srcs
[TEX_LOGICAL_SRC_MCS
] =
5279 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5280 instr
->coord_components
,
5281 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5282 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5284 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5288 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5289 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5291 bool shader_supports_implicit_lod
= stage
== MESA_SHADER_FRAGMENT
||
5292 (stage
== MESA_SHADER_COMPUTE
&&
5293 nir
->info
.cs
.derivative_group
!= DERIVATIVE_GROUP_NONE
);
5296 switch (instr
->op
) {
5298 opcode
= shader_supports_implicit_lod
?
5299 SHADER_OPCODE_TEX_LOGICAL
: SHADER_OPCODE_TXL_LOGICAL
;
5302 opcode
= FS_OPCODE_TXB_LOGICAL
;
5305 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5308 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5311 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5313 case nir_texop_txf_ms
:
5314 if ((key_tex
->msaa_16
& (1 << sampler
)))
5315 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5317 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5319 case nir_texop_txf_ms_mcs
:
5320 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5322 case nir_texop_query_levels
:
5324 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5327 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5330 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5331 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5333 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5335 case nir_texop_texture_samples
:
5336 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5338 case nir_texop_samples_identical
: {
5339 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5341 /* If mcs is an immediate value, it means there is no MCS. In that case
5342 * just return false.
5344 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5345 bld
.MOV(dst
, brw_imm_ud(0u));
5346 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5347 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5348 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5349 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5350 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5352 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5353 BRW_CONDITIONAL_EQ
);
5358 unreachable("unknown texture opcode");
5361 if (instr
->op
== nir_texop_tg4
) {
5362 if (instr
->component
== 1 &&
5363 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5364 /* gather4 sampler is broken for green channel on RG32F --
5365 * we must ask for blue instead.
5367 header_bits
|= 2 << 16;
5369 header_bits
|= instr
->component
<< 16;
5373 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5374 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5375 inst
->offset
= header_bits
;
5377 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5378 if (devinfo
->gen
>= 9 &&
5379 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5380 unsigned write_mask
= instr
->dest
.is_ssa
?
5381 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5382 (1 << dest_size
) - 1;
5383 assert(write_mask
!= 0); /* dead code should have been eliminated */
5384 inst
->size_written
= util_last_bit(write_mask
) *
5385 inst
->dst
.component_size(inst
->exec_size
);
5387 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5390 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5391 inst
->shadow_compare
= true;
5393 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5394 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5397 for (unsigned i
= 0; i
< dest_size
; i
++)
5398 nir_dest
[i
] = offset(dst
, bld
, i
);
5400 if (instr
->op
== nir_texop_query_levels
) {
5401 /* # levels is in .w */
5402 nir_dest
[0] = offset(dst
, bld
, 3);
5403 } else if (instr
->op
== nir_texop_txs
&&
5404 dest_size
>= 3 && devinfo
->gen
< 7) {
5405 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5406 fs_reg depth
= offset(dst
, bld
, 2);
5407 nir_dest
[2] = vgrf(glsl_type::int_type
);
5408 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5411 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5415 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5417 switch (instr
->type
) {
5418 case nir_jump_break
:
5419 bld
.emit(BRW_OPCODE_BREAK
);
5421 case nir_jump_continue
:
5422 bld
.emit(BRW_OPCODE_CONTINUE
);
5424 case nir_jump_return
:
5426 unreachable("unknown jump");
5431 * This helper takes a source register and un/shuffles it into the destination
5434 * If source type size is smaller than destination type size the operation
5435 * needed is a component shuffle. The opposite case would be an unshuffle. If
5436 * source/destination type size is equal a shuffle is done that would be
5437 * equivalent to a simple MOV.
5439 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5440 * components .xyz 16-bit vector on SIMD8 would be.
5442 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5443 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5445 * This helper will return the following 2 32-bit components with the 16-bit
5448 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5449 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5451 * For unshuffle, the example would be the opposite, a 64-bit type source
5452 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5455 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5456 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5457 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5458 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5460 * The returned result would be the following 4 32-bit components unshuffled:
5462 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5463 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5464 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5465 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5467 * - Source and destination register must not be overlapped.
5468 * - components units are measured in terms of the smaller type between
5469 * source and destination because we are un/shuffling the smaller
5470 * components from/into the bigger ones.
5471 * - first_component parameter allows skipping source components.
5474 shuffle_src_to_dst(const fs_builder
&bld
,
5477 uint32_t first_component
,
5478 uint32_t components
)
5480 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5481 assert(!regions_overlap(dst
,
5482 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5483 offset(src
, bld
, first_component
),
5484 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5485 for (unsigned i
= 0; i
< components
; i
++) {
5486 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5487 offset(src
, bld
, i
+ first_component
));
5489 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5490 /* Source is shuffled into destination */
5491 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5492 assert(!regions_overlap(dst
,
5493 type_sz(dst
.type
) * bld
.dispatch_width() *
5494 DIV_ROUND_UP(components
, size_ratio
),
5495 offset(src
, bld
, first_component
),
5496 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5498 brw_reg_type shuffle_type
=
5499 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5500 BRW_REGISTER_TYPE_D
);
5501 for (unsigned i
= 0; i
< components
; i
++) {
5502 fs_reg shuffle_component_i
=
5503 subscript(offset(dst
, bld
, i
/ size_ratio
),
5504 shuffle_type
, i
% size_ratio
);
5505 bld
.MOV(shuffle_component_i
,
5506 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5509 /* Source is unshuffled into destination */
5510 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5511 assert(!regions_overlap(dst
,
5512 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5513 offset(src
, bld
, first_component
/ size_ratio
),
5514 type_sz(src
.type
) * bld
.dispatch_width() *
5515 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5518 brw_reg_type shuffle_type
=
5519 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5520 BRW_REGISTER_TYPE_D
);
5521 for (unsigned i
= 0; i
< components
; i
++) {
5522 fs_reg shuffle_component_i
=
5523 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5524 shuffle_type
, (first_component
+ i
) % size_ratio
);
5525 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5526 shuffle_component_i
);
5532 shuffle_from_32bit_read(const fs_builder
&bld
,
5535 uint32_t first_component
,
5536 uint32_t components
)
5538 assert(type_sz(src
.type
) == 4);
5540 /* This function takes components in units of the destination type while
5541 * shuffle_src_to_dst takes components in units of the smallest type
5543 if (type_sz(dst
.type
) > 4) {
5544 assert(type_sz(dst
.type
) == 8);
5545 first_component
*= 2;
5549 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5553 shuffle_for_32bit_write(const fs_builder
&bld
,
5555 uint32_t first_component
,
5556 uint32_t components
)
5558 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5559 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5560 /* This function takes components in units of the source type while
5561 * shuffle_src_to_dst takes components in units of the smallest type
5563 if (type_sz(src
.type
) > 4) {
5564 assert(type_sz(src
.type
) == 8);
5565 first_component
*= 2;
5569 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5575 setup_imm_df(const fs_builder
&bld
, double v
)
5577 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5578 assert(devinfo
->gen
>= 7);
5580 if (devinfo
->gen
>= 8)
5581 return brw_imm_df(v
);
5583 /* gen7.5 does not support DF immediates straighforward but the DIM
5584 * instruction allows to set the 64-bit immediate value.
5586 if (devinfo
->is_haswell
) {
5587 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5588 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5589 ubld
.DIM(dst
, brw_imm_df(v
));
5590 return component(dst
, 0);
5593 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5594 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5595 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5597 * Alternatively, we could also produce a normal VGRF (without stride 0)
5598 * by writing to all the channels in the VGRF, however, that would hit the
5599 * gen7 bug where we have to split writes that span more than 1 register
5600 * into instructions with a width of 4 (otherwise the write to the second
5601 * register written runs into an execmask hardware bug) which isn't very
5614 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5615 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5616 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5617 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5619 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5623 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5625 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5626 bld
.MOV(tmp
, brw_imm_w(v
));
5631 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5633 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5634 bld
.MOV(tmp
, brw_imm_uw(v
));