2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 nir_foreach_variable(var
, &nir
->outputs
) {
71 const int loc
= var
->data
.driver_location
;
72 if (outputs
[loc
].file
== BAD_FILE
) {
73 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
[loc
]);
74 for (unsigned i
= 0; i
< vec4s
[loc
]; i
++) {
75 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
82 fs_visitor::nir_setup_uniforms()
84 if (dispatch_width
!= min_dispatch_width
)
87 uniforms
= nir
->num_uniforms
/ 4;
91 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
95 nir_foreach_instr(instr
, block
) {
96 if (instr
->type
!= nir_instr_type_intrinsic
)
99 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
100 switch (intrin
->intrinsic
) {
101 case nir_intrinsic_load_vertex_id
:
102 unreachable("should be lowered by lower_vertex_id().");
104 case nir_intrinsic_load_vertex_id_zero_base
:
105 case nir_intrinsic_load_base_vertex
:
106 case nir_intrinsic_load_instance_id
:
107 case nir_intrinsic_load_base_instance
:
108 case nir_intrinsic_load_draw_id
:
109 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
111 case nir_intrinsic_load_invocation_id
:
112 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
114 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
115 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
116 if (reg
->file
== BAD_FILE
) {
117 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
118 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
119 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
120 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
125 case nir_intrinsic_load_sample_pos
:
126 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
127 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
128 if (reg
->file
== BAD_FILE
)
129 *reg
= *v
->emit_samplepos_setup();
132 case nir_intrinsic_load_sample_id
:
133 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
134 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
135 if (reg
->file
== BAD_FILE
)
136 *reg
= *v
->emit_sampleid_setup();
139 case nir_intrinsic_load_sample_mask_in
:
140 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
141 assert(v
->devinfo
->gen
>= 7);
142 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
143 if (reg
->file
== BAD_FILE
)
144 *reg
= *v
->emit_samplemaskin_setup();
147 case nir_intrinsic_load_work_group_id
:
148 assert(v
->stage
== MESA_SHADER_COMPUTE
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_cs_work_group_id_setup();
154 case nir_intrinsic_load_helper_invocation
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
157 if (reg
->file
== BAD_FILE
) {
158 const fs_builder abld
=
159 v
->bld
.annotate("gl_HelperInvocation", NULL
);
161 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
162 * pixel mask is in g1.7 of the thread payload.
164 * We move the per-channel pixel enable bit to the low bit of each
165 * channel by shifting the byte containing the pixel mask by the
166 * vector immediate 0x76543210UV.
168 * The region of <1,8,0> reads only 1 byte (the pixel masks for
169 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
170 * masks for 2 and 3) in SIMD16.
172 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
174 stride(byte_offset(retype(brw_vec1_grf(1, 0),
175 BRW_REGISTER_TYPE_UB
), 28),
177 brw_imm_v(0x76543210));
179 /* A set bit in the pixel mask means the channel is enabled, but
180 * that is the opposite of gl_HelperInvocation so we need to invert
183 * The negate source-modifier bit of logical instructions on Gen8+
184 * performs 1's complement negation, so we can use that instead of
187 fs_reg inverted
= negate(shifted
);
188 if (v
->devinfo
->gen
< 8) {
189 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
190 abld
.NOT(inverted
, shifted
);
193 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
194 * with 1 and negating.
196 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
197 abld
.AND(anded
, inverted
, brw_imm_uw(1));
199 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
200 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
214 fs_visitor::nir_emit_system_values()
216 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
217 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
218 nir_system_values
[i
] = fs_reg();
221 nir_foreach_function(function
, nir
) {
222 assert(strcmp(function
->name
, "main") == 0);
223 assert(function
->impl
);
224 nir_foreach_block(block
, function
->impl
) {
225 emit_system_values_block(block
, this);
231 * Returns a type based on a reference_type (word, float, half-float) and a
234 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
236 * @FIXME: 64-bit return types are always DF on integer types to maintain
237 * compability with uses of DF previously to the introduction of int64
241 brw_reg_type_from_bit_size(const unsigned bit_size
,
242 const brw_reg_type reference_type
)
244 switch(reference_type
) {
245 case BRW_REGISTER_TYPE_HF
:
246 case BRW_REGISTER_TYPE_F
:
247 case BRW_REGISTER_TYPE_DF
:
250 return BRW_REGISTER_TYPE_HF
;
252 return BRW_REGISTER_TYPE_F
;
254 return BRW_REGISTER_TYPE_DF
;
256 unreachable("Invalid bit size");
258 case BRW_REGISTER_TYPE_W
:
259 case BRW_REGISTER_TYPE_D
:
260 case BRW_REGISTER_TYPE_Q
:
263 return BRW_REGISTER_TYPE_W
;
265 return BRW_REGISTER_TYPE_D
;
267 return BRW_REGISTER_TYPE_DF
;
269 unreachable("Invalid bit size");
271 case BRW_REGISTER_TYPE_UW
:
272 case BRW_REGISTER_TYPE_UD
:
273 case BRW_REGISTER_TYPE_UQ
:
276 return BRW_REGISTER_TYPE_UW
;
278 return BRW_REGISTER_TYPE_UD
;
280 return BRW_REGISTER_TYPE_DF
;
282 unreachable("Invalid bit size");
285 unreachable("Unknown type");
290 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
292 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
293 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
294 nir_locals
[i
] = fs_reg();
297 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
298 unsigned array_elems
=
299 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
300 unsigned size
= array_elems
* reg
->num_components
;
301 const brw_reg_type reg_type
=
302 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
303 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
306 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
309 nir_emit_cf_list(&impl
->body
);
313 fs_visitor::nir_emit_cf_list(exec_list
*list
)
315 exec_list_validate(list
);
316 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
317 switch (node
->type
) {
319 nir_emit_if(nir_cf_node_as_if(node
));
322 case nir_cf_node_loop
:
323 nir_emit_loop(nir_cf_node_as_loop(node
));
326 case nir_cf_node_block
:
327 nir_emit_block(nir_cf_node_as_block(node
));
331 unreachable("Invalid CFG node block");
337 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
339 /* first, put the condition into f0 */
340 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
341 retype(get_nir_src(if_stmt
->condition
),
342 BRW_REGISTER_TYPE_D
));
343 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
345 bld
.IF(BRW_PREDICATE_NORMAL
);
347 nir_emit_cf_list(&if_stmt
->then_list
);
349 /* note: if the else is empty, dead CF elimination will remove it */
350 bld
.emit(BRW_OPCODE_ELSE
);
352 nir_emit_cf_list(&if_stmt
->else_list
);
354 bld
.emit(BRW_OPCODE_ENDIF
);
358 fs_visitor::nir_emit_loop(nir_loop
*loop
)
360 bld
.emit(BRW_OPCODE_DO
);
362 nir_emit_cf_list(&loop
->body
);
364 bld
.emit(BRW_OPCODE_WHILE
);
368 fs_visitor::nir_emit_block(nir_block
*block
)
370 nir_foreach_instr(instr
, block
) {
371 nir_emit_instr(instr
);
376 fs_visitor::nir_emit_instr(nir_instr
*instr
)
378 const fs_builder abld
= bld
.annotate(NULL
, instr
);
380 switch (instr
->type
) {
381 case nir_instr_type_alu
:
382 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
385 case nir_instr_type_intrinsic
:
387 case MESA_SHADER_VERTEX
:
388 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
390 case MESA_SHADER_TESS_CTRL
:
391 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
393 case MESA_SHADER_TESS_EVAL
:
394 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
396 case MESA_SHADER_GEOMETRY
:
397 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
399 case MESA_SHADER_FRAGMENT
:
400 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
402 case MESA_SHADER_COMPUTE
:
403 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
406 unreachable("unsupported shader stage");
410 case nir_instr_type_tex
:
411 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
414 case nir_instr_type_load_const
:
415 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
418 case nir_instr_type_ssa_undef
:
419 /* We create a new VGRF for undefs on every use (by handling
420 * them in get_nir_src()), rather than for each definition.
421 * This helps register coalescing eliminate MOVs from undef.
425 case nir_instr_type_jump
:
426 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
430 unreachable("unknown instruction type");
435 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
439 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
440 const fs_reg
&result
)
442 if (!instr
->src
[0].src
.is_ssa
||
443 !instr
->src
[0].src
.ssa
->parent_instr
)
446 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
449 nir_alu_instr
*src0
=
450 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
452 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
453 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
456 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
457 assert(element
!= NULL
);
459 /* Element type to extract.*/
460 const brw_reg_type type
= brw_int_type(
461 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
462 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
464 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
465 op0
.type
= brw_type_for_nir_type(devinfo
,
466 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
467 nir_src_bit_size(src0
->src
[0].src
)));
468 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
470 set_saturate(instr
->dest
.saturate
,
471 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
476 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
477 const fs_reg
&result
)
479 if (!instr
->src
[0].src
.is_ssa
||
480 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
483 nir_intrinsic_instr
*src0
=
484 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
486 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
489 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
490 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
493 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
494 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
497 fs_reg tmp
= vgrf(glsl_type::int_type
);
499 if (devinfo
->gen
>= 6) {
500 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
501 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
503 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
505 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
506 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
508 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
510 * This negation looks like it's safe in practice, because bits 0:4 will
511 * surely be TRIANGLES
514 if (value1
->f32
[0] == -1.0f
) {
518 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
519 g0
, brw_imm_uw(0x3f80));
521 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
522 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
524 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
526 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
527 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
529 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
531 * This negation looks like it's safe in practice, because bits 0:4 will
532 * surely be TRIANGLES
535 if (value1
->f32
[0] == -1.0f
) {
539 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
541 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
547 emit_find_msb_using_lzd(const fs_builder
&bld
,
548 const fs_reg
&result
,
556 /* LZD of an absolute value source almost always does the right
557 * thing. There are two problem values:
559 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
560 * 0. However, findMSB(int(0x80000000)) == 30.
562 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
563 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
565 * For a value of zero or negative one, -1 will be returned.
567 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
568 * findMSB(-(1<<x)) should return x-1.
570 * For all negative number cases, including 0x80000000 and
571 * 0xffffffff, the correct value is obtained from LZD if instead of
572 * negating the (already negative) value the logical-not is used. A
573 * conditonal logical-not can be achieved in two instructions.
575 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
577 bld
.ASR(temp
, src
, brw_imm_d(31));
578 bld
.XOR(temp
, temp
, src
);
581 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
582 retype(temp
, BRW_REGISTER_TYPE_UD
));
584 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
585 * from the LSB side. Subtract the result from 31 to convert the MSB
586 * count into an LSB count. If no bits are set, LZD will return 32.
587 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
589 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
590 inst
->src
[0].negate
= true;
594 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
596 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
599 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
600 result
.type
= brw_type_for_nir_type(devinfo
,
601 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
602 nir_dest_bit_size(instr
->dest
.dest
)));
605 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
606 op
[i
] = get_nir_src(instr
->src
[i
].src
);
607 op
[i
].type
= brw_type_for_nir_type(devinfo
,
608 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
609 nir_src_bit_size(instr
->src
[i
].src
)));
610 op
[i
].abs
= instr
->src
[i
].abs
;
611 op
[i
].negate
= instr
->src
[i
].negate
;
614 /* We get a bunch of mov's out of the from_ssa pass and they may still
615 * be vectorized. We'll handle them as a special-case. We'll also
616 * handle vecN here because it's basically the same thing.
624 fs_reg temp
= result
;
625 bool need_extra_copy
= false;
626 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
627 if (!instr
->src
[i
].src
.is_ssa
&&
628 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
629 need_extra_copy
= true;
630 temp
= bld
.vgrf(result
.type
, 4);
635 for (unsigned i
= 0; i
< 4; i
++) {
636 if (!(instr
->dest
.write_mask
& (1 << i
)))
639 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
640 inst
= bld
.MOV(offset(temp
, bld
, i
),
641 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
643 inst
= bld
.MOV(offset(temp
, bld
, i
),
644 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
646 inst
->saturate
= instr
->dest
.saturate
;
649 /* In this case the source and destination registers were the same,
650 * so we need to insert an extra set of moves in order to deal with
653 if (need_extra_copy
) {
654 for (unsigned i
= 0; i
< 4; i
++) {
655 if (!(instr
->dest
.write_mask
& (1 << i
)))
658 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
667 /* At this point, we have dealt with any instruction that operates on
668 * more than a single channel. Therefore, we can just adjust the source
669 * and destination registers for that channel and emit the instruction.
671 unsigned channel
= 0;
672 if (nir_op_infos
[instr
->op
].output_size
== 0) {
673 /* Since NIR is doing the scalarizing for us, we should only ever see
674 * vectorized operations with a single channel.
676 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
677 channel
= ffs(instr
->dest
.write_mask
) - 1;
679 result
= offset(result
, bld
, channel
);
682 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
683 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
684 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
690 if (optimize_extract_to_float(instr
, result
))
692 inst
= bld
.MOV(result
, op
[0]);
693 inst
->saturate
= instr
->dest
.saturate
;
699 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
701 * "When source or destination is 64b (...), regioning in Align1
702 * must follow these rules:
704 * 1. Source and destination horizontal stride must be aligned to
708 * This means that 32-bit to 64-bit conversions need to have the 32-bit
709 * data elements aligned to 64-bit. This restriction does not apply to
712 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
713 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
714 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
715 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
716 tmp
= subscript(tmp
, op
[0].type
, 0);
717 inst
= bld
.MOV(tmp
, op
[0]);
718 inst
= bld
.MOV(result
, tmp
);
719 inst
->saturate
= instr
->dest
.saturate
;
732 inst
= bld
.MOV(result
, op
[0]);
733 inst
->saturate
= instr
->dest
.saturate
;
738 /* Straightforward since the source can be assumed to be
741 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
742 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
744 } else if (type_sz(op
[0].type
) < 8) {
745 /* AND(val, 0x80000000) gives the sign bit.
747 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
750 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
752 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
753 op
[0].type
= BRW_REGISTER_TYPE_UD
;
754 result
.type
= BRW_REGISTER_TYPE_UD
;
755 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
757 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
758 inst
->predicate
= BRW_PREDICATE_NORMAL
;
759 if (instr
->dest
.saturate
) {
760 inst
= bld
.MOV(result
, result
);
761 inst
->saturate
= true;
764 /* For doubles we do the same but we need to consider:
766 * - 2-src instructions can't operate with 64-bit immediates
767 * - The sign is encoded in the high 32-bit of each DF
768 * - We need to produce a DF result.
771 fs_reg zero
= vgrf(glsl_type::double_type
);
772 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
773 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
775 bld
.MOV(result
, zero
);
777 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
778 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
779 brw_imm_ud(0x80000000u
));
781 set_predicate(BRW_PREDICATE_NORMAL
,
782 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
784 if (instr
->dest
.saturate
) {
785 inst
= bld
.MOV(result
, result
);
786 inst
->saturate
= true;
793 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
794 * -> non-negative val generates 0x00000000.
795 * Predicated OR sets 1 if val is positive.
797 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
798 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
799 bld
.ASR(result
, op
[0], brw_imm_d(31));
800 inst
= bld
.OR(result
, result
, brw_imm_d(1));
801 inst
->predicate
= BRW_PREDICATE_NORMAL
;
805 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
806 inst
->saturate
= instr
->dest
.saturate
;
810 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
811 inst
->saturate
= instr
->dest
.saturate
;
815 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
816 inst
->saturate
= instr
->dest
.saturate
;
820 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
821 inst
->saturate
= instr
->dest
.saturate
;
825 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
826 inst
->saturate
= instr
->dest
.saturate
;
830 if (fs_key
->high_quality_derivatives
) {
831 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
833 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
835 inst
->saturate
= instr
->dest
.saturate
;
837 case nir_op_fddx_fine
:
838 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
839 inst
->saturate
= instr
->dest
.saturate
;
841 case nir_op_fddx_coarse
:
842 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
843 inst
->saturate
= instr
->dest
.saturate
;
846 if (fs_key
->high_quality_derivatives
) {
847 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
849 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
851 inst
->saturate
= instr
->dest
.saturate
;
853 case nir_op_fddy_fine
:
854 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
855 inst
->saturate
= instr
->dest
.saturate
;
857 case nir_op_fddy_coarse
:
858 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
859 inst
->saturate
= instr
->dest
.saturate
;
864 inst
= bld
.ADD(result
, op
[0], op
[1]);
865 inst
->saturate
= instr
->dest
.saturate
;
869 inst
= bld
.MUL(result
, op
[0], op
[1]);
870 inst
->saturate
= instr
->dest
.saturate
;
874 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
875 bld
.MUL(result
, op
[0], op
[1]);
878 case nir_op_imul_high
:
879 case nir_op_umul_high
:
880 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
881 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
886 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
887 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
890 case nir_op_uadd_carry
:
891 unreachable("Should have been lowered by carry_to_arith().");
893 case nir_op_usub_borrow
:
894 unreachable("Should have been lowered by borrow_to_arith().");
898 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
899 * appears that our hardware just does the right thing for signed
902 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
903 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
907 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
908 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
910 /* Math instructions don't support conditional mod */
911 inst
= bld
.MOV(bld
.null_reg_d(), result
);
912 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
914 /* Now, we need to determine if signs of the sources are different.
915 * When we XOR the sources, the top bit is 0 if they are the same and 1
916 * if they are different. We can then use a conditional modifier to
917 * turn that into a predicate. This leads us to an XOR.l instruction.
919 * Technically, according to the PRM, you're not allowed to use .l on a
920 * XOR instruction. However, emperical experiments and Curro's reading
921 * of the simulator source both indicate that it's safe.
923 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
924 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
925 inst
->predicate
= BRW_PREDICATE_NORMAL
;
926 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
928 /* If the result of the initial remainder operation is non-zero and the
929 * two sources have different signs, add in a copy of op[1] to get the
930 * final integer modulus value.
932 inst
= bld
.ADD(result
, result
, op
[1]);
933 inst
->predicate
= BRW_PREDICATE_NORMAL
;
941 fs_reg dest
= result
;
942 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
943 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
945 brw_conditional_mod cond
;
948 cond
= BRW_CONDITIONAL_L
;
951 cond
= BRW_CONDITIONAL_GE
;
954 cond
= BRW_CONDITIONAL_Z
;
957 cond
= BRW_CONDITIONAL_NZ
;
960 unreachable("bad opcode");
962 bld
.CMP(dest
, op
[0], op
[1], cond
);
963 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
964 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
975 fs_reg dest
= result
;
976 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
977 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
980 brw_conditional_mod cond
;
984 cond
= BRW_CONDITIONAL_L
;
988 cond
= BRW_CONDITIONAL_GE
;
991 cond
= BRW_CONDITIONAL_Z
;
994 cond
= BRW_CONDITIONAL_NZ
;
997 unreachable("bad opcode");
999 bld
.CMP(dest
, op
[0], op
[1], cond
);
1000 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1001 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1007 if (devinfo
->gen
>= 8) {
1008 op
[0] = resolve_source_modifiers(op
[0]);
1010 bld
.NOT(result
, op
[0]);
1013 if (devinfo
->gen
>= 8) {
1014 op
[0] = resolve_source_modifiers(op
[0]);
1015 op
[1] = resolve_source_modifiers(op
[1]);
1017 bld
.XOR(result
, op
[0], op
[1]);
1020 if (devinfo
->gen
>= 8) {
1021 op
[0] = resolve_source_modifiers(op
[0]);
1022 op
[1] = resolve_source_modifiers(op
[1]);
1024 bld
.OR(result
, op
[0], op
[1]);
1027 if (devinfo
->gen
>= 8) {
1028 op
[0] = resolve_source_modifiers(op
[0]);
1029 op
[1] = resolve_source_modifiers(op
[1]);
1031 bld
.AND(result
, op
[0], op
[1]);
1037 case nir_op_ball_fequal2
:
1038 case nir_op_ball_iequal2
:
1039 case nir_op_ball_fequal3
:
1040 case nir_op_ball_iequal3
:
1041 case nir_op_ball_fequal4
:
1042 case nir_op_ball_iequal4
:
1043 case nir_op_bany_fnequal2
:
1044 case nir_op_bany_inequal2
:
1045 case nir_op_bany_fnequal3
:
1046 case nir_op_bany_inequal3
:
1047 case nir_op_bany_fnequal4
:
1048 case nir_op_bany_inequal4
:
1049 unreachable("Lowered by nir_lower_alu_reductions");
1051 case nir_op_fnoise1_1
:
1052 case nir_op_fnoise1_2
:
1053 case nir_op_fnoise1_3
:
1054 case nir_op_fnoise1_4
:
1055 case nir_op_fnoise2_1
:
1056 case nir_op_fnoise2_2
:
1057 case nir_op_fnoise2_3
:
1058 case nir_op_fnoise2_4
:
1059 case nir_op_fnoise3_1
:
1060 case nir_op_fnoise3_2
:
1061 case nir_op_fnoise3_3
:
1062 case nir_op_fnoise3_4
:
1063 case nir_op_fnoise4_1
:
1064 case nir_op_fnoise4_2
:
1065 case nir_op_fnoise4_3
:
1066 case nir_op_fnoise4_4
:
1067 unreachable("not reached: should be handled by lower_noise");
1070 unreachable("not reached: should be handled by ldexp_to_arith()");
1073 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1074 inst
->saturate
= instr
->dest
.saturate
;
1078 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1079 inst
->saturate
= instr
->dest
.saturate
;
1084 bld
.MOV(result
, negate(op
[0]));
1089 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1090 /* two-argument instructions can't take 64-bit immediates */
1094 if (instr
->op
== nir_op_f2b
) {
1095 zero
= vgrf(glsl_type::double_type
);
1096 tmp
= vgrf(glsl_type::double_type
);
1098 zero
= vgrf(glsl_type::int64_t_type
);
1099 tmp
= vgrf(glsl_type::int64_t_type
);
1102 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1103 /* A SIMD16 execution needs to be split in two instructions, so use
1104 * a vgrf instead of the flag register as dst so instruction splitting
1107 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1108 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1110 if (instr
->op
== nir_op_f2b
) {
1111 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1113 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1119 inst
= bld
.RNDZ(result
, op
[0]);
1120 inst
->saturate
= instr
->dest
.saturate
;
1123 case nir_op_fceil
: {
1124 op
[0].negate
= !op
[0].negate
;
1125 fs_reg temp
= vgrf(glsl_type::float_type
);
1126 bld
.RNDD(temp
, op
[0]);
1128 inst
= bld
.MOV(result
, temp
);
1129 inst
->saturate
= instr
->dest
.saturate
;
1133 inst
= bld
.RNDD(result
, op
[0]);
1134 inst
->saturate
= instr
->dest
.saturate
;
1137 inst
= bld
.FRC(result
, op
[0]);
1138 inst
->saturate
= instr
->dest
.saturate
;
1140 case nir_op_fround_even
:
1141 inst
= bld
.RNDE(result
, op
[0]);
1142 inst
->saturate
= instr
->dest
.saturate
;
1145 case nir_op_fquantize2f16
: {
1146 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1147 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1148 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1150 /* The destination stride must be at least as big as the source stride. */
1151 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1154 /* Check for denormal */
1155 fs_reg abs_src0
= op
[0];
1156 abs_src0
.abs
= true;
1157 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1159 /* Get the appropriately signed zero */
1160 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1161 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1162 brw_imm_ud(0x80000000));
1163 /* Do the actual F32 -> F16 -> F32 conversion */
1164 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1165 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1166 /* Select that or zero based on normal status */
1167 inst
= bld
.SEL(result
, zero
, tmp32
);
1168 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1169 inst
->saturate
= instr
->dest
.saturate
;
1176 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1177 inst
->saturate
= instr
->dest
.saturate
;
1183 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1184 inst
->saturate
= instr
->dest
.saturate
;
1187 case nir_op_pack_snorm_2x16
:
1188 case nir_op_pack_snorm_4x8
:
1189 case nir_op_pack_unorm_2x16
:
1190 case nir_op_pack_unorm_4x8
:
1191 case nir_op_unpack_snorm_2x16
:
1192 case nir_op_unpack_snorm_4x8
:
1193 case nir_op_unpack_unorm_2x16
:
1194 case nir_op_unpack_unorm_4x8
:
1195 case nir_op_unpack_half_2x16
:
1196 case nir_op_pack_half_2x16
:
1197 unreachable("not reached: should be handled by lower_packing_builtins");
1199 case nir_op_unpack_half_2x16_split_x
:
1200 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1201 inst
->saturate
= instr
->dest
.saturate
;
1203 case nir_op_unpack_half_2x16_split_y
:
1204 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1205 inst
->saturate
= instr
->dest
.saturate
;
1208 case nir_op_pack_64_2x32_split
:
1209 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1212 case nir_op_unpack_64_2x32_split_x
:
1213 case nir_op_unpack_64_2x32_split_y
: {
1214 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1215 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1217 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1222 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1223 inst
->saturate
= instr
->dest
.saturate
;
1226 case nir_op_bitfield_reverse
:
1227 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1228 bld
.BFREV(result
, op
[0]);
1231 case nir_op_bit_count
:
1232 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1233 bld
.CBIT(result
, op
[0]);
1236 case nir_op_ufind_msb
: {
1237 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1238 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1242 case nir_op_ifind_msb
: {
1243 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1245 if (devinfo
->gen
< 7) {
1246 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1248 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1250 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1251 * count from the LSB side. If FBH didn't return an error
1252 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1253 * count into an LSB count.
1255 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1257 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1258 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1259 inst
->src
[0].negate
= true;
1264 case nir_op_find_lsb
:
1265 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1267 if (devinfo
->gen
< 7) {
1268 fs_reg temp
= vgrf(glsl_type::int_type
);
1270 /* (x & -x) generates a value that consists of only the LSB of x.
1271 * For all powers of 2, findMSB(y) == findLSB(y).
1273 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1274 fs_reg negated_src
= src
;
1276 /* One must be negated, and the other must be non-negated. It
1277 * doesn't matter which is which.
1279 negated_src
.negate
= true;
1282 bld
.AND(temp
, src
, negated_src
);
1283 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1285 bld
.FBL(result
, op
[0]);
1289 case nir_op_ubitfield_extract
:
1290 case nir_op_ibitfield_extract
:
1291 unreachable("should have been lowered");
1294 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1295 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1298 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1299 bld
.BFI1(result
, op
[0], op
[1]);
1302 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1303 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1306 case nir_op_bitfield_insert
:
1307 unreachable("not reached: should have been lowered");
1312 fs_reg shift_count
= op
[1];
1314 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1315 if (op
[1].file
== VGRF
&&
1316 (result
.type
== BRW_REGISTER_TYPE_Q
||
1317 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1318 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1319 BRW_REGISTER_TYPE_UD
);
1320 shift_count
.stride
= 2;
1321 bld
.MOV(shift_count
, op
[1]);
1325 switch (instr
->op
) {
1327 bld
.SHL(result
, op
[0], shift_count
);
1330 bld
.ASR(result
, op
[0], shift_count
);
1333 bld
.SHR(result
, op
[0], shift_count
);
1336 unreachable("not reached");
1341 case nir_op_pack_half_2x16_split
:
1342 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1346 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1347 inst
->saturate
= instr
->dest
.saturate
;
1351 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1352 inst
->saturate
= instr
->dest
.saturate
;
1356 if (optimize_frontfacing_ternary(instr
, result
))
1359 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1360 inst
= bld
.SEL(result
, op
[1], op
[2]);
1361 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1364 case nir_op_extract_u8
:
1365 case nir_op_extract_i8
: {
1366 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1367 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1368 assert(byte
!= NULL
);
1369 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1373 case nir_op_extract_u16
:
1374 case nir_op_extract_i16
: {
1375 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1376 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1377 assert(word
!= NULL
);
1378 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1383 unreachable("unhandled instruction");
1386 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1387 * to sign extend the low bit to 0/~0
1389 if (devinfo
->gen
<= 5 &&
1390 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1391 fs_reg masked
= vgrf(glsl_type::int_type
);
1392 bld
.AND(masked
, result
, brw_imm_d(1));
1393 masked
.negate
= true;
1394 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1399 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1400 nir_load_const_instr
*instr
)
1402 const brw_reg_type reg_type
=
1403 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1404 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1406 switch (instr
->def
.bit_size
) {
1408 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1409 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1413 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1414 bld
.MOV(offset(reg
, bld
, i
),
1415 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1419 unreachable("Invalid bit size");
1422 nir_ssa_values
[instr
->def
.index
] = reg
;
1426 fs_visitor::get_nir_src(const nir_src
&src
)
1430 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1431 const brw_reg_type reg_type
=
1432 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1433 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1435 reg
= nir_ssa_values
[src
.ssa
->index
];
1438 /* We don't handle indirects on locals */
1439 assert(src
.reg
.indirect
== NULL
);
1440 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1441 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1444 /* to avoid floating-point denorm flushing problems, set the type by
1445 * default to D - instructions that need floating point semantics will set
1446 * this to F if they need to
1448 return retype(reg
, BRW_REGISTER_TYPE_D
);
1452 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1455 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1457 nir_const_value
*val
= nir_src_as_const_value(src
);
1458 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1462 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1465 const brw_reg_type reg_type
=
1466 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1467 nir_ssa_values
[dest
.ssa
.index
] =
1468 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1469 return nir_ssa_values
[dest
.ssa
.index
];
1471 /* We don't handle indirects on locals */
1472 assert(dest
.reg
.indirect
== NULL
);
1473 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1474 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1479 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1481 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1482 BRW_REGISTER_TYPE_UD
);
1484 unsigned indirect_max
= 0;
1486 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1487 tail
= tail
->child
) {
1488 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1489 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1490 const unsigned size
= glsl_get_length(tail
->type
);
1491 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1492 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1493 image
= offset(image
, bld
, base
* element_size
);
1495 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1496 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1498 /* Accessing an invalid surface index with the dataport can result
1499 * in a hang. According to the spec "if the index used to
1500 * select an individual element is negative or greater than or
1501 * equal to the size of the array, the results of the operation
1502 * are undefined but may not lead to termination" -- which is one
1503 * of the possible outcomes of the hang. Clamp the index to
1504 * prevent access outside of the array bounds.
1506 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1507 BRW_REGISTER_TYPE_UD
),
1508 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1510 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1512 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1513 if (indirect
.file
== BAD_FILE
) {
1516 bld
.ADD(indirect
, indirect
, tmp
);
1521 if (indirect
.file
== BAD_FILE
) {
1524 /* Emit a pile of MOVs to load the uniform into a temporary. The
1525 * dead-code elimination pass will get rid of what we don't use.
1527 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1528 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1529 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1530 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1531 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1538 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1541 for (unsigned i
= 0; i
< 4; i
++) {
1542 if (!((wr_mask
>> i
) & 1))
1545 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1546 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1547 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1548 if (new_inst
->src
[j
].file
== VGRF
)
1549 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1556 * Get the matching channel register datatype for an image intrinsic of the
1557 * specified GLSL image type.
1560 get_image_base_type(const glsl_type
*type
)
1562 switch ((glsl_base_type
)type
->sampled_type
) {
1563 case GLSL_TYPE_UINT
:
1564 return BRW_REGISTER_TYPE_UD
;
1566 return BRW_REGISTER_TYPE_D
;
1567 case GLSL_TYPE_FLOAT
:
1568 return BRW_REGISTER_TYPE_F
;
1570 unreachable("Not reached.");
1575 * Get the appropriate atomic op for an image atomic intrinsic.
1578 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1581 case nir_intrinsic_image_atomic_add
:
1583 case nir_intrinsic_image_atomic_min
:
1584 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1585 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1586 case nir_intrinsic_image_atomic_max
:
1587 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1588 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1589 case nir_intrinsic_image_atomic_and
:
1591 case nir_intrinsic_image_atomic_or
:
1593 case nir_intrinsic_image_atomic_xor
:
1595 case nir_intrinsic_image_atomic_exchange
:
1597 case nir_intrinsic_image_atomic_comp_swap
:
1598 return BRW_AOP_CMPWR
;
1600 unreachable("Not reachable.");
1605 emit_pixel_interpolater_send(const fs_builder
&bld
,
1610 glsl_interp_mode interpolation
)
1612 struct brw_wm_prog_data
*wm_prog_data
=
1613 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1618 if (src
.file
== BAD_FILE
) {
1620 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1624 mlen
= 2 * bld
.dispatch_width() / 8;
1627 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1629 /* 2 floats per slot returned */
1630 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1631 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1633 wm_prog_data
->pulls_bary
= true;
1639 * Computes 1 << x, given a D/UD register containing some value x.
1642 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1644 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1646 fs_reg result
= bld
.vgrf(x
.type
, 1);
1647 fs_reg one
= bld
.vgrf(x
.type
, 1);
1649 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1650 bld
.SHL(result
, one
, x
);
1655 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1657 assert(stage
== MESA_SHADER_GEOMETRY
);
1659 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1661 if (gs_compile
->control_data_header_size_bits
== 0)
1664 /* We can only do EndPrimitive() functionality when the control data
1665 * consists of cut bits. Fortunately, the only time it isn't is when the
1666 * output type is points, in which case EndPrimitive() is a no-op.
1668 if (gs_prog_data
->control_data_format
!=
1669 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1673 /* Cut bits use one bit per vertex. */
1674 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1676 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1677 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1679 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1680 * vertex n, 0 otherwise. So all we need to do here is mark bit
1681 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1682 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1683 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1685 * Note that if EndPrimitive() is called before emitting any vertices, this
1686 * will cause us to set bit 31 of the control_data_bits register to 1.
1687 * That's fine because:
1689 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1690 * output, so the hardware will ignore cut bit 31.
1692 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1693 * last vertex, so setting cut bit 31 has no effect (since the primitive
1694 * is automatically ended when the GS terminates).
1696 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1697 * control_data_bits register to 0 when the first vertex is emitted.
1700 const fs_builder abld
= bld
.annotate("end primitive");
1702 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1703 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1704 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1705 fs_reg mask
= intexp2(abld
, prev_count
);
1706 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1707 * attention to the lower 5 bits of its second source argument, so on this
1708 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1709 * ((vertex_count - 1) % 32).
1711 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1715 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1717 assert(stage
== MESA_SHADER_GEOMETRY
);
1718 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1720 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1722 const fs_builder abld
= bld
.annotate("emit control data bits");
1723 const fs_builder fwa_bld
= bld
.exec_all();
1725 /* We use a single UD register to accumulate control data bits (32 bits
1726 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1729 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1730 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1731 * use the Channel Mask phase to enable/disable which DWord within that
1732 * group to write. (Remember, different SIMD8 channels may have emitted
1733 * different numbers of vertices, so we may need per-slot offsets.)
1735 * Channel masking presents an annoying problem: we may have to replicate
1736 * the data up to 4 times:
1738 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1740 * To avoid penalizing shaders that emit a small number of vertices, we
1741 * can avoid these sometimes: if the size of the control data header is
1742 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1743 * land in the same 128-bit group, so we can skip per-slot offsets.
1745 * Similarly, if the control data header is <= 32 bits, there is only one
1746 * DWord, so we can skip channel masks.
1748 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1750 fs_reg channel_mask
, per_slot_offset
;
1752 if (gs_compile
->control_data_header_size_bits
> 32) {
1753 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1754 channel_mask
= vgrf(glsl_type::uint_type
);
1757 if (gs_compile
->control_data_header_size_bits
> 128) {
1758 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1759 per_slot_offset
= vgrf(glsl_type::uint_type
);
1762 /* Figure out which DWord we're trying to write to using the formula:
1764 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1766 * Since bits_per_vertex is a power of two, and is known at compile
1767 * time, this can be optimized to:
1769 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1771 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1772 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1773 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1774 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1775 unsigned log2_bits_per_vertex
=
1776 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1777 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1779 if (per_slot_offset
.file
!= BAD_FILE
) {
1780 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1781 * the appropriate OWord within the control data header.
1783 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1786 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1787 * write to the appropriate DWORD within the OWORD.
1789 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1790 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1791 channel_mask
= intexp2(fwa_bld
, channel
);
1792 /* Then the channel masks need to be in bits 23:16. */
1793 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1796 /* Store the control data bits in the message payload and send it. */
1798 if (channel_mask
.file
!= BAD_FILE
)
1799 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1800 if (per_slot_offset
.file
!= BAD_FILE
)
1803 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1804 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1806 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1807 if (per_slot_offset
.file
!= BAD_FILE
)
1808 sources
[i
++] = per_slot_offset
;
1809 if (channel_mask
.file
!= BAD_FILE
)
1810 sources
[i
++] = channel_mask
;
1812 sources
[i
++] = this->control_data_bits
;
1815 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1816 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1818 /* We need to increment Global Offset by 256-bits to make room for
1819 * Broadwell's extra "Vertex Count" payload at the beginning of the
1820 * URB entry. Since this is an OWord message, Global Offset is counted
1821 * in 128-bit units, so we must set it to 2.
1823 if (gs_prog_data
->static_vertex_count
== -1)
1828 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1831 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1833 /* Note: we are calling this *before* increasing vertex_count, so
1834 * this->vertex_count == vertex_count - 1 in the formula above.
1837 /* Stream mode uses 2 bits per vertex */
1838 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1840 /* Must be a valid stream */
1841 assert(stream_id
< MAX_VERTEX_STREAMS
);
1843 /* Control data bits are initialized to 0 so we don't have to set any
1844 * bits when sending vertices to stream 0.
1849 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1851 /* reg::sid = stream_id */
1852 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1853 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1855 /* reg:shift_count = 2 * (vertex_count - 1) */
1856 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1857 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1859 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1860 * attention to the lower 5 bits of its second source argument, so on this
1861 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1862 * stream_id << ((2 * (vertex_count - 1)) % 32).
1864 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1865 abld
.SHL(mask
, sid
, shift_count
);
1866 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1870 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1873 assert(stage
== MESA_SHADER_GEOMETRY
);
1875 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1877 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1878 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1880 /* Haswell and later hardware ignores the "Render Stream Select" bits
1881 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1882 * and instead sends all primitives down the pipeline for rasterization.
1883 * If the SOL stage is enabled, "Render Stream Select" is honored and
1884 * primitives bound to non-zero streams are discarded after stream output.
1886 * Since the only purpose of primives sent to non-zero streams is to
1887 * be recorded by transform feedback, we can simply discard all geometry
1888 * bound to these streams when transform feedback is disabled.
1890 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1893 /* If we're outputting 32 control data bits or less, then we can wait
1894 * until the shader is over to output them all. Otherwise we need to
1895 * output them as we go. Now is the time to do it, since we're about to
1896 * output the vertex_count'th vertex, so it's guaranteed that the
1897 * control data bits associated with the (vertex_count - 1)th vertex are
1900 if (gs_compile
->control_data_header_size_bits
> 32) {
1901 const fs_builder abld
=
1902 bld
.annotate("emit vertex: emit control data bits");
1904 /* Only emit control data bits if we've finished accumulating a batch
1905 * of 32 bits. This is the case when:
1907 * (vertex_count * bits_per_vertex) % 32 == 0
1909 * (in other words, when the last 5 bits of vertex_count *
1910 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1911 * integer n (which is always the case, since bits_per_vertex is
1912 * always 1 or 2), this is equivalent to requiring that the last 5-n
1913 * bits of vertex_count are 0:
1915 * vertex_count & (2^(5-n) - 1) == 0
1917 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1920 * vertex_count & (32 / bits_per_vertex - 1) == 0
1922 * TODO: If vertex_count is an immediate, we could do some of this math
1923 * at compile time...
1926 abld
.AND(bld
.null_reg_d(), vertex_count
,
1927 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1928 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1930 abld
.IF(BRW_PREDICATE_NORMAL
);
1931 /* If vertex_count is 0, then no control data bits have been
1932 * accumulated yet, so we can skip emitting them.
1934 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1935 BRW_CONDITIONAL_NEQ
);
1936 abld
.IF(BRW_PREDICATE_NORMAL
);
1937 emit_gs_control_data_bits(vertex_count
);
1938 abld
.emit(BRW_OPCODE_ENDIF
);
1940 /* Reset control_data_bits to 0 so we can start accumulating a new
1943 * Note: in the case where vertex_count == 0, this neutralizes the
1944 * effect of any call to EndPrimitive() that the shader may have
1945 * made before outputting its first vertex.
1947 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1948 inst
->force_writemask_all
= true;
1949 abld
.emit(BRW_OPCODE_ENDIF
);
1952 emit_urb_writes(vertex_count
);
1954 /* In stream mode we have to set control data bits for all vertices
1955 * unless we have disabled control data bits completely (which we do
1956 * do for GL_POINTS outputs that don't use streams).
1958 if (gs_compile
->control_data_header_size_bits
> 0 &&
1959 gs_prog_data
->control_data_format
==
1960 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1961 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1966 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1967 const nir_src
&vertex_src
,
1968 unsigned base_offset
,
1969 const nir_src
&offset_src
,
1970 unsigned num_components
,
1971 unsigned first_component
)
1973 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1975 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1976 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1977 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1979 /* TODO: figure out push input layout for invocations == 1 */
1980 /* TODO: make this work with 64-bit inputs */
1981 if (gs_prog_data
->invocations
== 1 &&
1982 type_sz(dst
.type
) <= 4 &&
1983 offset_const
!= NULL
&& vertex_const
!= NULL
&&
1984 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1985 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1986 vertex_const
->u32
[0] * push_reg_count
;
1987 for (unsigned i
= 0; i
< num_components
; i
++) {
1988 bld
.MOV(offset(dst
, bld
, i
),
1989 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
1994 /* Resort to the pull model. Ensure the VUE handles are provided. */
1995 assert(gs_prog_data
->base
.include_vue_handles
);
1997 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1998 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2000 if (gs_prog_data
->invocations
== 1) {
2002 /* The vertex index is constant; just select the proper URB handle. */
2004 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2005 BRW_REGISTER_TYPE_UD
);
2007 /* The vertex index is non-constant. We need to use indirect
2008 * addressing to fetch the proper URB handle.
2010 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2011 * indicating that channel <n> should read the handle from
2012 * DWord <n>. We convert that to bytes by multiplying by 4.
2014 * Next, we convert the vertex index to bytes by multiplying
2015 * by 32 (shifting by 5), and add the two together. This is
2016 * the final indirect byte offset.
2018 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2019 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2020 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2021 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2023 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2024 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2025 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2026 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2027 /* Convert vertex_index to bytes (multiply by 32) */
2028 bld
.SHL(vertex_offset_bytes
,
2029 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2031 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2033 /* Use first_icp_handle as the base offset. There is one register
2034 * of URB handles per vertex, so inform the register allocator that
2035 * we might read up to nir->info.gs.vertices_in registers.
2037 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2038 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2039 fs_reg(icp_offset_bytes
),
2040 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2043 assert(gs_prog_data
->invocations
> 1);
2046 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2048 retype(brw_vec1_grf(first_icp_handle
+
2049 vertex_const
->i32
[0] / 8,
2050 vertex_const
->i32
[0] % 8),
2051 BRW_REGISTER_TYPE_UD
));
2053 /* The vertex index is non-constant. We need to use indirect
2054 * addressing to fetch the proper URB handle.
2057 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2059 /* Convert vertex_index to bytes (multiply by 4) */
2060 bld
.SHL(icp_offset_bytes
,
2061 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2064 /* Use first_icp_handle as the base offset. There is one DWord
2065 * of URB handles per vertex, so inform the register allocator that
2066 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2068 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2069 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2070 fs_reg(icp_offset_bytes
),
2071 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2078 fs_reg tmp_dst
= dst
;
2079 fs_reg indirect_offset
= get_nir_src(offset_src
);
2080 unsigned num_iterations
= 1;
2081 unsigned orig_num_components
= num_components
;
2083 if (type_sz(dst
.type
) == 8) {
2084 if (num_components
> 2) {
2088 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2090 first_component
= first_component
/ 2;
2093 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2095 /* Constant indexing - use global offset. */
2096 if (first_component
!= 0) {
2097 unsigned read_components
= num_components
+ first_component
;
2098 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2099 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2100 inst
->size_written
= read_components
*
2101 tmp
.component_size(inst
->exec_size
);
2102 for (unsigned i
= 0; i
< num_components
; i
++) {
2103 bld
.MOV(offset(tmp_dst
, bld
, i
),
2104 offset(tmp
, bld
, i
+ first_component
));
2107 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2109 inst
->size_written
= num_components
*
2110 tmp_dst
.component_size(inst
->exec_size
);
2112 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2115 /* Indirect indexing - use per-slot offsets as well. */
2116 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2117 unsigned read_components
= num_components
+ first_component
;
2118 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2119 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2120 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2121 if (first_component
!= 0) {
2122 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2124 inst
->size_written
= read_components
*
2125 tmp
.component_size(inst
->exec_size
);
2126 for (unsigned i
= 0; i
< num_components
; i
++) {
2127 bld
.MOV(offset(tmp_dst
, bld
, i
),
2128 offset(tmp
, bld
, i
+ first_component
));
2131 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2133 inst
->size_written
= num_components
*
2134 tmp_dst
.component_size(inst
->exec_size
);
2136 inst
->offset
= base_offset
;
2140 if (type_sz(dst
.type
) == 8) {
2141 shuffle_32bit_load_result_to_64bit_data(
2142 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2144 for (unsigned c
= 0; c
< num_components
; c
++)
2145 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2148 if (num_iterations
> 1) {
2149 num_components
= orig_num_components
- 2;
2153 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2154 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2155 indirect_offset
= new_indirect
;
2162 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2164 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2165 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2168 /* The only constant offset we should find is 0. brw_nir.c's
2169 * add_const_offset_to_base() will fold other constant offsets
2170 * into instr->const_index[0].
2172 assert(const_value
->u32
[0] == 0);
2176 return get_nir_src(*offset_src
);
2180 do_untyped_vector_read(const fs_builder
&bld
,
2182 const fs_reg surf_index
,
2183 const fs_reg offset_reg
,
2184 unsigned num_components
)
2186 if (type_sz(dest
.type
) == 4) {
2187 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2190 BRW_PREDICATE_NONE
);
2191 read_result
.type
= dest
.type
;
2192 for (unsigned i
= 0; i
< num_components
; i
++)
2193 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2194 } else if (type_sz(dest
.type
) == 8) {
2195 /* Reading a dvec, so we need to:
2197 * 1. Multiply num_components by 2, to account for the fact that we
2198 * need to read 64-bit components.
2199 * 2. Shuffle the result of the load to form valid 64-bit elements
2200 * 3. Emit a second load (for components z/w) if needed.
2202 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2203 bld
.MOV(read_offset
, offset_reg
);
2205 int iters
= num_components
<= 2 ? 1 : 2;
2207 /* Load the dvec, the first iteration loads components x/y, the second
2208 * iteration, if needed, loads components z/w
2210 for (int it
= 0; it
< iters
; it
++) {
2211 /* Compute number of components to read in this iteration */
2212 int iter_components
= MIN2(2, num_components
);
2213 num_components
-= iter_components
;
2215 /* Read. Since this message reads 32-bit components, we need to
2216 * read twice as many components.
2218 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2220 iter_components
* 2,
2221 BRW_PREDICATE_NONE
);
2223 /* Shuffle the 32-bit load result into valid 64-bit data */
2224 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2225 shuffle_32bit_load_result_to_64bit_data(
2226 bld
, packed_result
, read_result
, iter_components
);
2228 /* Move each component to its destination */
2229 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2230 for (int c
= 0; c
< iter_components
; c
++) {
2231 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2232 offset(packed_result
, bld
, c
));
2235 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2238 unreachable("Unsupported type");
2243 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2244 nir_intrinsic_instr
*instr
)
2246 assert(stage
== MESA_SHADER_VERTEX
);
2249 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2250 dest
= get_nir_dest(instr
->dest
);
2252 switch (instr
->intrinsic
) {
2253 case nir_intrinsic_load_vertex_id
:
2254 unreachable("should be lowered by lower_vertex_id()");
2256 case nir_intrinsic_load_vertex_id_zero_base
:
2257 case nir_intrinsic_load_base_vertex
:
2258 case nir_intrinsic_load_instance_id
:
2259 case nir_intrinsic_load_base_instance
:
2260 case nir_intrinsic_load_draw_id
: {
2261 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2262 fs_reg val
= nir_system_values
[sv
];
2263 assert(val
.file
!= BAD_FILE
);
2264 dest
.type
= val
.type
;
2269 case nir_intrinsic_load_input
: {
2270 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2271 unsigned first_component
= nir_intrinsic_component(instr
);
2272 unsigned num_components
= instr
->num_components
;
2273 enum brw_reg_type type
= dest
.type
;
2275 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2276 assert(const_offset
&& "Indirect input loads not allowed");
2277 src
= offset(src
, bld
, const_offset
->u32
[0]);
2279 for (unsigned j
= 0; j
< num_components
; j
++) {
2280 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2283 if (type
== BRW_REGISTER_TYPE_DF
) {
2284 /* Once the double vector is read, set again its original register
2285 * type to continue with normal execution.
2287 src
= retype(src
, type
);
2288 dest
= retype(dest
, type
);
2291 if (type_sz(src
.type
) == 8) {
2292 shuffle_32bit_load_result_to_64bit_data(bld
,
2294 retype(dest
, BRW_REGISTER_TYPE_F
),
2295 instr
->num_components
);
2301 nir_emit_intrinsic(bld
, instr
);
2307 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2308 nir_intrinsic_instr
*instr
)
2310 assert(stage
== MESA_SHADER_TESS_CTRL
);
2311 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2312 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2315 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2316 dst
= get_nir_dest(instr
->dest
);
2318 switch (instr
->intrinsic
) {
2319 case nir_intrinsic_load_primitive_id
:
2320 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2322 case nir_intrinsic_load_invocation_id
:
2323 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2325 case nir_intrinsic_load_patch_vertices_in
:
2326 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2327 brw_imm_d(tcs_key
->input_vertices
));
2330 case nir_intrinsic_barrier
: {
2331 if (tcs_prog_data
->instances
== 1)
2334 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2335 fs_reg m0_2
= component(m0
, 2);
2337 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2339 /* Zero the message header */
2340 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2342 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2343 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2344 brw_imm_ud(INTEL_MASK(16, 13)));
2346 /* Shift it up to bits 27:24. */
2347 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2349 /* Set the Barrier Count and the enable bit */
2350 chanbld
.OR(m0_2
, m0_2
,
2351 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2353 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2357 case nir_intrinsic_load_input
:
2358 unreachable("nir_lower_io should never give us these.");
2361 case nir_intrinsic_load_per_vertex_input
: {
2362 fs_reg indirect_offset
= get_indirect_offset(instr
);
2363 unsigned imm_offset
= instr
->const_index
[0];
2365 const nir_src
&vertex_src
= instr
->src
[0];
2366 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2373 /* Emit a MOV to resolve <0,1,0> regioning. */
2374 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2376 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2377 vertex_const
->i32
[0] & 7),
2378 BRW_REGISTER_TYPE_UD
));
2379 } else if (tcs_prog_data
->instances
== 1 &&
2380 vertex_src
.is_ssa
&&
2381 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2382 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2383 /* For the common case of only 1 instance, an array index of
2384 * gl_InvocationID means reading g1. Skip all the indirect work.
2386 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2388 /* The vertex index is non-constant. We need to use indirect
2389 * addressing to fetch the proper URB handle.
2391 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2393 /* Each ICP handle is a single DWord (4 bytes) */
2394 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2395 bld
.SHL(vertex_offset_bytes
,
2396 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2399 /* Start at g1. We might read up to 4 registers. */
2400 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2401 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2402 brw_imm_ud(4 * REG_SIZE
));
2405 /* We can only read two double components with each URB read, so
2406 * we send two read messages in that case, each one loading up to
2407 * two double components.
2409 unsigned num_iterations
= 1;
2410 unsigned num_components
= instr
->num_components
;
2411 unsigned first_component
= nir_intrinsic_component(instr
);
2412 fs_reg orig_dst
= dst
;
2413 if (type_sz(dst
.type
) == 8) {
2414 first_component
= first_component
/ 2;
2415 if (instr
->num_components
> 2) {
2420 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2424 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2425 if (indirect_offset
.file
== BAD_FILE
) {
2426 /* Constant indexing - use global offset. */
2427 if (first_component
!= 0) {
2428 unsigned read_components
= num_components
+ first_component
;
2429 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2430 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2431 for (unsigned i
= 0; i
< num_components
; i
++) {
2432 bld
.MOV(offset(dst
, bld
, i
),
2433 offset(tmp
, bld
, i
+ first_component
));
2436 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2438 inst
->offset
= imm_offset
;
2441 /* Indirect indexing - use per-slot offsets as well. */
2442 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2443 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2444 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2445 if (first_component
!= 0) {
2446 unsigned read_components
= num_components
+ first_component
;
2447 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2448 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2450 for (unsigned i
= 0; i
< num_components
; i
++) {
2451 bld
.MOV(offset(dst
, bld
, i
),
2452 offset(tmp
, bld
, i
+ first_component
));
2455 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2458 inst
->offset
= imm_offset
;
2461 inst
->size_written
= (num_components
+ first_component
) *
2462 inst
->dst
.component_size(inst
->exec_size
);
2464 /* If we are reading 64-bit data using 32-bit read messages we need
2465 * build proper 64-bit data elements by shuffling the low and high
2466 * 32-bit components around like we do for other things like UBOs
2469 if (type_sz(dst
.type
) == 8) {
2470 shuffle_32bit_load_result_to_64bit_data(
2471 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2473 for (unsigned c
= 0; c
< num_components
; c
++) {
2474 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2475 offset(dst
, bld
, c
));
2479 /* Copy the temporary to the destination to deal with writemasking.
2481 * Also attempt to deal with gl_PointSize being in the .w component.
2483 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2484 assert(type_sz(dst
.type
) < 8);
2485 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2486 inst
->size_written
= 4 * REG_SIZE
;
2487 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2490 /* If we are loading double data and we need a second read message
2491 * adjust the write offset
2493 if (num_iterations
> 1) {
2494 num_components
= instr
->num_components
- 2;
2501 case nir_intrinsic_load_output
:
2502 case nir_intrinsic_load_per_vertex_output
: {
2503 fs_reg indirect_offset
= get_indirect_offset(instr
);
2504 unsigned imm_offset
= instr
->const_index
[0];
2505 unsigned first_component
= nir_intrinsic_component(instr
);
2508 if (indirect_offset
.file
== BAD_FILE
) {
2509 /* Replicate the patch handle to all enabled channels */
2510 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2511 bld
.MOV(patch_handle
,
2512 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2515 if (first_component
!= 0) {
2516 unsigned read_components
=
2517 instr
->num_components
+ first_component
;
2518 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2519 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2521 inst
->size_written
= read_components
* REG_SIZE
;
2522 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2523 bld
.MOV(offset(dst
, bld
, i
),
2524 offset(tmp
, bld
, i
+ first_component
));
2527 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2529 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2531 inst
->offset
= imm_offset
;
2535 /* Indirect indexing - use per-slot offsets as well. */
2536 const fs_reg srcs
[] = {
2537 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2540 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2541 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2542 if (first_component
!= 0) {
2543 unsigned read_components
=
2544 instr
->num_components
+ first_component
;
2545 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2546 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2548 inst
->size_written
= read_components
* REG_SIZE
;
2549 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2550 bld
.MOV(offset(dst
, bld
, i
),
2551 offset(tmp
, bld
, i
+ first_component
));
2554 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2556 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2558 inst
->offset
= imm_offset
;
2564 case nir_intrinsic_store_output
:
2565 case nir_intrinsic_store_per_vertex_output
: {
2566 fs_reg value
= get_nir_src(instr
->src
[0]);
2567 bool is_64bit
= (instr
->src
[0].is_ssa
?
2568 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2569 fs_reg indirect_offset
= get_indirect_offset(instr
);
2570 unsigned imm_offset
= instr
->const_index
[0];
2571 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2572 unsigned mask
= instr
->const_index
[1];
2573 unsigned header_regs
= 0;
2575 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2577 if (indirect_offset
.file
!= BAD_FILE
) {
2578 srcs
[header_regs
++] = indirect_offset
;
2584 unsigned num_components
= util_last_bit(mask
);
2587 /* We can only pack two 64-bit components in a single message, so send
2588 * 2 messages if we have more components
2590 unsigned num_iterations
= 1;
2591 unsigned iter_components
= num_components
;
2592 unsigned first_component
= nir_intrinsic_component(instr
);
2594 first_component
= first_component
/ 2;
2595 if (instr
->num_components
> 2) {
2597 iter_components
= 2;
2601 /* 64-bit data needs to me shuffled before we can write it to the URB.
2602 * We will use this temporary to shuffle the components in each
2606 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2608 mask
= mask
<< first_component
;
2610 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2611 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2612 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2613 opcode
= indirect_offset
.file
!= BAD_FILE
?
2614 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2615 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2616 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2617 /* Expand the 64-bit mask to 32-bit channels. We only handle
2618 * two channels in each iteration, so we only care about X/Y.
2620 unsigned mask32
= 0;
2621 if (mask
& WRITEMASK_X
)
2622 mask32
|= WRITEMASK_XY
;
2623 if (mask
& WRITEMASK_Y
)
2624 mask32
|= WRITEMASK_ZW
;
2626 /* If the mask does not include any of the channels X or Y there
2627 * is nothing to do in this iteration. Move on to the next couple
2628 * of 64-bit channels.
2636 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2637 opcode
= indirect_offset
.file
!= BAD_FILE
?
2638 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2639 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2641 opcode
= indirect_offset
.file
!= BAD_FILE
?
2642 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2643 SHADER_OPCODE_URB_WRITE_SIMD8
;
2646 for (unsigned i
= 0; i
< iter_components
; i
++) {
2647 if (!(mask
& (1 << (i
+ first_component
))))
2651 srcs
[header_regs
+ i
+ first_component
] =
2652 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2654 /* We need to shuffle the 64-bit data to match the layout
2655 * expected by our 32-bit URB write messages. We use a temporary
2658 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2659 shuffle_64bit_data_for_32bit_write(bld
,
2660 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2661 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2664 /* Now copy the data to the destination */
2665 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2666 unsigned idx
= 2 * i
;
2667 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2668 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2669 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2670 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2671 offset(dest
, bld
, 1);
2676 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2677 (is_64bit
? 2 * first_component
: first_component
);
2679 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2680 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2682 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2683 inst
->offset
= imm_offset
;
2686 /* If this is a 64-bit attribute, select the next two 64-bit channels
2687 * to be handled in the next iteration.
2698 nir_emit_intrinsic(bld
, instr
);
2704 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2705 nir_intrinsic_instr
*instr
)
2707 assert(stage
== MESA_SHADER_TESS_EVAL
);
2708 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2711 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2712 dest
= get_nir_dest(instr
->dest
);
2714 switch (instr
->intrinsic
) {
2715 case nir_intrinsic_load_primitive_id
:
2716 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2718 case nir_intrinsic_load_tess_coord
:
2719 /* gl_TessCoord is part of the payload in g1-3 */
2720 for (unsigned i
= 0; i
< 3; i
++) {
2721 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2725 case nir_intrinsic_load_input
:
2726 case nir_intrinsic_load_per_vertex_input
: {
2727 fs_reg indirect_offset
= get_indirect_offset(instr
);
2728 unsigned imm_offset
= instr
->const_index
[0];
2729 unsigned first_component
= nir_intrinsic_component(instr
);
2731 if (type_sz(dest
.type
) == 8) {
2732 first_component
= first_component
/ 2;
2736 if (indirect_offset
.file
== BAD_FILE
) {
2737 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2738 * which is 16 registers (since each holds 2 vec4 slots).
2740 unsigned slot_count
= 1;
2741 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2744 const unsigned max_push_slots
= 32;
2745 if (imm_offset
+ slot_count
<= max_push_slots
) {
2746 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2747 for (int i
= 0; i
< instr
->num_components
; i
++) {
2748 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2749 i
+ first_component
;
2750 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2753 tes_prog_data
->base
.urb_read_length
=
2754 MAX2(tes_prog_data
->base
.urb_read_length
,
2755 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2757 /* Replicate the patch handle to all enabled channels */
2758 const fs_reg srcs
[] = {
2759 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2761 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2762 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2764 if (first_component
!= 0) {
2765 unsigned read_components
=
2766 instr
->num_components
+ first_component
;
2767 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2768 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2770 inst
->size_written
= read_components
* REG_SIZE
;
2771 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2772 bld
.MOV(offset(dest
, bld
, i
),
2773 offset(tmp
, bld
, i
+ first_component
));
2776 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2778 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2781 inst
->offset
= imm_offset
;
2784 /* Indirect indexing - use per-slot offsets as well. */
2786 /* We can only read two double components with each URB read, so
2787 * we send two read messages in that case, each one loading up to
2788 * two double components.
2790 unsigned num_iterations
= 1;
2791 unsigned num_components
= instr
->num_components
;
2792 fs_reg orig_dest
= dest
;
2793 if (type_sz(dest
.type
) == 8) {
2794 if (instr
->num_components
> 2) {
2798 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2802 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2803 const fs_reg srcs
[] = {
2804 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2807 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2808 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2810 if (first_component
!= 0) {
2811 unsigned read_components
=
2812 num_components
+ first_component
;
2813 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2814 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2816 for (unsigned i
= 0; i
< num_components
; i
++) {
2817 bld
.MOV(offset(dest
, bld
, i
),
2818 offset(tmp
, bld
, i
+ first_component
));
2821 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2825 inst
->offset
= imm_offset
;
2826 inst
->size_written
= (num_components
+ first_component
) *
2827 inst
->dst
.component_size(inst
->exec_size
);
2829 /* If we are reading 64-bit data using 32-bit read messages we need
2830 * build proper 64-bit data elements by shuffling the low and high
2831 * 32-bit components around like we do for other things like UBOs
2834 if (type_sz(dest
.type
) == 8) {
2835 shuffle_32bit_load_result_to_64bit_data(
2836 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2838 for (unsigned c
= 0; c
< num_components
; c
++) {
2839 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2840 offset(dest
, bld
, c
));
2844 /* If we are loading double data and we need a second read message
2847 if (num_iterations
> 1) {
2848 num_components
= instr
->num_components
- 2;
2856 nir_emit_intrinsic(bld
, instr
);
2862 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2863 nir_intrinsic_instr
*instr
)
2865 assert(stage
== MESA_SHADER_GEOMETRY
);
2866 fs_reg indirect_offset
;
2869 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2870 dest
= get_nir_dest(instr
->dest
);
2872 switch (instr
->intrinsic
) {
2873 case nir_intrinsic_load_primitive_id
:
2874 assert(stage
== MESA_SHADER_GEOMETRY
);
2875 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2876 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2877 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2880 case nir_intrinsic_load_input
:
2881 unreachable("load_input intrinsics are invalid for the GS stage");
2883 case nir_intrinsic_load_per_vertex_input
:
2884 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2885 instr
->src
[1], instr
->num_components
,
2886 nir_intrinsic_component(instr
));
2889 case nir_intrinsic_emit_vertex_with_counter
:
2890 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2893 case nir_intrinsic_end_primitive_with_counter
:
2894 emit_gs_end_primitive(instr
->src
[0]);
2897 case nir_intrinsic_set_vertex_count
:
2898 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2901 case nir_intrinsic_load_invocation_id
: {
2902 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2903 assert(val
.file
!= BAD_FILE
);
2904 dest
.type
= val
.type
;
2910 nir_emit_intrinsic(bld
, instr
);
2916 * Fetch the current render target layer index.
2919 fetch_render_target_array_index(const fs_builder
&bld
)
2921 if (bld
.shader
->devinfo
->gen
>= 6) {
2922 /* The render target array index is provided in the thread payload as
2923 * bits 26:16 of r0.0.
2925 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2926 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2930 /* Pre-SNB we only ever render into the first layer of the framebuffer
2931 * since layered rendering is not implemented.
2933 return brw_imm_ud(0);
2938 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2939 * framebuffer at the current fragment coordinates and sample index.
2942 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2945 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2947 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2948 const brw_wm_prog_key
*wm_key
=
2949 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2950 assert(!wm_key
->coherent_fb_fetch
);
2951 const struct brw_wm_prog_data
*wm_prog_data
=
2952 brw_wm_prog_data(stage_prog_data
);
2954 /* Calculate the surface index relative to the start of the texture binding
2955 * table block, since that's what the texturing messages expect.
2957 const unsigned surface
= target
+
2958 wm_prog_data
->binding_table
.render_target_read_start
-
2959 wm_prog_data
->base
.binding_table
.texture_start
;
2961 brw_mark_surface_used(
2962 bld
.shader
->stage_prog_data
,
2963 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2965 /* Calculate the fragment coordinates. */
2966 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2967 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2968 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2969 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2971 /* Calculate the sample index and MCS payload when multisampling. Luckily
2972 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2973 * shouldn't be necessary to recompile based on whether the framebuffer is
2976 if (wm_key
->multisample_fbo
&&
2977 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2978 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2980 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2981 const fs_reg mcs
= wm_key
->multisample_fbo
?
2982 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2984 /* Use either a normal or a CMS texel fetch message depending on whether
2985 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2986 * message just in case the framebuffer uses 16x multisampling, it should
2987 * be equivalent to the normal CMS fetch for lower multisampling modes.
2989 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2990 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2991 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2993 /* Emit the instruction. */
2994 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
2996 brw_imm_ud(surface
), brw_imm_ud(0),
2997 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
2998 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3000 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3001 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3007 * Actual coherent framebuffer read implemented using the native render target
3008 * read message. Requires SKL+.
3011 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3013 assert(bld
.shader
->devinfo
->gen
>= 9);
3014 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3015 inst
->target
= target
;
3016 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3022 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3024 if (n
&& regs
[0].file
!= BAD_FILE
) {
3028 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3030 for (unsigned i
= 0; i
< n
; i
++)
3038 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3040 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3041 const brw_wm_prog_key
*const key
=
3042 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3043 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3044 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3046 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3047 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3049 else if (l
== FRAG_RESULT_COLOR
)
3050 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3051 MAX2(key
->nr_color_regions
, 1));
3053 else if (l
== FRAG_RESULT_DEPTH
)
3054 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3056 else if (l
== FRAG_RESULT_STENCIL
)
3057 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3059 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3060 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3062 else if (l
>= FRAG_RESULT_DATA0
&&
3063 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3064 return alloc_temporary(v
->bld
, 4,
3065 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3068 unreachable("Invalid location");
3072 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3073 nir_intrinsic_instr
*instr
)
3075 assert(stage
== MESA_SHADER_FRAGMENT
);
3078 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3079 dest
= get_nir_dest(instr
->dest
);
3081 switch (instr
->intrinsic
) {
3082 case nir_intrinsic_load_front_face
:
3083 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3084 *emit_frontfacing_interpolation());
3087 case nir_intrinsic_load_sample_pos
: {
3088 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3089 assert(sample_pos
.file
!= BAD_FILE
);
3090 dest
.type
= sample_pos
.type
;
3091 bld
.MOV(dest
, sample_pos
);
3092 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3096 case nir_intrinsic_load_layer_id
:
3097 dest
.type
= BRW_REGISTER_TYPE_UD
;
3098 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3101 case nir_intrinsic_load_helper_invocation
:
3102 case nir_intrinsic_load_sample_mask_in
:
3103 case nir_intrinsic_load_sample_id
: {
3104 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3105 fs_reg val
= nir_system_values
[sv
];
3106 assert(val
.file
!= BAD_FILE
);
3107 dest
.type
= val
.type
;
3112 case nir_intrinsic_store_output
: {
3113 const fs_reg src
= get_nir_src(instr
->src
[0]);
3114 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3115 assert(const_offset
&& "Indirect output stores not allowed");
3116 const unsigned location
= nir_intrinsic_base(instr
) +
3117 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3118 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3121 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3122 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3123 offset(src
, bld
, j
));
3128 case nir_intrinsic_load_output
: {
3129 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3130 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3131 assert(l
>= FRAG_RESULT_DATA0
);
3132 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3133 assert(const_offset
&& "Indirect output loads not allowed");
3134 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3135 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3137 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3138 emit_coherent_fb_read(bld
, tmp
, target
);
3140 emit_non_coherent_fb_read(bld
, tmp
, target
);
3142 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3143 bld
.MOV(offset(dest
, bld
, j
),
3144 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3150 case nir_intrinsic_discard
:
3151 case nir_intrinsic_discard_if
: {
3152 /* We track our discarded pixels in f0.1. By predicating on it, we can
3153 * update just the flag bits that aren't yet discarded. If there's no
3154 * condition, we emit a CMP of g0 != g0, so all currently executing
3155 * channels will get turned off.
3158 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3159 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3160 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3162 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3163 BRW_REGISTER_TYPE_UW
));
3164 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3166 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3167 cmp
->flag_subreg
= 1;
3169 if (devinfo
->gen
>= 6) {
3170 emit_discard_jump();
3175 case nir_intrinsic_load_input
: {
3176 /* load_input is only used for flat inputs */
3177 unsigned base
= nir_intrinsic_base(instr
);
3178 unsigned component
= nir_intrinsic_component(instr
);
3179 unsigned num_components
= instr
->num_components
;
3180 enum brw_reg_type type
= dest
.type
;
3182 /* Special case fields in the VUE header */
3183 if (base
== VARYING_SLOT_LAYER
)
3185 else if (base
== VARYING_SLOT_VIEWPORT
)
3188 if (nir_dest_bit_size(instr
->dest
) == 64) {
3189 /* const_index is in 32-bit type size units that could not be aligned
3190 * with DF. We need to read the double vector as if it was a float
3191 * vector of twice the number of components to fetch the right data.
3193 type
= BRW_REGISTER_TYPE_F
;
3194 num_components
*= 2;
3197 for (unsigned int i
= 0; i
< num_components
; i
++) {
3198 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3199 interp
= suboffset(interp
, 3);
3200 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3201 retype(fs_reg(interp
), type
));
3204 if (nir_dest_bit_size(instr
->dest
) == 64) {
3205 shuffle_32bit_load_result_to_64bit_data(bld
,
3208 instr
->num_components
);
3213 case nir_intrinsic_load_barycentric_pixel
:
3214 case nir_intrinsic_load_barycentric_centroid
:
3215 case nir_intrinsic_load_barycentric_sample
:
3216 /* Do nothing - load_interpolated_input handling will handle it later. */
3219 case nir_intrinsic_load_barycentric_at_sample
: {
3220 const glsl_interp_mode interpolation
=
3221 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3223 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3226 unsigned msg_data
= const_sample
->i32
[0] << 4;
3228 emit_pixel_interpolater_send(bld
,
3229 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3232 brw_imm_ud(msg_data
),
3235 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3236 BRW_REGISTER_TYPE_UD
);
3238 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3239 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3240 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3241 bld
.exec_all().group(1, 0)
3242 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3243 emit_pixel_interpolater_send(bld
,
3244 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3250 /* Make a loop that sends a message to the pixel interpolater
3251 * for the sample number in each live channel. If there are
3252 * multiple channels with the same sample number then these
3253 * will be handled simultaneously with a single interation of
3256 bld
.emit(BRW_OPCODE_DO
);
3258 /* Get the next live sample number into sample_id_reg */
3259 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3261 /* Set the flag register so that we can perform the send
3262 * message on all channels that have the same sample number
3264 bld
.CMP(bld
.null_reg_ud(),
3265 sample_src
, sample_id
,
3266 BRW_CONDITIONAL_EQ
);
3267 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3268 bld
.exec_all().group(1, 0)
3269 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3271 emit_pixel_interpolater_send(bld
,
3272 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3277 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3279 /* Continue the loop if there are any live channels left */
3280 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3282 bld
.emit(BRW_OPCODE_WHILE
));
3288 case nir_intrinsic_load_barycentric_at_offset
: {
3289 const glsl_interp_mode interpolation
=
3290 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3292 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3295 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3296 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3298 emit_pixel_interpolater_send(bld
,
3299 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3302 brw_imm_ud(off_x
| (off_y
<< 4)),
3305 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3306 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3307 BRW_REGISTER_TYPE_F
);
3308 for (int i
= 0; i
< 2; i
++) {
3309 fs_reg temp
= vgrf(glsl_type::float_type
);
3310 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3311 fs_reg itemp
= vgrf(glsl_type::int_type
);
3313 bld
.MOV(itemp
, temp
);
3315 /* Clamp the upper end of the range to +7/16.
3316 * ARB_gpu_shader5 requires that we support a maximum offset
3317 * of +0.5, which isn't representable in a S0.4 value -- if
3318 * we didn't clamp it, we'd end up with -8/16, which is the
3319 * opposite of what the shader author wanted.
3321 * This is legal due to ARB_gpu_shader5's quantization
3324 * "Not all values of <offset> may be supported; x and y
3325 * offsets may be rounded to fixed-point values with the
3326 * number of fraction bits given by the
3327 * implementation-dependent constant
3328 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3330 set_condmod(BRW_CONDITIONAL_L
,
3331 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3334 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3335 emit_pixel_interpolater_send(bld
,
3345 case nir_intrinsic_load_interpolated_input
: {
3346 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3347 emit_fragcoord_interpolation(dest
);
3351 assert(instr
->src
[0].ssa
&&
3352 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3353 nir_intrinsic_instr
*bary_intrinsic
=
3354 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3355 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3356 enum glsl_interp_mode interp_mode
=
3357 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3360 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3361 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3362 /* Use the result of the PI message */
3363 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3365 /* Use the delta_xy values computed from the payload */
3366 enum brw_barycentric_mode bary
=
3367 brw_barycentric_mode(interp_mode
, bary_intrin
);
3369 dst_xy
= this->delta_xy
[bary
];
3372 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3374 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3375 nir_intrinsic_component(instr
) + i
));
3376 interp
.type
= BRW_REGISTER_TYPE_F
;
3377 dest
.type
= BRW_REGISTER_TYPE_F
;
3379 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3380 fs_reg tmp
= vgrf(glsl_type::float_type
);
3381 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3382 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3384 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3391 nir_emit_intrinsic(bld
, instr
);
3397 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3398 nir_intrinsic_instr
*instr
)
3400 assert(stage
== MESA_SHADER_COMPUTE
);
3401 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3404 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3405 dest
= get_nir_dest(instr
->dest
);
3407 switch (instr
->intrinsic
) {
3408 case nir_intrinsic_barrier
:
3410 cs_prog_data
->uses_barrier
= true;
3413 case nir_intrinsic_load_local_invocation_id
:
3414 case nir_intrinsic_load_work_group_id
: {
3415 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3416 fs_reg val
= nir_system_values
[sv
];
3417 assert(val
.file
!= BAD_FILE
);
3418 dest
.type
= val
.type
;
3419 for (unsigned i
= 0; i
< 3; i
++)
3420 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3424 case nir_intrinsic_load_num_work_groups
: {
3425 const unsigned surface
=
3426 cs_prog_data
->binding_table
.work_groups_start
;
3428 cs_prog_data
->uses_num_work_groups
= true;
3430 fs_reg surf_index
= brw_imm_ud(surface
);
3431 brw_mark_surface_used(prog_data
, surface
);
3433 /* Read the 3 GLuint components of gl_NumWorkGroups */
3434 for (unsigned i
= 0; i
< 3; i
++) {
3435 fs_reg read_result
=
3436 emit_untyped_read(bld
, surf_index
,
3438 1 /* dims */, 1 /* size */,
3439 BRW_PREDICATE_NONE
);
3440 read_result
.type
= dest
.type
;
3441 bld
.MOV(dest
, read_result
);
3442 dest
= offset(dest
, bld
, 1);
3447 case nir_intrinsic_shared_atomic_add
:
3448 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3450 case nir_intrinsic_shared_atomic_imin
:
3451 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3453 case nir_intrinsic_shared_atomic_umin
:
3454 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3456 case nir_intrinsic_shared_atomic_imax
:
3457 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3459 case nir_intrinsic_shared_atomic_umax
:
3460 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3462 case nir_intrinsic_shared_atomic_and
:
3463 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3465 case nir_intrinsic_shared_atomic_or
:
3466 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3468 case nir_intrinsic_shared_atomic_xor
:
3469 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3471 case nir_intrinsic_shared_atomic_exchange
:
3472 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3474 case nir_intrinsic_shared_atomic_comp_swap
:
3475 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3478 case nir_intrinsic_load_shared
: {
3479 assert(devinfo
->gen
>= 7);
3481 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3483 /* Get the offset to read from */
3485 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3487 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3489 offset_reg
= vgrf(glsl_type::uint_type
);
3491 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3492 brw_imm_ud(instr
->const_index
[0]));
3495 /* Read the vector */
3496 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3497 instr
->num_components
);
3501 case nir_intrinsic_store_shared
: {
3502 assert(devinfo
->gen
>= 7);
3505 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3508 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3511 unsigned writemask
= instr
->const_index
[1];
3513 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3514 * since the untyped writes below operate in units of 32-bits, which
3515 * means that we need to write twice as many components each time.
3516 * Also, we have to suffle 64-bit data to be in the appropriate layout
3517 * expected by our 32-bit write messages.
3519 unsigned type_size
= 4;
3520 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3523 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3524 shuffle_64bit_data_for_32bit_write(
3526 retype(tmp
, BRW_REGISTER_TYPE_F
),
3527 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3528 instr
->num_components
);
3532 unsigned type_slots
= type_size
/ 4;
3534 /* Combine groups of consecutive enabled channels in one write
3535 * message. We use ffs to find the first enabled channel and then ffs on
3536 * the bit-inverse, down-shifted writemask to determine the length of
3537 * the block of enabled bits.
3540 unsigned first_component
= ffs(writemask
) - 1;
3541 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3543 /* We can't write more than 2 64-bit components at once. Limit the
3544 * length of the write to what we can do and let the next iteration
3548 length
= MIN2(2, length
);
3551 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3553 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3554 type_size
* first_component
);
3556 offset_reg
= vgrf(glsl_type::uint_type
);
3558 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3559 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3562 emit_untyped_write(bld
, surf_index
, offset_reg
,
3563 offset(val_reg
, bld
, first_component
* type_slots
),
3564 1 /* dims */, length
* type_slots
,
3565 BRW_PREDICATE_NONE
);
3567 /* Clear the bits in the writemask that we just wrote, then try
3568 * again to see if more channels are left.
3570 writemask
&= (15 << (first_component
+ length
));
3577 nir_emit_intrinsic(bld
, instr
);
3583 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3586 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3587 dest
= get_nir_dest(instr
->dest
);
3589 switch (instr
->intrinsic
) {
3590 case nir_intrinsic_atomic_counter_inc
:
3591 case nir_intrinsic_atomic_counter_dec
:
3592 case nir_intrinsic_atomic_counter_read
:
3593 case nir_intrinsic_atomic_counter_add
:
3594 case nir_intrinsic_atomic_counter_min
:
3595 case nir_intrinsic_atomic_counter_max
:
3596 case nir_intrinsic_atomic_counter_and
:
3597 case nir_intrinsic_atomic_counter_or
:
3598 case nir_intrinsic_atomic_counter_xor
:
3599 case nir_intrinsic_atomic_counter_exchange
:
3600 case nir_intrinsic_atomic_counter_comp_swap
: {
3601 if (stage
== MESA_SHADER_FRAGMENT
&&
3602 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3603 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3605 /* Get some metadata from the image intrinsic. */
3606 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3608 /* Get the arguments of the atomic intrinsic. */
3609 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3610 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3611 instr
->const_index
[0]);
3612 const fs_reg src0
= (info
->num_srcs
>= 2
3613 ? get_nir_src(instr
->src
[1]) : fs_reg());
3614 const fs_reg src1
= (info
->num_srcs
>= 3
3615 ? get_nir_src(instr
->src
[2]) : fs_reg());
3618 assert(info
->num_srcs
<= 3);
3620 /* Emit a surface read or atomic op. */
3621 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3622 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3624 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3626 get_atomic_counter_op(instr
->intrinsic
));
3629 /* Assign the result. */
3630 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3632 /* Mark the surface as used. */
3633 brw_mark_surface_used(stage_prog_data
, surface
);
3637 case nir_intrinsic_image_load
:
3638 case nir_intrinsic_image_store
:
3639 case nir_intrinsic_image_atomic_add
:
3640 case nir_intrinsic_image_atomic_min
:
3641 case nir_intrinsic_image_atomic_max
:
3642 case nir_intrinsic_image_atomic_and
:
3643 case nir_intrinsic_image_atomic_or
:
3644 case nir_intrinsic_image_atomic_xor
:
3645 case nir_intrinsic_image_atomic_exchange
:
3646 case nir_intrinsic_image_atomic_comp_swap
: {
3647 using namespace image_access
;
3649 if (stage
== MESA_SHADER_FRAGMENT
&&
3650 instr
->intrinsic
!= nir_intrinsic_image_load
)
3651 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3653 /* Get the referenced image variable and type. */
3654 const nir_variable
*var
= instr
->variables
[0]->var
;
3655 const glsl_type
*type
= var
->type
->without_array();
3656 const brw_reg_type base_type
= get_image_base_type(type
);
3658 /* Get some metadata from the image intrinsic. */
3659 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3660 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3661 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3662 const unsigned format
= var
->data
.image
.format
;
3664 /* Get the arguments of the image intrinsic. */
3665 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3666 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3667 BRW_REGISTER_TYPE_UD
);
3668 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3669 retype(get_nir_src(instr
->src
[2]), base_type
) :
3671 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3672 retype(get_nir_src(instr
->src
[3]), base_type
) :
3676 /* Emit an image load, store or atomic op. */
3677 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3678 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3680 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3681 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3682 var
->data
.image
.write_only
? GL_NONE
: format
);
3685 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3686 surf_dims
, arr_dims
, info
->dest_components
,
3687 get_image_atomic_op(instr
->intrinsic
, type
));
3689 /* Assign the result. */
3690 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3691 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3692 offset(tmp
, bld
, c
));
3696 case nir_intrinsic_memory_barrier_atomic_counter
:
3697 case nir_intrinsic_memory_barrier_buffer
:
3698 case nir_intrinsic_memory_barrier_image
:
3699 case nir_intrinsic_memory_barrier
: {
3700 const fs_builder ubld
= bld
.group(8, 0);
3701 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3702 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3703 ->size_written
= 2 * REG_SIZE
;
3707 case nir_intrinsic_group_memory_barrier
:
3708 case nir_intrinsic_memory_barrier_shared
:
3709 /* We treat these workgroup-level barriers as no-ops. This should be
3710 * safe at present and as long as:
3712 * - Memory access instructions are not subsequently reordered by the
3713 * compiler back-end.
3715 * - All threads from a given compute shader workgroup fit within a
3716 * single subslice and therefore talk to the same HDC shared unit
3717 * what supposedly guarantees ordering and coherency between threads
3718 * from the same workgroup. This may change in the future when we
3719 * start splitting workgroups across multiple subslices.
3721 * - The context is not in fault-and-stream mode, which could cause
3722 * memory transactions (including to SLM) prior to the barrier to be
3723 * replayed after the barrier if a pagefault occurs. This shouldn't
3724 * be a problem up to and including SKL because fault-and-stream is
3725 * not usable due to hardware issues, but that's likely to change in
3730 case nir_intrinsic_shader_clock
: {
3731 /* We cannot do anything if there is an event, so ignore it for now */
3732 const fs_reg shader_clock
= get_timestamp(bld
);
3733 const fs_reg srcs
[] = { component(shader_clock
, 0),
3734 component(shader_clock
, 1) };
3735 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3739 case nir_intrinsic_image_size
: {
3740 /* Get the referenced image variable and type. */
3741 const nir_variable
*var
= instr
->variables
[0]->var
;
3742 const glsl_type
*type
= var
->type
->without_array();
3744 /* Get the size of the image. */
3745 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3746 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3748 /* For 1DArray image types, the array index is stored in the Z component.
3749 * Fix this by swizzling the Z component to the Y component.
3751 const bool is_1d_array_image
=
3752 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3753 type
->sampler_array
;
3755 /* For CubeArray images, we should count the number of cubes instead
3756 * of the number of faces. Fix it by dividing the (Z component) by 6.
3758 const bool is_cube_array_image
=
3759 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3760 type
->sampler_array
;
3762 /* Copy all the components. */
3763 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3764 if ((int)c
>= type
->coordinate_components()) {
3765 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3767 } else if (c
== 1 && is_1d_array_image
) {
3768 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3769 offset(size
, bld
, 2));
3770 } else if (c
== 2 && is_cube_array_image
) {
3771 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3772 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3773 offset(size
, bld
, c
), brw_imm_d(6));
3775 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3776 offset(size
, bld
, c
));
3783 case nir_intrinsic_image_samples
:
3784 /* The driver does not support multi-sampled images. */
3785 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3788 case nir_intrinsic_load_uniform
: {
3789 /* Offsets are in bytes but they should always be multiples of 4 */
3790 assert(instr
->const_index
[0] % 4 == 0);
3792 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3794 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3796 /* Offsets are in bytes but they should always be multiples of 4 */
3797 assert(const_offset
->u32
[0] % 4 == 0);
3798 src
.offset
= const_offset
->u32
[0];
3800 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3801 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3804 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3805 BRW_REGISTER_TYPE_UD
);
3807 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3808 * go past the end of the uniform. In order to keep the n'th
3809 * component from running past, we subtract off the size of all but
3810 * one component of the vector.
3812 assert(instr
->const_index
[1] >=
3813 instr
->num_components
* (int) type_sz(dest
.type
));
3814 unsigned read_size
= instr
->const_index
[1] -
3815 (instr
->num_components
- 1) * type_sz(dest
.type
);
3817 bool supports_64bit_indirects
=
3818 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3820 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3821 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3822 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3823 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3824 indirect
, brw_imm_ud(read_size
));
3827 const unsigned num_mov_indirects
=
3828 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3829 /* We read a little bit less per MOV INDIRECT, as they are now
3830 * 32-bits ones instead of 64-bit. Fix read_size then.
3832 const unsigned read_size_32bit
= read_size
-
3833 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3834 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3835 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3836 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3837 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3838 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3839 indirect
, brw_imm_ud(read_size_32bit
));
3847 case nir_intrinsic_load_ubo
: {
3848 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3852 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3853 const_index
->u32
[0];
3854 surf_index
= brw_imm_ud(index
);
3855 brw_mark_surface_used(prog_data
, index
);
3857 /* The block index is not a constant. Evaluate the index expression
3858 * per-channel and add the base UBO index; we have to select a value
3859 * from any live channel.
3861 surf_index
= vgrf(glsl_type::uint_type
);
3862 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3863 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3864 surf_index
= bld
.emit_uniformize(surf_index
);
3866 /* Assume this may touch any UBO. It would be nice to provide
3867 * a tighter bound, but the array information is already lowered away.
3869 brw_mark_surface_used(prog_data
,
3870 stage_prog_data
->binding_table
.ubo_start
+
3871 nir
->info
.num_ubos
- 1);
3874 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3875 if (const_offset
== NULL
) {
3876 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3877 BRW_REGISTER_TYPE_UD
);
3879 for (int i
= 0; i
< instr
->num_components
; i
++)
3880 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3881 base_offset
, i
* type_sz(dest
.type
));
3883 /* Even if we are loading doubles, a pull constant load will load
3884 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3885 * need to load a full dvec4 we will have to emit 2 loads. This is
3886 * similar to demote_pull_constants(), except that in that case we
3887 * see individual accesses to each component of the vector and then
3888 * we let CSE deal with duplicate loads. Here we see a vector access
3889 * and we have to split it if necessary.
3891 const unsigned type_size
= type_sz(dest
.type
);
3893 /* See if we've selected this as a push constant candidate */
3895 const unsigned ubo_block
= const_index
->u32
[0];
3896 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
3899 for (int i
= 0; i
< 4; i
++) {
3900 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3901 if (range
->block
== ubo_block
&&
3902 offset_256b
>= range
->start
&&
3903 offset_256b
< range
->start
+ range
->length
) {
3905 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3906 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
3911 if (push_reg
.file
!= BAD_FILE
) {
3912 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3913 bld
.MOV(offset(dest
, bld
, i
),
3914 byte_offset(push_reg
, i
* type_size
));
3920 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3921 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3922 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3924 for (unsigned c
= 0; c
< instr
->num_components
;) {
3925 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3926 /* Number of usable components in the next block-aligned load. */
3927 const unsigned count
= MIN2(instr
->num_components
- c
,
3928 (block_sz
- base
% block_sz
) / type_size
);
3930 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3931 packed_consts
, surf_index
,
3932 brw_imm_ud(base
& ~(block_sz
- 1)));
3934 const fs_reg consts
=
3935 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3938 for (unsigned d
= 0; d
< count
; d
++)
3939 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3947 case nir_intrinsic_load_ssbo
: {
3948 assert(devinfo
->gen
>= 7);
3950 nir_const_value
*const_uniform_block
=
3951 nir_src_as_const_value(instr
->src
[0]);
3954 if (const_uniform_block
) {
3955 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3956 const_uniform_block
->u32
[0];
3957 surf_index
= brw_imm_ud(index
);
3958 brw_mark_surface_used(prog_data
, index
);
3960 surf_index
= vgrf(glsl_type::uint_type
);
3961 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3962 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3964 /* Assume this may touch any UBO. It would be nice to provide
3965 * a tighter bound, but the array information is already lowered away.
3967 brw_mark_surface_used(prog_data
,
3968 stage_prog_data
->binding_table
.ssbo_start
+
3969 nir
->info
.num_ssbos
- 1);
3973 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3975 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3977 offset_reg
= get_nir_src(instr
->src
[1]);
3980 /* Read the vector */
3981 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3982 instr
->num_components
);
3987 case nir_intrinsic_store_ssbo
: {
3988 assert(devinfo
->gen
>= 7);
3990 if (stage
== MESA_SHADER_FRAGMENT
)
3991 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3995 nir_const_value
*const_uniform_block
=
3996 nir_src_as_const_value(instr
->src
[1]);
3997 if (const_uniform_block
) {
3998 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3999 const_uniform_block
->u32
[0];
4000 surf_index
= brw_imm_ud(index
);
4001 brw_mark_surface_used(prog_data
, index
);
4003 surf_index
= vgrf(glsl_type::uint_type
);
4004 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4005 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4007 brw_mark_surface_used(prog_data
,
4008 stage_prog_data
->binding_table
.ssbo_start
+
4009 nir
->info
.num_ssbos
- 1);
4013 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4016 unsigned writemask
= instr
->const_index
[0];
4018 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4019 * since the untyped writes below operate in units of 32-bits, which
4020 * means that we need to write twice as many components each time.
4021 * Also, we have to suffle 64-bit data to be in the appropriate layout
4022 * expected by our 32-bit write messages.
4024 unsigned type_size
= 4;
4025 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4028 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
4029 shuffle_64bit_data_for_32bit_write(bld
,
4030 retype(tmp
, BRW_REGISTER_TYPE_F
),
4031 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
4032 instr
->num_components
);
4036 unsigned type_slots
= type_size
/ 4;
4038 /* Combine groups of consecutive enabled channels in one write
4039 * message. We use ffs to find the first enabled channel and then ffs on
4040 * the bit-inverse, down-shifted writemask to determine the length of
4041 * the block of enabled bits.
4044 unsigned first_component
= ffs(writemask
) - 1;
4045 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4047 /* We can't write more than 2 64-bit components at once. Limit the
4048 * length of the write to what we can do and let the next iteration
4052 length
= MIN2(2, length
);
4055 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4057 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4058 type_size
* first_component
);
4060 offset_reg
= vgrf(glsl_type::uint_type
);
4062 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4063 brw_imm_ud(type_size
* first_component
));
4067 emit_untyped_write(bld
, surf_index
, offset_reg
,
4068 offset(val_reg
, bld
, first_component
* type_slots
),
4069 1 /* dims */, length
* type_slots
,
4070 BRW_PREDICATE_NONE
);
4072 /* Clear the bits in the writemask that we just wrote, then try
4073 * again to see if more channels are left.
4075 writemask
&= (15 << (first_component
+ length
));
4080 case nir_intrinsic_store_output
: {
4081 fs_reg src
= get_nir_src(instr
->src
[0]);
4083 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4084 assert(const_offset
&& "Indirect output stores not allowed");
4085 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4086 4 * const_offset
->u32
[0]), src
.type
);
4088 unsigned num_components
= instr
->num_components
;
4089 unsigned first_component
= nir_intrinsic_component(instr
);
4090 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4092 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4093 BRW_REGISTER_TYPE_F
);
4094 shuffle_64bit_data_for_32bit_write(
4095 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4096 src
= retype(tmp
, src
.type
);
4097 num_components
*= 2;
4100 for (unsigned j
= 0; j
< num_components
; j
++) {
4101 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4102 offset(src
, bld
, j
));
4107 case nir_intrinsic_ssbo_atomic_add
:
4108 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4110 case nir_intrinsic_ssbo_atomic_imin
:
4111 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4113 case nir_intrinsic_ssbo_atomic_umin
:
4114 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4116 case nir_intrinsic_ssbo_atomic_imax
:
4117 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4119 case nir_intrinsic_ssbo_atomic_umax
:
4120 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4122 case nir_intrinsic_ssbo_atomic_and
:
4123 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4125 case nir_intrinsic_ssbo_atomic_or
:
4126 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4128 case nir_intrinsic_ssbo_atomic_xor
:
4129 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4131 case nir_intrinsic_ssbo_atomic_exchange
:
4132 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4134 case nir_intrinsic_ssbo_atomic_comp_swap
:
4135 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4138 case nir_intrinsic_get_buffer_size
: {
4139 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4140 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4142 /* A resinfo's sampler message is used to get the buffer size. The
4143 * SIMD8's writeback message consists of four registers and SIMD16's
4144 * writeback message consists of 8 destination registers (two per each
4145 * component). Because we are only interested on the first channel of
4146 * the first returned component, where resinfo returns the buffer size
4147 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4148 * the dispatch width.
4150 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4151 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4152 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4155 ubld
.MOV(src_payload
, brw_imm_d(0));
4157 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4158 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4159 src_payload
, brw_imm_ud(index
));
4160 inst
->header_size
= 0;
4162 inst
->size_written
= 4 * REG_SIZE
;
4164 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4165 brw_mark_surface_used(prog_data
, index
);
4169 case nir_intrinsic_load_subgroup_size
:
4170 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4173 case nir_intrinsic_load_subgroup_invocation
: {
4174 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4175 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4176 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4177 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4178 if (dispatch_width
> 8)
4179 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4180 if (dispatch_width
> 16) {
4181 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4182 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4188 case nir_intrinsic_load_subgroup_eq_mask
:
4189 case nir_intrinsic_load_subgroup_ge_mask
:
4190 case nir_intrinsic_load_subgroup_gt_mask
:
4191 case nir_intrinsic_load_subgroup_le_mask
:
4192 case nir_intrinsic_load_subgroup_lt_mask
:
4193 unreachable("not reached");
4195 case nir_intrinsic_vote_any
: {
4196 const fs_builder ubld
= bld
.exec_all();
4198 /* The any/all predicates do not consider channel enables. To prevent
4199 * dead channels from affecting the result, we initialize the flag with
4200 * with the identity value for the logical operation.
4202 if (dispatch_width
== 32) {
4203 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4204 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4207 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4209 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4211 dest
.type
= BRW_REGISTER_TYPE_D
;
4212 bld
.MOV(dest
, brw_imm_d(-1));
4213 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4214 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4215 BRW_PREDICATE_ALIGN1_ANY32H
,
4216 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4219 case nir_intrinsic_vote_all
: {
4220 const fs_builder ubld
= bld
.exec_all();
4222 /* The any/all predicates do not consider channel enables. To prevent
4223 * dead channels from affecting the result, we initialize the flag with
4224 * with the identity value for the logical operation.
4226 if (dispatch_width
== 32) {
4227 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4228 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4229 brw_imm_ud(0xffffffff));
4231 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4233 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4235 dest
.type
= BRW_REGISTER_TYPE_D
;
4236 bld
.MOV(dest
, brw_imm_d(-1));
4237 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4238 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4239 BRW_PREDICATE_ALIGN1_ALL32H
,
4240 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4243 case nir_intrinsic_vote_eq
: {
4244 fs_reg value
= get_nir_src(instr
->src
[0]);
4245 fs_reg uniformized
= bld
.emit_uniformize(value
);
4246 const fs_builder ubld
= bld
.exec_all();
4248 /* The any/all predicates do not consider channel enables. To prevent
4249 * dead channels from affecting the result, we initialize the flag with
4250 * with the identity value for the logical operation.
4252 if (dispatch_width
== 32) {
4253 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4254 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4255 brw_imm_ud(0xffffffff));
4257 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4259 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4261 dest
.type
= BRW_REGISTER_TYPE_D
;
4262 bld
.MOV(dest
, brw_imm_d(-1));
4263 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4264 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4265 BRW_PREDICATE_ALIGN1_ALL32H
,
4266 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4270 case nir_intrinsic_ballot
: {
4271 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4272 BRW_REGISTER_TYPE_UD
);
4273 struct brw_reg flag
= brw_flag_reg(0, 0);
4274 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4275 * as f0.0. This is a problem for fragment programs as we currently use
4276 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4277 * programs yet so this isn't a problem. When we do, something will
4280 if (dispatch_width
== 32)
4281 flag
.type
= BRW_REGISTER_TYPE_UD
;
4283 bld
.exec_all().MOV(flag
, brw_imm_ud(0u));
4284 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4286 if (instr
->dest
.ssa
.bit_size
> 32) {
4287 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4289 dest
.type
= BRW_REGISTER_TYPE_UD
;
4291 bld
.MOV(dest
, flag
);
4295 case nir_intrinsic_read_invocation
: {
4296 const fs_reg value
= get_nir_src(instr
->src
[0]);
4297 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4298 fs_reg tmp
= bld
.vgrf(value
.type
);
4300 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4301 component(invocation
, 0));
4303 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4304 fs_reg(component(tmp
, 0)));
4308 case nir_intrinsic_read_first_invocation
: {
4309 const fs_reg value
= get_nir_src(instr
->src
[0]);
4310 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4311 bld
.emit_uniformize(value
));
4316 unreachable("unknown intrinsic");
4321 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4322 int op
, nir_intrinsic_instr
*instr
)
4324 if (stage
== MESA_SHADER_FRAGMENT
)
4325 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4328 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4329 dest
= get_nir_dest(instr
->dest
);
4332 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4333 if (const_surface
) {
4334 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4335 const_surface
->u32
[0];
4336 surface
= brw_imm_ud(surf_index
);
4337 brw_mark_surface_used(prog_data
, surf_index
);
4339 surface
= vgrf(glsl_type::uint_type
);
4340 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4341 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4343 /* Assume this may touch any SSBO. This is the same we do for other
4344 * UBO/SSBO accesses with non-constant surface.
4346 brw_mark_surface_used(prog_data
,
4347 stage_prog_data
->binding_table
.ssbo_start
+
4348 nir
->info
.num_ssbos
- 1);
4351 fs_reg offset
= get_nir_src(instr
->src
[1]);
4352 fs_reg data1
= get_nir_src(instr
->src
[2]);
4354 if (op
== BRW_AOP_CMPWR
)
4355 data2
= get_nir_src(instr
->src
[3]);
4357 /* Emit the actual atomic operation */
4359 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4361 1 /* dims */, 1 /* rsize */,
4363 BRW_PREDICATE_NONE
);
4364 dest
.type
= atomic_result
.type
;
4365 bld
.MOV(dest
, atomic_result
);
4369 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4370 int op
, nir_intrinsic_instr
*instr
)
4373 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4374 dest
= get_nir_dest(instr
->dest
);
4376 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4378 fs_reg data1
= get_nir_src(instr
->src
[1]);
4380 if (op
== BRW_AOP_CMPWR
)
4381 data2
= get_nir_src(instr
->src
[2]);
4383 /* Get the offset */
4384 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4386 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4388 offset
= vgrf(glsl_type::uint_type
);
4390 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4391 brw_imm_ud(instr
->const_index
[0]));
4394 /* Emit the actual atomic operation operation */
4396 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4398 1 /* dims */, 1 /* rsize */,
4400 BRW_PREDICATE_NONE
);
4401 dest
.type
= atomic_result
.type
;
4402 bld
.MOV(dest
, atomic_result
);
4406 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4408 unsigned texture
= instr
->texture_index
;
4409 unsigned sampler
= instr
->sampler_index
;
4411 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4413 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4414 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4416 int lod_components
= 0;
4418 /* The hardware requires a LOD for buffer textures */
4419 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4420 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4422 uint32_t header_bits
= 0;
4423 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4424 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4425 switch (instr
->src
[i
].src_type
) {
4426 case nir_tex_src_bias
:
4427 srcs
[TEX_LOGICAL_SRC_LOD
] =
4428 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4430 case nir_tex_src_comparator
:
4431 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4433 case nir_tex_src_coord
:
4434 switch (instr
->op
) {
4436 case nir_texop_txf_ms
:
4437 case nir_texop_txf_ms_mcs
:
4438 case nir_texop_samples_identical
:
4439 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4442 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4446 case nir_tex_src_ddx
:
4447 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4448 lod_components
= nir_tex_instr_src_size(instr
, i
);
4450 case nir_tex_src_ddy
:
4451 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4453 case nir_tex_src_lod
:
4454 switch (instr
->op
) {
4456 srcs
[TEX_LOGICAL_SRC_LOD
] =
4457 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4460 srcs
[TEX_LOGICAL_SRC_LOD
] =
4461 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4464 srcs
[TEX_LOGICAL_SRC_LOD
] =
4465 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4469 case nir_tex_src_ms_index
:
4470 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4473 case nir_tex_src_offset
: {
4474 nir_const_value
*const_offset
=
4475 nir_src_as_const_value(instr
->src
[i
].src
);
4476 unsigned offset_bits
= 0;
4478 brw_texture_offset(const_offset
->i32
,
4479 nir_tex_instr_src_size(instr
, i
),
4481 header_bits
|= offset_bits
;
4483 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4484 retype(src
, BRW_REGISTER_TYPE_D
);
4489 case nir_tex_src_projector
:
4490 unreachable("should be lowered");
4492 case nir_tex_src_texture_offset
: {
4493 /* Figure out the highest possible texture index and mark it as used */
4494 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4495 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4496 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4498 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4500 brw_mark_surface_used(prog_data
, max_used
);
4502 /* Emit code to evaluate the actual indexing expression */
4503 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4504 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4505 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4509 case nir_tex_src_sampler_offset
: {
4510 /* Emit code to evaluate the actual indexing expression */
4511 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4512 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4513 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4517 case nir_tex_src_ms_mcs
:
4518 assert(instr
->op
== nir_texop_txf_ms
);
4519 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4522 case nir_tex_src_plane
: {
4523 nir_const_value
*const_plane
=
4524 nir_src_as_const_value(instr
->src
[i
].src
);
4525 const uint32_t plane
= const_plane
->u32
[0];
4526 const uint32_t texture_index
=
4527 instr
->texture_index
+
4528 stage_prog_data
->binding_table
.plane_start
[plane
] -
4529 stage_prog_data
->binding_table
.texture_start
;
4531 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4536 unreachable("unknown texture source");
4540 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4541 (instr
->op
== nir_texop_txf_ms
||
4542 instr
->op
== nir_texop_samples_identical
)) {
4543 if (devinfo
->gen
>= 7 &&
4544 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4545 srcs
[TEX_LOGICAL_SRC_MCS
] =
4546 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4547 instr
->coord_components
,
4548 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4550 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4554 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4555 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4558 switch (instr
->op
) {
4560 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4561 SHADER_OPCODE_TXL_LOGICAL
);
4564 opcode
= FS_OPCODE_TXB_LOGICAL
;
4567 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4570 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4573 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4575 case nir_texop_txf_ms
:
4576 if ((key_tex
->msaa_16
& (1 << sampler
)))
4577 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4579 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4581 case nir_texop_txf_ms_mcs
:
4582 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4584 case nir_texop_query_levels
:
4586 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4589 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4592 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4593 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4595 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4597 case nir_texop_texture_samples
:
4598 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4600 case nir_texop_samples_identical
: {
4601 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4603 /* If mcs is an immediate value, it means there is no MCS. In that case
4604 * just return false.
4606 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4607 bld
.MOV(dst
, brw_imm_ud(0u));
4608 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4609 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4610 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4611 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4612 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4614 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4615 BRW_CONDITIONAL_EQ
);
4620 unreachable("unknown texture opcode");
4623 if (instr
->op
== nir_texop_tg4
) {
4624 if (instr
->component
== 1 &&
4625 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4626 /* gather4 sampler is broken for green channel on RG32F --
4627 * we must ask for blue instead.
4629 header_bits
|= 2 << 16;
4631 header_bits
|= instr
->component
<< 16;
4635 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4636 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4637 inst
->offset
= header_bits
;
4639 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4640 if (devinfo
->gen
>= 9 &&
4641 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4642 unsigned write_mask
= instr
->dest
.is_ssa
?
4643 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4644 (1 << dest_size
) - 1;
4645 assert(write_mask
!= 0); /* dead code should have been eliminated */
4646 inst
->size_written
= util_last_bit(write_mask
) *
4647 inst
->dst
.component_size(inst
->exec_size
);
4649 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4652 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4653 inst
->shadow_compare
= true;
4655 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4656 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4659 for (unsigned i
= 0; i
< dest_size
; i
++)
4660 nir_dest
[i
] = offset(dst
, bld
, i
);
4662 if (instr
->op
== nir_texop_query_levels
) {
4663 /* # levels is in .w */
4664 nir_dest
[0] = offset(dst
, bld
, 3);
4665 } else if (instr
->op
== nir_texop_txs
&&
4666 dest_size
>= 3 && devinfo
->gen
< 7) {
4667 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4668 fs_reg depth
= offset(dst
, bld
, 2);
4669 nir_dest
[2] = vgrf(glsl_type::int_type
);
4670 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4673 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4677 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4679 switch (instr
->type
) {
4680 case nir_jump_break
:
4681 bld
.emit(BRW_OPCODE_BREAK
);
4683 case nir_jump_continue
:
4684 bld
.emit(BRW_OPCODE_CONTINUE
);
4686 case nir_jump_return
:
4688 unreachable("unknown jump");
4693 * This helper takes the result of a load operation that reads 32-bit elements
4701 * and shuffles the data to get this:
4708 * Which is exactly what we want if the load is reading 64-bit components
4709 * like doubles, where x represents the low 32-bit of the x double component
4710 * and y represents the high 32-bit of the x double component (likewise with
4711 * z and w for double component y). The parameter @components represents
4712 * the number of 64-bit components present in @src. This would typically be
4713 * 2 at most, since we can only fit 2 double elements in the result of a
4716 * Notice that @dst and @src can be the same register.
4719 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4722 uint32_t components
)
4724 assert(type_sz(src
.type
) == 4);
4725 assert(type_sz(dst
.type
) == 8);
4727 /* A temporary that we will use to shuffle the 32-bit data of each
4728 * component in the vector into valid 64-bit data. We can't write directly
4729 * to dst because dst can be (and would usually be) the same as src
4730 * and in that case the first MOV in the loop below would overwrite the
4731 * data read in the second MOV.
4733 fs_reg tmp
= bld
.vgrf(dst
.type
);
4735 for (unsigned i
= 0; i
< components
; i
++) {
4736 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4738 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4739 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4741 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4746 * This helper does the inverse operation of
4747 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4749 * We need to do this when we are going to use untyped write messsages that
4750 * operate with 32-bit components in order to arrange our 64-bit data to be
4751 * in the expected layout.
4753 * Notice that callers of this function, unlike in the case of the inverse
4754 * operation, would typically need to call this with dst and src being
4755 * different registers, since they would otherwise corrupt the original
4756 * 64-bit data they are about to write. Because of this the function checks
4757 * that the src and dst regions involved in the operation do not overlap.
4760 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4763 uint32_t components
)
4765 assert(type_sz(src
.type
) == 8);
4766 assert(type_sz(dst
.type
) == 4);
4768 assert(!regions_overlap(
4769 dst
, 2 * components
* dst
.component_size(bld
.dispatch_width()),
4770 src
, components
* src
.component_size(bld
.dispatch_width())));
4772 for (unsigned i
= 0; i
< components
; i
++) {
4773 const fs_reg component_i
= offset(src
, bld
, i
);
4774 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4775 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4780 setup_imm_df(const fs_builder
&bld
, double v
)
4782 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4783 assert(devinfo
->gen
>= 7);
4785 if (devinfo
->gen
>= 8)
4786 return brw_imm_df(v
);
4788 /* gen7.5 does not support DF immediates straighforward but the DIM
4789 * instruction allows to set the 64-bit immediate value.
4791 if (devinfo
->is_haswell
) {
4792 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4793 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4794 ubld
.DIM(dst
, brw_imm_df(v
));
4795 return component(dst
, 0);
4798 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4799 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4800 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4802 * Alternatively, we could also produce a normal VGRF (without stride 0)
4803 * by writing to all the channels in the VGRF, however, that would hit the
4804 * gen7 bug where we have to split writes that span more than 1 register
4805 * into instructions with a width of 4 (otherwise the write to the second
4806 * register written runs into an execmask hardware bug) which isn't very
4819 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4820 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4821 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4822 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4824 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);