2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 nir_foreach_variable(var
, &nir
->outputs
) {
71 const int loc
= var
->data
.driver_location
;
72 if (outputs
[loc
].file
== BAD_FILE
) {
73 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
[loc
]);
74 for (unsigned i
= 0; i
< vec4s
[loc
]; i
++) {
75 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
82 fs_visitor::nir_setup_uniforms()
84 /* Only the first compile gets to set up uniforms. */
85 if (push_constant_loc
) {
86 assert(pull_constant_loc
);
90 uniforms
= nir
->num_uniforms
/ 4;
92 if (stage
== MESA_SHADER_COMPUTE
) {
93 /* Add a uniform for the thread local id. It must be the last uniform
96 assert(uniforms
== prog_data
->nr_params
);
97 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
98 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
99 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
104 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
108 nir_foreach_instr(instr
, block
) {
109 if (instr
->type
!= nir_instr_type_intrinsic
)
112 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
113 switch (intrin
->intrinsic
) {
114 case nir_intrinsic_load_vertex_id
:
115 unreachable("should be lowered by lower_vertex_id().");
117 case nir_intrinsic_load_vertex_id_zero_base
:
118 case nir_intrinsic_load_base_vertex
:
119 case nir_intrinsic_load_instance_id
:
120 case nir_intrinsic_load_base_instance
:
121 case nir_intrinsic_load_draw_id
:
122 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
124 case nir_intrinsic_load_invocation_id
:
125 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
127 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
128 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
129 if (reg
->file
== BAD_FILE
) {
130 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
131 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
132 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
133 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
138 case nir_intrinsic_load_sample_pos
:
139 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
140 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
141 if (reg
->file
== BAD_FILE
)
142 *reg
= *v
->emit_samplepos_setup();
145 case nir_intrinsic_load_sample_id
:
146 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
147 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
148 if (reg
->file
== BAD_FILE
)
149 *reg
= *v
->emit_sampleid_setup();
152 case nir_intrinsic_load_sample_mask_in
:
153 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
154 assert(v
->devinfo
->gen
>= 7);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_samplemaskin_setup();
160 case nir_intrinsic_load_work_group_id
:
161 assert(v
->stage
== MESA_SHADER_COMPUTE
);
162 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
163 if (reg
->file
== BAD_FILE
)
164 *reg
= *v
->emit_cs_work_group_id_setup();
167 case nir_intrinsic_load_helper_invocation
:
168 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
169 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
170 if (reg
->file
== BAD_FILE
) {
171 const fs_builder abld
=
172 v
->bld
.annotate("gl_HelperInvocation", NULL
);
174 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
175 * pixel mask is in g1.7 of the thread payload.
177 * We move the per-channel pixel enable bit to the low bit of each
178 * channel by shifting the byte containing the pixel mask by the
179 * vector immediate 0x76543210UV.
181 * The region of <1,8,0> reads only 1 byte (the pixel masks for
182 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
183 * masks for 2 and 3) in SIMD16.
185 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
187 stride(byte_offset(retype(brw_vec1_grf(1, 0),
188 BRW_REGISTER_TYPE_UB
), 28),
190 brw_imm_v(0x76543210));
192 /* A set bit in the pixel mask means the channel is enabled, but
193 * that is the opposite of gl_HelperInvocation so we need to invert
196 * The negate source-modifier bit of logical instructions on Gen8+
197 * performs 1's complement negation, so we can use that instead of
200 fs_reg inverted
= negate(shifted
);
201 if (v
->devinfo
->gen
< 8) {
202 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
203 abld
.NOT(inverted
, shifted
);
206 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
207 * with 1 and negating.
209 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
210 abld
.AND(anded
, inverted
, brw_imm_uw(1));
212 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
213 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
227 fs_visitor::nir_emit_system_values()
229 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
230 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
231 nir_system_values
[i
] = fs_reg();
234 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
235 * never end up using it.
238 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
239 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
240 reg
= abld
.vgrf(BRW_REGISTER_TYPE_W
);
242 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
243 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
244 if (dispatch_width
> 8)
245 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
246 if (dispatch_width
> 16) {
247 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
248 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
252 nir_foreach_function(function
, nir
) {
253 assert(strcmp(function
->name
, "main") == 0);
254 assert(function
->impl
);
255 nir_foreach_block(block
, function
->impl
) {
256 emit_system_values_block(block
, this);
262 * Returns a type based on a reference_type (word, float, half-float) and a
265 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
267 * @FIXME: 64-bit return types are always DF on integer types to maintain
268 * compability with uses of DF previously to the introduction of int64
272 brw_reg_type_from_bit_size(const unsigned bit_size
,
273 const brw_reg_type reference_type
)
275 switch(reference_type
) {
276 case BRW_REGISTER_TYPE_HF
:
277 case BRW_REGISTER_TYPE_F
:
278 case BRW_REGISTER_TYPE_DF
:
281 return BRW_REGISTER_TYPE_HF
;
283 return BRW_REGISTER_TYPE_F
;
285 return BRW_REGISTER_TYPE_DF
;
287 unreachable("Invalid bit size");
289 case BRW_REGISTER_TYPE_W
:
290 case BRW_REGISTER_TYPE_D
:
291 case BRW_REGISTER_TYPE_Q
:
294 return BRW_REGISTER_TYPE_W
;
296 return BRW_REGISTER_TYPE_D
;
298 return BRW_REGISTER_TYPE_Q
;
300 unreachable("Invalid bit size");
302 case BRW_REGISTER_TYPE_UW
:
303 case BRW_REGISTER_TYPE_UD
:
304 case BRW_REGISTER_TYPE_UQ
:
307 return BRW_REGISTER_TYPE_UW
;
309 return BRW_REGISTER_TYPE_UD
;
311 return BRW_REGISTER_TYPE_UQ
;
313 unreachable("Invalid bit size");
316 unreachable("Unknown type");
321 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
323 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
324 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
325 nir_locals
[i
] = fs_reg();
328 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
329 unsigned array_elems
=
330 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
331 unsigned size
= array_elems
* reg
->num_components
;
332 const brw_reg_type reg_type
=
333 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
334 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
337 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
340 nir_emit_cf_list(&impl
->body
);
344 fs_visitor::nir_emit_cf_list(exec_list
*list
)
346 exec_list_validate(list
);
347 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
348 switch (node
->type
) {
350 nir_emit_if(nir_cf_node_as_if(node
));
353 case nir_cf_node_loop
:
354 nir_emit_loop(nir_cf_node_as_loop(node
));
357 case nir_cf_node_block
:
358 nir_emit_block(nir_cf_node_as_block(node
));
362 unreachable("Invalid CFG node block");
368 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
370 /* first, put the condition into f0 */
371 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
372 retype(get_nir_src(if_stmt
->condition
),
373 BRW_REGISTER_TYPE_D
));
374 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
376 bld
.IF(BRW_PREDICATE_NORMAL
);
378 nir_emit_cf_list(&if_stmt
->then_list
);
380 /* note: if the else is empty, dead CF elimination will remove it */
381 bld
.emit(BRW_OPCODE_ELSE
);
383 nir_emit_cf_list(&if_stmt
->else_list
);
385 bld
.emit(BRW_OPCODE_ENDIF
);
389 fs_visitor::nir_emit_loop(nir_loop
*loop
)
391 bld
.emit(BRW_OPCODE_DO
);
393 nir_emit_cf_list(&loop
->body
);
395 bld
.emit(BRW_OPCODE_WHILE
);
399 fs_visitor::nir_emit_block(nir_block
*block
)
401 nir_foreach_instr(instr
, block
) {
402 nir_emit_instr(instr
);
407 fs_visitor::nir_emit_instr(nir_instr
*instr
)
409 const fs_builder abld
= bld
.annotate(NULL
, instr
);
411 switch (instr
->type
) {
412 case nir_instr_type_alu
:
413 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
416 case nir_instr_type_intrinsic
:
418 case MESA_SHADER_VERTEX
:
419 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
421 case MESA_SHADER_TESS_CTRL
:
422 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
424 case MESA_SHADER_TESS_EVAL
:
425 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
427 case MESA_SHADER_GEOMETRY
:
428 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
430 case MESA_SHADER_FRAGMENT
:
431 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
433 case MESA_SHADER_COMPUTE
:
434 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
437 unreachable("unsupported shader stage");
441 case nir_instr_type_tex
:
442 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
445 case nir_instr_type_load_const
:
446 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
449 case nir_instr_type_ssa_undef
:
450 /* We create a new VGRF for undefs on every use (by handling
451 * them in get_nir_src()), rather than for each definition.
452 * This helps register coalescing eliminate MOVs from undef.
456 case nir_instr_type_jump
:
457 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
461 unreachable("unknown instruction type");
466 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
470 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
471 const fs_reg
&result
)
473 if (!instr
->src
[0].src
.is_ssa
||
474 !instr
->src
[0].src
.ssa
->parent_instr
)
477 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
480 nir_alu_instr
*src0
=
481 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
483 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
484 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
487 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
488 assert(element
!= NULL
);
490 /* Element type to extract.*/
491 const brw_reg_type type
= brw_int_type(
492 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
493 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
495 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
496 op0
.type
= brw_type_for_nir_type(devinfo
,
497 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
498 nir_src_bit_size(src0
->src
[0].src
)));
499 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
501 set_saturate(instr
->dest
.saturate
,
502 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
507 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
508 const fs_reg
&result
)
510 if (!instr
->src
[0].src
.is_ssa
||
511 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
514 nir_intrinsic_instr
*src0
=
515 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
517 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
520 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
521 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
524 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
525 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
528 fs_reg tmp
= vgrf(glsl_type::int_type
);
530 if (devinfo
->gen
>= 6) {
531 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
532 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
534 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
536 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
537 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
539 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
541 * This negation looks like it's safe in practice, because bits 0:4 will
542 * surely be TRIANGLES
545 if (value1
->f32
[0] == -1.0f
) {
549 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
550 g0
, brw_imm_uw(0x3f80));
552 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
553 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
555 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
557 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
558 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
560 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
562 * This negation looks like it's safe in practice, because bits 0:4 will
563 * surely be TRIANGLES
566 if (value1
->f32
[0] == -1.0f
) {
570 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
572 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
578 emit_find_msb_using_lzd(const fs_builder
&bld
,
579 const fs_reg
&result
,
587 /* LZD of an absolute value source almost always does the right
588 * thing. There are two problem values:
590 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
591 * 0. However, findMSB(int(0x80000000)) == 30.
593 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
594 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
596 * For a value of zero or negative one, -1 will be returned.
598 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
599 * findMSB(-(1<<x)) should return x-1.
601 * For all negative number cases, including 0x80000000 and
602 * 0xffffffff, the correct value is obtained from LZD if instead of
603 * negating the (already negative) value the logical-not is used. A
604 * conditonal logical-not can be achieved in two instructions.
606 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
608 bld
.ASR(temp
, src
, brw_imm_d(31));
609 bld
.XOR(temp
, temp
, src
);
612 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
613 retype(temp
, BRW_REGISTER_TYPE_UD
));
615 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
616 * from the LSB side. Subtract the result from 31 to convert the MSB
617 * count into an LSB count. If no bits are set, LZD will return 32.
618 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
620 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
621 inst
->src
[0].negate
= true;
625 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
627 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
630 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
631 result
.type
= brw_type_for_nir_type(devinfo
,
632 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
633 nir_dest_bit_size(instr
->dest
.dest
)));
636 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
637 op
[i
] = get_nir_src(instr
->src
[i
].src
);
638 op
[i
].type
= brw_type_for_nir_type(devinfo
,
639 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
640 nir_src_bit_size(instr
->src
[i
].src
)));
641 op
[i
].abs
= instr
->src
[i
].abs
;
642 op
[i
].negate
= instr
->src
[i
].negate
;
645 /* We get a bunch of mov's out of the from_ssa pass and they may still
646 * be vectorized. We'll handle them as a special-case. We'll also
647 * handle vecN here because it's basically the same thing.
655 fs_reg temp
= result
;
656 bool need_extra_copy
= false;
657 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
658 if (!instr
->src
[i
].src
.is_ssa
&&
659 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
660 need_extra_copy
= true;
661 temp
= bld
.vgrf(result
.type
, 4);
666 for (unsigned i
= 0; i
< 4; i
++) {
667 if (!(instr
->dest
.write_mask
& (1 << i
)))
670 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
671 inst
= bld
.MOV(offset(temp
, bld
, i
),
672 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
674 inst
= bld
.MOV(offset(temp
, bld
, i
),
675 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
677 inst
->saturate
= instr
->dest
.saturate
;
680 /* In this case the source and destination registers were the same,
681 * so we need to insert an extra set of moves in order to deal with
684 if (need_extra_copy
) {
685 for (unsigned i
= 0; i
< 4; i
++) {
686 if (!(instr
->dest
.write_mask
& (1 << i
)))
689 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
698 /* At this point, we have dealt with any instruction that operates on
699 * more than a single channel. Therefore, we can just adjust the source
700 * and destination registers for that channel and emit the instruction.
702 unsigned channel
= 0;
703 if (nir_op_infos
[instr
->op
].output_size
== 0) {
704 /* Since NIR is doing the scalarizing for us, we should only ever see
705 * vectorized operations with a single channel.
707 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
708 channel
= ffs(instr
->dest
.write_mask
) - 1;
710 result
= offset(result
, bld
, channel
);
713 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
714 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
715 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
721 if (optimize_extract_to_float(instr
, result
))
723 inst
= bld
.MOV(result
, op
[0]);
724 inst
->saturate
= instr
->dest
.saturate
;
734 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
736 * "When source or destination is 64b (...), regioning in Align1
737 * must follow these rules:
739 * 1. Source and destination horizontal stride must be aligned to
743 * This means that 32-bit to 64-bit conversions need to have the 32-bit
744 * data elements aligned to 64-bit. This restriction does not apply to
747 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
748 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
749 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
750 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
751 tmp
= subscript(tmp
, op
[0].type
, 0);
752 inst
= bld
.MOV(tmp
, op
[0]);
753 inst
= bld
.MOV(result
, tmp
);
754 inst
->saturate
= instr
->dest
.saturate
;
763 inst
= bld
.MOV(result
, op
[0]);
764 inst
->saturate
= instr
->dest
.saturate
;
769 /* Straightforward since the source can be assumed to be
772 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
773 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
775 } else if (type_sz(op
[0].type
) < 8) {
776 /* AND(val, 0x80000000) gives the sign bit.
778 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
781 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
783 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
784 op
[0].type
= BRW_REGISTER_TYPE_UD
;
785 result
.type
= BRW_REGISTER_TYPE_UD
;
786 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
788 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
789 inst
->predicate
= BRW_PREDICATE_NORMAL
;
790 if (instr
->dest
.saturate
) {
791 inst
= bld
.MOV(result
, result
);
792 inst
->saturate
= true;
795 /* For doubles we do the same but we need to consider:
797 * - 2-src instructions can't operate with 64-bit immediates
798 * - The sign is encoded in the high 32-bit of each DF
799 * - We need to produce a DF result.
802 fs_reg zero
= vgrf(glsl_type::double_type
);
803 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
804 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
806 bld
.MOV(result
, zero
);
808 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
809 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
810 brw_imm_ud(0x80000000u
));
812 set_predicate(BRW_PREDICATE_NORMAL
,
813 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
815 if (instr
->dest
.saturate
) {
816 inst
= bld
.MOV(result
, result
);
817 inst
->saturate
= true;
824 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
825 * -> non-negative val generates 0x00000000.
826 * Predicated OR sets 1 if val is positive.
828 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
829 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
830 bld
.ASR(result
, op
[0], brw_imm_d(31));
831 inst
= bld
.OR(result
, result
, brw_imm_d(1));
832 inst
->predicate
= BRW_PREDICATE_NORMAL
;
836 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
837 inst
->saturate
= instr
->dest
.saturate
;
841 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
842 inst
->saturate
= instr
->dest
.saturate
;
846 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
847 inst
->saturate
= instr
->dest
.saturate
;
851 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
852 inst
->saturate
= instr
->dest
.saturate
;
856 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
857 inst
->saturate
= instr
->dest
.saturate
;
861 if (fs_key
->high_quality_derivatives
) {
862 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
864 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
866 inst
->saturate
= instr
->dest
.saturate
;
868 case nir_op_fddx_fine
:
869 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
870 inst
->saturate
= instr
->dest
.saturate
;
872 case nir_op_fddx_coarse
:
873 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
874 inst
->saturate
= instr
->dest
.saturate
;
877 if (fs_key
->high_quality_derivatives
) {
878 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
880 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
882 inst
->saturate
= instr
->dest
.saturate
;
884 case nir_op_fddy_fine
:
885 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
886 inst
->saturate
= instr
->dest
.saturate
;
888 case nir_op_fddy_coarse
:
889 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
890 inst
->saturate
= instr
->dest
.saturate
;
895 inst
= bld
.ADD(result
, op
[0], op
[1]);
896 inst
->saturate
= instr
->dest
.saturate
;
900 inst
= bld
.MUL(result
, op
[0], op
[1]);
901 inst
->saturate
= instr
->dest
.saturate
;
905 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
906 bld
.MUL(result
, op
[0], op
[1]);
909 case nir_op_imul_high
:
910 case nir_op_umul_high
:
911 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
912 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
917 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
918 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
921 case nir_op_uadd_carry
:
922 unreachable("Should have been lowered by carry_to_arith().");
924 case nir_op_usub_borrow
:
925 unreachable("Should have been lowered by borrow_to_arith().");
929 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
930 * appears that our hardware just does the right thing for signed
933 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
934 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
938 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
939 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
941 /* Math instructions don't support conditional mod */
942 inst
= bld
.MOV(bld
.null_reg_d(), result
);
943 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
945 /* Now, we need to determine if signs of the sources are different.
946 * When we XOR the sources, the top bit is 0 if they are the same and 1
947 * if they are different. We can then use a conditional modifier to
948 * turn that into a predicate. This leads us to an XOR.l instruction.
950 * Technically, according to the PRM, you're not allowed to use .l on a
951 * XOR instruction. However, emperical experiments and Curro's reading
952 * of the simulator source both indicate that it's safe.
954 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
955 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
956 inst
->predicate
= BRW_PREDICATE_NORMAL
;
957 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
959 /* If the result of the initial remainder operation is non-zero and the
960 * two sources have different signs, add in a copy of op[1] to get the
961 * final integer modulus value.
963 inst
= bld
.ADD(result
, result
, op
[1]);
964 inst
->predicate
= BRW_PREDICATE_NORMAL
;
972 fs_reg dest
= result
;
973 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
974 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
976 brw_conditional_mod cond
;
979 cond
= BRW_CONDITIONAL_L
;
982 cond
= BRW_CONDITIONAL_GE
;
985 cond
= BRW_CONDITIONAL_Z
;
988 cond
= BRW_CONDITIONAL_NZ
;
991 unreachable("bad opcode");
993 bld
.CMP(dest
, op
[0], op
[1], cond
);
994 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
995 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1006 fs_reg dest
= result
;
1007 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1008 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
1011 brw_conditional_mod cond
;
1012 switch (instr
->op
) {
1015 cond
= BRW_CONDITIONAL_L
;
1019 cond
= BRW_CONDITIONAL_GE
;
1022 cond
= BRW_CONDITIONAL_Z
;
1025 cond
= BRW_CONDITIONAL_NZ
;
1028 unreachable("bad opcode");
1030 bld
.CMP(dest
, op
[0], op
[1], cond
);
1031 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1032 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1038 if (devinfo
->gen
>= 8) {
1039 op
[0] = resolve_source_modifiers(op
[0]);
1041 bld
.NOT(result
, op
[0]);
1044 if (devinfo
->gen
>= 8) {
1045 op
[0] = resolve_source_modifiers(op
[0]);
1046 op
[1] = resolve_source_modifiers(op
[1]);
1048 bld
.XOR(result
, op
[0], op
[1]);
1051 if (devinfo
->gen
>= 8) {
1052 op
[0] = resolve_source_modifiers(op
[0]);
1053 op
[1] = resolve_source_modifiers(op
[1]);
1055 bld
.OR(result
, op
[0], op
[1]);
1058 if (devinfo
->gen
>= 8) {
1059 op
[0] = resolve_source_modifiers(op
[0]);
1060 op
[1] = resolve_source_modifiers(op
[1]);
1062 bld
.AND(result
, op
[0], op
[1]);
1068 case nir_op_ball_fequal2
:
1069 case nir_op_ball_iequal2
:
1070 case nir_op_ball_fequal3
:
1071 case nir_op_ball_iequal3
:
1072 case nir_op_ball_fequal4
:
1073 case nir_op_ball_iequal4
:
1074 case nir_op_bany_fnequal2
:
1075 case nir_op_bany_inequal2
:
1076 case nir_op_bany_fnequal3
:
1077 case nir_op_bany_inequal3
:
1078 case nir_op_bany_fnequal4
:
1079 case nir_op_bany_inequal4
:
1080 unreachable("Lowered by nir_lower_alu_reductions");
1082 case nir_op_fnoise1_1
:
1083 case nir_op_fnoise1_2
:
1084 case nir_op_fnoise1_3
:
1085 case nir_op_fnoise1_4
:
1086 case nir_op_fnoise2_1
:
1087 case nir_op_fnoise2_2
:
1088 case nir_op_fnoise2_3
:
1089 case nir_op_fnoise2_4
:
1090 case nir_op_fnoise3_1
:
1091 case nir_op_fnoise3_2
:
1092 case nir_op_fnoise3_3
:
1093 case nir_op_fnoise3_4
:
1094 case nir_op_fnoise4_1
:
1095 case nir_op_fnoise4_2
:
1096 case nir_op_fnoise4_3
:
1097 case nir_op_fnoise4_4
:
1098 unreachable("not reached: should be handled by lower_noise");
1101 unreachable("not reached: should be handled by ldexp_to_arith()");
1104 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1105 inst
->saturate
= instr
->dest
.saturate
;
1109 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1110 inst
->saturate
= instr
->dest
.saturate
;
1115 bld
.MOV(result
, negate(op
[0]));
1120 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1121 /* two-argument instructions can't take 64-bit immediates */
1125 if (instr
->op
== nir_op_f2b
) {
1126 zero
= vgrf(glsl_type::double_type
);
1127 tmp
= vgrf(glsl_type::double_type
);
1128 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1130 zero
= vgrf(glsl_type::int64_t_type
);
1131 tmp
= vgrf(glsl_type::int64_t_type
);
1132 bld
.MOV(zero
, brw_imm_q(0));
1135 /* A SIMD16 execution needs to be split in two instructions, so use
1136 * a vgrf instead of the flag register as dst so instruction splitting
1139 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1140 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1142 if (instr
->op
== nir_op_f2b
) {
1143 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1145 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1151 inst
= bld
.RNDZ(result
, op
[0]);
1152 inst
->saturate
= instr
->dest
.saturate
;
1155 case nir_op_fceil
: {
1156 op
[0].negate
= !op
[0].negate
;
1157 fs_reg temp
= vgrf(glsl_type::float_type
);
1158 bld
.RNDD(temp
, op
[0]);
1160 inst
= bld
.MOV(result
, temp
);
1161 inst
->saturate
= instr
->dest
.saturate
;
1165 inst
= bld
.RNDD(result
, op
[0]);
1166 inst
->saturate
= instr
->dest
.saturate
;
1169 inst
= bld
.FRC(result
, op
[0]);
1170 inst
->saturate
= instr
->dest
.saturate
;
1172 case nir_op_fround_even
:
1173 inst
= bld
.RNDE(result
, op
[0]);
1174 inst
->saturate
= instr
->dest
.saturate
;
1177 case nir_op_fquantize2f16
: {
1178 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1179 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1180 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1182 /* The destination stride must be at least as big as the source stride. */
1183 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1186 /* Check for denormal */
1187 fs_reg abs_src0
= op
[0];
1188 abs_src0
.abs
= true;
1189 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1191 /* Get the appropriately signed zero */
1192 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1193 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1194 brw_imm_ud(0x80000000));
1195 /* Do the actual F32 -> F16 -> F32 conversion */
1196 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1197 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1198 /* Select that or zero based on normal status */
1199 inst
= bld
.SEL(result
, zero
, tmp32
);
1200 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1201 inst
->saturate
= instr
->dest
.saturate
;
1208 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1209 inst
->saturate
= instr
->dest
.saturate
;
1215 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1216 inst
->saturate
= instr
->dest
.saturate
;
1219 case nir_op_pack_snorm_2x16
:
1220 case nir_op_pack_snorm_4x8
:
1221 case nir_op_pack_unorm_2x16
:
1222 case nir_op_pack_unorm_4x8
:
1223 case nir_op_unpack_snorm_2x16
:
1224 case nir_op_unpack_snorm_4x8
:
1225 case nir_op_unpack_unorm_2x16
:
1226 case nir_op_unpack_unorm_4x8
:
1227 case nir_op_unpack_half_2x16
:
1228 case nir_op_pack_half_2x16
:
1229 unreachable("not reached: should be handled by lower_packing_builtins");
1231 case nir_op_unpack_half_2x16_split_x
:
1232 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1233 inst
->saturate
= instr
->dest
.saturate
;
1235 case nir_op_unpack_half_2x16_split_y
:
1236 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1237 inst
->saturate
= instr
->dest
.saturate
;
1240 case nir_op_pack_64_2x32_split
:
1241 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1244 case nir_op_unpack_64_2x32_split_x
:
1245 case nir_op_unpack_64_2x32_split_y
: {
1246 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1247 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1249 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1254 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1255 inst
->saturate
= instr
->dest
.saturate
;
1258 case nir_op_bitfield_reverse
:
1259 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1260 bld
.BFREV(result
, op
[0]);
1263 case nir_op_bit_count
:
1264 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1265 bld
.CBIT(result
, op
[0]);
1268 case nir_op_ufind_msb
: {
1269 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1270 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1274 case nir_op_ifind_msb
: {
1275 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1277 if (devinfo
->gen
< 7) {
1278 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1280 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1282 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1283 * count from the LSB side. If FBH didn't return an error
1284 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1285 * count into an LSB count.
1287 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1289 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1290 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1291 inst
->src
[0].negate
= true;
1296 case nir_op_find_lsb
:
1297 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1299 if (devinfo
->gen
< 7) {
1300 fs_reg temp
= vgrf(glsl_type::int_type
);
1302 /* (x & -x) generates a value that consists of only the LSB of x.
1303 * For all powers of 2, findMSB(y) == findLSB(y).
1305 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1306 fs_reg negated_src
= src
;
1308 /* One must be negated, and the other must be non-negated. It
1309 * doesn't matter which is which.
1311 negated_src
.negate
= true;
1314 bld
.AND(temp
, src
, negated_src
);
1315 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1317 bld
.FBL(result
, op
[0]);
1321 case nir_op_ubitfield_extract
:
1322 case nir_op_ibitfield_extract
:
1323 unreachable("should have been lowered");
1326 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1327 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1330 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1331 bld
.BFI1(result
, op
[0], op
[1]);
1334 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1335 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1338 case nir_op_bitfield_insert
:
1339 unreachable("not reached: should have been lowered");
1344 fs_reg shift_count
= op
[1];
1346 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1347 if (op
[1].file
== VGRF
&&
1348 (result
.type
== BRW_REGISTER_TYPE_Q
||
1349 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1350 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1351 BRW_REGISTER_TYPE_UD
);
1352 shift_count
.stride
= 2;
1353 bld
.MOV(shift_count
, op
[1]);
1357 switch (instr
->op
) {
1359 bld
.SHL(result
, op
[0], shift_count
);
1362 bld
.ASR(result
, op
[0], shift_count
);
1365 bld
.SHR(result
, op
[0], shift_count
);
1368 unreachable("not reached");
1373 case nir_op_pack_half_2x16_split
:
1374 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1378 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1379 inst
->saturate
= instr
->dest
.saturate
;
1383 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1384 inst
->saturate
= instr
->dest
.saturate
;
1388 if (optimize_frontfacing_ternary(instr
, result
))
1391 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1392 inst
= bld
.SEL(result
, op
[1], op
[2]);
1393 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1396 case nir_op_extract_u8
:
1397 case nir_op_extract_i8
: {
1398 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1399 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1400 assert(byte
!= NULL
);
1401 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1405 case nir_op_extract_u16
:
1406 case nir_op_extract_i16
: {
1407 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1408 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1409 assert(word
!= NULL
);
1410 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1415 unreachable("unhandled instruction");
1418 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1419 * to sign extend the low bit to 0/~0
1421 if (devinfo
->gen
<= 5 &&
1422 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1423 fs_reg masked
= vgrf(glsl_type::int_type
);
1424 bld
.AND(masked
, result
, brw_imm_d(1));
1425 masked
.negate
= true;
1426 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1431 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1432 nir_load_const_instr
*instr
)
1434 const brw_reg_type reg_type
=
1435 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1436 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1438 switch (instr
->def
.bit_size
) {
1440 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1441 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1445 assert(devinfo
->gen
>= 7);
1446 if (devinfo
->gen
== 7) {
1447 /* We don't get 64-bit integer types until gen8 */
1448 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1449 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1450 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1453 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1454 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1459 unreachable("Invalid bit size");
1462 nir_ssa_values
[instr
->def
.index
] = reg
;
1466 fs_visitor::get_nir_src(const nir_src
&src
)
1470 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1471 const brw_reg_type reg_type
=
1472 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1473 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1475 reg
= nir_ssa_values
[src
.ssa
->index
];
1478 /* We don't handle indirects on locals */
1479 assert(src
.reg
.indirect
== NULL
);
1480 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1481 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1484 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1485 /* The only 64-bit type available on gen7 is DF, so use that. */
1486 reg
.type
= BRW_REGISTER_TYPE_DF
;
1488 /* To avoid floating-point denorm flushing problems, set the type by
1489 * default to an integer type - instructions that need floating point
1490 * semantics will set this to F if they need to
1492 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1493 BRW_REGISTER_TYPE_D
);
1500 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1502 * This function should not be called on any value which may be 64 bits.
1503 * We could theoretically support 64-bit on gen8+ but we choose not to
1504 * because it wouldn't work in general (no gen7 support) and there are
1505 * enough restrictions in 64-bit immediates that you can't take the return
1506 * value and treat it the same as the result of get_nir_src().
1509 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1511 nir_const_value
*val
= nir_src_as_const_value(src
);
1512 assert(nir_src_bit_size(src
) == 32);
1513 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1517 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1520 const brw_reg_type reg_type
=
1521 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1522 nir_ssa_values
[dest
.ssa
.index
] =
1523 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1524 return nir_ssa_values
[dest
.ssa
.index
];
1526 /* We don't handle indirects on locals */
1527 assert(dest
.reg
.indirect
== NULL
);
1528 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1529 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1534 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1536 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1537 BRW_REGISTER_TYPE_UD
);
1539 unsigned indirect_max
= 0;
1541 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1542 tail
= tail
->child
) {
1543 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1544 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1545 const unsigned size
= glsl_get_length(tail
->type
);
1546 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1547 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1548 image
= offset(image
, bld
, base
* element_size
);
1550 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1551 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1553 /* Accessing an invalid surface index with the dataport can result
1554 * in a hang. According to the spec "if the index used to
1555 * select an individual element is negative or greater than or
1556 * equal to the size of the array, the results of the operation
1557 * are undefined but may not lead to termination" -- which is one
1558 * of the possible outcomes of the hang. Clamp the index to
1559 * prevent access outside of the array bounds.
1561 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1562 BRW_REGISTER_TYPE_UD
),
1563 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1565 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1567 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1568 if (indirect
.file
== BAD_FILE
) {
1571 bld
.ADD(indirect
, indirect
, tmp
);
1576 if (indirect
.file
== BAD_FILE
) {
1579 /* Emit a pile of MOVs to load the uniform into a temporary. The
1580 * dead-code elimination pass will get rid of what we don't use.
1582 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1583 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1584 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1585 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1586 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1593 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1596 for (unsigned i
= 0; i
< 4; i
++) {
1597 if (!((wr_mask
>> i
) & 1))
1600 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1601 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1602 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1603 if (new_inst
->src
[j
].file
== VGRF
)
1604 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1611 * Get the matching channel register datatype for an image intrinsic of the
1612 * specified GLSL image type.
1615 get_image_base_type(const glsl_type
*type
)
1617 switch ((glsl_base_type
)type
->sampled_type
) {
1618 case GLSL_TYPE_UINT
:
1619 return BRW_REGISTER_TYPE_UD
;
1621 return BRW_REGISTER_TYPE_D
;
1622 case GLSL_TYPE_FLOAT
:
1623 return BRW_REGISTER_TYPE_F
;
1625 unreachable("Not reached.");
1630 * Get the appropriate atomic op for an image atomic intrinsic.
1633 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1636 case nir_intrinsic_image_atomic_add
:
1638 case nir_intrinsic_image_atomic_min
:
1639 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1640 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1641 case nir_intrinsic_image_atomic_max
:
1642 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1643 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1644 case nir_intrinsic_image_atomic_and
:
1646 case nir_intrinsic_image_atomic_or
:
1648 case nir_intrinsic_image_atomic_xor
:
1650 case nir_intrinsic_image_atomic_exchange
:
1652 case nir_intrinsic_image_atomic_comp_swap
:
1653 return BRW_AOP_CMPWR
;
1655 unreachable("Not reachable.");
1660 emit_pixel_interpolater_send(const fs_builder
&bld
,
1665 glsl_interp_mode interpolation
)
1667 struct brw_wm_prog_data
*wm_prog_data
=
1668 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1673 if (src
.file
== BAD_FILE
) {
1675 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1679 mlen
= 2 * bld
.dispatch_width() / 8;
1682 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1684 /* 2 floats per slot returned */
1685 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1686 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1688 wm_prog_data
->pulls_bary
= true;
1694 * Computes 1 << x, given a D/UD register containing some value x.
1697 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1699 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1701 fs_reg result
= bld
.vgrf(x
.type
, 1);
1702 fs_reg one
= bld
.vgrf(x
.type
, 1);
1704 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1705 bld
.SHL(result
, one
, x
);
1710 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1712 assert(stage
== MESA_SHADER_GEOMETRY
);
1714 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1716 if (gs_compile
->control_data_header_size_bits
== 0)
1719 /* We can only do EndPrimitive() functionality when the control data
1720 * consists of cut bits. Fortunately, the only time it isn't is when the
1721 * output type is points, in which case EndPrimitive() is a no-op.
1723 if (gs_prog_data
->control_data_format
!=
1724 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1728 /* Cut bits use one bit per vertex. */
1729 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1731 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1732 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1734 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1735 * vertex n, 0 otherwise. So all we need to do here is mark bit
1736 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1737 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1738 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1740 * Note that if EndPrimitive() is called before emitting any vertices, this
1741 * will cause us to set bit 31 of the control_data_bits register to 1.
1742 * That's fine because:
1744 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1745 * output, so the hardware will ignore cut bit 31.
1747 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1748 * last vertex, so setting cut bit 31 has no effect (since the primitive
1749 * is automatically ended when the GS terminates).
1751 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1752 * control_data_bits register to 0 when the first vertex is emitted.
1755 const fs_builder abld
= bld
.annotate("end primitive");
1757 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1758 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1759 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1760 fs_reg mask
= intexp2(abld
, prev_count
);
1761 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1762 * attention to the lower 5 bits of its second source argument, so on this
1763 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1764 * ((vertex_count - 1) % 32).
1766 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1770 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1772 assert(stage
== MESA_SHADER_GEOMETRY
);
1773 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1775 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1777 const fs_builder abld
= bld
.annotate("emit control data bits");
1778 const fs_builder fwa_bld
= bld
.exec_all();
1780 /* We use a single UD register to accumulate control data bits (32 bits
1781 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1784 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1785 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1786 * use the Channel Mask phase to enable/disable which DWord within that
1787 * group to write. (Remember, different SIMD8 channels may have emitted
1788 * different numbers of vertices, so we may need per-slot offsets.)
1790 * Channel masking presents an annoying problem: we may have to replicate
1791 * the data up to 4 times:
1793 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1795 * To avoid penalizing shaders that emit a small number of vertices, we
1796 * can avoid these sometimes: if the size of the control data header is
1797 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1798 * land in the same 128-bit group, so we can skip per-slot offsets.
1800 * Similarly, if the control data header is <= 32 bits, there is only one
1801 * DWord, so we can skip channel masks.
1803 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1805 fs_reg channel_mask
, per_slot_offset
;
1807 if (gs_compile
->control_data_header_size_bits
> 32) {
1808 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1809 channel_mask
= vgrf(glsl_type::uint_type
);
1812 if (gs_compile
->control_data_header_size_bits
> 128) {
1813 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1814 per_slot_offset
= vgrf(glsl_type::uint_type
);
1817 /* Figure out which DWord we're trying to write to using the formula:
1819 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1821 * Since bits_per_vertex is a power of two, and is known at compile
1822 * time, this can be optimized to:
1824 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1826 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1827 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1828 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1829 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1830 unsigned log2_bits_per_vertex
=
1831 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1832 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1834 if (per_slot_offset
.file
!= BAD_FILE
) {
1835 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1836 * the appropriate OWord within the control data header.
1838 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1841 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1842 * write to the appropriate DWORD within the OWORD.
1844 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1845 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1846 channel_mask
= intexp2(fwa_bld
, channel
);
1847 /* Then the channel masks need to be in bits 23:16. */
1848 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1851 /* Store the control data bits in the message payload and send it. */
1853 if (channel_mask
.file
!= BAD_FILE
)
1854 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1855 if (per_slot_offset
.file
!= BAD_FILE
)
1858 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1859 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1861 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1862 if (per_slot_offset
.file
!= BAD_FILE
)
1863 sources
[i
++] = per_slot_offset
;
1864 if (channel_mask
.file
!= BAD_FILE
)
1865 sources
[i
++] = channel_mask
;
1867 sources
[i
++] = this->control_data_bits
;
1870 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1871 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1873 /* We need to increment Global Offset by 256-bits to make room for
1874 * Broadwell's extra "Vertex Count" payload at the beginning of the
1875 * URB entry. Since this is an OWord message, Global Offset is counted
1876 * in 128-bit units, so we must set it to 2.
1878 if (gs_prog_data
->static_vertex_count
== -1)
1883 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1886 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1888 /* Note: we are calling this *before* increasing vertex_count, so
1889 * this->vertex_count == vertex_count - 1 in the formula above.
1892 /* Stream mode uses 2 bits per vertex */
1893 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1895 /* Must be a valid stream */
1896 assert(stream_id
< MAX_VERTEX_STREAMS
);
1898 /* Control data bits are initialized to 0 so we don't have to set any
1899 * bits when sending vertices to stream 0.
1904 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1906 /* reg::sid = stream_id */
1907 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1908 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1910 /* reg:shift_count = 2 * (vertex_count - 1) */
1911 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1912 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1914 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1915 * attention to the lower 5 bits of its second source argument, so on this
1916 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1917 * stream_id << ((2 * (vertex_count - 1)) % 32).
1919 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1920 abld
.SHL(mask
, sid
, shift_count
);
1921 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1925 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1928 assert(stage
== MESA_SHADER_GEOMETRY
);
1930 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1932 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1933 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1935 /* Haswell and later hardware ignores the "Render Stream Select" bits
1936 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1937 * and instead sends all primitives down the pipeline for rasterization.
1938 * If the SOL stage is enabled, "Render Stream Select" is honored and
1939 * primitives bound to non-zero streams are discarded after stream output.
1941 * Since the only purpose of primives sent to non-zero streams is to
1942 * be recorded by transform feedback, we can simply discard all geometry
1943 * bound to these streams when transform feedback is disabled.
1945 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1948 /* If we're outputting 32 control data bits or less, then we can wait
1949 * until the shader is over to output them all. Otherwise we need to
1950 * output them as we go. Now is the time to do it, since we're about to
1951 * output the vertex_count'th vertex, so it's guaranteed that the
1952 * control data bits associated with the (vertex_count - 1)th vertex are
1955 if (gs_compile
->control_data_header_size_bits
> 32) {
1956 const fs_builder abld
=
1957 bld
.annotate("emit vertex: emit control data bits");
1959 /* Only emit control data bits if we've finished accumulating a batch
1960 * of 32 bits. This is the case when:
1962 * (vertex_count * bits_per_vertex) % 32 == 0
1964 * (in other words, when the last 5 bits of vertex_count *
1965 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1966 * integer n (which is always the case, since bits_per_vertex is
1967 * always 1 or 2), this is equivalent to requiring that the last 5-n
1968 * bits of vertex_count are 0:
1970 * vertex_count & (2^(5-n) - 1) == 0
1972 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1975 * vertex_count & (32 / bits_per_vertex - 1) == 0
1977 * TODO: If vertex_count is an immediate, we could do some of this math
1978 * at compile time...
1981 abld
.AND(bld
.null_reg_d(), vertex_count
,
1982 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1983 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1985 abld
.IF(BRW_PREDICATE_NORMAL
);
1986 /* If vertex_count is 0, then no control data bits have been
1987 * accumulated yet, so we can skip emitting them.
1989 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1990 BRW_CONDITIONAL_NEQ
);
1991 abld
.IF(BRW_PREDICATE_NORMAL
);
1992 emit_gs_control_data_bits(vertex_count
);
1993 abld
.emit(BRW_OPCODE_ENDIF
);
1995 /* Reset control_data_bits to 0 so we can start accumulating a new
1998 * Note: in the case where vertex_count == 0, this neutralizes the
1999 * effect of any call to EndPrimitive() that the shader may have
2000 * made before outputting its first vertex.
2002 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2003 inst
->force_writemask_all
= true;
2004 abld
.emit(BRW_OPCODE_ENDIF
);
2007 emit_urb_writes(vertex_count
);
2009 /* In stream mode we have to set control data bits for all vertices
2010 * unless we have disabled control data bits completely (which we do
2011 * do for GL_POINTS outputs that don't use streams).
2013 if (gs_compile
->control_data_header_size_bits
> 0 &&
2014 gs_prog_data
->control_data_format
==
2015 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2016 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2021 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2022 const nir_src
&vertex_src
,
2023 unsigned base_offset
,
2024 const nir_src
&offset_src
,
2025 unsigned num_components
,
2026 unsigned first_component
)
2028 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2030 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2031 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2032 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2034 /* TODO: figure out push input layout for invocations == 1 */
2035 /* TODO: make this work with 64-bit inputs */
2036 if (gs_prog_data
->invocations
== 1 &&
2037 type_sz(dst
.type
) <= 4 &&
2038 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2039 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2040 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2041 vertex_const
->u32
[0] * push_reg_count
;
2042 for (unsigned i
= 0; i
< num_components
; i
++) {
2043 bld
.MOV(offset(dst
, bld
, i
),
2044 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2049 /* Resort to the pull model. Ensure the VUE handles are provided. */
2050 assert(gs_prog_data
->base
.include_vue_handles
);
2052 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2053 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2055 if (gs_prog_data
->invocations
== 1) {
2057 /* The vertex index is constant; just select the proper URB handle. */
2059 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2060 BRW_REGISTER_TYPE_UD
);
2062 /* The vertex index is non-constant. We need to use indirect
2063 * addressing to fetch the proper URB handle.
2065 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2066 * indicating that channel <n> should read the handle from
2067 * DWord <n>. We convert that to bytes by multiplying by 4.
2069 * Next, we convert the vertex index to bytes by multiplying
2070 * by 32 (shifting by 5), and add the two together. This is
2071 * the final indirect byte offset.
2073 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2074 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2075 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2076 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2078 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2079 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2080 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2081 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2082 /* Convert vertex_index to bytes (multiply by 32) */
2083 bld
.SHL(vertex_offset_bytes
,
2084 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2086 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2088 /* Use first_icp_handle as the base offset. There is one register
2089 * of URB handles per vertex, so inform the register allocator that
2090 * we might read up to nir->info.gs.vertices_in registers.
2092 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2093 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2094 fs_reg(icp_offset_bytes
),
2095 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2098 assert(gs_prog_data
->invocations
> 1);
2101 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2103 retype(brw_vec1_grf(first_icp_handle
+
2104 vertex_const
->i32
[0] / 8,
2105 vertex_const
->i32
[0] % 8),
2106 BRW_REGISTER_TYPE_UD
));
2108 /* The vertex index is non-constant. We need to use indirect
2109 * addressing to fetch the proper URB handle.
2112 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2114 /* Convert vertex_index to bytes (multiply by 4) */
2115 bld
.SHL(icp_offset_bytes
,
2116 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2119 /* Use first_icp_handle as the base offset. There is one DWord
2120 * of URB handles per vertex, so inform the register allocator that
2121 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2123 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2124 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2125 fs_reg(icp_offset_bytes
),
2126 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2133 fs_reg tmp_dst
= dst
;
2134 fs_reg indirect_offset
= get_nir_src(offset_src
);
2135 unsigned num_iterations
= 1;
2136 unsigned orig_num_components
= num_components
;
2138 if (type_sz(dst
.type
) == 8) {
2139 if (num_components
> 2) {
2143 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2145 first_component
= first_component
/ 2;
2148 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2150 /* Constant indexing - use global offset. */
2151 if (first_component
!= 0) {
2152 unsigned read_components
= num_components
+ first_component
;
2153 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2154 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2155 inst
->size_written
= read_components
*
2156 tmp
.component_size(inst
->exec_size
);
2157 for (unsigned i
= 0; i
< num_components
; i
++) {
2158 bld
.MOV(offset(tmp_dst
, bld
, i
),
2159 offset(tmp
, bld
, i
+ first_component
));
2162 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2164 inst
->size_written
= num_components
*
2165 tmp_dst
.component_size(inst
->exec_size
);
2167 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2170 /* Indirect indexing - use per-slot offsets as well. */
2171 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2172 unsigned read_components
= num_components
+ first_component
;
2173 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2174 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2175 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2176 if (first_component
!= 0) {
2177 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2179 inst
->size_written
= read_components
*
2180 tmp
.component_size(inst
->exec_size
);
2181 for (unsigned i
= 0; i
< num_components
; i
++) {
2182 bld
.MOV(offset(tmp_dst
, bld
, i
),
2183 offset(tmp
, bld
, i
+ first_component
));
2186 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2188 inst
->size_written
= num_components
*
2189 tmp_dst
.component_size(inst
->exec_size
);
2191 inst
->offset
= base_offset
;
2195 if (type_sz(dst
.type
) == 8) {
2196 shuffle_32bit_load_result_to_64bit_data(
2197 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2199 for (unsigned c
= 0; c
< num_components
; c
++)
2200 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2203 if (num_iterations
> 1) {
2204 num_components
= orig_num_components
- 2;
2208 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2209 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2210 indirect_offset
= new_indirect
;
2217 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2219 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2220 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2223 /* The only constant offset we should find is 0. brw_nir.c's
2224 * add_const_offset_to_base() will fold other constant offsets
2225 * into instr->const_index[0].
2227 assert(const_value
->u32
[0] == 0);
2231 return get_nir_src(*offset_src
);
2235 do_untyped_vector_read(const fs_builder
&bld
,
2237 const fs_reg surf_index
,
2238 const fs_reg offset_reg
,
2239 unsigned num_components
)
2241 if (type_sz(dest
.type
) == 4) {
2242 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2245 BRW_PREDICATE_NONE
);
2246 read_result
.type
= dest
.type
;
2247 for (unsigned i
= 0; i
< num_components
; i
++)
2248 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2249 } else if (type_sz(dest
.type
) == 8) {
2250 /* Reading a dvec, so we need to:
2252 * 1. Multiply num_components by 2, to account for the fact that we
2253 * need to read 64-bit components.
2254 * 2. Shuffle the result of the load to form valid 64-bit elements
2255 * 3. Emit a second load (for components z/w) if needed.
2257 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2258 bld
.MOV(read_offset
, offset_reg
);
2260 int iters
= num_components
<= 2 ? 1 : 2;
2262 /* Load the dvec, the first iteration loads components x/y, the second
2263 * iteration, if needed, loads components z/w
2265 for (int it
= 0; it
< iters
; it
++) {
2266 /* Compute number of components to read in this iteration */
2267 int iter_components
= MIN2(2, num_components
);
2268 num_components
-= iter_components
;
2270 /* Read. Since this message reads 32-bit components, we need to
2271 * read twice as many components.
2273 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2275 iter_components
* 2,
2276 BRW_PREDICATE_NONE
);
2278 /* Shuffle the 32-bit load result into valid 64-bit data */
2279 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2280 shuffle_32bit_load_result_to_64bit_data(
2281 bld
, packed_result
, read_result
, iter_components
);
2283 /* Move each component to its destination */
2284 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2285 for (int c
= 0; c
< iter_components
; c
++) {
2286 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2287 offset(packed_result
, bld
, c
));
2290 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2293 unreachable("Unsupported type");
2298 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2299 nir_intrinsic_instr
*instr
)
2301 assert(stage
== MESA_SHADER_VERTEX
);
2304 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2305 dest
= get_nir_dest(instr
->dest
);
2307 switch (instr
->intrinsic
) {
2308 case nir_intrinsic_load_vertex_id
:
2309 unreachable("should be lowered by lower_vertex_id()");
2311 case nir_intrinsic_load_vertex_id_zero_base
:
2312 case nir_intrinsic_load_base_vertex
:
2313 case nir_intrinsic_load_instance_id
:
2314 case nir_intrinsic_load_base_instance
:
2315 case nir_intrinsic_load_draw_id
: {
2316 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2317 fs_reg val
= nir_system_values
[sv
];
2318 assert(val
.file
!= BAD_FILE
);
2319 dest
.type
= val
.type
;
2324 case nir_intrinsic_load_input
: {
2325 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2326 unsigned first_component
= nir_intrinsic_component(instr
);
2327 unsigned num_components
= instr
->num_components
;
2328 enum brw_reg_type type
= dest
.type
;
2330 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2331 assert(const_offset
&& "Indirect input loads not allowed");
2332 src
= offset(src
, bld
, const_offset
->u32
[0]);
2334 for (unsigned j
= 0; j
< num_components
; j
++) {
2335 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2338 if (type
== BRW_REGISTER_TYPE_DF
) {
2339 /* Once the double vector is read, set again its original register
2340 * type to continue with normal execution.
2342 src
= retype(src
, type
);
2343 dest
= retype(dest
, type
);
2346 if (type_sz(src
.type
) == 8) {
2347 shuffle_32bit_load_result_to_64bit_data(bld
,
2349 retype(dest
, BRW_REGISTER_TYPE_F
),
2350 instr
->num_components
);
2356 nir_emit_intrinsic(bld
, instr
);
2362 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2363 nir_intrinsic_instr
*instr
)
2365 assert(stage
== MESA_SHADER_TESS_CTRL
);
2366 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2367 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2370 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2371 dst
= get_nir_dest(instr
->dest
);
2373 switch (instr
->intrinsic
) {
2374 case nir_intrinsic_load_primitive_id
:
2375 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2377 case nir_intrinsic_load_invocation_id
:
2378 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2380 case nir_intrinsic_load_patch_vertices_in
:
2381 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2382 brw_imm_d(tcs_key
->input_vertices
));
2385 case nir_intrinsic_barrier
: {
2386 if (tcs_prog_data
->instances
== 1)
2389 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2390 fs_reg m0_2
= component(m0
, 2);
2392 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2394 /* Zero the message header */
2395 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2397 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2398 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2399 brw_imm_ud(INTEL_MASK(16, 13)));
2401 /* Shift it up to bits 27:24. */
2402 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2404 /* Set the Barrier Count and the enable bit */
2405 chanbld
.OR(m0_2
, m0_2
,
2406 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2408 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2412 case nir_intrinsic_load_input
:
2413 unreachable("nir_lower_io should never give us these.");
2416 case nir_intrinsic_load_per_vertex_input
: {
2417 fs_reg indirect_offset
= get_indirect_offset(instr
);
2418 unsigned imm_offset
= instr
->const_index
[0];
2420 const nir_src
&vertex_src
= instr
->src
[0];
2421 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2428 /* Emit a MOV to resolve <0,1,0> regioning. */
2429 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2431 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2432 vertex_const
->i32
[0] & 7),
2433 BRW_REGISTER_TYPE_UD
));
2434 } else if (tcs_prog_data
->instances
== 1 &&
2435 vertex_src
.is_ssa
&&
2436 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2437 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2438 /* For the common case of only 1 instance, an array index of
2439 * gl_InvocationID means reading g1. Skip all the indirect work.
2441 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2443 /* The vertex index is non-constant. We need to use indirect
2444 * addressing to fetch the proper URB handle.
2446 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2448 /* Each ICP handle is a single DWord (4 bytes) */
2449 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2450 bld
.SHL(vertex_offset_bytes
,
2451 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2454 /* Start at g1. We might read up to 4 registers. */
2455 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2456 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2457 brw_imm_ud(4 * REG_SIZE
));
2460 /* We can only read two double components with each URB read, so
2461 * we send two read messages in that case, each one loading up to
2462 * two double components.
2464 unsigned num_iterations
= 1;
2465 unsigned num_components
= instr
->num_components
;
2466 unsigned first_component
= nir_intrinsic_component(instr
);
2467 fs_reg orig_dst
= dst
;
2468 if (type_sz(dst
.type
) == 8) {
2469 first_component
= first_component
/ 2;
2470 if (instr
->num_components
> 2) {
2475 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2479 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2480 if (indirect_offset
.file
== BAD_FILE
) {
2481 /* Constant indexing - use global offset. */
2482 if (first_component
!= 0) {
2483 unsigned read_components
= num_components
+ first_component
;
2484 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2485 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2486 for (unsigned i
= 0; i
< num_components
; i
++) {
2487 bld
.MOV(offset(dst
, bld
, i
),
2488 offset(tmp
, bld
, i
+ first_component
));
2491 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2493 inst
->offset
= imm_offset
;
2496 /* Indirect indexing - use per-slot offsets as well. */
2497 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2498 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2499 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2500 if (first_component
!= 0) {
2501 unsigned read_components
= num_components
+ first_component
;
2502 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2503 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2505 for (unsigned i
= 0; i
< num_components
; i
++) {
2506 bld
.MOV(offset(dst
, bld
, i
),
2507 offset(tmp
, bld
, i
+ first_component
));
2510 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2513 inst
->offset
= imm_offset
;
2516 inst
->size_written
= (num_components
+ first_component
) *
2517 inst
->dst
.component_size(inst
->exec_size
);
2519 /* If we are reading 64-bit data using 32-bit read messages we need
2520 * build proper 64-bit data elements by shuffling the low and high
2521 * 32-bit components around like we do for other things like UBOs
2524 if (type_sz(dst
.type
) == 8) {
2525 shuffle_32bit_load_result_to_64bit_data(
2526 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2528 for (unsigned c
= 0; c
< num_components
; c
++) {
2529 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2530 offset(dst
, bld
, c
));
2534 /* Copy the temporary to the destination to deal with writemasking.
2536 * Also attempt to deal with gl_PointSize being in the .w component.
2538 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2539 assert(type_sz(dst
.type
) < 8);
2540 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2541 inst
->size_written
= 4 * REG_SIZE
;
2542 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2545 /* If we are loading double data and we need a second read message
2546 * adjust the write offset
2548 if (num_iterations
> 1) {
2549 num_components
= instr
->num_components
- 2;
2556 case nir_intrinsic_load_output
:
2557 case nir_intrinsic_load_per_vertex_output
: {
2558 fs_reg indirect_offset
= get_indirect_offset(instr
);
2559 unsigned imm_offset
= instr
->const_index
[0];
2560 unsigned first_component
= nir_intrinsic_component(instr
);
2563 if (indirect_offset
.file
== BAD_FILE
) {
2564 /* Replicate the patch handle to all enabled channels */
2565 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2566 bld
.MOV(patch_handle
,
2567 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2570 if (first_component
!= 0) {
2571 unsigned read_components
=
2572 instr
->num_components
+ first_component
;
2573 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2574 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2576 inst
->size_written
= read_components
* REG_SIZE
;
2577 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2578 bld
.MOV(offset(dst
, bld
, i
),
2579 offset(tmp
, bld
, i
+ first_component
));
2582 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2584 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2586 inst
->offset
= imm_offset
;
2590 /* Indirect indexing - use per-slot offsets as well. */
2591 const fs_reg srcs
[] = {
2592 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2595 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2596 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2597 if (first_component
!= 0) {
2598 unsigned read_components
=
2599 instr
->num_components
+ first_component
;
2600 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2601 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2603 inst
->size_written
= read_components
* REG_SIZE
;
2604 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2605 bld
.MOV(offset(dst
, bld
, i
),
2606 offset(tmp
, bld
, i
+ first_component
));
2609 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2611 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2613 inst
->offset
= imm_offset
;
2619 case nir_intrinsic_store_output
:
2620 case nir_intrinsic_store_per_vertex_output
: {
2621 fs_reg value
= get_nir_src(instr
->src
[0]);
2622 bool is_64bit
= (instr
->src
[0].is_ssa
?
2623 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2624 fs_reg indirect_offset
= get_indirect_offset(instr
);
2625 unsigned imm_offset
= instr
->const_index
[0];
2626 unsigned mask
= instr
->const_index
[1];
2627 unsigned header_regs
= 0;
2629 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2631 if (indirect_offset
.file
!= BAD_FILE
) {
2632 srcs
[header_regs
++] = indirect_offset
;
2638 unsigned num_components
= util_last_bit(mask
);
2641 /* We can only pack two 64-bit components in a single message, so send
2642 * 2 messages if we have more components
2644 unsigned num_iterations
= 1;
2645 unsigned iter_components
= num_components
;
2646 unsigned first_component
= nir_intrinsic_component(instr
);
2648 first_component
= first_component
/ 2;
2649 if (instr
->num_components
> 2) {
2651 iter_components
= 2;
2655 mask
= mask
<< first_component
;
2657 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2658 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2659 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2660 opcode
= indirect_offset
.file
!= BAD_FILE
?
2661 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2662 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2663 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2664 /* Expand the 64-bit mask to 32-bit channels. We only handle
2665 * two channels in each iteration, so we only care about X/Y.
2667 unsigned mask32
= 0;
2668 if (mask
& WRITEMASK_X
)
2669 mask32
|= WRITEMASK_XY
;
2670 if (mask
& WRITEMASK_Y
)
2671 mask32
|= WRITEMASK_ZW
;
2673 /* If the mask does not include any of the channels X or Y there
2674 * is nothing to do in this iteration. Move on to the next couple
2675 * of 64-bit channels.
2683 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2684 opcode
= indirect_offset
.file
!= BAD_FILE
?
2685 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2686 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2688 opcode
= indirect_offset
.file
!= BAD_FILE
?
2689 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2690 SHADER_OPCODE_URB_WRITE_SIMD8
;
2693 for (unsigned i
= 0; i
< iter_components
; i
++) {
2694 if (!(mask
& (1 << (i
+ first_component
))))
2698 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2700 /* We need to shuffle the 64-bit data to match the layout
2701 * expected by our 32-bit URB write messages. We use a temporary
2704 unsigned channel
= iter
* 2 + i
;
2705 fs_reg dest
= shuffle_64bit_data_for_32bit_write(bld
,
2706 offset(value
, bld
, channel
), 1);
2708 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2709 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2710 offset(dest
, bld
, 1);
2715 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2716 (is_64bit
? 2 * first_component
: first_component
);
2718 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2719 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2721 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2722 inst
->offset
= imm_offset
;
2725 /* If this is a 64-bit attribute, select the next two 64-bit channels
2726 * to be handled in the next iteration.
2737 nir_emit_intrinsic(bld
, instr
);
2743 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2744 nir_intrinsic_instr
*instr
)
2746 assert(stage
== MESA_SHADER_TESS_EVAL
);
2747 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2750 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2751 dest
= get_nir_dest(instr
->dest
);
2753 switch (instr
->intrinsic
) {
2754 case nir_intrinsic_load_primitive_id
:
2755 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2757 case nir_intrinsic_load_tess_coord
:
2758 /* gl_TessCoord is part of the payload in g1-3 */
2759 for (unsigned i
= 0; i
< 3; i
++) {
2760 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2764 case nir_intrinsic_load_input
:
2765 case nir_intrinsic_load_per_vertex_input
: {
2766 fs_reg indirect_offset
= get_indirect_offset(instr
);
2767 unsigned imm_offset
= instr
->const_index
[0];
2768 unsigned first_component
= nir_intrinsic_component(instr
);
2770 if (type_sz(dest
.type
) == 8) {
2771 first_component
= first_component
/ 2;
2775 if (indirect_offset
.file
== BAD_FILE
) {
2776 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2777 * which is 16 registers (since each holds 2 vec4 slots).
2779 unsigned slot_count
= 1;
2780 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2783 const unsigned max_push_slots
= 32;
2784 if (imm_offset
+ slot_count
<= max_push_slots
) {
2785 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2786 for (int i
= 0; i
< instr
->num_components
; i
++) {
2787 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2788 i
+ first_component
;
2789 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2792 tes_prog_data
->base
.urb_read_length
=
2793 MAX2(tes_prog_data
->base
.urb_read_length
,
2794 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2796 /* Replicate the patch handle to all enabled channels */
2797 const fs_reg srcs
[] = {
2798 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2800 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2801 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2803 if (first_component
!= 0) {
2804 unsigned read_components
=
2805 instr
->num_components
+ first_component
;
2806 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2807 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2809 inst
->size_written
= read_components
* REG_SIZE
;
2810 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2811 bld
.MOV(offset(dest
, bld
, i
),
2812 offset(tmp
, bld
, i
+ first_component
));
2815 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2817 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2820 inst
->offset
= imm_offset
;
2823 /* Indirect indexing - use per-slot offsets as well. */
2825 /* We can only read two double components with each URB read, so
2826 * we send two read messages in that case, each one loading up to
2827 * two double components.
2829 unsigned num_iterations
= 1;
2830 unsigned num_components
= instr
->num_components
;
2831 fs_reg orig_dest
= dest
;
2832 if (type_sz(dest
.type
) == 8) {
2833 if (instr
->num_components
> 2) {
2837 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2841 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2842 const fs_reg srcs
[] = {
2843 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2846 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2847 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2849 if (first_component
!= 0) {
2850 unsigned read_components
=
2851 num_components
+ first_component
;
2852 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2853 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2855 for (unsigned i
= 0; i
< num_components
; i
++) {
2856 bld
.MOV(offset(dest
, bld
, i
),
2857 offset(tmp
, bld
, i
+ first_component
));
2860 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2864 inst
->offset
= imm_offset
;
2865 inst
->size_written
= (num_components
+ first_component
) *
2866 inst
->dst
.component_size(inst
->exec_size
);
2868 /* If we are reading 64-bit data using 32-bit read messages we need
2869 * build proper 64-bit data elements by shuffling the low and high
2870 * 32-bit components around like we do for other things like UBOs
2873 if (type_sz(dest
.type
) == 8) {
2874 shuffle_32bit_load_result_to_64bit_data(
2875 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2877 for (unsigned c
= 0; c
< num_components
; c
++) {
2878 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2879 offset(dest
, bld
, c
));
2883 /* If we are loading double data and we need a second read message
2886 if (num_iterations
> 1) {
2887 num_components
= instr
->num_components
- 2;
2895 nir_emit_intrinsic(bld
, instr
);
2901 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2902 nir_intrinsic_instr
*instr
)
2904 assert(stage
== MESA_SHADER_GEOMETRY
);
2905 fs_reg indirect_offset
;
2908 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2909 dest
= get_nir_dest(instr
->dest
);
2911 switch (instr
->intrinsic
) {
2912 case nir_intrinsic_load_primitive_id
:
2913 assert(stage
== MESA_SHADER_GEOMETRY
);
2914 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2915 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2916 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2919 case nir_intrinsic_load_input
:
2920 unreachable("load_input intrinsics are invalid for the GS stage");
2922 case nir_intrinsic_load_per_vertex_input
:
2923 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2924 instr
->src
[1], instr
->num_components
,
2925 nir_intrinsic_component(instr
));
2928 case nir_intrinsic_emit_vertex_with_counter
:
2929 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2932 case nir_intrinsic_end_primitive_with_counter
:
2933 emit_gs_end_primitive(instr
->src
[0]);
2936 case nir_intrinsic_set_vertex_count
:
2937 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2940 case nir_intrinsic_load_invocation_id
: {
2941 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2942 assert(val
.file
!= BAD_FILE
);
2943 dest
.type
= val
.type
;
2949 nir_emit_intrinsic(bld
, instr
);
2955 * Fetch the current render target layer index.
2958 fetch_render_target_array_index(const fs_builder
&bld
)
2960 if (bld
.shader
->devinfo
->gen
>= 6) {
2961 /* The render target array index is provided in the thread payload as
2962 * bits 26:16 of r0.0.
2964 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2965 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2969 /* Pre-SNB we only ever render into the first layer of the framebuffer
2970 * since layered rendering is not implemented.
2972 return brw_imm_ud(0);
2977 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2978 * framebuffer at the current fragment coordinates and sample index.
2981 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2984 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2986 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2987 const brw_wm_prog_key
*wm_key
=
2988 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2989 assert(!wm_key
->coherent_fb_fetch
);
2990 const struct brw_wm_prog_data
*wm_prog_data
=
2991 brw_wm_prog_data(stage_prog_data
);
2993 /* Calculate the surface index relative to the start of the texture binding
2994 * table block, since that's what the texturing messages expect.
2996 const unsigned surface
= target
+
2997 wm_prog_data
->binding_table
.render_target_read_start
-
2998 wm_prog_data
->base
.binding_table
.texture_start
;
3000 brw_mark_surface_used(
3001 bld
.shader
->stage_prog_data
,
3002 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3004 /* Calculate the fragment coordinates. */
3005 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3006 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3007 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3008 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3010 /* Calculate the sample index and MCS payload when multisampling. Luckily
3011 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3012 * shouldn't be necessary to recompile based on whether the framebuffer is
3015 if (wm_key
->multisample_fbo
&&
3016 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3017 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3019 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3020 const fs_reg mcs
= wm_key
->multisample_fbo
?
3021 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3023 /* Use either a normal or a CMS texel fetch message depending on whether
3024 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3025 * message just in case the framebuffer uses 16x multisampling, it should
3026 * be equivalent to the normal CMS fetch for lower multisampling modes.
3028 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3029 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3030 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3032 /* Emit the instruction. */
3033 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3035 brw_imm_ud(surface
), brw_imm_ud(0),
3036 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3037 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3039 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3040 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3046 * Actual coherent framebuffer read implemented using the native render target
3047 * read message. Requires SKL+.
3050 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3052 assert(bld
.shader
->devinfo
->gen
>= 9);
3053 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3054 inst
->target
= target
;
3055 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3061 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3063 if (n
&& regs
[0].file
!= BAD_FILE
) {
3067 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3069 for (unsigned i
= 0; i
< n
; i
++)
3077 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3079 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3080 const brw_wm_prog_key
*const key
=
3081 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3082 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3083 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3085 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3086 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3088 else if (l
== FRAG_RESULT_COLOR
)
3089 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3090 MAX2(key
->nr_color_regions
, 1));
3092 else if (l
== FRAG_RESULT_DEPTH
)
3093 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3095 else if (l
== FRAG_RESULT_STENCIL
)
3096 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3098 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3099 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3101 else if (l
>= FRAG_RESULT_DATA0
&&
3102 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3103 return alloc_temporary(v
->bld
, 4,
3104 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3107 unreachable("Invalid location");
3111 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3112 nir_intrinsic_instr
*instr
)
3114 assert(stage
== MESA_SHADER_FRAGMENT
);
3117 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3118 dest
= get_nir_dest(instr
->dest
);
3120 switch (instr
->intrinsic
) {
3121 case nir_intrinsic_load_front_face
:
3122 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3123 *emit_frontfacing_interpolation());
3126 case nir_intrinsic_load_sample_pos
: {
3127 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3128 assert(sample_pos
.file
!= BAD_FILE
);
3129 dest
.type
= sample_pos
.type
;
3130 bld
.MOV(dest
, sample_pos
);
3131 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3135 case nir_intrinsic_load_layer_id
:
3136 dest
.type
= BRW_REGISTER_TYPE_UD
;
3137 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3140 case nir_intrinsic_load_helper_invocation
:
3141 case nir_intrinsic_load_sample_mask_in
:
3142 case nir_intrinsic_load_sample_id
: {
3143 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3144 fs_reg val
= nir_system_values
[sv
];
3145 assert(val
.file
!= BAD_FILE
);
3146 dest
.type
= val
.type
;
3151 case nir_intrinsic_store_output
: {
3152 const fs_reg src
= get_nir_src(instr
->src
[0]);
3153 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3154 assert(const_offset
&& "Indirect output stores not allowed");
3155 const unsigned location
= nir_intrinsic_base(instr
) +
3156 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3157 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3160 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3161 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3162 offset(src
, bld
, j
));
3167 case nir_intrinsic_load_output
: {
3168 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3169 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3170 assert(l
>= FRAG_RESULT_DATA0
);
3171 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3172 assert(const_offset
&& "Indirect output loads not allowed");
3173 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3174 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3176 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3177 emit_coherent_fb_read(bld
, tmp
, target
);
3179 emit_non_coherent_fb_read(bld
, tmp
, target
);
3181 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3182 bld
.MOV(offset(dest
, bld
, j
),
3183 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3189 case nir_intrinsic_discard
:
3190 case nir_intrinsic_discard_if
: {
3191 /* We track our discarded pixels in f0.1. By predicating on it, we can
3192 * update just the flag bits that aren't yet discarded. If there's no
3193 * condition, we emit a CMP of g0 != g0, so all currently executing
3194 * channels will get turned off.
3197 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3198 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3199 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3201 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3202 BRW_REGISTER_TYPE_UW
));
3203 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3205 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3206 cmp
->flag_subreg
= 1;
3208 if (devinfo
->gen
>= 6) {
3209 emit_discard_jump();
3214 case nir_intrinsic_load_input
: {
3215 /* load_input is only used for flat inputs */
3216 unsigned base
= nir_intrinsic_base(instr
);
3217 unsigned component
= nir_intrinsic_component(instr
);
3218 unsigned num_components
= instr
->num_components
;
3219 enum brw_reg_type type
= dest
.type
;
3221 /* Special case fields in the VUE header */
3222 if (base
== VARYING_SLOT_LAYER
)
3224 else if (base
== VARYING_SLOT_VIEWPORT
)
3227 if (nir_dest_bit_size(instr
->dest
) == 64) {
3228 /* const_index is in 32-bit type size units that could not be aligned
3229 * with DF. We need to read the double vector as if it was a float
3230 * vector of twice the number of components to fetch the right data.
3232 type
= BRW_REGISTER_TYPE_F
;
3233 num_components
*= 2;
3236 for (unsigned int i
= 0; i
< num_components
; i
++) {
3237 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3238 interp
= suboffset(interp
, 3);
3239 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3240 retype(fs_reg(interp
), type
));
3243 if (nir_dest_bit_size(instr
->dest
) == 64) {
3244 shuffle_32bit_load_result_to_64bit_data(bld
,
3247 instr
->num_components
);
3252 case nir_intrinsic_load_barycentric_pixel
:
3253 case nir_intrinsic_load_barycentric_centroid
:
3254 case nir_intrinsic_load_barycentric_sample
:
3255 /* Do nothing - load_interpolated_input handling will handle it later. */
3258 case nir_intrinsic_load_barycentric_at_sample
: {
3259 const glsl_interp_mode interpolation
=
3260 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3262 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3265 unsigned msg_data
= const_sample
->i32
[0] << 4;
3267 emit_pixel_interpolater_send(bld
,
3268 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3271 brw_imm_ud(msg_data
),
3274 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3275 BRW_REGISTER_TYPE_UD
);
3277 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3278 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3279 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3280 bld
.exec_all().group(1, 0)
3281 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3282 emit_pixel_interpolater_send(bld
,
3283 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3289 /* Make a loop that sends a message to the pixel interpolater
3290 * for the sample number in each live channel. If there are
3291 * multiple channels with the same sample number then these
3292 * will be handled simultaneously with a single interation of
3295 bld
.emit(BRW_OPCODE_DO
);
3297 /* Get the next live sample number into sample_id_reg */
3298 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3300 /* Set the flag register so that we can perform the send
3301 * message on all channels that have the same sample number
3303 bld
.CMP(bld
.null_reg_ud(),
3304 sample_src
, sample_id
,
3305 BRW_CONDITIONAL_EQ
);
3306 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3307 bld
.exec_all().group(1, 0)
3308 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3310 emit_pixel_interpolater_send(bld
,
3311 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3316 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3318 /* Continue the loop if there are any live channels left */
3319 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3321 bld
.emit(BRW_OPCODE_WHILE
));
3327 case nir_intrinsic_load_barycentric_at_offset
: {
3328 const glsl_interp_mode interpolation
=
3329 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3331 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3334 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3335 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3337 emit_pixel_interpolater_send(bld
,
3338 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3341 brw_imm_ud(off_x
| (off_y
<< 4)),
3344 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3345 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3346 BRW_REGISTER_TYPE_F
);
3347 for (int i
= 0; i
< 2; i
++) {
3348 fs_reg temp
= vgrf(glsl_type::float_type
);
3349 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3350 fs_reg itemp
= vgrf(glsl_type::int_type
);
3352 bld
.MOV(itemp
, temp
);
3354 /* Clamp the upper end of the range to +7/16.
3355 * ARB_gpu_shader5 requires that we support a maximum offset
3356 * of +0.5, which isn't representable in a S0.4 value -- if
3357 * we didn't clamp it, we'd end up with -8/16, which is the
3358 * opposite of what the shader author wanted.
3360 * This is legal due to ARB_gpu_shader5's quantization
3363 * "Not all values of <offset> may be supported; x and y
3364 * offsets may be rounded to fixed-point values with the
3365 * number of fraction bits given by the
3366 * implementation-dependent constant
3367 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3369 set_condmod(BRW_CONDITIONAL_L
,
3370 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3373 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3374 emit_pixel_interpolater_send(bld
,
3384 case nir_intrinsic_load_interpolated_input
: {
3385 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3386 emit_fragcoord_interpolation(dest
);
3390 assert(instr
->src
[0].ssa
&&
3391 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3392 nir_intrinsic_instr
*bary_intrinsic
=
3393 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3394 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3395 enum glsl_interp_mode interp_mode
=
3396 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3399 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3400 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3401 /* Use the result of the PI message */
3402 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3404 /* Use the delta_xy values computed from the payload */
3405 enum brw_barycentric_mode bary
=
3406 brw_barycentric_mode(interp_mode
, bary_intrin
);
3408 dst_xy
= this->delta_xy
[bary
];
3411 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3413 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3414 nir_intrinsic_component(instr
) + i
));
3415 interp
.type
= BRW_REGISTER_TYPE_F
;
3416 dest
.type
= BRW_REGISTER_TYPE_F
;
3418 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3419 fs_reg tmp
= vgrf(glsl_type::float_type
);
3420 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3421 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3423 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3430 nir_emit_intrinsic(bld
, instr
);
3436 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3437 nir_intrinsic_instr
*instr
)
3439 assert(stage
== MESA_SHADER_COMPUTE
);
3440 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3443 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3444 dest
= get_nir_dest(instr
->dest
);
3446 switch (instr
->intrinsic
) {
3447 case nir_intrinsic_barrier
:
3449 cs_prog_data
->uses_barrier
= true;
3452 case nir_intrinsic_load_subgroup_id
:
3453 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3456 case nir_intrinsic_load_local_invocation_id
:
3457 case nir_intrinsic_load_work_group_id
: {
3458 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3459 fs_reg val
= nir_system_values
[sv
];
3460 assert(val
.file
!= BAD_FILE
);
3461 dest
.type
= val
.type
;
3462 for (unsigned i
= 0; i
< 3; i
++)
3463 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3467 case nir_intrinsic_load_num_work_groups
: {
3468 const unsigned surface
=
3469 cs_prog_data
->binding_table
.work_groups_start
;
3471 cs_prog_data
->uses_num_work_groups
= true;
3473 fs_reg surf_index
= brw_imm_ud(surface
);
3474 brw_mark_surface_used(prog_data
, surface
);
3476 /* Read the 3 GLuint components of gl_NumWorkGroups */
3477 for (unsigned i
= 0; i
< 3; i
++) {
3478 fs_reg read_result
=
3479 emit_untyped_read(bld
, surf_index
,
3481 1 /* dims */, 1 /* size */,
3482 BRW_PREDICATE_NONE
);
3483 read_result
.type
= dest
.type
;
3484 bld
.MOV(dest
, read_result
);
3485 dest
= offset(dest
, bld
, 1);
3490 case nir_intrinsic_shared_atomic_add
:
3491 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3493 case nir_intrinsic_shared_atomic_imin
:
3494 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3496 case nir_intrinsic_shared_atomic_umin
:
3497 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3499 case nir_intrinsic_shared_atomic_imax
:
3500 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3502 case nir_intrinsic_shared_atomic_umax
:
3503 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3505 case nir_intrinsic_shared_atomic_and
:
3506 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3508 case nir_intrinsic_shared_atomic_or
:
3509 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3511 case nir_intrinsic_shared_atomic_xor
:
3512 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3514 case nir_intrinsic_shared_atomic_exchange
:
3515 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3517 case nir_intrinsic_shared_atomic_comp_swap
:
3518 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3521 case nir_intrinsic_load_shared
: {
3522 assert(devinfo
->gen
>= 7);
3524 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3526 /* Get the offset to read from */
3528 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3530 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3532 offset_reg
= vgrf(glsl_type::uint_type
);
3534 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3535 brw_imm_ud(instr
->const_index
[0]));
3538 /* Read the vector */
3539 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3540 instr
->num_components
);
3544 case nir_intrinsic_store_shared
: {
3545 assert(devinfo
->gen
>= 7);
3548 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3551 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3554 unsigned writemask
= instr
->const_index
[1];
3556 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3557 * since the untyped writes below operate in units of 32-bits, which
3558 * means that we need to write twice as many components each time.
3559 * Also, we have to suffle 64-bit data to be in the appropriate layout
3560 * expected by our 32-bit write messages.
3562 unsigned type_size
= 4;
3563 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3565 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
3566 val_reg
, instr
->num_components
);
3569 unsigned type_slots
= type_size
/ 4;
3571 /* Combine groups of consecutive enabled channels in one write
3572 * message. We use ffs to find the first enabled channel and then ffs on
3573 * the bit-inverse, down-shifted writemask to determine the length of
3574 * the block of enabled bits.
3577 unsigned first_component
= ffs(writemask
) - 1;
3578 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3580 /* We can't write more than 2 64-bit components at once. Limit the
3581 * length of the write to what we can do and let the next iteration
3585 length
= MIN2(2, length
);
3588 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3590 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3591 type_size
* first_component
);
3593 offset_reg
= vgrf(glsl_type::uint_type
);
3595 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3596 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3599 emit_untyped_write(bld
, surf_index
, offset_reg
,
3600 offset(val_reg
, bld
, first_component
* type_slots
),
3601 1 /* dims */, length
* type_slots
,
3602 BRW_PREDICATE_NONE
);
3604 /* Clear the bits in the writemask that we just wrote, then try
3605 * again to see if more channels are left.
3607 writemask
&= (15 << (first_component
+ length
));
3614 nir_emit_intrinsic(bld
, instr
);
3620 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3623 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3624 dest
= get_nir_dest(instr
->dest
);
3626 switch (instr
->intrinsic
) {
3627 case nir_intrinsic_atomic_counter_inc
:
3628 case nir_intrinsic_atomic_counter_dec
:
3629 case nir_intrinsic_atomic_counter_read
:
3630 case nir_intrinsic_atomic_counter_add
:
3631 case nir_intrinsic_atomic_counter_min
:
3632 case nir_intrinsic_atomic_counter_max
:
3633 case nir_intrinsic_atomic_counter_and
:
3634 case nir_intrinsic_atomic_counter_or
:
3635 case nir_intrinsic_atomic_counter_xor
:
3636 case nir_intrinsic_atomic_counter_exchange
:
3637 case nir_intrinsic_atomic_counter_comp_swap
: {
3638 if (stage
== MESA_SHADER_FRAGMENT
&&
3639 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3640 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3642 /* Get some metadata from the image intrinsic. */
3643 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3645 /* Get the arguments of the atomic intrinsic. */
3646 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3647 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3648 instr
->const_index
[0]);
3649 const fs_reg src0
= (info
->num_srcs
>= 2
3650 ? get_nir_src(instr
->src
[1]) : fs_reg());
3651 const fs_reg src1
= (info
->num_srcs
>= 3
3652 ? get_nir_src(instr
->src
[2]) : fs_reg());
3655 assert(info
->num_srcs
<= 3);
3657 /* Emit a surface read or atomic op. */
3658 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3659 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3661 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3663 get_atomic_counter_op(instr
->intrinsic
));
3666 /* Assign the result. */
3667 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3669 /* Mark the surface as used. */
3670 brw_mark_surface_used(stage_prog_data
, surface
);
3674 case nir_intrinsic_image_load
:
3675 case nir_intrinsic_image_store
:
3676 case nir_intrinsic_image_atomic_add
:
3677 case nir_intrinsic_image_atomic_min
:
3678 case nir_intrinsic_image_atomic_max
:
3679 case nir_intrinsic_image_atomic_and
:
3680 case nir_intrinsic_image_atomic_or
:
3681 case nir_intrinsic_image_atomic_xor
:
3682 case nir_intrinsic_image_atomic_exchange
:
3683 case nir_intrinsic_image_atomic_comp_swap
: {
3684 using namespace image_access
;
3686 if (stage
== MESA_SHADER_FRAGMENT
&&
3687 instr
->intrinsic
!= nir_intrinsic_image_load
)
3688 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3690 /* Get the referenced image variable and type. */
3691 const nir_variable
*var
= instr
->variables
[0]->var
;
3692 const glsl_type
*type
= var
->type
->without_array();
3693 const brw_reg_type base_type
= get_image_base_type(type
);
3695 /* Get some metadata from the image intrinsic. */
3696 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3697 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3698 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3699 const unsigned format
= var
->data
.image
.format
;
3701 /* Get the arguments of the image intrinsic. */
3702 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3703 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3704 BRW_REGISTER_TYPE_UD
);
3705 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3706 retype(get_nir_src(instr
->src
[2]), base_type
) :
3708 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3709 retype(get_nir_src(instr
->src
[3]), base_type
) :
3713 /* Emit an image load, store or atomic op. */
3714 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3715 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3717 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3718 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3719 var
->data
.image
.write_only
? GL_NONE
: format
);
3722 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3723 surf_dims
, arr_dims
, info
->dest_components
,
3724 get_image_atomic_op(instr
->intrinsic
, type
));
3726 /* Assign the result. */
3727 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3728 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3729 offset(tmp
, bld
, c
));
3733 case nir_intrinsic_memory_barrier_atomic_counter
:
3734 case nir_intrinsic_memory_barrier_buffer
:
3735 case nir_intrinsic_memory_barrier_image
:
3736 case nir_intrinsic_memory_barrier
: {
3737 const fs_builder ubld
= bld
.group(8, 0);
3738 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3739 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3740 ->size_written
= 2 * REG_SIZE
;
3744 case nir_intrinsic_group_memory_barrier
:
3745 case nir_intrinsic_memory_barrier_shared
:
3746 /* We treat these workgroup-level barriers as no-ops. This should be
3747 * safe at present and as long as:
3749 * - Memory access instructions are not subsequently reordered by the
3750 * compiler back-end.
3752 * - All threads from a given compute shader workgroup fit within a
3753 * single subslice and therefore talk to the same HDC shared unit
3754 * what supposedly guarantees ordering and coherency between threads
3755 * from the same workgroup. This may change in the future when we
3756 * start splitting workgroups across multiple subslices.
3758 * - The context is not in fault-and-stream mode, which could cause
3759 * memory transactions (including to SLM) prior to the barrier to be
3760 * replayed after the barrier if a pagefault occurs. This shouldn't
3761 * be a problem up to and including SKL because fault-and-stream is
3762 * not usable due to hardware issues, but that's likely to change in
3767 case nir_intrinsic_shader_clock
: {
3768 /* We cannot do anything if there is an event, so ignore it for now */
3769 const fs_reg shader_clock
= get_timestamp(bld
);
3770 const fs_reg srcs
[] = { component(shader_clock
, 0),
3771 component(shader_clock
, 1) };
3772 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3776 case nir_intrinsic_image_size
: {
3777 /* Get the referenced image variable and type. */
3778 const nir_variable
*var
= instr
->variables
[0]->var
;
3779 const glsl_type
*type
= var
->type
->without_array();
3781 /* Get the size of the image. */
3782 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3783 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3785 /* For 1DArray image types, the array index is stored in the Z component.
3786 * Fix this by swizzling the Z component to the Y component.
3788 const bool is_1d_array_image
=
3789 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3790 type
->sampler_array
;
3792 /* For CubeArray images, we should count the number of cubes instead
3793 * of the number of faces. Fix it by dividing the (Z component) by 6.
3795 const bool is_cube_array_image
=
3796 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3797 type
->sampler_array
;
3799 /* Copy all the components. */
3800 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3801 if ((int)c
>= type
->coordinate_components()) {
3802 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3804 } else if (c
== 1 && is_1d_array_image
) {
3805 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3806 offset(size
, bld
, 2));
3807 } else if (c
== 2 && is_cube_array_image
) {
3808 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3809 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3810 offset(size
, bld
, c
), brw_imm_d(6));
3812 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3813 offset(size
, bld
, c
));
3820 case nir_intrinsic_image_samples
:
3821 /* The driver does not support multi-sampled images. */
3822 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3825 case nir_intrinsic_load_uniform
: {
3826 /* Offsets are in bytes but they should always be multiples of 4 */
3827 assert(instr
->const_index
[0] % 4 == 0);
3829 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3831 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3833 /* Offsets are in bytes but they should always be multiples of 4 */
3834 assert(const_offset
->u32
[0] % 4 == 0);
3835 src
.offset
= const_offset
->u32
[0];
3837 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3838 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3841 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3842 BRW_REGISTER_TYPE_UD
);
3844 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3845 * go past the end of the uniform. In order to keep the n'th
3846 * component from running past, we subtract off the size of all but
3847 * one component of the vector.
3849 assert(instr
->const_index
[1] >=
3850 instr
->num_components
* (int) type_sz(dest
.type
));
3851 unsigned read_size
= instr
->const_index
[1] -
3852 (instr
->num_components
- 1) * type_sz(dest
.type
);
3854 bool supports_64bit_indirects
=
3855 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3857 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3858 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3859 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3860 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3861 indirect
, brw_imm_ud(read_size
));
3864 const unsigned num_mov_indirects
=
3865 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3866 /* We read a little bit less per MOV INDIRECT, as they are now
3867 * 32-bits ones instead of 64-bit. Fix read_size then.
3869 const unsigned read_size_32bit
= read_size
-
3870 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3871 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3872 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3873 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3874 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3875 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3876 indirect
, brw_imm_ud(read_size_32bit
));
3884 case nir_intrinsic_load_ubo
: {
3885 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3889 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3890 const_index
->u32
[0];
3891 surf_index
= brw_imm_ud(index
);
3892 brw_mark_surface_used(prog_data
, index
);
3894 /* The block index is not a constant. Evaluate the index expression
3895 * per-channel and add the base UBO index; we have to select a value
3896 * from any live channel.
3898 surf_index
= vgrf(glsl_type::uint_type
);
3899 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3900 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3901 surf_index
= bld
.emit_uniformize(surf_index
);
3903 /* Assume this may touch any UBO. It would be nice to provide
3904 * a tighter bound, but the array information is already lowered away.
3906 brw_mark_surface_used(prog_data
,
3907 stage_prog_data
->binding_table
.ubo_start
+
3908 nir
->info
.num_ubos
- 1);
3911 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3912 if (const_offset
== NULL
) {
3913 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3914 BRW_REGISTER_TYPE_UD
);
3916 for (int i
= 0; i
< instr
->num_components
; i
++)
3917 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3918 base_offset
, i
* type_sz(dest
.type
));
3920 /* Even if we are loading doubles, a pull constant load will load
3921 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3922 * need to load a full dvec4 we will have to emit 2 loads. This is
3923 * similar to demote_pull_constants(), except that in that case we
3924 * see individual accesses to each component of the vector and then
3925 * we let CSE deal with duplicate loads. Here we see a vector access
3926 * and we have to split it if necessary.
3928 const unsigned type_size
= type_sz(dest
.type
);
3930 /* See if we've selected this as a push constant candidate */
3932 const unsigned ubo_block
= const_index
->u32
[0];
3933 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
3936 for (int i
= 0; i
< 4; i
++) {
3937 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3938 if (range
->block
== ubo_block
&&
3939 offset_256b
>= range
->start
&&
3940 offset_256b
< range
->start
+ range
->length
) {
3942 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3943 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
3948 if (push_reg
.file
!= BAD_FILE
) {
3949 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3950 bld
.MOV(offset(dest
, bld
, i
),
3951 byte_offset(push_reg
, i
* type_size
));
3957 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3958 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3959 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3961 for (unsigned c
= 0; c
< instr
->num_components
;) {
3962 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3963 /* Number of usable components in the next block-aligned load. */
3964 const unsigned count
= MIN2(instr
->num_components
- c
,
3965 (block_sz
- base
% block_sz
) / type_size
);
3967 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3968 packed_consts
, surf_index
,
3969 brw_imm_ud(base
& ~(block_sz
- 1)));
3971 const fs_reg consts
=
3972 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3975 for (unsigned d
= 0; d
< count
; d
++)
3976 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3984 case nir_intrinsic_load_ssbo
: {
3985 assert(devinfo
->gen
>= 7);
3987 nir_const_value
*const_uniform_block
=
3988 nir_src_as_const_value(instr
->src
[0]);
3991 if (const_uniform_block
) {
3992 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3993 const_uniform_block
->u32
[0];
3994 surf_index
= brw_imm_ud(index
);
3995 brw_mark_surface_used(prog_data
, index
);
3997 surf_index
= vgrf(glsl_type::uint_type
);
3998 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3999 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4001 /* Assume this may touch any UBO. It would be nice to provide
4002 * a tighter bound, but the array information is already lowered away.
4004 brw_mark_surface_used(prog_data
,
4005 stage_prog_data
->binding_table
.ssbo_start
+
4006 nir
->info
.num_ssbos
- 1);
4010 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4012 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4014 offset_reg
= get_nir_src(instr
->src
[1]);
4017 /* Read the vector */
4018 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4019 instr
->num_components
);
4024 case nir_intrinsic_store_ssbo
: {
4025 assert(devinfo
->gen
>= 7);
4027 if (stage
== MESA_SHADER_FRAGMENT
)
4028 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4032 nir_const_value
*const_uniform_block
=
4033 nir_src_as_const_value(instr
->src
[1]);
4034 if (const_uniform_block
) {
4035 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4036 const_uniform_block
->u32
[0];
4037 surf_index
= brw_imm_ud(index
);
4038 brw_mark_surface_used(prog_data
, index
);
4040 surf_index
= vgrf(glsl_type::uint_type
);
4041 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4042 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4044 brw_mark_surface_used(prog_data
,
4045 stage_prog_data
->binding_table
.ssbo_start
+
4046 nir
->info
.num_ssbos
- 1);
4050 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4053 unsigned writemask
= instr
->const_index
[0];
4055 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4056 * since the untyped writes below operate in units of 32-bits, which
4057 * means that we need to write twice as many components each time.
4058 * Also, we have to suffle 64-bit data to be in the appropriate layout
4059 * expected by our 32-bit write messages.
4061 unsigned type_size
= 4;
4062 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4064 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
4065 val_reg
, instr
->num_components
);
4068 unsigned type_slots
= type_size
/ 4;
4070 /* Combine groups of consecutive enabled channels in one write
4071 * message. We use ffs to find the first enabled channel and then ffs on
4072 * the bit-inverse, down-shifted writemask to determine the length of
4073 * the block of enabled bits.
4076 unsigned first_component
= ffs(writemask
) - 1;
4077 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4079 /* We can't write more than 2 64-bit components at once. Limit the
4080 * length of the write to what we can do and let the next iteration
4084 length
= MIN2(2, length
);
4087 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4089 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4090 type_size
* first_component
);
4092 offset_reg
= vgrf(glsl_type::uint_type
);
4094 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4095 brw_imm_ud(type_size
* first_component
));
4099 emit_untyped_write(bld
, surf_index
, offset_reg
,
4100 offset(val_reg
, bld
, first_component
* type_slots
),
4101 1 /* dims */, length
* type_slots
,
4102 BRW_PREDICATE_NONE
);
4104 /* Clear the bits in the writemask that we just wrote, then try
4105 * again to see if more channels are left.
4107 writemask
&= (15 << (first_component
+ length
));
4112 case nir_intrinsic_store_output
: {
4113 fs_reg src
= get_nir_src(instr
->src
[0]);
4115 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4116 assert(const_offset
&& "Indirect output stores not allowed");
4118 unsigned num_components
= instr
->num_components
;
4119 unsigned first_component
= nir_intrinsic_component(instr
);
4120 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4121 src
= shuffle_64bit_data_for_32bit_write(bld
, src
, num_components
);
4122 num_components
*= 2;
4125 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4126 4 * const_offset
->u32
[0]), src
.type
);
4127 for (unsigned j
= 0; j
< num_components
; j
++) {
4128 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4129 offset(src
, bld
, j
));
4134 case nir_intrinsic_ssbo_atomic_add
:
4135 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4137 case nir_intrinsic_ssbo_atomic_imin
:
4138 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4140 case nir_intrinsic_ssbo_atomic_umin
:
4141 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4143 case nir_intrinsic_ssbo_atomic_imax
:
4144 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4146 case nir_intrinsic_ssbo_atomic_umax
:
4147 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4149 case nir_intrinsic_ssbo_atomic_and
:
4150 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4152 case nir_intrinsic_ssbo_atomic_or
:
4153 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4155 case nir_intrinsic_ssbo_atomic_xor
:
4156 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4158 case nir_intrinsic_ssbo_atomic_exchange
:
4159 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4161 case nir_intrinsic_ssbo_atomic_comp_swap
:
4162 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4165 case nir_intrinsic_get_buffer_size
: {
4166 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4167 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4169 /* A resinfo's sampler message is used to get the buffer size. The
4170 * SIMD8's writeback message consists of four registers and SIMD16's
4171 * writeback message consists of 8 destination registers (two per each
4172 * component). Because we are only interested on the first channel of
4173 * the first returned component, where resinfo returns the buffer size
4174 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4175 * the dispatch width.
4177 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4178 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4179 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4182 ubld
.MOV(src_payload
, brw_imm_d(0));
4184 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4185 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4186 src_payload
, brw_imm_ud(index
));
4187 inst
->header_size
= 0;
4189 inst
->size_written
= 4 * REG_SIZE
;
4191 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4192 brw_mark_surface_used(prog_data
, index
);
4196 case nir_intrinsic_load_subgroup_invocation
:
4197 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4198 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4201 case nir_intrinsic_load_subgroup_eq_mask
:
4202 case nir_intrinsic_load_subgroup_ge_mask
:
4203 case nir_intrinsic_load_subgroup_gt_mask
:
4204 case nir_intrinsic_load_subgroup_le_mask
:
4205 case nir_intrinsic_load_subgroup_lt_mask
:
4206 unreachable("not reached");
4208 case nir_intrinsic_vote_any
: {
4209 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4211 /* The any/all predicates do not consider channel enables. To prevent
4212 * dead channels from affecting the result, we initialize the flag with
4213 * with the identity value for the logical operation.
4215 if (dispatch_width
== 32) {
4216 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4217 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4220 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4222 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4224 /* For some reason, the any/all predicates don't work properly with
4225 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4226 * doesn't read the correct subset of the flag register and you end up
4227 * getting garbage in the second half. Work around this by using a pair
4228 * of 1-wide MOVs and scattering the result.
4230 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4231 ubld
.MOV(res1
, brw_imm_d(0));
4232 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4233 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4234 BRW_PREDICATE_ALIGN1_ANY32H
,
4235 ubld
.MOV(res1
, brw_imm_d(-1)));
4237 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4240 case nir_intrinsic_vote_all
: {
4241 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4243 /* The any/all predicates do not consider channel enables. To prevent
4244 * dead channels from affecting the result, we initialize the flag with
4245 * with the identity value for the logical operation.
4247 if (dispatch_width
== 32) {
4248 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4249 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4250 brw_imm_ud(0xffffffff));
4252 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4254 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4256 /* For some reason, the any/all predicates don't work properly with
4257 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4258 * doesn't read the correct subset of the flag register and you end up
4259 * getting garbage in the second half. Work around this by using a pair
4260 * of 1-wide MOVs and scattering the result.
4262 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4263 ubld
.MOV(res1
, brw_imm_d(0));
4264 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4265 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4266 BRW_PREDICATE_ALIGN1_ALL32H
,
4267 ubld
.MOV(res1
, brw_imm_d(-1)));
4269 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4272 case nir_intrinsic_vote_eq
: {
4273 fs_reg value
= get_nir_src(instr
->src
[0]);
4274 fs_reg uniformized
= bld
.emit_uniformize(value
);
4275 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4277 /* The any/all predicates do not consider channel enables. To prevent
4278 * dead channels from affecting the result, we initialize the flag with
4279 * with the identity value for the logical operation.
4281 if (dispatch_width
== 32) {
4282 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4283 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4284 brw_imm_ud(0xffffffff));
4286 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4288 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4290 /* For some reason, the any/all predicates don't work properly with
4291 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4292 * doesn't read the correct subset of the flag register and you end up
4293 * getting garbage in the second half. Work around this by using a pair
4294 * of 1-wide MOVs and scattering the result.
4296 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4297 ubld
.MOV(res1
, brw_imm_d(0));
4298 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4299 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4300 BRW_PREDICATE_ALIGN1_ALL32H
,
4301 ubld
.MOV(res1
, brw_imm_d(-1)));
4303 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4307 case nir_intrinsic_ballot
: {
4308 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4309 BRW_REGISTER_TYPE_UD
);
4310 struct brw_reg flag
= brw_flag_reg(0, 0);
4311 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4312 * as f0.0. This is a problem for fragment programs as we currently use
4313 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4314 * programs yet so this isn't a problem. When we do, something will
4317 if (dispatch_width
== 32)
4318 flag
.type
= BRW_REGISTER_TYPE_UD
;
4320 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4321 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4323 if (instr
->dest
.ssa
.bit_size
> 32) {
4324 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4326 dest
.type
= BRW_REGISTER_TYPE_UD
;
4328 bld
.MOV(dest
, flag
);
4332 case nir_intrinsic_read_invocation
: {
4333 const fs_reg value
= get_nir_src(instr
->src
[0]);
4334 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4335 fs_reg tmp
= bld
.vgrf(value
.type
);
4337 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4338 bld
.emit_uniformize(invocation
));
4340 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4344 case nir_intrinsic_read_first_invocation
: {
4345 const fs_reg value
= get_nir_src(instr
->src
[0]);
4346 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4351 unreachable("unknown intrinsic");
4356 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4357 int op
, nir_intrinsic_instr
*instr
)
4359 if (stage
== MESA_SHADER_FRAGMENT
)
4360 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4363 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4364 dest
= get_nir_dest(instr
->dest
);
4367 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4368 if (const_surface
) {
4369 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4370 const_surface
->u32
[0];
4371 surface
= brw_imm_ud(surf_index
);
4372 brw_mark_surface_used(prog_data
, surf_index
);
4374 surface
= vgrf(glsl_type::uint_type
);
4375 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4376 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4378 /* Assume this may touch any SSBO. This is the same we do for other
4379 * UBO/SSBO accesses with non-constant surface.
4381 brw_mark_surface_used(prog_data
,
4382 stage_prog_data
->binding_table
.ssbo_start
+
4383 nir
->info
.num_ssbos
- 1);
4386 fs_reg offset
= get_nir_src(instr
->src
[1]);
4387 fs_reg data1
= get_nir_src(instr
->src
[2]);
4389 if (op
== BRW_AOP_CMPWR
)
4390 data2
= get_nir_src(instr
->src
[3]);
4392 /* Emit the actual atomic operation */
4394 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4396 1 /* dims */, 1 /* rsize */,
4398 BRW_PREDICATE_NONE
);
4399 dest
.type
= atomic_result
.type
;
4400 bld
.MOV(dest
, atomic_result
);
4404 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4405 int op
, nir_intrinsic_instr
*instr
)
4408 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4409 dest
= get_nir_dest(instr
->dest
);
4411 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4413 fs_reg data1
= get_nir_src(instr
->src
[1]);
4415 if (op
== BRW_AOP_CMPWR
)
4416 data2
= get_nir_src(instr
->src
[2]);
4418 /* Get the offset */
4419 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4421 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4423 offset
= vgrf(glsl_type::uint_type
);
4425 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4426 brw_imm_ud(instr
->const_index
[0]));
4429 /* Emit the actual atomic operation operation */
4431 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4433 1 /* dims */, 1 /* rsize */,
4435 BRW_PREDICATE_NONE
);
4436 dest
.type
= atomic_result
.type
;
4437 bld
.MOV(dest
, atomic_result
);
4441 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4443 unsigned texture
= instr
->texture_index
;
4444 unsigned sampler
= instr
->sampler_index
;
4446 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4448 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4449 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4451 int lod_components
= 0;
4453 /* The hardware requires a LOD for buffer textures */
4454 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4455 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4457 uint32_t header_bits
= 0;
4458 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4459 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4460 switch (instr
->src
[i
].src_type
) {
4461 case nir_tex_src_bias
:
4462 srcs
[TEX_LOGICAL_SRC_LOD
] =
4463 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4465 case nir_tex_src_comparator
:
4466 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4468 case nir_tex_src_coord
:
4469 switch (instr
->op
) {
4471 case nir_texop_txf_ms
:
4472 case nir_texop_txf_ms_mcs
:
4473 case nir_texop_samples_identical
:
4474 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4477 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4481 case nir_tex_src_ddx
:
4482 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4483 lod_components
= nir_tex_instr_src_size(instr
, i
);
4485 case nir_tex_src_ddy
:
4486 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4488 case nir_tex_src_lod
:
4489 switch (instr
->op
) {
4491 srcs
[TEX_LOGICAL_SRC_LOD
] =
4492 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4495 srcs
[TEX_LOGICAL_SRC_LOD
] =
4496 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4499 srcs
[TEX_LOGICAL_SRC_LOD
] =
4500 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4504 case nir_tex_src_ms_index
:
4505 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4508 case nir_tex_src_offset
: {
4509 nir_const_value
*const_offset
=
4510 nir_src_as_const_value(instr
->src
[i
].src
);
4511 unsigned offset_bits
= 0;
4513 brw_texture_offset(const_offset
->i32
,
4514 nir_tex_instr_src_size(instr
, i
),
4516 header_bits
|= offset_bits
;
4518 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4519 retype(src
, BRW_REGISTER_TYPE_D
);
4524 case nir_tex_src_projector
:
4525 unreachable("should be lowered");
4527 case nir_tex_src_texture_offset
: {
4528 /* Figure out the highest possible texture index and mark it as used */
4529 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4530 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4531 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4533 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4535 brw_mark_surface_used(prog_data
, max_used
);
4537 /* Emit code to evaluate the actual indexing expression */
4538 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4539 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4540 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4544 case nir_tex_src_sampler_offset
: {
4545 /* Emit code to evaluate the actual indexing expression */
4546 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4547 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4548 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4552 case nir_tex_src_ms_mcs
:
4553 assert(instr
->op
== nir_texop_txf_ms
);
4554 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4557 case nir_tex_src_plane
: {
4558 nir_const_value
*const_plane
=
4559 nir_src_as_const_value(instr
->src
[i
].src
);
4560 const uint32_t plane
= const_plane
->u32
[0];
4561 const uint32_t texture_index
=
4562 instr
->texture_index
+
4563 stage_prog_data
->binding_table
.plane_start
[plane
] -
4564 stage_prog_data
->binding_table
.texture_start
;
4566 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4571 unreachable("unknown texture source");
4575 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4576 (instr
->op
== nir_texop_txf_ms
||
4577 instr
->op
== nir_texop_samples_identical
)) {
4578 if (devinfo
->gen
>= 7 &&
4579 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4580 srcs
[TEX_LOGICAL_SRC_MCS
] =
4581 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4582 instr
->coord_components
,
4583 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4585 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4589 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4590 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4593 switch (instr
->op
) {
4595 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4596 SHADER_OPCODE_TXL_LOGICAL
);
4599 opcode
= FS_OPCODE_TXB_LOGICAL
;
4602 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4605 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4608 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4610 case nir_texop_txf_ms
:
4611 if ((key_tex
->msaa_16
& (1 << sampler
)))
4612 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4614 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4616 case nir_texop_txf_ms_mcs
:
4617 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4619 case nir_texop_query_levels
:
4621 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4624 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4627 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4628 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4630 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4632 case nir_texop_texture_samples
:
4633 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4635 case nir_texop_samples_identical
: {
4636 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4638 /* If mcs is an immediate value, it means there is no MCS. In that case
4639 * just return false.
4641 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4642 bld
.MOV(dst
, brw_imm_ud(0u));
4643 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4644 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4645 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4646 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4647 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4649 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4650 BRW_CONDITIONAL_EQ
);
4655 unreachable("unknown texture opcode");
4658 if (instr
->op
== nir_texop_tg4
) {
4659 if (instr
->component
== 1 &&
4660 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4661 /* gather4 sampler is broken for green channel on RG32F --
4662 * we must ask for blue instead.
4664 header_bits
|= 2 << 16;
4666 header_bits
|= instr
->component
<< 16;
4670 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4671 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4672 inst
->offset
= header_bits
;
4674 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4675 if (devinfo
->gen
>= 9 &&
4676 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4677 unsigned write_mask
= instr
->dest
.is_ssa
?
4678 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4679 (1 << dest_size
) - 1;
4680 assert(write_mask
!= 0); /* dead code should have been eliminated */
4681 inst
->size_written
= util_last_bit(write_mask
) *
4682 inst
->dst
.component_size(inst
->exec_size
);
4684 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4687 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4688 inst
->shadow_compare
= true;
4690 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4691 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4694 for (unsigned i
= 0; i
< dest_size
; i
++)
4695 nir_dest
[i
] = offset(dst
, bld
, i
);
4697 if (instr
->op
== nir_texop_query_levels
) {
4698 /* # levels is in .w */
4699 nir_dest
[0] = offset(dst
, bld
, 3);
4700 } else if (instr
->op
== nir_texop_txs
&&
4701 dest_size
>= 3 && devinfo
->gen
< 7) {
4702 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4703 fs_reg depth
= offset(dst
, bld
, 2);
4704 nir_dest
[2] = vgrf(glsl_type::int_type
);
4705 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4708 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4712 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4714 switch (instr
->type
) {
4715 case nir_jump_break
:
4716 bld
.emit(BRW_OPCODE_BREAK
);
4718 case nir_jump_continue
:
4719 bld
.emit(BRW_OPCODE_CONTINUE
);
4721 case nir_jump_return
:
4723 unreachable("unknown jump");
4728 * This helper takes the result of a load operation that reads 32-bit elements
4736 * and shuffles the data to get this:
4743 * Which is exactly what we want if the load is reading 64-bit components
4744 * like doubles, where x represents the low 32-bit of the x double component
4745 * and y represents the high 32-bit of the x double component (likewise with
4746 * z and w for double component y). The parameter @components represents
4747 * the number of 64-bit components present in @src. This would typically be
4748 * 2 at most, since we can only fit 2 double elements in the result of a
4751 * Notice that @dst and @src can be the same register.
4754 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4757 uint32_t components
)
4759 assert(type_sz(src
.type
) == 4);
4760 assert(type_sz(dst
.type
) == 8);
4762 /* A temporary that we will use to shuffle the 32-bit data of each
4763 * component in the vector into valid 64-bit data. We can't write directly
4764 * to dst because dst can be (and would usually be) the same as src
4765 * and in that case the first MOV in the loop below would overwrite the
4766 * data read in the second MOV.
4768 fs_reg tmp
= bld
.vgrf(dst
.type
);
4770 for (unsigned i
= 0; i
< components
; i
++) {
4771 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4773 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4774 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4776 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4781 * This helper does the inverse operation of
4782 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4784 * We need to do this when we are going to use untyped write messsages that
4785 * operate with 32-bit components in order to arrange our 64-bit data to be
4786 * in the expected layout.
4788 * Notice that callers of this function, unlike in the case of the inverse
4789 * operation, would typically need to call this with dst and src being
4790 * different registers, since they would otherwise corrupt the original
4791 * 64-bit data they are about to write. Because of this the function checks
4792 * that the src and dst regions involved in the operation do not overlap.
4795 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4797 uint32_t components
)
4799 assert(type_sz(src
.type
) == 8);
4801 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 2 * components
);
4803 for (unsigned i
= 0; i
< components
; i
++) {
4804 const fs_reg component_i
= offset(src
, bld
, i
);
4805 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4806 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4813 setup_imm_df(const fs_builder
&bld
, double v
)
4815 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4816 assert(devinfo
->gen
>= 7);
4818 if (devinfo
->gen
>= 8)
4819 return brw_imm_df(v
);
4821 /* gen7.5 does not support DF immediates straighforward but the DIM
4822 * instruction allows to set the 64-bit immediate value.
4824 if (devinfo
->is_haswell
) {
4825 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4826 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4827 ubld
.DIM(dst
, brw_imm_df(v
));
4828 return component(dst
, 0);
4831 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4832 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4833 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4835 * Alternatively, we could also produce a normal VGRF (without stride 0)
4836 * by writing to all the channels in the VGRF, however, that would hit the
4837 * gen7 bug where we have to split writes that span more than 1 register
4838 * into instructions with a width of 4 (otherwise the write to the second
4839 * register written runs into an execmask hardware bug) which isn't very
4852 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4853 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4854 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4855 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4857 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);