2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
46 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
50 fs_visitor::nir_setup_outputs()
52 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
55 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
57 /* Calculate the size of output registers in a separate pass, before
58 * allocating them. With ARB_enhanced_layouts, multiple output variables
59 * may occupy the same slot, but have different type sizes.
61 nir_foreach_variable(var
, &nir
->outputs
) {
62 const int loc
= var
->data
.driver_location
;
63 const unsigned var_vec4s
=
64 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
65 : type_size_vec4(var
->type
, true);
66 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
69 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
70 if (vec4s
[loc
] == 0) {
75 unsigned reg_size
= vec4s
[loc
];
77 /* Check if there are any ranges that start within this range and extend
78 * past it. If so, include them in this allocation.
80 for (unsigned i
= 1; i
< reg_size
; i
++)
81 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
83 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
84 for (unsigned i
= 0; i
< reg_size
; i
++)
85 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
92 fs_visitor::nir_setup_uniforms()
94 /* Only the first compile gets to set up uniforms. */
95 if (push_constant_loc
) {
96 assert(pull_constant_loc
);
100 uniforms
= nir
->num_uniforms
/ 4;
102 if (stage
== MESA_SHADER_COMPUTE
) {
103 /* Add a uniform for the thread local id. It must be the last uniform
106 assert(uniforms
== prog_data
->nr_params
);
107 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
108 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
109 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
114 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
118 nir_foreach_instr(instr
, block
) {
119 if (instr
->type
!= nir_instr_type_intrinsic
)
122 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
123 switch (intrin
->intrinsic
) {
124 case nir_intrinsic_load_vertex_id
:
125 case nir_intrinsic_load_base_vertex
:
126 unreachable("should be lowered by nir_lower_system_values().");
128 case nir_intrinsic_load_vertex_id_zero_base
:
129 case nir_intrinsic_load_is_indexed_draw
:
130 case nir_intrinsic_load_first_vertex
:
131 case nir_intrinsic_load_instance_id
:
132 case nir_intrinsic_load_base_instance
:
133 case nir_intrinsic_load_draw_id
:
134 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
136 case nir_intrinsic_load_invocation_id
:
137 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
139 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
140 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
141 if (reg
->file
== BAD_FILE
) {
142 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
143 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
144 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
145 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
150 case nir_intrinsic_load_sample_pos
:
151 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
152 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
153 if (reg
->file
== BAD_FILE
)
154 *reg
= *v
->emit_samplepos_setup();
157 case nir_intrinsic_load_sample_id
:
158 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
159 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
160 if (reg
->file
== BAD_FILE
)
161 *reg
= *v
->emit_sampleid_setup();
164 case nir_intrinsic_load_sample_mask_in
:
165 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
166 assert(v
->devinfo
->gen
>= 7);
167 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
168 if (reg
->file
== BAD_FILE
)
169 *reg
= *v
->emit_samplemaskin_setup();
172 case nir_intrinsic_load_work_group_id
:
173 assert(v
->stage
== MESA_SHADER_COMPUTE
);
174 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
175 if (reg
->file
== BAD_FILE
)
176 *reg
= *v
->emit_cs_work_group_id_setup();
179 case nir_intrinsic_load_helper_invocation
:
180 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
181 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
182 if (reg
->file
== BAD_FILE
) {
183 const fs_builder abld
=
184 v
->bld
.annotate("gl_HelperInvocation", NULL
);
186 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
187 * pixel mask is in g1.7 of the thread payload.
189 * We move the per-channel pixel enable bit to the low bit of each
190 * channel by shifting the byte containing the pixel mask by the
191 * vector immediate 0x76543210UV.
193 * The region of <1,8,0> reads only 1 byte (the pixel masks for
194 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
195 * masks for 2 and 3) in SIMD16.
197 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
199 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
200 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
201 hbld
.SHR(offset(shifted
, hbld
, i
),
202 stride(retype(brw_vec1_grf(1 + i
, 7),
203 BRW_REGISTER_TYPE_UB
),
205 brw_imm_v(0x76543210));
208 /* A set bit in the pixel mask means the channel is enabled, but
209 * that is the opposite of gl_HelperInvocation so we need to invert
212 * The negate source-modifier bit of logical instructions on Gen8+
213 * performs 1's complement negation, so we can use that instead of
216 fs_reg inverted
= negate(shifted
);
217 if (v
->devinfo
->gen
< 8) {
218 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
219 abld
.NOT(inverted
, shifted
);
222 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
223 * with 1 and negating.
225 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
226 abld
.AND(anded
, inverted
, brw_imm_uw(1));
228 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
229 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
243 fs_visitor::nir_emit_system_values()
245 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
246 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
247 nir_system_values
[i
] = fs_reg();
250 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
251 * never end up using it.
254 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
255 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
256 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
258 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
259 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
260 if (dispatch_width
> 8)
261 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
262 if (dispatch_width
> 16) {
263 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
264 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
268 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
269 nir_foreach_block(block
, impl
)
270 emit_system_values_block(block
, this);
274 * Returns a type based on a reference_type (word, float, half-float) and a
277 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
279 * @FIXME: 64-bit return types are always DF on integer types to maintain
280 * compability with uses of DF previously to the introduction of int64
284 brw_reg_type_from_bit_size(const unsigned bit_size
,
285 const brw_reg_type reference_type
)
287 switch(reference_type
) {
288 case BRW_REGISTER_TYPE_HF
:
289 case BRW_REGISTER_TYPE_F
:
290 case BRW_REGISTER_TYPE_DF
:
293 return BRW_REGISTER_TYPE_HF
;
295 return BRW_REGISTER_TYPE_F
;
297 return BRW_REGISTER_TYPE_DF
;
299 unreachable("Invalid bit size");
301 case BRW_REGISTER_TYPE_B
:
302 case BRW_REGISTER_TYPE_W
:
303 case BRW_REGISTER_TYPE_D
:
304 case BRW_REGISTER_TYPE_Q
:
307 return BRW_REGISTER_TYPE_B
;
309 return BRW_REGISTER_TYPE_W
;
311 return BRW_REGISTER_TYPE_D
;
313 return BRW_REGISTER_TYPE_Q
;
315 unreachable("Invalid bit size");
317 case BRW_REGISTER_TYPE_UB
:
318 case BRW_REGISTER_TYPE_UW
:
319 case BRW_REGISTER_TYPE_UD
:
320 case BRW_REGISTER_TYPE_UQ
:
323 return BRW_REGISTER_TYPE_UB
;
325 return BRW_REGISTER_TYPE_UW
;
327 return BRW_REGISTER_TYPE_UD
;
329 return BRW_REGISTER_TYPE_UQ
;
331 unreachable("Invalid bit size");
334 unreachable("Unknown type");
339 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
341 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
342 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
343 nir_locals
[i
] = fs_reg();
346 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
347 unsigned array_elems
=
348 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
349 unsigned size
= array_elems
* reg
->num_components
;
350 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
351 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
352 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
355 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
358 nir_emit_cf_list(&impl
->body
);
362 fs_visitor::nir_emit_cf_list(exec_list
*list
)
364 exec_list_validate(list
);
365 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
366 switch (node
->type
) {
368 nir_emit_if(nir_cf_node_as_if(node
));
371 case nir_cf_node_loop
:
372 nir_emit_loop(nir_cf_node_as_loop(node
));
375 case nir_cf_node_block
:
376 nir_emit_block(nir_cf_node_as_block(node
));
380 unreachable("Invalid CFG node block");
386 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
391 /* If the condition has the form !other_condition, use other_condition as
392 * the source, but invert the predicate on the if instruction.
394 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
395 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
396 assert(!cond
->src
[0].negate
);
397 assert(!cond
->src
[0].abs
);
400 cond_reg
= get_nir_src(cond
->src
[0].src
);
403 cond_reg
= get_nir_src(if_stmt
->condition
);
406 /* first, put the condition into f0 */
407 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
408 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
409 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
411 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
413 nir_emit_cf_list(&if_stmt
->then_list
);
415 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
416 bld
.emit(BRW_OPCODE_ELSE
);
417 nir_emit_cf_list(&if_stmt
->else_list
);
420 bld
.emit(BRW_OPCODE_ENDIF
);
422 if (devinfo
->gen
< 7)
423 limit_dispatch_width(16, "Non-uniform control flow unsupported "
428 fs_visitor::nir_emit_loop(nir_loop
*loop
)
430 bld
.emit(BRW_OPCODE_DO
);
432 nir_emit_cf_list(&loop
->body
);
434 bld
.emit(BRW_OPCODE_WHILE
);
436 if (devinfo
->gen
< 7)
437 limit_dispatch_width(16, "Non-uniform control flow unsupported "
442 fs_visitor::nir_emit_block(nir_block
*block
)
444 nir_foreach_instr(instr
, block
) {
445 nir_emit_instr(instr
);
450 fs_visitor::nir_emit_instr(nir_instr
*instr
)
452 const fs_builder abld
= bld
.annotate(NULL
, instr
);
454 switch (instr
->type
) {
455 case nir_instr_type_alu
:
456 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
459 case nir_instr_type_deref
:
460 unreachable("All derefs should've been lowered");
463 case nir_instr_type_intrinsic
:
465 case MESA_SHADER_VERTEX
:
466 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_TESS_CTRL
:
469 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_TESS_EVAL
:
472 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_GEOMETRY
:
475 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
477 case MESA_SHADER_FRAGMENT
:
478 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
480 case MESA_SHADER_COMPUTE
:
481 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
484 unreachable("unsupported shader stage");
488 case nir_instr_type_tex
:
489 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
492 case nir_instr_type_load_const
:
493 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
496 case nir_instr_type_ssa_undef
:
497 /* We create a new VGRF for undefs on every use (by handling
498 * them in get_nir_src()), rather than for each definition.
499 * This helps register coalescing eliminate MOVs from undef.
503 case nir_instr_type_jump
:
504 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
508 unreachable("unknown instruction type");
513 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
517 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
518 const fs_reg
&result
)
520 if (!instr
->src
[0].src
.is_ssa
||
521 !instr
->src
[0].src
.ssa
->parent_instr
)
524 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
527 nir_alu_instr
*src0
=
528 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
530 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
531 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
534 /* If either opcode has source modifiers, bail.
536 * TODO: We can potentially handle source modifiers if both of the opcodes
537 * we're combining are signed integers.
539 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
540 src0
->src
[0].abs
|| src0
->src
[0].negate
)
543 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
545 /* Element type to extract.*/
546 const brw_reg_type type
= brw_int_type(
547 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
548 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
550 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
551 op0
.type
= brw_type_for_nir_type(devinfo
,
552 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
553 nir_src_bit_size(src0
->src
[0].src
)));
554 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
556 set_saturate(instr
->dest
.saturate
,
557 bld
.MOV(result
, subscript(op0
, type
, element
)));
562 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
563 const fs_reg
&result
)
565 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
566 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
569 if (!nir_src_is_const(instr
->src
[1].src
) ||
570 !nir_src_is_const(instr
->src
[2].src
))
573 const float value1
= nir_src_as_float(instr
->src
[1].src
);
574 const float value2
= nir_src_as_float(instr
->src
[2].src
);
575 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
578 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
579 assert(value1
== -value2
);
581 fs_reg tmp
= vgrf(glsl_type::int_type
);
583 if (devinfo
->gen
>= 6) {
584 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
585 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
587 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
589 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
590 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
592 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
594 * This negation looks like it's safe in practice, because bits 0:4 will
595 * surely be TRIANGLES
598 if (value1
== -1.0f
) {
602 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
603 g0
, brw_imm_uw(0x3f80));
605 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
606 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
608 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
610 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
611 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
613 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
615 * This negation looks like it's safe in practice, because bits 0:4 will
616 * surely be TRIANGLES
619 if (value1
== -1.0f
) {
623 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
625 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
631 emit_find_msb_using_lzd(const fs_builder
&bld
,
632 const fs_reg
&result
,
640 /* LZD of an absolute value source almost always does the right
641 * thing. There are two problem values:
643 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
644 * 0. However, findMSB(int(0x80000000)) == 30.
646 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
647 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
649 * For a value of zero or negative one, -1 will be returned.
651 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
652 * findMSB(-(1<<x)) should return x-1.
654 * For all negative number cases, including 0x80000000 and
655 * 0xffffffff, the correct value is obtained from LZD if instead of
656 * negating the (already negative) value the logical-not is used. A
657 * conditonal logical-not can be achieved in two instructions.
659 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
661 bld
.ASR(temp
, src
, brw_imm_d(31));
662 bld
.XOR(temp
, temp
, src
);
665 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
666 retype(temp
, BRW_REGISTER_TYPE_UD
));
668 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
669 * from the LSB side. Subtract the result from 31 to convert the MSB
670 * count into an LSB count. If no bits are set, LZD will return 32.
671 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
673 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
674 inst
->src
[0].negate
= true;
678 brw_rnd_mode_from_nir_op (const nir_op op
) {
680 case nir_op_f2f16_rtz
:
681 return BRW_RND_MODE_RTZ
;
682 case nir_op_f2f16_rtne
:
683 return BRW_RND_MODE_RTNE
;
685 unreachable("Operation doesn't support rounding mode");
690 brw_rnd_mode_from_execution_mode(unsigned execution_mode
)
692 if (nir_has_any_rounding_mode_rtne(execution_mode
))
693 return BRW_RND_MODE_RTNE
;
694 if (nir_has_any_rounding_mode_rtz(execution_mode
))
695 return BRW_RND_MODE_RTZ
;
696 return BRW_RND_MODE_UNSPECIFIED
;
700 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
701 nir_alu_instr
*instr
,
706 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
708 result
.type
= brw_type_for_nir_type(devinfo
,
709 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
710 nir_dest_bit_size(instr
->dest
.dest
)));
712 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
713 op
[i
] = get_nir_src(instr
->src
[i
].src
);
714 op
[i
].type
= brw_type_for_nir_type(devinfo
,
715 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
716 nir_src_bit_size(instr
->src
[i
].src
)));
717 op
[i
].abs
= instr
->src
[i
].abs
;
718 op
[i
].negate
= instr
->src
[i
].negate
;
721 /* Move and vecN instrutions may still be vectored. Return the raw,
722 * vectored source and destination so that fs_visitor::nir_emit_alu can
723 * handle it. Other callers should not have to handle these kinds of
736 /* At this point, we have dealt with any instruction that operates on
737 * more than a single channel. Therefore, we can just adjust the source
738 * and destination registers for that channel and emit the instruction.
740 unsigned channel
= 0;
741 if (nir_op_infos
[instr
->op
].output_size
== 0) {
742 /* Since NIR is doing the scalarizing for us, we should only ever see
743 * vectorized operations with a single channel.
745 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
746 channel
= ffs(instr
->dest
.write_mask
) - 1;
748 result
= offset(result
, bld
, channel
);
751 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
752 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
753 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
760 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
763 for (unsigned i
= 0; i
< 2; i
++) {
764 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
766 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
767 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
768 /* The source of the inot is now the source of instr. */
769 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
771 assert(!op
[i
].negate
);
774 op
[i
] = resolve_source_modifiers(op
[i
]);
780 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
782 nir_alu_instr
*instr
)
784 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
787 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
789 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
792 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
793 * of valid size-changing combinations is a bit more complex.
795 * The source restriction is just because I was lazy about generating the
798 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
799 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
802 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
803 * this is float(1 + a).
807 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
809 /* Ignore the saturate modifier, if there is one. The result of the
810 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
812 bld
.ADD(result
, op
, brw_imm_d(1));
818 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
820 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
821 * the source of \c instr that is a \c nir_op_fsign.
824 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
825 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
829 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
830 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
832 if (instr
->op
!= nir_op_fsign
) {
833 const nir_alu_instr
*const fsign_instr
=
834 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
836 assert(!fsign_instr
->dest
.saturate
);
838 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
839 * fsign_src] has the other multiply source. This must be rearranged so
840 * that op[0] is the source of the fsign op[1] is the other multiply
846 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
848 const nir_alu_type t
=
849 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
850 nir_src_bit_size(fsign_instr
->src
[0].src
));
852 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
853 op
[0].abs
= fsign_instr
->src
[0].abs
;
854 op
[0].negate
= fsign_instr
->src
[0].negate
;
856 unsigned channel
= 0;
857 if (nir_op_infos
[instr
->op
].output_size
== 0) {
858 /* Since NIR is doing the scalarizing for us, we should only ever see
859 * vectorized operations with a single channel.
861 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
862 channel
= ffs(instr
->dest
.write_mask
) - 1;
865 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
867 assert(!instr
->dest
.saturate
);
871 /* Straightforward since the source can be assumed to be either strictly
872 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
874 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
876 if (instr
->op
== nir_op_fsign
) {
877 inst
= (op
[0].negate
)
878 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
879 : bld
.MOV(result
, brw_imm_f(1.0f
));
881 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
882 inst
= bld
.MOV(result
, op
[1]);
885 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
886 } else if (type_sz(op
[0].type
) == 2) {
887 /* AND(val, 0x8000) gives the sign bit.
889 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
891 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
892 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
894 op
[0].type
= BRW_REGISTER_TYPE_UW
;
895 result
.type
= BRW_REGISTER_TYPE_UW
;
896 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
898 if (instr
->op
== nir_op_fsign
)
899 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
901 /* Use XOR here to get the result sign correct. */
902 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
905 inst
->predicate
= BRW_PREDICATE_NORMAL
;
906 } else if (type_sz(op
[0].type
) == 4) {
907 /* AND(val, 0x80000000) gives the sign bit.
909 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
912 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
914 op
[0].type
= BRW_REGISTER_TYPE_UD
;
915 result
.type
= BRW_REGISTER_TYPE_UD
;
916 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
918 if (instr
->op
== nir_op_fsign
)
919 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
921 /* Use XOR here to get the result sign correct. */
922 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
925 inst
->predicate
= BRW_PREDICATE_NORMAL
;
927 /* For doubles we do the same but we need to consider:
929 * - 2-src instructions can't operate with 64-bit immediates
930 * - The sign is encoded in the high 32-bit of each DF
931 * - We need to produce a DF result.
934 fs_reg zero
= vgrf(glsl_type::double_type
);
935 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
936 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
938 bld
.MOV(result
, zero
);
940 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
941 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
942 brw_imm_ud(0x80000000u
));
944 if (instr
->op
== nir_op_fsign
) {
945 set_predicate(BRW_PREDICATE_NORMAL
,
946 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
948 /* This could be done better in some cases. If the scale is an
949 * immediate with the low 32-bits all 0, emitting a separate XOR and
950 * OR would allow an algebraic optimization to remove the OR. There
951 * are currently zero instances of fsign(double(x))*IMM in shader-db
952 * or any test suite, so it is hard to care at this time.
954 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
955 inst
= bld
.XOR(result_int64
, result_int64
,
956 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
962 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
964 * Checks the operands of a \c nir_op_fmul to determine whether or not
965 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
967 * \param instr The multiplication instruction
969 * \param fsign_src The source of \c instr that may or may not be a
973 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
975 assert(instr
->op
== nir_op_fmul
);
977 nir_alu_instr
*const fsign_instr
=
978 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
982 * 1. instr->src[fsign_src] must be a nir_op_fsign.
983 * 2. The nir_op_fsign can only be used by this multiplication.
984 * 3. The source that is the nir_op_fsign does not have source modifiers.
985 * \c emit_fsign only examines the source modifiers of the source of the
988 * The nir_op_fsign must also not have the saturate modifier, but steps
989 * have already been taken (in nir_opt_algebraic) to ensure that.
991 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
992 is_used_once(fsign_instr
) &&
993 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
997 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
1000 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
1002 unsigned execution_mode
=
1003 bld
.shader
->nir
->info
.float_controls_execution_mode
;
1006 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1008 switch (instr
->op
) {
1013 fs_reg temp
= result
;
1014 bool need_extra_copy
= false;
1015 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1016 if (!instr
->src
[i
].src
.is_ssa
&&
1017 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1018 need_extra_copy
= true;
1019 temp
= bld
.vgrf(result
.type
, 4);
1024 for (unsigned i
= 0; i
< 4; i
++) {
1025 if (!(instr
->dest
.write_mask
& (1 << i
)))
1028 if (instr
->op
== nir_op_mov
) {
1029 inst
= bld
.MOV(offset(temp
, bld
, i
),
1030 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1032 inst
= bld
.MOV(offset(temp
, bld
, i
),
1033 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1035 inst
->saturate
= instr
->dest
.saturate
;
1038 /* In this case the source and destination registers were the same,
1039 * so we need to insert an extra set of moves in order to deal with
1042 if (need_extra_copy
) {
1043 for (unsigned i
= 0; i
< 4; i
++) {
1044 if (!(instr
->dest
.write_mask
& (1 << i
)))
1047 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1055 if (optimize_extract_to_float(instr
, result
))
1057 inst
= bld
.MOV(result
, op
[0]);
1058 inst
->saturate
= instr
->dest
.saturate
;
1061 case nir_op_f2f16_rtne
:
1062 case nir_op_f2f16_rtz
:
1063 case nir_op_f2f16
: {
1064 brw_rnd_mode rnd
= BRW_RND_MODE_UNSPECIFIED
;
1066 if (nir_op_f2f16
== instr
->op
)
1067 rnd
= brw_rnd_mode_from_execution_mode(execution_mode
);
1069 rnd
= brw_rnd_mode_from_nir_op(instr
->op
);
1071 if (BRW_RND_MODE_UNSPECIFIED
!= rnd
)
1072 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(), brw_imm_d(rnd
));
1074 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1075 * on the HW gen, it is a special hw opcode or just a MOV, and
1076 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1078 * But if we want to use that opcode, we need to provide support on
1079 * different optimizations and lowerings. As right now HF support is
1080 * only for gen8+, it will be better to use directly the MOV, and use
1081 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1083 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1084 inst
= bld
.MOV(result
, op
[0]);
1085 inst
->saturate
= instr
->dest
.saturate
;
1096 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1098 op
[0].type
= BRW_REGISTER_TYPE_D
;
1099 op
[0].negate
= !op
[0].negate
;
1122 if (result
.type
== BRW_REGISTER_TYPE_B
||
1123 result
.type
== BRW_REGISTER_TYPE_UB
||
1124 result
.type
== BRW_REGISTER_TYPE_HF
)
1125 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1127 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1128 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1129 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1130 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1132 inst
= bld
.MOV(result
, op
[0]);
1133 inst
->saturate
= instr
->dest
.saturate
;
1137 inst
= bld
.MOV(result
, op
[0]);
1138 inst
->saturate
= true;
1143 op
[0].negate
= true;
1144 inst
= bld
.MOV(result
, op
[0]);
1145 if (instr
->op
== nir_op_fneg
)
1146 inst
->saturate
= instr
->dest
.saturate
;
1151 op
[0].negate
= false;
1153 inst
= bld
.MOV(result
, op
[0]);
1154 if (instr
->op
== nir_op_fabs
)
1155 inst
->saturate
= instr
->dest
.saturate
;
1159 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1161 brw_rnd_mode_from_execution_mode(execution_mode
);
1162 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1166 if (op
[0].type
== BRW_REGISTER_TYPE_HF
)
1167 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1169 inst
= bld
.MOV(result
, op
[0]);
1170 inst
->saturate
= instr
->dest
.saturate
;
1174 emit_fsign(bld
, instr
, result
, op
, 0);
1178 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1179 inst
->saturate
= instr
->dest
.saturate
;
1183 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1184 inst
->saturate
= instr
->dest
.saturate
;
1188 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1189 inst
->saturate
= instr
->dest
.saturate
;
1193 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1194 inst
->saturate
= instr
->dest
.saturate
;
1198 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1199 inst
->saturate
= instr
->dest
.saturate
;
1203 if (fs_key
->high_quality_derivatives
) {
1204 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1206 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1208 inst
->saturate
= instr
->dest
.saturate
;
1210 case nir_op_fddx_fine
:
1211 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1212 inst
->saturate
= instr
->dest
.saturate
;
1214 case nir_op_fddx_coarse
:
1215 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1216 inst
->saturate
= instr
->dest
.saturate
;
1219 if (fs_key
->high_quality_derivatives
) {
1220 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1222 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1224 inst
->saturate
= instr
->dest
.saturate
;
1226 case nir_op_fddy_fine
:
1227 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1228 inst
->saturate
= instr
->dest
.saturate
;
1230 case nir_op_fddy_coarse
:
1231 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1232 inst
->saturate
= instr
->dest
.saturate
;
1236 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1238 brw_rnd_mode_from_execution_mode(execution_mode
);
1239 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1244 inst
= bld
.ADD(result
, op
[0], op
[1]);
1245 inst
->saturate
= instr
->dest
.saturate
;
1248 case nir_op_uadd_sat
:
1249 inst
= bld
.ADD(result
, op
[0], op
[1]);
1250 inst
->saturate
= true;
1254 for (unsigned i
= 0; i
< 2; i
++) {
1255 if (can_fuse_fmul_fsign(instr
, i
)) {
1256 emit_fsign(bld
, instr
, result
, op
, i
);
1261 /* We emit the rounding mode after the previous fsign optimization since
1262 * it won't result in a MUL, but will try to negate the value by other
1265 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1267 brw_rnd_mode_from_execution_mode(execution_mode
);
1268 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1272 inst
= bld
.MUL(result
, op
[0], op
[1]);
1273 inst
->saturate
= instr
->dest
.saturate
;
1276 case nir_op_imul_2x32_64
:
1277 case nir_op_umul_2x32_64
:
1278 bld
.MUL(result
, op
[0], op
[1]);
1282 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1283 bld
.MUL(result
, op
[0], op
[1]);
1286 case nir_op_imul_high
:
1287 case nir_op_umul_high
:
1288 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1289 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1294 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1295 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1298 case nir_op_uadd_carry
:
1299 unreachable("Should have been lowered by carry_to_arith().");
1301 case nir_op_usub_borrow
:
1302 unreachable("Should have been lowered by borrow_to_arith().");
1306 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1307 * appears that our hardware just does the right thing for signed
1310 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1311 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1315 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1316 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1318 /* Math instructions don't support conditional mod */
1319 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1320 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1322 /* Now, we need to determine if signs of the sources are different.
1323 * When we XOR the sources, the top bit is 0 if they are the same and 1
1324 * if they are different. We can then use a conditional modifier to
1325 * turn that into a predicate. This leads us to an XOR.l instruction.
1327 * Technically, according to the PRM, you're not allowed to use .l on a
1328 * XOR instruction. However, emperical experiments and Curro's reading
1329 * of the simulator source both indicate that it's safe.
1331 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1332 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1333 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1334 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1336 /* If the result of the initial remainder operation is non-zero and the
1337 * two sources have different signs, add in a copy of op[1] to get the
1338 * final integer modulus value.
1340 inst
= bld
.ADD(result
, result
, op
[1]);
1341 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1348 case nir_op_fne32
: {
1349 fs_reg dest
= result
;
1351 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1353 dest
= bld
.vgrf(op
[0].type
, 1);
1355 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1357 if (bit_size
> 32) {
1358 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1359 } else if(bit_size
< 32) {
1360 /* When we convert the result to 32-bit we need to be careful and do
1361 * it as a signed conversion to get sign extension (for 32-bit true)
1363 const brw_reg_type src_type
=
1364 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1366 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1376 case nir_op_ine32
: {
1377 fs_reg dest
= result
;
1379 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1380 * type. So we convert both operands for the comparison.
1383 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1384 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1386 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1388 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1390 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1391 brw_cmod_for_nir_comparison(instr
->op
));
1393 if (bit_size
> 32) {
1394 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1395 } else if (bit_size
< 32) {
1396 /* When we convert the result to 32-bit we need to be careful and do
1397 * it as a signed conversion to get sign extension (for 32-bit true)
1399 const brw_reg_type src_type
=
1400 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1402 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1408 if (devinfo
->gen
>= 8) {
1409 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1411 if (inot_src_instr
!= NULL
&&
1412 (inot_src_instr
->op
== nir_op_ior
||
1413 inot_src_instr
->op
== nir_op_ixor
||
1414 inot_src_instr
->op
== nir_op_iand
) &&
1415 !inot_src_instr
->src
[0].abs
&&
1416 !inot_src_instr
->src
[0].negate
&&
1417 !inot_src_instr
->src
[1].abs
&&
1418 !inot_src_instr
->src
[1].negate
) {
1419 /* The sources of the source logical instruction are now the
1420 * sources of the instruction that will be generated.
1422 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1423 resolve_inot_sources(bld
, inot_src_instr
, op
);
1425 /* Smash all of the sources and destination to be signed. This
1426 * doesn't matter for the operation of the instruction, but cmod
1427 * propagation fails on unsigned sources with negation (due to
1428 * fs_inst::can_do_cmod returning false).
1431 brw_type_for_nir_type(devinfo
,
1432 (nir_alu_type
)(nir_type_int
|
1433 nir_dest_bit_size(instr
->dest
.dest
)));
1435 brw_type_for_nir_type(devinfo
,
1436 (nir_alu_type
)(nir_type_int
|
1437 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1439 brw_type_for_nir_type(devinfo
,
1440 (nir_alu_type
)(nir_type_int
|
1441 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1443 /* For XOR, only invert one of the sources. Arbitrarily choose
1446 op
[0].negate
= !op
[0].negate
;
1447 if (inot_src_instr
->op
!= nir_op_ixor
)
1448 op
[1].negate
= !op
[1].negate
;
1450 switch (inot_src_instr
->op
) {
1452 bld
.AND(result
, op
[0], op
[1]);
1456 bld
.OR(result
, op
[0], op
[1]);
1460 bld
.XOR(result
, op
[0], op
[1]);
1464 unreachable("impossible opcode");
1467 op
[0] = resolve_source_modifiers(op
[0]);
1469 bld
.NOT(result
, op
[0]);
1472 if (devinfo
->gen
>= 8) {
1473 resolve_inot_sources(bld
, instr
, op
);
1475 bld
.XOR(result
, op
[0], op
[1]);
1478 if (devinfo
->gen
>= 8) {
1479 resolve_inot_sources(bld
, instr
, op
);
1481 bld
.OR(result
, op
[0], op
[1]);
1484 if (devinfo
->gen
>= 8) {
1485 resolve_inot_sources(bld
, instr
, op
);
1487 bld
.AND(result
, op
[0], op
[1]);
1493 case nir_op_b32all_fequal2
:
1494 case nir_op_b32all_iequal2
:
1495 case nir_op_b32all_fequal3
:
1496 case nir_op_b32all_iequal3
:
1497 case nir_op_b32all_fequal4
:
1498 case nir_op_b32all_iequal4
:
1499 case nir_op_b32any_fnequal2
:
1500 case nir_op_b32any_inequal2
:
1501 case nir_op_b32any_fnequal3
:
1502 case nir_op_b32any_inequal3
:
1503 case nir_op_b32any_fnequal4
:
1504 case nir_op_b32any_inequal4
:
1505 unreachable("Lowered by nir_lower_alu_reductions");
1507 case nir_op_fnoise1_1
:
1508 case nir_op_fnoise1_2
:
1509 case nir_op_fnoise1_3
:
1510 case nir_op_fnoise1_4
:
1511 case nir_op_fnoise2_1
:
1512 case nir_op_fnoise2_2
:
1513 case nir_op_fnoise2_3
:
1514 case nir_op_fnoise2_4
:
1515 case nir_op_fnoise3_1
:
1516 case nir_op_fnoise3_2
:
1517 case nir_op_fnoise3_3
:
1518 case nir_op_fnoise3_4
:
1519 case nir_op_fnoise4_1
:
1520 case nir_op_fnoise4_2
:
1521 case nir_op_fnoise4_3
:
1522 case nir_op_fnoise4_4
:
1523 unreachable("not reached: should be handled by lower_noise");
1526 unreachable("not reached: should be handled by ldexp_to_arith()");
1529 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1530 inst
->saturate
= instr
->dest
.saturate
;
1534 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1535 inst
->saturate
= instr
->dest
.saturate
;
1539 case nir_op_f2b32
: {
1540 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1541 if (bit_size
== 64) {
1542 /* two-argument instructions can't take 64-bit immediates */
1546 if (instr
->op
== nir_op_f2b32
) {
1547 zero
= vgrf(glsl_type::double_type
);
1548 tmp
= vgrf(glsl_type::double_type
);
1549 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1551 zero
= vgrf(glsl_type::int64_t_type
);
1552 tmp
= vgrf(glsl_type::int64_t_type
);
1553 bld
.MOV(zero
, brw_imm_q(0));
1556 /* A SIMD16 execution needs to be split in two instructions, so use
1557 * a vgrf instead of the flag register as dst so instruction splitting
1560 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1561 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1564 if (bit_size
== 32) {
1565 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1567 assert(bit_size
== 16);
1568 zero
= instr
->op
== nir_op_f2b32
?
1569 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1571 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1577 inst
= bld
.RNDZ(result
, op
[0]);
1578 inst
->saturate
= instr
->dest
.saturate
;
1581 case nir_op_fceil
: {
1582 op
[0].negate
= !op
[0].negate
;
1583 fs_reg temp
= vgrf(glsl_type::float_type
);
1584 bld
.RNDD(temp
, op
[0]);
1586 inst
= bld
.MOV(result
, temp
);
1587 inst
->saturate
= instr
->dest
.saturate
;
1591 inst
= bld
.RNDD(result
, op
[0]);
1592 inst
->saturate
= instr
->dest
.saturate
;
1595 inst
= bld
.FRC(result
, op
[0]);
1596 inst
->saturate
= instr
->dest
.saturate
;
1598 case nir_op_fround_even
:
1599 inst
= bld
.RNDE(result
, op
[0]);
1600 inst
->saturate
= instr
->dest
.saturate
;
1603 case nir_op_fquantize2f16
: {
1604 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1605 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1606 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1608 /* The destination stride must be at least as big as the source stride. */
1609 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1612 /* Check for denormal */
1613 fs_reg abs_src0
= op
[0];
1614 abs_src0
.abs
= true;
1615 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1617 /* Get the appropriately signed zero */
1618 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1619 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1620 brw_imm_ud(0x80000000));
1621 /* Do the actual F32 -> F16 -> F32 conversion */
1622 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1623 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1624 /* Select that or zero based on normal status */
1625 inst
= bld
.SEL(result
, zero
, tmp32
);
1626 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1627 inst
->saturate
= instr
->dest
.saturate
;
1634 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1635 inst
->saturate
= instr
->dest
.saturate
;
1641 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1642 inst
->saturate
= instr
->dest
.saturate
;
1645 case nir_op_pack_snorm_2x16
:
1646 case nir_op_pack_snorm_4x8
:
1647 case nir_op_pack_unorm_2x16
:
1648 case nir_op_pack_unorm_4x8
:
1649 case nir_op_unpack_snorm_2x16
:
1650 case nir_op_unpack_snorm_4x8
:
1651 case nir_op_unpack_unorm_2x16
:
1652 case nir_op_unpack_unorm_4x8
:
1653 case nir_op_unpack_half_2x16
:
1654 case nir_op_pack_half_2x16
:
1655 unreachable("not reached: should be handled by lower_packing_builtins");
1657 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1658 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1660 case nir_op_unpack_half_2x16_split_x
:
1661 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1662 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1663 inst
->saturate
= instr
->dest
.saturate
;
1666 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1667 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1669 case nir_op_unpack_half_2x16_split_y
:
1670 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1671 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1672 inst
->saturate
= instr
->dest
.saturate
;
1675 case nir_op_pack_64_2x32_split
:
1676 case nir_op_pack_32_2x16_split
:
1677 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1680 case nir_op_unpack_64_2x32_split_x
:
1681 case nir_op_unpack_64_2x32_split_y
: {
1682 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1683 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1685 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1689 case nir_op_unpack_32_2x16_split_x
:
1690 case nir_op_unpack_32_2x16_split_y
: {
1691 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1692 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1694 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1699 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1700 inst
->saturate
= instr
->dest
.saturate
;
1703 case nir_op_bitfield_reverse
:
1704 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1705 bld
.BFREV(result
, op
[0]);
1708 case nir_op_bit_count
:
1709 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1710 bld
.CBIT(result
, op
[0]);
1713 case nir_op_ufind_msb
: {
1714 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1715 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1719 case nir_op_ifind_msb
: {
1720 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1722 if (devinfo
->gen
< 7) {
1723 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1725 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1727 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1728 * count from the LSB side. If FBH didn't return an error
1729 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1730 * count into an LSB count.
1732 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1734 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1735 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1736 inst
->src
[0].negate
= true;
1741 case nir_op_find_lsb
:
1742 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1744 if (devinfo
->gen
< 7) {
1745 fs_reg temp
= vgrf(glsl_type::int_type
);
1747 /* (x & -x) generates a value that consists of only the LSB of x.
1748 * For all powers of 2, findMSB(y) == findLSB(y).
1750 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1751 fs_reg negated_src
= src
;
1753 /* One must be negated, and the other must be non-negated. It
1754 * doesn't matter which is which.
1756 negated_src
.negate
= true;
1759 bld
.AND(temp
, src
, negated_src
);
1760 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1762 bld
.FBL(result
, op
[0]);
1766 case nir_op_ubitfield_extract
:
1767 case nir_op_ibitfield_extract
:
1768 unreachable("should have been lowered");
1771 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1772 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1775 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1776 bld
.BFI1(result
, op
[0], op
[1]);
1779 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1780 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1783 case nir_op_bitfield_insert
:
1784 unreachable("not reached: should have been lowered");
1787 bld
.SHL(result
, op
[0], op
[1]);
1790 bld
.ASR(result
, op
[0], op
[1]);
1793 bld
.SHR(result
, op
[0], op
[1]);
1797 bld
.ROL(result
, op
[0], op
[1]);
1800 bld
.ROR(result
, op
[0], op
[1]);
1803 case nir_op_pack_half_2x16_split
:
1804 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1808 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1810 brw_rnd_mode_from_execution_mode(execution_mode
);
1811 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1815 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1816 inst
->saturate
= instr
->dest
.saturate
;
1820 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1821 inst
->saturate
= instr
->dest
.saturate
;
1824 case nir_op_b32csel
:
1825 if (optimize_frontfacing_ternary(instr
, result
))
1828 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1829 inst
= bld
.SEL(result
, op
[1], op
[2]);
1830 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1833 case nir_op_extract_u8
:
1834 case nir_op_extract_i8
: {
1835 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1840 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1841 * Use two instructions and a word or DWord intermediate integer type.
1843 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1844 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1846 if (instr
->op
== nir_op_extract_i8
) {
1847 /* If we need to sign extend, extract to a word first */
1848 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1849 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1850 bld
.MOV(result
, w_temp
);
1851 } else if (byte
& 1) {
1852 /* Extract the high byte from the word containing the desired byte
1856 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1859 /* Otherwise use an AND with 0xff and a word type */
1861 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1865 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1866 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1871 case nir_op_extract_u16
:
1872 case nir_op_extract_i16
: {
1873 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1874 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1875 bld
.MOV(result
, subscript(op
[0], type
, word
));
1880 unreachable("unhandled instruction");
1883 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1884 * to sign extend the low bit to 0/~0
1886 if (devinfo
->gen
<= 5 &&
1887 !result
.is_null() &&
1888 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1889 fs_reg masked
= vgrf(glsl_type::int_type
);
1890 bld
.AND(masked
, result
, brw_imm_d(1));
1891 masked
.negate
= true;
1892 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1897 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1898 nir_load_const_instr
*instr
)
1900 const brw_reg_type reg_type
=
1901 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1902 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1904 switch (instr
->def
.bit_size
) {
1906 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1907 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1911 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1912 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1916 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1917 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1921 assert(devinfo
->gen
>= 7);
1922 if (devinfo
->gen
== 7) {
1923 /* We don't get 64-bit integer types until gen8 */
1924 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1925 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1926 setup_imm_df(bld
, instr
->value
[i
].f64
));
1929 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1930 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1935 unreachable("Invalid bit size");
1938 nir_ssa_values
[instr
->def
.index
] = reg
;
1942 fs_visitor::get_nir_src(const nir_src
&src
)
1946 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1947 const brw_reg_type reg_type
=
1948 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1949 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1951 reg
= nir_ssa_values
[src
.ssa
->index
];
1954 /* We don't handle indirects on locals */
1955 assert(src
.reg
.indirect
== NULL
);
1956 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1957 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1960 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1961 /* The only 64-bit type available on gen7 is DF, so use that. */
1962 reg
.type
= BRW_REGISTER_TYPE_DF
;
1964 /* To avoid floating-point denorm flushing problems, set the type by
1965 * default to an integer type - instructions that need floating point
1966 * semantics will set this to F if they need to
1968 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1969 BRW_REGISTER_TYPE_D
);
1976 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1978 * This function should not be called on any value which may be 64 bits.
1979 * We could theoretically support 64-bit on gen8+ but we choose not to
1980 * because it wouldn't work in general (no gen7 support) and there are
1981 * enough restrictions in 64-bit immediates that you can't take the return
1982 * value and treat it the same as the result of get_nir_src().
1985 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1987 assert(nir_src_bit_size(src
) == 32);
1988 return nir_src_is_const(src
) ?
1989 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1993 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1996 const brw_reg_type reg_type
=
1997 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1998 dest
.ssa
.bit_size
== 8 ?
1999 BRW_REGISTER_TYPE_D
:
2000 BRW_REGISTER_TYPE_F
);
2001 nir_ssa_values
[dest
.ssa
.index
] =
2002 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
2003 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
2004 return nir_ssa_values
[dest
.ssa
.index
];
2006 /* We don't handle indirects on locals */
2007 assert(dest
.reg
.indirect
== NULL
);
2008 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
2009 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
2014 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
2017 for (unsigned i
= 0; i
< 4; i
++) {
2018 if (!((wr_mask
>> i
) & 1))
2021 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
2022 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
2023 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
2024 if (new_inst
->src
[j
].file
== VGRF
)
2025 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2032 emit_pixel_interpolater_send(const fs_builder
&bld
,
2037 glsl_interp_mode interpolation
)
2039 struct brw_wm_prog_data
*wm_prog_data
=
2040 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2042 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2043 /* 2 floats per slot returned */
2044 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2045 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2047 wm_prog_data
->pulls_bary
= true;
2053 * Computes 1 << x, given a D/UD register containing some value x.
2056 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2058 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2060 fs_reg result
= bld
.vgrf(x
.type
, 1);
2061 fs_reg one
= bld
.vgrf(x
.type
, 1);
2063 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2064 bld
.SHL(result
, one
, x
);
2069 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2071 assert(stage
== MESA_SHADER_GEOMETRY
);
2073 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2075 if (gs_compile
->control_data_header_size_bits
== 0)
2078 /* We can only do EndPrimitive() functionality when the control data
2079 * consists of cut bits. Fortunately, the only time it isn't is when the
2080 * output type is points, in which case EndPrimitive() is a no-op.
2082 if (gs_prog_data
->control_data_format
!=
2083 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2087 /* Cut bits use one bit per vertex. */
2088 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2090 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2091 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2093 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2094 * vertex n, 0 otherwise. So all we need to do here is mark bit
2095 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2096 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2097 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2099 * Note that if EndPrimitive() is called before emitting any vertices, this
2100 * will cause us to set bit 31 of the control_data_bits register to 1.
2101 * That's fine because:
2103 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2104 * output, so the hardware will ignore cut bit 31.
2106 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2107 * last vertex, so setting cut bit 31 has no effect (since the primitive
2108 * is automatically ended when the GS terminates).
2110 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2111 * control_data_bits register to 0 when the first vertex is emitted.
2114 const fs_builder abld
= bld
.annotate("end primitive");
2116 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2117 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2118 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2119 fs_reg mask
= intexp2(abld
, prev_count
);
2120 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2121 * attention to the lower 5 bits of its second source argument, so on this
2122 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2123 * ((vertex_count - 1) % 32).
2125 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2129 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2131 assert(stage
== MESA_SHADER_GEOMETRY
);
2132 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2134 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2136 const fs_builder abld
= bld
.annotate("emit control data bits");
2137 const fs_builder fwa_bld
= bld
.exec_all();
2139 /* We use a single UD register to accumulate control data bits (32 bits
2140 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2143 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2144 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2145 * use the Channel Mask phase to enable/disable which DWord within that
2146 * group to write. (Remember, different SIMD8 channels may have emitted
2147 * different numbers of vertices, so we may need per-slot offsets.)
2149 * Channel masking presents an annoying problem: we may have to replicate
2150 * the data up to 4 times:
2152 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2154 * To avoid penalizing shaders that emit a small number of vertices, we
2155 * can avoid these sometimes: if the size of the control data header is
2156 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2157 * land in the same 128-bit group, so we can skip per-slot offsets.
2159 * Similarly, if the control data header is <= 32 bits, there is only one
2160 * DWord, so we can skip channel masks.
2162 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2164 fs_reg channel_mask
, per_slot_offset
;
2166 if (gs_compile
->control_data_header_size_bits
> 32) {
2167 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2168 channel_mask
= vgrf(glsl_type::uint_type
);
2171 if (gs_compile
->control_data_header_size_bits
> 128) {
2172 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2173 per_slot_offset
= vgrf(glsl_type::uint_type
);
2176 /* Figure out which DWord we're trying to write to using the formula:
2178 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2180 * Since bits_per_vertex is a power of two, and is known at compile
2181 * time, this can be optimized to:
2183 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2185 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2186 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2187 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2188 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2189 unsigned log2_bits_per_vertex
=
2190 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2191 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2193 if (per_slot_offset
.file
!= BAD_FILE
) {
2194 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2195 * the appropriate OWord within the control data header.
2197 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2200 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2201 * write to the appropriate DWORD within the OWORD.
2203 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2204 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2205 channel_mask
= intexp2(fwa_bld
, channel
);
2206 /* Then the channel masks need to be in bits 23:16. */
2207 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2210 /* Store the control data bits in the message payload and send it. */
2212 if (channel_mask
.file
!= BAD_FILE
)
2213 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2214 if (per_slot_offset
.file
!= BAD_FILE
)
2217 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2218 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2220 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2221 if (per_slot_offset
.file
!= BAD_FILE
)
2222 sources
[i
++] = per_slot_offset
;
2223 if (channel_mask
.file
!= BAD_FILE
)
2224 sources
[i
++] = channel_mask
;
2226 sources
[i
++] = this->control_data_bits
;
2229 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2230 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2232 /* We need to increment Global Offset by 256-bits to make room for
2233 * Broadwell's extra "Vertex Count" payload at the beginning of the
2234 * URB entry. Since this is an OWord message, Global Offset is counted
2235 * in 128-bit units, so we must set it to 2.
2237 if (gs_prog_data
->static_vertex_count
== -1)
2242 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2245 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2247 /* Note: we are calling this *before* increasing vertex_count, so
2248 * this->vertex_count == vertex_count - 1 in the formula above.
2251 /* Stream mode uses 2 bits per vertex */
2252 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2254 /* Must be a valid stream */
2255 assert(stream_id
< MAX_VERTEX_STREAMS
);
2257 /* Control data bits are initialized to 0 so we don't have to set any
2258 * bits when sending vertices to stream 0.
2263 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2265 /* reg::sid = stream_id */
2266 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2267 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2269 /* reg:shift_count = 2 * (vertex_count - 1) */
2270 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2271 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2273 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2274 * attention to the lower 5 bits of its second source argument, so on this
2275 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2276 * stream_id << ((2 * (vertex_count - 1)) % 32).
2278 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2279 abld
.SHL(mask
, sid
, shift_count
);
2280 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2284 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2287 assert(stage
== MESA_SHADER_GEOMETRY
);
2289 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2291 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2292 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2294 /* Haswell and later hardware ignores the "Render Stream Select" bits
2295 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2296 * and instead sends all primitives down the pipeline for rasterization.
2297 * If the SOL stage is enabled, "Render Stream Select" is honored and
2298 * primitives bound to non-zero streams are discarded after stream output.
2300 * Since the only purpose of primives sent to non-zero streams is to
2301 * be recorded by transform feedback, we can simply discard all geometry
2302 * bound to these streams when transform feedback is disabled.
2304 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2307 /* If we're outputting 32 control data bits or less, then we can wait
2308 * until the shader is over to output them all. Otherwise we need to
2309 * output them as we go. Now is the time to do it, since we're about to
2310 * output the vertex_count'th vertex, so it's guaranteed that the
2311 * control data bits associated with the (vertex_count - 1)th vertex are
2314 if (gs_compile
->control_data_header_size_bits
> 32) {
2315 const fs_builder abld
=
2316 bld
.annotate("emit vertex: emit control data bits");
2318 /* Only emit control data bits if we've finished accumulating a batch
2319 * of 32 bits. This is the case when:
2321 * (vertex_count * bits_per_vertex) % 32 == 0
2323 * (in other words, when the last 5 bits of vertex_count *
2324 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2325 * integer n (which is always the case, since bits_per_vertex is
2326 * always 1 or 2), this is equivalent to requiring that the last 5-n
2327 * bits of vertex_count are 0:
2329 * vertex_count & (2^(5-n) - 1) == 0
2331 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2334 * vertex_count & (32 / bits_per_vertex - 1) == 0
2336 * TODO: If vertex_count is an immediate, we could do some of this math
2337 * at compile time...
2340 abld
.AND(bld
.null_reg_d(), vertex_count
,
2341 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2342 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2344 abld
.IF(BRW_PREDICATE_NORMAL
);
2345 /* If vertex_count is 0, then no control data bits have been
2346 * accumulated yet, so we can skip emitting them.
2348 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2349 BRW_CONDITIONAL_NEQ
);
2350 abld
.IF(BRW_PREDICATE_NORMAL
);
2351 emit_gs_control_data_bits(vertex_count
);
2352 abld
.emit(BRW_OPCODE_ENDIF
);
2354 /* Reset control_data_bits to 0 so we can start accumulating a new
2357 * Note: in the case where vertex_count == 0, this neutralizes the
2358 * effect of any call to EndPrimitive() that the shader may have
2359 * made before outputting its first vertex.
2361 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2362 inst
->force_writemask_all
= true;
2363 abld
.emit(BRW_OPCODE_ENDIF
);
2366 emit_urb_writes(vertex_count
);
2368 /* In stream mode we have to set control data bits for all vertices
2369 * unless we have disabled control data bits completely (which we do
2370 * do for GL_POINTS outputs that don't use streams).
2372 if (gs_compile
->control_data_header_size_bits
> 0 &&
2373 gs_prog_data
->control_data_format
==
2374 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2375 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2380 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2381 const nir_src
&vertex_src
,
2382 unsigned base_offset
,
2383 const nir_src
&offset_src
,
2384 unsigned num_components
,
2385 unsigned first_component
)
2387 assert(type_sz(dst
.type
) == 4);
2388 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2389 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2391 /* TODO: figure out push input layout for invocations == 1 */
2392 if (gs_prog_data
->invocations
== 1 &&
2393 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2394 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2395 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2396 nir_src_as_uint(vertex_src
) * push_reg_count
;
2397 for (unsigned i
= 0; i
< num_components
; i
++) {
2398 bld
.MOV(offset(dst
, bld
, i
),
2399 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2404 /* Resort to the pull model. Ensure the VUE handles are provided. */
2405 assert(gs_prog_data
->base
.include_vue_handles
);
2407 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2408 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2410 if (gs_prog_data
->invocations
== 1) {
2411 if (nir_src_is_const(vertex_src
)) {
2412 /* The vertex index is constant; just select the proper URB handle. */
2414 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2415 BRW_REGISTER_TYPE_UD
);
2417 /* The vertex index is non-constant. We need to use indirect
2418 * addressing to fetch the proper URB handle.
2420 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2421 * indicating that channel <n> should read the handle from
2422 * DWord <n>. We convert that to bytes by multiplying by 4.
2424 * Next, we convert the vertex index to bytes by multiplying
2425 * by 32 (shifting by 5), and add the two together. This is
2426 * the final indirect byte offset.
2428 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2429 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2430 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2431 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2433 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2434 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2435 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2436 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2437 /* Convert vertex_index to bytes (multiply by 32) */
2438 bld
.SHL(vertex_offset_bytes
,
2439 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2441 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2443 /* Use first_icp_handle as the base offset. There is one register
2444 * of URB handles per vertex, so inform the register allocator that
2445 * we might read up to nir->info.gs.vertices_in registers.
2447 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2448 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2449 fs_reg(icp_offset_bytes
),
2450 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2453 assert(gs_prog_data
->invocations
> 1);
2455 if (nir_src_is_const(vertex_src
)) {
2456 unsigned vertex
= nir_src_as_uint(vertex_src
);
2457 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2459 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2460 BRW_REGISTER_TYPE_UD
));
2462 /* The vertex index is non-constant. We need to use indirect
2463 * addressing to fetch the proper URB handle.
2466 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2468 /* Convert vertex_index to bytes (multiply by 4) */
2469 bld
.SHL(icp_offset_bytes
,
2470 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2473 /* Use first_icp_handle as the base offset. There is one DWord
2474 * of URB handles per vertex, so inform the register allocator that
2475 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2477 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2478 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2479 fs_reg(icp_offset_bytes
),
2480 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2486 fs_reg indirect_offset
= get_nir_src(offset_src
);
2488 if (nir_src_is_const(offset_src
)) {
2489 /* Constant indexing - use global offset. */
2490 if (first_component
!= 0) {
2491 unsigned read_components
= num_components
+ first_component
;
2492 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2493 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2494 inst
->size_written
= read_components
*
2495 tmp
.component_size(inst
->exec_size
);
2496 for (unsigned i
= 0; i
< num_components
; i
++) {
2497 bld
.MOV(offset(dst
, bld
, i
),
2498 offset(tmp
, bld
, i
+ first_component
));
2501 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2502 inst
->size_written
= num_components
*
2503 dst
.component_size(inst
->exec_size
);
2505 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2508 /* Indirect indexing - use per-slot offsets as well. */
2509 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2510 unsigned read_components
= num_components
+ first_component
;
2511 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2512 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2513 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2514 if (first_component
!= 0) {
2515 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2517 inst
->size_written
= read_components
*
2518 tmp
.component_size(inst
->exec_size
);
2519 for (unsigned i
= 0; i
< num_components
; i
++) {
2520 bld
.MOV(offset(dst
, bld
, i
),
2521 offset(tmp
, bld
, i
+ first_component
));
2524 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2525 inst
->size_written
= num_components
*
2526 dst
.component_size(inst
->exec_size
);
2528 inst
->offset
= base_offset
;
2534 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2536 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2538 if (nir_src_is_const(*offset_src
)) {
2539 /* The only constant offset we should find is 0. brw_nir.c's
2540 * add_const_offset_to_base() will fold other constant offsets
2541 * into instr->const_index[0].
2543 assert(nir_src_as_uint(*offset_src
) == 0);
2547 return get_nir_src(*offset_src
);
2551 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2552 nir_intrinsic_instr
*instr
)
2554 assert(stage
== MESA_SHADER_VERTEX
);
2557 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2558 dest
= get_nir_dest(instr
->dest
);
2560 switch (instr
->intrinsic
) {
2561 case nir_intrinsic_load_vertex_id
:
2562 case nir_intrinsic_load_base_vertex
:
2563 unreachable("should be lowered by nir_lower_system_values()");
2565 case nir_intrinsic_load_input
: {
2566 assert(nir_dest_bit_size(instr
->dest
) == 32);
2567 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2568 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2569 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2571 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2572 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2576 case nir_intrinsic_load_vertex_id_zero_base
:
2577 case nir_intrinsic_load_instance_id
:
2578 case nir_intrinsic_load_base_instance
:
2579 case nir_intrinsic_load_draw_id
:
2580 case nir_intrinsic_load_first_vertex
:
2581 case nir_intrinsic_load_is_indexed_draw
:
2582 unreachable("lowered by brw_nir_lower_vs_inputs");
2585 nir_emit_intrinsic(bld
, instr
);
2591 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2592 nir_intrinsic_instr
*instr
)
2594 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2595 const nir_src
&vertex_src
= instr
->src
[0];
2596 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2599 if (nir_src_is_const(vertex_src
)) {
2600 /* Emit a MOV to resolve <0,1,0> regioning. */
2601 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2602 unsigned vertex
= nir_src_as_uint(vertex_src
);
2604 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2605 BRW_REGISTER_TYPE_UD
));
2606 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2607 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2608 /* For the common case of only 1 instance, an array index of
2609 * gl_InvocationID means reading g1. Skip all the indirect work.
2611 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2613 /* The vertex index is non-constant. We need to use indirect
2614 * addressing to fetch the proper URB handle.
2616 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2618 /* Each ICP handle is a single DWord (4 bytes) */
2619 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2620 bld
.SHL(vertex_offset_bytes
,
2621 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2624 /* Start at g1. We might read up to 4 registers. */
2625 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2626 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2627 brw_imm_ud(4 * REG_SIZE
));
2634 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2635 nir_intrinsic_instr
*instr
)
2637 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2638 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2639 const nir_src
&vertex_src
= instr
->src
[0];
2641 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2643 if (nir_src_is_const(vertex_src
)) {
2644 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2645 nir_src_as_uint(vertex_src
), 0),
2646 BRW_REGISTER_TYPE_UD
));
2649 /* The vertex index is non-constant. We need to use indirect
2650 * addressing to fetch the proper URB handle.
2652 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2653 * indicating that channel <n> should read the handle from
2654 * DWord <n>. We convert that to bytes by multiplying by 4.
2656 * Next, we convert the vertex index to bytes by multiplying
2657 * by 32 (shifting by 5), and add the two together. This is
2658 * the final indirect byte offset.
2660 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2661 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2662 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2663 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2664 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2666 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2667 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2668 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2669 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2670 /* Convert vertex_index to bytes (multiply by 32) */
2671 bld
.SHL(vertex_offset_bytes
,
2672 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2674 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2676 /* Use first_icp_handle as the base offset. There is one register
2677 * of URB handles per vertex, so inform the register allocator that
2678 * we might read up to nir->info.gs.vertices_in registers.
2680 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2681 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2682 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2688 fs_visitor::get_tcs_output_urb_handle()
2690 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2692 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2693 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2695 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2696 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2701 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2702 nir_intrinsic_instr
*instr
)
2704 assert(stage
== MESA_SHADER_TESS_CTRL
);
2705 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2706 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2707 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2710 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2713 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2714 dst
= get_nir_dest(instr
->dest
);
2716 switch (instr
->intrinsic
) {
2717 case nir_intrinsic_load_primitive_id
:
2718 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2719 : brw_vec1_grf(0, 1)));
2721 case nir_intrinsic_load_invocation_id
:
2722 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2724 case nir_intrinsic_load_patch_vertices_in
:
2725 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2726 brw_imm_d(tcs_key
->input_vertices
));
2729 case nir_intrinsic_barrier
: {
2730 if (tcs_prog_data
->instances
== 1)
2733 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2734 fs_reg m0_2
= component(m0
, 2);
2736 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2738 /* Zero the message header */
2739 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2741 if (devinfo
->gen
< 11) {
2742 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2743 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2744 brw_imm_ud(INTEL_MASK(16, 13)));
2746 /* Shift it up to bits 27:24. */
2747 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2749 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2750 brw_imm_ud(INTEL_MASK(30, 24)));
2753 /* Set the Barrier Count and the enable bit */
2754 if (devinfo
->gen
< 11) {
2755 chanbld
.OR(m0_2
, m0_2
,
2756 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2758 chanbld
.OR(m0_2
, m0_2
,
2759 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2762 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2766 case nir_intrinsic_load_input
:
2767 unreachable("nir_lower_io should never give us these.");
2770 case nir_intrinsic_load_per_vertex_input
: {
2771 assert(nir_dest_bit_size(instr
->dest
) == 32);
2772 fs_reg indirect_offset
= get_indirect_offset(instr
);
2773 unsigned imm_offset
= instr
->const_index
[0];
2777 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2778 : get_tcs_single_patch_icp_handle(bld
, instr
);
2780 /* We can only read two double components with each URB read, so
2781 * we send two read messages in that case, each one loading up to
2782 * two double components.
2784 unsigned num_components
= instr
->num_components
;
2785 unsigned first_component
= nir_intrinsic_component(instr
);
2787 if (indirect_offset
.file
== BAD_FILE
) {
2788 /* Constant indexing - use global offset. */
2789 if (first_component
!= 0) {
2790 unsigned read_components
= num_components
+ first_component
;
2791 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2792 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2793 for (unsigned i
= 0; i
< num_components
; i
++) {
2794 bld
.MOV(offset(dst
, bld
, i
),
2795 offset(tmp
, bld
, i
+ first_component
));
2798 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2800 inst
->offset
= imm_offset
;
2803 /* Indirect indexing - use per-slot offsets as well. */
2804 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2805 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2806 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2807 if (first_component
!= 0) {
2808 unsigned read_components
= num_components
+ first_component
;
2809 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2810 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2812 for (unsigned i
= 0; i
< num_components
; i
++) {
2813 bld
.MOV(offset(dst
, bld
, i
),
2814 offset(tmp
, bld
, i
+ first_component
));
2817 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2820 inst
->offset
= imm_offset
;
2823 inst
->size_written
= (num_components
+ first_component
) *
2824 inst
->dst
.component_size(inst
->exec_size
);
2826 /* Copy the temporary to the destination to deal with writemasking.
2828 * Also attempt to deal with gl_PointSize being in the .w component.
2830 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2831 assert(type_sz(dst
.type
) == 4);
2832 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2833 inst
->size_written
= 4 * REG_SIZE
;
2834 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2839 case nir_intrinsic_load_output
:
2840 case nir_intrinsic_load_per_vertex_output
: {
2841 assert(nir_dest_bit_size(instr
->dest
) == 32);
2842 fs_reg indirect_offset
= get_indirect_offset(instr
);
2843 unsigned imm_offset
= instr
->const_index
[0];
2844 unsigned first_component
= nir_intrinsic_component(instr
);
2846 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2849 if (indirect_offset
.file
== BAD_FILE
) {
2850 /* This MOV replicates the output handle to all enabled channels
2851 * is SINGLE_PATCH mode.
2853 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2854 bld
.MOV(patch_handle
, output_handles
);
2857 if (first_component
!= 0) {
2858 unsigned read_components
=
2859 instr
->num_components
+ first_component
;
2860 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2861 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2863 inst
->size_written
= read_components
* REG_SIZE
;
2864 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2865 bld
.MOV(offset(dst
, bld
, i
),
2866 offset(tmp
, bld
, i
+ first_component
));
2869 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2871 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2873 inst
->offset
= imm_offset
;
2877 /* Indirect indexing - use per-slot offsets as well. */
2878 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2879 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2880 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2881 if (first_component
!= 0) {
2882 unsigned read_components
=
2883 instr
->num_components
+ first_component
;
2884 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2885 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2887 inst
->size_written
= read_components
* REG_SIZE
;
2888 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2889 bld
.MOV(offset(dst
, bld
, i
),
2890 offset(tmp
, bld
, i
+ first_component
));
2893 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2895 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2897 inst
->offset
= imm_offset
;
2903 case nir_intrinsic_store_output
:
2904 case nir_intrinsic_store_per_vertex_output
: {
2905 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2906 fs_reg value
= get_nir_src(instr
->src
[0]);
2907 fs_reg indirect_offset
= get_indirect_offset(instr
);
2908 unsigned imm_offset
= instr
->const_index
[0];
2909 unsigned mask
= instr
->const_index
[1];
2910 unsigned header_regs
= 0;
2911 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2914 srcs
[header_regs
++] = output_handles
;
2916 if (indirect_offset
.file
!= BAD_FILE
) {
2917 srcs
[header_regs
++] = indirect_offset
;
2923 unsigned num_components
= util_last_bit(mask
);
2926 /* We can only pack two 64-bit components in a single message, so send
2927 * 2 messages if we have more components
2929 unsigned first_component
= nir_intrinsic_component(instr
);
2930 mask
= mask
<< first_component
;
2932 if (mask
!= WRITEMASK_XYZW
) {
2933 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2934 opcode
= indirect_offset
.file
!= BAD_FILE
?
2935 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2936 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2938 opcode
= indirect_offset
.file
!= BAD_FILE
?
2939 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2940 SHADER_OPCODE_URB_WRITE_SIMD8
;
2943 for (unsigned i
= 0; i
< num_components
; i
++) {
2944 if (!(mask
& (1 << (i
+ first_component
))))
2947 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2950 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2952 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2953 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2955 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2956 inst
->offset
= imm_offset
;
2962 nir_emit_intrinsic(bld
, instr
);
2968 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2969 nir_intrinsic_instr
*instr
)
2971 assert(stage
== MESA_SHADER_TESS_EVAL
);
2972 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2975 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2976 dest
= get_nir_dest(instr
->dest
);
2978 switch (instr
->intrinsic
) {
2979 case nir_intrinsic_load_primitive_id
:
2980 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2982 case nir_intrinsic_load_tess_coord
:
2983 /* gl_TessCoord is part of the payload in g1-3 */
2984 for (unsigned i
= 0; i
< 3; i
++) {
2985 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2989 case nir_intrinsic_load_input
:
2990 case nir_intrinsic_load_per_vertex_input
: {
2991 assert(nir_dest_bit_size(instr
->dest
) == 32);
2992 fs_reg indirect_offset
= get_indirect_offset(instr
);
2993 unsigned imm_offset
= instr
->const_index
[0];
2994 unsigned first_component
= nir_intrinsic_component(instr
);
2997 if (indirect_offset
.file
== BAD_FILE
) {
2998 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2999 * which is 16 registers (since each holds 2 vec4 slots).
3001 const unsigned max_push_slots
= 32;
3002 if (imm_offset
< max_push_slots
) {
3003 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3004 for (int i
= 0; i
< instr
->num_components
; i
++) {
3005 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
3006 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3009 tes_prog_data
->base
.urb_read_length
=
3010 MAX2(tes_prog_data
->base
.urb_read_length
,
3011 (imm_offset
/ 2) + 1);
3013 /* Replicate the patch handle to all enabled channels */
3014 const fs_reg srcs
[] = {
3015 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3017 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3018 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3020 if (first_component
!= 0) {
3021 unsigned read_components
=
3022 instr
->num_components
+ first_component
;
3023 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3024 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3026 inst
->size_written
= read_components
* REG_SIZE
;
3027 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3028 bld
.MOV(offset(dest
, bld
, i
),
3029 offset(tmp
, bld
, i
+ first_component
));
3032 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3034 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3037 inst
->offset
= imm_offset
;
3040 /* Indirect indexing - use per-slot offsets as well. */
3042 /* We can only read two double components with each URB read, so
3043 * we send two read messages in that case, each one loading up to
3044 * two double components.
3046 unsigned num_components
= instr
->num_components
;
3047 const fs_reg srcs
[] = {
3048 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3051 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3052 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3054 if (first_component
!= 0) {
3055 unsigned read_components
=
3056 num_components
+ first_component
;
3057 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3058 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3060 for (unsigned i
= 0; i
< num_components
; i
++) {
3061 bld
.MOV(offset(dest
, bld
, i
),
3062 offset(tmp
, bld
, i
+ first_component
));
3065 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3069 inst
->offset
= imm_offset
;
3070 inst
->size_written
= (num_components
+ first_component
) *
3071 inst
->dst
.component_size(inst
->exec_size
);
3076 nir_emit_intrinsic(bld
, instr
);
3082 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3083 nir_intrinsic_instr
*instr
)
3085 assert(stage
== MESA_SHADER_GEOMETRY
);
3086 fs_reg indirect_offset
;
3089 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3090 dest
= get_nir_dest(instr
->dest
);
3092 switch (instr
->intrinsic
) {
3093 case nir_intrinsic_load_primitive_id
:
3094 assert(stage
== MESA_SHADER_GEOMETRY
);
3095 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3096 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3097 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3100 case nir_intrinsic_load_input
:
3101 unreachable("load_input intrinsics are invalid for the GS stage");
3103 case nir_intrinsic_load_per_vertex_input
:
3104 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3105 instr
->src
[1], instr
->num_components
,
3106 nir_intrinsic_component(instr
));
3109 case nir_intrinsic_emit_vertex_with_counter
:
3110 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3113 case nir_intrinsic_end_primitive_with_counter
:
3114 emit_gs_end_primitive(instr
->src
[0]);
3117 case nir_intrinsic_set_vertex_count
:
3118 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3121 case nir_intrinsic_load_invocation_id
: {
3122 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3123 assert(val
.file
!= BAD_FILE
);
3124 dest
.type
= val
.type
;
3130 nir_emit_intrinsic(bld
, instr
);
3136 * Fetch the current render target layer index.
3139 fetch_render_target_array_index(const fs_builder
&bld
)
3141 if (bld
.shader
->devinfo
->gen
>= 6) {
3142 /* The render target array index is provided in the thread payload as
3143 * bits 26:16 of r0.0.
3145 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3146 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3150 /* Pre-SNB we only ever render into the first layer of the framebuffer
3151 * since layered rendering is not implemented.
3153 return brw_imm_ud(0);
3158 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3159 * framebuffer at the current fragment coordinates and sample index.
3162 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3165 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3167 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3168 const brw_wm_prog_key
*wm_key
=
3169 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3170 assert(!wm_key
->coherent_fb_fetch
);
3171 const struct brw_wm_prog_data
*wm_prog_data
=
3172 brw_wm_prog_data(stage_prog_data
);
3174 /* Calculate the surface index relative to the start of the texture binding
3175 * table block, since that's what the texturing messages expect.
3177 const unsigned surface
= target
+
3178 wm_prog_data
->binding_table
.render_target_read_start
-
3179 wm_prog_data
->base
.binding_table
.texture_start
;
3181 /* Calculate the fragment coordinates. */
3182 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3183 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3184 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3185 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3187 /* Calculate the sample index and MCS payload when multisampling. Luckily
3188 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3189 * shouldn't be necessary to recompile based on whether the framebuffer is
3192 if (wm_key
->multisample_fbo
&&
3193 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3194 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3196 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3197 const fs_reg mcs
= wm_key
->multisample_fbo
?
3198 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3200 /* Use either a normal or a CMS texel fetch message depending on whether
3201 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3202 * message just in case the framebuffer uses 16x multisampling, it should
3203 * be equivalent to the normal CMS fetch for lower multisampling modes.
3205 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3206 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3207 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3209 /* Emit the instruction. */
3210 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3211 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3212 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3213 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3214 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3215 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3216 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3217 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3218 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3220 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3221 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3227 * Actual coherent framebuffer read implemented using the native render target
3228 * read message. Requires SKL+.
3231 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3233 assert(bld
.shader
->devinfo
->gen
>= 9);
3234 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3235 inst
->target
= target
;
3236 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3242 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3244 if (n
&& regs
[0].file
!= BAD_FILE
) {
3248 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3250 for (unsigned i
= 0; i
< n
; i
++)
3258 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3260 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3261 const brw_wm_prog_key
*const key
=
3262 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3263 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3264 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3266 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3267 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3269 else if (l
== FRAG_RESULT_COLOR
)
3270 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3271 MAX2(key
->nr_color_regions
, 1));
3273 else if (l
== FRAG_RESULT_DEPTH
)
3274 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3276 else if (l
== FRAG_RESULT_STENCIL
)
3277 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3279 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3280 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3282 else if (l
>= FRAG_RESULT_DATA0
&&
3283 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3284 return alloc_temporary(v
->bld
, 4,
3285 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3288 unreachable("Invalid location");
3291 /* Annoyingly, we get the barycentrics into the shader in a layout that's
3292 * optimized for PLN but it doesn't work nearly as well as one would like for
3293 * manual interpolation.
3296 shuffle_from_pln_layout(const fs_builder
&bld
, fs_reg dest
, fs_reg pln_data
)
3298 dest
.type
= BRW_REGISTER_TYPE_F
;
3299 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3300 const fs_reg dest_u
= offset(dest
, bld
, 0);
3301 const fs_reg dest_v
= offset(dest
, bld
, 1);
3303 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3304 const fs_builder gbld
= bld
.group(8, g
);
3305 gbld
.MOV(horiz_offset(dest_u
, g
* 8),
3306 byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
));
3307 gbld
.MOV(horiz_offset(dest_v
, g
* 8),
3308 byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
));
3313 shuffle_to_pln_layout(const fs_builder
&bld
, fs_reg pln_data
, fs_reg src
)
3315 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3316 src
.type
= BRW_REGISTER_TYPE_F
;
3317 const fs_reg src_u
= offset(src
, bld
, 0);
3318 const fs_reg src_v
= offset(src
, bld
, 1);
3320 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3321 const fs_builder gbld
= bld
.group(8, g
);
3322 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
),
3323 horiz_offset(src_u
, g
* 8));
3324 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
),
3325 horiz_offset(src_v
, g
* 8));
3330 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3331 nir_intrinsic_instr
*instr
)
3333 assert(stage
== MESA_SHADER_FRAGMENT
);
3336 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3337 dest
= get_nir_dest(instr
->dest
);
3339 switch (instr
->intrinsic
) {
3340 case nir_intrinsic_load_front_face
:
3341 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3342 *emit_frontfacing_interpolation());
3345 case nir_intrinsic_load_sample_pos
: {
3346 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3347 assert(sample_pos
.file
!= BAD_FILE
);
3348 dest
.type
= sample_pos
.type
;
3349 bld
.MOV(dest
, sample_pos
);
3350 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3354 case nir_intrinsic_load_layer_id
:
3355 dest
.type
= BRW_REGISTER_TYPE_UD
;
3356 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3359 case nir_intrinsic_is_helper_invocation
: {
3360 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3361 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3362 * consideration demoted invocations. That information is stored in
3365 dest
.type
= BRW_REGISTER_TYPE_UD
;
3367 bld
.MOV(dest
, brw_imm_ud(0));
3369 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3370 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3371 mov
->predicate_inverse
= true;
3372 mov
->flag_subreg
= 1;
3376 case nir_intrinsic_load_helper_invocation
:
3377 case nir_intrinsic_load_sample_mask_in
:
3378 case nir_intrinsic_load_sample_id
: {
3379 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3380 fs_reg val
= nir_system_values
[sv
];
3381 assert(val
.file
!= BAD_FILE
);
3382 dest
.type
= val
.type
;
3387 case nir_intrinsic_store_output
: {
3388 const fs_reg src
= get_nir_src(instr
->src
[0]);
3389 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3390 const unsigned location
= nir_intrinsic_base(instr
) +
3391 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3392 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3395 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3396 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3397 offset(src
, bld
, j
));
3402 case nir_intrinsic_load_output
: {
3403 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3404 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3405 assert(l
>= FRAG_RESULT_DATA0
);
3406 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3407 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3408 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3410 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3411 emit_coherent_fb_read(bld
, tmp
, target
);
3413 emit_non_coherent_fb_read(bld
, tmp
, target
);
3415 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3416 bld
.MOV(offset(dest
, bld
, j
),
3417 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3423 case nir_intrinsic_demote
:
3424 case nir_intrinsic_discard
:
3425 case nir_intrinsic_demote_if
:
3426 case nir_intrinsic_discard_if
: {
3427 /* We track our discarded pixels in f0.1. By predicating on it, we can
3428 * update just the flag bits that aren't yet discarded. If there's no
3429 * condition, we emit a CMP of g0 != g0, so all currently executing
3430 * channels will get turned off.
3432 fs_inst
*cmp
= NULL
;
3433 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3434 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3435 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3438 alu
->op
!= nir_op_bcsel
&&
3439 alu
->op
!= nir_op_inot
) {
3440 /* Re-emit the instruction that generated the Boolean value, but
3441 * do not store it. Since this instruction will be conditional,
3442 * other instructions that want to use the real Boolean value may
3443 * get garbage. This was a problem for piglit's fs-discard-exit-2
3446 * Ideally we'd detect that the instruction cannot have a
3447 * conditional modifier before emitting the instructions. Alas,
3448 * that is nigh impossible. Instead, we're going to assume the
3449 * instruction (or last instruction) generated can have a
3450 * conditional modifier. If it cannot, fallback to the old-style
3451 * compare, and hope dead code elimination will clean up the
3452 * extra instructions generated.
3454 nir_emit_alu(bld
, alu
, false);
3456 cmp
= (fs_inst
*) instructions
.get_tail();
3457 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3458 if (cmp
->can_do_cmod())
3459 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3463 /* The old sequence that would have been generated is,
3464 * basically, bool_result == false. This is equivalent to
3465 * !bool_result, so negate the old modifier.
3467 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3472 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3473 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3476 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3477 BRW_REGISTER_TYPE_UW
));
3478 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3481 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3482 cmp
->flag_subreg
= 1;
3484 if (devinfo
->gen
>= 6) {
3485 /* Due to the way we implement discard, the jump will only happen
3486 * when the whole quad is discarded. So we can do this even for
3487 * demote as it won't break its uniformity promises.
3489 emit_discard_jump();
3492 limit_dispatch_width(16, "Fragment discard/demote not implemented in SIMD32 mode.");
3496 case nir_intrinsic_load_input
: {
3497 /* load_input is only used for flat inputs */
3498 assert(nir_dest_bit_size(instr
->dest
) == 32);
3499 unsigned base
= nir_intrinsic_base(instr
);
3500 unsigned comp
= nir_intrinsic_component(instr
);
3501 unsigned num_components
= instr
->num_components
;
3503 /* Special case fields in the VUE header */
3504 if (base
== VARYING_SLOT_LAYER
)
3506 else if (base
== VARYING_SLOT_VIEWPORT
)
3509 for (unsigned int i
= 0; i
< num_components
; i
++) {
3510 bld
.MOV(offset(dest
, bld
, i
),
3511 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3516 case nir_intrinsic_load_fs_input_interp_deltas
: {
3517 assert(stage
== MESA_SHADER_FRAGMENT
);
3518 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3519 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3520 nir_intrinsic_component(instr
));
3521 dest
.type
= BRW_REGISTER_TYPE_F
;
3522 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3523 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3524 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3528 case nir_intrinsic_load_barycentric_pixel
:
3529 case nir_intrinsic_load_barycentric_centroid
:
3530 case nir_intrinsic_load_barycentric_sample
: {
3531 /* Use the delta_xy values computed from the payload */
3532 const glsl_interp_mode interp_mode
=
3533 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3534 enum brw_barycentric_mode bary
=
3535 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3537 shuffle_from_pln_layout(bld
, dest
, this->delta_xy
[bary
]);
3541 case nir_intrinsic_load_barycentric_at_sample
: {
3542 const glsl_interp_mode interpolation
=
3543 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3545 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3546 if (nir_src_is_const(instr
->src
[0])) {
3547 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3549 emit_pixel_interpolater_send(bld
,
3550 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3553 brw_imm_ud(msg_data
),
3556 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3557 BRW_REGISTER_TYPE_UD
);
3559 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3560 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3561 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3562 bld
.exec_all().group(1, 0)
3563 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3564 emit_pixel_interpolater_send(bld
,
3565 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3571 /* Make a loop that sends a message to the pixel interpolater
3572 * for the sample number in each live channel. If there are
3573 * multiple channels with the same sample number then these
3574 * will be handled simultaneously with a single interation of
3577 bld
.emit(BRW_OPCODE_DO
);
3579 /* Get the next live sample number into sample_id_reg */
3580 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3582 /* Set the flag register so that we can perform the send
3583 * message on all channels that have the same sample number
3585 bld
.CMP(bld
.null_reg_ud(),
3586 sample_src
, sample_id
,
3587 BRW_CONDITIONAL_EQ
);
3588 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3589 bld
.exec_all().group(1, 0)
3590 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3592 emit_pixel_interpolater_send(bld
,
3593 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3596 component(msg_data
, 0),
3598 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3600 /* Continue the loop if there are any live channels left */
3601 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3603 bld
.emit(BRW_OPCODE_WHILE
));
3606 shuffle_from_pln_layout(bld
, dest
, tmp
);
3610 case nir_intrinsic_load_barycentric_at_offset
: {
3611 const glsl_interp_mode interpolation
=
3612 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3614 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3616 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3618 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3619 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3620 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3622 emit_pixel_interpolater_send(bld
,
3623 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3626 brw_imm_ud(off_x
| (off_y
<< 4)),
3629 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3630 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3631 BRW_REGISTER_TYPE_F
);
3632 for (int i
= 0; i
< 2; i
++) {
3633 fs_reg temp
= vgrf(glsl_type::float_type
);
3634 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3635 fs_reg itemp
= vgrf(glsl_type::int_type
);
3637 bld
.MOV(itemp
, temp
);
3639 /* Clamp the upper end of the range to +7/16.
3640 * ARB_gpu_shader5 requires that we support a maximum offset
3641 * of +0.5, which isn't representable in a S0.4 value -- if
3642 * we didn't clamp it, we'd end up with -8/16, which is the
3643 * opposite of what the shader author wanted.
3645 * This is legal due to ARB_gpu_shader5's quantization
3648 * "Not all values of <offset> may be supported; x and y
3649 * offsets may be rounded to fixed-point values with the
3650 * number of fraction bits given by the
3651 * implementation-dependent constant
3652 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3654 set_condmod(BRW_CONDITIONAL_L
,
3655 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3658 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3659 emit_pixel_interpolater_send(bld
,
3666 shuffle_from_pln_layout(bld
, dest
, tmp
);
3670 case nir_intrinsic_load_frag_coord
:
3671 emit_fragcoord_interpolation(dest
);
3674 case nir_intrinsic_load_interpolated_input
: {
3675 assert(instr
->src
[0].ssa
&&
3676 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3677 nir_intrinsic_instr
*bary_intrinsic
=
3678 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3679 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3680 enum glsl_interp_mode interp_mode
=
3681 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3684 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3685 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3686 /* Use the result of the PI message. Because the load_barycentric
3687 * intrinsics return a regular vec2 and we need it in PLN layout, we
3688 * have to do a translation. Fortunately, copy-prop cleans this up
3691 dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3692 shuffle_to_pln_layout(bld
, dst_xy
, get_nir_src(instr
->src
[0]));
3694 /* Use the delta_xy values computed from the payload */
3695 enum brw_barycentric_mode bary
=
3696 brw_barycentric_mode(interp_mode
, bary_intrin
);
3698 dst_xy
= this->delta_xy
[bary
];
3701 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3703 component(interp_reg(nir_intrinsic_base(instr
),
3704 nir_intrinsic_component(instr
) + i
), 0);
3705 interp
.type
= BRW_REGISTER_TYPE_F
;
3706 dest
.type
= BRW_REGISTER_TYPE_F
;
3708 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3709 fs_reg tmp
= vgrf(glsl_type::float_type
);
3710 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3711 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3713 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3720 nir_emit_intrinsic(bld
, instr
);
3726 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3727 nir_intrinsic_instr
*instr
)
3729 assert(stage
== MESA_SHADER_COMPUTE
);
3730 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3733 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3734 dest
= get_nir_dest(instr
->dest
);
3736 switch (instr
->intrinsic
) {
3737 case nir_intrinsic_barrier
:
3739 cs_prog_data
->uses_barrier
= true;
3742 case nir_intrinsic_load_subgroup_id
:
3743 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3746 case nir_intrinsic_load_local_invocation_id
:
3747 case nir_intrinsic_load_work_group_id
: {
3748 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3749 fs_reg val
= nir_system_values
[sv
];
3750 assert(val
.file
!= BAD_FILE
);
3751 dest
.type
= val
.type
;
3752 for (unsigned i
= 0; i
< 3; i
++)
3753 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3757 case nir_intrinsic_load_num_work_groups
: {
3758 const unsigned surface
=
3759 cs_prog_data
->binding_table
.work_groups_start
;
3761 cs_prog_data
->uses_num_work_groups
= true;
3763 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3764 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3765 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3766 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3768 /* Read the 3 GLuint components of gl_NumWorkGroups */
3769 for (unsigned i
= 0; i
< 3; i
++) {
3770 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3771 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3772 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3777 case nir_intrinsic_shared_atomic_add
:
3778 case nir_intrinsic_shared_atomic_imin
:
3779 case nir_intrinsic_shared_atomic_umin
:
3780 case nir_intrinsic_shared_atomic_imax
:
3781 case nir_intrinsic_shared_atomic_umax
:
3782 case nir_intrinsic_shared_atomic_and
:
3783 case nir_intrinsic_shared_atomic_or
:
3784 case nir_intrinsic_shared_atomic_xor
:
3785 case nir_intrinsic_shared_atomic_exchange
:
3786 case nir_intrinsic_shared_atomic_comp_swap
:
3787 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3789 case nir_intrinsic_shared_atomic_fmin
:
3790 case nir_intrinsic_shared_atomic_fmax
:
3791 case nir_intrinsic_shared_atomic_fcomp_swap
:
3792 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3795 case nir_intrinsic_load_shared
: {
3796 assert(devinfo
->gen
>= 7);
3797 assert(stage
== MESA_SHADER_COMPUTE
);
3799 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3800 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3801 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3802 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3803 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3805 /* Make dest unsigned because that's what the temporary will be */
3806 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3808 /* Read the vector */
3809 if (nir_intrinsic_align(instr
) >= 4) {
3810 assert(nir_dest_bit_size(instr
->dest
) == 32);
3811 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3813 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3814 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3815 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3817 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3818 assert(nir_dest_num_components(instr
->dest
) == 1);
3819 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3821 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3822 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3823 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3824 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3829 case nir_intrinsic_store_shared
: {
3830 assert(devinfo
->gen
>= 7);
3831 assert(stage
== MESA_SHADER_COMPUTE
);
3833 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3834 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3835 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3836 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3837 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3839 fs_reg data
= get_nir_src(instr
->src
[0]);
3840 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3842 assert(nir_intrinsic_write_mask(instr
) ==
3843 (1u << instr
->num_components
) - 1);
3844 if (nir_intrinsic_align(instr
) >= 4) {
3845 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3846 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3847 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3848 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3849 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3850 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3852 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3853 assert(nir_src_num_components(instr
->src
[0]) == 1);
3854 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3856 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3857 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3859 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3860 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3866 nir_emit_intrinsic(bld
, instr
);
3872 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3873 nir_op op
, brw_reg_type type
)
3875 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3876 switch (type_sz(type
)) {
3878 if (type
== BRW_REGISTER_TYPE_UB
) {
3879 return brw_imm_uw(value
.u8
);
3881 assert(type
== BRW_REGISTER_TYPE_B
);
3882 return brw_imm_w(value
.i8
);
3885 return retype(brw_imm_uw(value
.u16
), type
);
3887 return retype(brw_imm_ud(value
.u32
), type
);
3889 if (type
== BRW_REGISTER_TYPE_DF
)
3890 return setup_imm_df(bld
, value
.f64
);
3892 return retype(brw_imm_u64(value
.u64
), type
);
3894 unreachable("Invalid type size");
3899 brw_op_for_nir_reduction_op(nir_op op
)
3902 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3903 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3904 case nir_op_imul
: return BRW_OPCODE_MUL
;
3905 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3906 case nir_op_imin
: return BRW_OPCODE_SEL
;
3907 case nir_op_umin
: return BRW_OPCODE_SEL
;
3908 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3909 case nir_op_imax
: return BRW_OPCODE_SEL
;
3910 case nir_op_umax
: return BRW_OPCODE_SEL
;
3911 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3912 case nir_op_iand
: return BRW_OPCODE_AND
;
3913 case nir_op_ior
: return BRW_OPCODE_OR
;
3914 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3916 unreachable("Invalid reduction operation");
3920 static brw_conditional_mod
3921 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3924 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3925 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3926 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3927 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3928 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3929 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3930 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3931 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3932 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3933 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3934 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3935 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3936 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3938 unreachable("Invalid reduction operation");
3943 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3944 nir_intrinsic_instr
*instr
)
3946 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3948 if (stage_prog_data
->binding_table
.image_start
> 0) {
3949 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3950 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3952 bld
.ADD(image
, image
,
3953 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3957 return bld
.emit_uniformize(image
);
3961 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3962 nir_intrinsic_instr
*instr
)
3964 /* SSBO stores are weird in that their index is in src[1] */
3965 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3968 if (nir_src_is_const(instr
->src
[src
])) {
3969 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3970 nir_src_as_uint(instr
->src
[src
]);
3971 surf_index
= brw_imm_ud(index
);
3973 surf_index
= vgrf(glsl_type::uint_type
);
3974 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3975 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3978 return bld
.emit_uniformize(surf_index
);
3982 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3984 switch (nir_intrinsic_image_dim(instr
)) {
3985 case GLSL_SAMPLER_DIM_1D
:
3986 return 1 + nir_intrinsic_image_array(instr
);
3987 case GLSL_SAMPLER_DIM_2D
:
3988 case GLSL_SAMPLER_DIM_RECT
:
3989 return 2 + nir_intrinsic_image_array(instr
);
3990 case GLSL_SAMPLER_DIM_3D
:
3991 case GLSL_SAMPLER_DIM_CUBE
:
3993 case GLSL_SAMPLER_DIM_BUF
:
3995 case GLSL_SAMPLER_DIM_MS
:
3996 return 2 + nir_intrinsic_image_array(instr
);
3998 unreachable("Invalid image dimension");
4003 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4006 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4007 dest
= get_nir_dest(instr
->dest
);
4009 switch (instr
->intrinsic
) {
4010 case nir_intrinsic_image_load
:
4011 case nir_intrinsic_image_store
:
4012 case nir_intrinsic_image_atomic_add
:
4013 case nir_intrinsic_image_atomic_imin
:
4014 case nir_intrinsic_image_atomic_umin
:
4015 case nir_intrinsic_image_atomic_imax
:
4016 case nir_intrinsic_image_atomic_umax
:
4017 case nir_intrinsic_image_atomic_and
:
4018 case nir_intrinsic_image_atomic_or
:
4019 case nir_intrinsic_image_atomic_xor
:
4020 case nir_intrinsic_image_atomic_exchange
:
4021 case nir_intrinsic_image_atomic_comp_swap
:
4022 case nir_intrinsic_bindless_image_load
:
4023 case nir_intrinsic_bindless_image_store
:
4024 case nir_intrinsic_bindless_image_atomic_add
:
4025 case nir_intrinsic_bindless_image_atomic_imin
:
4026 case nir_intrinsic_bindless_image_atomic_umin
:
4027 case nir_intrinsic_bindless_image_atomic_imax
:
4028 case nir_intrinsic_bindless_image_atomic_umax
:
4029 case nir_intrinsic_bindless_image_atomic_and
:
4030 case nir_intrinsic_bindless_image_atomic_or
:
4031 case nir_intrinsic_bindless_image_atomic_xor
:
4032 case nir_intrinsic_bindless_image_atomic_exchange
:
4033 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4034 if (stage
== MESA_SHADER_FRAGMENT
&&
4035 instr
->intrinsic
!= nir_intrinsic_image_load
)
4036 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4038 /* Get some metadata from the image intrinsic. */
4039 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4041 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4043 switch (instr
->intrinsic
) {
4044 case nir_intrinsic_image_load
:
4045 case nir_intrinsic_image_store
:
4046 case nir_intrinsic_image_atomic_add
:
4047 case nir_intrinsic_image_atomic_imin
:
4048 case nir_intrinsic_image_atomic_umin
:
4049 case nir_intrinsic_image_atomic_imax
:
4050 case nir_intrinsic_image_atomic_umax
:
4051 case nir_intrinsic_image_atomic_and
:
4052 case nir_intrinsic_image_atomic_or
:
4053 case nir_intrinsic_image_atomic_xor
:
4054 case nir_intrinsic_image_atomic_exchange
:
4055 case nir_intrinsic_image_atomic_comp_swap
:
4056 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4057 get_nir_image_intrinsic_image(bld
, instr
);
4062 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4063 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4067 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4068 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4069 brw_imm_ud(image_intrinsic_coord_components(instr
));
4071 /* Emit an image load, store or atomic op. */
4072 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4073 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4074 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4076 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4077 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4078 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4079 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4080 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4081 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4082 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4083 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4084 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4086 unsigned num_srcs
= info
->num_srcs
;
4087 int op
= brw_aop_for_nir_intrinsic(instr
);
4088 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4089 assert(num_srcs
== 4);
4093 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4097 data
= get_nir_src(instr
->src
[3]);
4098 if (num_srcs
>= 5) {
4099 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4100 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4101 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4104 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4106 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4107 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4112 case nir_intrinsic_image_size
:
4113 case nir_intrinsic_bindless_image_size
: {
4114 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4115 * into will handle the binding table index for us in the geneerator.
4116 * Incidentally, this means that we can handle bindless with exactly the
4119 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4120 BRW_REGISTER_TYPE_UD
);
4121 image
= bld
.emit_uniformize(image
);
4123 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4124 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4125 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4127 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4128 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4129 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4130 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4132 /* Since the image size is always uniform, we can just emit a SIMD8
4133 * query instruction and splat the result out.
4135 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4137 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4138 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4139 tmp
, srcs
, ARRAY_SIZE(srcs
));
4140 inst
->size_written
= 4 * REG_SIZE
;
4142 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4143 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4144 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4145 offset(retype(dest
, tmp
.type
), bld
, c
),
4146 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4148 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4149 component(offset(tmp
, ubld
, c
), 0));
4155 case nir_intrinsic_image_load_raw_intel
: {
4156 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4157 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4158 get_nir_image_intrinsic_image(bld
, instr
);
4159 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4160 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4161 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4164 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4165 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4166 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4170 case nir_intrinsic_image_store_raw_intel
: {
4171 if (stage
== MESA_SHADER_FRAGMENT
)
4172 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4174 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4175 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4176 get_nir_image_intrinsic_image(bld
, instr
);
4177 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4178 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4179 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4180 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4182 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4183 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4187 case nir_intrinsic_group_memory_barrier
:
4188 case nir_intrinsic_memory_barrier_shared
:
4189 case nir_intrinsic_memory_barrier_atomic_counter
:
4190 case nir_intrinsic_memory_barrier_buffer
:
4191 case nir_intrinsic_memory_barrier_image
:
4192 case nir_intrinsic_memory_barrier
: {
4193 bool l3_fence
, slm_fence
;
4194 if (devinfo
->gen
>= 11) {
4195 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4196 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4197 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4198 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4200 /* Prior to gen11, we only have one kind of fence. */
4205 /* Be conservative in Gen11+ and always stall in a fence. Since there
4206 * are two different fences, and shader might want to synchronize
4209 * TODO: Improve NIR so that scope and visibility information for the
4210 * barriers is available here to make a better decision.
4212 * TODO: When emitting more than one fence, it might help emit all
4213 * the fences first and then generate the stall moves.
4215 const bool stall
= devinfo
->gen
>= 11;
4217 const fs_builder ubld
= bld
.group(8, 0);
4218 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4221 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4222 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4223 /* bti */ brw_imm_ud(0))
4224 ->size_written
= 2 * REG_SIZE
;
4228 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4229 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4230 brw_imm_ud(GEN7_BTI_SLM
))
4231 ->size_written
= 2 * REG_SIZE
;
4237 case nir_intrinsic_shader_clock
: {
4238 /* We cannot do anything if there is an event, so ignore it for now */
4239 const fs_reg shader_clock
= get_timestamp(bld
);
4240 const fs_reg srcs
[] = { component(shader_clock
, 0),
4241 component(shader_clock
, 1) };
4242 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4246 case nir_intrinsic_image_samples
:
4247 /* The driver does not support multi-sampled images. */
4248 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4251 case nir_intrinsic_load_uniform
: {
4252 /* Offsets are in bytes but they should always aligned to
4255 assert(instr
->const_index
[0] % 4 == 0 ||
4256 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4258 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4260 if (nir_src_is_const(instr
->src
[0])) {
4261 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4262 assert(load_offset
% type_sz(dest
.type
) == 0);
4263 /* For 16-bit types we add the module of the const_index[0]
4264 * offset to access to not 32-bit aligned element
4266 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4268 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4269 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4272 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4273 BRW_REGISTER_TYPE_UD
);
4275 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4276 * go past the end of the uniform. In order to keep the n'th
4277 * component from running past, we subtract off the size of all but
4278 * one component of the vector.
4280 assert(instr
->const_index
[1] >=
4281 instr
->num_components
* (int) type_sz(dest
.type
));
4282 unsigned read_size
= instr
->const_index
[1] -
4283 (instr
->num_components
- 1) * type_sz(dest
.type
);
4285 bool supports_64bit_indirects
=
4286 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4288 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4289 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4290 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4291 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4292 indirect
, brw_imm_ud(read_size
));
4295 const unsigned num_mov_indirects
=
4296 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4297 /* We read a little bit less per MOV INDIRECT, as they are now
4298 * 32-bits ones instead of 64-bit. Fix read_size then.
4300 const unsigned read_size_32bit
= read_size
-
4301 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4302 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4303 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4304 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4305 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4306 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4307 indirect
, brw_imm_ud(read_size_32bit
));
4315 case nir_intrinsic_load_ubo
: {
4317 if (nir_src_is_const(instr
->src
[0])) {
4318 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4319 nir_src_as_uint(instr
->src
[0]);
4320 surf_index
= brw_imm_ud(index
);
4322 /* The block index is not a constant. Evaluate the index expression
4323 * per-channel and add the base UBO index; we have to select a value
4324 * from any live channel.
4326 surf_index
= vgrf(glsl_type::uint_type
);
4327 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4328 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4329 surf_index
= bld
.emit_uniformize(surf_index
);
4332 if (!nir_src_is_const(instr
->src
[1])) {
4333 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4334 BRW_REGISTER_TYPE_UD
);
4336 for (int i
= 0; i
< instr
->num_components
; i
++)
4337 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4338 base_offset
, i
* type_sz(dest
.type
));
4340 prog_data
->has_ubo_pull
= true;
4342 /* Even if we are loading doubles, a pull constant load will load
4343 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4344 * need to load a full dvec4 we will have to emit 2 loads. This is
4345 * similar to demote_pull_constants(), except that in that case we
4346 * see individual accesses to each component of the vector and then
4347 * we let CSE deal with duplicate loads. Here we see a vector access
4348 * and we have to split it if necessary.
4350 const unsigned type_size
= type_sz(dest
.type
);
4351 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4353 /* See if we've selected this as a push constant candidate */
4354 if (nir_src_is_const(instr
->src
[0])) {
4355 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4356 const unsigned offset_256b
= load_offset
/ 32;
4359 for (int i
= 0; i
< 4; i
++) {
4360 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4361 if (range
->block
== ubo_block
&&
4362 offset_256b
>= range
->start
&&
4363 offset_256b
< range
->start
+ range
->length
) {
4365 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4366 push_reg
.offset
= load_offset
- 32 * range
->start
;
4371 if (push_reg
.file
!= BAD_FILE
) {
4372 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4373 bld
.MOV(offset(dest
, bld
, i
),
4374 byte_offset(push_reg
, i
* type_size
));
4380 prog_data
->has_ubo_pull
= true;
4382 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4383 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4384 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4386 for (unsigned c
= 0; c
< instr
->num_components
;) {
4387 const unsigned base
= load_offset
+ c
* type_size
;
4388 /* Number of usable components in the next block-aligned load. */
4389 const unsigned count
= MIN2(instr
->num_components
- c
,
4390 (block_sz
- base
% block_sz
) / type_size
);
4392 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4393 packed_consts
, surf_index
,
4394 brw_imm_ud(base
& ~(block_sz
- 1)));
4396 const fs_reg consts
=
4397 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4400 for (unsigned d
= 0; d
< count
; d
++)
4401 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4409 case nir_intrinsic_load_global
: {
4410 assert(devinfo
->gen
>= 8);
4412 if (nir_intrinsic_align(instr
) >= 4) {
4413 assert(nir_dest_bit_size(instr
->dest
) == 32);
4414 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4416 get_nir_src(instr
->src
[0]), /* Address */
4417 fs_reg(), /* No source data */
4418 brw_imm_ud(instr
->num_components
));
4419 inst
->size_written
= instr
->num_components
*
4420 inst
->dst
.component_size(inst
->exec_size
);
4422 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4423 assert(bit_size
<= 32);
4424 assert(nir_dest_num_components(instr
->dest
) == 1);
4425 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4426 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4428 get_nir_src(instr
->src
[0]), /* Address */
4429 fs_reg(), /* No source data */
4430 brw_imm_ud(bit_size
));
4431 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4436 case nir_intrinsic_store_global
:
4437 assert(devinfo
->gen
>= 8);
4439 if (stage
== MESA_SHADER_FRAGMENT
)
4440 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4442 if (nir_intrinsic_align(instr
) >= 4) {
4443 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4444 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4446 get_nir_src(instr
->src
[1]), /* Address */
4447 get_nir_src(instr
->src
[0]), /* Data */
4448 brw_imm_ud(instr
->num_components
));
4450 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4451 assert(bit_size
<= 32);
4452 assert(nir_src_num_components(instr
->src
[0]) == 1);
4453 brw_reg_type data_type
=
4454 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4455 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4456 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4457 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4459 get_nir_src(instr
->src
[1]), /* Address */
4461 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4465 case nir_intrinsic_global_atomic_add
:
4466 case nir_intrinsic_global_atomic_imin
:
4467 case nir_intrinsic_global_atomic_umin
:
4468 case nir_intrinsic_global_atomic_imax
:
4469 case nir_intrinsic_global_atomic_umax
:
4470 case nir_intrinsic_global_atomic_and
:
4471 case nir_intrinsic_global_atomic_or
:
4472 case nir_intrinsic_global_atomic_xor
:
4473 case nir_intrinsic_global_atomic_exchange
:
4474 case nir_intrinsic_global_atomic_comp_swap
:
4475 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4477 case nir_intrinsic_global_atomic_fmin
:
4478 case nir_intrinsic_global_atomic_fmax
:
4479 case nir_intrinsic_global_atomic_fcomp_swap
:
4480 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4483 case nir_intrinsic_load_ssbo
: {
4484 assert(devinfo
->gen
>= 7);
4486 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4487 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4488 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4489 get_nir_ssbo_intrinsic_index(bld
, instr
);
4490 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4491 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4493 /* Make dest unsigned because that's what the temporary will be */
4494 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4496 /* Read the vector */
4497 if (nir_intrinsic_align(instr
) >= 4) {
4498 assert(nir_dest_bit_size(instr
->dest
) == 32);
4499 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4501 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4502 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4503 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4505 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4506 assert(nir_dest_num_components(instr
->dest
) == 1);
4507 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4509 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4510 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4511 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4512 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4517 case nir_intrinsic_store_ssbo
: {
4518 assert(devinfo
->gen
>= 7);
4520 if (stage
== MESA_SHADER_FRAGMENT
)
4521 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4523 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4524 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4525 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4526 get_nir_ssbo_intrinsic_index(bld
, instr
);
4527 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4528 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4530 fs_reg data
= get_nir_src(instr
->src
[0]);
4531 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4533 assert(nir_intrinsic_write_mask(instr
) ==
4534 (1u << instr
->num_components
) - 1);
4535 if (nir_intrinsic_align(instr
) >= 4) {
4536 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4537 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4538 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4539 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4540 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4541 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4543 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4544 assert(nir_src_num_components(instr
->src
[0]) == 1);
4545 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4547 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4548 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4550 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4551 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4556 case nir_intrinsic_store_output
: {
4557 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4558 fs_reg src
= get_nir_src(instr
->src
[0]);
4560 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4561 unsigned num_components
= instr
->num_components
;
4562 unsigned first_component
= nir_intrinsic_component(instr
);
4564 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4565 4 * store_offset
), src
.type
);
4566 for (unsigned j
= 0; j
< num_components
; j
++) {
4567 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4568 offset(src
, bld
, j
));
4573 case nir_intrinsic_ssbo_atomic_add
:
4574 case nir_intrinsic_ssbo_atomic_imin
:
4575 case nir_intrinsic_ssbo_atomic_umin
:
4576 case nir_intrinsic_ssbo_atomic_imax
:
4577 case nir_intrinsic_ssbo_atomic_umax
:
4578 case nir_intrinsic_ssbo_atomic_and
:
4579 case nir_intrinsic_ssbo_atomic_or
:
4580 case nir_intrinsic_ssbo_atomic_xor
:
4581 case nir_intrinsic_ssbo_atomic_exchange
:
4582 case nir_intrinsic_ssbo_atomic_comp_swap
:
4583 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4585 case nir_intrinsic_ssbo_atomic_fmin
:
4586 case nir_intrinsic_ssbo_atomic_fmax
:
4587 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4588 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4591 case nir_intrinsic_get_buffer_size
: {
4592 assert(nir_src_num_components(instr
->src
[0]) == 1);
4593 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4594 nir_src_as_uint(instr
->src
[0]) : 0;
4596 /* A resinfo's sampler message is used to get the buffer size. The
4597 * SIMD8's writeback message consists of four registers and SIMD16's
4598 * writeback message consists of 8 destination registers (two per each
4599 * component). Because we are only interested on the first channel of
4600 * the first returned component, where resinfo returns the buffer size
4601 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4602 * the dispatch width.
4604 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4605 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4606 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4609 ubld
.MOV(src_payload
, brw_imm_d(0));
4611 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4612 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4613 src_payload
, brw_imm_ud(index
));
4614 inst
->header_size
= 0;
4616 inst
->size_written
= 4 * REG_SIZE
;
4618 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4620 * "Out-of-bounds checking is always performed at a DWord granularity. If
4621 * any part of the DWord is out-of-bounds then the whole DWord is
4622 * considered out-of-bounds."
4624 * This implies that types with size smaller than 4-bytes need to be
4625 * padded if they don't complete the last dword of the buffer. But as we
4626 * need to maintain the original size we need to reverse the padding
4627 * calculation to return the correct size to know the number of elements
4628 * of an unsized array. As we stored in the last two bits of the surface
4629 * size the needed padding for the buffer, we calculate here the
4630 * original buffer_size reversing the surface_size calculation:
4632 * surface_size = isl_align(buffer_size, 4) +
4633 * (isl_align(buffer_size) - buffer_size)
4635 * buffer_size = surface_size & ~3 - surface_size & 3
4638 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4639 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4640 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4642 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4643 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4644 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4646 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4650 case nir_intrinsic_load_subgroup_size
:
4651 /* This should only happen for fragment shaders because every other case
4652 * is lowered in NIR so we can optimize on it.
4654 assert(stage
== MESA_SHADER_FRAGMENT
);
4655 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4658 case nir_intrinsic_load_subgroup_invocation
:
4659 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4660 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4663 case nir_intrinsic_load_subgroup_eq_mask
:
4664 case nir_intrinsic_load_subgroup_ge_mask
:
4665 case nir_intrinsic_load_subgroup_gt_mask
:
4666 case nir_intrinsic_load_subgroup_le_mask
:
4667 case nir_intrinsic_load_subgroup_lt_mask
:
4668 unreachable("not reached");
4670 case nir_intrinsic_vote_any
: {
4671 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4673 /* The any/all predicates do not consider channel enables. To prevent
4674 * dead channels from affecting the result, we initialize the flag with
4675 * with the identity value for the logical operation.
4677 if (dispatch_width
== 32) {
4678 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4679 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4682 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4684 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4686 /* For some reason, the any/all predicates don't work properly with
4687 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4688 * doesn't read the correct subset of the flag register and you end up
4689 * getting garbage in the second half. Work around this by using a pair
4690 * of 1-wide MOVs and scattering the result.
4692 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4693 ubld
.MOV(res1
, brw_imm_d(0));
4694 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4695 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4696 BRW_PREDICATE_ALIGN1_ANY32H
,
4697 ubld
.MOV(res1
, brw_imm_d(-1)));
4699 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4702 case nir_intrinsic_vote_all
: {
4703 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4705 /* The any/all predicates do not consider channel enables. To prevent
4706 * dead channels from affecting the result, we initialize the flag with
4707 * with the identity value for the logical operation.
4709 if (dispatch_width
== 32) {
4710 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4711 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4712 brw_imm_ud(0xffffffff));
4714 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4716 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4718 /* For some reason, the any/all predicates don't work properly with
4719 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4720 * doesn't read the correct subset of the flag register and you end up
4721 * getting garbage in the second half. Work around this by using a pair
4722 * of 1-wide MOVs and scattering the result.
4724 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4725 ubld
.MOV(res1
, brw_imm_d(0));
4726 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4727 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4728 BRW_PREDICATE_ALIGN1_ALL32H
,
4729 ubld
.MOV(res1
, brw_imm_d(-1)));
4731 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4734 case nir_intrinsic_vote_feq
:
4735 case nir_intrinsic_vote_ieq
: {
4736 fs_reg value
= get_nir_src(instr
->src
[0]);
4737 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4738 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4739 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4740 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4743 fs_reg uniformized
= bld
.emit_uniformize(value
);
4744 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4746 /* The any/all predicates do not consider channel enables. To prevent
4747 * dead channels from affecting the result, we initialize the flag with
4748 * with the identity value for the logical operation.
4750 if (dispatch_width
== 32) {
4751 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4752 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4753 brw_imm_ud(0xffffffff));
4755 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4757 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4759 /* For some reason, the any/all predicates don't work properly with
4760 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4761 * doesn't read the correct subset of the flag register and you end up
4762 * getting garbage in the second half. Work around this by using a pair
4763 * of 1-wide MOVs and scattering the result.
4765 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4766 ubld
.MOV(res1
, brw_imm_d(0));
4767 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4768 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4769 BRW_PREDICATE_ALIGN1_ALL32H
,
4770 ubld
.MOV(res1
, brw_imm_d(-1)));
4772 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4776 case nir_intrinsic_ballot
: {
4777 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4778 BRW_REGISTER_TYPE_UD
);
4779 struct brw_reg flag
= brw_flag_reg(0, 0);
4780 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4781 * as f0.0. This is a problem for fragment programs as we currently use
4782 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4783 * programs yet so this isn't a problem. When we do, something will
4786 if (dispatch_width
== 32)
4787 flag
.type
= BRW_REGISTER_TYPE_UD
;
4789 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4790 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4792 if (instr
->dest
.ssa
.bit_size
> 32) {
4793 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4795 dest
.type
= BRW_REGISTER_TYPE_UD
;
4797 bld
.MOV(dest
, flag
);
4801 case nir_intrinsic_read_invocation
: {
4802 const fs_reg value
= get_nir_src(instr
->src
[0]);
4803 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4804 fs_reg tmp
= bld
.vgrf(value
.type
);
4806 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4807 bld
.emit_uniformize(invocation
));
4809 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4813 case nir_intrinsic_read_first_invocation
: {
4814 const fs_reg value
= get_nir_src(instr
->src
[0]);
4815 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4819 case nir_intrinsic_shuffle
: {
4820 const fs_reg value
= get_nir_src(instr
->src
[0]);
4821 const fs_reg index
= get_nir_src(instr
->src
[1]);
4823 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4827 case nir_intrinsic_first_invocation
: {
4828 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4829 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4830 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4831 fs_reg(component(tmp
, 0)));
4835 case nir_intrinsic_quad_broadcast
: {
4836 const fs_reg value
= get_nir_src(instr
->src
[0]);
4837 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4839 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4840 value
, brw_imm_ud(index
), brw_imm_ud(4));
4844 case nir_intrinsic_quad_swap_horizontal
: {
4845 const fs_reg value
= get_nir_src(instr
->src
[0]);
4846 const fs_reg tmp
= bld
.vgrf(value
.type
);
4847 if (devinfo
->gen
<= 7) {
4848 /* The hardware doesn't seem to support these crazy regions with
4849 * compressed instructions on gen7 and earlier so we fall back to
4850 * using quad swizzles. Fortunately, we don't support 64-bit
4851 * anything in Vulkan on gen7.
4853 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4854 const fs_builder ubld
= bld
.exec_all();
4855 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4856 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
4857 bld
.MOV(retype(dest
, value
.type
), tmp
);
4859 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4861 const fs_reg src_left
= horiz_stride(value
, 2);
4862 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4863 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4864 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4866 ubld
.MOV(tmp_left
, src_right
);
4867 ubld
.MOV(tmp_right
, src_left
);
4870 bld
.MOV(retype(dest
, value
.type
), tmp
);
4874 case nir_intrinsic_quad_swap_vertical
: {
4875 const fs_reg value
= get_nir_src(instr
->src
[0]);
4876 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4877 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4878 const fs_reg tmp
= bld
.vgrf(value
.type
);
4879 const fs_builder ubld
= bld
.exec_all();
4880 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4881 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4882 bld
.MOV(retype(dest
, value
.type
), tmp
);
4884 /* For larger data types, we have to either emit dispatch_width many
4885 * MOVs or else fall back to doing indirects.
4887 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4888 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4890 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4895 case nir_intrinsic_quad_swap_diagonal
: {
4896 const fs_reg value
= get_nir_src(instr
->src
[0]);
4897 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4898 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4899 const fs_reg tmp
= bld
.vgrf(value
.type
);
4900 const fs_builder ubld
= bld
.exec_all();
4901 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4902 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4903 bld
.MOV(retype(dest
, value
.type
), tmp
);
4905 /* For larger data types, we have to either emit dispatch_width many
4906 * MOVs or else fall back to doing indirects.
4908 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4909 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4911 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4916 case nir_intrinsic_reduce
: {
4917 fs_reg src
= get_nir_src(instr
->src
[0]);
4918 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4919 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4920 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4921 cluster_size
= dispatch_width
;
4923 /* Figure out the source type */
4924 src
.type
= brw_type_for_nir_type(devinfo
,
4925 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4926 nir_src_bit_size(instr
->src
[0])));
4928 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4929 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4930 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4932 /* There are a couple of register region issues that make things
4933 * complicated for 8-bit types:
4935 * 1. Only raw moves are allowed to write to a packed 8-bit
4937 * 2. If we use a strided destination, the efficient way to do scan
4938 * operations ends up using strides that are too big to encode in
4941 * To get around these issues, we just do all 8-bit scan operations in
4942 * 16 bits. It's actually fewer instructions than what we'd have to do
4943 * if we were trying to do it in native 8-bit types and the results are
4944 * the same once we truncate to 8 bits at the end.
4946 brw_reg_type scan_type
= src
.type
;
4947 if (type_sz(scan_type
) == 1)
4948 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
4950 /* Set up a register for all of our scratching around and initialize it
4951 * to reduction operation's identity value.
4953 fs_reg scan
= bld
.vgrf(scan_type
);
4954 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4956 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4958 dest
.type
= src
.type
;
4959 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4960 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4961 * the distance between clusters is at least 2 GRFs. In this case,
4962 * we don't need the weird striding of the CLUSTER_BROADCAST
4963 * instruction and can just do regular MOVs.
4965 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4966 const unsigned groups
=
4967 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4968 const unsigned group_size
= dispatch_width
/ groups
;
4969 for (unsigned i
= 0; i
< groups
; i
++) {
4970 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4971 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4972 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4973 component(scan
, comp
));
4976 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4977 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4982 case nir_intrinsic_inclusive_scan
:
4983 case nir_intrinsic_exclusive_scan
: {
4984 fs_reg src
= get_nir_src(instr
->src
[0]);
4985 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4987 /* Figure out the source type */
4988 src
.type
= brw_type_for_nir_type(devinfo
,
4989 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4990 nir_src_bit_size(instr
->src
[0])));
4992 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4993 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4994 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4996 /* There are a couple of register region issues that make things
4997 * complicated for 8-bit types:
4999 * 1. Only raw moves are allowed to write to a packed 8-bit
5001 * 2. If we use a strided destination, the efficient way to do scan
5002 * operations ends up using strides that are too big to encode in
5005 * To get around these issues, we just do all 8-bit scan operations in
5006 * 16 bits. It's actually fewer instructions than what we'd have to do
5007 * if we were trying to do it in native 8-bit types and the results are
5008 * the same once we truncate to 8 bits at the end.
5010 brw_reg_type scan_type
= src
.type
;
5011 if (type_sz(scan_type
) == 1)
5012 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5014 /* Set up a register for all of our scratching around and initialize it
5015 * to reduction operation's identity value.
5017 fs_reg scan
= bld
.vgrf(scan_type
);
5018 const fs_builder allbld
= bld
.exec_all();
5019 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5021 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5022 /* Exclusive scan is a bit harder because we have to do an annoying
5023 * shift of the contents before we can begin. To make things worse,
5024 * we can't do this with a normal stride; we have to use indirects.
5026 fs_reg shifted
= bld
.vgrf(scan_type
);
5027 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5028 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5030 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5031 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5035 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5037 bld
.MOV(retype(dest
, src
.type
), scan
);
5041 case nir_intrinsic_begin_invocation_interlock
: {
5042 const fs_builder ubld
= bld
.group(8, 0);
5043 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5045 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
5046 ->size_written
= 2 * REG_SIZE
;
5050 case nir_intrinsic_end_invocation_interlock
: {
5051 /* For endInvocationInterlock(), we need to insert a memory fence which
5052 * stalls in the shader until the memory transactions prior to that
5053 * fence are complete. This ensures that the shader does not end before
5054 * any writes from its critical section have landed. Otherwise, you can
5055 * end up with a case where the next invocation on that pixel properly
5056 * stalls for previous FS invocation on its pixel to complete but
5057 * doesn't actually wait for the dataport memory transactions from that
5058 * thread to land before submitting its own.
5060 const fs_builder ubld
= bld
.group(8, 0);
5061 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5062 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
5063 brw_vec8_grf(0, 0), brw_imm_ud(1), brw_imm_ud(0))
5064 ->size_written
= 2 * REG_SIZE
;
5069 unreachable("unknown intrinsic");
5074 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5075 int op
, nir_intrinsic_instr
*instr
)
5077 if (stage
== MESA_SHADER_FRAGMENT
)
5078 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5080 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5081 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5082 * appear to exist. However, if you look at Vol 2a, there are no message
5083 * descriptors provided for Qword atomic ops except for A64 messages.
5085 assert(nir_dest_bit_size(instr
->dest
) == 32);
5088 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5089 dest
= get_nir_dest(instr
->dest
);
5091 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5092 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5093 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5094 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5095 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5098 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5099 data
= get_nir_src(instr
->src
[2]);
5101 if (op
== BRW_AOP_CMPWR
) {
5102 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5103 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5104 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5107 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5109 /* Emit the actual atomic operation */
5111 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5112 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5116 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5117 int op
, nir_intrinsic_instr
*instr
)
5119 if (stage
== MESA_SHADER_FRAGMENT
)
5120 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5123 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5124 dest
= get_nir_dest(instr
->dest
);
5126 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5127 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5128 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5129 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5130 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5132 fs_reg data
= get_nir_src(instr
->src
[2]);
5133 if (op
== BRW_AOP_FCMPWR
) {
5134 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5135 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5136 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5139 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5141 /* Emit the actual atomic operation */
5143 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5144 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5148 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5149 int op
, nir_intrinsic_instr
*instr
)
5152 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5153 dest
= get_nir_dest(instr
->dest
);
5155 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5156 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5157 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5158 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5161 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5162 data
= get_nir_src(instr
->src
[1]);
5163 if (op
== BRW_AOP_CMPWR
) {
5164 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5165 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5166 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5169 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5171 /* Get the offset */
5172 if (nir_src_is_const(instr
->src
[0])) {
5173 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5174 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5176 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5177 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5178 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5179 brw_imm_ud(instr
->const_index
[0]));
5182 /* Emit the actual atomic operation operation */
5184 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5185 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5189 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5190 int op
, nir_intrinsic_instr
*instr
)
5193 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5194 dest
= get_nir_dest(instr
->dest
);
5196 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5197 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5198 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5199 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5201 fs_reg data
= get_nir_src(instr
->src
[1]);
5202 if (op
== BRW_AOP_FCMPWR
) {
5203 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5204 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5205 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5208 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5210 /* Get the offset */
5211 if (nir_src_is_const(instr
->src
[0])) {
5212 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5213 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5215 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5216 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5217 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5218 brw_imm_ud(instr
->const_index
[0]));
5221 /* Emit the actual atomic operation operation */
5223 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5224 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5228 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5229 int op
, nir_intrinsic_instr
*instr
)
5231 if (stage
== MESA_SHADER_FRAGMENT
)
5232 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5235 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5236 dest
= get_nir_dest(instr
->dest
);
5238 fs_reg addr
= get_nir_src(instr
->src
[0]);
5241 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5242 data
= get_nir_src(instr
->src
[1]);
5244 if (op
== BRW_AOP_CMPWR
) {
5245 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5246 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5247 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5251 if (nir_dest_bit_size(instr
->dest
) == 64) {
5252 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5253 dest
, addr
, data
, brw_imm_ud(op
));
5255 assert(nir_dest_bit_size(instr
->dest
) == 32);
5256 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5257 dest
, addr
, data
, brw_imm_ud(op
));
5262 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5263 int op
, nir_intrinsic_instr
*instr
)
5265 if (stage
== MESA_SHADER_FRAGMENT
)
5266 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5268 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5269 fs_reg dest
= get_nir_dest(instr
->dest
);
5271 fs_reg addr
= get_nir_src(instr
->src
[0]);
5273 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5274 fs_reg data
= get_nir_src(instr
->src
[1]);
5276 if (op
== BRW_AOP_FCMPWR
) {
5277 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5278 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5279 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5283 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5284 dest
, addr
, data
, brw_imm_ud(op
));
5288 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5290 unsigned texture
= instr
->texture_index
;
5291 unsigned sampler
= instr
->sampler_index
;
5293 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5295 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5296 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5298 int lod_components
= 0;
5300 /* The hardware requires a LOD for buffer textures */
5301 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5302 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5304 uint32_t header_bits
= 0;
5305 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5306 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5307 switch (instr
->src
[i
].src_type
) {
5308 case nir_tex_src_bias
:
5309 srcs
[TEX_LOGICAL_SRC_LOD
] =
5310 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5312 case nir_tex_src_comparator
:
5313 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5315 case nir_tex_src_coord
:
5316 switch (instr
->op
) {
5318 case nir_texop_txf_ms
:
5319 case nir_texop_txf_ms_mcs
:
5320 case nir_texop_samples_identical
:
5321 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5324 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5328 case nir_tex_src_ddx
:
5329 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5330 lod_components
= nir_tex_instr_src_size(instr
, i
);
5332 case nir_tex_src_ddy
:
5333 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5335 case nir_tex_src_lod
:
5336 switch (instr
->op
) {
5338 srcs
[TEX_LOGICAL_SRC_LOD
] =
5339 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5342 srcs
[TEX_LOGICAL_SRC_LOD
] =
5343 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5346 srcs
[TEX_LOGICAL_SRC_LOD
] =
5347 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5351 case nir_tex_src_min_lod
:
5352 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5353 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5355 case nir_tex_src_ms_index
:
5356 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5359 case nir_tex_src_offset
: {
5360 uint32_t offset_bits
= 0;
5361 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5362 header_bits
|= offset_bits
;
5364 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5365 retype(src
, BRW_REGISTER_TYPE_D
);
5370 case nir_tex_src_projector
:
5371 unreachable("should be lowered");
5373 case nir_tex_src_texture_offset
: {
5374 /* Emit code to evaluate the actual indexing expression */
5375 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5376 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5377 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5381 case nir_tex_src_sampler_offset
: {
5382 /* Emit code to evaluate the actual indexing expression */
5383 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5384 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5385 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5389 case nir_tex_src_texture_handle
:
5390 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5391 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5392 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5395 case nir_tex_src_sampler_handle
:
5396 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5397 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5398 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5401 case nir_tex_src_ms_mcs
:
5402 assert(instr
->op
== nir_texop_txf_ms
);
5403 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5406 case nir_tex_src_plane
: {
5407 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5408 const uint32_t texture_index
=
5409 instr
->texture_index
+
5410 stage_prog_data
->binding_table
.plane_start
[plane
] -
5411 stage_prog_data
->binding_table
.texture_start
;
5413 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5418 unreachable("unknown texture source");
5422 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5423 (instr
->op
== nir_texop_txf_ms
||
5424 instr
->op
== nir_texop_samples_identical
)) {
5425 if (devinfo
->gen
>= 7 &&
5426 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5427 srcs
[TEX_LOGICAL_SRC_MCS
] =
5428 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5429 instr
->coord_components
,
5430 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5431 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5433 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5437 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5438 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5441 switch (instr
->op
) {
5443 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5446 opcode
= FS_OPCODE_TXB_LOGICAL
;
5449 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5452 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5455 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5457 case nir_texop_txf_ms
:
5458 if ((key_tex
->msaa_16
& (1 << sampler
)))
5459 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5461 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5463 case nir_texop_txf_ms_mcs
:
5464 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5466 case nir_texop_query_levels
:
5468 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5471 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5474 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5475 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5477 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5479 case nir_texop_texture_samples
:
5480 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5482 case nir_texop_samples_identical
: {
5483 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5485 /* If mcs is an immediate value, it means there is no MCS. In that case
5486 * just return false.
5488 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5489 bld
.MOV(dst
, brw_imm_ud(0u));
5490 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5491 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5492 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5493 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5494 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5496 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5497 BRW_CONDITIONAL_EQ
);
5502 unreachable("unknown texture opcode");
5505 if (instr
->op
== nir_texop_tg4
) {
5506 if (instr
->component
== 1 &&
5507 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5508 /* gather4 sampler is broken for green channel on RG32F --
5509 * we must ask for blue instead.
5511 header_bits
|= 2 << 16;
5513 header_bits
|= instr
->component
<< 16;
5517 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5518 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5519 inst
->offset
= header_bits
;
5521 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5522 if (devinfo
->gen
>= 9 &&
5523 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5524 unsigned write_mask
= instr
->dest
.is_ssa
?
5525 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5526 (1 << dest_size
) - 1;
5527 assert(write_mask
!= 0); /* dead code should have been eliminated */
5528 inst
->size_written
= util_last_bit(write_mask
) *
5529 inst
->dst
.component_size(inst
->exec_size
);
5531 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5534 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5535 inst
->shadow_compare
= true;
5537 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5538 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5541 for (unsigned i
= 0; i
< dest_size
; i
++)
5542 nir_dest
[i
] = offset(dst
, bld
, i
);
5544 if (instr
->op
== nir_texop_query_levels
) {
5545 /* # levels is in .w */
5546 nir_dest
[0] = offset(dst
, bld
, 3);
5547 } else if (instr
->op
== nir_texop_txs
&&
5548 dest_size
>= 3 && devinfo
->gen
< 7) {
5549 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5550 fs_reg depth
= offset(dst
, bld
, 2);
5551 nir_dest
[2] = vgrf(glsl_type::int_type
);
5552 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5555 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5559 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5561 switch (instr
->type
) {
5562 case nir_jump_break
:
5563 bld
.emit(BRW_OPCODE_BREAK
);
5565 case nir_jump_continue
:
5566 bld
.emit(BRW_OPCODE_CONTINUE
);
5568 case nir_jump_return
:
5570 unreachable("unknown jump");
5575 * This helper takes a source register and un/shuffles it into the destination
5578 * If source type size is smaller than destination type size the operation
5579 * needed is a component shuffle. The opposite case would be an unshuffle. If
5580 * source/destination type size is equal a shuffle is done that would be
5581 * equivalent to a simple MOV.
5583 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5584 * components .xyz 16-bit vector on SIMD8 would be.
5586 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5587 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5589 * This helper will return the following 2 32-bit components with the 16-bit
5592 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5593 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5595 * For unshuffle, the example would be the opposite, a 64-bit type source
5596 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5599 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5600 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5601 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5602 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5604 * The returned result would be the following 4 32-bit components unshuffled:
5606 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5607 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5608 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5609 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5611 * - Source and destination register must not be overlapped.
5612 * - components units are measured in terms of the smaller type between
5613 * source and destination because we are un/shuffling the smaller
5614 * components from/into the bigger ones.
5615 * - first_component parameter allows skipping source components.
5618 shuffle_src_to_dst(const fs_builder
&bld
,
5621 uint32_t first_component
,
5622 uint32_t components
)
5624 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5625 assert(!regions_overlap(dst
,
5626 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5627 offset(src
, bld
, first_component
),
5628 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5629 for (unsigned i
= 0; i
< components
; i
++) {
5630 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5631 offset(src
, bld
, i
+ first_component
));
5633 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5634 /* Source is shuffled into destination */
5635 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5636 assert(!regions_overlap(dst
,
5637 type_sz(dst
.type
) * bld
.dispatch_width() *
5638 DIV_ROUND_UP(components
, size_ratio
),
5639 offset(src
, bld
, first_component
),
5640 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5642 brw_reg_type shuffle_type
=
5643 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5644 BRW_REGISTER_TYPE_D
);
5645 for (unsigned i
= 0; i
< components
; i
++) {
5646 fs_reg shuffle_component_i
=
5647 subscript(offset(dst
, bld
, i
/ size_ratio
),
5648 shuffle_type
, i
% size_ratio
);
5649 bld
.MOV(shuffle_component_i
,
5650 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5653 /* Source is unshuffled into destination */
5654 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5655 assert(!regions_overlap(dst
,
5656 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5657 offset(src
, bld
, first_component
/ size_ratio
),
5658 type_sz(src
.type
) * bld
.dispatch_width() *
5659 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5662 brw_reg_type shuffle_type
=
5663 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5664 BRW_REGISTER_TYPE_D
);
5665 for (unsigned i
= 0; i
< components
; i
++) {
5666 fs_reg shuffle_component_i
=
5667 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5668 shuffle_type
, (first_component
+ i
) % size_ratio
);
5669 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5670 shuffle_component_i
);
5676 shuffle_from_32bit_read(const fs_builder
&bld
,
5679 uint32_t first_component
,
5680 uint32_t components
)
5682 assert(type_sz(src
.type
) == 4);
5684 /* This function takes components in units of the destination type while
5685 * shuffle_src_to_dst takes components in units of the smallest type
5687 if (type_sz(dst
.type
) > 4) {
5688 assert(type_sz(dst
.type
) == 8);
5689 first_component
*= 2;
5693 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5697 setup_imm_df(const fs_builder
&bld
, double v
)
5699 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5700 assert(devinfo
->gen
>= 7);
5702 if (devinfo
->gen
>= 8)
5703 return brw_imm_df(v
);
5705 /* gen7.5 does not support DF immediates straighforward but the DIM
5706 * instruction allows to set the 64-bit immediate value.
5708 if (devinfo
->is_haswell
) {
5709 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5710 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5711 ubld
.DIM(dst
, brw_imm_df(v
));
5712 return component(dst
, 0);
5715 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5716 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5717 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5719 * Alternatively, we could also produce a normal VGRF (without stride 0)
5720 * by writing to all the channels in the VGRF, however, that would hit the
5721 * gen7 bug where we have to split writes that span more than 1 register
5722 * into instructions with a width of 4 (otherwise the write to the second
5723 * register written runs into an execmask hardware bug) which isn't very
5736 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5737 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5738 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5739 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5741 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5745 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5747 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5748 bld
.MOV(tmp
, brw_imm_w(v
));
5753 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5755 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5756 bld
.MOV(tmp
, brw_imm_uw(v
));