2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 nir_foreach_variable(var
, &nir
->outputs
) {
57 const unsigned vec4s
=
58 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
59 : type_size_vec4(var
->type
);
60 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
);
61 for (unsigned i
= 0; i
< vec4s
; i
++) {
62 if (outputs
[var
->data
.driver_location
+ i
].file
== BAD_FILE
)
63 outputs
[var
->data
.driver_location
+ i
] = offset(reg
, bld
, 4 * i
);
69 fs_visitor::nir_setup_uniforms()
71 if (dispatch_width
!= min_dispatch_width
)
74 uniforms
= nir
->num_uniforms
/ 4;
78 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
82 nir_foreach_instr(instr
, block
) {
83 if (instr
->type
!= nir_instr_type_intrinsic
)
86 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
87 switch (intrin
->intrinsic
) {
88 case nir_intrinsic_load_vertex_id
:
89 unreachable("should be lowered by lower_vertex_id().");
91 case nir_intrinsic_load_vertex_id_zero_base
:
92 case nir_intrinsic_load_base_vertex
:
93 case nir_intrinsic_load_instance_id
:
94 case nir_intrinsic_load_base_instance
:
95 case nir_intrinsic_load_draw_id
:
96 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
98 case nir_intrinsic_load_invocation_id
:
99 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
101 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
102 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
103 if (reg
->file
== BAD_FILE
) {
104 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
105 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
106 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
107 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
112 case nir_intrinsic_load_sample_pos
:
113 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
114 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
115 if (reg
->file
== BAD_FILE
)
116 *reg
= *v
->emit_samplepos_setup();
119 case nir_intrinsic_load_sample_id
:
120 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
121 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
122 if (reg
->file
== BAD_FILE
)
123 *reg
= *v
->emit_sampleid_setup();
126 case nir_intrinsic_load_sample_mask_in
:
127 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
128 assert(v
->devinfo
->gen
>= 7);
129 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
130 if (reg
->file
== BAD_FILE
)
131 *reg
= *v
->emit_samplemaskin_setup();
134 case nir_intrinsic_load_work_group_id
:
135 assert(v
->stage
== MESA_SHADER_COMPUTE
);
136 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
137 if (reg
->file
== BAD_FILE
)
138 *reg
= *v
->emit_cs_work_group_id_setup();
141 case nir_intrinsic_load_helper_invocation
:
142 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
143 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
144 if (reg
->file
== BAD_FILE
) {
145 const fs_builder abld
=
146 v
->bld
.annotate("gl_HelperInvocation", NULL
);
148 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
149 * pixel mask is in g1.7 of the thread payload.
151 * We move the per-channel pixel enable bit to the low bit of each
152 * channel by shifting the byte containing the pixel mask by the
153 * vector immediate 0x76543210UV.
155 * The region of <1,8,0> reads only 1 byte (the pixel masks for
156 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
157 * masks for 2 and 3) in SIMD16.
159 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
161 stride(byte_offset(retype(brw_vec1_grf(1, 0),
162 BRW_REGISTER_TYPE_UB
), 28),
164 brw_imm_v(0x76543210));
166 /* A set bit in the pixel mask means the channel is enabled, but
167 * that is the opposite of gl_HelperInvocation so we need to invert
170 * The negate source-modifier bit of logical instructions on Gen8+
171 * performs 1's complement negation, so we can use that instead of
174 fs_reg inverted
= negate(shifted
);
175 if (v
->devinfo
->gen
< 8) {
176 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
177 abld
.NOT(inverted
, shifted
);
180 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
181 * with 1 and negating.
183 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
184 abld
.AND(anded
, inverted
, brw_imm_uw(1));
186 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
187 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
201 fs_visitor::nir_emit_system_values()
203 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
204 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
205 nir_system_values
[i
] = fs_reg();
208 nir_foreach_function(function
, nir
) {
209 assert(strcmp(function
->name
, "main") == 0);
210 assert(function
->impl
);
211 nir_foreach_block(block
, function
->impl
) {
212 emit_system_values_block(block
, this);
218 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
220 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
221 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
222 nir_locals
[i
] = fs_reg();
225 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
226 unsigned array_elems
=
227 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
228 unsigned size
= array_elems
* reg
->num_components
;
229 const brw_reg_type reg_type
=
230 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
231 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
234 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
237 nir_emit_cf_list(&impl
->body
);
241 fs_visitor::nir_emit_cf_list(exec_list
*list
)
243 exec_list_validate(list
);
244 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
245 switch (node
->type
) {
247 nir_emit_if(nir_cf_node_as_if(node
));
250 case nir_cf_node_loop
:
251 nir_emit_loop(nir_cf_node_as_loop(node
));
254 case nir_cf_node_block
:
255 nir_emit_block(nir_cf_node_as_block(node
));
259 unreachable("Invalid CFG node block");
265 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
267 /* first, put the condition into f0 */
268 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
269 retype(get_nir_src(if_stmt
->condition
),
270 BRW_REGISTER_TYPE_D
));
271 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
273 bld
.IF(BRW_PREDICATE_NORMAL
);
275 nir_emit_cf_list(&if_stmt
->then_list
);
277 /* note: if the else is empty, dead CF elimination will remove it */
278 bld
.emit(BRW_OPCODE_ELSE
);
280 nir_emit_cf_list(&if_stmt
->else_list
);
282 bld
.emit(BRW_OPCODE_ENDIF
);
286 fs_visitor::nir_emit_loop(nir_loop
*loop
)
288 bld
.emit(BRW_OPCODE_DO
);
290 nir_emit_cf_list(&loop
->body
);
292 bld
.emit(BRW_OPCODE_WHILE
);
296 fs_visitor::nir_emit_block(nir_block
*block
)
298 nir_foreach_instr(instr
, block
) {
299 nir_emit_instr(instr
);
304 fs_visitor::nir_emit_instr(nir_instr
*instr
)
306 const fs_builder abld
= bld
.annotate(NULL
, instr
);
308 switch (instr
->type
) {
309 case nir_instr_type_alu
:
310 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
313 case nir_instr_type_intrinsic
:
315 case MESA_SHADER_VERTEX
:
316 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
318 case MESA_SHADER_TESS_CTRL
:
319 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
321 case MESA_SHADER_TESS_EVAL
:
322 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
324 case MESA_SHADER_GEOMETRY
:
325 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
327 case MESA_SHADER_FRAGMENT
:
328 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
330 case MESA_SHADER_COMPUTE
:
331 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
334 unreachable("unsupported shader stage");
338 case nir_instr_type_tex
:
339 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
342 case nir_instr_type_load_const
:
343 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
346 case nir_instr_type_ssa_undef
:
347 /* We create a new VGRF for undefs on every use (by handling
348 * them in get_nir_src()), rather than for each definition.
349 * This helps register coalescing eliminate MOVs from undef.
353 case nir_instr_type_jump
:
354 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
358 unreachable("unknown instruction type");
363 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
367 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
368 const fs_reg
&result
)
370 if (!instr
->src
[0].src
.is_ssa
||
371 !instr
->src
[0].src
.ssa
->parent_instr
)
374 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
377 nir_alu_instr
*src0
=
378 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
380 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
381 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
384 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
385 assert(element
!= NULL
);
387 /* Element type to extract.*/
388 const brw_reg_type type
= brw_int_type(
389 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
390 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
392 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
393 op0
.type
= brw_type_for_nir_type(devinfo
,
394 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
395 nir_src_bit_size(src0
->src
[0].src
)));
396 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
398 set_saturate(instr
->dest
.saturate
,
399 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
404 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
405 const fs_reg
&result
)
407 if (!instr
->src
[0].src
.is_ssa
||
408 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
411 nir_intrinsic_instr
*src0
=
412 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
414 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
417 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
418 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
421 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
422 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
425 fs_reg tmp
= vgrf(glsl_type::int_type
);
427 if (devinfo
->gen
>= 6) {
428 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
429 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
431 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
433 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
434 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
436 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
438 * This negation looks like it's safe in practice, because bits 0:4 will
439 * surely be TRIANGLES
442 if (value1
->f32
[0] == -1.0f
) {
446 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
447 g0
, brw_imm_uw(0x3f80));
449 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
450 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
452 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
454 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
455 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
457 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
459 * This negation looks like it's safe in practice, because bits 0:4 will
460 * surely be TRIANGLES
463 if (value1
->f32
[0] == -1.0f
) {
467 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
469 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
475 emit_find_msb_using_lzd(const fs_builder
&bld
,
476 const fs_reg
&result
,
484 /* LZD of an absolute value source almost always does the right
485 * thing. There are two problem values:
487 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
488 * 0. However, findMSB(int(0x80000000)) == 30.
490 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
491 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
493 * For a value of zero or negative one, -1 will be returned.
495 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
496 * findMSB(-(1<<x)) should return x-1.
498 * For all negative number cases, including 0x80000000 and
499 * 0xffffffff, the correct value is obtained from LZD if instead of
500 * negating the (already negative) value the logical-not is used. A
501 * conditonal logical-not can be achieved in two instructions.
503 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
505 bld
.ASR(temp
, src
, brw_imm_d(31));
506 bld
.XOR(temp
, temp
, src
);
509 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
510 retype(temp
, BRW_REGISTER_TYPE_UD
));
512 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
513 * from the LSB side. Subtract the result from 31 to convert the MSB
514 * count into an LSB count. If no bits are set, LZD will return 32.
515 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
517 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
518 inst
->src
[0].negate
= true;
522 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
524 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
527 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
528 result
.type
= brw_type_for_nir_type(devinfo
,
529 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
530 nir_dest_bit_size(instr
->dest
.dest
)));
533 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
534 op
[i
] = get_nir_src(instr
->src
[i
].src
);
535 op
[i
].type
= brw_type_for_nir_type(devinfo
,
536 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
537 nir_src_bit_size(instr
->src
[i
].src
)));
538 op
[i
].abs
= instr
->src
[i
].abs
;
539 op
[i
].negate
= instr
->src
[i
].negate
;
542 /* We get a bunch of mov's out of the from_ssa pass and they may still
543 * be vectorized. We'll handle them as a special-case. We'll also
544 * handle vecN here because it's basically the same thing.
552 fs_reg temp
= result
;
553 bool need_extra_copy
= false;
554 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
555 if (!instr
->src
[i
].src
.is_ssa
&&
556 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
557 need_extra_copy
= true;
558 temp
= bld
.vgrf(result
.type
, 4);
563 for (unsigned i
= 0; i
< 4; i
++) {
564 if (!(instr
->dest
.write_mask
& (1 << i
)))
567 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
568 inst
= bld
.MOV(offset(temp
, bld
, i
),
569 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
571 inst
= bld
.MOV(offset(temp
, bld
, i
),
572 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
574 inst
->saturate
= instr
->dest
.saturate
;
577 /* In this case the source and destination registers were the same,
578 * so we need to insert an extra set of moves in order to deal with
581 if (need_extra_copy
) {
582 for (unsigned i
= 0; i
< 4; i
++) {
583 if (!(instr
->dest
.write_mask
& (1 << i
)))
586 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
595 /* At this point, we have dealt with any instruction that operates on
596 * more than a single channel. Therefore, we can just adjust the source
597 * and destination registers for that channel and emit the instruction.
599 unsigned channel
= 0;
600 if (nir_op_infos
[instr
->op
].output_size
== 0) {
601 /* Since NIR is doing the scalarizing for us, we should only ever see
602 * vectorized operations with a single channel.
604 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
605 channel
= ffs(instr
->dest
.write_mask
) - 1;
607 result
= offset(result
, bld
, channel
);
610 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
611 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
612 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
618 if (optimize_extract_to_float(instr
, result
))
620 inst
= bld
.MOV(result
, op
[0]);
621 inst
->saturate
= instr
->dest
.saturate
;
627 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
629 * "When source or destination is 64b (...), regioning in Align1
630 * must follow these rules:
632 * 1. Source and destination horizontal stride must be aligned to
636 * This means that 32-bit to 64-bit conversions need to have the 32-bit
637 * data elements aligned to 64-bit. This restriction does not apply to
640 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
641 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
642 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
643 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
644 tmp
= subscript(tmp
, op
[0].type
, 0);
645 inst
= bld
.MOV(tmp
, op
[0]);
646 inst
= bld
.MOV(result
, tmp
);
647 inst
->saturate
= instr
->dest
.saturate
;
660 inst
= bld
.MOV(result
, op
[0]);
661 inst
->saturate
= instr
->dest
.saturate
;
666 /* Straightforward since the source can be assumed to be
669 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
670 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
672 } else if (type_sz(op
[0].type
) < 8) {
673 /* AND(val, 0x80000000) gives the sign bit.
675 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
678 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
680 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
681 op
[0].type
= BRW_REGISTER_TYPE_UD
;
682 result
.type
= BRW_REGISTER_TYPE_UD
;
683 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
685 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
686 inst
->predicate
= BRW_PREDICATE_NORMAL
;
687 if (instr
->dest
.saturate
) {
688 inst
= bld
.MOV(result
, result
);
689 inst
->saturate
= true;
692 /* For doubles we do the same but we need to consider:
694 * - 2-src instructions can't operate with 64-bit immediates
695 * - The sign is encoded in the high 32-bit of each DF
696 * - CMP with DF requires special handling in SIMD16
697 * - We need to produce a DF result.
700 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
701 * a register and compare with that.
703 fs_reg tmp
= vgrf(glsl_type::double_type
);
704 bld
.MOV(tmp
, setup_imm_df(bld
, 0.0));
706 /* A direct DF CMP using the flag register (null dst) won't work in
707 * SIMD16 because the CMP will be split in two by lower_simd_width,
708 * resulting in two CMP instructions with the same dst (NULL),
709 * leading to dead code elimination of the first one. In SIMD8,
710 * however, there is no need to split the CMP and we can save some
713 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
714 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
716 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
717 * so we store the result of the comparison in a vgrf instead and
718 * then we generate a UD comparison from that that won't have to
719 * be split by lower_simd_width. This is what NIR does to handle
720 * double comparisons in the general case.
722 if (bld
.dispatch_width() == 16 ) {
723 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
724 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
725 bld
.CMP(bld
.null_reg_ud(),
726 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
729 /* Get the high 32-bit of each double component where the sign is */
730 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
731 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
733 /* Get the sign bit */
734 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
736 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
737 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
738 inst
->predicate
= BRW_PREDICATE_NORMAL
;
740 /* Convert from 32-bit float to 64-bit double */
741 result
.type
= BRW_REGISTER_TYPE_DF
;
742 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
744 if (instr
->dest
.saturate
) {
745 inst
= bld
.MOV(result
, result
);
746 inst
->saturate
= true;
753 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
754 * -> non-negative val generates 0x00000000.
755 * Predicated OR sets 1 if val is positive.
757 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
758 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
759 bld
.ASR(result
, op
[0], brw_imm_d(31));
760 inst
= bld
.OR(result
, result
, brw_imm_d(1));
761 inst
->predicate
= BRW_PREDICATE_NORMAL
;
765 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
766 inst
->saturate
= instr
->dest
.saturate
;
770 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
771 inst
->saturate
= instr
->dest
.saturate
;
775 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
776 inst
->saturate
= instr
->dest
.saturate
;
780 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
781 inst
->saturate
= instr
->dest
.saturate
;
785 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
786 inst
->saturate
= instr
->dest
.saturate
;
790 if (fs_key
->high_quality_derivatives
) {
791 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
793 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
795 inst
->saturate
= instr
->dest
.saturate
;
797 case nir_op_fddx_fine
:
798 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
799 inst
->saturate
= instr
->dest
.saturate
;
801 case nir_op_fddx_coarse
:
802 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
803 inst
->saturate
= instr
->dest
.saturate
;
806 if (fs_key
->high_quality_derivatives
) {
807 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
809 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
811 inst
->saturate
= instr
->dest
.saturate
;
813 case nir_op_fddy_fine
:
814 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
815 inst
->saturate
= instr
->dest
.saturate
;
817 case nir_op_fddy_coarse
:
818 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
819 inst
->saturate
= instr
->dest
.saturate
;
824 inst
= bld
.ADD(result
, op
[0], op
[1]);
825 inst
->saturate
= instr
->dest
.saturate
;
829 inst
= bld
.MUL(result
, op
[0], op
[1]);
830 inst
->saturate
= instr
->dest
.saturate
;
834 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
835 bld
.MUL(result
, op
[0], op
[1]);
838 case nir_op_imul_high
:
839 case nir_op_umul_high
:
840 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
841 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
846 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
847 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
850 case nir_op_uadd_carry
:
851 unreachable("Should have been lowered by carry_to_arith().");
853 case nir_op_usub_borrow
:
854 unreachable("Should have been lowered by borrow_to_arith().");
858 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
859 * appears that our hardware just does the right thing for signed
862 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
863 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
867 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
868 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
870 /* Math instructions don't support conditional mod */
871 inst
= bld
.MOV(bld
.null_reg_d(), result
);
872 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
874 /* Now, we need to determine if signs of the sources are different.
875 * When we XOR the sources, the top bit is 0 if they are the same and 1
876 * if they are different. We can then use a conditional modifier to
877 * turn that into a predicate. This leads us to an XOR.l instruction.
879 * Technically, according to the PRM, you're not allowed to use .l on a
880 * XOR instruction. However, emperical experiments and Curro's reading
881 * of the simulator source both indicate that it's safe.
883 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
884 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
885 inst
->predicate
= BRW_PREDICATE_NORMAL
;
886 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
888 /* If the result of the initial remainder operation is non-zero and the
889 * two sources have different signs, add in a copy of op[1] to get the
890 * final integer modulus value.
892 inst
= bld
.ADD(result
, result
, op
[1]);
893 inst
->predicate
= BRW_PREDICATE_NORMAL
;
901 fs_reg dest
= result
;
902 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
903 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
905 brw_conditional_mod cond
;
908 cond
= BRW_CONDITIONAL_L
;
911 cond
= BRW_CONDITIONAL_GE
;
914 cond
= BRW_CONDITIONAL_Z
;
917 cond
= BRW_CONDITIONAL_NZ
;
920 unreachable("bad opcode");
922 bld
.CMP(dest
, op
[0], op
[1], cond
);
923 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
924 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
935 fs_reg dest
= result
;
936 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
937 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
940 brw_conditional_mod cond
;
944 cond
= BRW_CONDITIONAL_L
;
948 cond
= BRW_CONDITIONAL_GE
;
951 cond
= BRW_CONDITIONAL_Z
;
954 cond
= BRW_CONDITIONAL_NZ
;
957 unreachable("bad opcode");
959 bld
.CMP(dest
, op
[0], op
[1], cond
);
960 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
961 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
967 if (devinfo
->gen
>= 8) {
968 op
[0] = resolve_source_modifiers(op
[0]);
970 bld
.NOT(result
, op
[0]);
973 if (devinfo
->gen
>= 8) {
974 op
[0] = resolve_source_modifiers(op
[0]);
975 op
[1] = resolve_source_modifiers(op
[1]);
977 bld
.XOR(result
, op
[0], op
[1]);
980 if (devinfo
->gen
>= 8) {
981 op
[0] = resolve_source_modifiers(op
[0]);
982 op
[1] = resolve_source_modifiers(op
[1]);
984 bld
.OR(result
, op
[0], op
[1]);
987 if (devinfo
->gen
>= 8) {
988 op
[0] = resolve_source_modifiers(op
[0]);
989 op
[1] = resolve_source_modifiers(op
[1]);
991 bld
.AND(result
, op
[0], op
[1]);
997 case nir_op_ball_fequal2
:
998 case nir_op_ball_iequal2
:
999 case nir_op_ball_fequal3
:
1000 case nir_op_ball_iequal3
:
1001 case nir_op_ball_fequal4
:
1002 case nir_op_ball_iequal4
:
1003 case nir_op_bany_fnequal2
:
1004 case nir_op_bany_inequal2
:
1005 case nir_op_bany_fnequal3
:
1006 case nir_op_bany_inequal3
:
1007 case nir_op_bany_fnequal4
:
1008 case nir_op_bany_inequal4
:
1009 unreachable("Lowered by nir_lower_alu_reductions");
1011 case nir_op_fnoise1_1
:
1012 case nir_op_fnoise1_2
:
1013 case nir_op_fnoise1_3
:
1014 case nir_op_fnoise1_4
:
1015 case nir_op_fnoise2_1
:
1016 case nir_op_fnoise2_2
:
1017 case nir_op_fnoise2_3
:
1018 case nir_op_fnoise2_4
:
1019 case nir_op_fnoise3_1
:
1020 case nir_op_fnoise3_2
:
1021 case nir_op_fnoise3_3
:
1022 case nir_op_fnoise3_4
:
1023 case nir_op_fnoise4_1
:
1024 case nir_op_fnoise4_2
:
1025 case nir_op_fnoise4_3
:
1026 case nir_op_fnoise4_4
:
1027 unreachable("not reached: should be handled by lower_noise");
1030 unreachable("not reached: should be handled by ldexp_to_arith()");
1033 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1034 inst
->saturate
= instr
->dest
.saturate
;
1038 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1039 inst
->saturate
= instr
->dest
.saturate
;
1044 bld
.MOV(result
, negate(op
[0]));
1049 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1050 /* two-argument instructions can't take 64-bit immediates */
1054 if (instr
->op
== nir_op_f2b
) {
1055 zero
= vgrf(glsl_type::double_type
);
1056 tmp
= vgrf(glsl_type::double_type
);
1058 zero
= vgrf(glsl_type::int64_t_type
);
1059 tmp
= vgrf(glsl_type::int64_t_type
);
1062 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1063 /* A SIMD16 execution needs to be split in two instructions, so use
1064 * a vgrf instead of the flag register as dst so instruction splitting
1067 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1068 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1070 if (instr
->op
== nir_op_f2b
) {
1071 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1073 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1079 inst
= bld
.RNDZ(result
, op
[0]);
1080 inst
->saturate
= instr
->dest
.saturate
;
1083 case nir_op_fceil
: {
1084 op
[0].negate
= !op
[0].negate
;
1085 fs_reg temp
= vgrf(glsl_type::float_type
);
1086 bld
.RNDD(temp
, op
[0]);
1088 inst
= bld
.MOV(result
, temp
);
1089 inst
->saturate
= instr
->dest
.saturate
;
1093 inst
= bld
.RNDD(result
, op
[0]);
1094 inst
->saturate
= instr
->dest
.saturate
;
1097 inst
= bld
.FRC(result
, op
[0]);
1098 inst
->saturate
= instr
->dest
.saturate
;
1100 case nir_op_fround_even
:
1101 inst
= bld
.RNDE(result
, op
[0]);
1102 inst
->saturate
= instr
->dest
.saturate
;
1105 case nir_op_fquantize2f16
: {
1106 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1107 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1108 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1110 /* The destination stride must be at least as big as the source stride. */
1111 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1114 /* Check for denormal */
1115 fs_reg abs_src0
= op
[0];
1116 abs_src0
.abs
= true;
1117 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1119 /* Get the appropriately signed zero */
1120 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1121 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1122 brw_imm_ud(0x80000000));
1123 /* Do the actual F32 -> F16 -> F32 conversion */
1124 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1125 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1126 /* Select that or zero based on normal status */
1127 inst
= bld
.SEL(result
, zero
, tmp32
);
1128 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1129 inst
->saturate
= instr
->dest
.saturate
;
1136 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1137 inst
->saturate
= instr
->dest
.saturate
;
1143 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1144 inst
->saturate
= instr
->dest
.saturate
;
1147 case nir_op_pack_snorm_2x16
:
1148 case nir_op_pack_snorm_4x8
:
1149 case nir_op_pack_unorm_2x16
:
1150 case nir_op_pack_unorm_4x8
:
1151 case nir_op_unpack_snorm_2x16
:
1152 case nir_op_unpack_snorm_4x8
:
1153 case nir_op_unpack_unorm_2x16
:
1154 case nir_op_unpack_unorm_4x8
:
1155 case nir_op_unpack_half_2x16
:
1156 case nir_op_pack_half_2x16
:
1157 unreachable("not reached: should be handled by lower_packing_builtins");
1159 case nir_op_unpack_half_2x16_split_x
:
1160 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1161 inst
->saturate
= instr
->dest
.saturate
;
1163 case nir_op_unpack_half_2x16_split_y
:
1164 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1165 inst
->saturate
= instr
->dest
.saturate
;
1168 case nir_op_pack_64_2x32_split
:
1169 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1172 case nir_op_unpack_64_2x32_split_x
:
1173 case nir_op_unpack_64_2x32_split_y
: {
1174 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1175 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1177 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1182 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1183 inst
->saturate
= instr
->dest
.saturate
;
1186 case nir_op_bitfield_reverse
:
1187 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1188 bld
.BFREV(result
, op
[0]);
1191 case nir_op_bit_count
:
1192 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1193 bld
.CBIT(result
, op
[0]);
1196 case nir_op_ufind_msb
: {
1197 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1198 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1202 case nir_op_ifind_msb
: {
1203 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1205 if (devinfo
->gen
< 7) {
1206 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1208 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1210 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1211 * count from the LSB side. If FBH didn't return an error
1212 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1213 * count into an LSB count.
1215 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1217 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1218 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1219 inst
->src
[0].negate
= true;
1224 case nir_op_find_lsb
:
1225 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1227 if (devinfo
->gen
< 7) {
1228 fs_reg temp
= vgrf(glsl_type::int_type
);
1230 /* (x & -x) generates a value that consists of only the LSB of x.
1231 * For all powers of 2, findMSB(y) == findLSB(y).
1233 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1234 fs_reg negated_src
= src
;
1236 /* One must be negated, and the other must be non-negated. It
1237 * doesn't matter which is which.
1239 negated_src
.negate
= true;
1242 bld
.AND(temp
, src
, negated_src
);
1243 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1245 bld
.FBL(result
, op
[0]);
1249 case nir_op_ubitfield_extract
:
1250 case nir_op_ibitfield_extract
:
1251 unreachable("should have been lowered");
1254 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1255 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1258 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1259 bld
.BFI1(result
, op
[0], op
[1]);
1262 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1263 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1266 case nir_op_bitfield_insert
:
1267 unreachable("not reached: should have been lowered");
1270 bld
.SHL(result
, op
[0], op
[1]);
1273 bld
.ASR(result
, op
[0], op
[1]);
1276 bld
.SHR(result
, op
[0], op
[1]);
1279 case nir_op_pack_half_2x16_split
:
1280 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1284 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1285 inst
->saturate
= instr
->dest
.saturate
;
1289 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1290 inst
->saturate
= instr
->dest
.saturate
;
1294 if (optimize_frontfacing_ternary(instr
, result
))
1297 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1298 inst
= bld
.SEL(result
, op
[1], op
[2]);
1299 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1302 case nir_op_extract_u8
:
1303 case nir_op_extract_i8
: {
1304 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1305 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1306 assert(byte
!= NULL
);
1307 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1311 case nir_op_extract_u16
:
1312 case nir_op_extract_i16
: {
1313 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1314 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1315 assert(word
!= NULL
);
1316 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1321 unreachable("unhandled instruction");
1324 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1325 * to sign extend the low bit to 0/~0
1327 if (devinfo
->gen
<= 5 &&
1328 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1329 fs_reg masked
= vgrf(glsl_type::int_type
);
1330 bld
.AND(masked
, result
, brw_imm_d(1));
1331 masked
.negate
= true;
1332 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1337 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1338 nir_load_const_instr
*instr
)
1340 const brw_reg_type reg_type
=
1341 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1342 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1344 switch (instr
->def
.bit_size
) {
1346 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1347 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1351 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1352 bld
.MOV(offset(reg
, bld
, i
),
1353 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1357 unreachable("Invalid bit size");
1360 nir_ssa_values
[instr
->def
.index
] = reg
;
1364 fs_visitor::get_nir_src(const nir_src
&src
)
1368 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1369 const brw_reg_type reg_type
= src
.ssa
->bit_size
== 32 ?
1370 BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1371 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1373 reg
= nir_ssa_values
[src
.ssa
->index
];
1376 /* We don't handle indirects on locals */
1377 assert(src
.reg
.indirect
== NULL
);
1378 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1379 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1382 /* to avoid floating-point denorm flushing problems, set the type by
1383 * default to D - instructions that need floating point semantics will set
1384 * this to F if they need to
1386 return retype(reg
, BRW_REGISTER_TYPE_D
);
1390 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1393 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1395 nir_const_value
*val
= nir_src_as_const_value(src
);
1396 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1400 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1403 const brw_reg_type reg_type
=
1404 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1405 nir_ssa_values
[dest
.ssa
.index
] =
1406 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1407 return nir_ssa_values
[dest
.ssa
.index
];
1409 /* We don't handle indirects on locals */
1410 assert(dest
.reg
.indirect
== NULL
);
1411 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1412 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1417 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1419 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1420 BRW_REGISTER_TYPE_UD
);
1422 unsigned indirect_max
= 0;
1424 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1425 tail
= tail
->child
) {
1426 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1427 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1428 const unsigned size
= glsl_get_length(tail
->type
);
1429 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1430 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1431 image
= offset(image
, bld
, base
* element_size
);
1433 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1434 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1436 /* Accessing an invalid surface index with the dataport can result
1437 * in a hang. According to the spec "if the index used to
1438 * select an individual element is negative or greater than or
1439 * equal to the size of the array, the results of the operation
1440 * are undefined but may not lead to termination" -- which is one
1441 * of the possible outcomes of the hang. Clamp the index to
1442 * prevent access outside of the array bounds.
1444 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1445 BRW_REGISTER_TYPE_UD
),
1446 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1448 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1450 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1451 if (indirect
.file
== BAD_FILE
) {
1454 bld
.ADD(indirect
, indirect
, tmp
);
1459 if (indirect
.file
== BAD_FILE
) {
1462 /* Emit a pile of MOVs to load the uniform into a temporary. The
1463 * dead-code elimination pass will get rid of what we don't use.
1465 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1466 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1467 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1468 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1469 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1476 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1479 for (unsigned i
= 0; i
< 4; i
++) {
1480 if (!((wr_mask
>> i
) & 1))
1483 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1484 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1485 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1486 if (new_inst
->src
[j
].file
== VGRF
)
1487 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1494 * Get the matching channel register datatype for an image intrinsic of the
1495 * specified GLSL image type.
1498 get_image_base_type(const glsl_type
*type
)
1500 switch ((glsl_base_type
)type
->sampled_type
) {
1501 case GLSL_TYPE_UINT
:
1502 return BRW_REGISTER_TYPE_UD
;
1504 return BRW_REGISTER_TYPE_D
;
1505 case GLSL_TYPE_FLOAT
:
1506 return BRW_REGISTER_TYPE_F
;
1508 unreachable("Not reached.");
1513 * Get the appropriate atomic op for an image atomic intrinsic.
1516 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1519 case nir_intrinsic_image_atomic_add
:
1521 case nir_intrinsic_image_atomic_min
:
1522 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1523 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1524 case nir_intrinsic_image_atomic_max
:
1525 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1526 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1527 case nir_intrinsic_image_atomic_and
:
1529 case nir_intrinsic_image_atomic_or
:
1531 case nir_intrinsic_image_atomic_xor
:
1533 case nir_intrinsic_image_atomic_exchange
:
1535 case nir_intrinsic_image_atomic_comp_swap
:
1536 return BRW_AOP_CMPWR
;
1538 unreachable("Not reachable.");
1543 emit_pixel_interpolater_send(const fs_builder
&bld
,
1548 glsl_interp_mode interpolation
)
1550 struct brw_wm_prog_data
*wm_prog_data
=
1551 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1556 if (src
.file
== BAD_FILE
) {
1558 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1562 mlen
= 2 * bld
.dispatch_width() / 8;
1565 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1567 /* 2 floats per slot returned */
1568 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1569 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1571 wm_prog_data
->pulls_bary
= true;
1577 * Computes 1 << x, given a D/UD register containing some value x.
1580 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1582 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1584 fs_reg result
= bld
.vgrf(x
.type
, 1);
1585 fs_reg one
= bld
.vgrf(x
.type
, 1);
1587 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1588 bld
.SHL(result
, one
, x
);
1593 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1595 assert(stage
== MESA_SHADER_GEOMETRY
);
1597 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1599 if (gs_compile
->control_data_header_size_bits
== 0)
1602 /* We can only do EndPrimitive() functionality when the control data
1603 * consists of cut bits. Fortunately, the only time it isn't is when the
1604 * output type is points, in which case EndPrimitive() is a no-op.
1606 if (gs_prog_data
->control_data_format
!=
1607 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1611 /* Cut bits use one bit per vertex. */
1612 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1614 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1615 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1617 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1618 * vertex n, 0 otherwise. So all we need to do here is mark bit
1619 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1620 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1621 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1623 * Note that if EndPrimitive() is called before emitting any vertices, this
1624 * will cause us to set bit 31 of the control_data_bits register to 1.
1625 * That's fine because:
1627 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1628 * output, so the hardware will ignore cut bit 31.
1630 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1631 * last vertex, so setting cut bit 31 has no effect (since the primitive
1632 * is automatically ended when the GS terminates).
1634 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1635 * control_data_bits register to 0 when the first vertex is emitted.
1638 const fs_builder abld
= bld
.annotate("end primitive");
1640 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1641 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1642 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1643 fs_reg mask
= intexp2(abld
, prev_count
);
1644 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1645 * attention to the lower 5 bits of its second source argument, so on this
1646 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1647 * ((vertex_count - 1) % 32).
1649 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1653 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1655 assert(stage
== MESA_SHADER_GEOMETRY
);
1656 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1658 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1660 const fs_builder abld
= bld
.annotate("emit control data bits");
1661 const fs_builder fwa_bld
= bld
.exec_all();
1663 /* We use a single UD register to accumulate control data bits (32 bits
1664 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1667 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1668 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1669 * use the Channel Mask phase to enable/disable which DWord within that
1670 * group to write. (Remember, different SIMD8 channels may have emitted
1671 * different numbers of vertices, so we may need per-slot offsets.)
1673 * Channel masking presents an annoying problem: we may have to replicate
1674 * the data up to 4 times:
1676 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1678 * To avoid penalizing shaders that emit a small number of vertices, we
1679 * can avoid these sometimes: if the size of the control data header is
1680 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1681 * land in the same 128-bit group, so we can skip per-slot offsets.
1683 * Similarly, if the control data header is <= 32 bits, there is only one
1684 * DWord, so we can skip channel masks.
1686 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1688 fs_reg channel_mask
, per_slot_offset
;
1690 if (gs_compile
->control_data_header_size_bits
> 32) {
1691 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1692 channel_mask
= vgrf(glsl_type::uint_type
);
1695 if (gs_compile
->control_data_header_size_bits
> 128) {
1696 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1697 per_slot_offset
= vgrf(glsl_type::uint_type
);
1700 /* Figure out which DWord we're trying to write to using the formula:
1702 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1704 * Since bits_per_vertex is a power of two, and is known at compile
1705 * time, this can be optimized to:
1707 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1709 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1710 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1711 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1712 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1713 unsigned log2_bits_per_vertex
=
1714 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1715 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1717 if (per_slot_offset
.file
!= BAD_FILE
) {
1718 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1719 * the appropriate OWord within the control data header.
1721 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1724 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1725 * write to the appropriate DWORD within the OWORD.
1727 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1728 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1729 channel_mask
= intexp2(fwa_bld
, channel
);
1730 /* Then the channel masks need to be in bits 23:16. */
1731 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1734 /* Store the control data bits in the message payload and send it. */
1736 if (channel_mask
.file
!= BAD_FILE
)
1737 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1738 if (per_slot_offset
.file
!= BAD_FILE
)
1741 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1742 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1744 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1745 if (per_slot_offset
.file
!= BAD_FILE
)
1746 sources
[i
++] = per_slot_offset
;
1747 if (channel_mask
.file
!= BAD_FILE
)
1748 sources
[i
++] = channel_mask
;
1750 sources
[i
++] = this->control_data_bits
;
1753 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1754 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1756 /* We need to increment Global Offset by 256-bits to make room for
1757 * Broadwell's extra "Vertex Count" payload at the beginning of the
1758 * URB entry. Since this is an OWord message, Global Offset is counted
1759 * in 128-bit units, so we must set it to 2.
1761 if (gs_prog_data
->static_vertex_count
== -1)
1766 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1769 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1771 /* Note: we are calling this *before* increasing vertex_count, so
1772 * this->vertex_count == vertex_count - 1 in the formula above.
1775 /* Stream mode uses 2 bits per vertex */
1776 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1778 /* Must be a valid stream */
1779 assert(stream_id
< MAX_VERTEX_STREAMS
);
1781 /* Control data bits are initialized to 0 so we don't have to set any
1782 * bits when sending vertices to stream 0.
1787 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1789 /* reg::sid = stream_id */
1790 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1791 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1793 /* reg:shift_count = 2 * (vertex_count - 1) */
1794 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1795 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1797 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1798 * attention to the lower 5 bits of its second source argument, so on this
1799 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1800 * stream_id << ((2 * (vertex_count - 1)) % 32).
1802 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1803 abld
.SHL(mask
, sid
, shift_count
);
1804 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1808 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1811 assert(stage
== MESA_SHADER_GEOMETRY
);
1813 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1815 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1816 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1818 /* Haswell and later hardware ignores the "Render Stream Select" bits
1819 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1820 * and instead sends all primitives down the pipeline for rasterization.
1821 * If the SOL stage is enabled, "Render Stream Select" is honored and
1822 * primitives bound to non-zero streams are discarded after stream output.
1824 * Since the only purpose of primives sent to non-zero streams is to
1825 * be recorded by transform feedback, we can simply discard all geometry
1826 * bound to these streams when transform feedback is disabled.
1828 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1831 /* If we're outputting 32 control data bits or less, then we can wait
1832 * until the shader is over to output them all. Otherwise we need to
1833 * output them as we go. Now is the time to do it, since we're about to
1834 * output the vertex_count'th vertex, so it's guaranteed that the
1835 * control data bits associated with the (vertex_count - 1)th vertex are
1838 if (gs_compile
->control_data_header_size_bits
> 32) {
1839 const fs_builder abld
=
1840 bld
.annotate("emit vertex: emit control data bits");
1842 /* Only emit control data bits if we've finished accumulating a batch
1843 * of 32 bits. This is the case when:
1845 * (vertex_count * bits_per_vertex) % 32 == 0
1847 * (in other words, when the last 5 bits of vertex_count *
1848 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1849 * integer n (which is always the case, since bits_per_vertex is
1850 * always 1 or 2), this is equivalent to requiring that the last 5-n
1851 * bits of vertex_count are 0:
1853 * vertex_count & (2^(5-n) - 1) == 0
1855 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1858 * vertex_count & (32 / bits_per_vertex - 1) == 0
1860 * TODO: If vertex_count is an immediate, we could do some of this math
1861 * at compile time...
1864 abld
.AND(bld
.null_reg_d(), vertex_count
,
1865 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1866 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1868 abld
.IF(BRW_PREDICATE_NORMAL
);
1869 /* If vertex_count is 0, then no control data bits have been
1870 * accumulated yet, so we can skip emitting them.
1872 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1873 BRW_CONDITIONAL_NEQ
);
1874 abld
.IF(BRW_PREDICATE_NORMAL
);
1875 emit_gs_control_data_bits(vertex_count
);
1876 abld
.emit(BRW_OPCODE_ENDIF
);
1878 /* Reset control_data_bits to 0 so we can start accumulating a new
1881 * Note: in the case where vertex_count == 0, this neutralizes the
1882 * effect of any call to EndPrimitive() that the shader may have
1883 * made before outputting its first vertex.
1885 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1886 inst
->force_writemask_all
= true;
1887 abld
.emit(BRW_OPCODE_ENDIF
);
1890 emit_urb_writes(vertex_count
);
1892 /* In stream mode we have to set control data bits for all vertices
1893 * unless we have disabled control data bits completely (which we do
1894 * do for GL_POINTS outputs that don't use streams).
1896 if (gs_compile
->control_data_header_size_bits
> 0 &&
1897 gs_prog_data
->control_data_format
==
1898 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1899 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1904 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1905 const nir_src
&vertex_src
,
1906 unsigned base_offset
,
1907 const nir_src
&offset_src
,
1908 unsigned num_components
,
1909 unsigned first_component
)
1911 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1913 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1914 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1915 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1917 /* TODO: figure out push input layout for invocations == 1 */
1918 if (gs_prog_data
->invocations
== 1 &&
1919 offset_const
!= NULL
&& vertex_const
!= NULL
&&
1920 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1921 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1922 vertex_const
->u32
[0] * push_reg_count
;
1923 for (unsigned i
= 0; i
< num_components
; i
++) {
1924 bld
.MOV(offset(dst
, bld
, i
),
1925 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
1930 /* Resort to the pull model. Ensure the VUE handles are provided. */
1931 gs_prog_data
->base
.include_vue_handles
= true;
1933 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1934 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1936 if (gs_prog_data
->invocations
== 1) {
1938 /* The vertex index is constant; just select the proper URB handle. */
1940 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
1941 BRW_REGISTER_TYPE_UD
);
1943 /* The vertex index is non-constant. We need to use indirect
1944 * addressing to fetch the proper URB handle.
1946 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1947 * indicating that channel <n> should read the handle from
1948 * DWord <n>. We convert that to bytes by multiplying by 4.
1950 * Next, we convert the vertex index to bytes by multiplying
1951 * by 32 (shifting by 5), and add the two together. This is
1952 * the final indirect byte offset.
1954 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1955 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1956 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1957 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1959 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1960 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1961 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1962 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1963 /* Convert vertex_index to bytes (multiply by 32) */
1964 bld
.SHL(vertex_offset_bytes
,
1965 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1967 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1969 /* Use first_icp_handle as the base offset. There is one register
1970 * of URB handles per vertex, so inform the register allocator that
1971 * we might read up to nir->info.gs.vertices_in registers.
1973 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1974 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
1975 fs_reg(icp_offset_bytes
),
1976 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1979 assert(gs_prog_data
->invocations
> 1);
1982 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
1984 retype(brw_vec1_grf(first_icp_handle
+
1985 vertex_const
->i32
[0] / 8,
1986 vertex_const
->i32
[0] % 8),
1987 BRW_REGISTER_TYPE_UD
));
1989 /* The vertex index is non-constant. We need to use indirect
1990 * addressing to fetch the proper URB handle.
1993 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1995 /* Convert vertex_index to bytes (multiply by 4) */
1996 bld
.SHL(icp_offset_bytes
,
1997 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2000 /* Use first_icp_handle as the base offset. There is one DWord
2001 * of URB handles per vertex, so inform the register allocator that
2002 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2004 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2005 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2006 fs_reg(icp_offset_bytes
),
2007 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2014 fs_reg tmp_dst
= dst
;
2015 fs_reg indirect_offset
= get_nir_src(offset_src
);
2016 unsigned num_iterations
= 1;
2017 unsigned orig_num_components
= num_components
;
2019 if (type_sz(dst
.type
) == 8) {
2020 if (num_components
> 2) {
2024 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2026 first_component
= first_component
/ 2;
2029 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2031 /* Constant indexing - use global offset. */
2032 if (first_component
!= 0) {
2033 unsigned read_components
= num_components
+ first_component
;
2034 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2035 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2036 inst
->size_written
= read_components
*
2037 tmp
.component_size(inst
->exec_size
);
2038 for (unsigned i
= 0; i
< num_components
; i
++) {
2039 bld
.MOV(offset(tmp_dst
, bld
, i
),
2040 offset(tmp
, bld
, i
+ first_component
));
2043 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2045 inst
->size_written
= num_components
*
2046 tmp_dst
.component_size(inst
->exec_size
);
2048 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2051 /* Indirect indexing - use per-slot offsets as well. */
2052 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2053 unsigned read_components
= num_components
+ first_component
;
2054 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2055 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2056 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2057 if (first_component
!= 0) {
2058 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2060 inst
->size_written
= read_components
*
2061 tmp
.component_size(inst
->exec_size
);
2062 for (unsigned i
= 0; i
< num_components
; i
++) {
2063 bld
.MOV(offset(tmp_dst
, bld
, i
),
2064 offset(tmp
, bld
, i
+ first_component
));
2067 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2069 inst
->size_written
= num_components
*
2070 tmp_dst
.component_size(inst
->exec_size
);
2072 inst
->offset
= base_offset
;
2076 if (type_sz(dst
.type
) == 8) {
2077 shuffle_32bit_load_result_to_64bit_data(
2078 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2080 for (unsigned c
= 0; c
< num_components
; c
++)
2081 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2084 if (num_iterations
> 1) {
2085 num_components
= orig_num_components
- 2;
2089 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2090 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2091 indirect_offset
= new_indirect
;
2098 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2100 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2101 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2104 /* The only constant offset we should find is 0. brw_nir.c's
2105 * add_const_offset_to_base() will fold other constant offsets
2106 * into instr->const_index[0].
2108 assert(const_value
->u32
[0] == 0);
2112 return get_nir_src(*offset_src
);
2116 do_untyped_vector_read(const fs_builder
&bld
,
2118 const fs_reg surf_index
,
2119 const fs_reg offset_reg
,
2120 unsigned num_components
)
2122 if (type_sz(dest
.type
) == 4) {
2123 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2126 BRW_PREDICATE_NONE
);
2127 read_result
.type
= dest
.type
;
2128 for (unsigned i
= 0; i
< num_components
; i
++)
2129 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2130 } else if (type_sz(dest
.type
) == 8) {
2131 /* Reading a dvec, so we need to:
2133 * 1. Multiply num_components by 2, to account for the fact that we
2134 * need to read 64-bit components.
2135 * 2. Shuffle the result of the load to form valid 64-bit elements
2136 * 3. Emit a second load (for components z/w) if needed.
2138 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2139 bld
.MOV(read_offset
, offset_reg
);
2141 int iters
= num_components
<= 2 ? 1 : 2;
2143 /* Load the dvec, the first iteration loads components x/y, the second
2144 * iteration, if needed, loads components z/w
2146 for (int it
= 0; it
< iters
; it
++) {
2147 /* Compute number of components to read in this iteration */
2148 int iter_components
= MIN2(2, num_components
);
2149 num_components
-= iter_components
;
2151 /* Read. Since this message reads 32-bit components, we need to
2152 * read twice as many components.
2154 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2156 iter_components
* 2,
2157 BRW_PREDICATE_NONE
);
2159 /* Shuffle the 32-bit load result into valid 64-bit data */
2160 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2161 shuffle_32bit_load_result_to_64bit_data(
2162 bld
, packed_result
, read_result
, iter_components
);
2164 /* Move each component to its destination */
2165 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2166 for (int c
= 0; c
< iter_components
; c
++) {
2167 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2168 offset(packed_result
, bld
, c
));
2171 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2174 unreachable("Unsupported type");
2179 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2180 nir_intrinsic_instr
*instr
)
2182 assert(stage
== MESA_SHADER_VERTEX
);
2185 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2186 dest
= get_nir_dest(instr
->dest
);
2188 switch (instr
->intrinsic
) {
2189 case nir_intrinsic_load_vertex_id
:
2190 unreachable("should be lowered by lower_vertex_id()");
2192 case nir_intrinsic_load_vertex_id_zero_base
:
2193 case nir_intrinsic_load_base_vertex
:
2194 case nir_intrinsic_load_instance_id
:
2195 case nir_intrinsic_load_base_instance
:
2196 case nir_intrinsic_load_draw_id
: {
2197 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2198 fs_reg val
= nir_system_values
[sv
];
2199 assert(val
.file
!= BAD_FILE
);
2200 dest
.type
= val
.type
;
2205 case nir_intrinsic_load_input
: {
2206 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2207 unsigned first_component
= nir_intrinsic_component(instr
);
2208 unsigned num_components
= instr
->num_components
;
2209 enum brw_reg_type type
= dest
.type
;
2211 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2212 assert(const_offset
&& "Indirect input loads not allowed");
2213 src
= offset(src
, bld
, const_offset
->u32
[0]);
2215 for (unsigned j
= 0; j
< num_components
; j
++) {
2216 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2219 if (type
== BRW_REGISTER_TYPE_DF
) {
2220 /* Once the double vector is read, set again its original register
2221 * type to continue with normal execution.
2223 src
= retype(src
, type
);
2224 dest
= retype(dest
, type
);
2227 if (type_sz(src
.type
) == 8) {
2228 shuffle_32bit_load_result_to_64bit_data(bld
,
2230 retype(dest
, BRW_REGISTER_TYPE_F
),
2231 instr
->num_components
);
2237 nir_emit_intrinsic(bld
, instr
);
2243 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2244 nir_intrinsic_instr
*instr
)
2246 assert(stage
== MESA_SHADER_TESS_CTRL
);
2247 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2248 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2251 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2252 dst
= get_nir_dest(instr
->dest
);
2254 switch (instr
->intrinsic
) {
2255 case nir_intrinsic_load_primitive_id
:
2256 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2258 case nir_intrinsic_load_invocation_id
:
2259 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2261 case nir_intrinsic_load_patch_vertices_in
:
2262 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2263 brw_imm_d(tcs_key
->input_vertices
));
2266 case nir_intrinsic_barrier
: {
2267 if (tcs_prog_data
->instances
== 1)
2270 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2271 fs_reg m0_2
= component(m0
, 2);
2273 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2275 /* Zero the message header */
2276 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2278 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2279 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2280 brw_imm_ud(INTEL_MASK(16, 13)));
2282 /* Shift it up to bits 27:24. */
2283 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2285 /* Set the Barrier Count and the enable bit */
2286 chanbld
.OR(m0_2
, m0_2
,
2287 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2289 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2293 case nir_intrinsic_load_input
:
2294 unreachable("nir_lower_io should never give us these.");
2297 case nir_intrinsic_load_per_vertex_input
: {
2298 fs_reg indirect_offset
= get_indirect_offset(instr
);
2299 unsigned imm_offset
= instr
->const_index
[0];
2301 const nir_src
&vertex_src
= instr
->src
[0];
2302 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2309 /* Emit a MOV to resolve <0,1,0> regioning. */
2310 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2312 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2313 vertex_const
->i32
[0] & 7),
2314 BRW_REGISTER_TYPE_UD
));
2315 } else if (tcs_prog_data
->instances
== 1 &&
2316 vertex_src
.is_ssa
&&
2317 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2318 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2319 /* For the common case of only 1 instance, an array index of
2320 * gl_InvocationID means reading g1. Skip all the indirect work.
2322 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2324 /* The vertex index is non-constant. We need to use indirect
2325 * addressing to fetch the proper URB handle.
2327 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2329 /* Each ICP handle is a single DWord (4 bytes) */
2330 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2331 bld
.SHL(vertex_offset_bytes
,
2332 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2335 /* Start at g1. We might read up to 4 registers. */
2336 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2337 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2338 brw_imm_ud(4 * REG_SIZE
));
2341 /* We can only read two double components with each URB read, so
2342 * we send two read messages in that case, each one loading up to
2343 * two double components.
2345 unsigned num_iterations
= 1;
2346 unsigned num_components
= instr
->num_components
;
2347 unsigned first_component
= nir_intrinsic_component(instr
);
2348 fs_reg orig_dst
= dst
;
2349 if (type_sz(dst
.type
) == 8) {
2350 first_component
= first_component
/ 2;
2351 if (instr
->num_components
> 2) {
2356 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2360 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2361 if (indirect_offset
.file
== BAD_FILE
) {
2362 /* Constant indexing - use global offset. */
2363 if (first_component
!= 0) {
2364 unsigned read_components
= num_components
+ first_component
;
2365 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2366 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2367 for (unsigned i
= 0; i
< num_components
; i
++) {
2368 bld
.MOV(offset(dst
, bld
, i
),
2369 offset(tmp
, bld
, i
+ first_component
));
2372 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2374 inst
->offset
= imm_offset
;
2377 /* Indirect indexing - use per-slot offsets as well. */
2378 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2379 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2380 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2381 if (first_component
!= 0) {
2382 unsigned read_components
= num_components
+ first_component
;
2383 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2384 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2386 for (unsigned i
= 0; i
< num_components
; i
++) {
2387 bld
.MOV(offset(dst
, bld
, i
),
2388 offset(tmp
, bld
, i
+ first_component
));
2391 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2394 inst
->offset
= imm_offset
;
2397 inst
->size_written
= (num_components
+ first_component
) *
2398 inst
->dst
.component_size(inst
->exec_size
);
2400 /* If we are reading 64-bit data using 32-bit read messages we need
2401 * build proper 64-bit data elements by shuffling the low and high
2402 * 32-bit components around like we do for other things like UBOs
2405 if (type_sz(dst
.type
) == 8) {
2406 shuffle_32bit_load_result_to_64bit_data(
2407 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2409 for (unsigned c
= 0; c
< num_components
; c
++) {
2410 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2411 offset(dst
, bld
, c
));
2415 /* Copy the temporary to the destination to deal with writemasking.
2417 * Also attempt to deal with gl_PointSize being in the .w component.
2419 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2420 assert(type_sz(dst
.type
) < 8);
2421 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2422 inst
->size_written
= 4 * REG_SIZE
;
2423 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2426 /* If we are loading double data and we need a second read message
2427 * adjust the write offset
2429 if (num_iterations
> 1) {
2430 num_components
= instr
->num_components
- 2;
2437 case nir_intrinsic_load_output
:
2438 case nir_intrinsic_load_per_vertex_output
: {
2439 fs_reg indirect_offset
= get_indirect_offset(instr
);
2440 unsigned imm_offset
= instr
->const_index
[0];
2441 unsigned first_component
= nir_intrinsic_component(instr
);
2444 if (indirect_offset
.file
== BAD_FILE
) {
2445 /* Replicate the patch handle to all enabled channels */
2446 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2447 bld
.MOV(patch_handle
,
2448 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2451 if (first_component
!= 0) {
2452 unsigned read_components
=
2453 instr
->num_components
+ first_component
;
2454 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2455 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2457 inst
->size_written
= read_components
* REG_SIZE
;
2458 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2459 bld
.MOV(offset(dst
, bld
, i
),
2460 offset(tmp
, bld
, i
+ first_component
));
2463 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2465 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2467 inst
->offset
= imm_offset
;
2471 /* Indirect indexing - use per-slot offsets as well. */
2472 const fs_reg srcs
[] = {
2473 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2476 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2477 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2478 if (first_component
!= 0) {
2479 unsigned read_components
=
2480 instr
->num_components
+ first_component
;
2481 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2482 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2484 inst
->size_written
= read_components
* REG_SIZE
;
2485 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2486 bld
.MOV(offset(dst
, bld
, i
),
2487 offset(tmp
, bld
, i
+ first_component
));
2490 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2492 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2494 inst
->offset
= imm_offset
;
2500 case nir_intrinsic_store_output
:
2501 case nir_intrinsic_store_per_vertex_output
: {
2502 fs_reg value
= get_nir_src(instr
->src
[0]);
2503 bool is_64bit
= (instr
->src
[0].is_ssa
?
2504 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2505 fs_reg indirect_offset
= get_indirect_offset(instr
);
2506 unsigned imm_offset
= instr
->const_index
[0];
2507 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2508 unsigned mask
= instr
->const_index
[1];
2509 unsigned header_regs
= 0;
2511 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2513 if (indirect_offset
.file
!= BAD_FILE
) {
2514 srcs
[header_regs
++] = indirect_offset
;
2520 unsigned num_components
= util_last_bit(mask
);
2523 /* We can only pack two 64-bit components in a single message, so send
2524 * 2 messages if we have more components
2526 unsigned num_iterations
= 1;
2527 unsigned iter_components
= num_components
;
2528 unsigned first_component
= nir_intrinsic_component(instr
);
2530 first_component
= first_component
/ 2;
2531 if (instr
->num_components
> 2) {
2533 iter_components
= 2;
2537 /* 64-bit data needs to me shuffled before we can write it to the URB.
2538 * We will use this temporary to shuffle the components in each
2542 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2544 mask
= mask
<< first_component
;
2546 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2547 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2548 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2549 opcode
= indirect_offset
.file
!= BAD_FILE
?
2550 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2551 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2552 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2553 /* Expand the 64-bit mask to 32-bit channels. We only handle
2554 * two channels in each iteration, so we only care about X/Y.
2556 unsigned mask32
= 0;
2557 if (mask
& WRITEMASK_X
)
2558 mask32
|= WRITEMASK_XY
;
2559 if (mask
& WRITEMASK_Y
)
2560 mask32
|= WRITEMASK_ZW
;
2562 /* If the mask does not include any of the channels X or Y there
2563 * is nothing to do in this iteration. Move on to the next couple
2564 * of 64-bit channels.
2572 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2573 opcode
= indirect_offset
.file
!= BAD_FILE
?
2574 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2575 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2577 opcode
= indirect_offset
.file
!= BAD_FILE
?
2578 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2579 SHADER_OPCODE_URB_WRITE_SIMD8
;
2582 for (unsigned i
= 0; i
< iter_components
; i
++) {
2583 if (!(mask
& (1 << (i
+ first_component
))))
2587 srcs
[header_regs
+ i
+ first_component
] =
2588 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2590 /* We need to shuffle the 64-bit data to match the layout
2591 * expected by our 32-bit URB write messages. We use a temporary
2594 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2595 shuffle_64bit_data_for_32bit_write(bld
,
2596 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2597 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2600 /* Now copy the data to the destination */
2601 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2602 unsigned idx
= 2 * i
;
2603 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2604 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2605 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2606 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2607 offset(dest
, bld
, 1);
2612 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2613 (is_64bit
? 2 * first_component
: first_component
);
2615 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2616 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2618 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2619 inst
->offset
= imm_offset
;
2622 /* If this is a 64-bit attribute, select the next two 64-bit channels
2623 * to be handled in the next iteration.
2634 nir_emit_intrinsic(bld
, instr
);
2640 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2641 nir_intrinsic_instr
*instr
)
2643 assert(stage
== MESA_SHADER_TESS_EVAL
);
2644 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2647 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2648 dest
= get_nir_dest(instr
->dest
);
2650 switch (instr
->intrinsic
) {
2651 case nir_intrinsic_load_primitive_id
:
2652 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2654 case nir_intrinsic_load_tess_coord
:
2655 /* gl_TessCoord is part of the payload in g1-3 */
2656 for (unsigned i
= 0; i
< 3; i
++) {
2657 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2661 case nir_intrinsic_load_input
:
2662 case nir_intrinsic_load_per_vertex_input
: {
2663 fs_reg indirect_offset
= get_indirect_offset(instr
);
2664 unsigned imm_offset
= instr
->const_index
[0];
2665 unsigned first_component
= nir_intrinsic_component(instr
);
2667 if (type_sz(dest
.type
) == 8) {
2668 first_component
= first_component
/ 2;
2672 if (indirect_offset
.file
== BAD_FILE
) {
2673 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2674 * which is 16 registers (since each holds 2 vec4 slots).
2676 const unsigned max_push_slots
= 32;
2677 if (imm_offset
< max_push_slots
) {
2678 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2679 for (int i
= 0; i
< instr
->num_components
; i
++) {
2680 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2681 i
+ first_component
;
2682 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2684 tes_prog_data
->base
.urb_read_length
=
2685 MAX2(tes_prog_data
->base
.urb_read_length
,
2686 DIV_ROUND_UP(imm_offset
+ 1, 2));
2688 /* Replicate the patch handle to all enabled channels */
2689 const fs_reg srcs
[] = {
2690 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2692 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2693 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2695 if (first_component
!= 0) {
2696 unsigned read_components
=
2697 instr
->num_components
+ first_component
;
2698 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2699 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2701 inst
->size_written
= read_components
* REG_SIZE
;
2702 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2703 bld
.MOV(offset(dest
, bld
, i
),
2704 offset(tmp
, bld
, i
+ first_component
));
2707 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2709 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2712 inst
->offset
= imm_offset
;
2715 /* Indirect indexing - use per-slot offsets as well. */
2717 /* We can only read two double components with each URB read, so
2718 * we send two read messages in that case, each one loading up to
2719 * two double components.
2721 unsigned num_iterations
= 1;
2722 unsigned num_components
= instr
->num_components
;
2723 fs_reg orig_dest
= dest
;
2724 if (type_sz(dest
.type
) == 8) {
2725 if (instr
->num_components
> 2) {
2729 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2733 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2734 const fs_reg srcs
[] = {
2735 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2738 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2739 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2741 if (first_component
!= 0) {
2742 unsigned read_components
=
2743 num_components
+ first_component
;
2744 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2745 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2747 for (unsigned i
= 0; i
< num_components
; i
++) {
2748 bld
.MOV(offset(dest
, bld
, i
),
2749 offset(tmp
, bld
, i
+ first_component
));
2752 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2756 inst
->offset
= imm_offset
;
2757 inst
->size_written
= (num_components
+ first_component
) *
2758 inst
->dst
.component_size(inst
->exec_size
);
2760 /* If we are reading 64-bit data using 32-bit read messages we need
2761 * build proper 64-bit data elements by shuffling the low and high
2762 * 32-bit components around like we do for other things like UBOs
2765 if (type_sz(dest
.type
) == 8) {
2766 shuffle_32bit_load_result_to_64bit_data(
2767 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2769 for (unsigned c
= 0; c
< num_components
; c
++) {
2770 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2771 offset(dest
, bld
, c
));
2775 /* If we are loading double data and we need a second read message
2778 if (num_iterations
> 1) {
2779 num_components
= instr
->num_components
- 2;
2787 nir_emit_intrinsic(bld
, instr
);
2793 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2794 nir_intrinsic_instr
*instr
)
2796 assert(stage
== MESA_SHADER_GEOMETRY
);
2797 fs_reg indirect_offset
;
2800 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2801 dest
= get_nir_dest(instr
->dest
);
2803 switch (instr
->intrinsic
) {
2804 case nir_intrinsic_load_primitive_id
:
2805 assert(stage
== MESA_SHADER_GEOMETRY
);
2806 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2807 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2808 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2811 case nir_intrinsic_load_input
:
2812 unreachable("load_input intrinsics are invalid for the GS stage");
2814 case nir_intrinsic_load_per_vertex_input
:
2815 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2816 instr
->src
[1], instr
->num_components
,
2817 nir_intrinsic_component(instr
));
2820 case nir_intrinsic_emit_vertex_with_counter
:
2821 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2824 case nir_intrinsic_end_primitive_with_counter
:
2825 emit_gs_end_primitive(instr
->src
[0]);
2828 case nir_intrinsic_set_vertex_count
:
2829 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2832 case nir_intrinsic_load_invocation_id
: {
2833 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2834 assert(val
.file
!= BAD_FILE
);
2835 dest
.type
= val
.type
;
2841 nir_emit_intrinsic(bld
, instr
);
2847 * Fetch the current render target layer index.
2850 fetch_render_target_array_index(const fs_builder
&bld
)
2852 if (bld
.shader
->devinfo
->gen
>= 6) {
2853 /* The render target array index is provided in the thread payload as
2854 * bits 26:16 of r0.0.
2856 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2857 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2861 /* Pre-SNB we only ever render into the first layer of the framebuffer
2862 * since layered rendering is not implemented.
2864 return brw_imm_ud(0);
2869 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2870 * framebuffer at the current fragment coordinates and sample index.
2873 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2876 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2878 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2879 const brw_wm_prog_key
*wm_key
=
2880 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2881 assert(!wm_key
->coherent_fb_fetch
);
2882 const struct brw_wm_prog_data
*wm_prog_data
=
2883 brw_wm_prog_data(stage_prog_data
);
2885 /* Calculate the surface index relative to the start of the texture binding
2886 * table block, since that's what the texturing messages expect.
2888 const unsigned surface
= target
+
2889 wm_prog_data
->binding_table
.render_target_read_start
-
2890 wm_prog_data
->base
.binding_table
.texture_start
;
2892 brw_mark_surface_used(
2893 bld
.shader
->stage_prog_data
,
2894 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2896 /* Calculate the fragment coordinates. */
2897 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2898 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2899 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2900 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2902 /* Calculate the sample index and MCS payload when multisampling. Luckily
2903 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2904 * shouldn't be necessary to recompile based on whether the framebuffer is
2907 if (wm_key
->multisample_fbo
&&
2908 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2909 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2911 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2912 const fs_reg mcs
= wm_key
->multisample_fbo
?
2913 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2915 /* Use either a normal or a CMS texel fetch message depending on whether
2916 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2917 * message just in case the framebuffer uses 16x multisampling, it should
2918 * be equivalent to the normal CMS fetch for lower multisampling modes.
2920 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2921 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2922 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2924 /* Emit the instruction. */
2925 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
2927 brw_imm_ud(surface
), brw_imm_ud(0),
2928 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
2929 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
2931 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
2932 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2938 * Actual coherent framebuffer read implemented using the native render target
2939 * read message. Requires SKL+.
2942 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
2944 assert(bld
.shader
->devinfo
->gen
>= 9);
2945 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
2946 inst
->target
= target
;
2947 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2953 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
2955 if (n
&& regs
[0].file
!= BAD_FILE
) {
2959 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
2961 for (unsigned i
= 0; i
< n
; i
++)
2969 alloc_frag_output(fs_visitor
*v
, unsigned location
)
2971 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
2972 const brw_wm_prog_key
*const key
=
2973 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
2974 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
2975 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
2977 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
2978 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
2980 else if (l
== FRAG_RESULT_COLOR
)
2981 return alloc_temporary(v
->bld
, 4, v
->outputs
,
2982 MAX2(key
->nr_color_regions
, 1));
2984 else if (l
== FRAG_RESULT_DEPTH
)
2985 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
2987 else if (l
== FRAG_RESULT_STENCIL
)
2988 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
2990 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
2991 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
2993 else if (l
>= FRAG_RESULT_DATA0
&&
2994 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
2995 return alloc_temporary(v
->bld
, 4,
2996 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
2999 unreachable("Invalid location");
3003 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3004 nir_intrinsic_instr
*instr
)
3006 assert(stage
== MESA_SHADER_FRAGMENT
);
3009 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3010 dest
= get_nir_dest(instr
->dest
);
3012 switch (instr
->intrinsic
) {
3013 case nir_intrinsic_load_front_face
:
3014 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3015 *emit_frontfacing_interpolation());
3018 case nir_intrinsic_load_sample_pos
: {
3019 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3020 assert(sample_pos
.file
!= BAD_FILE
);
3021 dest
.type
= sample_pos
.type
;
3022 bld
.MOV(dest
, sample_pos
);
3023 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3027 case nir_intrinsic_load_layer_id
:
3028 dest
.type
= BRW_REGISTER_TYPE_UD
;
3029 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3032 case nir_intrinsic_load_helper_invocation
:
3033 case nir_intrinsic_load_sample_mask_in
:
3034 case nir_intrinsic_load_sample_id
: {
3035 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3036 fs_reg val
= nir_system_values
[sv
];
3037 assert(val
.file
!= BAD_FILE
);
3038 dest
.type
= val
.type
;
3043 case nir_intrinsic_store_output
: {
3044 const fs_reg src
= get_nir_src(instr
->src
[0]);
3045 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3046 assert(const_offset
&& "Indirect output stores not allowed");
3047 const unsigned location
= nir_intrinsic_base(instr
) +
3048 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3049 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3052 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3053 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3054 offset(src
, bld
, j
));
3059 case nir_intrinsic_load_output
: {
3060 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3061 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3062 assert(l
>= FRAG_RESULT_DATA0
);
3063 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3064 assert(const_offset
&& "Indirect output loads not allowed");
3065 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3066 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3068 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3069 emit_coherent_fb_read(bld
, tmp
, target
);
3071 emit_non_coherent_fb_read(bld
, tmp
, target
);
3073 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3074 bld
.MOV(offset(dest
, bld
, j
),
3075 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3081 case nir_intrinsic_discard
:
3082 case nir_intrinsic_discard_if
: {
3083 /* We track our discarded pixels in f0.1. By predicating on it, we can
3084 * update just the flag bits that aren't yet discarded. If there's no
3085 * condition, we emit a CMP of g0 != g0, so all currently executing
3086 * channels will get turned off.
3089 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3090 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3091 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3093 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3094 BRW_REGISTER_TYPE_UW
));
3095 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3097 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3098 cmp
->flag_subreg
= 1;
3100 if (devinfo
->gen
>= 6) {
3101 emit_discard_jump();
3106 case nir_intrinsic_load_input
: {
3107 /* load_input is only used for flat inputs */
3108 unsigned base
= nir_intrinsic_base(instr
);
3109 unsigned component
= nir_intrinsic_component(instr
);
3110 unsigned num_components
= instr
->num_components
;
3111 enum brw_reg_type type
= dest
.type
;
3113 /* Special case fields in the VUE header */
3114 if (base
== VARYING_SLOT_LAYER
)
3116 else if (base
== VARYING_SLOT_VIEWPORT
)
3119 if (nir_dest_bit_size(instr
->dest
) == 64) {
3120 /* const_index is in 32-bit type size units that could not be aligned
3121 * with DF. We need to read the double vector as if it was a float
3122 * vector of twice the number of components to fetch the right data.
3124 type
= BRW_REGISTER_TYPE_F
;
3125 num_components
*= 2;
3128 for (unsigned int i
= 0; i
< num_components
; i
++) {
3129 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3130 interp
= suboffset(interp
, 3);
3131 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3132 retype(fs_reg(interp
), type
));
3135 if (nir_dest_bit_size(instr
->dest
) == 64) {
3136 shuffle_32bit_load_result_to_64bit_data(bld
,
3139 instr
->num_components
);
3144 case nir_intrinsic_load_barycentric_pixel
:
3145 case nir_intrinsic_load_barycentric_centroid
:
3146 case nir_intrinsic_load_barycentric_sample
:
3147 /* Do nothing - load_interpolated_input handling will handle it later. */
3150 case nir_intrinsic_load_barycentric_at_sample
: {
3151 const glsl_interp_mode interpolation
=
3152 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3154 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3157 unsigned msg_data
= const_sample
->i32
[0] << 4;
3159 emit_pixel_interpolater_send(bld
,
3160 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3163 brw_imm_ud(msg_data
),
3166 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3167 BRW_REGISTER_TYPE_UD
);
3169 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3170 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3171 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3172 bld
.exec_all().group(1, 0)
3173 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3174 emit_pixel_interpolater_send(bld
,
3175 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3181 /* Make a loop that sends a message to the pixel interpolater
3182 * for the sample number in each live channel. If there are
3183 * multiple channels with the same sample number then these
3184 * will be handled simultaneously with a single interation of
3187 bld
.emit(BRW_OPCODE_DO
);
3189 /* Get the next live sample number into sample_id_reg */
3190 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3192 /* Set the flag register so that we can perform the send
3193 * message on all channels that have the same sample number
3195 bld
.CMP(bld
.null_reg_ud(),
3196 sample_src
, sample_id
,
3197 BRW_CONDITIONAL_EQ
);
3198 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3199 bld
.exec_all().group(1, 0)
3200 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3202 emit_pixel_interpolater_send(bld
,
3203 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3208 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3210 /* Continue the loop if there are any live channels left */
3211 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3213 bld
.emit(BRW_OPCODE_WHILE
));
3219 case nir_intrinsic_load_barycentric_at_offset
: {
3220 const glsl_interp_mode interpolation
=
3221 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3223 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3226 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3227 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3229 emit_pixel_interpolater_send(bld
,
3230 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3233 brw_imm_ud(off_x
| (off_y
<< 4)),
3236 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3237 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3238 BRW_REGISTER_TYPE_F
);
3239 for (int i
= 0; i
< 2; i
++) {
3240 fs_reg temp
= vgrf(glsl_type::float_type
);
3241 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3242 fs_reg itemp
= vgrf(glsl_type::int_type
);
3244 bld
.MOV(itemp
, temp
);
3246 /* Clamp the upper end of the range to +7/16.
3247 * ARB_gpu_shader5 requires that we support a maximum offset
3248 * of +0.5, which isn't representable in a S0.4 value -- if
3249 * we didn't clamp it, we'd end up with -8/16, which is the
3250 * opposite of what the shader author wanted.
3252 * This is legal due to ARB_gpu_shader5's quantization
3255 * "Not all values of <offset> may be supported; x and y
3256 * offsets may be rounded to fixed-point values with the
3257 * number of fraction bits given by the
3258 * implementation-dependent constant
3259 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3261 set_condmod(BRW_CONDITIONAL_L
,
3262 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3265 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3266 emit_pixel_interpolater_send(bld
,
3276 case nir_intrinsic_load_interpolated_input
: {
3277 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3278 emit_fragcoord_interpolation(dest
);
3282 assert(instr
->src
[0].ssa
&&
3283 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3284 nir_intrinsic_instr
*bary_intrinsic
=
3285 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3286 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3287 enum glsl_interp_mode interp_mode
=
3288 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3291 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3292 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3293 /* Use the result of the PI message */
3294 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3296 /* Use the delta_xy values computed from the payload */
3297 enum brw_barycentric_mode bary
=
3298 brw_barycentric_mode(interp_mode
, bary_intrin
);
3300 dst_xy
= this->delta_xy
[bary
];
3303 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3305 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3306 nir_intrinsic_component(instr
) + i
));
3307 interp
.type
= BRW_REGISTER_TYPE_F
;
3308 dest
.type
= BRW_REGISTER_TYPE_F
;
3310 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3311 fs_reg tmp
= vgrf(glsl_type::float_type
);
3312 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3313 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3315 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3322 nir_emit_intrinsic(bld
, instr
);
3328 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3329 nir_intrinsic_instr
*instr
)
3331 assert(stage
== MESA_SHADER_COMPUTE
);
3332 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3335 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3336 dest
= get_nir_dest(instr
->dest
);
3338 switch (instr
->intrinsic
) {
3339 case nir_intrinsic_barrier
:
3341 cs_prog_data
->uses_barrier
= true;
3344 case nir_intrinsic_load_local_invocation_id
:
3345 case nir_intrinsic_load_work_group_id
: {
3346 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3347 fs_reg val
= nir_system_values
[sv
];
3348 assert(val
.file
!= BAD_FILE
);
3349 dest
.type
= val
.type
;
3350 for (unsigned i
= 0; i
< 3; i
++)
3351 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3355 case nir_intrinsic_load_num_work_groups
: {
3356 const unsigned surface
=
3357 cs_prog_data
->binding_table
.work_groups_start
;
3359 cs_prog_data
->uses_num_work_groups
= true;
3361 fs_reg surf_index
= brw_imm_ud(surface
);
3362 brw_mark_surface_used(prog_data
, surface
);
3364 /* Read the 3 GLuint components of gl_NumWorkGroups */
3365 for (unsigned i
= 0; i
< 3; i
++) {
3366 fs_reg read_result
=
3367 emit_untyped_read(bld
, surf_index
,
3369 1 /* dims */, 1 /* size */,
3370 BRW_PREDICATE_NONE
);
3371 read_result
.type
= dest
.type
;
3372 bld
.MOV(dest
, read_result
);
3373 dest
= offset(dest
, bld
, 1);
3378 case nir_intrinsic_shared_atomic_add
:
3379 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3381 case nir_intrinsic_shared_atomic_imin
:
3382 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3384 case nir_intrinsic_shared_atomic_umin
:
3385 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3387 case nir_intrinsic_shared_atomic_imax
:
3388 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3390 case nir_intrinsic_shared_atomic_umax
:
3391 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3393 case nir_intrinsic_shared_atomic_and
:
3394 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3396 case nir_intrinsic_shared_atomic_or
:
3397 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3399 case nir_intrinsic_shared_atomic_xor
:
3400 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3402 case nir_intrinsic_shared_atomic_exchange
:
3403 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3405 case nir_intrinsic_shared_atomic_comp_swap
:
3406 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3409 case nir_intrinsic_load_shared
: {
3410 assert(devinfo
->gen
>= 7);
3412 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3414 /* Get the offset to read from */
3416 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3418 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3420 offset_reg
= vgrf(glsl_type::uint_type
);
3422 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3423 brw_imm_ud(instr
->const_index
[0]));
3426 /* Read the vector */
3427 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3428 instr
->num_components
);
3432 case nir_intrinsic_store_shared
: {
3433 assert(devinfo
->gen
>= 7);
3436 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3439 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3442 unsigned writemask
= instr
->const_index
[1];
3444 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3445 * since the untyped writes below operate in units of 32-bits, which
3446 * means that we need to write twice as many components each time.
3447 * Also, we have to suffle 64-bit data to be in the appropriate layout
3448 * expected by our 32-bit write messages.
3450 unsigned type_size
= 4;
3451 unsigned bit_size
= instr
->src
[0].is_ssa
?
3452 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3453 if (bit_size
== 64) {
3456 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3457 shuffle_64bit_data_for_32bit_write(
3459 retype(tmp
, BRW_REGISTER_TYPE_F
),
3460 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3461 instr
->num_components
);
3465 unsigned type_slots
= type_size
/ 4;
3467 /* Combine groups of consecutive enabled channels in one write
3468 * message. We use ffs to find the first enabled channel and then ffs on
3469 * the bit-inverse, down-shifted writemask to determine the length of
3470 * the block of enabled bits.
3473 unsigned first_component
= ffs(writemask
) - 1;
3474 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3476 /* We can't write more than 2 64-bit components at once. Limit the
3477 * length of the write to what we can do and let the next iteration
3481 length
= MIN2(2, length
);
3484 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3486 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3487 type_size
* first_component
);
3489 offset_reg
= vgrf(glsl_type::uint_type
);
3491 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3492 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3495 emit_untyped_write(bld
, surf_index
, offset_reg
,
3496 offset(val_reg
, bld
, first_component
* type_slots
),
3497 1 /* dims */, length
* type_slots
,
3498 BRW_PREDICATE_NONE
);
3500 /* Clear the bits in the writemask that we just wrote, then try
3501 * again to see if more channels are left.
3503 writemask
&= (15 << (first_component
+ length
));
3510 nir_emit_intrinsic(bld
, instr
);
3516 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3519 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3520 dest
= get_nir_dest(instr
->dest
);
3522 switch (instr
->intrinsic
) {
3523 case nir_intrinsic_atomic_counter_inc
:
3524 case nir_intrinsic_atomic_counter_dec
:
3525 case nir_intrinsic_atomic_counter_read
:
3526 case nir_intrinsic_atomic_counter_add
:
3527 case nir_intrinsic_atomic_counter_min
:
3528 case nir_intrinsic_atomic_counter_max
:
3529 case nir_intrinsic_atomic_counter_and
:
3530 case nir_intrinsic_atomic_counter_or
:
3531 case nir_intrinsic_atomic_counter_xor
:
3532 case nir_intrinsic_atomic_counter_exchange
:
3533 case nir_intrinsic_atomic_counter_comp_swap
: {
3534 if (stage
== MESA_SHADER_FRAGMENT
&&
3535 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3536 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3538 /* Get some metadata from the image intrinsic. */
3539 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3541 /* Get the arguments of the atomic intrinsic. */
3542 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3543 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3544 instr
->const_index
[0]);
3545 const fs_reg src0
= (info
->num_srcs
>= 2
3546 ? get_nir_src(instr
->src
[1]) : fs_reg());
3547 const fs_reg src1
= (info
->num_srcs
>= 3
3548 ? get_nir_src(instr
->src
[2]) : fs_reg());
3551 assert(info
->num_srcs
<= 3);
3553 /* Emit a surface read or atomic op. */
3554 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3555 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3557 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3559 get_atomic_counter_op(instr
->intrinsic
));
3562 /* Assign the result. */
3563 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3565 /* Mark the surface as used. */
3566 brw_mark_surface_used(stage_prog_data
, surface
);
3570 case nir_intrinsic_image_load
:
3571 case nir_intrinsic_image_store
:
3572 case nir_intrinsic_image_atomic_add
:
3573 case nir_intrinsic_image_atomic_min
:
3574 case nir_intrinsic_image_atomic_max
:
3575 case nir_intrinsic_image_atomic_and
:
3576 case nir_intrinsic_image_atomic_or
:
3577 case nir_intrinsic_image_atomic_xor
:
3578 case nir_intrinsic_image_atomic_exchange
:
3579 case nir_intrinsic_image_atomic_comp_swap
: {
3580 using namespace image_access
;
3582 if (stage
== MESA_SHADER_FRAGMENT
&&
3583 instr
->intrinsic
!= nir_intrinsic_image_load
)
3584 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3586 /* Get the referenced image variable and type. */
3587 const nir_variable
*var
= instr
->variables
[0]->var
;
3588 const glsl_type
*type
= var
->type
->without_array();
3589 const brw_reg_type base_type
= get_image_base_type(type
);
3591 /* Get some metadata from the image intrinsic. */
3592 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3593 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3594 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3595 const unsigned format
= var
->data
.image
.format
;
3597 /* Get the arguments of the image intrinsic. */
3598 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3599 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3600 BRW_REGISTER_TYPE_UD
);
3601 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3602 retype(get_nir_src(instr
->src
[2]), base_type
) :
3604 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3605 retype(get_nir_src(instr
->src
[3]), base_type
) :
3609 /* Emit an image load, store or atomic op. */
3610 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3611 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3613 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3614 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3615 var
->data
.image
.write_only
? GL_NONE
: format
);
3618 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3619 surf_dims
, arr_dims
, info
->dest_components
,
3620 get_image_atomic_op(instr
->intrinsic
, type
));
3622 /* Assign the result. */
3623 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3624 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3625 offset(tmp
, bld
, c
));
3629 case nir_intrinsic_memory_barrier_atomic_counter
:
3630 case nir_intrinsic_memory_barrier_buffer
:
3631 case nir_intrinsic_memory_barrier_image
:
3632 case nir_intrinsic_memory_barrier
: {
3633 const fs_builder ubld
= bld
.group(8, 0);
3634 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3635 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3636 ->size_written
= 2 * REG_SIZE
;
3640 case nir_intrinsic_group_memory_barrier
:
3641 case nir_intrinsic_memory_barrier_shared
:
3642 /* We treat these workgroup-level barriers as no-ops. This should be
3643 * safe at present and as long as:
3645 * - Memory access instructions are not subsequently reordered by the
3646 * compiler back-end.
3648 * - All threads from a given compute shader workgroup fit within a
3649 * single subslice and therefore talk to the same HDC shared unit
3650 * what supposedly guarantees ordering and coherency between threads
3651 * from the same workgroup. This may change in the future when we
3652 * start splitting workgroups across multiple subslices.
3654 * - The context is not in fault-and-stream mode, which could cause
3655 * memory transactions (including to SLM) prior to the barrier to be
3656 * replayed after the barrier if a pagefault occurs. This shouldn't
3657 * be a problem up to and including SKL because fault-and-stream is
3658 * not usable due to hardware issues, but that's likely to change in
3663 case nir_intrinsic_shader_clock
: {
3664 /* We cannot do anything if there is an event, so ignore it for now */
3665 const fs_reg shader_clock
= get_timestamp(bld
);
3666 const fs_reg srcs
[] = { component(shader_clock
, 0),
3667 component(shader_clock
, 1) };
3668 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3672 case nir_intrinsic_image_size
: {
3673 /* Get the referenced image variable and type. */
3674 const nir_variable
*var
= instr
->variables
[0]->var
;
3675 const glsl_type
*type
= var
->type
->without_array();
3677 /* Get the size of the image. */
3678 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3679 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3681 /* For 1DArray image types, the array index is stored in the Z component.
3682 * Fix this by swizzling the Z component to the Y component.
3684 const bool is_1d_array_image
=
3685 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3686 type
->sampler_array
;
3688 /* For CubeArray images, we should count the number of cubes instead
3689 * of the number of faces. Fix it by dividing the (Z component) by 6.
3691 const bool is_cube_array_image
=
3692 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3693 type
->sampler_array
;
3695 /* Copy all the components. */
3696 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3697 if ((int)c
>= type
->coordinate_components()) {
3698 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3700 } else if (c
== 1 && is_1d_array_image
) {
3701 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3702 offset(size
, bld
, 2));
3703 } else if (c
== 2 && is_cube_array_image
) {
3704 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3705 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3706 offset(size
, bld
, c
), brw_imm_d(6));
3708 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3709 offset(size
, bld
, c
));
3716 case nir_intrinsic_image_samples
:
3717 /* The driver does not support multi-sampled images. */
3718 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3721 case nir_intrinsic_load_uniform
: {
3722 /* Offsets are in bytes but they should always be multiples of 4 */
3723 assert(instr
->const_index
[0] % 4 == 0);
3725 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3727 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3729 /* Offsets are in bytes but they should always be multiples of 4 */
3730 assert(const_offset
->u32
[0] % 4 == 0);
3731 src
.offset
= const_offset
->u32
[0];
3733 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3734 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3737 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3738 BRW_REGISTER_TYPE_UD
);
3740 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3741 * go past the end of the uniform. In order to keep the n'th
3742 * component from running past, we subtract off the size of all but
3743 * one component of the vector.
3745 assert(instr
->const_index
[1] >=
3746 instr
->num_components
* (int) type_sz(dest
.type
));
3747 unsigned read_size
= instr
->const_index
[1] -
3748 (instr
->num_components
- 1) * type_sz(dest
.type
);
3750 bool supports_64bit_indirects
=
3751 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3753 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3754 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3755 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3756 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3757 indirect
, brw_imm_ud(read_size
));
3760 const unsigned num_mov_indirects
=
3761 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3762 /* We read a little bit less per MOV INDIRECT, as they are now
3763 * 32-bits ones instead of 64-bit. Fix read_size then.
3765 const unsigned read_size_32bit
= read_size
-
3766 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3767 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3768 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3769 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3770 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3771 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3772 indirect
, brw_imm_ud(read_size_32bit
));
3780 case nir_intrinsic_load_ubo
: {
3781 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3785 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3786 const_index
->u32
[0];
3787 surf_index
= brw_imm_ud(index
);
3788 brw_mark_surface_used(prog_data
, index
);
3790 /* The block index is not a constant. Evaluate the index expression
3791 * per-channel and add the base UBO index; we have to select a value
3792 * from any live channel.
3794 surf_index
= vgrf(glsl_type::uint_type
);
3795 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3796 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3797 surf_index
= bld
.emit_uniformize(surf_index
);
3799 /* Assume this may touch any UBO. It would be nice to provide
3800 * a tighter bound, but the array information is already lowered away.
3802 brw_mark_surface_used(prog_data
,
3803 stage_prog_data
->binding_table
.ubo_start
+
3804 nir
->info
.num_ubos
- 1);
3807 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3808 if (const_offset
== NULL
) {
3809 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3810 BRW_REGISTER_TYPE_UD
);
3812 for (int i
= 0; i
< instr
->num_components
; i
++)
3813 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3814 base_offset
, i
* type_sz(dest
.type
));
3816 /* Even if we are loading doubles, a pull constant load will load
3817 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3818 * need to load a full dvec4 we will have to emit 2 loads. This is
3819 * similar to demote_pull_constants(), except that in that case we
3820 * see individual accesses to each component of the vector and then
3821 * we let CSE deal with duplicate loads. Here we see a vector access
3822 * and we have to split it if necessary.
3824 const unsigned type_size
= type_sz(dest
.type
);
3826 /* See if we've selected this as a push constant candidate */
3828 const unsigned ubo_block
= const_index
->u32
[0];
3829 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
3832 for (int i
= 0; i
< 4; i
++) {
3833 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3834 if (range
->block
== ubo_block
&&
3835 offset_256b
>= range
->start
&&
3836 offset_256b
< range
->start
+ range
->length
) {
3838 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3839 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
3844 if (push_reg
.file
!= BAD_FILE
) {
3845 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3846 bld
.MOV(offset(dest
, bld
, i
),
3847 byte_offset(push_reg
, i
* type_size
));
3853 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3854 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3855 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3857 for (unsigned c
= 0; c
< instr
->num_components
;) {
3858 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3859 /* Number of usable components in the next block-aligned load. */
3860 const unsigned count
= MIN2(instr
->num_components
- c
,
3861 (block_sz
- base
% block_sz
) / type_size
);
3863 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3864 packed_consts
, surf_index
,
3865 brw_imm_ud(base
& ~(block_sz
- 1)));
3867 const fs_reg consts
=
3868 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3871 for (unsigned d
= 0; d
< count
; d
++)
3872 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3880 case nir_intrinsic_load_ssbo
: {
3881 assert(devinfo
->gen
>= 7);
3883 nir_const_value
*const_uniform_block
=
3884 nir_src_as_const_value(instr
->src
[0]);
3887 if (const_uniform_block
) {
3888 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3889 const_uniform_block
->u32
[0];
3890 surf_index
= brw_imm_ud(index
);
3891 brw_mark_surface_used(prog_data
, index
);
3893 surf_index
= vgrf(glsl_type::uint_type
);
3894 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3895 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3897 /* Assume this may touch any UBO. It would be nice to provide
3898 * a tighter bound, but the array information is already lowered away.
3900 brw_mark_surface_used(prog_data
,
3901 stage_prog_data
->binding_table
.ssbo_start
+
3902 nir
->info
.num_ssbos
- 1);
3906 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3908 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3910 offset_reg
= get_nir_src(instr
->src
[1]);
3913 /* Read the vector */
3914 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3915 instr
->num_components
);
3920 case nir_intrinsic_store_ssbo
: {
3921 assert(devinfo
->gen
>= 7);
3923 if (stage
== MESA_SHADER_FRAGMENT
)
3924 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3928 nir_const_value
*const_uniform_block
=
3929 nir_src_as_const_value(instr
->src
[1]);
3930 if (const_uniform_block
) {
3931 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3932 const_uniform_block
->u32
[0];
3933 surf_index
= brw_imm_ud(index
);
3934 brw_mark_surface_used(prog_data
, index
);
3936 surf_index
= vgrf(glsl_type::uint_type
);
3937 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3938 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3940 brw_mark_surface_used(prog_data
,
3941 stage_prog_data
->binding_table
.ssbo_start
+
3942 nir
->info
.num_ssbos
- 1);
3946 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3949 unsigned writemask
= instr
->const_index
[0];
3951 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3952 * since the untyped writes below operate in units of 32-bits, which
3953 * means that we need to write twice as many components each time.
3954 * Also, we have to suffle 64-bit data to be in the appropriate layout
3955 * expected by our 32-bit write messages.
3957 unsigned type_size
= 4;
3958 unsigned bit_size
= instr
->src
[0].is_ssa
?
3959 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3960 if (bit_size
== 64) {
3963 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3964 shuffle_64bit_data_for_32bit_write(bld
,
3965 retype(tmp
, BRW_REGISTER_TYPE_F
),
3966 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3967 instr
->num_components
);
3971 unsigned type_slots
= type_size
/ 4;
3973 /* Combine groups of consecutive enabled channels in one write
3974 * message. We use ffs to find the first enabled channel and then ffs on
3975 * the bit-inverse, down-shifted writemask to determine the length of
3976 * the block of enabled bits.
3979 unsigned first_component
= ffs(writemask
) - 1;
3980 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3982 /* We can't write more than 2 64-bit components at once. Limit the
3983 * length of the write to what we can do and let the next iteration
3987 length
= MIN2(2, length
);
3990 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
3992 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
3993 type_size
* first_component
);
3995 offset_reg
= vgrf(glsl_type::uint_type
);
3997 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
3998 brw_imm_ud(type_size
* first_component
));
4002 emit_untyped_write(bld
, surf_index
, offset_reg
,
4003 offset(val_reg
, bld
, first_component
* type_slots
),
4004 1 /* dims */, length
* type_slots
,
4005 BRW_PREDICATE_NONE
);
4007 /* Clear the bits in the writemask that we just wrote, then try
4008 * again to see if more channels are left.
4010 writemask
&= (15 << (first_component
+ length
));
4015 case nir_intrinsic_store_output
: {
4016 fs_reg src
= get_nir_src(instr
->src
[0]);
4018 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4019 assert(const_offset
&& "Indirect output stores not allowed");
4020 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4021 4 * const_offset
->u32
[0]), src
.type
);
4023 unsigned num_components
= instr
->num_components
;
4024 unsigned first_component
= nir_intrinsic_component(instr
);
4025 unsigned bit_size
= instr
->src
[0].is_ssa
?
4026 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4027 if (bit_size
== 64) {
4029 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4030 BRW_REGISTER_TYPE_F
);
4031 shuffle_64bit_data_for_32bit_write(
4032 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4033 src
= retype(tmp
, src
.type
);
4034 num_components
*= 2;
4037 for (unsigned j
= 0; j
< num_components
; j
++) {
4038 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4039 offset(src
, bld
, j
));
4044 case nir_intrinsic_ssbo_atomic_add
:
4045 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4047 case nir_intrinsic_ssbo_atomic_imin
:
4048 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4050 case nir_intrinsic_ssbo_atomic_umin
:
4051 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4053 case nir_intrinsic_ssbo_atomic_imax
:
4054 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4056 case nir_intrinsic_ssbo_atomic_umax
:
4057 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4059 case nir_intrinsic_ssbo_atomic_and
:
4060 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4062 case nir_intrinsic_ssbo_atomic_or
:
4063 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4065 case nir_intrinsic_ssbo_atomic_xor
:
4066 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4068 case nir_intrinsic_ssbo_atomic_exchange
:
4069 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4071 case nir_intrinsic_ssbo_atomic_comp_swap
:
4072 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4075 case nir_intrinsic_get_buffer_size
: {
4076 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4077 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4079 /* A resinfo's sampler message is used to get the buffer size. The
4080 * SIMD8's writeback message consists of four registers and SIMD16's
4081 * writeback message consists of 8 destination registers (two per each
4082 * component). Because we are only interested on the first channel of
4083 * the first returned component, where resinfo returns the buffer size
4084 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4085 * the dispatch width.
4087 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4088 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4089 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4092 ubld
.MOV(src_payload
, brw_imm_d(0));
4094 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4095 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4096 src_payload
, brw_imm_ud(index
));
4097 inst
->header_size
= 0;
4099 inst
->size_written
= 4 * REG_SIZE
;
4101 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4102 brw_mark_surface_used(prog_data
, index
);
4106 case nir_intrinsic_load_channel_num
: {
4107 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4108 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4109 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4110 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4111 if (dispatch_width
> 8)
4112 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4113 if (dispatch_width
> 16) {
4114 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4115 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4121 case nir_intrinsic_vote_any
: {
4122 const fs_builder ubld
= bld
.exec_all();
4124 /* The any/all predicates do not consider channel enables. To prevent
4125 * dead channels from affecting the result, we initialize the flag with
4126 * with the identity value for the logical operation.
4128 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4129 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4130 bld
.MOV(dest
, brw_imm_d(-1));
4131 set_predicate(dispatch_width
== 8 ?
4132 BRW_PREDICATE_ALIGN1_ANY8H
:
4133 BRW_PREDICATE_ALIGN1_ANY16H
,
4134 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4137 case nir_intrinsic_vote_all
: {
4138 const fs_builder ubld
= bld
.exec_all();
4140 /* The any/all predicates do not consider channel enables. To prevent
4141 * dead channels from affecting the result, we initialize the flag with
4142 * with the identity value for the logical operation.
4144 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4145 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4146 bld
.MOV(dest
, brw_imm_d(-1));
4147 set_predicate(dispatch_width
== 8 ?
4148 BRW_PREDICATE_ALIGN1_ALL8H
:
4149 BRW_PREDICATE_ALIGN1_ALL16H
,
4150 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4153 case nir_intrinsic_vote_eq
: {
4154 fs_reg value
= get_nir_src(instr
->src
[0]);
4155 fs_reg uniformized
= bld
.emit_uniformize(value
);
4156 const fs_builder ubld
= bld
.exec_all();
4158 /* The any/all predicates do not consider channel enables. To prevent
4159 * dead channels from affecting the result, we initialize the flag with
4160 * with the identity value for the logical operation.
4162 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4163 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4164 bld
.MOV(dest
, brw_imm_d(-1));
4165 set_predicate(dispatch_width
== 8 ?
4166 BRW_PREDICATE_ALIGN1_ALL8H
:
4167 BRW_PREDICATE_ALIGN1_ALL16H
,
4168 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4172 unreachable("unknown intrinsic");
4177 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4178 int op
, nir_intrinsic_instr
*instr
)
4180 if (stage
== MESA_SHADER_FRAGMENT
)
4181 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4184 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4185 dest
= get_nir_dest(instr
->dest
);
4188 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4189 if (const_surface
) {
4190 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4191 const_surface
->u32
[0];
4192 surface
= brw_imm_ud(surf_index
);
4193 brw_mark_surface_used(prog_data
, surf_index
);
4195 surface
= vgrf(glsl_type::uint_type
);
4196 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4197 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4199 /* Assume this may touch any SSBO. This is the same we do for other
4200 * UBO/SSBO accesses with non-constant surface.
4202 brw_mark_surface_used(prog_data
,
4203 stage_prog_data
->binding_table
.ssbo_start
+
4204 nir
->info
.num_ssbos
- 1);
4207 fs_reg offset
= get_nir_src(instr
->src
[1]);
4208 fs_reg data1
= get_nir_src(instr
->src
[2]);
4210 if (op
== BRW_AOP_CMPWR
)
4211 data2
= get_nir_src(instr
->src
[3]);
4213 /* Emit the actual atomic operation */
4215 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4217 1 /* dims */, 1 /* rsize */,
4219 BRW_PREDICATE_NONE
);
4220 dest
.type
= atomic_result
.type
;
4221 bld
.MOV(dest
, atomic_result
);
4225 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4226 int op
, nir_intrinsic_instr
*instr
)
4229 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4230 dest
= get_nir_dest(instr
->dest
);
4232 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4234 fs_reg data1
= get_nir_src(instr
->src
[1]);
4236 if (op
== BRW_AOP_CMPWR
)
4237 data2
= get_nir_src(instr
->src
[2]);
4239 /* Get the offset */
4240 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4242 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4244 offset
= vgrf(glsl_type::uint_type
);
4246 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4247 brw_imm_ud(instr
->const_index
[0]));
4250 /* Emit the actual atomic operation operation */
4252 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4254 1 /* dims */, 1 /* rsize */,
4256 BRW_PREDICATE_NONE
);
4257 dest
.type
= atomic_result
.type
;
4258 bld
.MOV(dest
, atomic_result
);
4262 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4264 unsigned texture
= instr
->texture_index
;
4265 unsigned sampler
= instr
->sampler_index
;
4267 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4269 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4270 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4272 int lod_components
= 0;
4274 /* The hardware requires a LOD for buffer textures */
4275 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4276 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4278 uint32_t header_bits
= 0;
4279 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4280 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4281 switch (instr
->src
[i
].src_type
) {
4282 case nir_tex_src_bias
:
4283 srcs
[TEX_LOGICAL_SRC_LOD
] =
4284 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4286 case nir_tex_src_comparator
:
4287 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4289 case nir_tex_src_coord
:
4290 switch (instr
->op
) {
4292 case nir_texop_txf_ms
:
4293 case nir_texop_txf_ms_mcs
:
4294 case nir_texop_samples_identical
:
4295 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4298 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4302 case nir_tex_src_ddx
:
4303 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4304 lod_components
= nir_tex_instr_src_size(instr
, i
);
4306 case nir_tex_src_ddy
:
4307 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4309 case nir_tex_src_lod
:
4310 switch (instr
->op
) {
4312 srcs
[TEX_LOGICAL_SRC_LOD
] =
4313 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4316 srcs
[TEX_LOGICAL_SRC_LOD
] =
4317 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4320 srcs
[TEX_LOGICAL_SRC_LOD
] =
4321 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4325 case nir_tex_src_ms_index
:
4326 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4329 case nir_tex_src_offset
: {
4330 nir_const_value
*const_offset
=
4331 nir_src_as_const_value(instr
->src
[i
].src
);
4332 unsigned offset_bits
= 0;
4334 brw_texture_offset(const_offset
->i32
,
4335 nir_tex_instr_src_size(instr
, i
),
4337 header_bits
|= offset_bits
;
4339 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4340 retype(src
, BRW_REGISTER_TYPE_D
);
4345 case nir_tex_src_projector
:
4346 unreachable("should be lowered");
4348 case nir_tex_src_texture_offset
: {
4349 /* Figure out the highest possible texture index and mark it as used */
4350 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4351 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4352 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4354 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4356 brw_mark_surface_used(prog_data
, max_used
);
4358 /* Emit code to evaluate the actual indexing expression */
4359 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4360 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4361 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4365 case nir_tex_src_sampler_offset
: {
4366 /* Emit code to evaluate the actual indexing expression */
4367 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4368 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4369 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4373 case nir_tex_src_ms_mcs
:
4374 assert(instr
->op
== nir_texop_txf_ms
);
4375 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4378 case nir_tex_src_plane
: {
4379 nir_const_value
*const_plane
=
4380 nir_src_as_const_value(instr
->src
[i
].src
);
4381 const uint32_t plane
= const_plane
->u32
[0];
4382 const uint32_t texture_index
=
4383 instr
->texture_index
+
4384 stage_prog_data
->binding_table
.plane_start
[plane
] -
4385 stage_prog_data
->binding_table
.texture_start
;
4387 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4392 unreachable("unknown texture source");
4396 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4397 (instr
->op
== nir_texop_txf_ms
||
4398 instr
->op
== nir_texop_samples_identical
)) {
4399 if (devinfo
->gen
>= 7 &&
4400 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4401 srcs
[TEX_LOGICAL_SRC_MCS
] =
4402 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4403 instr
->coord_components
,
4404 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4406 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4410 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4411 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4414 switch (instr
->op
) {
4416 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4417 SHADER_OPCODE_TXL_LOGICAL
);
4420 opcode
= FS_OPCODE_TXB_LOGICAL
;
4423 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4426 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4429 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4431 case nir_texop_txf_ms
:
4432 if ((key_tex
->msaa_16
& (1 << sampler
)))
4433 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4435 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4437 case nir_texop_txf_ms_mcs
:
4438 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4440 case nir_texop_query_levels
:
4442 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4445 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4448 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4449 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4451 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4453 case nir_texop_texture_samples
:
4454 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4456 case nir_texop_samples_identical
: {
4457 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4459 /* If mcs is an immediate value, it means there is no MCS. In that case
4460 * just return false.
4462 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4463 bld
.MOV(dst
, brw_imm_ud(0u));
4464 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4465 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4466 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4467 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4468 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4470 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4471 BRW_CONDITIONAL_EQ
);
4476 unreachable("unknown texture opcode");
4479 /* TXS and TXL require a LOD but not everything we implement using those
4480 * two opcodes provides one. Provide a default LOD of 0.
4482 if ((opcode
== SHADER_OPCODE_TXS_LOGICAL
||
4483 opcode
== SHADER_OPCODE_TXL_LOGICAL
) &&
4484 srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
) {
4485 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4488 if (instr
->op
== nir_texop_tg4
) {
4489 if (instr
->component
== 1 &&
4490 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4491 /* gather4 sampler is broken for green channel on RG32F --
4492 * we must ask for blue instead.
4494 header_bits
|= 2 << 16;
4496 header_bits
|= instr
->component
<< 16;
4500 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4501 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4502 inst
->offset
= header_bits
;
4504 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4505 if (devinfo
->gen
>= 9 &&
4506 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4507 unsigned write_mask
= instr
->dest
.is_ssa
?
4508 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4509 (1 << dest_size
) - 1;
4510 assert(write_mask
!= 0); /* dead code should have been eliminated */
4511 inst
->size_written
= util_last_bit(write_mask
) *
4512 inst
->dst
.component_size(inst
->exec_size
);
4514 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4517 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4518 inst
->shadow_compare
= true;
4520 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4521 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4524 for (unsigned i
= 0; i
< dest_size
; i
++)
4525 nir_dest
[i
] = offset(dst
, bld
, i
);
4527 if (instr
->op
== nir_texop_query_levels
) {
4528 /* # levels is in .w */
4529 nir_dest
[0] = offset(dst
, bld
, 3);
4530 } else if (instr
->op
== nir_texop_txs
&&
4531 dest_size
>= 3 && devinfo
->gen
< 7) {
4532 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4533 fs_reg depth
= offset(dst
, bld
, 2);
4534 nir_dest
[2] = vgrf(glsl_type::int_type
);
4535 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4538 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4542 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4544 switch (instr
->type
) {
4545 case nir_jump_break
:
4546 bld
.emit(BRW_OPCODE_BREAK
);
4548 case nir_jump_continue
:
4549 bld
.emit(BRW_OPCODE_CONTINUE
);
4551 case nir_jump_return
:
4553 unreachable("unknown jump");
4558 * This helper takes the result of a load operation that reads 32-bit elements
4566 * and shuffles the data to get this:
4573 * Which is exactly what we want if the load is reading 64-bit components
4574 * like doubles, where x represents the low 32-bit of the x double component
4575 * and y represents the high 32-bit of the x double component (likewise with
4576 * z and w for double component y). The parameter @components represents
4577 * the number of 64-bit components present in @src. This would typically be
4578 * 2 at most, since we can only fit 2 double elements in the result of a
4581 * Notice that @dst and @src can be the same register.
4584 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4587 uint32_t components
)
4589 assert(type_sz(src
.type
) == 4);
4590 assert(type_sz(dst
.type
) == 8);
4592 /* A temporary that we will use to shuffle the 32-bit data of each
4593 * component in the vector into valid 64-bit data. We can't write directly
4594 * to dst because dst can be (and would usually be) the same as src
4595 * and in that case the first MOV in the loop below would overwrite the
4596 * data read in the second MOV.
4598 fs_reg tmp
= bld
.vgrf(dst
.type
);
4600 for (unsigned i
= 0; i
< components
; i
++) {
4601 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4603 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4604 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4606 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4611 * This helper does the inverse operation of
4612 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4614 * We need to do this when we are going to use untyped write messsages that
4615 * operate with 32-bit components in order to arrange our 64-bit data to be
4616 * in the expected layout.
4618 * Notice that callers of this function, unlike in the case of the inverse
4619 * operation, would typically need to call this with dst and src being
4620 * different registers, since they would otherwise corrupt the original
4621 * 64-bit data they are about to write. Because of this the function checks
4622 * that the src and dst regions involved in the operation do not overlap.
4625 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4628 uint32_t components
)
4630 assert(type_sz(src
.type
) == 8);
4631 assert(type_sz(dst
.type
) == 4);
4633 assert(!regions_overlap(
4634 dst
, 2 * components
* dst
.component_size(bld
.dispatch_width()),
4635 src
, components
* src
.component_size(bld
.dispatch_width())));
4637 for (unsigned i
= 0; i
< components
; i
++) {
4638 const fs_reg component_i
= offset(src
, bld
, i
);
4639 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4640 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4645 setup_imm_df(const fs_builder
&bld
, double v
)
4647 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4648 assert(devinfo
->gen
>= 7);
4650 if (devinfo
->gen
>= 8)
4651 return brw_imm_df(v
);
4653 /* gen7.5 does not support DF immediates straighforward but the DIM
4654 * instruction allows to set the 64-bit immediate value.
4656 if (devinfo
->is_haswell
) {
4657 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4658 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4659 ubld
.DIM(dst
, brw_imm_df(v
));
4660 return component(dst
, 0);
4663 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4664 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4665 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4667 * Alternatively, we could also produce a normal VGRF (without stride 0)
4668 * by writing to all the channels in the VGRF, however, that would hit the
4669 * gen7 bug where we have to split writes that span more than 1 register
4670 * into instructions with a width of 4 (otherwise the write to the second
4671 * register written runs into an execmask hardware bug) which isn't very
4684 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4685 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4686 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4687 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4689 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);