2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "util/u_math.h"
29 #include "util/bitscan.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
48 fs_visitor::nir_setup_outputs()
50 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
53 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
55 /* Calculate the size of output registers in a separate pass, before
56 * allocating them. With ARB_enhanced_layouts, multiple output variables
57 * may occupy the same slot, but have different type sizes.
59 nir_foreach_variable(var
, &nir
->outputs
) {
60 const int loc
= var
->data
.driver_location
;
61 const unsigned var_vec4s
=
62 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
63 : type_size_vec4(var
->type
);
64 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
67 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
68 if (vec4s
[loc
] == 0) {
73 unsigned reg_size
= vec4s
[loc
];
75 /* Check if there are any ranges that start within this range and extend
76 * past it. If so, include them in this allocation.
78 for (unsigned i
= 1; i
< reg_size
; i
++)
79 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
81 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
82 for (unsigned i
= 0; i
< reg_size
; i
++)
83 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
90 fs_visitor::nir_setup_uniforms()
92 /* Only the first compile gets to set up uniforms. */
93 if (push_constant_loc
) {
94 assert(pull_constant_loc
);
98 uniforms
= nir
->num_uniforms
/ 4;
100 if (stage
== MESA_SHADER_COMPUTE
) {
101 /* Add a uniform for the thread local id. It must be the last uniform
104 assert(uniforms
== prog_data
->nr_params
);
105 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
106 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
107 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
112 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
116 nir_foreach_instr(instr
, block
) {
117 if (instr
->type
!= nir_instr_type_intrinsic
)
120 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
121 switch (intrin
->intrinsic
) {
122 case nir_intrinsic_load_vertex_id
:
123 case nir_intrinsic_load_base_vertex
:
124 unreachable("should be lowered by nir_lower_system_values().");
126 case nir_intrinsic_load_vertex_id_zero_base
:
127 case nir_intrinsic_load_is_indexed_draw
:
128 case nir_intrinsic_load_first_vertex
:
129 case nir_intrinsic_load_instance_id
:
130 case nir_intrinsic_load_base_instance
:
131 case nir_intrinsic_load_draw_id
:
132 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
134 case nir_intrinsic_load_invocation_id
:
135 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
137 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
138 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
139 if (reg
->file
== BAD_FILE
) {
140 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
141 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
142 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
143 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
148 case nir_intrinsic_load_sample_pos
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_samplepos_setup();
155 case nir_intrinsic_load_sample_id
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_sampleid_setup();
162 case nir_intrinsic_load_sample_mask_in
:
163 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
164 assert(v
->devinfo
->gen
>= 7);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplemaskin_setup();
170 case nir_intrinsic_load_work_group_id
:
171 assert(v
->stage
== MESA_SHADER_COMPUTE
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_cs_work_group_id_setup();
177 case nir_intrinsic_load_helper_invocation
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
180 if (reg
->file
== BAD_FILE
) {
181 const fs_builder abld
=
182 v
->bld
.annotate("gl_HelperInvocation", NULL
);
184 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
185 * pixel mask is in g1.7 of the thread payload.
187 * We move the per-channel pixel enable bit to the low bit of each
188 * channel by shifting the byte containing the pixel mask by the
189 * vector immediate 0x76543210UV.
191 * The region of <1,8,0> reads only 1 byte (the pixel masks for
192 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
193 * masks for 2 and 3) in SIMD16.
195 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
197 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
198 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
199 hbld
.SHR(offset(shifted
, hbld
, i
),
200 stride(retype(brw_vec1_grf(1 + i
, 7),
201 BRW_REGISTER_TYPE_UB
),
203 brw_imm_v(0x76543210));
206 /* A set bit in the pixel mask means the channel is enabled, but
207 * that is the opposite of gl_HelperInvocation so we need to invert
210 * The negate source-modifier bit of logical instructions on Gen8+
211 * performs 1's complement negation, so we can use that instead of
214 fs_reg inverted
= negate(shifted
);
215 if (v
->devinfo
->gen
< 8) {
216 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
217 abld
.NOT(inverted
, shifted
);
220 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
221 * with 1 and negating.
223 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
224 abld
.AND(anded
, inverted
, brw_imm_uw(1));
226 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
227 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
241 fs_visitor::nir_emit_system_values()
243 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
244 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
245 nir_system_values
[i
] = fs_reg();
248 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
249 * never end up using it.
252 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
253 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
254 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
256 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
257 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
258 if (dispatch_width
> 8)
259 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
260 if (dispatch_width
> 16) {
261 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
262 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
266 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
267 nir_foreach_block(block
, impl
)
268 emit_system_values_block(block
, this);
272 * Returns a type based on a reference_type (word, float, half-float) and a
275 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
277 * @FIXME: 64-bit return types are always DF on integer types to maintain
278 * compability with uses of DF previously to the introduction of int64
282 brw_reg_type_from_bit_size(const unsigned bit_size
,
283 const brw_reg_type reference_type
)
285 switch(reference_type
) {
286 case BRW_REGISTER_TYPE_HF
:
287 case BRW_REGISTER_TYPE_F
:
288 case BRW_REGISTER_TYPE_DF
:
291 return BRW_REGISTER_TYPE_HF
;
293 return BRW_REGISTER_TYPE_F
;
295 return BRW_REGISTER_TYPE_DF
;
297 unreachable("Invalid bit size");
299 case BRW_REGISTER_TYPE_B
:
300 case BRW_REGISTER_TYPE_W
:
301 case BRW_REGISTER_TYPE_D
:
302 case BRW_REGISTER_TYPE_Q
:
305 return BRW_REGISTER_TYPE_B
;
307 return BRW_REGISTER_TYPE_W
;
309 return BRW_REGISTER_TYPE_D
;
311 return BRW_REGISTER_TYPE_Q
;
313 unreachable("Invalid bit size");
315 case BRW_REGISTER_TYPE_UB
:
316 case BRW_REGISTER_TYPE_UW
:
317 case BRW_REGISTER_TYPE_UD
:
318 case BRW_REGISTER_TYPE_UQ
:
321 return BRW_REGISTER_TYPE_UB
;
323 return BRW_REGISTER_TYPE_UW
;
325 return BRW_REGISTER_TYPE_UD
;
327 return BRW_REGISTER_TYPE_UQ
;
329 unreachable("Invalid bit size");
332 unreachable("Unknown type");
337 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
339 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
340 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
341 nir_locals
[i
] = fs_reg();
344 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
345 unsigned array_elems
=
346 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
347 unsigned size
= array_elems
* reg
->num_components
;
348 const brw_reg_type reg_type
=
349 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
350 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
353 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
356 nir_emit_cf_list(&impl
->body
);
360 fs_visitor::nir_emit_cf_list(exec_list
*list
)
362 exec_list_validate(list
);
363 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
364 switch (node
->type
) {
366 nir_emit_if(nir_cf_node_as_if(node
));
369 case nir_cf_node_loop
:
370 nir_emit_loop(nir_cf_node_as_loop(node
));
373 case nir_cf_node_block
:
374 nir_emit_block(nir_cf_node_as_block(node
));
378 unreachable("Invalid CFG node block");
384 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
386 /* first, put the condition into f0 */
387 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
388 retype(get_nir_src(if_stmt
->condition
),
389 BRW_REGISTER_TYPE_D
));
390 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
392 bld
.IF(BRW_PREDICATE_NORMAL
);
394 nir_emit_cf_list(&if_stmt
->then_list
);
396 /* note: if the else is empty, dead CF elimination will remove it */
397 bld
.emit(BRW_OPCODE_ELSE
);
399 nir_emit_cf_list(&if_stmt
->else_list
);
401 bld
.emit(BRW_OPCODE_ENDIF
);
403 if (devinfo
->gen
< 7)
404 limit_dispatch_width(16, "Non-uniform control flow unsupported "
409 fs_visitor::nir_emit_loop(nir_loop
*loop
)
411 bld
.emit(BRW_OPCODE_DO
);
413 nir_emit_cf_list(&loop
->body
);
415 bld
.emit(BRW_OPCODE_WHILE
);
417 if (devinfo
->gen
< 7)
418 limit_dispatch_width(16, "Non-uniform control flow unsupported "
423 fs_visitor::nir_emit_block(nir_block
*block
)
425 nir_foreach_instr(instr
, block
) {
426 nir_emit_instr(instr
);
431 fs_visitor::nir_emit_instr(nir_instr
*instr
)
433 const fs_builder abld
= bld
.annotate(NULL
, instr
);
435 switch (instr
->type
) {
436 case nir_instr_type_alu
:
437 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
440 case nir_instr_type_deref
:
441 /* Derefs can exist for images but they do nothing */
444 case nir_instr_type_intrinsic
:
446 case MESA_SHADER_VERTEX
:
447 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
449 case MESA_SHADER_TESS_CTRL
:
450 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
452 case MESA_SHADER_TESS_EVAL
:
453 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
455 case MESA_SHADER_GEOMETRY
:
456 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
458 case MESA_SHADER_FRAGMENT
:
459 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
461 case MESA_SHADER_COMPUTE
:
462 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 unreachable("unsupported shader stage");
469 case nir_instr_type_tex
:
470 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
473 case nir_instr_type_load_const
:
474 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
477 case nir_instr_type_ssa_undef
:
478 /* We create a new VGRF for undefs on every use (by handling
479 * them in get_nir_src()), rather than for each definition.
480 * This helps register coalescing eliminate MOVs from undef.
484 case nir_instr_type_jump
:
485 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
489 unreachable("unknown instruction type");
494 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
498 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
499 const fs_reg
&result
)
501 if (!instr
->src
[0].src
.is_ssa
||
502 !instr
->src
[0].src
.ssa
->parent_instr
)
505 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
508 nir_alu_instr
*src0
=
509 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
511 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
512 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
515 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
517 /* Element type to extract.*/
518 const brw_reg_type type
= brw_int_type(
519 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
520 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
522 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
523 op0
.type
= brw_type_for_nir_type(devinfo
,
524 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
525 nir_src_bit_size(src0
->src
[0].src
)));
526 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
528 set_saturate(instr
->dest
.saturate
,
529 bld
.MOV(result
, subscript(op0
, type
, element
)));
534 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
535 const fs_reg
&result
)
537 if (!instr
->src
[0].src
.is_ssa
||
538 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
541 nir_intrinsic_instr
*src0
=
542 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
544 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
547 if (!nir_src_is_const(instr
->src
[1].src
) ||
548 !nir_src_is_const(instr
->src
[2].src
))
551 const float value1
= nir_src_as_float(instr
->src
[1].src
);
552 const float value2
= nir_src_as_float(instr
->src
[2].src
);
553 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
556 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
557 assert(value1
== -value2
);
559 fs_reg tmp
= vgrf(glsl_type::int_type
);
561 if (devinfo
->gen
>= 6) {
562 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
563 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
565 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
567 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
568 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
570 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
572 * This negation looks like it's safe in practice, because bits 0:4 will
573 * surely be TRIANGLES
576 if (value1
== -1.0f
) {
580 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
581 g0
, brw_imm_uw(0x3f80));
583 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
584 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
586 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
588 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
589 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
591 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
593 * This negation looks like it's safe in practice, because bits 0:4 will
594 * surely be TRIANGLES
597 if (value1
== -1.0f
) {
601 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
603 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
609 emit_find_msb_using_lzd(const fs_builder
&bld
,
610 const fs_reg
&result
,
618 /* LZD of an absolute value source almost always does the right
619 * thing. There are two problem values:
621 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
622 * 0. However, findMSB(int(0x80000000)) == 30.
624 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
625 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
627 * For a value of zero or negative one, -1 will be returned.
629 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
630 * findMSB(-(1<<x)) should return x-1.
632 * For all negative number cases, including 0x80000000 and
633 * 0xffffffff, the correct value is obtained from LZD if instead of
634 * negating the (already negative) value the logical-not is used. A
635 * conditonal logical-not can be achieved in two instructions.
637 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
639 bld
.ASR(temp
, src
, brw_imm_d(31));
640 bld
.XOR(temp
, temp
, src
);
643 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
644 retype(temp
, BRW_REGISTER_TYPE_UD
));
646 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
647 * from the LSB side. Subtract the result from 31 to convert the MSB
648 * count into an LSB count. If no bits are set, LZD will return 32.
649 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
651 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
652 inst
->src
[0].negate
= true;
656 brw_rnd_mode_from_nir_op (const nir_op op
) {
658 case nir_op_f2f16_rtz
:
659 return BRW_RND_MODE_RTZ
;
660 case nir_op_f2f16_rtne
:
661 return BRW_RND_MODE_RTNE
;
663 unreachable("Operation doesn't support rounding mode");
668 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
670 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
673 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
674 result
.type
= brw_type_for_nir_type(devinfo
,
675 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
676 nir_dest_bit_size(instr
->dest
.dest
)));
679 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
680 op
[i
] = get_nir_src(instr
->src
[i
].src
);
681 op
[i
].type
= brw_type_for_nir_type(devinfo
,
682 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
683 nir_src_bit_size(instr
->src
[i
].src
)));
684 op
[i
].abs
= instr
->src
[i
].abs
;
685 op
[i
].negate
= instr
->src
[i
].negate
;
688 /* We get a bunch of mov's out of the from_ssa pass and they may still
689 * be vectorized. We'll handle them as a special-case. We'll also
690 * handle vecN here because it's basically the same thing.
698 fs_reg temp
= result
;
699 bool need_extra_copy
= false;
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 if (!instr
->src
[i
].src
.is_ssa
&&
702 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
703 need_extra_copy
= true;
704 temp
= bld
.vgrf(result
.type
, 4);
709 for (unsigned i
= 0; i
< 4; i
++) {
710 if (!(instr
->dest
.write_mask
& (1 << i
)))
713 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
714 inst
= bld
.MOV(offset(temp
, bld
, i
),
715 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
717 inst
= bld
.MOV(offset(temp
, bld
, i
),
718 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
720 inst
->saturate
= instr
->dest
.saturate
;
723 /* In this case the source and destination registers were the same,
724 * so we need to insert an extra set of moves in order to deal with
727 if (need_extra_copy
) {
728 for (unsigned i
= 0; i
< 4; i
++) {
729 if (!(instr
->dest
.write_mask
& (1 << i
)))
732 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
741 /* At this point, we have dealt with any instruction that operates on
742 * more than a single channel. Therefore, we can just adjust the source
743 * and destination registers for that channel and emit the instruction.
745 unsigned channel
= 0;
746 if (nir_op_infos
[instr
->op
].output_size
== 0) {
747 /* Since NIR is doing the scalarizing for us, we should only ever see
748 * vectorized operations with a single channel.
750 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
751 channel
= ffs(instr
->dest
.write_mask
) - 1;
753 result
= offset(result
, bld
, channel
);
756 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
757 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
758 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
764 if (optimize_extract_to_float(instr
, result
))
766 inst
= bld
.MOV(result
, op
[0]);
767 inst
->saturate
= instr
->dest
.saturate
;
770 case nir_op_f2f16_rtne
:
771 case nir_op_f2f16_rtz
:
772 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
773 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
776 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
777 * on the HW gen, it is a special hw opcode or just a MOV, and
778 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
780 * But if we want to use that opcode, we need to provide support on
781 * different optimizations and lowerings. As right now HF support is
782 * only for gen8+, it will be better to use directly the MOV, and use
783 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
787 inst
= bld
.MOV(result
, op
[0]);
788 inst
->saturate
= instr
->dest
.saturate
;
798 op
[0].type
= BRW_REGISTER_TYPE_D
;
799 op
[0].negate
= !op
[0].negate
;
808 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
810 * "When source or destination is 64b (...), regioning in Align1
811 * must follow these rules:
813 * 1. Source and destination horizontal stride must be aligned to
817 * This means that conversions from bit-sizes smaller than 64-bit to
818 * 64-bit need to have the source data elements aligned to 64-bit.
819 * This restriction does not apply to BDW and later.
821 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
822 nir_src_bit_size(instr
->src
[0].src
) < 64 &&
823 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
824 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
825 tmp
= subscript(tmp
, op
[0].type
, 0);
826 inst
= bld
.MOV(tmp
, op
[0]);
827 inst
= bld
.MOV(result
, tmp
);
828 inst
->saturate
= instr
->dest
.saturate
;
845 inst
= bld
.MOV(result
, op
[0]);
846 inst
->saturate
= instr
->dest
.saturate
;
850 assert(!instr
->dest
.saturate
);
852 /* Straightforward since the source can be assumed to be either
853 * strictly >= 0 or strictly <= 0 depending on the setting of the
856 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
858 inst
= (op
[0].negate
)
859 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
860 : bld
.MOV(result
, brw_imm_f(1.0f
));
862 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
863 } else if (type_sz(op
[0].type
) < 8) {
864 /* AND(val, 0x80000000) gives the sign bit.
866 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
869 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
871 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
872 op
[0].type
= BRW_REGISTER_TYPE_UD
;
873 result
.type
= BRW_REGISTER_TYPE_UD
;
874 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
876 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
877 inst
->predicate
= BRW_PREDICATE_NORMAL
;
879 /* For doubles we do the same but we need to consider:
881 * - 2-src instructions can't operate with 64-bit immediates
882 * - The sign is encoded in the high 32-bit of each DF
883 * - We need to produce a DF result.
886 fs_reg zero
= vgrf(glsl_type::double_type
);
887 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
888 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
890 bld
.MOV(result
, zero
);
892 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
893 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
894 brw_imm_ud(0x80000000u
));
896 set_predicate(BRW_PREDICATE_NORMAL
,
897 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
903 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
904 * -> non-negative val generates 0x00000000.
905 * Predicated OR sets 1 if val is positive.
907 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
908 assert(bit_size
== 32 || bit_size
== 16);
910 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
911 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
912 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
914 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
915 bld
.ASR(result
, op
[0], shift
);
916 inst
= bld
.OR(result
, result
, one
);
917 inst
->predicate
= BRW_PREDICATE_NORMAL
;
922 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
923 inst
->saturate
= instr
->dest
.saturate
;
927 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
928 inst
->saturate
= instr
->dest
.saturate
;
932 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
933 inst
->saturate
= instr
->dest
.saturate
;
937 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
938 inst
->saturate
= instr
->dest
.saturate
;
942 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
943 inst
->saturate
= instr
->dest
.saturate
;
947 if (fs_key
->high_quality_derivatives
) {
948 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
950 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
952 inst
->saturate
= instr
->dest
.saturate
;
954 case nir_op_fddx_fine
:
955 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
956 inst
->saturate
= instr
->dest
.saturate
;
958 case nir_op_fddx_coarse
:
959 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
960 inst
->saturate
= instr
->dest
.saturate
;
963 if (fs_key
->high_quality_derivatives
) {
964 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
966 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
968 inst
->saturate
= instr
->dest
.saturate
;
970 case nir_op_fddy_fine
:
971 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
972 inst
->saturate
= instr
->dest
.saturate
;
974 case nir_op_fddy_coarse
:
975 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
976 inst
->saturate
= instr
->dest
.saturate
;
981 inst
= bld
.ADD(result
, op
[0], op
[1]);
982 inst
->saturate
= instr
->dest
.saturate
;
985 case nir_op_uadd_sat
:
986 inst
= bld
.ADD(result
, op
[0], op
[1]);
987 inst
->saturate
= true;
991 inst
= bld
.MUL(result
, op
[0], op
[1]);
992 inst
->saturate
= instr
->dest
.saturate
;
996 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
997 bld
.MUL(result
, op
[0], op
[1]);
1000 case nir_op_imul_high
:
1001 case nir_op_umul_high
:
1002 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1003 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1008 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1009 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1012 case nir_op_uadd_carry
:
1013 unreachable("Should have been lowered by carry_to_arith().");
1015 case nir_op_usub_borrow
:
1016 unreachable("Should have been lowered by borrow_to_arith().");
1020 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1021 * appears that our hardware just does the right thing for signed
1024 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1025 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1029 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1030 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1032 /* Math instructions don't support conditional mod */
1033 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1034 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1036 /* Now, we need to determine if signs of the sources are different.
1037 * When we XOR the sources, the top bit is 0 if they are the same and 1
1038 * if they are different. We can then use a conditional modifier to
1039 * turn that into a predicate. This leads us to an XOR.l instruction.
1041 * Technically, according to the PRM, you're not allowed to use .l on a
1042 * XOR instruction. However, emperical experiments and Curro's reading
1043 * of the simulator source both indicate that it's safe.
1045 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1046 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1047 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1048 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1050 /* If the result of the initial remainder operation is non-zero and the
1051 * two sources have different signs, add in a copy of op[1] to get the
1052 * final integer modulus value.
1054 inst
= bld
.ADD(result
, result
, op
[1]);
1055 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1063 fs_reg dest
= result
;
1065 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1067 dest
= bld
.vgrf(op
[0].type
, 1);
1069 brw_conditional_mod cond
;
1070 switch (instr
->op
) {
1072 cond
= BRW_CONDITIONAL_L
;
1075 cond
= BRW_CONDITIONAL_GE
;
1078 cond
= BRW_CONDITIONAL_Z
;
1081 cond
= BRW_CONDITIONAL_NZ
;
1084 unreachable("bad opcode");
1087 bld
.CMP(dest
, op
[0], op
[1], cond
);
1089 if (bit_size
> 32) {
1090 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1091 } else if(bit_size
< 32) {
1092 /* When we convert the result to 32-bit we need to be careful and do
1093 * it as a signed conversion to get sign extension (for 32-bit true)
1095 const brw_reg_type src_type
=
1096 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1098 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1109 fs_reg dest
= result
;
1111 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1113 dest
= bld
.vgrf(op
[0].type
, 1);
1115 brw_conditional_mod cond
;
1116 switch (instr
->op
) {
1119 cond
= BRW_CONDITIONAL_L
;
1123 cond
= BRW_CONDITIONAL_GE
;
1126 cond
= BRW_CONDITIONAL_Z
;
1129 cond
= BRW_CONDITIONAL_NZ
;
1132 unreachable("bad opcode");
1134 bld
.CMP(dest
, op
[0], op
[1], cond
);
1136 if (bit_size
> 32) {
1137 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1138 } else if (bit_size
< 32) {
1139 /* When we convert the result to 32-bit we need to be careful and do
1140 * it as a signed conversion to get sign extension (for 32-bit true)
1142 const brw_reg_type src_type
=
1143 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1145 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1151 if (devinfo
->gen
>= 8) {
1152 op
[0] = resolve_source_modifiers(op
[0]);
1154 bld
.NOT(result
, op
[0]);
1157 if (devinfo
->gen
>= 8) {
1158 op
[0] = resolve_source_modifiers(op
[0]);
1159 op
[1] = resolve_source_modifiers(op
[1]);
1161 bld
.XOR(result
, op
[0], op
[1]);
1164 if (devinfo
->gen
>= 8) {
1165 op
[0] = resolve_source_modifiers(op
[0]);
1166 op
[1] = resolve_source_modifiers(op
[1]);
1168 bld
.OR(result
, op
[0], op
[1]);
1171 if (devinfo
->gen
>= 8) {
1172 op
[0] = resolve_source_modifiers(op
[0]);
1173 op
[1] = resolve_source_modifiers(op
[1]);
1175 bld
.AND(result
, op
[0], op
[1]);
1181 case nir_op_ball_fequal2
:
1182 case nir_op_ball_iequal2
:
1183 case nir_op_ball_fequal3
:
1184 case nir_op_ball_iequal3
:
1185 case nir_op_ball_fequal4
:
1186 case nir_op_ball_iequal4
:
1187 case nir_op_bany_fnequal2
:
1188 case nir_op_bany_inequal2
:
1189 case nir_op_bany_fnequal3
:
1190 case nir_op_bany_inequal3
:
1191 case nir_op_bany_fnequal4
:
1192 case nir_op_bany_inequal4
:
1193 unreachable("Lowered by nir_lower_alu_reductions");
1195 case nir_op_fnoise1_1
:
1196 case nir_op_fnoise1_2
:
1197 case nir_op_fnoise1_3
:
1198 case nir_op_fnoise1_4
:
1199 case nir_op_fnoise2_1
:
1200 case nir_op_fnoise2_2
:
1201 case nir_op_fnoise2_3
:
1202 case nir_op_fnoise2_4
:
1203 case nir_op_fnoise3_1
:
1204 case nir_op_fnoise3_2
:
1205 case nir_op_fnoise3_3
:
1206 case nir_op_fnoise3_4
:
1207 case nir_op_fnoise4_1
:
1208 case nir_op_fnoise4_2
:
1209 case nir_op_fnoise4_3
:
1210 case nir_op_fnoise4_4
:
1211 unreachable("not reached: should be handled by lower_noise");
1214 unreachable("not reached: should be handled by ldexp_to_arith()");
1217 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1218 inst
->saturate
= instr
->dest
.saturate
;
1222 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1223 inst
->saturate
= instr
->dest
.saturate
;
1227 case nir_op_f2b32
: {
1228 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1229 if (bit_size
== 64) {
1230 /* two-argument instructions can't take 64-bit immediates */
1234 if (instr
->op
== nir_op_f2b32
) {
1235 zero
= vgrf(glsl_type::double_type
);
1236 tmp
= vgrf(glsl_type::double_type
);
1237 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1239 zero
= vgrf(glsl_type::int64_t_type
);
1240 tmp
= vgrf(glsl_type::int64_t_type
);
1241 bld
.MOV(zero
, brw_imm_q(0));
1244 /* A SIMD16 execution needs to be split in two instructions, so use
1245 * a vgrf instead of the flag register as dst so instruction splitting
1248 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1249 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1252 if (bit_size
== 32) {
1253 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1255 assert(bit_size
== 16);
1256 zero
= instr
->op
== nir_op_f2b32
?
1257 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1259 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1265 inst
= bld
.RNDZ(result
, op
[0]);
1266 inst
->saturate
= instr
->dest
.saturate
;
1269 case nir_op_fceil
: {
1270 op
[0].negate
= !op
[0].negate
;
1271 fs_reg temp
= vgrf(glsl_type::float_type
);
1272 bld
.RNDD(temp
, op
[0]);
1274 inst
= bld
.MOV(result
, temp
);
1275 inst
->saturate
= instr
->dest
.saturate
;
1279 inst
= bld
.RNDD(result
, op
[0]);
1280 inst
->saturate
= instr
->dest
.saturate
;
1283 inst
= bld
.FRC(result
, op
[0]);
1284 inst
->saturate
= instr
->dest
.saturate
;
1286 case nir_op_fround_even
:
1287 inst
= bld
.RNDE(result
, op
[0]);
1288 inst
->saturate
= instr
->dest
.saturate
;
1291 case nir_op_fquantize2f16
: {
1292 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1293 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1294 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1296 /* The destination stride must be at least as big as the source stride. */
1297 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1300 /* Check for denormal */
1301 fs_reg abs_src0
= op
[0];
1302 abs_src0
.abs
= true;
1303 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1305 /* Get the appropriately signed zero */
1306 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1307 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1308 brw_imm_ud(0x80000000));
1309 /* Do the actual F32 -> F16 -> F32 conversion */
1310 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1311 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1312 /* Select that or zero based on normal status */
1313 inst
= bld
.SEL(result
, zero
, tmp32
);
1314 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1315 inst
->saturate
= instr
->dest
.saturate
;
1322 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1323 inst
->saturate
= instr
->dest
.saturate
;
1329 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1330 inst
->saturate
= instr
->dest
.saturate
;
1333 case nir_op_pack_snorm_2x16
:
1334 case nir_op_pack_snorm_4x8
:
1335 case nir_op_pack_unorm_2x16
:
1336 case nir_op_pack_unorm_4x8
:
1337 case nir_op_unpack_snorm_2x16
:
1338 case nir_op_unpack_snorm_4x8
:
1339 case nir_op_unpack_unorm_2x16
:
1340 case nir_op_unpack_unorm_4x8
:
1341 case nir_op_unpack_half_2x16
:
1342 case nir_op_pack_half_2x16
:
1343 unreachable("not reached: should be handled by lower_packing_builtins");
1345 case nir_op_unpack_half_2x16_split_x
:
1346 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1347 inst
->saturate
= instr
->dest
.saturate
;
1349 case nir_op_unpack_half_2x16_split_y
:
1350 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1351 inst
->saturate
= instr
->dest
.saturate
;
1354 case nir_op_pack_64_2x32_split
:
1355 case nir_op_pack_32_2x16_split
:
1356 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1359 case nir_op_unpack_64_2x32_split_x
:
1360 case nir_op_unpack_64_2x32_split_y
: {
1361 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1362 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1364 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1368 case nir_op_unpack_32_2x16_split_x
:
1369 case nir_op_unpack_32_2x16_split_y
: {
1370 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1371 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1373 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1378 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1379 inst
->saturate
= instr
->dest
.saturate
;
1382 case nir_op_bitfield_reverse
:
1383 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1384 bld
.BFREV(result
, op
[0]);
1387 case nir_op_bit_count
:
1388 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1389 bld
.CBIT(result
, op
[0]);
1392 case nir_op_ufind_msb
: {
1393 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1394 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1398 case nir_op_ifind_msb
: {
1399 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1401 if (devinfo
->gen
< 7) {
1402 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1404 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1406 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1407 * count from the LSB side. If FBH didn't return an error
1408 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1409 * count into an LSB count.
1411 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1413 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1414 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1415 inst
->src
[0].negate
= true;
1420 case nir_op_find_lsb
:
1421 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1423 if (devinfo
->gen
< 7) {
1424 fs_reg temp
= vgrf(glsl_type::int_type
);
1426 /* (x & -x) generates a value that consists of only the LSB of x.
1427 * For all powers of 2, findMSB(y) == findLSB(y).
1429 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1430 fs_reg negated_src
= src
;
1432 /* One must be negated, and the other must be non-negated. It
1433 * doesn't matter which is which.
1435 negated_src
.negate
= true;
1438 bld
.AND(temp
, src
, negated_src
);
1439 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1441 bld
.FBL(result
, op
[0]);
1445 case nir_op_ubitfield_extract
:
1446 case nir_op_ibitfield_extract
:
1447 unreachable("should have been lowered");
1450 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1451 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1454 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1455 bld
.BFI1(result
, op
[0], op
[1]);
1458 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1459 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1462 case nir_op_bitfield_insert
:
1463 unreachable("not reached: should have been lowered");
1468 fs_reg shift_count
= op
[1];
1470 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1471 if (op
[1].file
== VGRF
&&
1472 (result
.type
== BRW_REGISTER_TYPE_Q
||
1473 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1474 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1475 BRW_REGISTER_TYPE_UD
);
1476 shift_count
.stride
= 2;
1477 bld
.MOV(shift_count
, op
[1]);
1481 switch (instr
->op
) {
1483 bld
.SHL(result
, op
[0], shift_count
);
1486 bld
.ASR(result
, op
[0], shift_count
);
1489 bld
.SHR(result
, op
[0], shift_count
);
1492 unreachable("not reached");
1497 case nir_op_pack_half_2x16_split
:
1498 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1502 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1503 inst
->saturate
= instr
->dest
.saturate
;
1507 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1508 inst
->saturate
= instr
->dest
.saturate
;
1512 if (optimize_frontfacing_ternary(instr
, result
))
1515 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1516 inst
= bld
.SEL(result
, op
[1], op
[2]);
1517 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1520 case nir_op_extract_u8
:
1521 case nir_op_extract_i8
: {
1522 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1527 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1528 * Use two instructions and a word or DWord intermediate integer type.
1530 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1531 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1533 if (instr
->op
== nir_op_extract_i8
) {
1534 /* If we need to sign extend, extract to a word first */
1535 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1536 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1537 bld
.MOV(result
, w_temp
);
1539 /* Otherwise use an AND with 0xff and a word type */
1540 bld
.AND(result
, subscript(op
[0], type
, byte
/ 2), brw_imm_uw(0xff));
1543 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1544 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1549 case nir_op_extract_u16
:
1550 case nir_op_extract_i16
: {
1551 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1552 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1553 bld
.MOV(result
, subscript(op
[0], type
, word
));
1558 unreachable("unhandled instruction");
1561 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1562 * to sign extend the low bit to 0/~0
1564 if (devinfo
->gen
<= 5 &&
1565 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1566 fs_reg masked
= vgrf(glsl_type::int_type
);
1567 bld
.AND(masked
, result
, brw_imm_d(1));
1568 masked
.negate
= true;
1569 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1574 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1575 nir_load_const_instr
*instr
)
1577 const brw_reg_type reg_type
=
1578 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1579 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1581 switch (instr
->def
.bit_size
) {
1583 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1584 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1588 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1589 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1593 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1594 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1598 assert(devinfo
->gen
>= 7);
1599 if (devinfo
->gen
== 7) {
1600 /* We don't get 64-bit integer types until gen8 */
1601 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1602 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1603 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1606 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1607 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1612 unreachable("Invalid bit size");
1615 nir_ssa_values
[instr
->def
.index
] = reg
;
1619 fs_visitor::get_nir_src(const nir_src
&src
)
1623 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1624 const brw_reg_type reg_type
=
1625 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1626 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1628 reg
= nir_ssa_values
[src
.ssa
->index
];
1631 /* We don't handle indirects on locals */
1632 assert(src
.reg
.indirect
== NULL
);
1633 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1634 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1637 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1638 /* The only 64-bit type available on gen7 is DF, so use that. */
1639 reg
.type
= BRW_REGISTER_TYPE_DF
;
1641 /* To avoid floating-point denorm flushing problems, set the type by
1642 * default to an integer type - instructions that need floating point
1643 * semantics will set this to F if they need to
1645 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1646 BRW_REGISTER_TYPE_D
);
1653 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1655 * This function should not be called on any value which may be 64 bits.
1656 * We could theoretically support 64-bit on gen8+ but we choose not to
1657 * because it wouldn't work in general (no gen7 support) and there are
1658 * enough restrictions in 64-bit immediates that you can't take the return
1659 * value and treat it the same as the result of get_nir_src().
1662 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1664 assert(nir_src_bit_size(src
) == 32);
1665 return nir_src_is_const(src
) ?
1666 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1670 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1673 const brw_reg_type reg_type
=
1674 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1675 dest
.ssa
.bit_size
== 8 ?
1676 BRW_REGISTER_TYPE_D
:
1677 BRW_REGISTER_TYPE_F
);
1678 nir_ssa_values
[dest
.ssa
.index
] =
1679 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1680 return nir_ssa_values
[dest
.ssa
.index
];
1682 /* We don't handle indirects on locals */
1683 assert(dest
.reg
.indirect
== NULL
);
1684 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1685 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1690 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1693 for (unsigned i
= 0; i
< 4; i
++) {
1694 if (!((wr_mask
>> i
) & 1))
1697 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1698 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1699 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1700 if (new_inst
->src
[j
].file
== VGRF
)
1701 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1708 emit_pixel_interpolater_send(const fs_builder
&bld
,
1713 glsl_interp_mode interpolation
)
1715 struct brw_wm_prog_data
*wm_prog_data
=
1716 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1718 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1719 /* 2 floats per slot returned */
1720 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1721 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1723 wm_prog_data
->pulls_bary
= true;
1729 * Computes 1 << x, given a D/UD register containing some value x.
1732 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1734 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1736 fs_reg result
= bld
.vgrf(x
.type
, 1);
1737 fs_reg one
= bld
.vgrf(x
.type
, 1);
1739 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1740 bld
.SHL(result
, one
, x
);
1745 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1747 assert(stage
== MESA_SHADER_GEOMETRY
);
1749 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1751 if (gs_compile
->control_data_header_size_bits
== 0)
1754 /* We can only do EndPrimitive() functionality when the control data
1755 * consists of cut bits. Fortunately, the only time it isn't is when the
1756 * output type is points, in which case EndPrimitive() is a no-op.
1758 if (gs_prog_data
->control_data_format
!=
1759 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1763 /* Cut bits use one bit per vertex. */
1764 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1766 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1767 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1769 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1770 * vertex n, 0 otherwise. So all we need to do here is mark bit
1771 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1772 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1773 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1775 * Note that if EndPrimitive() is called before emitting any vertices, this
1776 * will cause us to set bit 31 of the control_data_bits register to 1.
1777 * That's fine because:
1779 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1780 * output, so the hardware will ignore cut bit 31.
1782 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1783 * last vertex, so setting cut bit 31 has no effect (since the primitive
1784 * is automatically ended when the GS terminates).
1786 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1787 * control_data_bits register to 0 when the first vertex is emitted.
1790 const fs_builder abld
= bld
.annotate("end primitive");
1792 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1793 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1794 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1795 fs_reg mask
= intexp2(abld
, prev_count
);
1796 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1797 * attention to the lower 5 bits of its second source argument, so on this
1798 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1799 * ((vertex_count - 1) % 32).
1801 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1805 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1807 assert(stage
== MESA_SHADER_GEOMETRY
);
1808 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1810 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1812 const fs_builder abld
= bld
.annotate("emit control data bits");
1813 const fs_builder fwa_bld
= bld
.exec_all();
1815 /* We use a single UD register to accumulate control data bits (32 bits
1816 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1819 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1820 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1821 * use the Channel Mask phase to enable/disable which DWord within that
1822 * group to write. (Remember, different SIMD8 channels may have emitted
1823 * different numbers of vertices, so we may need per-slot offsets.)
1825 * Channel masking presents an annoying problem: we may have to replicate
1826 * the data up to 4 times:
1828 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1830 * To avoid penalizing shaders that emit a small number of vertices, we
1831 * can avoid these sometimes: if the size of the control data header is
1832 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1833 * land in the same 128-bit group, so we can skip per-slot offsets.
1835 * Similarly, if the control data header is <= 32 bits, there is only one
1836 * DWord, so we can skip channel masks.
1838 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1840 fs_reg channel_mask
, per_slot_offset
;
1842 if (gs_compile
->control_data_header_size_bits
> 32) {
1843 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1844 channel_mask
= vgrf(glsl_type::uint_type
);
1847 if (gs_compile
->control_data_header_size_bits
> 128) {
1848 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1849 per_slot_offset
= vgrf(glsl_type::uint_type
);
1852 /* Figure out which DWord we're trying to write to using the formula:
1854 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1856 * Since bits_per_vertex is a power of two, and is known at compile
1857 * time, this can be optimized to:
1859 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1861 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1862 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1863 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1864 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1865 unsigned log2_bits_per_vertex
=
1866 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1867 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1869 if (per_slot_offset
.file
!= BAD_FILE
) {
1870 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1871 * the appropriate OWord within the control data header.
1873 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1876 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1877 * write to the appropriate DWORD within the OWORD.
1879 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1880 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1881 channel_mask
= intexp2(fwa_bld
, channel
);
1882 /* Then the channel masks need to be in bits 23:16. */
1883 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1886 /* Store the control data bits in the message payload and send it. */
1888 if (channel_mask
.file
!= BAD_FILE
)
1889 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1890 if (per_slot_offset
.file
!= BAD_FILE
)
1893 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1894 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1896 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1897 if (per_slot_offset
.file
!= BAD_FILE
)
1898 sources
[i
++] = per_slot_offset
;
1899 if (channel_mask
.file
!= BAD_FILE
)
1900 sources
[i
++] = channel_mask
;
1902 sources
[i
++] = this->control_data_bits
;
1905 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1906 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1908 /* We need to increment Global Offset by 256-bits to make room for
1909 * Broadwell's extra "Vertex Count" payload at the beginning of the
1910 * URB entry. Since this is an OWord message, Global Offset is counted
1911 * in 128-bit units, so we must set it to 2.
1913 if (gs_prog_data
->static_vertex_count
== -1)
1918 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1921 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1923 /* Note: we are calling this *before* increasing vertex_count, so
1924 * this->vertex_count == vertex_count - 1 in the formula above.
1927 /* Stream mode uses 2 bits per vertex */
1928 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1930 /* Must be a valid stream */
1931 assert(stream_id
< MAX_VERTEX_STREAMS
);
1933 /* Control data bits are initialized to 0 so we don't have to set any
1934 * bits when sending vertices to stream 0.
1939 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1941 /* reg::sid = stream_id */
1942 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1943 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1945 /* reg:shift_count = 2 * (vertex_count - 1) */
1946 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1947 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1949 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1950 * attention to the lower 5 bits of its second source argument, so on this
1951 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1952 * stream_id << ((2 * (vertex_count - 1)) % 32).
1954 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1955 abld
.SHL(mask
, sid
, shift_count
);
1956 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1960 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1963 assert(stage
== MESA_SHADER_GEOMETRY
);
1965 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1967 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1968 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1970 /* Haswell and later hardware ignores the "Render Stream Select" bits
1971 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1972 * and instead sends all primitives down the pipeline for rasterization.
1973 * If the SOL stage is enabled, "Render Stream Select" is honored and
1974 * primitives bound to non-zero streams are discarded after stream output.
1976 * Since the only purpose of primives sent to non-zero streams is to
1977 * be recorded by transform feedback, we can simply discard all geometry
1978 * bound to these streams when transform feedback is disabled.
1980 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1983 /* If we're outputting 32 control data bits or less, then we can wait
1984 * until the shader is over to output them all. Otherwise we need to
1985 * output them as we go. Now is the time to do it, since we're about to
1986 * output the vertex_count'th vertex, so it's guaranteed that the
1987 * control data bits associated with the (vertex_count - 1)th vertex are
1990 if (gs_compile
->control_data_header_size_bits
> 32) {
1991 const fs_builder abld
=
1992 bld
.annotate("emit vertex: emit control data bits");
1994 /* Only emit control data bits if we've finished accumulating a batch
1995 * of 32 bits. This is the case when:
1997 * (vertex_count * bits_per_vertex) % 32 == 0
1999 * (in other words, when the last 5 bits of vertex_count *
2000 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2001 * integer n (which is always the case, since bits_per_vertex is
2002 * always 1 or 2), this is equivalent to requiring that the last 5-n
2003 * bits of vertex_count are 0:
2005 * vertex_count & (2^(5-n) - 1) == 0
2007 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2010 * vertex_count & (32 / bits_per_vertex - 1) == 0
2012 * TODO: If vertex_count is an immediate, we could do some of this math
2013 * at compile time...
2016 abld
.AND(bld
.null_reg_d(), vertex_count
,
2017 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2018 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2020 abld
.IF(BRW_PREDICATE_NORMAL
);
2021 /* If vertex_count is 0, then no control data bits have been
2022 * accumulated yet, so we can skip emitting them.
2024 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2025 BRW_CONDITIONAL_NEQ
);
2026 abld
.IF(BRW_PREDICATE_NORMAL
);
2027 emit_gs_control_data_bits(vertex_count
);
2028 abld
.emit(BRW_OPCODE_ENDIF
);
2030 /* Reset control_data_bits to 0 so we can start accumulating a new
2033 * Note: in the case where vertex_count == 0, this neutralizes the
2034 * effect of any call to EndPrimitive() that the shader may have
2035 * made before outputting its first vertex.
2037 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2038 inst
->force_writemask_all
= true;
2039 abld
.emit(BRW_OPCODE_ENDIF
);
2042 emit_urb_writes(vertex_count
);
2044 /* In stream mode we have to set control data bits for all vertices
2045 * unless we have disabled control data bits completely (which we do
2046 * do for GL_POINTS outputs that don't use streams).
2048 if (gs_compile
->control_data_header_size_bits
> 0 &&
2049 gs_prog_data
->control_data_format
==
2050 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2051 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2056 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2057 const nir_src
&vertex_src
,
2058 unsigned base_offset
,
2059 const nir_src
&offset_src
,
2060 unsigned num_components
,
2061 unsigned first_component
)
2063 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2064 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2066 /* TODO: figure out push input layout for invocations == 1 */
2067 /* TODO: make this work with 64-bit inputs */
2068 if (gs_prog_data
->invocations
== 1 &&
2069 type_sz(dst
.type
) <= 4 &&
2070 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2071 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2072 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2073 nir_src_as_uint(vertex_src
) * push_reg_count
;
2074 for (unsigned i
= 0; i
< num_components
; i
++) {
2075 bld
.MOV(offset(dst
, bld
, i
),
2076 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2081 /* Resort to the pull model. Ensure the VUE handles are provided. */
2082 assert(gs_prog_data
->base
.include_vue_handles
);
2084 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2085 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2087 if (gs_prog_data
->invocations
== 1) {
2088 if (nir_src_is_const(vertex_src
)) {
2089 /* The vertex index is constant; just select the proper URB handle. */
2091 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2092 BRW_REGISTER_TYPE_UD
);
2094 /* The vertex index is non-constant. We need to use indirect
2095 * addressing to fetch the proper URB handle.
2097 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2098 * indicating that channel <n> should read the handle from
2099 * DWord <n>. We convert that to bytes by multiplying by 4.
2101 * Next, we convert the vertex index to bytes by multiplying
2102 * by 32 (shifting by 5), and add the two together. This is
2103 * the final indirect byte offset.
2105 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2106 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2107 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2108 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2110 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2111 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2112 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2113 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2114 /* Convert vertex_index to bytes (multiply by 32) */
2115 bld
.SHL(vertex_offset_bytes
,
2116 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2118 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2120 /* Use first_icp_handle as the base offset. There is one register
2121 * of URB handles per vertex, so inform the register allocator that
2122 * we might read up to nir->info.gs.vertices_in registers.
2124 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2125 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2126 fs_reg(icp_offset_bytes
),
2127 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2130 assert(gs_prog_data
->invocations
> 1);
2132 if (nir_src_is_const(vertex_src
)) {
2133 unsigned vertex
= nir_src_as_uint(vertex_src
);
2134 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2136 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2137 BRW_REGISTER_TYPE_UD
));
2139 /* The vertex index is non-constant. We need to use indirect
2140 * addressing to fetch the proper URB handle.
2143 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2145 /* Convert vertex_index to bytes (multiply by 4) */
2146 bld
.SHL(icp_offset_bytes
,
2147 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2150 /* Use first_icp_handle as the base offset. There is one DWord
2151 * of URB handles per vertex, so inform the register allocator that
2152 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2154 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2155 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2156 fs_reg(icp_offset_bytes
),
2157 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2164 fs_reg tmp_dst
= dst
;
2165 fs_reg indirect_offset
= get_nir_src(offset_src
);
2166 unsigned num_iterations
= 1;
2167 unsigned orig_num_components
= num_components
;
2169 if (type_sz(dst
.type
) == 8) {
2170 if (num_components
> 2) {
2174 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2176 first_component
= first_component
/ 2;
2179 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2180 if (nir_src_is_const(offset_src
)) {
2181 /* Constant indexing - use global offset. */
2182 if (first_component
!= 0) {
2183 unsigned read_components
= num_components
+ first_component
;
2184 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2185 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2186 inst
->size_written
= read_components
*
2187 tmp
.component_size(inst
->exec_size
);
2188 for (unsigned i
= 0; i
< num_components
; i
++) {
2189 bld
.MOV(offset(tmp_dst
, bld
, i
),
2190 offset(tmp
, bld
, i
+ first_component
));
2193 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2195 inst
->size_written
= num_components
*
2196 tmp_dst
.component_size(inst
->exec_size
);
2198 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2201 /* Indirect indexing - use per-slot offsets as well. */
2202 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2203 unsigned read_components
= num_components
+ first_component
;
2204 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2205 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2206 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2207 if (first_component
!= 0) {
2208 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2210 inst
->size_written
= read_components
*
2211 tmp
.component_size(inst
->exec_size
);
2212 for (unsigned i
= 0; i
< num_components
; i
++) {
2213 bld
.MOV(offset(tmp_dst
, bld
, i
),
2214 offset(tmp
, bld
, i
+ first_component
));
2217 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2219 inst
->size_written
= num_components
*
2220 tmp_dst
.component_size(inst
->exec_size
);
2222 inst
->offset
= base_offset
;
2226 if (type_sz(dst
.type
) == 8) {
2227 shuffle_from_32bit_read(bld
,
2228 offset(dst
, bld
, iter
* 2),
2229 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2234 if (num_iterations
> 1) {
2235 num_components
= orig_num_components
- 2;
2236 if(nir_src_is_const(offset_src
)) {
2239 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2240 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2241 indirect_offset
= new_indirect
;
2248 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2250 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2252 if (nir_src_is_const(*offset_src
)) {
2253 /* The only constant offset we should find is 0. brw_nir.c's
2254 * add_const_offset_to_base() will fold other constant offsets
2255 * into instr->const_index[0].
2257 assert(nir_src_as_uint(*offset_src
) == 0);
2261 return get_nir_src(*offset_src
);
2265 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2266 nir_intrinsic_instr
*instr
)
2268 assert(stage
== MESA_SHADER_VERTEX
);
2271 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2272 dest
= get_nir_dest(instr
->dest
);
2274 switch (instr
->intrinsic
) {
2275 case nir_intrinsic_load_vertex_id
:
2276 case nir_intrinsic_load_base_vertex
:
2277 unreachable("should be lowered by nir_lower_system_values()");
2279 case nir_intrinsic_load_input
: {
2280 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2281 unsigned first_component
= nir_intrinsic_component(instr
);
2282 unsigned num_components
= instr
->num_components
;
2284 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2286 if (type_sz(dest
.type
) == 8)
2287 first_component
/= 2;
2289 /* For 16-bit support maybe a temporary will be needed to copy from
2292 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2293 first_component
, num_components
);
2297 case nir_intrinsic_load_vertex_id_zero_base
:
2298 case nir_intrinsic_load_instance_id
:
2299 case nir_intrinsic_load_base_instance
:
2300 case nir_intrinsic_load_draw_id
:
2301 case nir_intrinsic_load_first_vertex
:
2302 case nir_intrinsic_load_is_indexed_draw
:
2303 unreachable("lowered by brw_nir_lower_vs_inputs");
2306 nir_emit_intrinsic(bld
, instr
);
2312 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2313 nir_intrinsic_instr
*instr
)
2315 assert(stage
== MESA_SHADER_TESS_CTRL
);
2316 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2317 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2320 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2321 dst
= get_nir_dest(instr
->dest
);
2323 switch (instr
->intrinsic
) {
2324 case nir_intrinsic_load_primitive_id
:
2325 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2327 case nir_intrinsic_load_invocation_id
:
2328 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2330 case nir_intrinsic_load_patch_vertices_in
:
2331 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2332 brw_imm_d(tcs_key
->input_vertices
));
2335 case nir_intrinsic_barrier
: {
2336 if (tcs_prog_data
->instances
== 1)
2339 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2340 fs_reg m0_2
= component(m0
, 2);
2342 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2344 /* Zero the message header */
2345 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2347 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2348 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2349 brw_imm_ud(INTEL_MASK(16, 13)));
2351 /* Shift it up to bits 27:24. */
2352 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2354 /* Set the Barrier Count and the enable bit */
2355 chanbld
.OR(m0_2
, m0_2
,
2356 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2358 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2362 case nir_intrinsic_load_input
:
2363 unreachable("nir_lower_io should never give us these.");
2366 case nir_intrinsic_load_per_vertex_input
: {
2367 fs_reg indirect_offset
= get_indirect_offset(instr
);
2368 unsigned imm_offset
= instr
->const_index
[0];
2370 const nir_src
&vertex_src
= instr
->src
[0];
2376 if (nir_src_is_const(vertex_src
)) {
2377 /* Emit a MOV to resolve <0,1,0> regioning. */
2378 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2379 unsigned vertex
= nir_src_as_uint(vertex_src
);
2381 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2382 BRW_REGISTER_TYPE_UD
));
2383 } else if (tcs_prog_data
->instances
== 1 &&
2384 vertex_src
.is_ssa
&&
2385 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2386 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2387 /* For the common case of only 1 instance, an array index of
2388 * gl_InvocationID means reading g1. Skip all the indirect work.
2390 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2392 /* The vertex index is non-constant. We need to use indirect
2393 * addressing to fetch the proper URB handle.
2395 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2397 /* Each ICP handle is a single DWord (4 bytes) */
2398 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2399 bld
.SHL(vertex_offset_bytes
,
2400 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2403 /* Start at g1. We might read up to 4 registers. */
2404 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2405 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2406 brw_imm_ud(4 * REG_SIZE
));
2409 /* We can only read two double components with each URB read, so
2410 * we send two read messages in that case, each one loading up to
2411 * two double components.
2413 unsigned num_iterations
= 1;
2414 unsigned num_components
= instr
->num_components
;
2415 unsigned first_component
= nir_intrinsic_component(instr
);
2416 fs_reg orig_dst
= dst
;
2417 if (type_sz(dst
.type
) == 8) {
2418 first_component
= first_component
/ 2;
2419 if (instr
->num_components
> 2) {
2424 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2428 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2429 if (indirect_offset
.file
== BAD_FILE
) {
2430 /* Constant indexing - use global offset. */
2431 if (first_component
!= 0) {
2432 unsigned read_components
= num_components
+ first_component
;
2433 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2434 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2435 for (unsigned i
= 0; i
< num_components
; i
++) {
2436 bld
.MOV(offset(dst
, bld
, i
),
2437 offset(tmp
, bld
, i
+ first_component
));
2440 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2442 inst
->offset
= imm_offset
;
2445 /* Indirect indexing - use per-slot offsets as well. */
2446 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2447 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2448 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2449 if (first_component
!= 0) {
2450 unsigned read_components
= num_components
+ first_component
;
2451 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2452 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2454 for (unsigned i
= 0; i
< num_components
; i
++) {
2455 bld
.MOV(offset(dst
, bld
, i
),
2456 offset(tmp
, bld
, i
+ first_component
));
2459 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2462 inst
->offset
= imm_offset
;
2465 inst
->size_written
= (num_components
+ first_component
) *
2466 inst
->dst
.component_size(inst
->exec_size
);
2468 /* If we are reading 64-bit data using 32-bit read messages we need
2469 * build proper 64-bit data elements by shuffling the low and high
2470 * 32-bit components around like we do for other things like UBOs
2473 if (type_sz(dst
.type
) == 8) {
2474 shuffle_from_32bit_read(bld
,
2475 offset(orig_dst
, bld
, iter
* 2),
2476 retype(dst
, BRW_REGISTER_TYPE_D
),
2480 /* Copy the temporary to the destination to deal with writemasking.
2482 * Also attempt to deal with gl_PointSize being in the .w component.
2484 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2485 assert(type_sz(dst
.type
) < 8);
2486 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2487 inst
->size_written
= 4 * REG_SIZE
;
2488 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2491 /* If we are loading double data and we need a second read message
2492 * adjust the write offset
2494 if (num_iterations
> 1) {
2495 num_components
= instr
->num_components
- 2;
2502 case nir_intrinsic_load_output
:
2503 case nir_intrinsic_load_per_vertex_output
: {
2504 fs_reg indirect_offset
= get_indirect_offset(instr
);
2505 unsigned imm_offset
= instr
->const_index
[0];
2506 unsigned first_component
= nir_intrinsic_component(instr
);
2509 if (indirect_offset
.file
== BAD_FILE
) {
2510 /* Replicate the patch handle to all enabled channels */
2511 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2512 bld
.MOV(patch_handle
,
2513 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2516 if (first_component
!= 0) {
2517 unsigned read_components
=
2518 instr
->num_components
+ first_component
;
2519 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2520 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2522 inst
->size_written
= read_components
* REG_SIZE
;
2523 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2524 bld
.MOV(offset(dst
, bld
, i
),
2525 offset(tmp
, bld
, i
+ first_component
));
2528 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2530 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2532 inst
->offset
= imm_offset
;
2536 /* Indirect indexing - use per-slot offsets as well. */
2537 const fs_reg srcs
[] = {
2538 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2541 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2542 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2543 if (first_component
!= 0) {
2544 unsigned read_components
=
2545 instr
->num_components
+ first_component
;
2546 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2547 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2549 inst
->size_written
= read_components
* REG_SIZE
;
2550 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2551 bld
.MOV(offset(dst
, bld
, i
),
2552 offset(tmp
, bld
, i
+ first_component
));
2555 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2557 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2559 inst
->offset
= imm_offset
;
2565 case nir_intrinsic_store_output
:
2566 case nir_intrinsic_store_per_vertex_output
: {
2567 fs_reg value
= get_nir_src(instr
->src
[0]);
2568 bool is_64bit
= (instr
->src
[0].is_ssa
?
2569 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2570 fs_reg indirect_offset
= get_indirect_offset(instr
);
2571 unsigned imm_offset
= instr
->const_index
[0];
2572 unsigned mask
= instr
->const_index
[1];
2573 unsigned header_regs
= 0;
2575 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2577 if (indirect_offset
.file
!= BAD_FILE
) {
2578 srcs
[header_regs
++] = indirect_offset
;
2584 unsigned num_components
= util_last_bit(mask
);
2587 /* We can only pack two 64-bit components in a single message, so send
2588 * 2 messages if we have more components
2590 unsigned num_iterations
= 1;
2591 unsigned iter_components
= num_components
;
2592 unsigned first_component
= nir_intrinsic_component(instr
);
2594 first_component
= first_component
/ 2;
2595 if (instr
->num_components
> 2) {
2597 iter_components
= 2;
2601 mask
= mask
<< first_component
;
2603 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2604 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2605 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2606 opcode
= indirect_offset
.file
!= BAD_FILE
?
2607 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2608 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2609 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2610 /* Expand the 64-bit mask to 32-bit channels. We only handle
2611 * two channels in each iteration, so we only care about X/Y.
2613 unsigned mask32
= 0;
2614 if (mask
& WRITEMASK_X
)
2615 mask32
|= WRITEMASK_XY
;
2616 if (mask
& WRITEMASK_Y
)
2617 mask32
|= WRITEMASK_ZW
;
2619 /* If the mask does not include any of the channels X or Y there
2620 * is nothing to do in this iteration. Move on to the next couple
2621 * of 64-bit channels.
2629 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2630 opcode
= indirect_offset
.file
!= BAD_FILE
?
2631 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2632 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2634 opcode
= indirect_offset
.file
!= BAD_FILE
?
2635 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2636 SHADER_OPCODE_URB_WRITE_SIMD8
;
2639 for (unsigned i
= 0; i
< iter_components
; i
++) {
2640 if (!(mask
& (1 << (i
+ first_component
))))
2644 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2646 /* We need to shuffle the 64-bit data to match the layout
2647 * expected by our 32-bit URB write messages. We use a temporary
2650 unsigned channel
= iter
* 2 + i
;
2651 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2653 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2654 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2655 offset(dest
, bld
, 1);
2660 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2661 (is_64bit
? 2 * first_component
: first_component
);
2663 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2664 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2666 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2667 inst
->offset
= imm_offset
;
2670 /* If this is a 64-bit attribute, select the next two 64-bit channels
2671 * to be handled in the next iteration.
2682 nir_emit_intrinsic(bld
, instr
);
2688 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2689 nir_intrinsic_instr
*instr
)
2691 assert(stage
== MESA_SHADER_TESS_EVAL
);
2692 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2695 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2696 dest
= get_nir_dest(instr
->dest
);
2698 switch (instr
->intrinsic
) {
2699 case nir_intrinsic_load_primitive_id
:
2700 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2702 case nir_intrinsic_load_tess_coord
:
2703 /* gl_TessCoord is part of the payload in g1-3 */
2704 for (unsigned i
= 0; i
< 3; i
++) {
2705 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2709 case nir_intrinsic_load_input
:
2710 case nir_intrinsic_load_per_vertex_input
: {
2711 fs_reg indirect_offset
= get_indirect_offset(instr
);
2712 unsigned imm_offset
= instr
->const_index
[0];
2713 unsigned first_component
= nir_intrinsic_component(instr
);
2715 if (type_sz(dest
.type
) == 8) {
2716 first_component
= first_component
/ 2;
2720 if (indirect_offset
.file
== BAD_FILE
) {
2721 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2722 * which is 16 registers (since each holds 2 vec4 slots).
2724 unsigned slot_count
= 1;
2725 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2728 const unsigned max_push_slots
= 32;
2729 if (imm_offset
+ slot_count
<= max_push_slots
) {
2730 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2731 for (int i
= 0; i
< instr
->num_components
; i
++) {
2732 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2733 i
+ first_component
;
2734 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2737 tes_prog_data
->base
.urb_read_length
=
2738 MAX2(tes_prog_data
->base
.urb_read_length
,
2739 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2741 /* Replicate the patch handle to all enabled channels */
2742 const fs_reg srcs
[] = {
2743 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2745 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2746 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2748 if (first_component
!= 0) {
2749 unsigned read_components
=
2750 instr
->num_components
+ first_component
;
2751 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2752 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2754 inst
->size_written
= read_components
* REG_SIZE
;
2755 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2756 bld
.MOV(offset(dest
, bld
, i
),
2757 offset(tmp
, bld
, i
+ first_component
));
2760 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2762 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2765 inst
->offset
= imm_offset
;
2768 /* Indirect indexing - use per-slot offsets as well. */
2770 /* We can only read two double components with each URB read, so
2771 * we send two read messages in that case, each one loading up to
2772 * two double components.
2774 unsigned num_iterations
= 1;
2775 unsigned num_components
= instr
->num_components
;
2776 fs_reg orig_dest
= dest
;
2777 if (type_sz(dest
.type
) == 8) {
2778 if (instr
->num_components
> 2) {
2782 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2786 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2787 const fs_reg srcs
[] = {
2788 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2791 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2792 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2794 if (first_component
!= 0) {
2795 unsigned read_components
=
2796 num_components
+ first_component
;
2797 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2798 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2800 for (unsigned i
= 0; i
< num_components
; i
++) {
2801 bld
.MOV(offset(dest
, bld
, i
),
2802 offset(tmp
, bld
, i
+ first_component
));
2805 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2809 inst
->offset
= imm_offset
;
2810 inst
->size_written
= (num_components
+ first_component
) *
2811 inst
->dst
.component_size(inst
->exec_size
);
2813 /* If we are reading 64-bit data using 32-bit read messages we need
2814 * build proper 64-bit data elements by shuffling the low and high
2815 * 32-bit components around like we do for other things like UBOs
2818 if (type_sz(dest
.type
) == 8) {
2819 shuffle_from_32bit_read(bld
,
2820 offset(orig_dest
, bld
, iter
* 2),
2821 retype(dest
, BRW_REGISTER_TYPE_D
),
2825 /* If we are loading double data and we need a second read message
2828 if (num_iterations
> 1) {
2829 num_components
= instr
->num_components
- 2;
2837 nir_emit_intrinsic(bld
, instr
);
2843 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2844 nir_intrinsic_instr
*instr
)
2846 assert(stage
== MESA_SHADER_GEOMETRY
);
2847 fs_reg indirect_offset
;
2850 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2851 dest
= get_nir_dest(instr
->dest
);
2853 switch (instr
->intrinsic
) {
2854 case nir_intrinsic_load_primitive_id
:
2855 assert(stage
== MESA_SHADER_GEOMETRY
);
2856 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2857 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2858 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2861 case nir_intrinsic_load_input
:
2862 unreachable("load_input intrinsics are invalid for the GS stage");
2864 case nir_intrinsic_load_per_vertex_input
:
2865 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2866 instr
->src
[1], instr
->num_components
,
2867 nir_intrinsic_component(instr
));
2870 case nir_intrinsic_emit_vertex_with_counter
:
2871 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2874 case nir_intrinsic_end_primitive_with_counter
:
2875 emit_gs_end_primitive(instr
->src
[0]);
2878 case nir_intrinsic_set_vertex_count
:
2879 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2882 case nir_intrinsic_load_invocation_id
: {
2883 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2884 assert(val
.file
!= BAD_FILE
);
2885 dest
.type
= val
.type
;
2891 nir_emit_intrinsic(bld
, instr
);
2897 * Fetch the current render target layer index.
2900 fetch_render_target_array_index(const fs_builder
&bld
)
2902 if (bld
.shader
->devinfo
->gen
>= 6) {
2903 /* The render target array index is provided in the thread payload as
2904 * bits 26:16 of r0.0.
2906 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2907 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2911 /* Pre-SNB we only ever render into the first layer of the framebuffer
2912 * since layered rendering is not implemented.
2914 return brw_imm_ud(0);
2919 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2920 * framebuffer at the current fragment coordinates and sample index.
2923 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2926 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2928 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2929 const brw_wm_prog_key
*wm_key
=
2930 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2931 assert(!wm_key
->coherent_fb_fetch
);
2932 const struct brw_wm_prog_data
*wm_prog_data
=
2933 brw_wm_prog_data(stage_prog_data
);
2935 /* Calculate the surface index relative to the start of the texture binding
2936 * table block, since that's what the texturing messages expect.
2938 const unsigned surface
= target
+
2939 wm_prog_data
->binding_table
.render_target_read_start
-
2940 wm_prog_data
->base
.binding_table
.texture_start
;
2942 brw_mark_surface_used(
2943 bld
.shader
->stage_prog_data
,
2944 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2946 /* Calculate the fragment coordinates. */
2947 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2948 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2949 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2950 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2952 /* Calculate the sample index and MCS payload when multisampling. Luckily
2953 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2954 * shouldn't be necessary to recompile based on whether the framebuffer is
2957 if (wm_key
->multisample_fbo
&&
2958 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2959 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2961 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2962 const fs_reg mcs
= wm_key
->multisample_fbo
?
2963 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2965 /* Use either a normal or a CMS texel fetch message depending on whether
2966 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2967 * message just in case the framebuffer uses 16x multisampling, it should
2968 * be equivalent to the normal CMS fetch for lower multisampling modes.
2970 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2971 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2972 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2974 /* Emit the instruction. */
2975 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
2976 fs_reg(), sample
, mcs
,
2977 brw_imm_ud(surface
), brw_imm_ud(0),
2978 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
2979 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
2981 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
2982 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2988 * Actual coherent framebuffer read implemented using the native render target
2989 * read message. Requires SKL+.
2992 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
2994 assert(bld
.shader
->devinfo
->gen
>= 9);
2995 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
2996 inst
->target
= target
;
2997 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3003 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3005 if (n
&& regs
[0].file
!= BAD_FILE
) {
3009 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3011 for (unsigned i
= 0; i
< n
; i
++)
3019 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3021 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3022 const brw_wm_prog_key
*const key
=
3023 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3024 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3025 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3027 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3028 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3030 else if (l
== FRAG_RESULT_COLOR
)
3031 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3032 MAX2(key
->nr_color_regions
, 1));
3034 else if (l
== FRAG_RESULT_DEPTH
)
3035 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3037 else if (l
== FRAG_RESULT_STENCIL
)
3038 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3040 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3041 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3043 else if (l
>= FRAG_RESULT_DATA0
&&
3044 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3045 return alloc_temporary(v
->bld
, 4,
3046 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3049 unreachable("Invalid location");
3053 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3054 nir_intrinsic_instr
*instr
)
3056 assert(stage
== MESA_SHADER_FRAGMENT
);
3059 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3060 dest
= get_nir_dest(instr
->dest
);
3062 switch (instr
->intrinsic
) {
3063 case nir_intrinsic_load_front_face
:
3064 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3065 *emit_frontfacing_interpolation());
3068 case nir_intrinsic_load_sample_pos
: {
3069 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3070 assert(sample_pos
.file
!= BAD_FILE
);
3071 dest
.type
= sample_pos
.type
;
3072 bld
.MOV(dest
, sample_pos
);
3073 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3077 case nir_intrinsic_load_layer_id
:
3078 dest
.type
= BRW_REGISTER_TYPE_UD
;
3079 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3082 case nir_intrinsic_load_helper_invocation
:
3083 case nir_intrinsic_load_sample_mask_in
:
3084 case nir_intrinsic_load_sample_id
: {
3085 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3086 fs_reg val
= nir_system_values
[sv
];
3087 assert(val
.file
!= BAD_FILE
);
3088 dest
.type
= val
.type
;
3093 case nir_intrinsic_store_output
: {
3094 const fs_reg src
= get_nir_src(instr
->src
[0]);
3095 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3096 const unsigned location
= nir_intrinsic_base(instr
) +
3097 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3098 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3101 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3102 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3103 offset(src
, bld
, j
));
3108 case nir_intrinsic_load_output
: {
3109 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3110 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3111 assert(l
>= FRAG_RESULT_DATA0
);
3112 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3113 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3114 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3116 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3117 emit_coherent_fb_read(bld
, tmp
, target
);
3119 emit_non_coherent_fb_read(bld
, tmp
, target
);
3121 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3122 bld
.MOV(offset(dest
, bld
, j
),
3123 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3129 case nir_intrinsic_discard
:
3130 case nir_intrinsic_discard_if
: {
3131 /* We track our discarded pixels in f0.1. By predicating on it, we can
3132 * update just the flag bits that aren't yet discarded. If there's no
3133 * condition, we emit a CMP of g0 != g0, so all currently executing
3134 * channels will get turned off.
3137 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3138 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3139 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3141 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3142 BRW_REGISTER_TYPE_UW
));
3143 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3145 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3146 cmp
->flag_subreg
= 1;
3148 if (devinfo
->gen
>= 6) {
3149 emit_discard_jump();
3152 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3156 case nir_intrinsic_load_input
: {
3157 /* load_input is only used for flat inputs */
3158 unsigned base
= nir_intrinsic_base(instr
);
3159 unsigned comp
= nir_intrinsic_component(instr
);
3160 unsigned num_components
= instr
->num_components
;
3161 fs_reg orig_dest
= dest
;
3162 enum brw_reg_type type
= dest
.type
;
3164 /* Special case fields in the VUE header */
3165 if (base
== VARYING_SLOT_LAYER
)
3167 else if (base
== VARYING_SLOT_VIEWPORT
)
3170 if (nir_dest_bit_size(instr
->dest
) == 64) {
3171 /* const_index is in 32-bit type size units that could not be aligned
3172 * with DF. We need to read the double vector as if it was a float
3173 * vector of twice the number of components to fetch the right data.
3175 type
= BRW_REGISTER_TYPE_F
;
3176 num_components
*= 2;
3177 dest
= bld
.vgrf(type
, num_components
);
3180 for (unsigned int i
= 0; i
< num_components
; i
++) {
3181 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3182 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3185 if (nir_dest_bit_size(instr
->dest
) == 64) {
3186 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3187 instr
->num_components
);
3192 case nir_intrinsic_load_barycentric_pixel
:
3193 case nir_intrinsic_load_barycentric_centroid
:
3194 case nir_intrinsic_load_barycentric_sample
:
3195 /* Do nothing - load_interpolated_input handling will handle it later. */
3198 case nir_intrinsic_load_barycentric_at_sample
: {
3199 const glsl_interp_mode interpolation
=
3200 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3202 if (nir_src_is_const(instr
->src
[0])) {
3203 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3205 emit_pixel_interpolater_send(bld
,
3206 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3209 brw_imm_ud(msg_data
),
3212 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3213 BRW_REGISTER_TYPE_UD
);
3215 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3216 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3217 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3218 bld
.exec_all().group(1, 0)
3219 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3220 emit_pixel_interpolater_send(bld
,
3221 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3227 /* Make a loop that sends a message to the pixel interpolater
3228 * for the sample number in each live channel. If there are
3229 * multiple channels with the same sample number then these
3230 * will be handled simultaneously with a single interation of
3233 bld
.emit(BRW_OPCODE_DO
);
3235 /* Get the next live sample number into sample_id_reg */
3236 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3238 /* Set the flag register so that we can perform the send
3239 * message on all channels that have the same sample number
3241 bld
.CMP(bld
.null_reg_ud(),
3242 sample_src
, sample_id
,
3243 BRW_CONDITIONAL_EQ
);
3244 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3245 bld
.exec_all().group(1, 0)
3246 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3248 emit_pixel_interpolater_send(bld
,
3249 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3252 component(msg_data
, 0),
3254 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3256 /* Continue the loop if there are any live channels left */
3257 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3259 bld
.emit(BRW_OPCODE_WHILE
));
3265 case nir_intrinsic_load_barycentric_at_offset
: {
3266 const glsl_interp_mode interpolation
=
3267 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3269 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3272 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3273 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3274 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3276 emit_pixel_interpolater_send(bld
,
3277 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3280 brw_imm_ud(off_x
| (off_y
<< 4)),
3283 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3284 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3285 BRW_REGISTER_TYPE_F
);
3286 for (int i
= 0; i
< 2; i
++) {
3287 fs_reg temp
= vgrf(glsl_type::float_type
);
3288 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3289 fs_reg itemp
= vgrf(glsl_type::int_type
);
3291 bld
.MOV(itemp
, temp
);
3293 /* Clamp the upper end of the range to +7/16.
3294 * ARB_gpu_shader5 requires that we support a maximum offset
3295 * of +0.5, which isn't representable in a S0.4 value -- if
3296 * we didn't clamp it, we'd end up with -8/16, which is the
3297 * opposite of what the shader author wanted.
3299 * This is legal due to ARB_gpu_shader5's quantization
3302 * "Not all values of <offset> may be supported; x and y
3303 * offsets may be rounded to fixed-point values with the
3304 * number of fraction bits given by the
3305 * implementation-dependent constant
3306 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3308 set_condmod(BRW_CONDITIONAL_L
,
3309 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3312 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3313 emit_pixel_interpolater_send(bld
,
3323 case nir_intrinsic_load_interpolated_input
: {
3324 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3325 emit_fragcoord_interpolation(dest
);
3329 assert(instr
->src
[0].ssa
&&
3330 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3331 nir_intrinsic_instr
*bary_intrinsic
=
3332 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3333 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3334 enum glsl_interp_mode interp_mode
=
3335 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3338 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3339 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3340 /* Use the result of the PI message */
3341 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3343 /* Use the delta_xy values computed from the payload */
3344 enum brw_barycentric_mode bary
=
3345 brw_barycentric_mode(interp_mode
, bary_intrin
);
3347 dst_xy
= this->delta_xy
[bary
];
3350 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3352 component(interp_reg(nir_intrinsic_base(instr
),
3353 nir_intrinsic_component(instr
) + i
), 0);
3354 interp
.type
= BRW_REGISTER_TYPE_F
;
3355 dest
.type
= BRW_REGISTER_TYPE_F
;
3357 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3358 fs_reg tmp
= vgrf(glsl_type::float_type
);
3359 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3360 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3362 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3369 nir_emit_intrinsic(bld
, instr
);
3375 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3377 if (nir_src_is_const(instr
->src
[src
])) {
3378 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3381 else if (add_val
== -1)
3389 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3390 nir_intrinsic_instr
*instr
)
3392 assert(stage
== MESA_SHADER_COMPUTE
);
3393 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3396 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3397 dest
= get_nir_dest(instr
->dest
);
3399 switch (instr
->intrinsic
) {
3400 case nir_intrinsic_barrier
:
3402 cs_prog_data
->uses_barrier
= true;
3405 case nir_intrinsic_load_subgroup_id
:
3406 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3409 case nir_intrinsic_load_local_invocation_id
:
3410 case nir_intrinsic_load_work_group_id
: {
3411 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3412 fs_reg val
= nir_system_values
[sv
];
3413 assert(val
.file
!= BAD_FILE
);
3414 dest
.type
= val
.type
;
3415 for (unsigned i
= 0; i
< 3; i
++)
3416 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3420 case nir_intrinsic_load_num_work_groups
: {
3421 const unsigned surface
=
3422 cs_prog_data
->binding_table
.work_groups_start
;
3424 cs_prog_data
->uses_num_work_groups
= true;
3426 fs_reg surf_index
= brw_imm_ud(surface
);
3427 brw_mark_surface_used(prog_data
, surface
);
3429 /* Read the 3 GLuint components of gl_NumWorkGroups */
3430 for (unsigned i
= 0; i
< 3; i
++) {
3431 fs_reg read_result
=
3432 emit_untyped_read(bld
, surf_index
,
3434 1 /* dims */, 1 /* size */,
3435 BRW_PREDICATE_NONE
);
3436 read_result
.type
= dest
.type
;
3437 bld
.MOV(dest
, read_result
);
3438 dest
= offset(dest
, bld
, 1);
3443 case nir_intrinsic_shared_atomic_add
:
3444 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3446 case nir_intrinsic_shared_atomic_imin
:
3447 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3449 case nir_intrinsic_shared_atomic_umin
:
3450 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3452 case nir_intrinsic_shared_atomic_imax
:
3453 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3455 case nir_intrinsic_shared_atomic_umax
:
3456 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3458 case nir_intrinsic_shared_atomic_and
:
3459 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3461 case nir_intrinsic_shared_atomic_or
:
3462 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3464 case nir_intrinsic_shared_atomic_xor
:
3465 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3467 case nir_intrinsic_shared_atomic_exchange
:
3468 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3470 case nir_intrinsic_shared_atomic_comp_swap
:
3471 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3473 case nir_intrinsic_shared_atomic_fmin
:
3474 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3476 case nir_intrinsic_shared_atomic_fmax
:
3477 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3479 case nir_intrinsic_shared_atomic_fcomp_swap
:
3480 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3483 case nir_intrinsic_load_shared
: {
3484 assert(devinfo
->gen
>= 7);
3485 assert(stage
== MESA_SHADER_COMPUTE
);
3487 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3488 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[0]),
3489 BRW_REGISTER_TYPE_UD
);
3491 /* Make dest unsigned because that's what the temporary will be */
3492 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3494 /* Read the vector */
3495 if (nir_intrinsic_align(instr
) >= 4) {
3496 assert(nir_dest_bit_size(instr
->dest
) == 32);
3497 fs_reg read_result
= emit_untyped_read(bld
, brw_imm_ud(GEN7_BTI_SLM
),
3498 offset_reg
, 1 /* dims */,
3499 instr
->num_components
,
3500 BRW_PREDICATE_NONE
);
3501 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
3502 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
3504 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3505 assert(nir_dest_num_components(instr
->dest
) == 1);
3506 fs_reg read_result
=
3507 emit_byte_scattered_read(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
,
3508 1 /* dims */, 1, bit_size
,
3509 BRW_PREDICATE_NONE
);
3510 bld
.MOV(dest
, read_result
);
3515 case nir_intrinsic_store_shared
: {
3516 assert(devinfo
->gen
>= 7);
3517 assert(stage
== MESA_SHADER_COMPUTE
);
3519 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3520 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3521 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[1]),
3522 BRW_REGISTER_TYPE_UD
);
3524 val_reg
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3526 assert(nir_intrinsic_write_mask(instr
) ==
3527 (1u << instr
->num_components
) - 1);
3528 if (nir_intrinsic_align(instr
) >= 4) {
3529 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3530 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3531 emit_untyped_write(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
, val_reg
,
3532 1 /* dims */, instr
->num_components
,
3533 BRW_PREDICATE_NONE
);
3535 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3536 assert(nir_src_num_components(instr
->src
[0]) == 1);
3537 fs_reg write_src
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3538 bld
.MOV(write_src
, val_reg
);
3539 emit_byte_scattered_write(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
,
3540 write_src
, 1 /* dims */, bit_size
,
3541 BRW_PREDICATE_NONE
);
3547 nir_emit_intrinsic(bld
, instr
);
3553 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3554 nir_op op
, brw_reg_type type
)
3556 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3557 switch (type_sz(type
)) {
3559 assert(type
!= BRW_REGISTER_TYPE_HF
);
3560 return retype(brw_imm_uw(value
.u16
[0]), type
);
3562 return retype(brw_imm_ud(value
.u32
[0]), type
);
3564 if (type
== BRW_REGISTER_TYPE_DF
)
3565 return setup_imm_df(bld
, value
.f64
[0]);
3567 return retype(brw_imm_u64(value
.u64
[0]), type
);
3569 unreachable("Invalid type size");
3574 brw_op_for_nir_reduction_op(nir_op op
)
3577 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3578 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3579 case nir_op_imul
: return BRW_OPCODE_MUL
;
3580 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3581 case nir_op_imin
: return BRW_OPCODE_SEL
;
3582 case nir_op_umin
: return BRW_OPCODE_SEL
;
3583 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3584 case nir_op_imax
: return BRW_OPCODE_SEL
;
3585 case nir_op_umax
: return BRW_OPCODE_SEL
;
3586 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3587 case nir_op_iand
: return BRW_OPCODE_AND
;
3588 case nir_op_ior
: return BRW_OPCODE_OR
;
3589 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3591 unreachable("Invalid reduction operation");
3595 static brw_conditional_mod
3596 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3599 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3600 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3601 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3602 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3603 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3604 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3605 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3606 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3607 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3608 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3609 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3610 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3611 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3613 unreachable("Invalid reduction operation");
3618 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3619 nir_intrinsic_instr
*instr
)
3621 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3623 if (stage_prog_data
->binding_table
.image_start
> 0) {
3624 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3625 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3627 bld
.ADD(image
, image
,
3628 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3632 return bld
.emit_uniformize(image
);
3636 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3637 nir_intrinsic_instr
*instr
)
3639 /* SSBO stores are weird in that their index is in src[1] */
3640 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3643 if (nir_src_is_const(instr
->src
[src
])) {
3644 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3645 nir_src_as_uint(instr
->src
[src
]);
3646 surf_index
= brw_imm_ud(index
);
3647 brw_mark_surface_used(prog_data
, index
);
3649 surf_index
= vgrf(glsl_type::uint_type
);
3650 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3651 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3653 /* Assume this may touch any UBO. It would be nice to provide
3654 * a tighter bound, but the array information is already lowered away.
3656 brw_mark_surface_used(prog_data
,
3657 stage_prog_data
->binding_table
.ssbo_start
+
3658 nir
->info
.num_ssbos
- 1);
3665 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3667 switch (nir_intrinsic_image_dim(instr
)) {
3668 case GLSL_SAMPLER_DIM_1D
:
3669 return 1 + nir_intrinsic_image_array(instr
);
3670 case GLSL_SAMPLER_DIM_2D
:
3671 case GLSL_SAMPLER_DIM_RECT
:
3672 return 2 + nir_intrinsic_image_array(instr
);
3673 case GLSL_SAMPLER_DIM_3D
:
3674 case GLSL_SAMPLER_DIM_CUBE
:
3676 case GLSL_SAMPLER_DIM_BUF
:
3678 case GLSL_SAMPLER_DIM_MS
:
3679 return 2 + nir_intrinsic_image_array(instr
);
3681 unreachable("Invalid image dimension");
3686 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3689 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3690 dest
= get_nir_dest(instr
->dest
);
3692 switch (instr
->intrinsic
) {
3693 case nir_intrinsic_image_load
:
3694 case nir_intrinsic_image_store
:
3695 case nir_intrinsic_image_atomic_add
:
3696 case nir_intrinsic_image_atomic_min
:
3697 case nir_intrinsic_image_atomic_max
:
3698 case nir_intrinsic_image_atomic_and
:
3699 case nir_intrinsic_image_atomic_or
:
3700 case nir_intrinsic_image_atomic_xor
:
3701 case nir_intrinsic_image_atomic_exchange
:
3702 case nir_intrinsic_image_atomic_comp_swap
: {
3703 if (stage
== MESA_SHADER_FRAGMENT
&&
3704 instr
->intrinsic
!= nir_intrinsic_image_load
)
3705 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3707 /* Get some metadata from the image intrinsic. */
3708 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3709 const unsigned dims
= image_intrinsic_coord_components(instr
);
3710 const GLenum format
= nir_intrinsic_format(instr
);
3711 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3713 /* Get the arguments of the image intrinsic. */
3714 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3715 const fs_reg coords
= retype(get_nir_src(instr
->src
[1]),
3716 BRW_REGISTER_TYPE_UD
);
3719 /* Emit an image load, store or atomic op. */
3720 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3721 tmp
= emit_typed_read(bld
, image
, coords
, dims
,
3722 instr
->num_components
);
3723 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3724 const fs_reg src0
= get_nir_src(instr
->src
[3]);
3725 emit_typed_write(bld
, image
, coords
, src0
, dims
,
3726 instr
->num_components
);
3729 unsigned num_srcs
= info
->num_srcs
;
3731 switch (instr
->intrinsic
) {
3732 case nir_intrinsic_image_atomic_add
:
3733 assert(num_srcs
== 4);
3735 op
= get_op_for_atomic_add(instr
, 3);
3737 if (op
!= BRW_AOP_ADD
)
3740 case nir_intrinsic_image_atomic_min
:
3741 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3742 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3744 case nir_intrinsic_image_atomic_max
:
3745 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3746 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3748 case nir_intrinsic_image_atomic_and
:
3751 case nir_intrinsic_image_atomic_or
:
3754 case nir_intrinsic_image_atomic_xor
:
3757 case nir_intrinsic_image_atomic_exchange
:
3760 case nir_intrinsic_image_atomic_comp_swap
:
3764 unreachable("Not reachable.");
3767 const fs_reg src0
= (num_srcs
>= 4 ?
3768 get_nir_src(instr
->src
[3]) : fs_reg());
3769 const fs_reg src1
= (num_srcs
>= 5 ?
3770 get_nir_src(instr
->src
[4]) : fs_reg());
3772 tmp
= emit_typed_atomic(bld
, image
, coords
, src0
, src1
, dims
, 1, op
);
3775 /* Assign the result. */
3776 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3777 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3778 offset(tmp
, bld
, c
));
3783 case nir_intrinsic_image_size
: {
3784 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3785 * into will handle the binding table index for us in the geneerator.
3787 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3788 BRW_REGISTER_TYPE_UD
);
3789 image
= bld
.emit_uniformize(image
);
3791 /* Since the image size is always uniform, we can just emit a SIMD8
3792 * query instruction and splat the result out.
3794 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3796 /* The LOD also serves as the message payload */
3797 fs_reg lod
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3798 ubld
.MOV(lod
, brw_imm_ud(0));
3800 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3801 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE
, tmp
, lod
, image
);
3803 inst
->size_written
= 4 * REG_SIZE
;
3805 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3806 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3807 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3808 offset(retype(dest
, tmp
.type
), bld
, c
),
3809 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3811 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3812 component(offset(tmp
, ubld
, c
), 0));
3818 case nir_intrinsic_image_load_raw_intel
: {
3819 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3820 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3821 BRW_REGISTER_TYPE_UD
);
3823 fs_reg tmp
= emit_untyped_read(bld
, image
, addr
, 1,
3824 instr
->num_components
);
3826 for (unsigned c
= 0; c
< instr
->num_components
; ++c
) {
3827 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3828 offset(tmp
, bld
, c
));
3833 case nir_intrinsic_image_store_raw_intel
: {
3834 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3835 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3836 BRW_REGISTER_TYPE_UD
);
3837 const fs_reg data
= retype(get_nir_src(instr
->src
[2]),
3838 BRW_REGISTER_TYPE_UD
);
3840 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3842 emit_untyped_write(bld
, image
, addr
, data
, 1,
3843 instr
->num_components
);
3847 case nir_intrinsic_group_memory_barrier
:
3848 case nir_intrinsic_memory_barrier_shared
:
3849 case nir_intrinsic_memory_barrier_atomic_counter
:
3850 case nir_intrinsic_memory_barrier_buffer
:
3851 case nir_intrinsic_memory_barrier_image
:
3852 case nir_intrinsic_memory_barrier
: {
3853 const fs_builder ubld
= bld
.group(8, 0);
3854 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3855 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3856 ->size_written
= 2 * REG_SIZE
;
3860 case nir_intrinsic_shader_clock
: {
3861 /* We cannot do anything if there is an event, so ignore it for now */
3862 const fs_reg shader_clock
= get_timestamp(bld
);
3863 const fs_reg srcs
[] = { component(shader_clock
, 0),
3864 component(shader_clock
, 1) };
3865 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3869 case nir_intrinsic_image_samples
:
3870 /* The driver does not support multi-sampled images. */
3871 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3874 case nir_intrinsic_load_uniform
: {
3875 /* Offsets are in bytes but they should always aligned to
3878 assert(instr
->const_index
[0] % 4 == 0 ||
3879 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3881 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3883 if (nir_src_is_const(instr
->src
[0])) {
3884 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3885 assert(load_offset
% type_sz(dest
.type
) == 0);
3886 /* For 16-bit types we add the module of the const_index[0]
3887 * offset to access to not 32-bit aligned element
3889 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
3891 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3892 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3895 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3896 BRW_REGISTER_TYPE_UD
);
3898 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3899 * go past the end of the uniform. In order to keep the n'th
3900 * component from running past, we subtract off the size of all but
3901 * one component of the vector.
3903 assert(instr
->const_index
[1] >=
3904 instr
->num_components
* (int) type_sz(dest
.type
));
3905 unsigned read_size
= instr
->const_index
[1] -
3906 (instr
->num_components
- 1) * type_sz(dest
.type
);
3908 bool supports_64bit_indirects
=
3909 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3911 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3912 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3913 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3914 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3915 indirect
, brw_imm_ud(read_size
));
3918 const unsigned num_mov_indirects
=
3919 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3920 /* We read a little bit less per MOV INDIRECT, as they are now
3921 * 32-bits ones instead of 64-bit. Fix read_size then.
3923 const unsigned read_size_32bit
= read_size
-
3924 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3925 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3926 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3927 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3928 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3929 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3930 indirect
, brw_imm_ud(read_size_32bit
));
3938 case nir_intrinsic_load_ubo
: {
3940 if (nir_src_is_const(instr
->src
[0])) {
3941 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3942 nir_src_as_uint(instr
->src
[0]);
3943 surf_index
= brw_imm_ud(index
);
3944 brw_mark_surface_used(prog_data
, index
);
3946 /* The block index is not a constant. Evaluate the index expression
3947 * per-channel and add the base UBO index; we have to select a value
3948 * from any live channel.
3950 surf_index
= vgrf(glsl_type::uint_type
);
3951 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3952 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3953 surf_index
= bld
.emit_uniformize(surf_index
);
3955 /* Assume this may touch any UBO. It would be nice to provide
3956 * a tighter bound, but the array information is already lowered away.
3958 brw_mark_surface_used(prog_data
,
3959 stage_prog_data
->binding_table
.ubo_start
+
3960 nir
->info
.num_ubos
- 1);
3963 if (!nir_src_is_const(instr
->src
[1])) {
3964 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3965 BRW_REGISTER_TYPE_UD
);
3967 for (int i
= 0; i
< instr
->num_components
; i
++)
3968 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3969 base_offset
, i
* type_sz(dest
.type
));
3971 /* Even if we are loading doubles, a pull constant load will load
3972 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3973 * need to load a full dvec4 we will have to emit 2 loads. This is
3974 * similar to demote_pull_constants(), except that in that case we
3975 * see individual accesses to each component of the vector and then
3976 * we let CSE deal with duplicate loads. Here we see a vector access
3977 * and we have to split it if necessary.
3979 const unsigned type_size
= type_sz(dest
.type
);
3980 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
3982 /* See if we've selected this as a push constant candidate */
3983 if (nir_src_is_const(instr
->src
[0])) {
3984 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
3985 const unsigned offset_256b
= load_offset
/ 32;
3988 for (int i
= 0; i
< 4; i
++) {
3989 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3990 if (range
->block
== ubo_block
&&
3991 offset_256b
>= range
->start
&&
3992 offset_256b
< range
->start
+ range
->length
) {
3994 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3995 push_reg
.offset
= load_offset
- 32 * range
->start
;
4000 if (push_reg
.file
!= BAD_FILE
) {
4001 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4002 bld
.MOV(offset(dest
, bld
, i
),
4003 byte_offset(push_reg
, i
* type_size
));
4009 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4010 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4011 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4013 for (unsigned c
= 0; c
< instr
->num_components
;) {
4014 const unsigned base
= load_offset
+ c
* type_size
;
4015 /* Number of usable components in the next block-aligned load. */
4016 const unsigned count
= MIN2(instr
->num_components
- c
,
4017 (block_sz
- base
% block_sz
) / type_size
);
4019 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4020 packed_consts
, surf_index
,
4021 brw_imm_ud(base
& ~(block_sz
- 1)));
4023 const fs_reg consts
=
4024 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4027 for (unsigned d
= 0; d
< count
; d
++)
4028 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4036 case nir_intrinsic_load_ssbo
: {
4037 assert(devinfo
->gen
>= 7);
4039 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4040 fs_reg surf_index
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4041 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[1]),
4042 BRW_REGISTER_TYPE_UD
);
4044 /* Make dest unsigned because that's what the temporary will be */
4045 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4047 /* Read the vector */
4048 if (nir_intrinsic_align(instr
) >= 4) {
4049 assert(nir_dest_bit_size(instr
->dest
) == 32);
4050 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
4052 instr
->num_components
,
4053 BRW_PREDICATE_NONE
);
4054 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
4055 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
4057 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4058 assert(nir_dest_num_components(instr
->dest
) == 1);
4059 fs_reg read_result
=
4060 emit_byte_scattered_read(bld
, surf_index
, offset_reg
,
4061 1 /* dims */, 1, bit_size
,
4062 BRW_PREDICATE_NONE
);
4063 bld
.MOV(dest
, read_result
);
4068 case nir_intrinsic_store_ssbo
: {
4069 assert(devinfo
->gen
>= 7);
4071 if (stage
== MESA_SHADER_FRAGMENT
)
4072 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4074 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4075 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4076 fs_reg surf_index
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4077 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[2]),
4078 BRW_REGISTER_TYPE_UD
);
4080 val_reg
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4082 assert(nir_intrinsic_write_mask(instr
) ==
4083 (1u << instr
->num_components
) - 1);
4084 if (nir_intrinsic_align(instr
) >= 4) {
4085 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4086 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4087 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
4088 1 /* dims */, instr
->num_components
,
4089 BRW_PREDICATE_NONE
);
4091 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4092 assert(nir_src_num_components(instr
->src
[0]) == 1);
4093 fs_reg write_src
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4094 bld
.MOV(write_src
, val_reg
);
4095 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4096 write_src
, 1 /* dims */, bit_size
,
4097 BRW_PREDICATE_NONE
);
4102 case nir_intrinsic_store_output
: {
4103 fs_reg src
= get_nir_src(instr
->src
[0]);
4105 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4106 unsigned num_components
= instr
->num_components
;
4107 unsigned first_component
= nir_intrinsic_component(instr
);
4108 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4109 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4110 num_components
*= 2;
4113 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4114 4 * store_offset
), src
.type
);
4115 for (unsigned j
= 0; j
< num_components
; j
++) {
4116 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4117 offset(src
, bld
, j
));
4122 case nir_intrinsic_ssbo_atomic_add
:
4123 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4125 case nir_intrinsic_ssbo_atomic_imin
:
4126 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4128 case nir_intrinsic_ssbo_atomic_umin
:
4129 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4131 case nir_intrinsic_ssbo_atomic_imax
:
4132 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4134 case nir_intrinsic_ssbo_atomic_umax
:
4135 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4137 case nir_intrinsic_ssbo_atomic_and
:
4138 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4140 case nir_intrinsic_ssbo_atomic_or
:
4141 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4143 case nir_intrinsic_ssbo_atomic_xor
:
4144 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4146 case nir_intrinsic_ssbo_atomic_exchange
:
4147 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4149 case nir_intrinsic_ssbo_atomic_comp_swap
:
4150 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4152 case nir_intrinsic_ssbo_atomic_fmin
:
4153 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4155 case nir_intrinsic_ssbo_atomic_fmax
:
4156 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4158 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4159 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4162 case nir_intrinsic_get_buffer_size
: {
4163 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4164 nir_src_as_uint(instr
->src
[0]) : 0;
4166 /* A resinfo's sampler message is used to get the buffer size. The
4167 * SIMD8's writeback message consists of four registers and SIMD16's
4168 * writeback message consists of 8 destination registers (two per each
4169 * component). Because we are only interested on the first channel of
4170 * the first returned component, where resinfo returns the buffer size
4171 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4172 * the dispatch width.
4174 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4175 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4176 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4179 ubld
.MOV(src_payload
, brw_imm_d(0));
4181 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4182 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4183 src_payload
, brw_imm_ud(index
));
4184 inst
->header_size
= 0;
4186 inst
->size_written
= 4 * REG_SIZE
;
4188 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4190 * "Out-of-bounds checking is always performed at a DWord granularity. If
4191 * any part of the DWord is out-of-bounds then the whole DWord is
4192 * considered out-of-bounds."
4194 * This implies that types with size smaller than 4-bytes need to be
4195 * padded if they don't complete the last dword of the buffer. But as we
4196 * need to maintain the original size we need to reverse the padding
4197 * calculation to return the correct size to know the number of elements
4198 * of an unsized array. As we stored in the last two bits of the surface
4199 * size the needed padding for the buffer, we calculate here the
4200 * original buffer_size reversing the surface_size calculation:
4202 * surface_size = isl_align(buffer_size, 4) +
4203 * (isl_align(buffer_size) - buffer_size)
4205 * buffer_size = surface_size & ~3 - surface_size & 3
4208 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4209 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4210 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4212 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4213 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4214 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4216 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4218 brw_mark_surface_used(prog_data
, index
);
4222 case nir_intrinsic_load_subgroup_invocation
:
4223 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4224 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4227 case nir_intrinsic_load_subgroup_eq_mask
:
4228 case nir_intrinsic_load_subgroup_ge_mask
:
4229 case nir_intrinsic_load_subgroup_gt_mask
:
4230 case nir_intrinsic_load_subgroup_le_mask
:
4231 case nir_intrinsic_load_subgroup_lt_mask
:
4232 unreachable("not reached");
4234 case nir_intrinsic_vote_any
: {
4235 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4237 /* The any/all predicates do not consider channel enables. To prevent
4238 * dead channels from affecting the result, we initialize the flag with
4239 * with the identity value for the logical operation.
4241 if (dispatch_width
== 32) {
4242 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4243 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4246 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4248 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4250 /* For some reason, the any/all predicates don't work properly with
4251 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4252 * doesn't read the correct subset of the flag register and you end up
4253 * getting garbage in the second half. Work around this by using a pair
4254 * of 1-wide MOVs and scattering the result.
4256 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4257 ubld
.MOV(res1
, brw_imm_d(0));
4258 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4259 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4260 BRW_PREDICATE_ALIGN1_ANY32H
,
4261 ubld
.MOV(res1
, brw_imm_d(-1)));
4263 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4266 case nir_intrinsic_vote_all
: {
4267 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4269 /* The any/all predicates do not consider channel enables. To prevent
4270 * dead channels from affecting the result, we initialize the flag with
4271 * with the identity value for the logical operation.
4273 if (dispatch_width
== 32) {
4274 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4275 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4276 brw_imm_ud(0xffffffff));
4278 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4280 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4282 /* For some reason, the any/all predicates don't work properly with
4283 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4284 * doesn't read the correct subset of the flag register and you end up
4285 * getting garbage in the second half. Work around this by using a pair
4286 * of 1-wide MOVs and scattering the result.
4288 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4289 ubld
.MOV(res1
, brw_imm_d(0));
4290 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4291 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4292 BRW_PREDICATE_ALIGN1_ALL32H
,
4293 ubld
.MOV(res1
, brw_imm_d(-1)));
4295 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4298 case nir_intrinsic_vote_feq
:
4299 case nir_intrinsic_vote_ieq
: {
4300 fs_reg value
= get_nir_src(instr
->src
[0]);
4301 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4302 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4303 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4306 fs_reg uniformized
= bld
.emit_uniformize(value
);
4307 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4309 /* The any/all predicates do not consider channel enables. To prevent
4310 * dead channels from affecting the result, we initialize the flag with
4311 * with the identity value for the logical operation.
4313 if (dispatch_width
== 32) {
4314 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4315 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4316 brw_imm_ud(0xffffffff));
4318 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4320 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4322 /* For some reason, the any/all predicates don't work properly with
4323 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4324 * doesn't read the correct subset of the flag register and you end up
4325 * getting garbage in the second half. Work around this by using a pair
4326 * of 1-wide MOVs and scattering the result.
4328 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4329 ubld
.MOV(res1
, brw_imm_d(0));
4330 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4331 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4332 BRW_PREDICATE_ALIGN1_ALL32H
,
4333 ubld
.MOV(res1
, brw_imm_d(-1)));
4335 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4339 case nir_intrinsic_ballot
: {
4340 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4341 BRW_REGISTER_TYPE_UD
);
4342 struct brw_reg flag
= brw_flag_reg(0, 0);
4343 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4344 * as f0.0. This is a problem for fragment programs as we currently use
4345 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4346 * programs yet so this isn't a problem. When we do, something will
4349 if (dispatch_width
== 32)
4350 flag
.type
= BRW_REGISTER_TYPE_UD
;
4352 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4353 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4355 if (instr
->dest
.ssa
.bit_size
> 32) {
4356 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4358 dest
.type
= BRW_REGISTER_TYPE_UD
;
4360 bld
.MOV(dest
, flag
);
4364 case nir_intrinsic_read_invocation
: {
4365 const fs_reg value
= get_nir_src(instr
->src
[0]);
4366 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4367 fs_reg tmp
= bld
.vgrf(value
.type
);
4369 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4370 bld
.emit_uniformize(invocation
));
4372 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4376 case nir_intrinsic_read_first_invocation
: {
4377 const fs_reg value
= get_nir_src(instr
->src
[0]);
4378 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4382 case nir_intrinsic_shuffle
: {
4383 const fs_reg value
= get_nir_src(instr
->src
[0]);
4384 const fs_reg index
= get_nir_src(instr
->src
[1]);
4386 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4390 case nir_intrinsic_first_invocation
: {
4391 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4392 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4393 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4394 fs_reg(component(tmp
, 0)));
4398 case nir_intrinsic_quad_broadcast
: {
4399 const fs_reg value
= get_nir_src(instr
->src
[0]);
4400 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4402 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4403 value
, brw_imm_ud(index
), brw_imm_ud(4));
4407 case nir_intrinsic_quad_swap_horizontal
: {
4408 const fs_reg value
= get_nir_src(instr
->src
[0]);
4409 const fs_reg tmp
= bld
.vgrf(value
.type
);
4410 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4412 const fs_reg src_left
= horiz_stride(value
, 2);
4413 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4414 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4415 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4417 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4419 * "When source or destination datatype is 64b or operation is
4420 * integer DWord multiply, regioning in Align1 must follow
4425 * 3. Source and Destination offset must be the same, except
4426 * the case of scalar source."
4428 * In order to work around this, we have to emit two 32-bit MOVs instead
4429 * of a single 64-bit MOV to do the shuffle.
4431 if (type_sz(value
.type
) > 4 &&
4432 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4433 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4434 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4435 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4436 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4437 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4438 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4439 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4440 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4442 ubld
.MOV(tmp_left
, src_right
);
4443 ubld
.MOV(tmp_right
, src_left
);
4445 bld
.MOV(retype(dest
, value
.type
), tmp
);
4449 case nir_intrinsic_quad_swap_vertical
: {
4450 const fs_reg value
= get_nir_src(instr
->src
[0]);
4451 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4452 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4453 const fs_reg tmp
= bld
.vgrf(value
.type
);
4454 const fs_builder ubld
= bld
.exec_all();
4455 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4456 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4457 bld
.MOV(retype(dest
, value
.type
), tmp
);
4459 /* For larger data types, we have to either emit dispatch_width many
4460 * MOVs or else fall back to doing indirects.
4462 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4463 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4465 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4470 case nir_intrinsic_quad_swap_diagonal
: {
4471 const fs_reg value
= get_nir_src(instr
->src
[0]);
4472 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4473 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4474 const fs_reg tmp
= bld
.vgrf(value
.type
);
4475 const fs_builder ubld
= bld
.exec_all();
4476 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4477 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4478 bld
.MOV(retype(dest
, value
.type
), tmp
);
4480 /* For larger data types, we have to either emit dispatch_width many
4481 * MOVs or else fall back to doing indirects.
4483 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4484 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4486 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4491 case nir_intrinsic_reduce
: {
4492 fs_reg src
= get_nir_src(instr
->src
[0]);
4493 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4494 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4495 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4496 cluster_size
= dispatch_width
;
4498 /* Figure out the source type */
4499 src
.type
= brw_type_for_nir_type(devinfo
,
4500 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4501 nir_src_bit_size(instr
->src
[0])));
4503 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4504 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4505 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4507 /* Set up a register for all of our scratching around and initialize it
4508 * to reduction operation's identity value.
4510 fs_reg scan
= bld
.vgrf(src
.type
);
4511 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4513 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4515 dest
.type
= src
.type
;
4516 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4517 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4518 * the distance between clusters is at least 2 GRFs. In this case,
4519 * we don't need the weird striding of the CLUSTER_BROADCAST
4520 * instruction and can just do regular MOVs.
4522 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4523 const unsigned groups
=
4524 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4525 const unsigned group_size
= dispatch_width
/ groups
;
4526 for (unsigned i
= 0; i
< groups
; i
++) {
4527 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4528 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4529 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4530 component(scan
, comp
));
4533 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4534 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4539 case nir_intrinsic_inclusive_scan
:
4540 case nir_intrinsic_exclusive_scan
: {
4541 fs_reg src
= get_nir_src(instr
->src
[0]);
4542 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4544 /* Figure out the source type */
4545 src
.type
= brw_type_for_nir_type(devinfo
,
4546 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4547 nir_src_bit_size(instr
->src
[0])));
4549 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4550 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4551 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4553 /* Set up a register for all of our scratching around and initialize it
4554 * to reduction operation's identity value.
4556 fs_reg scan
= bld
.vgrf(src
.type
);
4557 const fs_builder allbld
= bld
.exec_all();
4558 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4560 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4561 /* Exclusive scan is a bit harder because we have to do an annoying
4562 * shift of the contents before we can begin. To make things worse,
4563 * we can't do this with a normal stride; we have to use indirects.
4565 fs_reg shifted
= bld
.vgrf(src
.type
);
4566 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4567 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4569 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4570 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4574 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4576 bld
.MOV(retype(dest
, src
.type
), scan
);
4580 case nir_intrinsic_begin_invocation_interlock
: {
4581 const fs_builder ubld
= bld
.group(8, 0);
4582 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4584 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4590 case nir_intrinsic_end_invocation_interlock
: {
4591 /* We don't need to do anything here */
4596 unreachable("unknown intrinsic");
4601 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4602 int op
, nir_intrinsic_instr
*instr
)
4604 if (stage
== MESA_SHADER_FRAGMENT
)
4605 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4608 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4609 dest
= get_nir_dest(instr
->dest
);
4611 fs_reg surface
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4612 fs_reg offset
= get_nir_src(instr
->src
[1]);
4614 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4615 data1
= get_nir_src(instr
->src
[2]);
4617 if (op
== BRW_AOP_CMPWR
)
4618 data2
= get_nir_src(instr
->src
[3]);
4620 /* Emit the actual atomic operation */
4622 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4624 1 /* dims */, 1 /* rsize */,
4626 BRW_PREDICATE_NONE
);
4627 dest
.type
= atomic_result
.type
;
4628 bld
.MOV(dest
, atomic_result
);
4632 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4633 int op
, nir_intrinsic_instr
*instr
)
4635 if (stage
== MESA_SHADER_FRAGMENT
)
4636 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4639 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4640 dest
= get_nir_dest(instr
->dest
);
4642 fs_reg surface
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4643 fs_reg offset
= get_nir_src(instr
->src
[1]);
4644 fs_reg data1
= get_nir_src(instr
->src
[2]);
4646 if (op
== BRW_AOP_FCMPWR
)
4647 data2
= get_nir_src(instr
->src
[3]);
4649 /* Emit the actual atomic operation */
4651 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4653 1 /* dims */, 1 /* rsize */,
4655 BRW_PREDICATE_NONE
);
4656 dest
.type
= atomic_result
.type
;
4657 bld
.MOV(dest
, atomic_result
);
4661 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4662 int op
, nir_intrinsic_instr
*instr
)
4665 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4666 dest
= get_nir_dest(instr
->dest
);
4668 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4671 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4672 data1
= get_nir_src(instr
->src
[1]);
4674 if (op
== BRW_AOP_CMPWR
)
4675 data2
= get_nir_src(instr
->src
[2]);
4677 /* Get the offset */
4678 if (nir_src_is_const(instr
->src
[0])) {
4679 offset
= brw_imm_ud(instr
->const_index
[0] +
4680 nir_src_as_uint(instr
->src
[0]));
4682 offset
= vgrf(glsl_type::uint_type
);
4684 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4685 brw_imm_ud(instr
->const_index
[0]));
4688 /* Emit the actual atomic operation operation */
4690 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4692 1 /* dims */, 1 /* rsize */,
4694 BRW_PREDICATE_NONE
);
4695 dest
.type
= atomic_result
.type
;
4696 bld
.MOV(dest
, atomic_result
);
4700 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4701 int op
, nir_intrinsic_instr
*instr
)
4704 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4705 dest
= get_nir_dest(instr
->dest
);
4707 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4709 fs_reg data1
= get_nir_src(instr
->src
[1]);
4711 if (op
== BRW_AOP_FCMPWR
)
4712 data2
= get_nir_src(instr
->src
[2]);
4714 /* Get the offset */
4715 if (nir_src_is_const(instr
->src
[0])) {
4716 offset
= brw_imm_ud(instr
->const_index
[0] +
4717 nir_src_as_uint(instr
->src
[0]));
4719 offset
= vgrf(glsl_type::uint_type
);
4721 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4722 brw_imm_ud(instr
->const_index
[0]));
4725 /* Emit the actual atomic operation operation */
4727 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4729 1 /* dims */, 1 /* rsize */,
4731 BRW_PREDICATE_NONE
);
4732 dest
.type
= atomic_result
.type
;
4733 bld
.MOV(dest
, atomic_result
);
4737 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4739 unsigned texture
= instr
->texture_index
;
4740 unsigned sampler
= instr
->sampler_index
;
4742 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4744 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4745 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4747 int lod_components
= 0;
4749 /* The hardware requires a LOD for buffer textures */
4750 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4751 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4753 uint32_t header_bits
= 0;
4754 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4755 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4756 switch (instr
->src
[i
].src_type
) {
4757 case nir_tex_src_bias
:
4758 srcs
[TEX_LOGICAL_SRC_LOD
] =
4759 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4761 case nir_tex_src_comparator
:
4762 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4764 case nir_tex_src_coord
:
4765 switch (instr
->op
) {
4767 case nir_texop_txf_ms
:
4768 case nir_texop_txf_ms_mcs
:
4769 case nir_texop_samples_identical
:
4770 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4773 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4777 case nir_tex_src_ddx
:
4778 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4779 lod_components
= nir_tex_instr_src_size(instr
, i
);
4781 case nir_tex_src_ddy
:
4782 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4784 case nir_tex_src_lod
:
4785 switch (instr
->op
) {
4787 srcs
[TEX_LOGICAL_SRC_LOD
] =
4788 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4791 srcs
[TEX_LOGICAL_SRC_LOD
] =
4792 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4795 srcs
[TEX_LOGICAL_SRC_LOD
] =
4796 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4800 case nir_tex_src_min_lod
:
4801 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
4802 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4804 case nir_tex_src_ms_index
:
4805 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4808 case nir_tex_src_offset
: {
4809 nir_const_value
*const_offset
=
4810 nir_src_as_const_value(instr
->src
[i
].src
);
4811 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
4812 unsigned offset_bits
= 0;
4814 brw_texture_offset(const_offset
->i32
,
4815 nir_tex_instr_src_size(instr
, i
),
4817 header_bits
|= offset_bits
;
4819 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4820 retype(src
, BRW_REGISTER_TYPE_D
);
4825 case nir_tex_src_projector
:
4826 unreachable("should be lowered");
4828 case nir_tex_src_texture_offset
: {
4829 /* Figure out the highest possible texture index and mark it as used */
4830 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4831 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4832 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4834 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4836 brw_mark_surface_used(prog_data
, max_used
);
4838 /* Emit code to evaluate the actual indexing expression */
4839 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4840 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4841 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4845 case nir_tex_src_sampler_offset
: {
4846 /* Emit code to evaluate the actual indexing expression */
4847 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4848 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4849 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4853 case nir_tex_src_ms_mcs
:
4854 assert(instr
->op
== nir_texop_txf_ms
);
4855 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4858 case nir_tex_src_plane
: {
4859 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
4860 const uint32_t texture_index
=
4861 instr
->texture_index
+
4862 stage_prog_data
->binding_table
.plane_start
[plane
] -
4863 stage_prog_data
->binding_table
.texture_start
;
4865 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4870 unreachable("unknown texture source");
4874 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4875 (instr
->op
== nir_texop_txf_ms
||
4876 instr
->op
== nir_texop_samples_identical
)) {
4877 if (devinfo
->gen
>= 7 &&
4878 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4879 srcs
[TEX_LOGICAL_SRC_MCS
] =
4880 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4881 instr
->coord_components
,
4882 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4884 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4888 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4889 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4892 switch (instr
->op
) {
4894 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4895 SHADER_OPCODE_TXL_LOGICAL
);
4898 opcode
= FS_OPCODE_TXB_LOGICAL
;
4901 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4904 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4907 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4909 case nir_texop_txf_ms
:
4910 if ((key_tex
->msaa_16
& (1 << sampler
)))
4911 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4913 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4915 case nir_texop_txf_ms_mcs
:
4916 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4918 case nir_texop_query_levels
:
4920 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4923 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4926 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4927 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4929 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4931 case nir_texop_texture_samples
:
4932 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4934 case nir_texop_samples_identical
: {
4935 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4937 /* If mcs is an immediate value, it means there is no MCS. In that case
4938 * just return false.
4940 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4941 bld
.MOV(dst
, brw_imm_ud(0u));
4942 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4943 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4944 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4945 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4946 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4948 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4949 BRW_CONDITIONAL_EQ
);
4954 unreachable("unknown texture opcode");
4957 if (instr
->op
== nir_texop_tg4
) {
4958 if (instr
->component
== 1 &&
4959 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4960 /* gather4 sampler is broken for green channel on RG32F --
4961 * we must ask for blue instead.
4963 header_bits
|= 2 << 16;
4965 header_bits
|= instr
->component
<< 16;
4969 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4970 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4971 inst
->offset
= header_bits
;
4973 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4974 if (devinfo
->gen
>= 9 &&
4975 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4976 unsigned write_mask
= instr
->dest
.is_ssa
?
4977 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4978 (1 << dest_size
) - 1;
4979 assert(write_mask
!= 0); /* dead code should have been eliminated */
4980 inst
->size_written
= util_last_bit(write_mask
) *
4981 inst
->dst
.component_size(inst
->exec_size
);
4983 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4986 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4987 inst
->shadow_compare
= true;
4989 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4990 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4993 for (unsigned i
= 0; i
< dest_size
; i
++)
4994 nir_dest
[i
] = offset(dst
, bld
, i
);
4996 if (instr
->op
== nir_texop_query_levels
) {
4997 /* # levels is in .w */
4998 nir_dest
[0] = offset(dst
, bld
, 3);
4999 } else if (instr
->op
== nir_texop_txs
&&
5000 dest_size
>= 3 && devinfo
->gen
< 7) {
5001 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5002 fs_reg depth
= offset(dst
, bld
, 2);
5003 nir_dest
[2] = vgrf(glsl_type::int_type
);
5004 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5007 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5011 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5013 switch (instr
->type
) {
5014 case nir_jump_break
:
5015 bld
.emit(BRW_OPCODE_BREAK
);
5017 case nir_jump_continue
:
5018 bld
.emit(BRW_OPCODE_CONTINUE
);
5020 case nir_jump_return
:
5022 unreachable("unknown jump");
5027 * This helper takes a source register and un/shuffles it into the destination
5030 * If source type size is smaller than destination type size the operation
5031 * needed is a component shuffle. The opposite case would be an unshuffle. If
5032 * source/destination type size is equal a shuffle is done that would be
5033 * equivalent to a simple MOV.
5035 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5036 * components .xyz 16-bit vector on SIMD8 would be.
5038 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5039 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5041 * This helper will return the following 2 32-bit components with the 16-bit
5044 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5045 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5047 * For unshuffle, the example would be the opposite, a 64-bit type source
5048 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5051 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5052 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5053 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5054 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5056 * The returned result would be the following 4 32-bit components unshuffled:
5058 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5059 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5060 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5061 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5063 * - Source and destination register must not be overlapped.
5064 * - components units are measured in terms of the smaller type between
5065 * source and destination because we are un/shuffling the smaller
5066 * components from/into the bigger ones.
5067 * - first_component parameter allows skipping source components.
5070 shuffle_src_to_dst(const fs_builder
&bld
,
5073 uint32_t first_component
,
5074 uint32_t components
)
5076 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5077 assert(!regions_overlap(dst
,
5078 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5079 offset(src
, bld
, first_component
),
5080 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5081 for (unsigned i
= 0; i
< components
; i
++) {
5082 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5083 offset(src
, bld
, i
+ first_component
));
5085 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5086 /* Source is shuffled into destination */
5087 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5088 assert(!regions_overlap(dst
,
5089 type_sz(dst
.type
) * bld
.dispatch_width() *
5090 DIV_ROUND_UP(components
, size_ratio
),
5091 offset(src
, bld
, first_component
),
5092 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5094 brw_reg_type shuffle_type
=
5095 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5096 BRW_REGISTER_TYPE_D
);
5097 for (unsigned i
= 0; i
< components
; i
++) {
5098 fs_reg shuffle_component_i
=
5099 subscript(offset(dst
, bld
, i
/ size_ratio
),
5100 shuffle_type
, i
% size_ratio
);
5101 bld
.MOV(shuffle_component_i
,
5102 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5105 /* Source is unshuffled into destination */
5106 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5107 assert(!regions_overlap(dst
,
5108 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5109 offset(src
, bld
, first_component
/ size_ratio
),
5110 type_sz(src
.type
) * bld
.dispatch_width() *
5111 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5114 brw_reg_type shuffle_type
=
5115 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5116 BRW_REGISTER_TYPE_D
);
5117 for (unsigned i
= 0; i
< components
; i
++) {
5118 fs_reg shuffle_component_i
=
5119 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5120 shuffle_type
, (first_component
+ i
) % size_ratio
);
5121 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5122 shuffle_component_i
);
5128 shuffle_from_32bit_read(const fs_builder
&bld
,
5131 uint32_t first_component
,
5132 uint32_t components
)
5134 assert(type_sz(src
.type
) == 4);
5136 /* This function takes components in units of the destination type while
5137 * shuffle_src_to_dst takes components in units of the smallest type
5139 if (type_sz(dst
.type
) > 4) {
5140 assert(type_sz(dst
.type
) == 8);
5141 first_component
*= 2;
5145 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5149 shuffle_for_32bit_write(const fs_builder
&bld
,
5151 uint32_t first_component
,
5152 uint32_t components
)
5154 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5155 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5156 /* This function takes components in units of the source type while
5157 * shuffle_src_to_dst takes components in units of the smallest type
5159 if (type_sz(src
.type
) > 4) {
5160 assert(type_sz(src
.type
) == 8);
5161 first_component
*= 2;
5165 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5171 setup_imm_df(const fs_builder
&bld
, double v
)
5173 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5174 assert(devinfo
->gen
>= 7);
5176 if (devinfo
->gen
>= 8)
5177 return brw_imm_df(v
);
5179 /* gen7.5 does not support DF immediates straighforward but the DIM
5180 * instruction allows to set the 64-bit immediate value.
5182 if (devinfo
->is_haswell
) {
5183 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5184 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5185 ubld
.DIM(dst
, brw_imm_df(v
));
5186 return component(dst
, 0);
5189 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5190 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5191 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5193 * Alternatively, we could also produce a normal VGRF (without stride 0)
5194 * by writing to all the channels in the VGRF, however, that would hit the
5195 * gen7 bug where we have to split writes that span more than 1 register
5196 * into instructions with a width of 4 (otherwise the write to the second
5197 * register written runs into an execmask hardware bug) which isn't very
5210 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5211 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5212 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5213 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5215 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5219 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5221 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5222 bld
.MOV(tmp
, brw_imm_w(v
));
5227 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5229 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5230 bld
.MOV(tmp
, brw_imm_uw(v
));