2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "util/u_math.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 /* get the main function and emit it */
44 nir_foreach_function(function
, nir
) {
45 assert(strcmp(function
->name
, "main") == 0);
46 assert(function
->impl
);
47 nir_emit_impl(function
->impl
);
52 fs_visitor::nir_setup_outputs()
54 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
57 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
59 /* Calculate the size of output registers in a separate pass, before
60 * allocating them. With ARB_enhanced_layouts, multiple output variables
61 * may occupy the same slot, but have different type sizes.
63 nir_foreach_variable(var
, &nir
->outputs
) {
64 const int loc
= var
->data
.driver_location
;
65 const unsigned var_vec4s
=
66 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
67 : type_size_vec4(var
->type
);
68 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
71 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
72 if (vec4s
[loc
] == 0) {
77 unsigned reg_size
= vec4s
[loc
];
79 /* Check if there are any ranges that start within this range and extend
80 * past it. If so, include them in this allocation.
82 for (unsigned i
= 1; i
< reg_size
; i
++)
83 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
85 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
86 for (unsigned i
= 0; i
< reg_size
; i
++)
87 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
94 fs_visitor::nir_setup_uniforms()
96 /* Only the first compile gets to set up uniforms. */
97 if (push_constant_loc
) {
98 assert(pull_constant_loc
);
102 uniforms
= nir
->num_uniforms
/ 4;
104 if (stage
== MESA_SHADER_COMPUTE
) {
105 /* Add a uniform for the thread local id. It must be the last uniform
108 assert(uniforms
== prog_data
->nr_params
);
109 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
110 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
111 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
116 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
120 nir_foreach_instr(instr
, block
) {
121 if (instr
->type
!= nir_instr_type_intrinsic
)
124 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
125 switch (intrin
->intrinsic
) {
126 case nir_intrinsic_load_vertex_id
:
127 case nir_intrinsic_load_base_vertex
:
128 unreachable("should be lowered by nir_lower_system_values().");
130 case nir_intrinsic_load_vertex_id_zero_base
:
131 case nir_intrinsic_load_is_indexed_draw
:
132 case nir_intrinsic_load_first_vertex
:
133 case nir_intrinsic_load_instance_id
:
134 case nir_intrinsic_load_base_instance
:
135 case nir_intrinsic_load_draw_id
:
136 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
138 case nir_intrinsic_load_invocation_id
:
139 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
141 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
142 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
143 if (reg
->file
== BAD_FILE
) {
144 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
145 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
146 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
147 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
152 case nir_intrinsic_load_sample_pos
:
153 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
154 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
155 if (reg
->file
== BAD_FILE
)
156 *reg
= *v
->emit_samplepos_setup();
159 case nir_intrinsic_load_sample_id
:
160 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
161 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
162 if (reg
->file
== BAD_FILE
)
163 *reg
= *v
->emit_sampleid_setup();
166 case nir_intrinsic_load_sample_mask_in
:
167 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
168 assert(v
->devinfo
->gen
>= 7);
169 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
170 if (reg
->file
== BAD_FILE
)
171 *reg
= *v
->emit_samplemaskin_setup();
174 case nir_intrinsic_load_work_group_id
:
175 assert(v
->stage
== MESA_SHADER_COMPUTE
);
176 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
177 if (reg
->file
== BAD_FILE
)
178 *reg
= *v
->emit_cs_work_group_id_setup();
181 case nir_intrinsic_load_helper_invocation
:
182 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
183 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
184 if (reg
->file
== BAD_FILE
) {
185 const fs_builder abld
=
186 v
->bld
.annotate("gl_HelperInvocation", NULL
);
188 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
189 * pixel mask is in g1.7 of the thread payload.
191 * We move the per-channel pixel enable bit to the low bit of each
192 * channel by shifting the byte containing the pixel mask by the
193 * vector immediate 0x76543210UV.
195 * The region of <1,8,0> reads only 1 byte (the pixel masks for
196 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
197 * masks for 2 and 3) in SIMD16.
199 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
201 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
202 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
203 hbld
.SHR(offset(shifted
, hbld
, i
),
204 stride(retype(brw_vec1_grf(1 + i
, 7),
205 BRW_REGISTER_TYPE_UB
),
207 brw_imm_v(0x76543210));
210 /* A set bit in the pixel mask means the channel is enabled, but
211 * that is the opposite of gl_HelperInvocation so we need to invert
214 * The negate source-modifier bit of logical instructions on Gen8+
215 * performs 1's complement negation, so we can use that instead of
218 fs_reg inverted
= negate(shifted
);
219 if (v
->devinfo
->gen
< 8) {
220 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
221 abld
.NOT(inverted
, shifted
);
224 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
225 * with 1 and negating.
227 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
228 abld
.AND(anded
, inverted
, brw_imm_uw(1));
230 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
231 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
245 fs_visitor::nir_emit_system_values()
247 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
248 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
249 nir_system_values
[i
] = fs_reg();
252 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
253 * never end up using it.
256 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
257 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
258 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
260 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
261 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
262 if (dispatch_width
> 8)
263 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
264 if (dispatch_width
> 16) {
265 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
266 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
270 nir_foreach_function(function
, nir
) {
271 assert(strcmp(function
->name
, "main") == 0);
272 assert(function
->impl
);
273 nir_foreach_block(block
, function
->impl
) {
274 emit_system_values_block(block
, this);
280 * Returns a type based on a reference_type (word, float, half-float) and a
283 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
285 * @FIXME: 64-bit return types are always DF on integer types to maintain
286 * compability with uses of DF previously to the introduction of int64
290 brw_reg_type_from_bit_size(const unsigned bit_size
,
291 const brw_reg_type reference_type
)
293 switch(reference_type
) {
294 case BRW_REGISTER_TYPE_HF
:
295 case BRW_REGISTER_TYPE_F
:
296 case BRW_REGISTER_TYPE_DF
:
299 return BRW_REGISTER_TYPE_HF
;
301 return BRW_REGISTER_TYPE_F
;
303 return BRW_REGISTER_TYPE_DF
;
305 unreachable("Invalid bit size");
307 case BRW_REGISTER_TYPE_B
:
308 case BRW_REGISTER_TYPE_W
:
309 case BRW_REGISTER_TYPE_D
:
310 case BRW_REGISTER_TYPE_Q
:
313 return BRW_REGISTER_TYPE_B
;
315 return BRW_REGISTER_TYPE_W
;
317 return BRW_REGISTER_TYPE_D
;
319 return BRW_REGISTER_TYPE_Q
;
321 unreachable("Invalid bit size");
323 case BRW_REGISTER_TYPE_UB
:
324 case BRW_REGISTER_TYPE_UW
:
325 case BRW_REGISTER_TYPE_UD
:
326 case BRW_REGISTER_TYPE_UQ
:
329 return BRW_REGISTER_TYPE_UB
;
331 return BRW_REGISTER_TYPE_UW
;
333 return BRW_REGISTER_TYPE_UD
;
335 return BRW_REGISTER_TYPE_UQ
;
337 unreachable("Invalid bit size");
340 unreachable("Unknown type");
345 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
347 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
348 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
349 nir_locals
[i
] = fs_reg();
352 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
353 unsigned array_elems
=
354 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
355 unsigned size
= array_elems
* reg
->num_components
;
356 const brw_reg_type reg_type
=
357 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
358 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
361 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
364 nir_emit_cf_list(&impl
->body
);
368 fs_visitor::nir_emit_cf_list(exec_list
*list
)
370 exec_list_validate(list
);
371 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
372 switch (node
->type
) {
374 nir_emit_if(nir_cf_node_as_if(node
));
377 case nir_cf_node_loop
:
378 nir_emit_loop(nir_cf_node_as_loop(node
));
381 case nir_cf_node_block
:
382 nir_emit_block(nir_cf_node_as_block(node
));
386 unreachable("Invalid CFG node block");
392 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
394 /* first, put the condition into f0 */
395 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
396 retype(get_nir_src(if_stmt
->condition
),
397 BRW_REGISTER_TYPE_D
));
398 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
400 bld
.IF(BRW_PREDICATE_NORMAL
);
402 nir_emit_cf_list(&if_stmt
->then_list
);
404 /* note: if the else is empty, dead CF elimination will remove it */
405 bld
.emit(BRW_OPCODE_ELSE
);
407 nir_emit_cf_list(&if_stmt
->else_list
);
409 bld
.emit(BRW_OPCODE_ENDIF
);
411 if (devinfo
->gen
< 7)
412 limit_dispatch_width(16, "Non-uniform control flow unsupported "
417 fs_visitor::nir_emit_loop(nir_loop
*loop
)
419 bld
.emit(BRW_OPCODE_DO
);
421 nir_emit_cf_list(&loop
->body
);
423 bld
.emit(BRW_OPCODE_WHILE
);
425 if (devinfo
->gen
< 7)
426 limit_dispatch_width(16, "Non-uniform control flow unsupported "
431 fs_visitor::nir_emit_block(nir_block
*block
)
433 nir_foreach_instr(instr
, block
) {
434 nir_emit_instr(instr
);
439 fs_visitor::nir_emit_instr(nir_instr
*instr
)
441 const fs_builder abld
= bld
.annotate(NULL
, instr
);
443 switch (instr
->type
) {
444 case nir_instr_type_alu
:
445 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
448 case nir_instr_type_deref
:
449 /* Derefs can exist for images but they do nothing */
452 case nir_instr_type_intrinsic
:
454 case MESA_SHADER_VERTEX
:
455 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
457 case MESA_SHADER_TESS_CTRL
:
458 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
460 case MESA_SHADER_TESS_EVAL
:
461 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
463 case MESA_SHADER_GEOMETRY
:
464 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
466 case MESA_SHADER_FRAGMENT
:
467 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 case MESA_SHADER_COMPUTE
:
470 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
473 unreachable("unsupported shader stage");
477 case nir_instr_type_tex
:
478 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
481 case nir_instr_type_load_const
:
482 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
485 case nir_instr_type_ssa_undef
:
486 /* We create a new VGRF for undefs on every use (by handling
487 * them in get_nir_src()), rather than for each definition.
488 * This helps register coalescing eliminate MOVs from undef.
492 case nir_instr_type_jump
:
493 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
497 unreachable("unknown instruction type");
502 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
506 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
507 const fs_reg
&result
)
509 if (!instr
->src
[0].src
.is_ssa
||
510 !instr
->src
[0].src
.ssa
->parent_instr
)
513 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
516 nir_alu_instr
*src0
=
517 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
519 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
520 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
523 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
524 assert(element
!= NULL
);
526 /* Element type to extract.*/
527 const brw_reg_type type
= brw_int_type(
528 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
529 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
531 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
532 op0
.type
= brw_type_for_nir_type(devinfo
,
533 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
534 nir_src_bit_size(src0
->src
[0].src
)));
535 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
537 set_saturate(instr
->dest
.saturate
,
538 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
543 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
544 const fs_reg
&result
)
546 if (!instr
->src
[0].src
.is_ssa
||
547 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
550 nir_intrinsic_instr
*src0
=
551 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
553 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
556 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
557 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
560 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
561 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
564 fs_reg tmp
= vgrf(glsl_type::int_type
);
566 if (devinfo
->gen
>= 6) {
567 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
568 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
570 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
572 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
573 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
575 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
577 * This negation looks like it's safe in practice, because bits 0:4 will
578 * surely be TRIANGLES
581 if (value1
->f32
[0] == -1.0f
) {
585 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
586 g0
, brw_imm_uw(0x3f80));
588 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
589 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
591 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
593 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
594 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
596 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
598 * This negation looks like it's safe in practice, because bits 0:4 will
599 * surely be TRIANGLES
602 if (value1
->f32
[0] == -1.0f
) {
606 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
608 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
614 emit_find_msb_using_lzd(const fs_builder
&bld
,
615 const fs_reg
&result
,
623 /* LZD of an absolute value source almost always does the right
624 * thing. There are two problem values:
626 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
627 * 0. However, findMSB(int(0x80000000)) == 30.
629 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
630 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
632 * For a value of zero or negative one, -1 will be returned.
634 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
635 * findMSB(-(1<<x)) should return x-1.
637 * For all negative number cases, including 0x80000000 and
638 * 0xffffffff, the correct value is obtained from LZD if instead of
639 * negating the (already negative) value the logical-not is used. A
640 * conditonal logical-not can be achieved in two instructions.
642 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
644 bld
.ASR(temp
, src
, brw_imm_d(31));
645 bld
.XOR(temp
, temp
, src
);
648 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
649 retype(temp
, BRW_REGISTER_TYPE_UD
));
651 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
652 * from the LSB side. Subtract the result from 31 to convert the MSB
653 * count into an LSB count. If no bits are set, LZD will return 32.
654 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
656 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
657 inst
->src
[0].negate
= true;
661 brw_rnd_mode_from_nir_op (const nir_op op
) {
663 case nir_op_f2f16_rtz
:
664 return BRW_RND_MODE_RTZ
;
665 case nir_op_f2f16_rtne
:
666 return BRW_RND_MODE_RTNE
;
668 unreachable("Operation doesn't support rounding mode");
673 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
675 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
678 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
679 result
.type
= brw_type_for_nir_type(devinfo
,
680 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
681 nir_dest_bit_size(instr
->dest
.dest
)));
684 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
685 op
[i
] = get_nir_src(instr
->src
[i
].src
);
686 op
[i
].type
= brw_type_for_nir_type(devinfo
,
687 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
688 nir_src_bit_size(instr
->src
[i
].src
)));
689 op
[i
].abs
= instr
->src
[i
].abs
;
690 op
[i
].negate
= instr
->src
[i
].negate
;
693 /* We get a bunch of mov's out of the from_ssa pass and they may still
694 * be vectorized. We'll handle them as a special-case. We'll also
695 * handle vecN here because it's basically the same thing.
703 fs_reg temp
= result
;
704 bool need_extra_copy
= false;
705 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
706 if (!instr
->src
[i
].src
.is_ssa
&&
707 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
708 need_extra_copy
= true;
709 temp
= bld
.vgrf(result
.type
, 4);
714 for (unsigned i
= 0; i
< 4; i
++) {
715 if (!(instr
->dest
.write_mask
& (1 << i
)))
718 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
719 inst
= bld
.MOV(offset(temp
, bld
, i
),
720 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
722 inst
= bld
.MOV(offset(temp
, bld
, i
),
723 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
725 inst
->saturate
= instr
->dest
.saturate
;
728 /* In this case the source and destination registers were the same,
729 * so we need to insert an extra set of moves in order to deal with
732 if (need_extra_copy
) {
733 for (unsigned i
= 0; i
< 4; i
++) {
734 if (!(instr
->dest
.write_mask
& (1 << i
)))
737 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
746 /* At this point, we have dealt with any instruction that operates on
747 * more than a single channel. Therefore, we can just adjust the source
748 * and destination registers for that channel and emit the instruction.
750 unsigned channel
= 0;
751 if (nir_op_infos
[instr
->op
].output_size
== 0) {
752 /* Since NIR is doing the scalarizing for us, we should only ever see
753 * vectorized operations with a single channel.
755 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
756 channel
= ffs(instr
->dest
.write_mask
) - 1;
758 result
= offset(result
, bld
, channel
);
761 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
762 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
763 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
769 if (optimize_extract_to_float(instr
, result
))
771 inst
= bld
.MOV(result
, op
[0]);
772 inst
->saturate
= instr
->dest
.saturate
;
775 case nir_op_f2f16_rtne
:
776 case nir_op_f2f16_rtz
:
777 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
778 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
781 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
782 * on the HW gen, it is a special hw opcode or just a MOV, and
783 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
785 * But if we want to use that opcode, we need to provide support on
786 * different optimizations and lowerings. As right now HF support is
787 * only for gen8+, it will be better to use directly the MOV, and use
788 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
792 inst
= bld
.MOV(result
, op
[0]);
793 inst
->saturate
= instr
->dest
.saturate
;
798 op
[0].type
= BRW_REGISTER_TYPE_D
;
799 op
[0].negate
= !op
[0].negate
;
808 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
810 * "When source or destination is 64b (...), regioning in Align1
811 * must follow these rules:
813 * 1. Source and destination horizontal stride must be aligned to
817 * This means that conversions from bit-sizes smaller than 64-bit to
818 * 64-bit need to have the source data elements aligned to 64-bit.
819 * This restriction does not apply to BDW and later.
821 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
822 nir_src_bit_size(instr
->src
[0].src
) < 64 &&
823 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
824 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
825 tmp
= subscript(tmp
, op
[0].type
, 0);
826 inst
= bld
.MOV(tmp
, op
[0]);
827 inst
= bld
.MOV(result
, tmp
);
828 inst
->saturate
= instr
->dest
.saturate
;
845 inst
= bld
.MOV(result
, op
[0]);
846 inst
->saturate
= instr
->dest
.saturate
;
850 assert(!instr
->dest
.saturate
);
852 /* Straightforward since the source can be assumed to be either
853 * strictly >= 0 or strictly <= 0 depending on the setting of the
856 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
858 inst
= (op
[0].negate
)
859 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
860 : bld
.MOV(result
, brw_imm_f(1.0f
));
862 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
863 } else if (type_sz(op
[0].type
) < 8) {
864 /* AND(val, 0x80000000) gives the sign bit.
866 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
869 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
871 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
872 op
[0].type
= BRW_REGISTER_TYPE_UD
;
873 result
.type
= BRW_REGISTER_TYPE_UD
;
874 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
876 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
877 inst
->predicate
= BRW_PREDICATE_NORMAL
;
879 /* For doubles we do the same but we need to consider:
881 * - 2-src instructions can't operate with 64-bit immediates
882 * - The sign is encoded in the high 32-bit of each DF
883 * - We need to produce a DF result.
886 fs_reg zero
= vgrf(glsl_type::double_type
);
887 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
888 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
890 bld
.MOV(result
, zero
);
892 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
893 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
894 brw_imm_ud(0x80000000u
));
896 set_predicate(BRW_PREDICATE_NORMAL
,
897 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
903 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
904 * -> non-negative val generates 0x00000000.
905 * Predicated OR sets 1 if val is positive.
907 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
908 assert(bit_size
== 32 || bit_size
== 16);
910 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
911 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
912 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
914 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
915 bld
.ASR(result
, op
[0], shift
);
916 inst
= bld
.OR(result
, result
, one
);
917 inst
->predicate
= BRW_PREDICATE_NORMAL
;
922 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
923 inst
->saturate
= instr
->dest
.saturate
;
927 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
928 inst
->saturate
= instr
->dest
.saturate
;
932 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
933 inst
->saturate
= instr
->dest
.saturate
;
937 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
938 inst
->saturate
= instr
->dest
.saturate
;
942 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
943 inst
->saturate
= instr
->dest
.saturate
;
947 if (fs_key
->high_quality_derivatives
) {
948 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
950 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
952 inst
->saturate
= instr
->dest
.saturate
;
954 case nir_op_fddx_fine
:
955 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
956 inst
->saturate
= instr
->dest
.saturate
;
958 case nir_op_fddx_coarse
:
959 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
960 inst
->saturate
= instr
->dest
.saturate
;
963 if (fs_key
->high_quality_derivatives
) {
964 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
966 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
968 inst
->saturate
= instr
->dest
.saturate
;
970 case nir_op_fddy_fine
:
971 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
972 inst
->saturate
= instr
->dest
.saturate
;
974 case nir_op_fddy_coarse
:
975 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
976 inst
->saturate
= instr
->dest
.saturate
;
981 inst
= bld
.ADD(result
, op
[0], op
[1]);
982 inst
->saturate
= instr
->dest
.saturate
;
986 inst
= bld
.MUL(result
, op
[0], op
[1]);
987 inst
->saturate
= instr
->dest
.saturate
;
991 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
992 bld
.MUL(result
, op
[0], op
[1]);
995 case nir_op_imul_high
:
996 case nir_op_umul_high
:
997 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
998 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1003 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1004 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1007 case nir_op_uadd_carry
:
1008 unreachable("Should have been lowered by carry_to_arith().");
1010 case nir_op_usub_borrow
:
1011 unreachable("Should have been lowered by borrow_to_arith().");
1015 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1016 * appears that our hardware just does the right thing for signed
1019 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1020 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1024 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1025 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1027 /* Math instructions don't support conditional mod */
1028 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1029 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1031 /* Now, we need to determine if signs of the sources are different.
1032 * When we XOR the sources, the top bit is 0 if they are the same and 1
1033 * if they are different. We can then use a conditional modifier to
1034 * turn that into a predicate. This leads us to an XOR.l instruction.
1036 * Technically, according to the PRM, you're not allowed to use .l on a
1037 * XOR instruction. However, emperical experiments and Curro's reading
1038 * of the simulator source both indicate that it's safe.
1040 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1041 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1042 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1043 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1045 /* If the result of the initial remainder operation is non-zero and the
1046 * two sources have different signs, add in a copy of op[1] to get the
1047 * final integer modulus value.
1049 inst
= bld
.ADD(result
, result
, op
[1]);
1050 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1058 fs_reg dest
= result
;
1060 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1062 dest
= bld
.vgrf(op
[0].type
, 1);
1064 brw_conditional_mod cond
;
1065 switch (instr
->op
) {
1067 cond
= BRW_CONDITIONAL_L
;
1070 cond
= BRW_CONDITIONAL_GE
;
1073 cond
= BRW_CONDITIONAL_Z
;
1076 cond
= BRW_CONDITIONAL_NZ
;
1079 unreachable("bad opcode");
1082 bld
.CMP(dest
, op
[0], op
[1], cond
);
1084 if (bit_size
> 32) {
1085 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1086 } else if(bit_size
< 32) {
1087 /* When we convert the result to 32-bit we need to be careful and do
1088 * it as a signed conversion to get sign extension (for 32-bit true)
1090 const brw_reg_type src_type
=
1091 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1093 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1104 fs_reg dest
= result
;
1106 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1108 dest
= bld
.vgrf(op
[0].type
, 1);
1110 brw_conditional_mod cond
;
1111 switch (instr
->op
) {
1114 cond
= BRW_CONDITIONAL_L
;
1118 cond
= BRW_CONDITIONAL_GE
;
1121 cond
= BRW_CONDITIONAL_Z
;
1124 cond
= BRW_CONDITIONAL_NZ
;
1127 unreachable("bad opcode");
1129 bld
.CMP(dest
, op
[0], op
[1], cond
);
1131 if (bit_size
> 32) {
1132 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1133 } else if (bit_size
< 32) {
1134 /* When we convert the result to 32-bit we need to be careful and do
1135 * it as a signed conversion to get sign extension (for 32-bit true)
1137 const brw_reg_type src_type
=
1138 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1140 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1146 if (devinfo
->gen
>= 8) {
1147 op
[0] = resolve_source_modifiers(op
[0]);
1149 bld
.NOT(result
, op
[0]);
1152 if (devinfo
->gen
>= 8) {
1153 op
[0] = resolve_source_modifiers(op
[0]);
1154 op
[1] = resolve_source_modifiers(op
[1]);
1156 bld
.XOR(result
, op
[0], op
[1]);
1159 if (devinfo
->gen
>= 8) {
1160 op
[0] = resolve_source_modifiers(op
[0]);
1161 op
[1] = resolve_source_modifiers(op
[1]);
1163 bld
.OR(result
, op
[0], op
[1]);
1166 if (devinfo
->gen
>= 8) {
1167 op
[0] = resolve_source_modifiers(op
[0]);
1168 op
[1] = resolve_source_modifiers(op
[1]);
1170 bld
.AND(result
, op
[0], op
[1]);
1176 case nir_op_ball_fequal2
:
1177 case nir_op_ball_iequal2
:
1178 case nir_op_ball_fequal3
:
1179 case nir_op_ball_iequal3
:
1180 case nir_op_ball_fequal4
:
1181 case nir_op_ball_iequal4
:
1182 case nir_op_bany_fnequal2
:
1183 case nir_op_bany_inequal2
:
1184 case nir_op_bany_fnequal3
:
1185 case nir_op_bany_inequal3
:
1186 case nir_op_bany_fnequal4
:
1187 case nir_op_bany_inequal4
:
1188 unreachable("Lowered by nir_lower_alu_reductions");
1190 case nir_op_fnoise1_1
:
1191 case nir_op_fnoise1_2
:
1192 case nir_op_fnoise1_3
:
1193 case nir_op_fnoise1_4
:
1194 case nir_op_fnoise2_1
:
1195 case nir_op_fnoise2_2
:
1196 case nir_op_fnoise2_3
:
1197 case nir_op_fnoise2_4
:
1198 case nir_op_fnoise3_1
:
1199 case nir_op_fnoise3_2
:
1200 case nir_op_fnoise3_3
:
1201 case nir_op_fnoise3_4
:
1202 case nir_op_fnoise4_1
:
1203 case nir_op_fnoise4_2
:
1204 case nir_op_fnoise4_3
:
1205 case nir_op_fnoise4_4
:
1206 unreachable("not reached: should be handled by lower_noise");
1209 unreachable("not reached: should be handled by ldexp_to_arith()");
1212 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1213 inst
->saturate
= instr
->dest
.saturate
;
1217 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1218 inst
->saturate
= instr
->dest
.saturate
;
1223 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1224 if (bit_size
== 64) {
1225 /* two-argument instructions can't take 64-bit immediates */
1229 if (instr
->op
== nir_op_f2b
) {
1230 zero
= vgrf(glsl_type::double_type
);
1231 tmp
= vgrf(glsl_type::double_type
);
1232 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1234 zero
= vgrf(glsl_type::int64_t_type
);
1235 tmp
= vgrf(glsl_type::int64_t_type
);
1236 bld
.MOV(zero
, brw_imm_q(0));
1239 /* A SIMD16 execution needs to be split in two instructions, so use
1240 * a vgrf instead of the flag register as dst so instruction splitting
1243 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1244 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1247 if (bit_size
== 32) {
1248 zero
= instr
->op
== nir_op_f2b
? brw_imm_f(0.0f
) : brw_imm_d(0);
1250 assert(bit_size
== 16);
1251 zero
= instr
->op
== nir_op_f2b
?
1252 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1254 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1260 inst
= bld
.RNDZ(result
, op
[0]);
1261 inst
->saturate
= instr
->dest
.saturate
;
1264 case nir_op_fceil
: {
1265 op
[0].negate
= !op
[0].negate
;
1266 fs_reg temp
= vgrf(glsl_type::float_type
);
1267 bld
.RNDD(temp
, op
[0]);
1269 inst
= bld
.MOV(result
, temp
);
1270 inst
->saturate
= instr
->dest
.saturate
;
1274 inst
= bld
.RNDD(result
, op
[0]);
1275 inst
->saturate
= instr
->dest
.saturate
;
1278 inst
= bld
.FRC(result
, op
[0]);
1279 inst
->saturate
= instr
->dest
.saturate
;
1281 case nir_op_fround_even
:
1282 inst
= bld
.RNDE(result
, op
[0]);
1283 inst
->saturate
= instr
->dest
.saturate
;
1286 case nir_op_fquantize2f16
: {
1287 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1288 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1289 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1291 /* The destination stride must be at least as big as the source stride. */
1292 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1295 /* Check for denormal */
1296 fs_reg abs_src0
= op
[0];
1297 abs_src0
.abs
= true;
1298 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1300 /* Get the appropriately signed zero */
1301 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1302 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1303 brw_imm_ud(0x80000000));
1304 /* Do the actual F32 -> F16 -> F32 conversion */
1305 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1306 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1307 /* Select that or zero based on normal status */
1308 inst
= bld
.SEL(result
, zero
, tmp32
);
1309 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1310 inst
->saturate
= instr
->dest
.saturate
;
1317 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1318 inst
->saturate
= instr
->dest
.saturate
;
1324 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1325 inst
->saturate
= instr
->dest
.saturate
;
1328 case nir_op_pack_snorm_2x16
:
1329 case nir_op_pack_snorm_4x8
:
1330 case nir_op_pack_unorm_2x16
:
1331 case nir_op_pack_unorm_4x8
:
1332 case nir_op_unpack_snorm_2x16
:
1333 case nir_op_unpack_snorm_4x8
:
1334 case nir_op_unpack_unorm_2x16
:
1335 case nir_op_unpack_unorm_4x8
:
1336 case nir_op_unpack_half_2x16
:
1337 case nir_op_pack_half_2x16
:
1338 unreachable("not reached: should be handled by lower_packing_builtins");
1340 case nir_op_unpack_half_2x16_split_x
:
1341 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1342 inst
->saturate
= instr
->dest
.saturate
;
1344 case nir_op_unpack_half_2x16_split_y
:
1345 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1346 inst
->saturate
= instr
->dest
.saturate
;
1349 case nir_op_pack_64_2x32_split
:
1350 case nir_op_pack_32_2x16_split
:
1351 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1354 case nir_op_unpack_64_2x32_split_x
:
1355 case nir_op_unpack_64_2x32_split_y
: {
1356 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1357 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1359 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1363 case nir_op_unpack_32_2x16_split_x
:
1364 case nir_op_unpack_32_2x16_split_y
: {
1365 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1366 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1368 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1373 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1374 inst
->saturate
= instr
->dest
.saturate
;
1377 case nir_op_bitfield_reverse
:
1378 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1379 bld
.BFREV(result
, op
[0]);
1382 case nir_op_bit_count
:
1383 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1384 bld
.CBIT(result
, op
[0]);
1387 case nir_op_ufind_msb
: {
1388 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1389 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1393 case nir_op_ifind_msb
: {
1394 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1396 if (devinfo
->gen
< 7) {
1397 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1399 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1401 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1402 * count from the LSB side. If FBH didn't return an error
1403 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1404 * count into an LSB count.
1406 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1408 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1409 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1410 inst
->src
[0].negate
= true;
1415 case nir_op_find_lsb
:
1416 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1418 if (devinfo
->gen
< 7) {
1419 fs_reg temp
= vgrf(glsl_type::int_type
);
1421 /* (x & -x) generates a value that consists of only the LSB of x.
1422 * For all powers of 2, findMSB(y) == findLSB(y).
1424 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1425 fs_reg negated_src
= src
;
1427 /* One must be negated, and the other must be non-negated. It
1428 * doesn't matter which is which.
1430 negated_src
.negate
= true;
1433 bld
.AND(temp
, src
, negated_src
);
1434 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1436 bld
.FBL(result
, op
[0]);
1440 case nir_op_ubitfield_extract
:
1441 case nir_op_ibitfield_extract
:
1442 unreachable("should have been lowered");
1445 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1446 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1449 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1450 bld
.BFI1(result
, op
[0], op
[1]);
1453 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1454 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1457 case nir_op_bitfield_insert
:
1458 unreachable("not reached: should have been lowered");
1463 fs_reg shift_count
= op
[1];
1465 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1466 if (op
[1].file
== VGRF
&&
1467 (result
.type
== BRW_REGISTER_TYPE_Q
||
1468 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1469 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1470 BRW_REGISTER_TYPE_UD
);
1471 shift_count
.stride
= 2;
1472 bld
.MOV(shift_count
, op
[1]);
1476 switch (instr
->op
) {
1478 bld
.SHL(result
, op
[0], shift_count
);
1481 bld
.ASR(result
, op
[0], shift_count
);
1484 bld
.SHR(result
, op
[0], shift_count
);
1487 unreachable("not reached");
1492 case nir_op_pack_half_2x16_split
:
1493 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1497 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1498 inst
->saturate
= instr
->dest
.saturate
;
1502 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1503 inst
->saturate
= instr
->dest
.saturate
;
1507 if (optimize_frontfacing_ternary(instr
, result
))
1510 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1511 inst
= bld
.SEL(result
, op
[1], op
[2]);
1512 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1515 case nir_op_extract_u8
:
1516 case nir_op_extract_i8
: {
1517 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1518 assert(byte
!= NULL
);
1523 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1524 * Use two instructions and a word or DWord intermediate integer type.
1526 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1527 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1529 if (instr
->op
== nir_op_extract_i8
) {
1530 /* If we need to sign extend, extract to a word first */
1531 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1532 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
->u32
[0]));
1533 bld
.MOV(result
, w_temp
);
1535 /* Otherwise use an AND with 0xff and a word type */
1536 bld
.AND(result
, subscript(op
[0], type
, byte
->u32
[0] / 2), brw_imm_uw(0xff));
1539 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1540 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1545 case nir_op_extract_u16
:
1546 case nir_op_extract_i16
: {
1547 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1548 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1549 assert(word
!= NULL
);
1550 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1555 unreachable("unhandled instruction");
1558 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1559 * to sign extend the low bit to 0/~0
1561 if (devinfo
->gen
<= 5 &&
1562 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1563 fs_reg masked
= vgrf(glsl_type::int_type
);
1564 bld
.AND(masked
, result
, brw_imm_d(1));
1565 masked
.negate
= true;
1566 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1571 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1572 nir_load_const_instr
*instr
)
1574 const brw_reg_type reg_type
=
1575 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1576 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1578 switch (instr
->def
.bit_size
) {
1580 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1581 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1585 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1586 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1590 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1591 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1595 assert(devinfo
->gen
>= 7);
1596 if (devinfo
->gen
== 7) {
1597 /* We don't get 64-bit integer types until gen8 */
1598 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1599 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1600 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1603 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1604 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1609 unreachable("Invalid bit size");
1612 nir_ssa_values
[instr
->def
.index
] = reg
;
1616 fs_visitor::get_nir_src(const nir_src
&src
)
1620 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1621 const brw_reg_type reg_type
=
1622 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1623 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1625 reg
= nir_ssa_values
[src
.ssa
->index
];
1628 /* We don't handle indirects on locals */
1629 assert(src
.reg
.indirect
== NULL
);
1630 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1631 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1634 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1635 /* The only 64-bit type available on gen7 is DF, so use that. */
1636 reg
.type
= BRW_REGISTER_TYPE_DF
;
1638 /* To avoid floating-point denorm flushing problems, set the type by
1639 * default to an integer type - instructions that need floating point
1640 * semantics will set this to F if they need to
1642 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1643 BRW_REGISTER_TYPE_D
);
1650 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1652 * This function should not be called on any value which may be 64 bits.
1653 * We could theoretically support 64-bit on gen8+ but we choose not to
1654 * because it wouldn't work in general (no gen7 support) and there are
1655 * enough restrictions in 64-bit immediates that you can't take the return
1656 * value and treat it the same as the result of get_nir_src().
1659 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1661 nir_const_value
*val
= nir_src_as_const_value(src
);
1662 assert(nir_src_bit_size(src
) == 32);
1663 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1667 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1670 const brw_reg_type reg_type
=
1671 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1672 dest
.ssa
.bit_size
== 8 ?
1673 BRW_REGISTER_TYPE_D
:
1674 BRW_REGISTER_TYPE_F
);
1675 nir_ssa_values
[dest
.ssa
.index
] =
1676 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1677 return nir_ssa_values
[dest
.ssa
.index
];
1679 /* We don't handle indirects on locals */
1680 assert(dest
.reg
.indirect
== NULL
);
1681 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1682 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1687 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1690 for (unsigned i
= 0; i
< 4; i
++) {
1691 if (!((wr_mask
>> i
) & 1))
1694 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1695 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1696 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1697 if (new_inst
->src
[j
].file
== VGRF
)
1698 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1705 emit_pixel_interpolater_send(const fs_builder
&bld
,
1710 glsl_interp_mode interpolation
)
1712 struct brw_wm_prog_data
*wm_prog_data
=
1713 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1715 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1716 /* 2 floats per slot returned */
1717 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1718 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1720 wm_prog_data
->pulls_bary
= true;
1726 * Computes 1 << x, given a D/UD register containing some value x.
1729 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1731 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1733 fs_reg result
= bld
.vgrf(x
.type
, 1);
1734 fs_reg one
= bld
.vgrf(x
.type
, 1);
1736 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1737 bld
.SHL(result
, one
, x
);
1742 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1744 assert(stage
== MESA_SHADER_GEOMETRY
);
1746 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1748 if (gs_compile
->control_data_header_size_bits
== 0)
1751 /* We can only do EndPrimitive() functionality when the control data
1752 * consists of cut bits. Fortunately, the only time it isn't is when the
1753 * output type is points, in which case EndPrimitive() is a no-op.
1755 if (gs_prog_data
->control_data_format
!=
1756 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1760 /* Cut bits use one bit per vertex. */
1761 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1763 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1764 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1766 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1767 * vertex n, 0 otherwise. So all we need to do here is mark bit
1768 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1769 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1770 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1772 * Note that if EndPrimitive() is called before emitting any vertices, this
1773 * will cause us to set bit 31 of the control_data_bits register to 1.
1774 * That's fine because:
1776 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1777 * output, so the hardware will ignore cut bit 31.
1779 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1780 * last vertex, so setting cut bit 31 has no effect (since the primitive
1781 * is automatically ended when the GS terminates).
1783 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1784 * control_data_bits register to 0 when the first vertex is emitted.
1787 const fs_builder abld
= bld
.annotate("end primitive");
1789 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1790 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1791 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1792 fs_reg mask
= intexp2(abld
, prev_count
);
1793 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1794 * attention to the lower 5 bits of its second source argument, so on this
1795 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1796 * ((vertex_count - 1) % 32).
1798 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1802 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1804 assert(stage
== MESA_SHADER_GEOMETRY
);
1805 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1807 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1809 const fs_builder abld
= bld
.annotate("emit control data bits");
1810 const fs_builder fwa_bld
= bld
.exec_all();
1812 /* We use a single UD register to accumulate control data bits (32 bits
1813 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1816 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1817 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1818 * use the Channel Mask phase to enable/disable which DWord within that
1819 * group to write. (Remember, different SIMD8 channels may have emitted
1820 * different numbers of vertices, so we may need per-slot offsets.)
1822 * Channel masking presents an annoying problem: we may have to replicate
1823 * the data up to 4 times:
1825 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1827 * To avoid penalizing shaders that emit a small number of vertices, we
1828 * can avoid these sometimes: if the size of the control data header is
1829 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1830 * land in the same 128-bit group, so we can skip per-slot offsets.
1832 * Similarly, if the control data header is <= 32 bits, there is only one
1833 * DWord, so we can skip channel masks.
1835 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1837 fs_reg channel_mask
, per_slot_offset
;
1839 if (gs_compile
->control_data_header_size_bits
> 32) {
1840 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1841 channel_mask
= vgrf(glsl_type::uint_type
);
1844 if (gs_compile
->control_data_header_size_bits
> 128) {
1845 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1846 per_slot_offset
= vgrf(glsl_type::uint_type
);
1849 /* Figure out which DWord we're trying to write to using the formula:
1851 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1853 * Since bits_per_vertex is a power of two, and is known at compile
1854 * time, this can be optimized to:
1856 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1858 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1859 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1860 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1861 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1862 unsigned log2_bits_per_vertex
=
1863 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1864 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1866 if (per_slot_offset
.file
!= BAD_FILE
) {
1867 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1868 * the appropriate OWord within the control data header.
1870 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1873 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1874 * write to the appropriate DWORD within the OWORD.
1876 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1877 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1878 channel_mask
= intexp2(fwa_bld
, channel
);
1879 /* Then the channel masks need to be in bits 23:16. */
1880 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1883 /* Store the control data bits in the message payload and send it. */
1885 if (channel_mask
.file
!= BAD_FILE
)
1886 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1887 if (per_slot_offset
.file
!= BAD_FILE
)
1890 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1891 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1893 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1894 if (per_slot_offset
.file
!= BAD_FILE
)
1895 sources
[i
++] = per_slot_offset
;
1896 if (channel_mask
.file
!= BAD_FILE
)
1897 sources
[i
++] = channel_mask
;
1899 sources
[i
++] = this->control_data_bits
;
1902 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1903 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1905 /* We need to increment Global Offset by 256-bits to make room for
1906 * Broadwell's extra "Vertex Count" payload at the beginning of the
1907 * URB entry. Since this is an OWord message, Global Offset is counted
1908 * in 128-bit units, so we must set it to 2.
1910 if (gs_prog_data
->static_vertex_count
== -1)
1915 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1918 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1920 /* Note: we are calling this *before* increasing vertex_count, so
1921 * this->vertex_count == vertex_count - 1 in the formula above.
1924 /* Stream mode uses 2 bits per vertex */
1925 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1927 /* Must be a valid stream */
1928 assert(stream_id
< MAX_VERTEX_STREAMS
);
1930 /* Control data bits are initialized to 0 so we don't have to set any
1931 * bits when sending vertices to stream 0.
1936 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1938 /* reg::sid = stream_id */
1939 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1940 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1942 /* reg:shift_count = 2 * (vertex_count - 1) */
1943 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1944 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1946 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1947 * attention to the lower 5 bits of its second source argument, so on this
1948 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1949 * stream_id << ((2 * (vertex_count - 1)) % 32).
1951 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1952 abld
.SHL(mask
, sid
, shift_count
);
1953 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1957 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1960 assert(stage
== MESA_SHADER_GEOMETRY
);
1962 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1964 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1965 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1967 /* Haswell and later hardware ignores the "Render Stream Select" bits
1968 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1969 * and instead sends all primitives down the pipeline for rasterization.
1970 * If the SOL stage is enabled, "Render Stream Select" is honored and
1971 * primitives bound to non-zero streams are discarded after stream output.
1973 * Since the only purpose of primives sent to non-zero streams is to
1974 * be recorded by transform feedback, we can simply discard all geometry
1975 * bound to these streams when transform feedback is disabled.
1977 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1980 /* If we're outputting 32 control data bits or less, then we can wait
1981 * until the shader is over to output them all. Otherwise we need to
1982 * output them as we go. Now is the time to do it, since we're about to
1983 * output the vertex_count'th vertex, so it's guaranteed that the
1984 * control data bits associated with the (vertex_count - 1)th vertex are
1987 if (gs_compile
->control_data_header_size_bits
> 32) {
1988 const fs_builder abld
=
1989 bld
.annotate("emit vertex: emit control data bits");
1991 /* Only emit control data bits if we've finished accumulating a batch
1992 * of 32 bits. This is the case when:
1994 * (vertex_count * bits_per_vertex) % 32 == 0
1996 * (in other words, when the last 5 bits of vertex_count *
1997 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1998 * integer n (which is always the case, since bits_per_vertex is
1999 * always 1 or 2), this is equivalent to requiring that the last 5-n
2000 * bits of vertex_count are 0:
2002 * vertex_count & (2^(5-n) - 1) == 0
2004 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2007 * vertex_count & (32 / bits_per_vertex - 1) == 0
2009 * TODO: If vertex_count is an immediate, we could do some of this math
2010 * at compile time...
2013 abld
.AND(bld
.null_reg_d(), vertex_count
,
2014 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2015 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2017 abld
.IF(BRW_PREDICATE_NORMAL
);
2018 /* If vertex_count is 0, then no control data bits have been
2019 * accumulated yet, so we can skip emitting them.
2021 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2022 BRW_CONDITIONAL_NEQ
);
2023 abld
.IF(BRW_PREDICATE_NORMAL
);
2024 emit_gs_control_data_bits(vertex_count
);
2025 abld
.emit(BRW_OPCODE_ENDIF
);
2027 /* Reset control_data_bits to 0 so we can start accumulating a new
2030 * Note: in the case where vertex_count == 0, this neutralizes the
2031 * effect of any call to EndPrimitive() that the shader may have
2032 * made before outputting its first vertex.
2034 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2035 inst
->force_writemask_all
= true;
2036 abld
.emit(BRW_OPCODE_ENDIF
);
2039 emit_urb_writes(vertex_count
);
2041 /* In stream mode we have to set control data bits for all vertices
2042 * unless we have disabled control data bits completely (which we do
2043 * do for GL_POINTS outputs that don't use streams).
2045 if (gs_compile
->control_data_header_size_bits
> 0 &&
2046 gs_prog_data
->control_data_format
==
2047 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2048 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2053 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2054 const nir_src
&vertex_src
,
2055 unsigned base_offset
,
2056 const nir_src
&offset_src
,
2057 unsigned num_components
,
2058 unsigned first_component
)
2060 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2062 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2063 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2064 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2066 /* TODO: figure out push input layout for invocations == 1 */
2067 /* TODO: make this work with 64-bit inputs */
2068 if (gs_prog_data
->invocations
== 1 &&
2069 type_sz(dst
.type
) <= 4 &&
2070 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2071 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2072 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2073 vertex_const
->u32
[0] * push_reg_count
;
2074 for (unsigned i
= 0; i
< num_components
; i
++) {
2075 bld
.MOV(offset(dst
, bld
, i
),
2076 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2081 /* Resort to the pull model. Ensure the VUE handles are provided. */
2082 assert(gs_prog_data
->base
.include_vue_handles
);
2084 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2085 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2087 if (gs_prog_data
->invocations
== 1) {
2089 /* The vertex index is constant; just select the proper URB handle. */
2091 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2092 BRW_REGISTER_TYPE_UD
);
2094 /* The vertex index is non-constant. We need to use indirect
2095 * addressing to fetch the proper URB handle.
2097 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2098 * indicating that channel <n> should read the handle from
2099 * DWord <n>. We convert that to bytes by multiplying by 4.
2101 * Next, we convert the vertex index to bytes by multiplying
2102 * by 32 (shifting by 5), and add the two together. This is
2103 * the final indirect byte offset.
2105 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2106 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2107 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2108 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2110 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2111 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2112 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2113 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2114 /* Convert vertex_index to bytes (multiply by 32) */
2115 bld
.SHL(vertex_offset_bytes
,
2116 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2118 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2120 /* Use first_icp_handle as the base offset. There is one register
2121 * of URB handles per vertex, so inform the register allocator that
2122 * we might read up to nir->info.gs.vertices_in registers.
2124 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2125 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2126 fs_reg(icp_offset_bytes
),
2127 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2130 assert(gs_prog_data
->invocations
> 1);
2133 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2135 retype(brw_vec1_grf(first_icp_handle
+
2136 vertex_const
->i32
[0] / 8,
2137 vertex_const
->i32
[0] % 8),
2138 BRW_REGISTER_TYPE_UD
));
2140 /* The vertex index is non-constant. We need to use indirect
2141 * addressing to fetch the proper URB handle.
2144 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2146 /* Convert vertex_index to bytes (multiply by 4) */
2147 bld
.SHL(icp_offset_bytes
,
2148 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2151 /* Use first_icp_handle as the base offset. There is one DWord
2152 * of URB handles per vertex, so inform the register allocator that
2153 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2155 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2156 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2157 fs_reg(icp_offset_bytes
),
2158 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2165 fs_reg tmp_dst
= dst
;
2166 fs_reg indirect_offset
= get_nir_src(offset_src
);
2167 unsigned num_iterations
= 1;
2168 unsigned orig_num_components
= num_components
;
2170 if (type_sz(dst
.type
) == 8) {
2171 if (num_components
> 2) {
2175 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2177 first_component
= first_component
/ 2;
2180 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2182 /* Constant indexing - use global offset. */
2183 if (first_component
!= 0) {
2184 unsigned read_components
= num_components
+ first_component
;
2185 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2186 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2187 inst
->size_written
= read_components
*
2188 tmp
.component_size(inst
->exec_size
);
2189 for (unsigned i
= 0; i
< num_components
; i
++) {
2190 bld
.MOV(offset(tmp_dst
, bld
, i
),
2191 offset(tmp
, bld
, i
+ first_component
));
2194 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2196 inst
->size_written
= num_components
*
2197 tmp_dst
.component_size(inst
->exec_size
);
2199 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2202 /* Indirect indexing - use per-slot offsets as well. */
2203 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2204 unsigned read_components
= num_components
+ first_component
;
2205 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2206 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2207 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2208 if (first_component
!= 0) {
2209 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2211 inst
->size_written
= read_components
*
2212 tmp
.component_size(inst
->exec_size
);
2213 for (unsigned i
= 0; i
< num_components
; i
++) {
2214 bld
.MOV(offset(tmp_dst
, bld
, i
),
2215 offset(tmp
, bld
, i
+ first_component
));
2218 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2220 inst
->size_written
= num_components
*
2221 tmp_dst
.component_size(inst
->exec_size
);
2223 inst
->offset
= base_offset
;
2227 if (type_sz(dst
.type
) == 8) {
2228 shuffle_from_32bit_read(bld
,
2229 offset(dst
, bld
, iter
* 2),
2230 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2235 if (num_iterations
> 1) {
2236 num_components
= orig_num_components
- 2;
2240 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2241 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2242 indirect_offset
= new_indirect
;
2249 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2251 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2252 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2255 /* The only constant offset we should find is 0. brw_nir.c's
2256 * add_const_offset_to_base() will fold other constant offsets
2257 * into instr->const_index[0].
2259 assert(const_value
->u32
[0] == 0);
2263 return get_nir_src(*offset_src
);
2267 do_untyped_vector_read(const fs_builder
&bld
,
2269 const fs_reg surf_index
,
2270 const fs_reg offset_reg
,
2271 unsigned num_components
)
2273 if (type_sz(dest
.type
) <= 2) {
2274 assert(dest
.stride
== 1);
2275 boolean is_const_offset
= offset_reg
.file
== BRW_IMMEDIATE_VALUE
;
2277 if (is_const_offset
) {
2278 uint32_t start
= offset_reg
.ud
& ~3;
2279 uint32_t end
= offset_reg
.ud
+ num_components
* type_sz(dest
.type
);
2280 end
= ALIGN(end
, 4);
2281 assert (end
- start
<= 16);
2283 /* At this point we have 16-bit component/s that have constant
2284 * offset aligned to 4-bytes that can be read with untyped_reads.
2285 * untyped_read message requires 32-bit aligned offsets.
2287 unsigned first_component
= (offset_reg
.ud
& 3) / type_sz(dest
.type
);
2288 unsigned num_components_32bit
= (end
- start
) / 4;
2290 fs_reg read_result
=
2291 emit_untyped_read(bld
, surf_index
, brw_imm_ud(start
),
2293 num_components_32bit
,
2294 BRW_PREDICATE_NONE
);
2295 shuffle_from_32bit_read(bld
, dest
, read_result
, first_component
,
2298 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2299 for (unsigned i
= 0; i
< num_components
; i
++) {
2301 bld
.MOV(read_offset
, offset_reg
);
2303 bld
.ADD(read_offset
, offset_reg
,
2304 brw_imm_ud(i
* type_sz(dest
.type
)));
2306 /* Non constant offsets are not guaranteed to be aligned 32-bits
2307 * so they are read using one byte_scattered_read message
2308 * for each component.
2310 fs_reg read_result
=
2311 emit_byte_scattered_read(bld
, surf_index
, read_offset
,
2313 type_sz(dest
.type
) * 8 /* bit_size */,
2314 BRW_PREDICATE_NONE
);
2315 bld
.MOV(offset(dest
, bld
, i
),
2316 subscript (read_result
, dest
.type
, 0));
2319 } else if (type_sz(dest
.type
) == 4) {
2320 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2323 BRW_PREDICATE_NONE
);
2324 read_result
.type
= dest
.type
;
2325 for (unsigned i
= 0; i
< num_components
; i
++)
2326 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2327 } else if (type_sz(dest
.type
) == 8) {
2328 /* Reading a dvec, so we need to:
2330 * 1. Multiply num_components by 2, to account for the fact that we
2331 * need to read 64-bit components.
2332 * 2. Shuffle the result of the load to form valid 64-bit elements
2333 * 3. Emit a second load (for components z/w) if needed.
2335 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2336 bld
.MOV(read_offset
, offset_reg
);
2338 int iters
= num_components
<= 2 ? 1 : 2;
2340 /* Load the dvec, the first iteration loads components x/y, the second
2341 * iteration, if needed, loads components z/w
2343 for (int it
= 0; it
< iters
; it
++) {
2344 /* Compute number of components to read in this iteration */
2345 int iter_components
= MIN2(2, num_components
);
2346 num_components
-= iter_components
;
2348 /* Read. Since this message reads 32-bit components, we need to
2349 * read twice as many components.
2351 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2353 iter_components
* 2,
2354 BRW_PREDICATE_NONE
);
2356 /* Shuffle the 32-bit load result into valid 64-bit data */
2357 shuffle_from_32bit_read(bld
, offset(dest
, bld
, it
* 2),
2358 read_result
, 0, iter_components
);
2360 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2363 unreachable("Unsupported type");
2368 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2369 nir_intrinsic_instr
*instr
)
2371 assert(stage
== MESA_SHADER_VERTEX
);
2374 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2375 dest
= get_nir_dest(instr
->dest
);
2377 switch (instr
->intrinsic
) {
2378 case nir_intrinsic_load_vertex_id
:
2379 case nir_intrinsic_load_base_vertex
:
2380 unreachable("should be lowered by nir_lower_system_values()");
2382 case nir_intrinsic_load_input
: {
2383 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2384 unsigned first_component
= nir_intrinsic_component(instr
);
2385 unsigned num_components
= instr
->num_components
;
2387 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2388 assert(const_offset
&& "Indirect input loads not allowed");
2389 src
= offset(src
, bld
, const_offset
->u32
[0]);
2391 if (type_sz(dest
.type
) == 8)
2392 first_component
/= 2;
2394 /* For 16-bit support maybe a temporary will be needed to copy from
2397 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2398 first_component
, num_components
);
2402 case nir_intrinsic_load_vertex_id_zero_base
:
2403 case nir_intrinsic_load_instance_id
:
2404 case nir_intrinsic_load_base_instance
:
2405 case nir_intrinsic_load_draw_id
:
2406 case nir_intrinsic_load_first_vertex
:
2407 case nir_intrinsic_load_is_indexed_draw
:
2408 unreachable("lowered by brw_nir_lower_vs_inputs");
2411 nir_emit_intrinsic(bld
, instr
);
2417 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2418 nir_intrinsic_instr
*instr
)
2420 assert(stage
== MESA_SHADER_TESS_CTRL
);
2421 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2422 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2425 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2426 dst
= get_nir_dest(instr
->dest
);
2428 switch (instr
->intrinsic
) {
2429 case nir_intrinsic_load_primitive_id
:
2430 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2432 case nir_intrinsic_load_invocation_id
:
2433 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2435 case nir_intrinsic_load_patch_vertices_in
:
2436 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2437 brw_imm_d(tcs_key
->input_vertices
));
2440 case nir_intrinsic_barrier
: {
2441 if (tcs_prog_data
->instances
== 1)
2444 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2445 fs_reg m0_2
= component(m0
, 2);
2447 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2449 /* Zero the message header */
2450 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2452 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2453 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2454 brw_imm_ud(INTEL_MASK(16, 13)));
2456 /* Shift it up to bits 27:24. */
2457 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2459 /* Set the Barrier Count and the enable bit */
2460 chanbld
.OR(m0_2
, m0_2
,
2461 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2463 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2467 case nir_intrinsic_load_input
:
2468 unreachable("nir_lower_io should never give us these.");
2471 case nir_intrinsic_load_per_vertex_input
: {
2472 fs_reg indirect_offset
= get_indirect_offset(instr
);
2473 unsigned imm_offset
= instr
->const_index
[0];
2475 const nir_src
&vertex_src
= instr
->src
[0];
2476 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2483 /* Emit a MOV to resolve <0,1,0> regioning. */
2484 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2486 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2487 vertex_const
->i32
[0] & 7),
2488 BRW_REGISTER_TYPE_UD
));
2489 } else if (tcs_prog_data
->instances
== 1 &&
2490 vertex_src
.is_ssa
&&
2491 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2492 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2493 /* For the common case of only 1 instance, an array index of
2494 * gl_InvocationID means reading g1. Skip all the indirect work.
2496 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2498 /* The vertex index is non-constant. We need to use indirect
2499 * addressing to fetch the proper URB handle.
2501 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2503 /* Each ICP handle is a single DWord (4 bytes) */
2504 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2505 bld
.SHL(vertex_offset_bytes
,
2506 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2509 /* Start at g1. We might read up to 4 registers. */
2510 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2511 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2512 brw_imm_ud(4 * REG_SIZE
));
2515 /* We can only read two double components with each URB read, so
2516 * we send two read messages in that case, each one loading up to
2517 * two double components.
2519 unsigned num_iterations
= 1;
2520 unsigned num_components
= instr
->num_components
;
2521 unsigned first_component
= nir_intrinsic_component(instr
);
2522 fs_reg orig_dst
= dst
;
2523 if (type_sz(dst
.type
) == 8) {
2524 first_component
= first_component
/ 2;
2525 if (instr
->num_components
> 2) {
2530 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2534 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2535 if (indirect_offset
.file
== BAD_FILE
) {
2536 /* Constant indexing - use global offset. */
2537 if (first_component
!= 0) {
2538 unsigned read_components
= num_components
+ first_component
;
2539 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2540 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2541 for (unsigned i
= 0; i
< num_components
; i
++) {
2542 bld
.MOV(offset(dst
, bld
, i
),
2543 offset(tmp
, bld
, i
+ first_component
));
2546 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2548 inst
->offset
= imm_offset
;
2551 /* Indirect indexing - use per-slot offsets as well. */
2552 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2553 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2554 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2555 if (first_component
!= 0) {
2556 unsigned read_components
= num_components
+ first_component
;
2557 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2558 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2560 for (unsigned i
= 0; i
< num_components
; i
++) {
2561 bld
.MOV(offset(dst
, bld
, i
),
2562 offset(tmp
, bld
, i
+ first_component
));
2565 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2568 inst
->offset
= imm_offset
;
2571 inst
->size_written
= (num_components
+ first_component
) *
2572 inst
->dst
.component_size(inst
->exec_size
);
2574 /* If we are reading 64-bit data using 32-bit read messages we need
2575 * build proper 64-bit data elements by shuffling the low and high
2576 * 32-bit components around like we do for other things like UBOs
2579 if (type_sz(dst
.type
) == 8) {
2580 shuffle_from_32bit_read(bld
,
2581 offset(orig_dst
, bld
, iter
* 2),
2582 retype(dst
, BRW_REGISTER_TYPE_D
),
2586 /* Copy the temporary to the destination to deal with writemasking.
2588 * Also attempt to deal with gl_PointSize being in the .w component.
2590 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2591 assert(type_sz(dst
.type
) < 8);
2592 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2593 inst
->size_written
= 4 * REG_SIZE
;
2594 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2597 /* If we are loading double data and we need a second read message
2598 * adjust the write offset
2600 if (num_iterations
> 1) {
2601 num_components
= instr
->num_components
- 2;
2608 case nir_intrinsic_load_output
:
2609 case nir_intrinsic_load_per_vertex_output
: {
2610 fs_reg indirect_offset
= get_indirect_offset(instr
);
2611 unsigned imm_offset
= instr
->const_index
[0];
2612 unsigned first_component
= nir_intrinsic_component(instr
);
2615 if (indirect_offset
.file
== BAD_FILE
) {
2616 /* Replicate the patch handle to all enabled channels */
2617 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2618 bld
.MOV(patch_handle
,
2619 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2622 if (first_component
!= 0) {
2623 unsigned read_components
=
2624 instr
->num_components
+ first_component
;
2625 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2626 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2628 inst
->size_written
= read_components
* REG_SIZE
;
2629 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2630 bld
.MOV(offset(dst
, bld
, i
),
2631 offset(tmp
, bld
, i
+ first_component
));
2634 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2636 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2638 inst
->offset
= imm_offset
;
2642 /* Indirect indexing - use per-slot offsets as well. */
2643 const fs_reg srcs
[] = {
2644 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2647 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2648 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2649 if (first_component
!= 0) {
2650 unsigned read_components
=
2651 instr
->num_components
+ first_component
;
2652 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2653 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2655 inst
->size_written
= read_components
* REG_SIZE
;
2656 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2657 bld
.MOV(offset(dst
, bld
, i
),
2658 offset(tmp
, bld
, i
+ first_component
));
2661 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2663 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2665 inst
->offset
= imm_offset
;
2671 case nir_intrinsic_store_output
:
2672 case nir_intrinsic_store_per_vertex_output
: {
2673 fs_reg value
= get_nir_src(instr
->src
[0]);
2674 bool is_64bit
= (instr
->src
[0].is_ssa
?
2675 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2676 fs_reg indirect_offset
= get_indirect_offset(instr
);
2677 unsigned imm_offset
= instr
->const_index
[0];
2678 unsigned mask
= instr
->const_index
[1];
2679 unsigned header_regs
= 0;
2681 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2683 if (indirect_offset
.file
!= BAD_FILE
) {
2684 srcs
[header_regs
++] = indirect_offset
;
2690 unsigned num_components
= util_last_bit(mask
);
2693 /* We can only pack two 64-bit components in a single message, so send
2694 * 2 messages if we have more components
2696 unsigned num_iterations
= 1;
2697 unsigned iter_components
= num_components
;
2698 unsigned first_component
= nir_intrinsic_component(instr
);
2700 first_component
= first_component
/ 2;
2701 if (instr
->num_components
> 2) {
2703 iter_components
= 2;
2707 mask
= mask
<< first_component
;
2709 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2710 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2711 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2712 opcode
= indirect_offset
.file
!= BAD_FILE
?
2713 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2714 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2715 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2716 /* Expand the 64-bit mask to 32-bit channels. We only handle
2717 * two channels in each iteration, so we only care about X/Y.
2719 unsigned mask32
= 0;
2720 if (mask
& WRITEMASK_X
)
2721 mask32
|= WRITEMASK_XY
;
2722 if (mask
& WRITEMASK_Y
)
2723 mask32
|= WRITEMASK_ZW
;
2725 /* If the mask does not include any of the channels X or Y there
2726 * is nothing to do in this iteration. Move on to the next couple
2727 * of 64-bit channels.
2735 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2736 opcode
= indirect_offset
.file
!= BAD_FILE
?
2737 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2738 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2740 opcode
= indirect_offset
.file
!= BAD_FILE
?
2741 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2742 SHADER_OPCODE_URB_WRITE_SIMD8
;
2745 for (unsigned i
= 0; i
< iter_components
; i
++) {
2746 if (!(mask
& (1 << (i
+ first_component
))))
2750 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2752 /* We need to shuffle the 64-bit data to match the layout
2753 * expected by our 32-bit URB write messages. We use a temporary
2756 unsigned channel
= iter
* 2 + i
;
2757 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2759 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2760 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2761 offset(dest
, bld
, 1);
2766 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2767 (is_64bit
? 2 * first_component
: first_component
);
2769 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2770 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2772 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2773 inst
->offset
= imm_offset
;
2776 /* If this is a 64-bit attribute, select the next two 64-bit channels
2777 * to be handled in the next iteration.
2788 nir_emit_intrinsic(bld
, instr
);
2794 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2795 nir_intrinsic_instr
*instr
)
2797 assert(stage
== MESA_SHADER_TESS_EVAL
);
2798 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2801 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2802 dest
= get_nir_dest(instr
->dest
);
2804 switch (instr
->intrinsic
) {
2805 case nir_intrinsic_load_primitive_id
:
2806 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2808 case nir_intrinsic_load_tess_coord
:
2809 /* gl_TessCoord is part of the payload in g1-3 */
2810 for (unsigned i
= 0; i
< 3; i
++) {
2811 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2815 case nir_intrinsic_load_input
:
2816 case nir_intrinsic_load_per_vertex_input
: {
2817 fs_reg indirect_offset
= get_indirect_offset(instr
);
2818 unsigned imm_offset
= instr
->const_index
[0];
2819 unsigned first_component
= nir_intrinsic_component(instr
);
2821 if (type_sz(dest
.type
) == 8) {
2822 first_component
= first_component
/ 2;
2826 if (indirect_offset
.file
== BAD_FILE
) {
2827 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2828 * which is 16 registers (since each holds 2 vec4 slots).
2830 unsigned slot_count
= 1;
2831 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2834 const unsigned max_push_slots
= 32;
2835 if (imm_offset
+ slot_count
<= max_push_slots
) {
2836 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2837 for (int i
= 0; i
< instr
->num_components
; i
++) {
2838 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2839 i
+ first_component
;
2840 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2843 tes_prog_data
->base
.urb_read_length
=
2844 MAX2(tes_prog_data
->base
.urb_read_length
,
2845 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2847 /* Replicate the patch handle to all enabled channels */
2848 const fs_reg srcs
[] = {
2849 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2851 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2852 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2854 if (first_component
!= 0) {
2855 unsigned read_components
=
2856 instr
->num_components
+ first_component
;
2857 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2858 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2860 inst
->size_written
= read_components
* REG_SIZE
;
2861 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2862 bld
.MOV(offset(dest
, bld
, i
),
2863 offset(tmp
, bld
, i
+ first_component
));
2866 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2868 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2871 inst
->offset
= imm_offset
;
2874 /* Indirect indexing - use per-slot offsets as well. */
2876 /* We can only read two double components with each URB read, so
2877 * we send two read messages in that case, each one loading up to
2878 * two double components.
2880 unsigned num_iterations
= 1;
2881 unsigned num_components
= instr
->num_components
;
2882 fs_reg orig_dest
= dest
;
2883 if (type_sz(dest
.type
) == 8) {
2884 if (instr
->num_components
> 2) {
2888 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2892 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2893 const fs_reg srcs
[] = {
2894 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2897 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2898 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2900 if (first_component
!= 0) {
2901 unsigned read_components
=
2902 num_components
+ first_component
;
2903 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2904 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2906 for (unsigned i
= 0; i
< num_components
; i
++) {
2907 bld
.MOV(offset(dest
, bld
, i
),
2908 offset(tmp
, bld
, i
+ first_component
));
2911 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2915 inst
->offset
= imm_offset
;
2916 inst
->size_written
= (num_components
+ first_component
) *
2917 inst
->dst
.component_size(inst
->exec_size
);
2919 /* If we are reading 64-bit data using 32-bit read messages we need
2920 * build proper 64-bit data elements by shuffling the low and high
2921 * 32-bit components around like we do for other things like UBOs
2924 if (type_sz(dest
.type
) == 8) {
2925 shuffle_from_32bit_read(bld
,
2926 offset(orig_dest
, bld
, iter
* 2),
2927 retype(dest
, BRW_REGISTER_TYPE_D
),
2931 /* If we are loading double data and we need a second read message
2934 if (num_iterations
> 1) {
2935 num_components
= instr
->num_components
- 2;
2943 nir_emit_intrinsic(bld
, instr
);
2949 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2950 nir_intrinsic_instr
*instr
)
2952 assert(stage
== MESA_SHADER_GEOMETRY
);
2953 fs_reg indirect_offset
;
2956 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2957 dest
= get_nir_dest(instr
->dest
);
2959 switch (instr
->intrinsic
) {
2960 case nir_intrinsic_load_primitive_id
:
2961 assert(stage
== MESA_SHADER_GEOMETRY
);
2962 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2963 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2964 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2967 case nir_intrinsic_load_input
:
2968 unreachable("load_input intrinsics are invalid for the GS stage");
2970 case nir_intrinsic_load_per_vertex_input
:
2971 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2972 instr
->src
[1], instr
->num_components
,
2973 nir_intrinsic_component(instr
));
2976 case nir_intrinsic_emit_vertex_with_counter
:
2977 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2980 case nir_intrinsic_end_primitive_with_counter
:
2981 emit_gs_end_primitive(instr
->src
[0]);
2984 case nir_intrinsic_set_vertex_count
:
2985 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2988 case nir_intrinsic_load_invocation_id
: {
2989 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2990 assert(val
.file
!= BAD_FILE
);
2991 dest
.type
= val
.type
;
2997 nir_emit_intrinsic(bld
, instr
);
3003 * Fetch the current render target layer index.
3006 fetch_render_target_array_index(const fs_builder
&bld
)
3008 if (bld
.shader
->devinfo
->gen
>= 6) {
3009 /* The render target array index is provided in the thread payload as
3010 * bits 26:16 of r0.0.
3012 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3013 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3017 /* Pre-SNB we only ever render into the first layer of the framebuffer
3018 * since layered rendering is not implemented.
3020 return brw_imm_ud(0);
3025 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3026 * framebuffer at the current fragment coordinates and sample index.
3029 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3032 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3034 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3035 const brw_wm_prog_key
*wm_key
=
3036 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3037 assert(!wm_key
->coherent_fb_fetch
);
3038 const struct brw_wm_prog_data
*wm_prog_data
=
3039 brw_wm_prog_data(stage_prog_data
);
3041 /* Calculate the surface index relative to the start of the texture binding
3042 * table block, since that's what the texturing messages expect.
3044 const unsigned surface
= target
+
3045 wm_prog_data
->binding_table
.render_target_read_start
-
3046 wm_prog_data
->base
.binding_table
.texture_start
;
3048 brw_mark_surface_used(
3049 bld
.shader
->stage_prog_data
,
3050 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3052 /* Calculate the fragment coordinates. */
3053 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3054 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3055 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3056 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3058 /* Calculate the sample index and MCS payload when multisampling. Luckily
3059 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3060 * shouldn't be necessary to recompile based on whether the framebuffer is
3063 if (wm_key
->multisample_fbo
&&
3064 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3065 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3067 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3068 const fs_reg mcs
= wm_key
->multisample_fbo
?
3069 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3071 /* Use either a normal or a CMS texel fetch message depending on whether
3072 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3073 * message just in case the framebuffer uses 16x multisampling, it should
3074 * be equivalent to the normal CMS fetch for lower multisampling modes.
3076 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3077 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3078 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3080 /* Emit the instruction. */
3081 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3083 brw_imm_ud(surface
), brw_imm_ud(0),
3084 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3085 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3087 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3088 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3094 * Actual coherent framebuffer read implemented using the native render target
3095 * read message. Requires SKL+.
3098 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3100 assert(bld
.shader
->devinfo
->gen
>= 9);
3101 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3102 inst
->target
= target
;
3103 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3109 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3111 if (n
&& regs
[0].file
!= BAD_FILE
) {
3115 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3117 for (unsigned i
= 0; i
< n
; i
++)
3125 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3127 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3128 const brw_wm_prog_key
*const key
=
3129 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3130 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3131 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3133 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3134 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3136 else if (l
== FRAG_RESULT_COLOR
)
3137 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3138 MAX2(key
->nr_color_regions
, 1));
3140 else if (l
== FRAG_RESULT_DEPTH
)
3141 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3143 else if (l
== FRAG_RESULT_STENCIL
)
3144 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3146 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3147 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3149 else if (l
>= FRAG_RESULT_DATA0
&&
3150 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3151 return alloc_temporary(v
->bld
, 4,
3152 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3155 unreachable("Invalid location");
3159 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3160 nir_intrinsic_instr
*instr
)
3162 assert(stage
== MESA_SHADER_FRAGMENT
);
3165 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3166 dest
= get_nir_dest(instr
->dest
);
3168 switch (instr
->intrinsic
) {
3169 case nir_intrinsic_load_front_face
:
3170 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3171 *emit_frontfacing_interpolation());
3174 case nir_intrinsic_load_sample_pos
: {
3175 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3176 assert(sample_pos
.file
!= BAD_FILE
);
3177 dest
.type
= sample_pos
.type
;
3178 bld
.MOV(dest
, sample_pos
);
3179 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3183 case nir_intrinsic_load_layer_id
:
3184 dest
.type
= BRW_REGISTER_TYPE_UD
;
3185 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3188 case nir_intrinsic_load_helper_invocation
:
3189 case nir_intrinsic_load_sample_mask_in
:
3190 case nir_intrinsic_load_sample_id
: {
3191 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3192 fs_reg val
= nir_system_values
[sv
];
3193 assert(val
.file
!= BAD_FILE
);
3194 dest
.type
= val
.type
;
3199 case nir_intrinsic_store_output
: {
3200 const fs_reg src
= get_nir_src(instr
->src
[0]);
3201 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3202 assert(const_offset
&& "Indirect output stores not allowed");
3203 const unsigned location
= nir_intrinsic_base(instr
) +
3204 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3205 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3208 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3209 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3210 offset(src
, bld
, j
));
3215 case nir_intrinsic_load_output
: {
3216 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3217 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3218 assert(l
>= FRAG_RESULT_DATA0
);
3219 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3220 assert(const_offset
&& "Indirect output loads not allowed");
3221 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3222 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3224 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3225 emit_coherent_fb_read(bld
, tmp
, target
);
3227 emit_non_coherent_fb_read(bld
, tmp
, target
);
3229 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3230 bld
.MOV(offset(dest
, bld
, j
),
3231 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3237 case nir_intrinsic_discard
:
3238 case nir_intrinsic_discard_if
: {
3239 /* We track our discarded pixels in f0.1. By predicating on it, we can
3240 * update just the flag bits that aren't yet discarded. If there's no
3241 * condition, we emit a CMP of g0 != g0, so all currently executing
3242 * channels will get turned off.
3245 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3246 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3247 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3249 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3250 BRW_REGISTER_TYPE_UW
));
3251 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3253 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3254 cmp
->flag_subreg
= 1;
3256 if (devinfo
->gen
>= 6) {
3257 emit_discard_jump();
3260 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3264 case nir_intrinsic_load_input
: {
3265 /* load_input is only used for flat inputs */
3266 unsigned base
= nir_intrinsic_base(instr
);
3267 unsigned comp
= nir_intrinsic_component(instr
);
3268 unsigned num_components
= instr
->num_components
;
3269 fs_reg orig_dest
= dest
;
3270 enum brw_reg_type type
= dest
.type
;
3272 /* Special case fields in the VUE header */
3273 if (base
== VARYING_SLOT_LAYER
)
3275 else if (base
== VARYING_SLOT_VIEWPORT
)
3278 if (nir_dest_bit_size(instr
->dest
) == 64) {
3279 /* const_index is in 32-bit type size units that could not be aligned
3280 * with DF. We need to read the double vector as if it was a float
3281 * vector of twice the number of components to fetch the right data.
3283 type
= BRW_REGISTER_TYPE_F
;
3284 num_components
*= 2;
3285 dest
= bld
.vgrf(type
, num_components
);
3288 for (unsigned int i
= 0; i
< num_components
; i
++) {
3289 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3290 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3293 if (nir_dest_bit_size(instr
->dest
) == 64) {
3294 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3295 instr
->num_components
);
3300 case nir_intrinsic_load_barycentric_pixel
:
3301 case nir_intrinsic_load_barycentric_centroid
:
3302 case nir_intrinsic_load_barycentric_sample
:
3303 /* Do nothing - load_interpolated_input handling will handle it later. */
3306 case nir_intrinsic_load_barycentric_at_sample
: {
3307 const glsl_interp_mode interpolation
=
3308 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3310 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3313 unsigned msg_data
= const_sample
->i32
[0] << 4;
3315 emit_pixel_interpolater_send(bld
,
3316 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3319 brw_imm_ud(msg_data
),
3322 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3323 BRW_REGISTER_TYPE_UD
);
3325 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3326 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3327 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3328 bld
.exec_all().group(1, 0)
3329 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3330 emit_pixel_interpolater_send(bld
,
3331 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3337 /* Make a loop that sends a message to the pixel interpolater
3338 * for the sample number in each live channel. If there are
3339 * multiple channels with the same sample number then these
3340 * will be handled simultaneously with a single interation of
3343 bld
.emit(BRW_OPCODE_DO
);
3345 /* Get the next live sample number into sample_id_reg */
3346 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3348 /* Set the flag register so that we can perform the send
3349 * message on all channels that have the same sample number
3351 bld
.CMP(bld
.null_reg_ud(),
3352 sample_src
, sample_id
,
3353 BRW_CONDITIONAL_EQ
);
3354 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3355 bld
.exec_all().group(1, 0)
3356 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3358 emit_pixel_interpolater_send(bld
,
3359 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3362 component(msg_data
, 0),
3364 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3366 /* Continue the loop if there are any live channels left */
3367 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3369 bld
.emit(BRW_OPCODE_WHILE
));
3375 case nir_intrinsic_load_barycentric_at_offset
: {
3376 const glsl_interp_mode interpolation
=
3377 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3379 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3382 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3383 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3385 emit_pixel_interpolater_send(bld
,
3386 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3389 brw_imm_ud(off_x
| (off_y
<< 4)),
3392 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3393 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3394 BRW_REGISTER_TYPE_F
);
3395 for (int i
= 0; i
< 2; i
++) {
3396 fs_reg temp
= vgrf(glsl_type::float_type
);
3397 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3398 fs_reg itemp
= vgrf(glsl_type::int_type
);
3400 bld
.MOV(itemp
, temp
);
3402 /* Clamp the upper end of the range to +7/16.
3403 * ARB_gpu_shader5 requires that we support a maximum offset
3404 * of +0.5, which isn't representable in a S0.4 value -- if
3405 * we didn't clamp it, we'd end up with -8/16, which is the
3406 * opposite of what the shader author wanted.
3408 * This is legal due to ARB_gpu_shader5's quantization
3411 * "Not all values of <offset> may be supported; x and y
3412 * offsets may be rounded to fixed-point values with the
3413 * number of fraction bits given by the
3414 * implementation-dependent constant
3415 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3417 set_condmod(BRW_CONDITIONAL_L
,
3418 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3421 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3422 emit_pixel_interpolater_send(bld
,
3432 case nir_intrinsic_load_interpolated_input
: {
3433 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3434 emit_fragcoord_interpolation(dest
);
3438 assert(instr
->src
[0].ssa
&&
3439 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3440 nir_intrinsic_instr
*bary_intrinsic
=
3441 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3442 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3443 enum glsl_interp_mode interp_mode
=
3444 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3447 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3448 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3449 /* Use the result of the PI message */
3450 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3452 /* Use the delta_xy values computed from the payload */
3453 enum brw_barycentric_mode bary
=
3454 brw_barycentric_mode(interp_mode
, bary_intrin
);
3456 dst_xy
= this->delta_xy
[bary
];
3459 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3461 component(interp_reg(nir_intrinsic_base(instr
),
3462 nir_intrinsic_component(instr
) + i
), 0);
3463 interp
.type
= BRW_REGISTER_TYPE_F
;
3464 dest
.type
= BRW_REGISTER_TYPE_F
;
3466 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3467 fs_reg tmp
= vgrf(glsl_type::float_type
);
3468 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3469 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3471 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3478 nir_emit_intrinsic(bld
, instr
);
3484 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3486 const nir_const_value
*const val
= nir_src_as_const_value(instr
->src
[src
]);
3489 if (val
->i32
[0] == 1)
3491 else if (val
->i32
[0] == -1)
3499 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3500 nir_intrinsic_instr
*instr
)
3502 assert(stage
== MESA_SHADER_COMPUTE
);
3503 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3506 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3507 dest
= get_nir_dest(instr
->dest
);
3509 switch (instr
->intrinsic
) {
3510 case nir_intrinsic_barrier
:
3512 cs_prog_data
->uses_barrier
= true;
3515 case nir_intrinsic_load_subgroup_id
:
3516 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3519 case nir_intrinsic_load_local_invocation_id
:
3520 case nir_intrinsic_load_work_group_id
: {
3521 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3522 fs_reg val
= nir_system_values
[sv
];
3523 assert(val
.file
!= BAD_FILE
);
3524 dest
.type
= val
.type
;
3525 for (unsigned i
= 0; i
< 3; i
++)
3526 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3530 case nir_intrinsic_load_num_work_groups
: {
3531 const unsigned surface
=
3532 cs_prog_data
->binding_table
.work_groups_start
;
3534 cs_prog_data
->uses_num_work_groups
= true;
3536 fs_reg surf_index
= brw_imm_ud(surface
);
3537 brw_mark_surface_used(prog_data
, surface
);
3539 /* Read the 3 GLuint components of gl_NumWorkGroups */
3540 for (unsigned i
= 0; i
< 3; i
++) {
3541 fs_reg read_result
=
3542 emit_untyped_read(bld
, surf_index
,
3544 1 /* dims */, 1 /* size */,
3545 BRW_PREDICATE_NONE
);
3546 read_result
.type
= dest
.type
;
3547 bld
.MOV(dest
, read_result
);
3548 dest
= offset(dest
, bld
, 1);
3553 case nir_intrinsic_shared_atomic_add
:
3554 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3556 case nir_intrinsic_shared_atomic_imin
:
3557 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3559 case nir_intrinsic_shared_atomic_umin
:
3560 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3562 case nir_intrinsic_shared_atomic_imax
:
3563 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3565 case nir_intrinsic_shared_atomic_umax
:
3566 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3568 case nir_intrinsic_shared_atomic_and
:
3569 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3571 case nir_intrinsic_shared_atomic_or
:
3572 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3574 case nir_intrinsic_shared_atomic_xor
:
3575 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3577 case nir_intrinsic_shared_atomic_exchange
:
3578 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3580 case nir_intrinsic_shared_atomic_comp_swap
:
3581 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3583 case nir_intrinsic_shared_atomic_fmin
:
3584 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3586 case nir_intrinsic_shared_atomic_fmax
:
3587 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3589 case nir_intrinsic_shared_atomic_fcomp_swap
:
3590 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3593 case nir_intrinsic_load_shared
: {
3594 assert(devinfo
->gen
>= 7);
3596 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3598 /* Get the offset to read from */
3600 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3602 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3604 offset_reg
= vgrf(glsl_type::uint_type
);
3606 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3607 brw_imm_ud(instr
->const_index
[0]));
3610 /* Read the vector */
3611 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3612 instr
->num_components
);
3616 case nir_intrinsic_store_shared
: {
3617 assert(devinfo
->gen
>= 7);
3620 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3623 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3626 unsigned writemask
= instr
->const_index
[1];
3628 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3629 * since the untyped writes below operate in units of 32-bits, which
3630 * means that we need to write twice as many components each time.
3631 * Also, we have to suffle 64-bit data to be in the appropriate layout
3632 * expected by our 32-bit write messages.
3634 unsigned type_size
= 4;
3635 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3637 val_reg
= shuffle_for_32bit_write(bld
, val_reg
, 0,
3638 instr
->num_components
);
3641 unsigned type_slots
= type_size
/ 4;
3643 /* Combine groups of consecutive enabled channels in one write
3644 * message. We use ffs to find the first enabled channel and then ffs on
3645 * the bit-inverse, down-shifted writemask to determine the length of
3646 * the block of enabled bits.
3649 unsigned first_component
= ffs(writemask
) - 1;
3650 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3652 /* We can't write more than 2 64-bit components at once. Limit the
3653 * length of the write to what we can do and let the next iteration
3657 length
= MIN2(2, length
);
3660 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3662 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3663 type_size
* first_component
);
3665 offset_reg
= vgrf(glsl_type::uint_type
);
3667 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3668 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3671 emit_untyped_write(bld
, surf_index
, offset_reg
,
3672 offset(val_reg
, bld
, first_component
* type_slots
),
3673 1 /* dims */, length
* type_slots
,
3674 BRW_PREDICATE_NONE
);
3676 /* Clear the bits in the writemask that we just wrote, then try
3677 * again to see if more channels are left.
3679 writemask
&= (15 << (first_component
+ length
));
3686 nir_emit_intrinsic(bld
, instr
);
3692 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3693 nir_op op
, brw_reg_type type
)
3695 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3696 switch (type_sz(type
)) {
3698 assert(type
!= BRW_REGISTER_TYPE_HF
);
3699 return retype(brw_imm_uw(value
.u16
[0]), type
);
3701 return retype(brw_imm_ud(value
.u32
[0]), type
);
3703 if (type
== BRW_REGISTER_TYPE_DF
)
3704 return setup_imm_df(bld
, value
.f64
[0]);
3706 return retype(brw_imm_u64(value
.u64
[0]), type
);
3708 unreachable("Invalid type size");
3713 brw_op_for_nir_reduction_op(nir_op op
)
3716 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3717 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3718 case nir_op_imul
: return BRW_OPCODE_MUL
;
3719 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3720 case nir_op_imin
: return BRW_OPCODE_SEL
;
3721 case nir_op_umin
: return BRW_OPCODE_SEL
;
3722 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3723 case nir_op_imax
: return BRW_OPCODE_SEL
;
3724 case nir_op_umax
: return BRW_OPCODE_SEL
;
3725 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3726 case nir_op_iand
: return BRW_OPCODE_AND
;
3727 case nir_op_ior
: return BRW_OPCODE_OR
;
3728 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3730 unreachable("Invalid reduction operation");
3734 static brw_conditional_mod
3735 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3738 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3739 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3740 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3741 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3742 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3743 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3744 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3745 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3746 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3747 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3748 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3749 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3750 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3752 unreachable("Invalid reduction operation");
3757 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3758 nir_intrinsic_instr
*instr
)
3760 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3762 if (stage_prog_data
->binding_table
.image_start
> 0) {
3763 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3764 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3766 bld
.ADD(image
, image
,
3767 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3771 return bld
.emit_uniformize(image
);
3775 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3777 switch (nir_intrinsic_image_dim(instr
)) {
3778 case GLSL_SAMPLER_DIM_1D
:
3779 return 1 + nir_intrinsic_image_array(instr
);
3780 case GLSL_SAMPLER_DIM_2D
:
3781 case GLSL_SAMPLER_DIM_RECT
:
3782 return 2 + nir_intrinsic_image_array(instr
);
3783 case GLSL_SAMPLER_DIM_3D
:
3784 case GLSL_SAMPLER_DIM_CUBE
:
3786 case GLSL_SAMPLER_DIM_BUF
:
3788 case GLSL_SAMPLER_DIM_MS
:
3789 return 2 + nir_intrinsic_image_array(instr
);
3791 unreachable("Invalid image dimension");
3796 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3799 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3800 dest
= get_nir_dest(instr
->dest
);
3802 switch (instr
->intrinsic
) {
3803 case nir_intrinsic_image_load
:
3804 case nir_intrinsic_image_store
:
3805 case nir_intrinsic_image_atomic_add
:
3806 case nir_intrinsic_image_atomic_min
:
3807 case nir_intrinsic_image_atomic_max
:
3808 case nir_intrinsic_image_atomic_and
:
3809 case nir_intrinsic_image_atomic_or
:
3810 case nir_intrinsic_image_atomic_xor
:
3811 case nir_intrinsic_image_atomic_exchange
:
3812 case nir_intrinsic_image_atomic_comp_swap
: {
3813 if (stage
== MESA_SHADER_FRAGMENT
&&
3814 instr
->intrinsic
!= nir_intrinsic_image_load
)
3815 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3817 /* Get some metadata from the image intrinsic. */
3818 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3819 const unsigned dims
= image_intrinsic_coord_components(instr
);
3820 const GLenum format
= nir_intrinsic_format(instr
);
3821 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3823 /* Get the arguments of the image intrinsic. */
3824 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3825 const fs_reg coords
= retype(get_nir_src(instr
->src
[1]),
3826 BRW_REGISTER_TYPE_UD
);
3829 /* Emit an image load, store or atomic op. */
3830 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3831 tmp
= emit_typed_read(bld
, image
, coords
, dims
,
3832 instr
->num_components
);
3833 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3834 const fs_reg src0
= get_nir_src(instr
->src
[3]);
3835 emit_typed_write(bld
, image
, coords
, src0
, dims
,
3836 instr
->num_components
);
3839 unsigned num_srcs
= info
->num_srcs
;
3841 switch (instr
->intrinsic
) {
3842 case nir_intrinsic_image_atomic_add
:
3843 assert(num_srcs
== 4);
3845 op
= get_op_for_atomic_add(instr
, 3);
3847 if (op
!= BRW_AOP_ADD
)
3850 case nir_intrinsic_image_atomic_min
:
3851 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3852 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3854 case nir_intrinsic_image_atomic_max
:
3855 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3856 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3858 case nir_intrinsic_image_atomic_and
:
3861 case nir_intrinsic_image_atomic_or
:
3864 case nir_intrinsic_image_atomic_xor
:
3867 case nir_intrinsic_image_atomic_exchange
:
3870 case nir_intrinsic_image_atomic_comp_swap
:
3874 unreachable("Not reachable.");
3877 const fs_reg src0
= (num_srcs
>= 4 ?
3878 get_nir_src(instr
->src
[3]) : fs_reg());
3879 const fs_reg src1
= (num_srcs
>= 5 ?
3880 get_nir_src(instr
->src
[4]) : fs_reg());
3882 tmp
= emit_typed_atomic(bld
, image
, coords
, src0
, src1
, dims
, 1, op
);
3885 /* Assign the result. */
3886 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3887 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3888 offset(tmp
, bld
, c
));
3893 case nir_intrinsic_image_size
: {
3894 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3895 * into will handle the binding table index for us in the geneerator.
3897 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3898 BRW_REGISTER_TYPE_UD
);
3899 image
= bld
.emit_uniformize(image
);
3901 /* Since the image size is always uniform, we can just emit a SIMD8
3902 * query instruction and splat the result out.
3904 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3906 /* The LOD also serves as the message payload */
3907 fs_reg lod
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3908 ubld
.MOV(lod
, brw_imm_ud(0));
3910 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3911 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE
, tmp
, lod
, image
);
3913 inst
->size_written
= 4 * REG_SIZE
;
3915 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3916 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3917 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3918 offset(retype(dest
, tmp
.type
), bld
, c
),
3919 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3921 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3922 component(offset(tmp
, ubld
, c
), 0));
3928 case nir_intrinsic_image_load_raw_intel
: {
3929 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3930 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3931 BRW_REGISTER_TYPE_UD
);
3933 fs_reg tmp
= emit_untyped_read(bld
, image
, addr
, 1,
3934 instr
->num_components
);
3936 for (unsigned c
= 0; c
< instr
->num_components
; ++c
) {
3937 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3938 offset(tmp
, bld
, c
));
3943 case nir_intrinsic_image_store_raw_intel
: {
3944 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3945 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3946 BRW_REGISTER_TYPE_UD
);
3947 const fs_reg data
= retype(get_nir_src(instr
->src
[2]),
3948 BRW_REGISTER_TYPE_UD
);
3950 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3952 emit_untyped_write(bld
, image
, addr
, data
, 1,
3953 instr
->num_components
);
3957 case nir_intrinsic_group_memory_barrier
:
3958 case nir_intrinsic_memory_barrier_shared
:
3959 case nir_intrinsic_memory_barrier_atomic_counter
:
3960 case nir_intrinsic_memory_barrier_buffer
:
3961 case nir_intrinsic_memory_barrier_image
:
3962 case nir_intrinsic_memory_barrier
: {
3963 const fs_builder ubld
= bld
.group(8, 0);
3964 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3965 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3966 ->size_written
= 2 * REG_SIZE
;
3970 case nir_intrinsic_shader_clock
: {
3971 /* We cannot do anything if there is an event, so ignore it for now */
3972 const fs_reg shader_clock
= get_timestamp(bld
);
3973 const fs_reg srcs
[] = { component(shader_clock
, 0),
3974 component(shader_clock
, 1) };
3975 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3979 case nir_intrinsic_image_samples
:
3980 /* The driver does not support multi-sampled images. */
3981 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3984 case nir_intrinsic_load_uniform
: {
3985 /* Offsets are in bytes but they should always aligned to
3988 assert(instr
->const_index
[0] % 4 == 0 ||
3989 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3991 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3993 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3995 assert(const_offset
->u32
[0] % type_sz(dest
.type
) == 0);
3996 /* For 16-bit types we add the module of the const_index[0]
3997 * offset to access to not 32-bit aligned element
3999 src
.offset
= const_offset
->u32
[0] + instr
->const_index
[0] % 4;
4001 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4002 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4005 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4006 BRW_REGISTER_TYPE_UD
);
4008 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4009 * go past the end of the uniform. In order to keep the n'th
4010 * component from running past, we subtract off the size of all but
4011 * one component of the vector.
4013 assert(instr
->const_index
[1] >=
4014 instr
->num_components
* (int) type_sz(dest
.type
));
4015 unsigned read_size
= instr
->const_index
[1] -
4016 (instr
->num_components
- 1) * type_sz(dest
.type
);
4018 bool supports_64bit_indirects
=
4019 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4021 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4022 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4023 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4024 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4025 indirect
, brw_imm_ud(read_size
));
4028 const unsigned num_mov_indirects
=
4029 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4030 /* We read a little bit less per MOV INDIRECT, as they are now
4031 * 32-bits ones instead of 64-bit. Fix read_size then.
4033 const unsigned read_size_32bit
= read_size
-
4034 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4035 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4036 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4037 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4038 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4039 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4040 indirect
, brw_imm_ud(read_size_32bit
));
4048 case nir_intrinsic_load_ubo
: {
4049 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4053 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4054 const_index
->u32
[0];
4055 surf_index
= brw_imm_ud(index
);
4056 brw_mark_surface_used(prog_data
, index
);
4058 /* The block index is not a constant. Evaluate the index expression
4059 * per-channel and add the base UBO index; we have to select a value
4060 * from any live channel.
4062 surf_index
= vgrf(glsl_type::uint_type
);
4063 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4064 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4065 surf_index
= bld
.emit_uniformize(surf_index
);
4067 /* Assume this may touch any UBO. It would be nice to provide
4068 * a tighter bound, but the array information is already lowered away.
4070 brw_mark_surface_used(prog_data
,
4071 stage_prog_data
->binding_table
.ubo_start
+
4072 nir
->info
.num_ubos
- 1);
4075 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4076 if (const_offset
== NULL
) {
4077 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4078 BRW_REGISTER_TYPE_UD
);
4080 for (int i
= 0; i
< instr
->num_components
; i
++)
4081 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4082 base_offset
, i
* type_sz(dest
.type
));
4084 /* Even if we are loading doubles, a pull constant load will load
4085 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4086 * need to load a full dvec4 we will have to emit 2 loads. This is
4087 * similar to demote_pull_constants(), except that in that case we
4088 * see individual accesses to each component of the vector and then
4089 * we let CSE deal with duplicate loads. Here we see a vector access
4090 * and we have to split it if necessary.
4092 const unsigned type_size
= type_sz(dest
.type
);
4094 /* See if we've selected this as a push constant candidate */
4096 const unsigned ubo_block
= const_index
->u32
[0];
4097 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
4100 for (int i
= 0; i
< 4; i
++) {
4101 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4102 if (range
->block
== ubo_block
&&
4103 offset_256b
>= range
->start
&&
4104 offset_256b
< range
->start
+ range
->length
) {
4106 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4107 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
4112 if (push_reg
.file
!= BAD_FILE
) {
4113 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4114 bld
.MOV(offset(dest
, bld
, i
),
4115 byte_offset(push_reg
, i
* type_size
));
4121 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4122 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4123 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4125 for (unsigned c
= 0; c
< instr
->num_components
;) {
4126 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4127 /* Number of usable components in the next block-aligned load. */
4128 const unsigned count
= MIN2(instr
->num_components
- c
,
4129 (block_sz
- base
% block_sz
) / type_size
);
4131 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4132 packed_consts
, surf_index
,
4133 brw_imm_ud(base
& ~(block_sz
- 1)));
4135 const fs_reg consts
=
4136 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4139 for (unsigned d
= 0; d
< count
; d
++)
4140 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4148 case nir_intrinsic_load_ssbo
: {
4149 assert(devinfo
->gen
>= 7);
4151 nir_const_value
*const_uniform_block
=
4152 nir_src_as_const_value(instr
->src
[0]);
4155 if (const_uniform_block
) {
4156 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4157 const_uniform_block
->u32
[0];
4158 surf_index
= brw_imm_ud(index
);
4159 brw_mark_surface_used(prog_data
, index
);
4161 surf_index
= vgrf(glsl_type::uint_type
);
4162 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4163 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4165 /* Assume this may touch any UBO. It would be nice to provide
4166 * a tighter bound, but the array information is already lowered away.
4168 brw_mark_surface_used(prog_data
,
4169 stage_prog_data
->binding_table
.ssbo_start
+
4170 nir
->info
.num_ssbos
- 1);
4174 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4176 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4178 offset_reg
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
);
4181 /* Read the vector */
4182 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4183 instr
->num_components
);
4188 case nir_intrinsic_store_ssbo
: {
4189 assert(devinfo
->gen
>= 7);
4191 if (stage
== MESA_SHADER_FRAGMENT
)
4192 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4196 nir_const_value
*const_uniform_block
=
4197 nir_src_as_const_value(instr
->src
[1]);
4198 if (const_uniform_block
) {
4199 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4200 const_uniform_block
->u32
[0];
4201 surf_index
= brw_imm_ud(index
);
4202 brw_mark_surface_used(prog_data
, index
);
4204 surf_index
= vgrf(glsl_type::uint_type
);
4205 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4206 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4208 brw_mark_surface_used(prog_data
,
4209 stage_prog_data
->binding_table
.ssbo_start
+
4210 nir
->info
.num_ssbos
- 1);
4214 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4217 unsigned writemask
= instr
->const_index
[0];
4219 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4220 * since the untyped writes below operate in units of 32-bits, which
4221 * means that we need to write twice as many components each time.
4222 * Also, we have to suffle 64-bit data to be in the appropriate layout
4223 * expected by our 32-bit write messages.
4225 unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4226 unsigned type_size
= bit_size
/ 8;
4228 /* Combine groups of consecutive enabled channels in one write
4229 * message. We use ffs to find the first enabled channel and then ffs on
4230 * the bit-inverse, down-shifted writemask to determine the num_components
4231 * of the block of enabled bits.
4234 unsigned first_component
= ffs(writemask
) - 1;
4235 unsigned num_components
= ffs(~(writemask
>> first_component
)) - 1;
4236 fs_reg write_src
= offset(val_reg
, bld
, first_component
);
4238 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4240 if (type_size
> 4) {
4241 /* We can't write more than 2 64-bit components at once. Limit
4242 * the num_components of the write to what we can do and let the next
4243 * iteration handle the rest.
4245 num_components
= MIN2(2, num_components
);
4246 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4248 } else if (type_size
< 4) {
4249 /* For 16-bit types we pack two consecutive values into a 32-bit
4250 * word and use an untyped write message. For single values or not
4251 * 32-bit-aligned we need to use byte-scattered writes because
4252 * untyped writes works with 32-bit components with 32-bit
4253 * alignment. byte_scattered_write messages only support one
4254 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4255 * could be enabled we can not guarantee that not constant offsets
4256 * to be 32-bit aligned for 16-bit types. For example an array, of
4257 * 16-bit vec3 with array element stride of 6.
4259 * In the case of 32-bit aligned constant offsets if there is
4260 * a 3-components vector we submit one untyped-write message
4261 * of 32-bit (first two components), and one byte-scattered
4262 * write message (the last component).
4265 if ( !const_offset
|| ((const_offset
->u32
[0] +
4266 type_size
* first_component
) % 4)) {
4267 /* If we use a .yz writemask we also need to emit 2
4268 * byte-scattered write messages because of y-component not
4269 * being aligned to 32-bit.
4272 } else if (num_components
* type_size
> 4 &&
4273 (num_components
* type_size
% 4)) {
4274 /* If the pending components size is not a multiple of 4 bytes
4275 * we left the not aligned components for following emits of
4276 * length == 1 with byte_scattered_write.
4278 num_components
-= (num_components
* type_size
% 4) / type_size
;
4279 } else if (num_components
* type_size
< 4) {
4282 /* For num_components == 1 we are also shuffling the component
4283 * because byte scattered writes of 16-bit need values to be dword
4284 * aligned. Shuffling only one component would be the same as
4287 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4294 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4295 type_size
* first_component
);
4297 offset_reg
= vgrf(glsl_type::uint_type
);
4299 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4300 brw_imm_ud(type_size
* first_component
));
4303 if (type_size
< 4 && num_components
== 1) {
4304 /* Untyped Surface messages have a fixed 32-bit size, so we need
4305 * to rely on byte scattered in order to write 16-bit elements.
4306 * The byte_scattered_write message needs that every written 16-bit
4307 * type to be aligned 32-bits (stride=2).
4309 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4313 BRW_PREDICATE_NONE
);
4315 assert(num_components
* type_size
<= 16);
4316 assert((num_components
* type_size
) % 4 == 0);
4317 assert(offset_reg
.file
!= BRW_IMMEDIATE_VALUE
||
4318 offset_reg
.ud
% 4 == 0);
4319 unsigned num_slots
= (num_components
* type_size
) / 4;
4321 emit_untyped_write(bld
, surf_index
, offset_reg
,
4323 1 /* dims */, num_slots
,
4324 BRW_PREDICATE_NONE
);
4327 /* Clear the bits in the writemask that we just wrote, then try
4328 * again to see if more channels are left.
4330 writemask
&= (15 << (first_component
+ num_components
));
4335 case nir_intrinsic_store_output
: {
4336 fs_reg src
= get_nir_src(instr
->src
[0]);
4338 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4339 assert(const_offset
&& "Indirect output stores not allowed");
4341 unsigned num_components
= instr
->num_components
;
4342 unsigned first_component
= nir_intrinsic_component(instr
);
4343 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4344 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4345 num_components
*= 2;
4348 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4349 4 * const_offset
->u32
[0]), src
.type
);
4350 for (unsigned j
= 0; j
< num_components
; j
++) {
4351 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4352 offset(src
, bld
, j
));
4357 case nir_intrinsic_ssbo_atomic_add
:
4358 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4360 case nir_intrinsic_ssbo_atomic_imin
:
4361 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4363 case nir_intrinsic_ssbo_atomic_umin
:
4364 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4366 case nir_intrinsic_ssbo_atomic_imax
:
4367 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4369 case nir_intrinsic_ssbo_atomic_umax
:
4370 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4372 case nir_intrinsic_ssbo_atomic_and
:
4373 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4375 case nir_intrinsic_ssbo_atomic_or
:
4376 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4378 case nir_intrinsic_ssbo_atomic_xor
:
4379 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4381 case nir_intrinsic_ssbo_atomic_exchange
:
4382 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4384 case nir_intrinsic_ssbo_atomic_comp_swap
:
4385 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4387 case nir_intrinsic_ssbo_atomic_fmin
:
4388 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4390 case nir_intrinsic_ssbo_atomic_fmax
:
4391 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4393 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4394 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4397 case nir_intrinsic_get_buffer_size
: {
4398 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4399 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4401 /* A resinfo's sampler message is used to get the buffer size. The
4402 * SIMD8's writeback message consists of four registers and SIMD16's
4403 * writeback message consists of 8 destination registers (two per each
4404 * component). Because we are only interested on the first channel of
4405 * the first returned component, where resinfo returns the buffer size
4406 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4407 * the dispatch width.
4409 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4410 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4411 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4414 ubld
.MOV(src_payload
, brw_imm_d(0));
4416 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4417 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4418 src_payload
, brw_imm_ud(index
));
4419 inst
->header_size
= 0;
4421 inst
->size_written
= 4 * REG_SIZE
;
4423 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4425 * "Out-of-bounds checking is always performed at a DWord granularity. If
4426 * any part of the DWord is out-of-bounds then the whole DWord is
4427 * considered out-of-bounds."
4429 * This implies that types with size smaller than 4-bytes need to be
4430 * padded if they don't complete the last dword of the buffer. But as we
4431 * need to maintain the original size we need to reverse the padding
4432 * calculation to return the correct size to know the number of elements
4433 * of an unsized array. As we stored in the last two bits of the surface
4434 * size the needed padding for the buffer, we calculate here the
4435 * original buffer_size reversing the surface_size calculation:
4437 * surface_size = isl_align(buffer_size, 4) +
4438 * (isl_align(buffer_size) - buffer_size)
4440 * buffer_size = surface_size & ~3 - surface_size & 3
4443 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4444 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4445 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4447 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4448 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4449 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4451 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4453 brw_mark_surface_used(prog_data
, index
);
4457 case nir_intrinsic_load_subgroup_invocation
:
4458 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4459 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4462 case nir_intrinsic_load_subgroup_eq_mask
:
4463 case nir_intrinsic_load_subgroup_ge_mask
:
4464 case nir_intrinsic_load_subgroup_gt_mask
:
4465 case nir_intrinsic_load_subgroup_le_mask
:
4466 case nir_intrinsic_load_subgroup_lt_mask
:
4467 unreachable("not reached");
4469 case nir_intrinsic_vote_any
: {
4470 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4472 /* The any/all predicates do not consider channel enables. To prevent
4473 * dead channels from affecting the result, we initialize the flag with
4474 * with the identity value for the logical operation.
4476 if (dispatch_width
== 32) {
4477 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4478 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4481 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4483 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4485 /* For some reason, the any/all predicates don't work properly with
4486 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4487 * doesn't read the correct subset of the flag register and you end up
4488 * getting garbage in the second half. Work around this by using a pair
4489 * of 1-wide MOVs and scattering the result.
4491 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4492 ubld
.MOV(res1
, brw_imm_d(0));
4493 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4494 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4495 BRW_PREDICATE_ALIGN1_ANY32H
,
4496 ubld
.MOV(res1
, brw_imm_d(-1)));
4498 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4501 case nir_intrinsic_vote_all
: {
4502 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4504 /* The any/all predicates do not consider channel enables. To prevent
4505 * dead channels from affecting the result, we initialize the flag with
4506 * with the identity value for the logical operation.
4508 if (dispatch_width
== 32) {
4509 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4510 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4511 brw_imm_ud(0xffffffff));
4513 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4515 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4517 /* For some reason, the any/all predicates don't work properly with
4518 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4519 * doesn't read the correct subset of the flag register and you end up
4520 * getting garbage in the second half. Work around this by using a pair
4521 * of 1-wide MOVs and scattering the result.
4523 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4524 ubld
.MOV(res1
, brw_imm_d(0));
4525 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4526 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4527 BRW_PREDICATE_ALIGN1_ALL32H
,
4528 ubld
.MOV(res1
, brw_imm_d(-1)));
4530 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4533 case nir_intrinsic_vote_feq
:
4534 case nir_intrinsic_vote_ieq
: {
4535 fs_reg value
= get_nir_src(instr
->src
[0]);
4536 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4537 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4538 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4541 fs_reg uniformized
= bld
.emit_uniformize(value
);
4542 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4544 /* The any/all predicates do not consider channel enables. To prevent
4545 * dead channels from affecting the result, we initialize the flag with
4546 * with the identity value for the logical operation.
4548 if (dispatch_width
== 32) {
4549 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4550 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4551 brw_imm_ud(0xffffffff));
4553 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4555 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4557 /* For some reason, the any/all predicates don't work properly with
4558 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4559 * doesn't read the correct subset of the flag register and you end up
4560 * getting garbage in the second half. Work around this by using a pair
4561 * of 1-wide MOVs and scattering the result.
4563 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4564 ubld
.MOV(res1
, brw_imm_d(0));
4565 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4566 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4567 BRW_PREDICATE_ALIGN1_ALL32H
,
4568 ubld
.MOV(res1
, brw_imm_d(-1)));
4570 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4574 case nir_intrinsic_ballot
: {
4575 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4576 BRW_REGISTER_TYPE_UD
);
4577 struct brw_reg flag
= brw_flag_reg(0, 0);
4578 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4579 * as f0.0. This is a problem for fragment programs as we currently use
4580 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4581 * programs yet so this isn't a problem. When we do, something will
4584 if (dispatch_width
== 32)
4585 flag
.type
= BRW_REGISTER_TYPE_UD
;
4587 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4588 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4590 if (instr
->dest
.ssa
.bit_size
> 32) {
4591 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4593 dest
.type
= BRW_REGISTER_TYPE_UD
;
4595 bld
.MOV(dest
, flag
);
4599 case nir_intrinsic_read_invocation
: {
4600 const fs_reg value
= get_nir_src(instr
->src
[0]);
4601 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4602 fs_reg tmp
= bld
.vgrf(value
.type
);
4604 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4605 bld
.emit_uniformize(invocation
));
4607 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4611 case nir_intrinsic_read_first_invocation
: {
4612 const fs_reg value
= get_nir_src(instr
->src
[0]);
4613 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4617 case nir_intrinsic_shuffle
: {
4618 const fs_reg value
= get_nir_src(instr
->src
[0]);
4619 const fs_reg index
= get_nir_src(instr
->src
[1]);
4621 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4625 case nir_intrinsic_first_invocation
: {
4626 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4627 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4628 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4629 fs_reg(component(tmp
, 0)));
4633 case nir_intrinsic_quad_broadcast
: {
4634 const fs_reg value
= get_nir_src(instr
->src
[0]);
4635 nir_const_value
*index
= nir_src_as_const_value(instr
->src
[1]);
4636 assert(nir_src_bit_size(instr
->src
[1]) == 32);
4638 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4639 value
, brw_imm_ud(index
->u32
[0]), brw_imm_ud(4));
4643 case nir_intrinsic_quad_swap_horizontal
: {
4644 const fs_reg value
= get_nir_src(instr
->src
[0]);
4645 const fs_reg tmp
= bld
.vgrf(value
.type
);
4646 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4648 const fs_reg src_left
= horiz_stride(value
, 2);
4649 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4650 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4651 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4653 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4655 * "When source or destination datatype is 64b or operation is
4656 * integer DWord multiply, regioning in Align1 must follow
4661 * 3. Source and Destination offset must be the same, except
4662 * the case of scalar source."
4664 * In order to work around this, we have to emit two 32-bit MOVs instead
4665 * of a single 64-bit MOV to do the shuffle.
4667 if (type_sz(value
.type
) > 4 &&
4668 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4669 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4670 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4671 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4672 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4673 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4674 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4675 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4676 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4678 ubld
.MOV(tmp_left
, src_right
);
4679 ubld
.MOV(tmp_right
, src_left
);
4681 bld
.MOV(retype(dest
, value
.type
), tmp
);
4685 case nir_intrinsic_quad_swap_vertical
: {
4686 const fs_reg value
= get_nir_src(instr
->src
[0]);
4687 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4688 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4689 const fs_reg tmp
= bld
.vgrf(value
.type
);
4690 const fs_builder ubld
= bld
.exec_all();
4691 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4692 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4693 bld
.MOV(retype(dest
, value
.type
), tmp
);
4695 /* For larger data types, we have to either emit dispatch_width many
4696 * MOVs or else fall back to doing indirects.
4698 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4699 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4701 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4706 case nir_intrinsic_quad_swap_diagonal
: {
4707 const fs_reg value
= get_nir_src(instr
->src
[0]);
4708 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4709 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4710 const fs_reg tmp
= bld
.vgrf(value
.type
);
4711 const fs_builder ubld
= bld
.exec_all();
4712 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4713 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4714 bld
.MOV(retype(dest
, value
.type
), tmp
);
4716 /* For larger data types, we have to either emit dispatch_width many
4717 * MOVs or else fall back to doing indirects.
4719 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4720 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4722 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4727 case nir_intrinsic_reduce
: {
4728 fs_reg src
= get_nir_src(instr
->src
[0]);
4729 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4730 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4731 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4732 cluster_size
= dispatch_width
;
4734 /* Figure out the source type */
4735 src
.type
= brw_type_for_nir_type(devinfo
,
4736 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4737 nir_src_bit_size(instr
->src
[0])));
4739 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4740 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4741 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4743 /* Set up a register for all of our scratching around and initialize it
4744 * to reduction operation's identity value.
4746 fs_reg scan
= bld
.vgrf(src
.type
);
4747 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4749 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4751 dest
.type
= src
.type
;
4752 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4753 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4754 * the distance between clusters is at least 2 GRFs. In this case,
4755 * we don't need the weird striding of the CLUSTER_BROADCAST
4756 * instruction and can just do regular MOVs.
4758 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4759 const unsigned groups
=
4760 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4761 const unsigned group_size
= dispatch_width
/ groups
;
4762 for (unsigned i
= 0; i
< groups
; i
++) {
4763 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4764 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4765 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4766 component(scan
, comp
));
4769 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4770 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4775 case nir_intrinsic_inclusive_scan
:
4776 case nir_intrinsic_exclusive_scan
: {
4777 fs_reg src
= get_nir_src(instr
->src
[0]);
4778 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4780 /* Figure out the source type */
4781 src
.type
= brw_type_for_nir_type(devinfo
,
4782 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4783 nir_src_bit_size(instr
->src
[0])));
4785 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4786 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4787 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4789 /* Set up a register for all of our scratching around and initialize it
4790 * to reduction operation's identity value.
4792 fs_reg scan
= bld
.vgrf(src
.type
);
4793 const fs_builder allbld
= bld
.exec_all();
4794 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4796 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4797 /* Exclusive scan is a bit harder because we have to do an annoying
4798 * shift of the contents before we can begin. To make things worse,
4799 * we can't do this with a normal stride; we have to use indirects.
4801 fs_reg shifted
= bld
.vgrf(src
.type
);
4802 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4803 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4805 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4806 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4810 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4812 bld
.MOV(retype(dest
, src
.type
), scan
);
4816 case nir_intrinsic_begin_fragment_shader_ordering
:
4817 case nir_intrinsic_begin_invocation_interlock
: {
4818 const fs_builder ubld
= bld
.group(8, 0);
4819 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4821 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4827 case nir_intrinsic_end_invocation_interlock
: {
4828 /* We don't need to do anything here */
4833 unreachable("unknown intrinsic");
4838 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4839 int op
, nir_intrinsic_instr
*instr
)
4841 if (stage
== MESA_SHADER_FRAGMENT
)
4842 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4845 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4846 dest
= get_nir_dest(instr
->dest
);
4849 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4850 if (const_surface
) {
4851 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4852 const_surface
->u32
[0];
4853 surface
= brw_imm_ud(surf_index
);
4854 brw_mark_surface_used(prog_data
, surf_index
);
4856 surface
= vgrf(glsl_type::uint_type
);
4857 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4858 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4860 /* Assume this may touch any SSBO. This is the same we do for other
4861 * UBO/SSBO accesses with non-constant surface.
4863 brw_mark_surface_used(prog_data
,
4864 stage_prog_data
->binding_table
.ssbo_start
+
4865 nir
->info
.num_ssbos
- 1);
4868 fs_reg offset
= get_nir_src(instr
->src
[1]);
4870 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4871 data1
= get_nir_src(instr
->src
[2]);
4873 if (op
== BRW_AOP_CMPWR
)
4874 data2
= get_nir_src(instr
->src
[3]);
4876 /* Emit the actual atomic operation */
4878 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4880 1 /* dims */, 1 /* rsize */,
4882 BRW_PREDICATE_NONE
);
4883 dest
.type
= atomic_result
.type
;
4884 bld
.MOV(dest
, atomic_result
);
4888 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4889 int op
, nir_intrinsic_instr
*instr
)
4891 if (stage
== MESA_SHADER_FRAGMENT
)
4892 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4895 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4896 dest
= get_nir_dest(instr
->dest
);
4899 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4900 if (const_surface
) {
4901 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4902 const_surface
->u32
[0];
4903 surface
= brw_imm_ud(surf_index
);
4904 brw_mark_surface_used(prog_data
, surf_index
);
4906 surface
= vgrf(glsl_type::uint_type
);
4907 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4908 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4910 /* Assume this may touch any SSBO. This is the same we do for other
4911 * UBO/SSBO accesses with non-constant surface.
4913 brw_mark_surface_used(prog_data
,
4914 stage_prog_data
->binding_table
.ssbo_start
+
4915 nir
->info
.num_ssbos
- 1);
4918 fs_reg offset
= get_nir_src(instr
->src
[1]);
4919 fs_reg data1
= get_nir_src(instr
->src
[2]);
4921 if (op
== BRW_AOP_FCMPWR
)
4922 data2
= get_nir_src(instr
->src
[3]);
4924 /* Emit the actual atomic operation */
4926 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4928 1 /* dims */, 1 /* rsize */,
4930 BRW_PREDICATE_NONE
);
4931 dest
.type
= atomic_result
.type
;
4932 bld
.MOV(dest
, atomic_result
);
4936 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4937 int op
, nir_intrinsic_instr
*instr
)
4940 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4941 dest
= get_nir_dest(instr
->dest
);
4943 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4946 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4947 data1
= get_nir_src(instr
->src
[1]);
4949 if (op
== BRW_AOP_CMPWR
)
4950 data2
= get_nir_src(instr
->src
[2]);
4952 /* Get the offset */
4953 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4955 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4957 offset
= vgrf(glsl_type::uint_type
);
4959 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4960 brw_imm_ud(instr
->const_index
[0]));
4963 /* Emit the actual atomic operation operation */
4965 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4967 1 /* dims */, 1 /* rsize */,
4969 BRW_PREDICATE_NONE
);
4970 dest
.type
= atomic_result
.type
;
4971 bld
.MOV(dest
, atomic_result
);
4975 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4976 int op
, nir_intrinsic_instr
*instr
)
4979 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4980 dest
= get_nir_dest(instr
->dest
);
4982 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4984 fs_reg data1
= get_nir_src(instr
->src
[1]);
4986 if (op
== BRW_AOP_FCMPWR
)
4987 data2
= get_nir_src(instr
->src
[2]);
4989 /* Get the offset */
4990 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4992 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4994 offset
= vgrf(glsl_type::uint_type
);
4996 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4997 brw_imm_ud(instr
->const_index
[0]));
5000 /* Emit the actual atomic operation operation */
5002 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
5004 1 /* dims */, 1 /* rsize */,
5006 BRW_PREDICATE_NONE
);
5007 dest
.type
= atomic_result
.type
;
5008 bld
.MOV(dest
, atomic_result
);
5012 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5014 unsigned texture
= instr
->texture_index
;
5015 unsigned sampler
= instr
->sampler_index
;
5017 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5019 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5020 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5022 int lod_components
= 0;
5024 /* The hardware requires a LOD for buffer textures */
5025 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5026 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5028 uint32_t header_bits
= 0;
5029 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5030 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5031 switch (instr
->src
[i
].src_type
) {
5032 case nir_tex_src_bias
:
5033 srcs
[TEX_LOGICAL_SRC_LOD
] =
5034 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5036 case nir_tex_src_comparator
:
5037 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5039 case nir_tex_src_coord
:
5040 switch (instr
->op
) {
5042 case nir_texop_txf_ms
:
5043 case nir_texop_txf_ms_mcs
:
5044 case nir_texop_samples_identical
:
5045 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5048 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5052 case nir_tex_src_ddx
:
5053 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5054 lod_components
= nir_tex_instr_src_size(instr
, i
);
5056 case nir_tex_src_ddy
:
5057 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5059 case nir_tex_src_lod
:
5060 switch (instr
->op
) {
5062 srcs
[TEX_LOGICAL_SRC_LOD
] =
5063 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5066 srcs
[TEX_LOGICAL_SRC_LOD
] =
5067 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5070 srcs
[TEX_LOGICAL_SRC_LOD
] =
5071 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5075 case nir_tex_src_ms_index
:
5076 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5079 case nir_tex_src_offset
: {
5080 nir_const_value
*const_offset
=
5081 nir_src_as_const_value(instr
->src
[i
].src
);
5082 unsigned offset_bits
= 0;
5084 brw_texture_offset(const_offset
->i32
,
5085 nir_tex_instr_src_size(instr
, i
),
5087 header_bits
|= offset_bits
;
5089 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5090 retype(src
, BRW_REGISTER_TYPE_D
);
5095 case nir_tex_src_projector
:
5096 unreachable("should be lowered");
5098 case nir_tex_src_texture_offset
: {
5099 /* Figure out the highest possible texture index and mark it as used */
5100 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
5101 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
5102 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
5104 max_used
+= stage_prog_data
->binding_table
.texture_start
;
5106 brw_mark_surface_used(prog_data
, max_used
);
5108 /* Emit code to evaluate the actual indexing expression */
5109 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5110 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5111 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5115 case nir_tex_src_sampler_offset
: {
5116 /* Emit code to evaluate the actual indexing expression */
5117 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5118 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5119 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5123 case nir_tex_src_ms_mcs
:
5124 assert(instr
->op
== nir_texop_txf_ms
);
5125 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5128 case nir_tex_src_plane
: {
5129 nir_const_value
*const_plane
=
5130 nir_src_as_const_value(instr
->src
[i
].src
);
5131 const uint32_t plane
= const_plane
->u32
[0];
5132 const uint32_t texture_index
=
5133 instr
->texture_index
+
5134 stage_prog_data
->binding_table
.plane_start
[plane
] -
5135 stage_prog_data
->binding_table
.texture_start
;
5137 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5142 unreachable("unknown texture source");
5146 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5147 (instr
->op
== nir_texop_txf_ms
||
5148 instr
->op
== nir_texop_samples_identical
)) {
5149 if (devinfo
->gen
>= 7 &&
5150 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5151 srcs
[TEX_LOGICAL_SRC_MCS
] =
5152 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5153 instr
->coord_components
,
5154 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5156 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5160 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5161 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5164 switch (instr
->op
) {
5166 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5167 SHADER_OPCODE_TXL_LOGICAL
);
5170 opcode
= FS_OPCODE_TXB_LOGICAL
;
5173 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5176 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5179 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5181 case nir_texop_txf_ms
:
5182 if ((key_tex
->msaa_16
& (1 << sampler
)))
5183 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5185 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5187 case nir_texop_txf_ms_mcs
:
5188 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5190 case nir_texop_query_levels
:
5192 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5195 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5198 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5199 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5201 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5203 case nir_texop_texture_samples
:
5204 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5206 case nir_texop_samples_identical
: {
5207 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5209 /* If mcs is an immediate value, it means there is no MCS. In that case
5210 * just return false.
5212 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5213 bld
.MOV(dst
, brw_imm_ud(0u));
5214 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5215 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5216 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5217 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5218 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5220 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5221 BRW_CONDITIONAL_EQ
);
5226 unreachable("unknown texture opcode");
5229 if (instr
->op
== nir_texop_tg4
) {
5230 if (instr
->component
== 1 &&
5231 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5232 /* gather4 sampler is broken for green channel on RG32F --
5233 * we must ask for blue instead.
5235 header_bits
|= 2 << 16;
5237 header_bits
|= instr
->component
<< 16;
5241 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5242 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5243 inst
->offset
= header_bits
;
5245 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5246 if (devinfo
->gen
>= 9 &&
5247 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5248 unsigned write_mask
= instr
->dest
.is_ssa
?
5249 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5250 (1 << dest_size
) - 1;
5251 assert(write_mask
!= 0); /* dead code should have been eliminated */
5252 inst
->size_written
= util_last_bit(write_mask
) *
5253 inst
->dst
.component_size(inst
->exec_size
);
5255 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5258 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5259 inst
->shadow_compare
= true;
5261 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5262 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5265 for (unsigned i
= 0; i
< dest_size
; i
++)
5266 nir_dest
[i
] = offset(dst
, bld
, i
);
5268 if (instr
->op
== nir_texop_query_levels
) {
5269 /* # levels is in .w */
5270 nir_dest
[0] = offset(dst
, bld
, 3);
5271 } else if (instr
->op
== nir_texop_txs
&&
5272 dest_size
>= 3 && devinfo
->gen
< 7) {
5273 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5274 fs_reg depth
= offset(dst
, bld
, 2);
5275 nir_dest
[2] = vgrf(glsl_type::int_type
);
5276 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5279 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5283 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5285 switch (instr
->type
) {
5286 case nir_jump_break
:
5287 bld
.emit(BRW_OPCODE_BREAK
);
5289 case nir_jump_continue
:
5290 bld
.emit(BRW_OPCODE_CONTINUE
);
5292 case nir_jump_return
:
5294 unreachable("unknown jump");
5299 * This helper takes a source register and un/shuffles it into the destination
5302 * If source type size is smaller than destination type size the operation
5303 * needed is a component shuffle. The opposite case would be an unshuffle. If
5304 * source/destination type size is equal a shuffle is done that would be
5305 * equivalent to a simple MOV.
5307 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5308 * components .xyz 16-bit vector on SIMD8 would be.
5310 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5311 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5313 * This helper will return the following 2 32-bit components with the 16-bit
5316 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5317 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5319 * For unshuffle, the example would be the opposite, a 64-bit type source
5320 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5323 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5324 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5325 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5326 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5328 * The returned result would be the following 4 32-bit components unshuffled:
5330 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5331 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5332 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5333 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5335 * - Source and destination register must not be overlapped.
5336 * - components units are measured in terms of the smaller type between
5337 * source and destination because we are un/shuffling the smaller
5338 * components from/into the bigger ones.
5339 * - first_component parameter allows skipping source components.
5342 shuffle_src_to_dst(const fs_builder
&bld
,
5345 uint32_t first_component
,
5346 uint32_t components
)
5348 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5349 assert(!regions_overlap(dst
,
5350 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5351 offset(src
, bld
, first_component
),
5352 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5353 for (unsigned i
= 0; i
< components
; i
++) {
5354 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5355 offset(src
, bld
, i
+ first_component
));
5357 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5358 /* Source is shuffled into destination */
5359 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5360 assert(!regions_overlap(dst
,
5361 type_sz(dst
.type
) * bld
.dispatch_width() *
5362 DIV_ROUND_UP(components
, size_ratio
),
5363 offset(src
, bld
, first_component
),
5364 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5366 brw_reg_type shuffle_type
=
5367 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5368 BRW_REGISTER_TYPE_D
);
5369 for (unsigned i
= 0; i
< components
; i
++) {
5370 fs_reg shuffle_component_i
=
5371 subscript(offset(dst
, bld
, i
/ size_ratio
),
5372 shuffle_type
, i
% size_ratio
);
5373 bld
.MOV(shuffle_component_i
,
5374 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5377 /* Source is unshuffled into destination */
5378 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5379 assert(!regions_overlap(dst
,
5380 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5381 offset(src
, bld
, first_component
/ size_ratio
),
5382 type_sz(src
.type
) * bld
.dispatch_width() *
5383 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5386 brw_reg_type shuffle_type
=
5387 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5388 BRW_REGISTER_TYPE_D
);
5389 for (unsigned i
= 0; i
< components
; i
++) {
5390 fs_reg shuffle_component_i
=
5391 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5392 shuffle_type
, (first_component
+ i
) % size_ratio
);
5393 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5394 shuffle_component_i
);
5400 shuffle_from_32bit_read(const fs_builder
&bld
,
5403 uint32_t first_component
,
5404 uint32_t components
)
5406 assert(type_sz(src
.type
) == 4);
5408 /* This function takes components in units of the destination type while
5409 * shuffle_src_to_dst takes components in units of the smallest type
5411 if (type_sz(dst
.type
) > 4) {
5412 assert(type_sz(dst
.type
) == 8);
5413 first_component
*= 2;
5417 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5421 shuffle_for_32bit_write(const fs_builder
&bld
,
5423 uint32_t first_component
,
5424 uint32_t components
)
5426 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5427 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5428 /* This function takes components in units of the source type while
5429 * shuffle_src_to_dst takes components in units of the smallest type
5431 if (type_sz(src
.type
) > 4) {
5432 assert(type_sz(src
.type
) == 8);
5433 first_component
*= 2;
5437 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5443 setup_imm_df(const fs_builder
&bld
, double v
)
5445 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5446 assert(devinfo
->gen
>= 7);
5448 if (devinfo
->gen
>= 8)
5449 return brw_imm_df(v
);
5451 /* gen7.5 does not support DF immediates straighforward but the DIM
5452 * instruction allows to set the 64-bit immediate value.
5454 if (devinfo
->is_haswell
) {
5455 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5456 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5457 ubld
.DIM(dst
, brw_imm_df(v
));
5458 return component(dst
, 0);
5461 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5462 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5463 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5465 * Alternatively, we could also produce a normal VGRF (without stride 0)
5466 * by writing to all the channels in the VGRF, however, that would hit the
5467 * gen7 bug where we have to split writes that span more than 1 register
5468 * into instructions with a width of 4 (otherwise the write to the second
5469 * register written runs into an execmask hardware bug) which isn't very
5482 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5483 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5484 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5485 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5487 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5491 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5493 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5494 bld
.MOV(tmp
, brw_imm_w(v
));
5499 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5501 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5502 bld
.MOV(tmp
, brw_imm_uw(v
));