2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
) {
104 /* Add a uniform for the thread local id. It must be the last uniform
107 assert(uniforms
== prog_data
->nr_params
);
108 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
109 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
110 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
115 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
119 nir_foreach_instr(instr
, block
) {
120 if (instr
->type
!= nir_instr_type_intrinsic
)
123 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
124 switch (intrin
->intrinsic
) {
125 case nir_intrinsic_load_vertex_id
:
126 case nir_intrinsic_load_base_vertex
:
127 unreachable("should be lowered by nir_lower_system_values().");
129 case nir_intrinsic_load_vertex_id_zero_base
:
130 case nir_intrinsic_load_is_indexed_draw
:
131 case nir_intrinsic_load_first_vertex
:
132 case nir_intrinsic_load_instance_id
:
133 case nir_intrinsic_load_base_instance
:
134 case nir_intrinsic_load_draw_id
:
135 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
137 case nir_intrinsic_load_invocation_id
:
138 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
140 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
141 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
142 if (reg
->file
== BAD_FILE
) {
143 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
144 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
145 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
146 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
151 case nir_intrinsic_load_sample_pos
:
152 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
153 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
154 if (reg
->file
== BAD_FILE
)
155 *reg
= *v
->emit_samplepos_setup();
158 case nir_intrinsic_load_sample_id
:
159 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
160 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
161 if (reg
->file
== BAD_FILE
)
162 *reg
= *v
->emit_sampleid_setup();
165 case nir_intrinsic_load_sample_mask_in
:
166 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
167 assert(v
->devinfo
->gen
>= 7);
168 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
169 if (reg
->file
== BAD_FILE
)
170 *reg
= *v
->emit_samplemaskin_setup();
173 case nir_intrinsic_load_work_group_id
:
174 assert(v
->stage
== MESA_SHADER_COMPUTE
);
175 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
176 if (reg
->file
== BAD_FILE
)
177 *reg
= *v
->emit_cs_work_group_id_setup();
180 case nir_intrinsic_load_helper_invocation
:
181 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
182 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
183 if (reg
->file
== BAD_FILE
) {
184 const fs_builder abld
=
185 v
->bld
.annotate("gl_HelperInvocation", NULL
);
187 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
188 * pixel mask is in g1.7 of the thread payload.
190 * We move the per-channel pixel enable bit to the low bit of each
191 * channel by shifting the byte containing the pixel mask by the
192 * vector immediate 0x76543210UV.
194 * The region of <1,8,0> reads only 1 byte (the pixel masks for
195 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
196 * masks for 2 and 3) in SIMD16.
198 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
200 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
201 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
202 hbld
.SHR(offset(shifted
, hbld
, i
),
203 stride(retype(brw_vec1_grf(1 + i
, 7),
204 BRW_REGISTER_TYPE_UB
),
206 brw_imm_v(0x76543210));
209 /* A set bit in the pixel mask means the channel is enabled, but
210 * that is the opposite of gl_HelperInvocation so we need to invert
213 * The negate source-modifier bit of logical instructions on Gen8+
214 * performs 1's complement negation, so we can use that instead of
217 fs_reg inverted
= negate(shifted
);
218 if (v
->devinfo
->gen
< 8) {
219 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
220 abld
.NOT(inverted
, shifted
);
223 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
224 * with 1 and negating.
226 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
227 abld
.AND(anded
, inverted
, brw_imm_uw(1));
229 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
230 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
244 fs_visitor::nir_emit_system_values()
246 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
247 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
248 nir_system_values
[i
] = fs_reg();
251 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
252 * never end up using it.
255 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
256 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
257 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
259 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
260 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
261 if (dispatch_width
> 8)
262 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
263 if (dispatch_width
> 16) {
264 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
265 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
269 nir_foreach_function(function
, nir
) {
270 assert(strcmp(function
->name
, "main") == 0);
271 assert(function
->impl
);
272 nir_foreach_block(block
, function
->impl
) {
273 emit_system_values_block(block
, this);
279 * Returns a type based on a reference_type (word, float, half-float) and a
282 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
284 * @FIXME: 64-bit return types are always DF on integer types to maintain
285 * compability with uses of DF previously to the introduction of int64
289 brw_reg_type_from_bit_size(const unsigned bit_size
,
290 const brw_reg_type reference_type
)
292 switch(reference_type
) {
293 case BRW_REGISTER_TYPE_HF
:
294 case BRW_REGISTER_TYPE_F
:
295 case BRW_REGISTER_TYPE_DF
:
298 return BRW_REGISTER_TYPE_HF
;
300 return BRW_REGISTER_TYPE_F
;
302 return BRW_REGISTER_TYPE_DF
;
304 unreachable("Invalid bit size");
306 case BRW_REGISTER_TYPE_B
:
307 case BRW_REGISTER_TYPE_W
:
308 case BRW_REGISTER_TYPE_D
:
309 case BRW_REGISTER_TYPE_Q
:
312 return BRW_REGISTER_TYPE_B
;
314 return BRW_REGISTER_TYPE_W
;
316 return BRW_REGISTER_TYPE_D
;
318 return BRW_REGISTER_TYPE_Q
;
320 unreachable("Invalid bit size");
322 case BRW_REGISTER_TYPE_UB
:
323 case BRW_REGISTER_TYPE_UW
:
324 case BRW_REGISTER_TYPE_UD
:
325 case BRW_REGISTER_TYPE_UQ
:
328 return BRW_REGISTER_TYPE_UB
;
330 return BRW_REGISTER_TYPE_UW
;
332 return BRW_REGISTER_TYPE_UD
;
334 return BRW_REGISTER_TYPE_UQ
;
336 unreachable("Invalid bit size");
339 unreachable("Unknown type");
344 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
346 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
347 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
348 nir_locals
[i
] = fs_reg();
351 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
352 unsigned array_elems
=
353 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
354 unsigned size
= array_elems
* reg
->num_components
;
355 const brw_reg_type reg_type
=
356 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
357 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
360 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
363 nir_emit_cf_list(&impl
->body
);
367 fs_visitor::nir_emit_cf_list(exec_list
*list
)
369 exec_list_validate(list
);
370 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
371 switch (node
->type
) {
373 nir_emit_if(nir_cf_node_as_if(node
));
376 case nir_cf_node_loop
:
377 nir_emit_loop(nir_cf_node_as_loop(node
));
380 case nir_cf_node_block
:
381 nir_emit_block(nir_cf_node_as_block(node
));
385 unreachable("Invalid CFG node block");
391 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
393 /* first, put the condition into f0 */
394 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
395 retype(get_nir_src(if_stmt
->condition
),
396 BRW_REGISTER_TYPE_D
));
397 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
399 bld
.IF(BRW_PREDICATE_NORMAL
);
401 nir_emit_cf_list(&if_stmt
->then_list
);
403 /* note: if the else is empty, dead CF elimination will remove it */
404 bld
.emit(BRW_OPCODE_ELSE
);
406 nir_emit_cf_list(&if_stmt
->else_list
);
408 bld
.emit(BRW_OPCODE_ENDIF
);
410 if (devinfo
->gen
< 7)
411 limit_dispatch_width(16, "Non-uniform control flow unsupported "
416 fs_visitor::nir_emit_loop(nir_loop
*loop
)
418 bld
.emit(BRW_OPCODE_DO
);
420 nir_emit_cf_list(&loop
->body
);
422 bld
.emit(BRW_OPCODE_WHILE
);
424 if (devinfo
->gen
< 7)
425 limit_dispatch_width(16, "Non-uniform control flow unsupported "
430 fs_visitor::nir_emit_block(nir_block
*block
)
432 nir_foreach_instr(instr
, block
) {
433 nir_emit_instr(instr
);
438 fs_visitor::nir_emit_instr(nir_instr
*instr
)
440 const fs_builder abld
= bld
.annotate(NULL
, instr
);
442 switch (instr
->type
) {
443 case nir_instr_type_alu
:
444 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
447 case nir_instr_type_deref
:
448 /* Derefs can exist for images but they do nothing */
451 case nir_instr_type_intrinsic
:
453 case MESA_SHADER_VERTEX
:
454 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_TESS_CTRL
:
457 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_TESS_EVAL
:
460 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case MESA_SHADER_GEOMETRY
:
463 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_FRAGMENT
:
466 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_COMPUTE
:
469 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 unreachable("unsupported shader stage");
476 case nir_instr_type_tex
:
477 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
480 case nir_instr_type_load_const
:
481 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
484 case nir_instr_type_ssa_undef
:
485 /* We create a new VGRF for undefs on every use (by handling
486 * them in get_nir_src()), rather than for each definition.
487 * This helps register coalescing eliminate MOVs from undef.
491 case nir_instr_type_jump
:
492 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
496 unreachable("unknown instruction type");
501 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
505 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
506 const fs_reg
&result
)
508 if (!instr
->src
[0].src
.is_ssa
||
509 !instr
->src
[0].src
.ssa
->parent_instr
)
512 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
515 nir_alu_instr
*src0
=
516 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
518 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
519 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
522 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
523 assert(element
!= NULL
);
525 /* Element type to extract.*/
526 const brw_reg_type type
= brw_int_type(
527 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
528 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
530 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
531 op0
.type
= brw_type_for_nir_type(devinfo
,
532 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
533 nir_src_bit_size(src0
->src
[0].src
)));
534 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
536 set_saturate(instr
->dest
.saturate
,
537 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
542 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
543 const fs_reg
&result
)
545 if (!instr
->src
[0].src
.is_ssa
||
546 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
549 nir_intrinsic_instr
*src0
=
550 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
552 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
555 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
556 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
559 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
560 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
563 fs_reg tmp
= vgrf(glsl_type::int_type
);
565 if (devinfo
->gen
>= 6) {
566 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
567 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
569 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
571 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
572 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
574 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
576 * This negation looks like it's safe in practice, because bits 0:4 will
577 * surely be TRIANGLES
580 if (value1
->f32
[0] == -1.0f
) {
584 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
585 g0
, brw_imm_uw(0x3f80));
587 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
588 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
590 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
592 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
593 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
595 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
597 * This negation looks like it's safe in practice, because bits 0:4 will
598 * surely be TRIANGLES
601 if (value1
->f32
[0] == -1.0f
) {
605 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
607 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
613 emit_find_msb_using_lzd(const fs_builder
&bld
,
614 const fs_reg
&result
,
622 /* LZD of an absolute value source almost always does the right
623 * thing. There are two problem values:
625 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
626 * 0. However, findMSB(int(0x80000000)) == 30.
628 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
629 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
631 * For a value of zero or negative one, -1 will be returned.
633 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
634 * findMSB(-(1<<x)) should return x-1.
636 * For all negative number cases, including 0x80000000 and
637 * 0xffffffff, the correct value is obtained from LZD if instead of
638 * negating the (already negative) value the logical-not is used. A
639 * conditonal logical-not can be achieved in two instructions.
641 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
643 bld
.ASR(temp
, src
, brw_imm_d(31));
644 bld
.XOR(temp
, temp
, src
);
647 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
648 retype(temp
, BRW_REGISTER_TYPE_UD
));
650 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
651 * from the LSB side. Subtract the result from 31 to convert the MSB
652 * count into an LSB count. If no bits are set, LZD will return 32.
653 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
655 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
656 inst
->src
[0].negate
= true;
660 brw_rnd_mode_from_nir_op (const nir_op op
) {
662 case nir_op_f2f16_rtz
:
663 return BRW_RND_MODE_RTZ
;
664 case nir_op_f2f16_rtne
:
665 return BRW_RND_MODE_RTNE
;
667 unreachable("Operation doesn't support rounding mode");
672 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
674 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
677 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
678 result
.type
= brw_type_for_nir_type(devinfo
,
679 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
680 nir_dest_bit_size(instr
->dest
.dest
)));
683 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
684 op
[i
] = get_nir_src(instr
->src
[i
].src
);
685 op
[i
].type
= brw_type_for_nir_type(devinfo
,
686 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
687 nir_src_bit_size(instr
->src
[i
].src
)));
688 op
[i
].abs
= instr
->src
[i
].abs
;
689 op
[i
].negate
= instr
->src
[i
].negate
;
692 /* We get a bunch of mov's out of the from_ssa pass and they may still
693 * be vectorized. We'll handle them as a special-case. We'll also
694 * handle vecN here because it's basically the same thing.
702 fs_reg temp
= result
;
703 bool need_extra_copy
= false;
704 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
705 if (!instr
->src
[i
].src
.is_ssa
&&
706 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
707 need_extra_copy
= true;
708 temp
= bld
.vgrf(result
.type
, 4);
713 for (unsigned i
= 0; i
< 4; i
++) {
714 if (!(instr
->dest
.write_mask
& (1 << i
)))
717 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
718 inst
= bld
.MOV(offset(temp
, bld
, i
),
719 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
721 inst
= bld
.MOV(offset(temp
, bld
, i
),
722 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
724 inst
->saturate
= instr
->dest
.saturate
;
727 /* In this case the source and destination registers were the same,
728 * so we need to insert an extra set of moves in order to deal with
731 if (need_extra_copy
) {
732 for (unsigned i
= 0; i
< 4; i
++) {
733 if (!(instr
->dest
.write_mask
& (1 << i
)))
736 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
745 /* At this point, we have dealt with any instruction that operates on
746 * more than a single channel. Therefore, we can just adjust the source
747 * and destination registers for that channel and emit the instruction.
749 unsigned channel
= 0;
750 if (nir_op_infos
[instr
->op
].output_size
== 0) {
751 /* Since NIR is doing the scalarizing for us, we should only ever see
752 * vectorized operations with a single channel.
754 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
755 channel
= ffs(instr
->dest
.write_mask
) - 1;
757 result
= offset(result
, bld
, channel
);
760 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
761 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
762 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
768 if (optimize_extract_to_float(instr
, result
))
770 inst
= bld
.MOV(result
, op
[0]);
771 inst
->saturate
= instr
->dest
.saturate
;
774 case nir_op_f2f16_rtne
:
775 case nir_op_f2f16_rtz
:
776 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
777 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
780 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
781 * on the HW gen, it is a special hw opcode or just a MOV, and
782 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
784 * But if we want to use that opcode, we need to provide support on
785 * different optimizations and lowerings. As right now HF support is
786 * only for gen8+, it will be better to use directly the MOV, and use
787 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
790 case nir_op_f2f16_undef
:
791 inst
= bld
.MOV(result
, op
[0]);
792 inst
->saturate
= instr
->dest
.saturate
;
802 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
804 * "When source or destination is 64b (...), regioning in Align1
805 * must follow these rules:
807 * 1. Source and destination horizontal stride must be aligned to
811 * This means that conversions from bit-sizes smaller than 64-bit to
812 * 64-bit need to have the source data elements aligned to 64-bit.
813 * This restriction does not apply to BDW and later.
815 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
816 nir_src_bit_size(instr
->src
[0].src
) < 64 &&
817 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
818 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
819 tmp
= subscript(tmp
, op
[0].type
, 0);
820 inst
= bld
.MOV(tmp
, op
[0]);
821 inst
= bld
.MOV(result
, tmp
);
822 inst
->saturate
= instr
->dest
.saturate
;
837 inst
= bld
.MOV(result
, op
[0]);
838 inst
->saturate
= instr
->dest
.saturate
;
843 /* Straightforward since the source can be assumed to be either
844 * strictly >= 0 or strictly <= 0 depending on the setting of the
847 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
849 inst
= (op
[0].negate
)
850 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
851 : bld
.MOV(result
, brw_imm_f(1.0f
));
853 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
855 if (instr
->dest
.saturate
)
856 inst
->saturate
= true;
858 } else if (type_sz(op
[0].type
) < 8) {
859 /* AND(val, 0x80000000) gives the sign bit.
861 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
864 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
866 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
867 op
[0].type
= BRW_REGISTER_TYPE_UD
;
868 result
.type
= BRW_REGISTER_TYPE_UD
;
869 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
871 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
872 inst
->predicate
= BRW_PREDICATE_NORMAL
;
873 if (instr
->dest
.saturate
) {
874 inst
= bld
.MOV(result
, result
);
875 inst
->saturate
= true;
878 /* For doubles we do the same but we need to consider:
880 * - 2-src instructions can't operate with 64-bit immediates
881 * - The sign is encoded in the high 32-bit of each DF
882 * - We need to produce a DF result.
885 fs_reg zero
= vgrf(glsl_type::double_type
);
886 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
887 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
889 bld
.MOV(result
, zero
);
891 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
892 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
893 brw_imm_ud(0x80000000u
));
895 set_predicate(BRW_PREDICATE_NORMAL
,
896 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
898 if (instr
->dest
.saturate
) {
899 inst
= bld
.MOV(result
, result
);
900 inst
->saturate
= true;
907 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
908 * -> non-negative val generates 0x00000000.
909 * Predicated OR sets 1 if val is positive.
911 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
912 assert(bit_size
== 32 || bit_size
== 16);
914 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
915 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
916 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
918 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
919 bld
.ASR(result
, op
[0], shift
);
920 inst
= bld
.OR(result
, result
, one
);
921 inst
->predicate
= BRW_PREDICATE_NORMAL
;
926 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
927 inst
->saturate
= instr
->dest
.saturate
;
931 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
932 inst
->saturate
= instr
->dest
.saturate
;
936 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
937 inst
->saturate
= instr
->dest
.saturate
;
941 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
942 inst
->saturate
= instr
->dest
.saturate
;
946 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
947 inst
->saturate
= instr
->dest
.saturate
;
951 if (fs_key
->high_quality_derivatives
) {
952 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
954 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
956 inst
->saturate
= instr
->dest
.saturate
;
958 case nir_op_fddx_fine
:
959 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
960 inst
->saturate
= instr
->dest
.saturate
;
962 case nir_op_fddx_coarse
:
963 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
964 inst
->saturate
= instr
->dest
.saturate
;
967 if (fs_key
->high_quality_derivatives
) {
968 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
970 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
972 inst
->saturate
= instr
->dest
.saturate
;
974 case nir_op_fddy_fine
:
975 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
976 inst
->saturate
= instr
->dest
.saturate
;
978 case nir_op_fddy_coarse
:
979 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
980 inst
->saturate
= instr
->dest
.saturate
;
985 inst
= bld
.ADD(result
, op
[0], op
[1]);
986 inst
->saturate
= instr
->dest
.saturate
;
990 inst
= bld
.MUL(result
, op
[0], op
[1]);
991 inst
->saturate
= instr
->dest
.saturate
;
995 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
996 bld
.MUL(result
, op
[0], op
[1]);
999 case nir_op_imul_high
:
1000 case nir_op_umul_high
:
1001 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1002 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1007 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1008 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1011 case nir_op_uadd_carry
:
1012 unreachable("Should have been lowered by carry_to_arith().");
1014 case nir_op_usub_borrow
:
1015 unreachable("Should have been lowered by borrow_to_arith().");
1019 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1020 * appears that our hardware just does the right thing for signed
1023 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1024 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1028 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1029 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1031 /* Math instructions don't support conditional mod */
1032 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1033 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1035 /* Now, we need to determine if signs of the sources are different.
1036 * When we XOR the sources, the top bit is 0 if they are the same and 1
1037 * if they are different. We can then use a conditional modifier to
1038 * turn that into a predicate. This leads us to an XOR.l instruction.
1040 * Technically, according to the PRM, you're not allowed to use .l on a
1041 * XOR instruction. However, emperical experiments and Curro's reading
1042 * of the simulator source both indicate that it's safe.
1044 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1045 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1046 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1047 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1049 /* If the result of the initial remainder operation is non-zero and the
1050 * two sources have different signs, add in a copy of op[1] to get the
1051 * final integer modulus value.
1053 inst
= bld
.ADD(result
, result
, op
[1]);
1054 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1062 fs_reg dest
= result
;
1064 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1066 dest
= bld
.vgrf(op
[0].type
, 1);
1068 brw_conditional_mod cond
;
1069 switch (instr
->op
) {
1071 cond
= BRW_CONDITIONAL_L
;
1074 cond
= BRW_CONDITIONAL_GE
;
1077 cond
= BRW_CONDITIONAL_Z
;
1080 cond
= BRW_CONDITIONAL_NZ
;
1083 unreachable("bad opcode");
1086 bld
.CMP(dest
, op
[0], op
[1], cond
);
1088 if (bit_size
> 32) {
1089 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1090 } else if(bit_size
< 32) {
1091 /* When we convert the result to 32-bit we need to be careful and do
1092 * it as a signed conversion to get sign extension (for 32-bit true)
1094 const brw_reg_type src_type
=
1095 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1097 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1108 fs_reg dest
= result
;
1110 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1112 dest
= bld
.vgrf(op
[0].type
, 1);
1114 brw_conditional_mod cond
;
1115 switch (instr
->op
) {
1118 cond
= BRW_CONDITIONAL_L
;
1122 cond
= BRW_CONDITIONAL_GE
;
1125 cond
= BRW_CONDITIONAL_Z
;
1128 cond
= BRW_CONDITIONAL_NZ
;
1131 unreachable("bad opcode");
1133 bld
.CMP(dest
, op
[0], op
[1], cond
);
1135 if (bit_size
> 32) {
1136 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1137 } else if (bit_size
< 32) {
1138 /* When we convert the result to 32-bit we need to be careful and do
1139 * it as a signed conversion to get sign extension (for 32-bit true)
1141 const brw_reg_type src_type
=
1142 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1144 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1150 if (devinfo
->gen
>= 8) {
1151 op
[0] = resolve_source_modifiers(op
[0]);
1153 bld
.NOT(result
, op
[0]);
1156 if (devinfo
->gen
>= 8) {
1157 op
[0] = resolve_source_modifiers(op
[0]);
1158 op
[1] = resolve_source_modifiers(op
[1]);
1160 bld
.XOR(result
, op
[0], op
[1]);
1163 if (devinfo
->gen
>= 8) {
1164 op
[0] = resolve_source_modifiers(op
[0]);
1165 op
[1] = resolve_source_modifiers(op
[1]);
1167 bld
.OR(result
, op
[0], op
[1]);
1170 if (devinfo
->gen
>= 8) {
1171 op
[0] = resolve_source_modifiers(op
[0]);
1172 op
[1] = resolve_source_modifiers(op
[1]);
1174 bld
.AND(result
, op
[0], op
[1]);
1180 case nir_op_ball_fequal2
:
1181 case nir_op_ball_iequal2
:
1182 case nir_op_ball_fequal3
:
1183 case nir_op_ball_iequal3
:
1184 case nir_op_ball_fequal4
:
1185 case nir_op_ball_iequal4
:
1186 case nir_op_bany_fnequal2
:
1187 case nir_op_bany_inequal2
:
1188 case nir_op_bany_fnequal3
:
1189 case nir_op_bany_inequal3
:
1190 case nir_op_bany_fnequal4
:
1191 case nir_op_bany_inequal4
:
1192 unreachable("Lowered by nir_lower_alu_reductions");
1194 case nir_op_fnoise1_1
:
1195 case nir_op_fnoise1_2
:
1196 case nir_op_fnoise1_3
:
1197 case nir_op_fnoise1_4
:
1198 case nir_op_fnoise2_1
:
1199 case nir_op_fnoise2_2
:
1200 case nir_op_fnoise2_3
:
1201 case nir_op_fnoise2_4
:
1202 case nir_op_fnoise3_1
:
1203 case nir_op_fnoise3_2
:
1204 case nir_op_fnoise3_3
:
1205 case nir_op_fnoise3_4
:
1206 case nir_op_fnoise4_1
:
1207 case nir_op_fnoise4_2
:
1208 case nir_op_fnoise4_3
:
1209 case nir_op_fnoise4_4
:
1210 unreachable("not reached: should be handled by lower_noise");
1213 unreachable("not reached: should be handled by ldexp_to_arith()");
1216 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1217 inst
->saturate
= instr
->dest
.saturate
;
1221 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1222 inst
->saturate
= instr
->dest
.saturate
;
1227 bld
.MOV(result
, negate(op
[0]));
1232 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1233 if (bit_size
== 64) {
1234 /* two-argument instructions can't take 64-bit immediates */
1238 if (instr
->op
== nir_op_f2b
) {
1239 zero
= vgrf(glsl_type::double_type
);
1240 tmp
= vgrf(glsl_type::double_type
);
1241 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1243 zero
= vgrf(glsl_type::int64_t_type
);
1244 tmp
= vgrf(glsl_type::int64_t_type
);
1245 bld
.MOV(zero
, brw_imm_q(0));
1248 /* A SIMD16 execution needs to be split in two instructions, so use
1249 * a vgrf instead of the flag register as dst so instruction splitting
1252 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1253 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1256 if (bit_size
== 32) {
1257 zero
= instr
->op
== nir_op_f2b
? brw_imm_f(0.0f
) : brw_imm_d(0);
1259 assert(bit_size
== 16);
1260 zero
= instr
->op
== nir_op_f2b
?
1261 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1263 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1269 inst
= bld
.RNDZ(result
, op
[0]);
1270 inst
->saturate
= instr
->dest
.saturate
;
1273 case nir_op_fceil
: {
1274 op
[0].negate
= !op
[0].negate
;
1275 fs_reg temp
= vgrf(glsl_type::float_type
);
1276 bld
.RNDD(temp
, op
[0]);
1278 inst
= bld
.MOV(result
, temp
);
1279 inst
->saturate
= instr
->dest
.saturate
;
1283 inst
= bld
.RNDD(result
, op
[0]);
1284 inst
->saturate
= instr
->dest
.saturate
;
1287 inst
= bld
.FRC(result
, op
[0]);
1288 inst
->saturate
= instr
->dest
.saturate
;
1290 case nir_op_fround_even
:
1291 inst
= bld
.RNDE(result
, op
[0]);
1292 inst
->saturate
= instr
->dest
.saturate
;
1295 case nir_op_fquantize2f16
: {
1296 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1297 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1298 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1300 /* The destination stride must be at least as big as the source stride. */
1301 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1304 /* Check for denormal */
1305 fs_reg abs_src0
= op
[0];
1306 abs_src0
.abs
= true;
1307 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1309 /* Get the appropriately signed zero */
1310 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1311 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1312 brw_imm_ud(0x80000000));
1313 /* Do the actual F32 -> F16 -> F32 conversion */
1314 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1315 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1316 /* Select that or zero based on normal status */
1317 inst
= bld
.SEL(result
, zero
, tmp32
);
1318 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1319 inst
->saturate
= instr
->dest
.saturate
;
1326 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1327 inst
->saturate
= instr
->dest
.saturate
;
1333 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1334 inst
->saturate
= instr
->dest
.saturate
;
1337 case nir_op_pack_snorm_2x16
:
1338 case nir_op_pack_snorm_4x8
:
1339 case nir_op_pack_unorm_2x16
:
1340 case nir_op_pack_unorm_4x8
:
1341 case nir_op_unpack_snorm_2x16
:
1342 case nir_op_unpack_snorm_4x8
:
1343 case nir_op_unpack_unorm_2x16
:
1344 case nir_op_unpack_unorm_4x8
:
1345 case nir_op_unpack_half_2x16
:
1346 case nir_op_pack_half_2x16
:
1347 unreachable("not reached: should be handled by lower_packing_builtins");
1349 case nir_op_unpack_half_2x16_split_x
:
1350 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1351 inst
->saturate
= instr
->dest
.saturate
;
1353 case nir_op_unpack_half_2x16_split_y
:
1354 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1355 inst
->saturate
= instr
->dest
.saturate
;
1358 case nir_op_pack_64_2x32_split
:
1359 case nir_op_pack_32_2x16_split
:
1360 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1363 case nir_op_unpack_64_2x32_split_x
:
1364 case nir_op_unpack_64_2x32_split_y
: {
1365 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1366 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1368 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1372 case nir_op_unpack_32_2x16_split_x
:
1373 case nir_op_unpack_32_2x16_split_y
: {
1374 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1375 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1377 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1382 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1383 inst
->saturate
= instr
->dest
.saturate
;
1386 case nir_op_bitfield_reverse
:
1387 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1388 bld
.BFREV(result
, op
[0]);
1391 case nir_op_bit_count
:
1392 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1393 bld
.CBIT(result
, op
[0]);
1396 case nir_op_ufind_msb
: {
1397 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1398 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1402 case nir_op_ifind_msb
: {
1403 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1405 if (devinfo
->gen
< 7) {
1406 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1408 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1410 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1411 * count from the LSB side. If FBH didn't return an error
1412 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1413 * count into an LSB count.
1415 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1417 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1418 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1419 inst
->src
[0].negate
= true;
1424 case nir_op_find_lsb
:
1425 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1427 if (devinfo
->gen
< 7) {
1428 fs_reg temp
= vgrf(glsl_type::int_type
);
1430 /* (x & -x) generates a value that consists of only the LSB of x.
1431 * For all powers of 2, findMSB(y) == findLSB(y).
1433 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1434 fs_reg negated_src
= src
;
1436 /* One must be negated, and the other must be non-negated. It
1437 * doesn't matter which is which.
1439 negated_src
.negate
= true;
1442 bld
.AND(temp
, src
, negated_src
);
1443 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1445 bld
.FBL(result
, op
[0]);
1449 case nir_op_ubitfield_extract
:
1450 case nir_op_ibitfield_extract
:
1451 unreachable("should have been lowered");
1454 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1455 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1458 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1459 bld
.BFI1(result
, op
[0], op
[1]);
1462 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1463 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1466 case nir_op_bitfield_insert
:
1467 unreachable("not reached: should have been lowered");
1472 fs_reg shift_count
= op
[1];
1474 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1475 if (op
[1].file
== VGRF
&&
1476 (result
.type
== BRW_REGISTER_TYPE_Q
||
1477 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1478 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1479 BRW_REGISTER_TYPE_UD
);
1480 shift_count
.stride
= 2;
1481 bld
.MOV(shift_count
, op
[1]);
1485 switch (instr
->op
) {
1487 bld
.SHL(result
, op
[0], shift_count
);
1490 bld
.ASR(result
, op
[0], shift_count
);
1493 bld
.SHR(result
, op
[0], shift_count
);
1496 unreachable("not reached");
1501 case nir_op_pack_half_2x16_split
:
1502 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1506 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1507 inst
->saturate
= instr
->dest
.saturate
;
1511 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1512 inst
->saturate
= instr
->dest
.saturate
;
1516 if (optimize_frontfacing_ternary(instr
, result
))
1519 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1520 inst
= bld
.SEL(result
, op
[1], op
[2]);
1521 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1524 case nir_op_extract_u8
:
1525 case nir_op_extract_i8
: {
1526 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1527 assert(byte
!= NULL
);
1532 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1533 * Use two instructions and a word or DWord intermediate integer type.
1535 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1536 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1538 if (instr
->op
== nir_op_extract_i8
) {
1539 /* If we need to sign extend, extract to a word first */
1540 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1541 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
->u32
[0]));
1542 bld
.MOV(result
, w_temp
);
1544 /* Otherwise use an AND with 0xff and a word type */
1545 bld
.AND(result
, subscript(op
[0], type
, byte
->u32
[0] / 2), brw_imm_uw(0xff));
1548 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1549 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1554 case nir_op_extract_u16
:
1555 case nir_op_extract_i16
: {
1556 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1557 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1558 assert(word
!= NULL
);
1559 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1564 unreachable("unhandled instruction");
1567 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1568 * to sign extend the low bit to 0/~0
1570 if (devinfo
->gen
<= 5 &&
1571 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1572 fs_reg masked
= vgrf(glsl_type::int_type
);
1573 bld
.AND(masked
, result
, brw_imm_d(1));
1574 masked
.negate
= true;
1575 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1580 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1581 nir_load_const_instr
*instr
)
1583 const brw_reg_type reg_type
=
1584 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1585 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1587 switch (instr
->def
.bit_size
) {
1589 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1590 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1594 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1595 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1599 assert(devinfo
->gen
>= 7);
1600 if (devinfo
->gen
== 7) {
1601 /* We don't get 64-bit integer types until gen8 */
1602 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1603 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1604 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1607 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1608 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1613 unreachable("Invalid bit size");
1616 nir_ssa_values
[instr
->def
.index
] = reg
;
1620 fs_visitor::get_nir_src(const nir_src
&src
)
1624 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1625 const brw_reg_type reg_type
=
1626 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1627 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1629 reg
= nir_ssa_values
[src
.ssa
->index
];
1632 /* We don't handle indirects on locals */
1633 assert(src
.reg
.indirect
== NULL
);
1634 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1635 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1638 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1639 /* The only 64-bit type available on gen7 is DF, so use that. */
1640 reg
.type
= BRW_REGISTER_TYPE_DF
;
1642 /* To avoid floating-point denorm flushing problems, set the type by
1643 * default to an integer type - instructions that need floating point
1644 * semantics will set this to F if they need to
1646 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1647 BRW_REGISTER_TYPE_D
);
1654 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1656 * This function should not be called on any value which may be 64 bits.
1657 * We could theoretically support 64-bit on gen8+ but we choose not to
1658 * because it wouldn't work in general (no gen7 support) and there are
1659 * enough restrictions in 64-bit immediates that you can't take the return
1660 * value and treat it the same as the result of get_nir_src().
1663 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1665 nir_const_value
*val
= nir_src_as_const_value(src
);
1666 assert(nir_src_bit_size(src
) == 32);
1667 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1671 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1674 const brw_reg_type reg_type
=
1675 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1676 dest
.ssa
.bit_size
== 8 ?
1677 BRW_REGISTER_TYPE_D
:
1678 BRW_REGISTER_TYPE_F
);
1679 nir_ssa_values
[dest
.ssa
.index
] =
1680 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1681 return nir_ssa_values
[dest
.ssa
.index
];
1683 /* We don't handle indirects on locals */
1684 assert(dest
.reg
.indirect
== NULL
);
1685 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1686 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1691 fs_visitor::get_nir_image_deref(nir_deref_instr
*deref
)
1693 fs_reg arr_offset
= brw_imm_ud(0);
1694 unsigned array_size
= BRW_IMAGE_PARAM_SIZE
* 4;
1695 nir_deref_instr
*head
= deref
;
1696 while (head
->deref_type
!= nir_deref_type_var
) {
1697 assert(head
->deref_type
== nir_deref_type_array
);
1699 /* This level's element size is the previous level's array size */
1700 const unsigned elem_size
= array_size
;
1702 fs_reg index
= retype(get_nir_src_imm(head
->arr
.index
),
1703 BRW_REGISTER_TYPE_UD
);
1704 if (arr_offset
.file
== BRW_IMMEDIATE_VALUE
&&
1705 index
.file
== BRW_IMMEDIATE_VALUE
) {
1706 arr_offset
.ud
+= index
.ud
* elem_size
;
1707 } else if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1708 bld
.ADD(arr_offset
, arr_offset
, brw_imm_ud(index
.ud
* elem_size
));
1710 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
1711 bld
.MUL(tmp
, index
, brw_imm_ud(elem_size
));
1712 bld
.ADD(tmp
, tmp
, arr_offset
);
1716 head
= nir_deref_instr_parent(head
);
1717 assert(glsl_type_is_array(head
->type
));
1718 array_size
= elem_size
* glsl_get_length(head
->type
);
1721 assert(head
->deref_type
== nir_deref_type_var
);
1722 const unsigned max_arr_offset
= array_size
- (BRW_IMAGE_PARAM_SIZE
* 4);
1723 fs_reg
image(UNIFORM
, head
->var
->data
.driver_location
/ 4,
1724 BRW_REGISTER_TYPE_UD
);
1726 if (arr_offset
.file
== BRW_IMMEDIATE_VALUE
) {
1727 /* The offset is in bytes but we want it in dwords */
1728 return offset(image
, bld
, MIN2(arr_offset
.ud
, max_arr_offset
) / 4);
1730 /* Accessing an invalid surface index with the dataport can result
1731 * in a hang. According to the spec "if the index used to
1732 * select an individual element is negative or greater than or
1733 * equal to the size of the array, the results of the operation
1734 * are undefined but may not lead to termination" -- which is one
1735 * of the possible outcomes of the hang. Clamp the index to
1736 * prevent access outside of the array bounds.
1738 bld
.emit_minmax(arr_offset
, arr_offset
, brw_imm_ud(max_arr_offset
),
1741 /* Emit a pile of MOVs to load the uniform into a temporary. The
1742 * dead-code elimination pass will get rid of what we don't use.
1744 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1745 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1746 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1747 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1748 arr_offset
, brw_imm_ud(max_arr_offset
+ 4));
1755 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1758 for (unsigned i
= 0; i
< 4; i
++) {
1759 if (!((wr_mask
>> i
) & 1))
1762 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1763 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1764 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1765 if (new_inst
->src
[j
].file
== VGRF
)
1766 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1773 * Get the matching channel register datatype for an image intrinsic of the
1774 * specified GLSL image type.
1777 get_image_base_type(const glsl_type
*type
)
1779 switch ((glsl_base_type
)type
->sampled_type
) {
1780 case GLSL_TYPE_UINT
:
1781 return BRW_REGISTER_TYPE_UD
;
1783 return BRW_REGISTER_TYPE_D
;
1784 case GLSL_TYPE_FLOAT
:
1785 return BRW_REGISTER_TYPE_F
;
1787 unreachable("Not reached.");
1792 * Get the appropriate atomic op for an image atomic intrinsic.
1795 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1798 case nir_intrinsic_image_deref_atomic_add
:
1800 case nir_intrinsic_image_deref_atomic_min
:
1801 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1802 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1803 case nir_intrinsic_image_deref_atomic_max
:
1804 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1805 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1806 case nir_intrinsic_image_deref_atomic_and
:
1808 case nir_intrinsic_image_deref_atomic_or
:
1810 case nir_intrinsic_image_deref_atomic_xor
:
1812 case nir_intrinsic_image_deref_atomic_exchange
:
1814 case nir_intrinsic_image_deref_atomic_comp_swap
:
1815 return BRW_AOP_CMPWR
;
1817 unreachable("Not reachable.");
1822 emit_pixel_interpolater_send(const fs_builder
&bld
,
1827 glsl_interp_mode interpolation
)
1829 struct brw_wm_prog_data
*wm_prog_data
=
1830 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1832 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1833 /* 2 floats per slot returned */
1834 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1835 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1837 wm_prog_data
->pulls_bary
= true;
1843 * Computes 1 << x, given a D/UD register containing some value x.
1846 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1848 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1850 fs_reg result
= bld
.vgrf(x
.type
, 1);
1851 fs_reg one
= bld
.vgrf(x
.type
, 1);
1853 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1854 bld
.SHL(result
, one
, x
);
1859 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1861 assert(stage
== MESA_SHADER_GEOMETRY
);
1863 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1865 if (gs_compile
->control_data_header_size_bits
== 0)
1868 /* We can only do EndPrimitive() functionality when the control data
1869 * consists of cut bits. Fortunately, the only time it isn't is when the
1870 * output type is points, in which case EndPrimitive() is a no-op.
1872 if (gs_prog_data
->control_data_format
!=
1873 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1877 /* Cut bits use one bit per vertex. */
1878 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1880 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1881 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1883 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1884 * vertex n, 0 otherwise. So all we need to do here is mark bit
1885 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1886 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1887 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1889 * Note that if EndPrimitive() is called before emitting any vertices, this
1890 * will cause us to set bit 31 of the control_data_bits register to 1.
1891 * That's fine because:
1893 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1894 * output, so the hardware will ignore cut bit 31.
1896 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1897 * last vertex, so setting cut bit 31 has no effect (since the primitive
1898 * is automatically ended when the GS terminates).
1900 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1901 * control_data_bits register to 0 when the first vertex is emitted.
1904 const fs_builder abld
= bld
.annotate("end primitive");
1906 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1907 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1908 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1909 fs_reg mask
= intexp2(abld
, prev_count
);
1910 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1911 * attention to the lower 5 bits of its second source argument, so on this
1912 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1913 * ((vertex_count - 1) % 32).
1915 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1919 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1921 assert(stage
== MESA_SHADER_GEOMETRY
);
1922 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1924 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1926 const fs_builder abld
= bld
.annotate("emit control data bits");
1927 const fs_builder fwa_bld
= bld
.exec_all();
1929 /* We use a single UD register to accumulate control data bits (32 bits
1930 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1933 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1934 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1935 * use the Channel Mask phase to enable/disable which DWord within that
1936 * group to write. (Remember, different SIMD8 channels may have emitted
1937 * different numbers of vertices, so we may need per-slot offsets.)
1939 * Channel masking presents an annoying problem: we may have to replicate
1940 * the data up to 4 times:
1942 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1944 * To avoid penalizing shaders that emit a small number of vertices, we
1945 * can avoid these sometimes: if the size of the control data header is
1946 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1947 * land in the same 128-bit group, so we can skip per-slot offsets.
1949 * Similarly, if the control data header is <= 32 bits, there is only one
1950 * DWord, so we can skip channel masks.
1952 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1954 fs_reg channel_mask
, per_slot_offset
;
1956 if (gs_compile
->control_data_header_size_bits
> 32) {
1957 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1958 channel_mask
= vgrf(glsl_type::uint_type
);
1961 if (gs_compile
->control_data_header_size_bits
> 128) {
1962 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1963 per_slot_offset
= vgrf(glsl_type::uint_type
);
1966 /* Figure out which DWord we're trying to write to using the formula:
1968 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1970 * Since bits_per_vertex is a power of two, and is known at compile
1971 * time, this can be optimized to:
1973 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1975 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1976 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1977 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1978 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1979 unsigned log2_bits_per_vertex
=
1980 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1981 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1983 if (per_slot_offset
.file
!= BAD_FILE
) {
1984 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1985 * the appropriate OWord within the control data header.
1987 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1990 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1991 * write to the appropriate DWORD within the OWORD.
1993 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1994 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1995 channel_mask
= intexp2(fwa_bld
, channel
);
1996 /* Then the channel masks need to be in bits 23:16. */
1997 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2000 /* Store the control data bits in the message payload and send it. */
2002 if (channel_mask
.file
!= BAD_FILE
)
2003 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2004 if (per_slot_offset
.file
!= BAD_FILE
)
2007 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2008 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2010 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2011 if (per_slot_offset
.file
!= BAD_FILE
)
2012 sources
[i
++] = per_slot_offset
;
2013 if (channel_mask
.file
!= BAD_FILE
)
2014 sources
[i
++] = channel_mask
;
2016 sources
[i
++] = this->control_data_bits
;
2019 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2020 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2022 /* We need to increment Global Offset by 256-bits to make room for
2023 * Broadwell's extra "Vertex Count" payload at the beginning of the
2024 * URB entry. Since this is an OWord message, Global Offset is counted
2025 * in 128-bit units, so we must set it to 2.
2027 if (gs_prog_data
->static_vertex_count
== -1)
2032 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2035 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2037 /* Note: we are calling this *before* increasing vertex_count, so
2038 * this->vertex_count == vertex_count - 1 in the formula above.
2041 /* Stream mode uses 2 bits per vertex */
2042 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2044 /* Must be a valid stream */
2045 assert(stream_id
< MAX_VERTEX_STREAMS
);
2047 /* Control data bits are initialized to 0 so we don't have to set any
2048 * bits when sending vertices to stream 0.
2053 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2055 /* reg::sid = stream_id */
2056 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2057 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2059 /* reg:shift_count = 2 * (vertex_count - 1) */
2060 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2061 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2063 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2064 * attention to the lower 5 bits of its second source argument, so on this
2065 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2066 * stream_id << ((2 * (vertex_count - 1)) % 32).
2068 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2069 abld
.SHL(mask
, sid
, shift_count
);
2070 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2074 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2077 assert(stage
== MESA_SHADER_GEOMETRY
);
2079 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2081 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2082 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2084 /* Haswell and later hardware ignores the "Render Stream Select" bits
2085 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2086 * and instead sends all primitives down the pipeline for rasterization.
2087 * If the SOL stage is enabled, "Render Stream Select" is honored and
2088 * primitives bound to non-zero streams are discarded after stream output.
2090 * Since the only purpose of primives sent to non-zero streams is to
2091 * be recorded by transform feedback, we can simply discard all geometry
2092 * bound to these streams when transform feedback is disabled.
2094 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2097 /* If we're outputting 32 control data bits or less, then we can wait
2098 * until the shader is over to output them all. Otherwise we need to
2099 * output them as we go. Now is the time to do it, since we're about to
2100 * output the vertex_count'th vertex, so it's guaranteed that the
2101 * control data bits associated with the (vertex_count - 1)th vertex are
2104 if (gs_compile
->control_data_header_size_bits
> 32) {
2105 const fs_builder abld
=
2106 bld
.annotate("emit vertex: emit control data bits");
2108 /* Only emit control data bits if we've finished accumulating a batch
2109 * of 32 bits. This is the case when:
2111 * (vertex_count * bits_per_vertex) % 32 == 0
2113 * (in other words, when the last 5 bits of vertex_count *
2114 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2115 * integer n (which is always the case, since bits_per_vertex is
2116 * always 1 or 2), this is equivalent to requiring that the last 5-n
2117 * bits of vertex_count are 0:
2119 * vertex_count & (2^(5-n) - 1) == 0
2121 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2124 * vertex_count & (32 / bits_per_vertex - 1) == 0
2126 * TODO: If vertex_count is an immediate, we could do some of this math
2127 * at compile time...
2130 abld
.AND(bld
.null_reg_d(), vertex_count
,
2131 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2132 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2134 abld
.IF(BRW_PREDICATE_NORMAL
);
2135 /* If vertex_count is 0, then no control data bits have been
2136 * accumulated yet, so we can skip emitting them.
2138 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2139 BRW_CONDITIONAL_NEQ
);
2140 abld
.IF(BRW_PREDICATE_NORMAL
);
2141 emit_gs_control_data_bits(vertex_count
);
2142 abld
.emit(BRW_OPCODE_ENDIF
);
2144 /* Reset control_data_bits to 0 so we can start accumulating a new
2147 * Note: in the case where vertex_count == 0, this neutralizes the
2148 * effect of any call to EndPrimitive() that the shader may have
2149 * made before outputting its first vertex.
2151 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2152 inst
->force_writemask_all
= true;
2153 abld
.emit(BRW_OPCODE_ENDIF
);
2156 emit_urb_writes(vertex_count
);
2158 /* In stream mode we have to set control data bits for all vertices
2159 * unless we have disabled control data bits completely (which we do
2160 * do for GL_POINTS outputs that don't use streams).
2162 if (gs_compile
->control_data_header_size_bits
> 0 &&
2163 gs_prog_data
->control_data_format
==
2164 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2165 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2170 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2171 const nir_src
&vertex_src
,
2172 unsigned base_offset
,
2173 const nir_src
&offset_src
,
2174 unsigned num_components
,
2175 unsigned first_component
)
2177 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2179 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2180 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2181 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2183 /* TODO: figure out push input layout for invocations == 1 */
2184 /* TODO: make this work with 64-bit inputs */
2185 if (gs_prog_data
->invocations
== 1 &&
2186 type_sz(dst
.type
) <= 4 &&
2187 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2188 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2189 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2190 vertex_const
->u32
[0] * push_reg_count
;
2191 for (unsigned i
= 0; i
< num_components
; i
++) {
2192 bld
.MOV(offset(dst
, bld
, i
),
2193 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2198 /* Resort to the pull model. Ensure the VUE handles are provided. */
2199 assert(gs_prog_data
->base
.include_vue_handles
);
2201 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2202 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2204 if (gs_prog_data
->invocations
== 1) {
2206 /* The vertex index is constant; just select the proper URB handle. */
2208 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2209 BRW_REGISTER_TYPE_UD
);
2211 /* The vertex index is non-constant. We need to use indirect
2212 * addressing to fetch the proper URB handle.
2214 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2215 * indicating that channel <n> should read the handle from
2216 * DWord <n>. We convert that to bytes by multiplying by 4.
2218 * Next, we convert the vertex index to bytes by multiplying
2219 * by 32 (shifting by 5), and add the two together. This is
2220 * the final indirect byte offset.
2222 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2223 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2224 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2225 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2227 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2228 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2229 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2230 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2231 /* Convert vertex_index to bytes (multiply by 32) */
2232 bld
.SHL(vertex_offset_bytes
,
2233 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2235 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2237 /* Use first_icp_handle as the base offset. There is one register
2238 * of URB handles per vertex, so inform the register allocator that
2239 * we might read up to nir->info.gs.vertices_in registers.
2241 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2242 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2243 fs_reg(icp_offset_bytes
),
2244 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2247 assert(gs_prog_data
->invocations
> 1);
2250 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2252 retype(brw_vec1_grf(first_icp_handle
+
2253 vertex_const
->i32
[0] / 8,
2254 vertex_const
->i32
[0] % 8),
2255 BRW_REGISTER_TYPE_UD
));
2257 /* The vertex index is non-constant. We need to use indirect
2258 * addressing to fetch the proper URB handle.
2261 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2263 /* Convert vertex_index to bytes (multiply by 4) */
2264 bld
.SHL(icp_offset_bytes
,
2265 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2268 /* Use first_icp_handle as the base offset. There is one DWord
2269 * of URB handles per vertex, so inform the register allocator that
2270 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2272 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2273 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2274 fs_reg(icp_offset_bytes
),
2275 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2282 fs_reg tmp_dst
= dst
;
2283 fs_reg indirect_offset
= get_nir_src(offset_src
);
2284 unsigned num_iterations
= 1;
2285 unsigned orig_num_components
= num_components
;
2287 if (type_sz(dst
.type
) == 8) {
2288 if (num_components
> 2) {
2292 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2294 first_component
= first_component
/ 2;
2297 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2299 /* Constant indexing - use global offset. */
2300 if (first_component
!= 0) {
2301 unsigned read_components
= num_components
+ first_component
;
2302 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2303 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2304 inst
->size_written
= read_components
*
2305 tmp
.component_size(inst
->exec_size
);
2306 for (unsigned i
= 0; i
< num_components
; i
++) {
2307 bld
.MOV(offset(tmp_dst
, bld
, i
),
2308 offset(tmp
, bld
, i
+ first_component
));
2311 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2313 inst
->size_written
= num_components
*
2314 tmp_dst
.component_size(inst
->exec_size
);
2316 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2319 /* Indirect indexing - use per-slot offsets as well. */
2320 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2321 unsigned read_components
= num_components
+ first_component
;
2322 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2323 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2324 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2325 if (first_component
!= 0) {
2326 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2328 inst
->size_written
= read_components
*
2329 tmp
.component_size(inst
->exec_size
);
2330 for (unsigned i
= 0; i
< num_components
; i
++) {
2331 bld
.MOV(offset(tmp_dst
, bld
, i
),
2332 offset(tmp
, bld
, i
+ first_component
));
2335 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2337 inst
->size_written
= num_components
*
2338 tmp_dst
.component_size(inst
->exec_size
);
2340 inst
->offset
= base_offset
;
2344 if (type_sz(dst
.type
) == 8) {
2345 shuffle_from_32bit_read(bld
,
2346 offset(dst
, bld
, iter
* 2),
2347 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2352 if (num_iterations
> 1) {
2353 num_components
= orig_num_components
- 2;
2357 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2358 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2359 indirect_offset
= new_indirect
;
2366 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2368 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2369 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2372 /* The only constant offset we should find is 0. brw_nir.c's
2373 * add_const_offset_to_base() will fold other constant offsets
2374 * into instr->const_index[0].
2376 assert(const_value
->u32
[0] == 0);
2380 return get_nir_src(*offset_src
);
2384 do_untyped_vector_read(const fs_builder
&bld
,
2386 const fs_reg surf_index
,
2387 const fs_reg offset_reg
,
2388 unsigned num_components
)
2390 if (type_sz(dest
.type
) <= 2) {
2391 assert(dest
.stride
== 1);
2392 boolean is_const_offset
= offset_reg
.file
== BRW_IMMEDIATE_VALUE
;
2394 if (is_const_offset
) {
2395 uint32_t start
= offset_reg
.ud
& ~3;
2396 uint32_t end
= offset_reg
.ud
+ num_components
* type_sz(dest
.type
);
2397 end
= ALIGN(end
, 4);
2398 assert (end
- start
<= 16);
2400 /* At this point we have 16-bit component/s that have constant
2401 * offset aligned to 4-bytes that can be read with untyped_reads.
2402 * untyped_read message requires 32-bit aligned offsets.
2404 unsigned first_component
= (offset_reg
.ud
& 3) / type_sz(dest
.type
);
2405 unsigned num_components_32bit
= (end
- start
) / 4;
2407 fs_reg read_result
=
2408 emit_untyped_read(bld
, surf_index
, brw_imm_ud(start
),
2410 num_components_32bit
,
2411 BRW_PREDICATE_NONE
);
2412 shuffle_from_32bit_read(bld
, dest
, read_result
, first_component
,
2415 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2416 for (unsigned i
= 0; i
< num_components
; i
++) {
2418 bld
.MOV(read_offset
, offset_reg
);
2420 bld
.ADD(read_offset
, offset_reg
,
2421 brw_imm_ud(i
* type_sz(dest
.type
)));
2423 /* Non constant offsets are not guaranteed to be aligned 32-bits
2424 * so they are read using one byte_scattered_read message
2425 * for each component.
2427 fs_reg read_result
=
2428 emit_byte_scattered_read(bld
, surf_index
, read_offset
,
2430 type_sz(dest
.type
) * 8 /* bit_size */,
2431 BRW_PREDICATE_NONE
);
2432 bld
.MOV(offset(dest
, bld
, i
),
2433 subscript (read_result
, dest
.type
, 0));
2436 } else if (type_sz(dest
.type
) == 4) {
2437 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2440 BRW_PREDICATE_NONE
);
2441 read_result
.type
= dest
.type
;
2442 for (unsigned i
= 0; i
< num_components
; i
++)
2443 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2444 } else if (type_sz(dest
.type
) == 8) {
2445 /* Reading a dvec, so we need to:
2447 * 1. Multiply num_components by 2, to account for the fact that we
2448 * need to read 64-bit components.
2449 * 2. Shuffle the result of the load to form valid 64-bit elements
2450 * 3. Emit a second load (for components z/w) if needed.
2452 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2453 bld
.MOV(read_offset
, offset_reg
);
2455 int iters
= num_components
<= 2 ? 1 : 2;
2457 /* Load the dvec, the first iteration loads components x/y, the second
2458 * iteration, if needed, loads components z/w
2460 for (int it
= 0; it
< iters
; it
++) {
2461 /* Compute number of components to read in this iteration */
2462 int iter_components
= MIN2(2, num_components
);
2463 num_components
-= iter_components
;
2465 /* Read. Since this message reads 32-bit components, we need to
2466 * read twice as many components.
2468 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2470 iter_components
* 2,
2471 BRW_PREDICATE_NONE
);
2473 /* Shuffle the 32-bit load result into valid 64-bit data */
2474 shuffle_from_32bit_read(bld
, offset(dest
, bld
, it
* 2),
2475 read_result
, 0, iter_components
);
2477 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2480 unreachable("Unsupported type");
2485 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2486 nir_intrinsic_instr
*instr
)
2488 assert(stage
== MESA_SHADER_VERTEX
);
2491 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2492 dest
= get_nir_dest(instr
->dest
);
2494 switch (instr
->intrinsic
) {
2495 case nir_intrinsic_load_vertex_id
:
2496 case nir_intrinsic_load_base_vertex
:
2497 unreachable("should be lowered by nir_lower_system_values()");
2499 case nir_intrinsic_load_vertex_id_zero_base
:
2500 case nir_intrinsic_load_instance_id
:
2501 case nir_intrinsic_load_base_instance
:
2502 case nir_intrinsic_load_draw_id
: {
2503 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2504 fs_reg val
= nir_system_values
[sv
];
2505 assert(val
.file
!= BAD_FILE
);
2506 dest
.type
= val
.type
;
2511 case nir_intrinsic_load_input
: {
2512 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2513 unsigned first_component
= nir_intrinsic_component(instr
);
2514 unsigned num_components
= instr
->num_components
;
2516 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2517 assert(const_offset
&& "Indirect input loads not allowed");
2518 src
= offset(src
, bld
, const_offset
->u32
[0]);
2520 if (type_sz(dest
.type
) == 8)
2521 first_component
/= 2;
2523 /* For 16-bit support maybe a temporary will be needed to copy from
2526 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2527 first_component
, num_components
);
2531 case nir_intrinsic_load_first_vertex
:
2532 case nir_intrinsic_load_is_indexed_draw
:
2533 unreachable("lowered by brw_nir_lower_vs_inputs");
2536 nir_emit_intrinsic(bld
, instr
);
2542 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2543 nir_intrinsic_instr
*instr
)
2545 assert(stage
== MESA_SHADER_TESS_CTRL
);
2546 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2547 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2550 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2551 dst
= get_nir_dest(instr
->dest
);
2553 switch (instr
->intrinsic
) {
2554 case nir_intrinsic_load_primitive_id
:
2555 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2557 case nir_intrinsic_load_invocation_id
:
2558 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2560 case nir_intrinsic_load_patch_vertices_in
:
2561 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2562 brw_imm_d(tcs_key
->input_vertices
));
2565 case nir_intrinsic_barrier
: {
2566 if (tcs_prog_data
->instances
== 1)
2569 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2570 fs_reg m0_2
= component(m0
, 2);
2572 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2574 /* Zero the message header */
2575 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2577 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2578 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2579 brw_imm_ud(INTEL_MASK(16, 13)));
2581 /* Shift it up to bits 27:24. */
2582 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2584 /* Set the Barrier Count and the enable bit */
2585 chanbld
.OR(m0_2
, m0_2
,
2586 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2588 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2592 case nir_intrinsic_load_input
:
2593 unreachable("nir_lower_io should never give us these.");
2596 case nir_intrinsic_load_per_vertex_input
: {
2597 fs_reg indirect_offset
= get_indirect_offset(instr
);
2598 unsigned imm_offset
= instr
->const_index
[0];
2600 const nir_src
&vertex_src
= instr
->src
[0];
2601 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2608 /* Emit a MOV to resolve <0,1,0> regioning. */
2609 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2611 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2612 vertex_const
->i32
[0] & 7),
2613 BRW_REGISTER_TYPE_UD
));
2614 } else if (tcs_prog_data
->instances
== 1 &&
2615 vertex_src
.is_ssa
&&
2616 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2617 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2618 /* For the common case of only 1 instance, an array index of
2619 * gl_InvocationID means reading g1. Skip all the indirect work.
2621 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2623 /* The vertex index is non-constant. We need to use indirect
2624 * addressing to fetch the proper URB handle.
2626 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2628 /* Each ICP handle is a single DWord (4 bytes) */
2629 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2630 bld
.SHL(vertex_offset_bytes
,
2631 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2634 /* Start at g1. We might read up to 4 registers. */
2635 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2636 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2637 brw_imm_ud(4 * REG_SIZE
));
2640 /* We can only read two double components with each URB read, so
2641 * we send two read messages in that case, each one loading up to
2642 * two double components.
2644 unsigned num_iterations
= 1;
2645 unsigned num_components
= instr
->num_components
;
2646 unsigned first_component
= nir_intrinsic_component(instr
);
2647 fs_reg orig_dst
= dst
;
2648 if (type_sz(dst
.type
) == 8) {
2649 first_component
= first_component
/ 2;
2650 if (instr
->num_components
> 2) {
2655 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2659 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2660 if (indirect_offset
.file
== BAD_FILE
) {
2661 /* Constant indexing - use global offset. */
2662 if (first_component
!= 0) {
2663 unsigned read_components
= num_components
+ first_component
;
2664 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2665 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2666 for (unsigned i
= 0; i
< num_components
; i
++) {
2667 bld
.MOV(offset(dst
, bld
, i
),
2668 offset(tmp
, bld
, i
+ first_component
));
2671 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2673 inst
->offset
= imm_offset
;
2676 /* Indirect indexing - use per-slot offsets as well. */
2677 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2678 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2679 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2680 if (first_component
!= 0) {
2681 unsigned read_components
= num_components
+ first_component
;
2682 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2683 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2685 for (unsigned i
= 0; i
< num_components
; i
++) {
2686 bld
.MOV(offset(dst
, bld
, i
),
2687 offset(tmp
, bld
, i
+ first_component
));
2690 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2693 inst
->offset
= imm_offset
;
2696 inst
->size_written
= (num_components
+ first_component
) *
2697 inst
->dst
.component_size(inst
->exec_size
);
2699 /* If we are reading 64-bit data using 32-bit read messages we need
2700 * build proper 64-bit data elements by shuffling the low and high
2701 * 32-bit components around like we do for other things like UBOs
2704 if (type_sz(dst
.type
) == 8) {
2705 shuffle_from_32bit_read(bld
,
2706 offset(orig_dst
, bld
, iter
* 2),
2707 retype(dst
, BRW_REGISTER_TYPE_D
),
2711 /* Copy the temporary to the destination to deal with writemasking.
2713 * Also attempt to deal with gl_PointSize being in the .w component.
2715 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2716 assert(type_sz(dst
.type
) < 8);
2717 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2718 inst
->size_written
= 4 * REG_SIZE
;
2719 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2722 /* If we are loading double data and we need a second read message
2723 * adjust the write offset
2725 if (num_iterations
> 1) {
2726 num_components
= instr
->num_components
- 2;
2733 case nir_intrinsic_load_output
:
2734 case nir_intrinsic_load_per_vertex_output
: {
2735 fs_reg indirect_offset
= get_indirect_offset(instr
);
2736 unsigned imm_offset
= instr
->const_index
[0];
2737 unsigned first_component
= nir_intrinsic_component(instr
);
2740 if (indirect_offset
.file
== BAD_FILE
) {
2741 /* Replicate the patch handle to all enabled channels */
2742 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2743 bld
.MOV(patch_handle
,
2744 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2747 if (first_component
!= 0) {
2748 unsigned read_components
=
2749 instr
->num_components
+ first_component
;
2750 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2751 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2753 inst
->size_written
= read_components
* REG_SIZE
;
2754 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2755 bld
.MOV(offset(dst
, bld
, i
),
2756 offset(tmp
, bld
, i
+ first_component
));
2759 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2761 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2763 inst
->offset
= imm_offset
;
2767 /* Indirect indexing - use per-slot offsets as well. */
2768 const fs_reg srcs
[] = {
2769 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2772 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2773 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2774 if (first_component
!= 0) {
2775 unsigned read_components
=
2776 instr
->num_components
+ first_component
;
2777 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2778 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2780 inst
->size_written
= read_components
* REG_SIZE
;
2781 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2782 bld
.MOV(offset(dst
, bld
, i
),
2783 offset(tmp
, bld
, i
+ first_component
));
2786 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2788 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2790 inst
->offset
= imm_offset
;
2796 case nir_intrinsic_store_output
:
2797 case nir_intrinsic_store_per_vertex_output
: {
2798 fs_reg value
= get_nir_src(instr
->src
[0]);
2799 bool is_64bit
= (instr
->src
[0].is_ssa
?
2800 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2801 fs_reg indirect_offset
= get_indirect_offset(instr
);
2802 unsigned imm_offset
= instr
->const_index
[0];
2803 unsigned mask
= instr
->const_index
[1];
2804 unsigned header_regs
= 0;
2806 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2808 if (indirect_offset
.file
!= BAD_FILE
) {
2809 srcs
[header_regs
++] = indirect_offset
;
2815 unsigned num_components
= util_last_bit(mask
);
2818 /* We can only pack two 64-bit components in a single message, so send
2819 * 2 messages if we have more components
2821 unsigned num_iterations
= 1;
2822 unsigned iter_components
= num_components
;
2823 unsigned first_component
= nir_intrinsic_component(instr
);
2825 first_component
= first_component
/ 2;
2826 if (instr
->num_components
> 2) {
2828 iter_components
= 2;
2832 mask
= mask
<< first_component
;
2834 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2835 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2836 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2837 opcode
= indirect_offset
.file
!= BAD_FILE
?
2838 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2839 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2840 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2841 /* Expand the 64-bit mask to 32-bit channels. We only handle
2842 * two channels in each iteration, so we only care about X/Y.
2844 unsigned mask32
= 0;
2845 if (mask
& WRITEMASK_X
)
2846 mask32
|= WRITEMASK_XY
;
2847 if (mask
& WRITEMASK_Y
)
2848 mask32
|= WRITEMASK_ZW
;
2850 /* If the mask does not include any of the channels X or Y there
2851 * is nothing to do in this iteration. Move on to the next couple
2852 * of 64-bit channels.
2860 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2861 opcode
= indirect_offset
.file
!= BAD_FILE
?
2862 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2863 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2865 opcode
= indirect_offset
.file
!= BAD_FILE
?
2866 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2867 SHADER_OPCODE_URB_WRITE_SIMD8
;
2870 for (unsigned i
= 0; i
< iter_components
; i
++) {
2871 if (!(mask
& (1 << (i
+ first_component
))))
2875 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2877 /* We need to shuffle the 64-bit data to match the layout
2878 * expected by our 32-bit URB write messages. We use a temporary
2881 unsigned channel
= iter
* 2 + i
;
2882 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2884 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2885 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2886 offset(dest
, bld
, 1);
2891 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2892 (is_64bit
? 2 * first_component
: first_component
);
2894 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2895 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2897 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2898 inst
->offset
= imm_offset
;
2901 /* If this is a 64-bit attribute, select the next two 64-bit channels
2902 * to be handled in the next iteration.
2913 nir_emit_intrinsic(bld
, instr
);
2919 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2920 nir_intrinsic_instr
*instr
)
2922 assert(stage
== MESA_SHADER_TESS_EVAL
);
2923 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2926 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2927 dest
= get_nir_dest(instr
->dest
);
2929 switch (instr
->intrinsic
) {
2930 case nir_intrinsic_load_primitive_id
:
2931 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2933 case nir_intrinsic_load_tess_coord
:
2934 /* gl_TessCoord is part of the payload in g1-3 */
2935 for (unsigned i
= 0; i
< 3; i
++) {
2936 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2940 case nir_intrinsic_load_input
:
2941 case nir_intrinsic_load_per_vertex_input
: {
2942 fs_reg indirect_offset
= get_indirect_offset(instr
);
2943 unsigned imm_offset
= instr
->const_index
[0];
2944 unsigned first_component
= nir_intrinsic_component(instr
);
2946 if (type_sz(dest
.type
) == 8) {
2947 first_component
= first_component
/ 2;
2951 if (indirect_offset
.file
== BAD_FILE
) {
2952 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2953 * which is 16 registers (since each holds 2 vec4 slots).
2955 unsigned slot_count
= 1;
2956 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2959 const unsigned max_push_slots
= 32;
2960 if (imm_offset
+ slot_count
<= max_push_slots
) {
2961 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2962 for (int i
= 0; i
< instr
->num_components
; i
++) {
2963 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2964 i
+ first_component
;
2965 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2968 tes_prog_data
->base
.urb_read_length
=
2969 MAX2(tes_prog_data
->base
.urb_read_length
,
2970 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2972 /* Replicate the patch handle to all enabled channels */
2973 const fs_reg srcs
[] = {
2974 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2976 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2977 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2979 if (first_component
!= 0) {
2980 unsigned read_components
=
2981 instr
->num_components
+ first_component
;
2982 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2983 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2985 inst
->size_written
= read_components
* REG_SIZE
;
2986 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2987 bld
.MOV(offset(dest
, bld
, i
),
2988 offset(tmp
, bld
, i
+ first_component
));
2991 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2993 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2996 inst
->offset
= imm_offset
;
2999 /* Indirect indexing - use per-slot offsets as well. */
3001 /* We can only read two double components with each URB read, so
3002 * we send two read messages in that case, each one loading up to
3003 * two double components.
3005 unsigned num_iterations
= 1;
3006 unsigned num_components
= instr
->num_components
;
3007 fs_reg orig_dest
= dest
;
3008 if (type_sz(dest
.type
) == 8) {
3009 if (instr
->num_components
> 2) {
3013 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3017 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3018 const fs_reg srcs
[] = {
3019 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3022 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3023 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3025 if (first_component
!= 0) {
3026 unsigned read_components
=
3027 num_components
+ first_component
;
3028 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3029 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3031 for (unsigned i
= 0; i
< num_components
; i
++) {
3032 bld
.MOV(offset(dest
, bld
, i
),
3033 offset(tmp
, bld
, i
+ first_component
));
3036 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3040 inst
->offset
= imm_offset
;
3041 inst
->size_written
= (num_components
+ first_component
) *
3042 inst
->dst
.component_size(inst
->exec_size
);
3044 /* If we are reading 64-bit data using 32-bit read messages we need
3045 * build proper 64-bit data elements by shuffling the low and high
3046 * 32-bit components around like we do for other things like UBOs
3049 if (type_sz(dest
.type
) == 8) {
3050 shuffle_from_32bit_read(bld
,
3051 offset(orig_dest
, bld
, iter
* 2),
3052 retype(dest
, BRW_REGISTER_TYPE_D
),
3056 /* If we are loading double data and we need a second read message
3059 if (num_iterations
> 1) {
3060 num_components
= instr
->num_components
- 2;
3068 nir_emit_intrinsic(bld
, instr
);
3074 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3075 nir_intrinsic_instr
*instr
)
3077 assert(stage
== MESA_SHADER_GEOMETRY
);
3078 fs_reg indirect_offset
;
3081 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3082 dest
= get_nir_dest(instr
->dest
);
3084 switch (instr
->intrinsic
) {
3085 case nir_intrinsic_load_primitive_id
:
3086 assert(stage
== MESA_SHADER_GEOMETRY
);
3087 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3088 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3089 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3092 case nir_intrinsic_load_input
:
3093 unreachable("load_input intrinsics are invalid for the GS stage");
3095 case nir_intrinsic_load_per_vertex_input
:
3096 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3097 instr
->src
[1], instr
->num_components
,
3098 nir_intrinsic_component(instr
));
3101 case nir_intrinsic_emit_vertex_with_counter
:
3102 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3105 case nir_intrinsic_end_primitive_with_counter
:
3106 emit_gs_end_primitive(instr
->src
[0]);
3109 case nir_intrinsic_set_vertex_count
:
3110 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3113 case nir_intrinsic_load_invocation_id
: {
3114 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3115 assert(val
.file
!= BAD_FILE
);
3116 dest
.type
= val
.type
;
3122 nir_emit_intrinsic(bld
, instr
);
3128 * Fetch the current render target layer index.
3131 fetch_render_target_array_index(const fs_builder
&bld
)
3133 if (bld
.shader
->devinfo
->gen
>= 6) {
3134 /* The render target array index is provided in the thread payload as
3135 * bits 26:16 of r0.0.
3137 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3138 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3142 /* Pre-SNB we only ever render into the first layer of the framebuffer
3143 * since layered rendering is not implemented.
3145 return brw_imm_ud(0);
3150 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3151 * framebuffer at the current fragment coordinates and sample index.
3154 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3157 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3159 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3160 const brw_wm_prog_key
*wm_key
=
3161 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3162 assert(!wm_key
->coherent_fb_fetch
);
3163 const struct brw_wm_prog_data
*wm_prog_data
=
3164 brw_wm_prog_data(stage_prog_data
);
3166 /* Calculate the surface index relative to the start of the texture binding
3167 * table block, since that's what the texturing messages expect.
3169 const unsigned surface
= target
+
3170 wm_prog_data
->binding_table
.render_target_read_start
-
3171 wm_prog_data
->base
.binding_table
.texture_start
;
3173 brw_mark_surface_used(
3174 bld
.shader
->stage_prog_data
,
3175 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3177 /* Calculate the fragment coordinates. */
3178 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3179 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3180 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3181 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3183 /* Calculate the sample index and MCS payload when multisampling. Luckily
3184 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3185 * shouldn't be necessary to recompile based on whether the framebuffer is
3188 if (wm_key
->multisample_fbo
&&
3189 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3190 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3192 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3193 const fs_reg mcs
= wm_key
->multisample_fbo
?
3194 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3196 /* Use either a normal or a CMS texel fetch message depending on whether
3197 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3198 * message just in case the framebuffer uses 16x multisampling, it should
3199 * be equivalent to the normal CMS fetch for lower multisampling modes.
3201 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3202 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3203 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3205 /* Emit the instruction. */
3206 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3208 brw_imm_ud(surface
), brw_imm_ud(0),
3209 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3210 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3212 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3213 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3219 * Actual coherent framebuffer read implemented using the native render target
3220 * read message. Requires SKL+.
3223 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3225 assert(bld
.shader
->devinfo
->gen
>= 9);
3226 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3227 inst
->target
= target
;
3228 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3234 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3236 if (n
&& regs
[0].file
!= BAD_FILE
) {
3240 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3242 for (unsigned i
= 0; i
< n
; i
++)
3250 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3252 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3253 const brw_wm_prog_key
*const key
=
3254 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3255 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3256 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3258 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3259 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3261 else if (l
== FRAG_RESULT_COLOR
)
3262 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3263 MAX2(key
->nr_color_regions
, 1));
3265 else if (l
== FRAG_RESULT_DEPTH
)
3266 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3268 else if (l
== FRAG_RESULT_STENCIL
)
3269 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3271 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3272 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3274 else if (l
>= FRAG_RESULT_DATA0
&&
3275 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3276 return alloc_temporary(v
->bld
, 4,
3277 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3280 unreachable("Invalid location");
3284 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3285 nir_intrinsic_instr
*instr
)
3287 assert(stage
== MESA_SHADER_FRAGMENT
);
3290 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3291 dest
= get_nir_dest(instr
->dest
);
3293 switch (instr
->intrinsic
) {
3294 case nir_intrinsic_load_front_face
:
3295 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3296 *emit_frontfacing_interpolation());
3299 case nir_intrinsic_load_sample_pos
: {
3300 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3301 assert(sample_pos
.file
!= BAD_FILE
);
3302 dest
.type
= sample_pos
.type
;
3303 bld
.MOV(dest
, sample_pos
);
3304 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3308 case nir_intrinsic_load_layer_id
:
3309 dest
.type
= BRW_REGISTER_TYPE_UD
;
3310 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3313 case nir_intrinsic_load_helper_invocation
:
3314 case nir_intrinsic_load_sample_mask_in
:
3315 case nir_intrinsic_load_sample_id
: {
3316 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3317 fs_reg val
= nir_system_values
[sv
];
3318 assert(val
.file
!= BAD_FILE
);
3319 dest
.type
= val
.type
;
3324 case nir_intrinsic_store_output
: {
3325 const fs_reg src
= get_nir_src(instr
->src
[0]);
3326 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3327 assert(const_offset
&& "Indirect output stores not allowed");
3328 const unsigned location
= nir_intrinsic_base(instr
) +
3329 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3330 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3333 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3334 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3335 offset(src
, bld
, j
));
3340 case nir_intrinsic_load_output
: {
3341 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3342 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3343 assert(l
>= FRAG_RESULT_DATA0
);
3344 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3345 assert(const_offset
&& "Indirect output loads not allowed");
3346 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3347 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3349 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3350 emit_coherent_fb_read(bld
, tmp
, target
);
3352 emit_non_coherent_fb_read(bld
, tmp
, target
);
3354 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3355 bld
.MOV(offset(dest
, bld
, j
),
3356 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3362 case nir_intrinsic_discard
:
3363 case nir_intrinsic_discard_if
: {
3364 /* We track our discarded pixels in f0.1. By predicating on it, we can
3365 * update just the flag bits that aren't yet discarded. If there's no
3366 * condition, we emit a CMP of g0 != g0, so all currently executing
3367 * channels will get turned off.
3370 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3371 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3372 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3374 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3375 BRW_REGISTER_TYPE_UW
));
3376 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3378 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3379 cmp
->flag_subreg
= 1;
3381 if (devinfo
->gen
>= 6) {
3382 emit_discard_jump();
3385 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3389 case nir_intrinsic_load_input
: {
3390 /* load_input is only used for flat inputs */
3391 unsigned base
= nir_intrinsic_base(instr
);
3392 unsigned comp
= nir_intrinsic_component(instr
);
3393 unsigned num_components
= instr
->num_components
;
3394 fs_reg orig_dest
= dest
;
3395 enum brw_reg_type type
= dest
.type
;
3397 /* Special case fields in the VUE header */
3398 if (base
== VARYING_SLOT_LAYER
)
3400 else if (base
== VARYING_SLOT_VIEWPORT
)
3403 if (nir_dest_bit_size(instr
->dest
) == 64) {
3404 /* const_index is in 32-bit type size units that could not be aligned
3405 * with DF. We need to read the double vector as if it was a float
3406 * vector of twice the number of components to fetch the right data.
3408 type
= BRW_REGISTER_TYPE_F
;
3409 num_components
*= 2;
3410 dest
= bld
.vgrf(type
, num_components
);
3413 for (unsigned int i
= 0; i
< num_components
; i
++) {
3414 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3415 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3418 if (nir_dest_bit_size(instr
->dest
) == 64) {
3419 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3420 instr
->num_components
);
3425 case nir_intrinsic_load_barycentric_pixel
:
3426 case nir_intrinsic_load_barycentric_centroid
:
3427 case nir_intrinsic_load_barycentric_sample
:
3428 /* Do nothing - load_interpolated_input handling will handle it later. */
3431 case nir_intrinsic_load_barycentric_at_sample
: {
3432 const glsl_interp_mode interpolation
=
3433 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3435 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3438 unsigned msg_data
= const_sample
->i32
[0] << 4;
3440 emit_pixel_interpolater_send(bld
,
3441 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3444 brw_imm_ud(msg_data
),
3447 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3448 BRW_REGISTER_TYPE_UD
);
3450 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3451 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3452 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3453 bld
.exec_all().group(1, 0)
3454 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3455 emit_pixel_interpolater_send(bld
,
3456 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3462 /* Make a loop that sends a message to the pixel interpolater
3463 * for the sample number in each live channel. If there are
3464 * multiple channels with the same sample number then these
3465 * will be handled simultaneously with a single interation of
3468 bld
.emit(BRW_OPCODE_DO
);
3470 /* Get the next live sample number into sample_id_reg */
3471 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3473 /* Set the flag register so that we can perform the send
3474 * message on all channels that have the same sample number
3476 bld
.CMP(bld
.null_reg_ud(),
3477 sample_src
, sample_id
,
3478 BRW_CONDITIONAL_EQ
);
3479 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3480 bld
.exec_all().group(1, 0)
3481 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3483 emit_pixel_interpolater_send(bld
,
3484 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3487 component(msg_data
, 0),
3489 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3491 /* Continue the loop if there are any live channels left */
3492 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3494 bld
.emit(BRW_OPCODE_WHILE
));
3500 case nir_intrinsic_load_barycentric_at_offset
: {
3501 const glsl_interp_mode interpolation
=
3502 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3504 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3507 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3508 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3510 emit_pixel_interpolater_send(bld
,
3511 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3514 brw_imm_ud(off_x
| (off_y
<< 4)),
3517 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3518 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3519 BRW_REGISTER_TYPE_F
);
3520 for (int i
= 0; i
< 2; i
++) {
3521 fs_reg temp
= vgrf(glsl_type::float_type
);
3522 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3523 fs_reg itemp
= vgrf(glsl_type::int_type
);
3525 bld
.MOV(itemp
, temp
);
3527 /* Clamp the upper end of the range to +7/16.
3528 * ARB_gpu_shader5 requires that we support a maximum offset
3529 * of +0.5, which isn't representable in a S0.4 value -- if
3530 * we didn't clamp it, we'd end up with -8/16, which is the
3531 * opposite of what the shader author wanted.
3533 * This is legal due to ARB_gpu_shader5's quantization
3536 * "Not all values of <offset> may be supported; x and y
3537 * offsets may be rounded to fixed-point values with the
3538 * number of fraction bits given by the
3539 * implementation-dependent constant
3540 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3542 set_condmod(BRW_CONDITIONAL_L
,
3543 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3546 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3547 emit_pixel_interpolater_send(bld
,
3557 case nir_intrinsic_load_interpolated_input
: {
3558 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3559 emit_fragcoord_interpolation(dest
);
3563 assert(instr
->src
[0].ssa
&&
3564 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3565 nir_intrinsic_instr
*bary_intrinsic
=
3566 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3567 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3568 enum glsl_interp_mode interp_mode
=
3569 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3572 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3573 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3574 /* Use the result of the PI message */
3575 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3577 /* Use the delta_xy values computed from the payload */
3578 enum brw_barycentric_mode bary
=
3579 brw_barycentric_mode(interp_mode
, bary_intrin
);
3581 dst_xy
= this->delta_xy
[bary
];
3584 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3586 component(interp_reg(nir_intrinsic_base(instr
),
3587 nir_intrinsic_component(instr
) + i
), 0);
3588 interp
.type
= BRW_REGISTER_TYPE_F
;
3589 dest
.type
= BRW_REGISTER_TYPE_F
;
3591 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3592 fs_reg tmp
= vgrf(glsl_type::float_type
);
3593 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3594 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3596 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3603 nir_emit_intrinsic(bld
, instr
);
3609 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3610 nir_intrinsic_instr
*instr
)
3612 assert(stage
== MESA_SHADER_COMPUTE
);
3613 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3616 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3617 dest
= get_nir_dest(instr
->dest
);
3619 switch (instr
->intrinsic
) {
3620 case nir_intrinsic_barrier
:
3622 cs_prog_data
->uses_barrier
= true;
3625 case nir_intrinsic_load_subgroup_id
:
3626 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3629 case nir_intrinsic_load_local_invocation_id
:
3630 case nir_intrinsic_load_work_group_id
: {
3631 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3632 fs_reg val
= nir_system_values
[sv
];
3633 assert(val
.file
!= BAD_FILE
);
3634 dest
.type
= val
.type
;
3635 for (unsigned i
= 0; i
< 3; i
++)
3636 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3640 case nir_intrinsic_load_num_work_groups
: {
3641 const unsigned surface
=
3642 cs_prog_data
->binding_table
.work_groups_start
;
3644 cs_prog_data
->uses_num_work_groups
= true;
3646 fs_reg surf_index
= brw_imm_ud(surface
);
3647 brw_mark_surface_used(prog_data
, surface
);
3649 /* Read the 3 GLuint components of gl_NumWorkGroups */
3650 for (unsigned i
= 0; i
< 3; i
++) {
3651 fs_reg read_result
=
3652 emit_untyped_read(bld
, surf_index
,
3654 1 /* dims */, 1 /* size */,
3655 BRW_PREDICATE_NONE
);
3656 read_result
.type
= dest
.type
;
3657 bld
.MOV(dest
, read_result
);
3658 dest
= offset(dest
, bld
, 1);
3663 case nir_intrinsic_shared_atomic_add
:
3664 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3666 case nir_intrinsic_shared_atomic_imin
:
3667 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3669 case nir_intrinsic_shared_atomic_umin
:
3670 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3672 case nir_intrinsic_shared_atomic_imax
:
3673 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3675 case nir_intrinsic_shared_atomic_umax
:
3676 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3678 case nir_intrinsic_shared_atomic_and
:
3679 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3681 case nir_intrinsic_shared_atomic_or
:
3682 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3684 case nir_intrinsic_shared_atomic_xor
:
3685 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3687 case nir_intrinsic_shared_atomic_exchange
:
3688 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3690 case nir_intrinsic_shared_atomic_comp_swap
:
3691 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3694 case nir_intrinsic_load_shared
: {
3695 assert(devinfo
->gen
>= 7);
3697 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3699 /* Get the offset to read from */
3701 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3703 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3705 offset_reg
= vgrf(glsl_type::uint_type
);
3707 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3708 brw_imm_ud(instr
->const_index
[0]));
3711 /* Read the vector */
3712 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3713 instr
->num_components
);
3717 case nir_intrinsic_store_shared
: {
3718 assert(devinfo
->gen
>= 7);
3721 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3724 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3727 unsigned writemask
= instr
->const_index
[1];
3729 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3730 * since the untyped writes below operate in units of 32-bits, which
3731 * means that we need to write twice as many components each time.
3732 * Also, we have to suffle 64-bit data to be in the appropriate layout
3733 * expected by our 32-bit write messages.
3735 unsigned type_size
= 4;
3736 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3738 val_reg
= shuffle_for_32bit_write(bld
, val_reg
, 0,
3739 instr
->num_components
);
3742 unsigned type_slots
= type_size
/ 4;
3744 /* Combine groups of consecutive enabled channels in one write
3745 * message. We use ffs to find the first enabled channel and then ffs on
3746 * the bit-inverse, down-shifted writemask to determine the length of
3747 * the block of enabled bits.
3750 unsigned first_component
= ffs(writemask
) - 1;
3751 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3753 /* We can't write more than 2 64-bit components at once. Limit the
3754 * length of the write to what we can do and let the next iteration
3758 length
= MIN2(2, length
);
3761 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3763 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3764 type_size
* first_component
);
3766 offset_reg
= vgrf(glsl_type::uint_type
);
3768 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3769 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3772 emit_untyped_write(bld
, surf_index
, offset_reg
,
3773 offset(val_reg
, bld
, first_component
* type_slots
),
3774 1 /* dims */, length
* type_slots
,
3775 BRW_PREDICATE_NONE
);
3777 /* Clear the bits in the writemask that we just wrote, then try
3778 * again to see if more channels are left.
3780 writemask
&= (15 << (first_component
+ length
));
3787 nir_emit_intrinsic(bld
, instr
);
3793 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3794 nir_op op
, brw_reg_type type
)
3796 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3797 switch (type_sz(type
)) {
3799 assert(type
!= BRW_REGISTER_TYPE_HF
);
3800 return retype(brw_imm_uw(value
.u16
[0]), type
);
3802 return retype(brw_imm_ud(value
.u32
[0]), type
);
3804 if (type
== BRW_REGISTER_TYPE_DF
)
3805 return setup_imm_df(bld
, value
.f64
[0]);
3807 return retype(brw_imm_u64(value
.u64
[0]), type
);
3809 unreachable("Invalid type size");
3814 brw_op_for_nir_reduction_op(nir_op op
)
3817 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3818 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3819 case nir_op_imul
: return BRW_OPCODE_MUL
;
3820 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3821 case nir_op_imin
: return BRW_OPCODE_SEL
;
3822 case nir_op_umin
: return BRW_OPCODE_SEL
;
3823 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3824 case nir_op_imax
: return BRW_OPCODE_SEL
;
3825 case nir_op_umax
: return BRW_OPCODE_SEL
;
3826 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3827 case nir_op_iand
: return BRW_OPCODE_AND
;
3828 case nir_op_ior
: return BRW_OPCODE_OR
;
3829 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3831 unreachable("Invalid reduction operation");
3835 static brw_conditional_mod
3836 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3839 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3840 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3841 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3842 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3843 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3844 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3845 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3846 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3847 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3848 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3849 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3850 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3851 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3853 unreachable("Invalid reduction operation");
3858 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3861 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3862 dest
= get_nir_dest(instr
->dest
);
3864 switch (instr
->intrinsic
) {
3865 case nir_intrinsic_image_deref_load
:
3866 case nir_intrinsic_image_deref_store
:
3867 case nir_intrinsic_image_deref_atomic_add
:
3868 case nir_intrinsic_image_deref_atomic_min
:
3869 case nir_intrinsic_image_deref_atomic_max
:
3870 case nir_intrinsic_image_deref_atomic_and
:
3871 case nir_intrinsic_image_deref_atomic_or
:
3872 case nir_intrinsic_image_deref_atomic_xor
:
3873 case nir_intrinsic_image_deref_atomic_exchange
:
3874 case nir_intrinsic_image_deref_atomic_comp_swap
: {
3875 using namespace image_access
;
3877 if (stage
== MESA_SHADER_FRAGMENT
&&
3878 instr
->intrinsic
!= nir_intrinsic_image_deref_load
)
3879 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3881 /* Get the referenced image variable and type. */
3882 nir_deref_instr
*deref
= nir_src_as_deref(instr
->src
[0]);
3883 const nir_variable
*var
= nir_deref_instr_get_variable(deref
);
3884 const glsl_type
*type
= var
->type
->without_array();
3885 const brw_reg_type base_type
= get_image_base_type(type
);
3887 /* Get some metadata from the image intrinsic. */
3888 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3889 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3890 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3891 const unsigned format
= var
->data
.image
.format
;
3892 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3894 /* Get the arguments of the image intrinsic. */
3895 const fs_reg image
= get_nir_image_deref(deref
);
3896 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3897 BRW_REGISTER_TYPE_UD
);
3898 const fs_reg src0
= (info
->num_srcs
>= 4 ?
3899 retype(get_nir_src(instr
->src
[3]), base_type
) :
3901 const fs_reg src1
= (info
->num_srcs
>= 5 ?
3902 retype(get_nir_src(instr
->src
[4]), base_type
) :
3906 /* Emit an image load, store or atomic op. */
3907 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
)
3908 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3910 else if (instr
->intrinsic
== nir_intrinsic_image_deref_store
)
3911 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3912 var
->data
.image
.write_only
? GL_NONE
: format
);
3915 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3916 surf_dims
, arr_dims
, dest_components
,
3917 get_image_atomic_op(instr
->intrinsic
, type
));
3919 /* Assign the result. */
3920 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3921 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3922 offset(tmp
, bld
, c
));
3927 case nir_intrinsic_memory_barrier_atomic_counter
:
3928 case nir_intrinsic_memory_barrier_buffer
:
3929 case nir_intrinsic_memory_barrier_image
:
3930 case nir_intrinsic_memory_barrier
: {
3931 const fs_builder ubld
= bld
.group(8, 0);
3932 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3933 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3934 ->size_written
= 2 * REG_SIZE
;
3938 case nir_intrinsic_group_memory_barrier
:
3939 case nir_intrinsic_memory_barrier_shared
:
3940 /* We treat these workgroup-level barriers as no-ops. This should be
3941 * safe at present and as long as:
3943 * - Memory access instructions are not subsequently reordered by the
3944 * compiler back-end.
3946 * - All threads from a given compute shader workgroup fit within a
3947 * single subslice and therefore talk to the same HDC shared unit
3948 * what supposedly guarantees ordering and coherency between threads
3949 * from the same workgroup. This may change in the future when we
3950 * start splitting workgroups across multiple subslices.
3952 * - The context is not in fault-and-stream mode, which could cause
3953 * memory transactions (including to SLM) prior to the barrier to be
3954 * replayed after the barrier if a pagefault occurs. This shouldn't
3955 * be a problem up to and including SKL because fault-and-stream is
3956 * not usable due to hardware issues, but that's likely to change in
3961 case nir_intrinsic_shader_clock
: {
3962 /* We cannot do anything if there is an event, so ignore it for now */
3963 const fs_reg shader_clock
= get_timestamp(bld
);
3964 const fs_reg srcs
[] = { component(shader_clock
, 0),
3965 component(shader_clock
, 1) };
3966 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3970 case nir_intrinsic_image_deref_size
: {
3971 /* Get the referenced image variable and type. */
3972 nir_deref_instr
*deref
= nir_src_as_deref(instr
->src
[0]);
3973 const nir_variable
*var
= nir_deref_instr_get_variable(deref
);
3974 const glsl_type
*type
= var
->type
->without_array();
3976 /* Get the size of the image. */
3977 const fs_reg image
= get_nir_image_deref(deref
);
3978 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3980 /* For 1DArray image types, the array index is stored in the Z component.
3981 * Fix this by swizzling the Z component to the Y component.
3983 const bool is_1d_array_image
=
3984 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3985 type
->sampler_array
;
3987 /* For CubeArray images, we should count the number of cubes instead
3988 * of the number of faces. Fix it by dividing the (Z component) by 6.
3990 const bool is_cube_array_image
=
3991 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3992 type
->sampler_array
;
3994 /* Copy all the components. */
3995 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3996 if ((int)c
>= type
->coordinate_components()) {
3997 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3999 } else if (c
== 1 && is_1d_array_image
) {
4000 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
4001 offset(size
, bld
, 2));
4002 } else if (c
== 2 && is_cube_array_image
) {
4003 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4004 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
4005 offset(size
, bld
, c
), brw_imm_d(6));
4007 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
4008 offset(size
, bld
, c
));
4015 case nir_intrinsic_image_deref_samples
:
4016 /* The driver does not support multi-sampled images. */
4017 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4020 case nir_intrinsic_load_uniform
: {
4021 /* Offsets are in bytes but they should always aligned to
4024 assert(instr
->const_index
[0] % 4 == 0 ||
4025 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4027 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4029 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4031 assert(const_offset
->u32
[0] % type_sz(dest
.type
) == 0);
4032 /* For 16-bit types we add the module of the const_index[0]
4033 * offset to access to not 32-bit aligned element
4035 src
.offset
= const_offset
->u32
[0] + instr
->const_index
[0] % 4;
4037 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4038 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4041 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4042 BRW_REGISTER_TYPE_UD
);
4044 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4045 * go past the end of the uniform. In order to keep the n'th
4046 * component from running past, we subtract off the size of all but
4047 * one component of the vector.
4049 assert(instr
->const_index
[1] >=
4050 instr
->num_components
* (int) type_sz(dest
.type
));
4051 unsigned read_size
= instr
->const_index
[1] -
4052 (instr
->num_components
- 1) * type_sz(dest
.type
);
4054 bool supports_64bit_indirects
=
4055 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4057 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4058 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4059 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4060 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4061 indirect
, brw_imm_ud(read_size
));
4064 const unsigned num_mov_indirects
=
4065 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4066 /* We read a little bit less per MOV INDIRECT, as they are now
4067 * 32-bits ones instead of 64-bit. Fix read_size then.
4069 const unsigned read_size_32bit
= read_size
-
4070 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4071 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4072 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4073 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4074 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4075 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4076 indirect
, brw_imm_ud(read_size_32bit
));
4084 case nir_intrinsic_load_ubo
: {
4085 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4089 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4090 const_index
->u32
[0];
4091 surf_index
= brw_imm_ud(index
);
4092 brw_mark_surface_used(prog_data
, index
);
4094 /* The block index is not a constant. Evaluate the index expression
4095 * per-channel and add the base UBO index; we have to select a value
4096 * from any live channel.
4098 surf_index
= vgrf(glsl_type::uint_type
);
4099 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4100 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4101 surf_index
= bld
.emit_uniformize(surf_index
);
4103 /* Assume this may touch any UBO. It would be nice to provide
4104 * a tighter bound, but the array information is already lowered away.
4106 brw_mark_surface_used(prog_data
,
4107 stage_prog_data
->binding_table
.ubo_start
+
4108 nir
->info
.num_ubos
- 1);
4111 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4112 if (const_offset
== NULL
) {
4113 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4114 BRW_REGISTER_TYPE_UD
);
4116 for (int i
= 0; i
< instr
->num_components
; i
++)
4117 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4118 base_offset
, i
* type_sz(dest
.type
));
4120 /* Even if we are loading doubles, a pull constant load will load
4121 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4122 * need to load a full dvec4 we will have to emit 2 loads. This is
4123 * similar to demote_pull_constants(), except that in that case we
4124 * see individual accesses to each component of the vector and then
4125 * we let CSE deal with duplicate loads. Here we see a vector access
4126 * and we have to split it if necessary.
4128 const unsigned type_size
= type_sz(dest
.type
);
4130 /* See if we've selected this as a push constant candidate */
4132 const unsigned ubo_block
= const_index
->u32
[0];
4133 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
4136 for (int i
= 0; i
< 4; i
++) {
4137 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4138 if (range
->block
== ubo_block
&&
4139 offset_256b
>= range
->start
&&
4140 offset_256b
< range
->start
+ range
->length
) {
4142 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4143 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
4148 if (push_reg
.file
!= BAD_FILE
) {
4149 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4150 bld
.MOV(offset(dest
, bld
, i
),
4151 byte_offset(push_reg
, i
* type_size
));
4157 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4158 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4159 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4161 for (unsigned c
= 0; c
< instr
->num_components
;) {
4162 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4163 /* Number of usable components in the next block-aligned load. */
4164 const unsigned count
= MIN2(instr
->num_components
- c
,
4165 (block_sz
- base
% block_sz
) / type_size
);
4167 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4168 packed_consts
, surf_index
,
4169 brw_imm_ud(base
& ~(block_sz
- 1)));
4171 const fs_reg consts
=
4172 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4175 for (unsigned d
= 0; d
< count
; d
++)
4176 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4184 case nir_intrinsic_load_ssbo
: {
4185 assert(devinfo
->gen
>= 7);
4187 nir_const_value
*const_uniform_block
=
4188 nir_src_as_const_value(instr
->src
[0]);
4191 if (const_uniform_block
) {
4192 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4193 const_uniform_block
->u32
[0];
4194 surf_index
= brw_imm_ud(index
);
4195 brw_mark_surface_used(prog_data
, index
);
4197 surf_index
= vgrf(glsl_type::uint_type
);
4198 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4199 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4201 /* Assume this may touch any UBO. It would be nice to provide
4202 * a tighter bound, but the array information is already lowered away.
4204 brw_mark_surface_used(prog_data
,
4205 stage_prog_data
->binding_table
.ssbo_start
+
4206 nir
->info
.num_ssbos
- 1);
4210 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4212 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4214 offset_reg
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
);
4217 /* Read the vector */
4218 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4219 instr
->num_components
);
4224 case nir_intrinsic_store_ssbo
: {
4225 assert(devinfo
->gen
>= 7);
4227 if (stage
== MESA_SHADER_FRAGMENT
)
4228 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4232 nir_const_value
*const_uniform_block
=
4233 nir_src_as_const_value(instr
->src
[1]);
4234 if (const_uniform_block
) {
4235 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4236 const_uniform_block
->u32
[0];
4237 surf_index
= brw_imm_ud(index
);
4238 brw_mark_surface_used(prog_data
, index
);
4240 surf_index
= vgrf(glsl_type::uint_type
);
4241 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4242 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4244 brw_mark_surface_used(prog_data
,
4245 stage_prog_data
->binding_table
.ssbo_start
+
4246 nir
->info
.num_ssbos
- 1);
4250 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4253 unsigned writemask
= instr
->const_index
[0];
4255 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4256 * since the untyped writes below operate in units of 32-bits, which
4257 * means that we need to write twice as many components each time.
4258 * Also, we have to suffle 64-bit data to be in the appropriate layout
4259 * expected by our 32-bit write messages.
4261 unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4262 unsigned type_size
= bit_size
/ 8;
4264 /* Combine groups of consecutive enabled channels in one write
4265 * message. We use ffs to find the first enabled channel and then ffs on
4266 * the bit-inverse, down-shifted writemask to determine the num_components
4267 * of the block of enabled bits.
4270 unsigned first_component
= ffs(writemask
) - 1;
4271 unsigned num_components
= ffs(~(writemask
>> first_component
)) - 1;
4272 fs_reg write_src
= offset(val_reg
, bld
, first_component
);
4274 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4276 if (type_size
> 4) {
4277 /* We can't write more than 2 64-bit components at once. Limit
4278 * the num_components of the write to what we can do and let the next
4279 * iteration handle the rest.
4281 num_components
= MIN2(2, num_components
);
4282 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4284 } else if (type_size
< 4) {
4285 assert(type_size
== 2);
4286 /* For 16-bit types we pack two consecutive values into a 32-bit
4287 * word and use an untyped write message. For single values or not
4288 * 32-bit-aligned we need to use byte-scattered writes because
4289 * untyped writes works with 32-bit components with 32-bit
4290 * alignment. byte_scattered_write messages only support one
4291 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4292 * could be enabled we can not guarantee that not constant offsets
4293 * to be 32-bit aligned for 16-bit types. For example an array, of
4294 * 16-bit vec3 with array element stride of 6.
4296 * In the case of 32-bit aligned constant offsets if there is
4297 * a 3-components vector we submit one untyped-write message
4298 * of 32-bit (first two components), and one byte-scattered
4299 * write message (the last component).
4302 if ( !const_offset
|| ((const_offset
->u32
[0] +
4303 type_size
* first_component
) % 4)) {
4304 /* If we use a .yz writemask we also need to emit 2
4305 * byte-scattered write messages because of y-component not
4306 * being aligned to 32-bit.
4309 } else if (num_components
> 2 && (num_components
% 2)) {
4310 /* If there is an odd number of consecutive components we left
4311 * the not paired component for a following emit of length == 1
4312 * with byte_scattered_write.
4316 /* For num_components == 1 we are also shuffling the component
4317 * because byte scattered writes of 16-bit need values to be dword
4318 * aligned. Shuffling only one component would be the same as
4321 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4328 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4329 type_size
* first_component
);
4331 offset_reg
= vgrf(glsl_type::uint_type
);
4333 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4334 brw_imm_ud(type_size
* first_component
));
4337 if (type_size
< 4 && num_components
== 1) {
4338 assert(type_size
== 2);
4339 /* Untyped Surface messages have a fixed 32-bit size, so we need
4340 * to rely on byte scattered in order to write 16-bit elements.
4341 * The byte_scattered_write message needs that every written 16-bit
4342 * type to be aligned 32-bits (stride=2).
4344 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4348 BRW_PREDICATE_NONE
);
4350 assert(num_components
* type_size
<= 16);
4351 assert((num_components
* type_size
) % 4 == 0);
4352 assert(offset_reg
.file
!= BRW_IMMEDIATE_VALUE
||
4353 offset_reg
.ud
% 4 == 0);
4354 unsigned num_slots
= (num_components
* type_size
) / 4;
4356 emit_untyped_write(bld
, surf_index
, offset_reg
,
4358 1 /* dims */, num_slots
,
4359 BRW_PREDICATE_NONE
);
4362 /* Clear the bits in the writemask that we just wrote, then try
4363 * again to see if more channels are left.
4365 writemask
&= (15 << (first_component
+ num_components
));
4370 case nir_intrinsic_store_output
: {
4371 fs_reg src
= get_nir_src(instr
->src
[0]);
4373 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4374 assert(const_offset
&& "Indirect output stores not allowed");
4376 unsigned num_components
= instr
->num_components
;
4377 unsigned first_component
= nir_intrinsic_component(instr
);
4378 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4379 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4380 num_components
*= 2;
4383 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4384 4 * const_offset
->u32
[0]), src
.type
);
4385 for (unsigned j
= 0; j
< num_components
; j
++) {
4386 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4387 offset(src
, bld
, j
));
4392 case nir_intrinsic_ssbo_atomic_add
:
4393 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4395 case nir_intrinsic_ssbo_atomic_imin
:
4396 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4398 case nir_intrinsic_ssbo_atomic_umin
:
4399 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4401 case nir_intrinsic_ssbo_atomic_imax
:
4402 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4404 case nir_intrinsic_ssbo_atomic_umax
:
4405 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4407 case nir_intrinsic_ssbo_atomic_and
:
4408 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4410 case nir_intrinsic_ssbo_atomic_or
:
4411 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4413 case nir_intrinsic_ssbo_atomic_xor
:
4414 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4416 case nir_intrinsic_ssbo_atomic_exchange
:
4417 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4419 case nir_intrinsic_ssbo_atomic_comp_swap
:
4420 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4423 case nir_intrinsic_get_buffer_size
: {
4424 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4425 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4427 /* A resinfo's sampler message is used to get the buffer size. The
4428 * SIMD8's writeback message consists of four registers and SIMD16's
4429 * writeback message consists of 8 destination registers (two per each
4430 * component). Because we are only interested on the first channel of
4431 * the first returned component, where resinfo returns the buffer size
4432 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4433 * the dispatch width.
4435 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4436 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4437 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4440 ubld
.MOV(src_payload
, brw_imm_d(0));
4442 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4443 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4444 src_payload
, brw_imm_ud(index
));
4445 inst
->header_size
= 0;
4447 inst
->size_written
= 4 * REG_SIZE
;
4449 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4451 * "Out-of-bounds checking is always performed at a DWord granularity. If
4452 * any part of the DWord is out-of-bounds then the whole DWord is
4453 * considered out-of-bounds."
4455 * This implies that types with size smaller than 4-bytes need to be
4456 * padded if they don't complete the last dword of the buffer. But as we
4457 * need to maintain the original size we need to reverse the padding
4458 * calculation to return the correct size to know the number of elements
4459 * of an unsized array. As we stored in the last two bits of the surface
4460 * size the needed padding for the buffer, we calculate here the
4461 * original buffer_size reversing the surface_size calculation:
4463 * surface_size = isl_align(buffer_size, 4) +
4464 * (isl_align(buffer_size) - buffer_size)
4466 * buffer_size = surface_size & ~3 - surface_size & 3
4469 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4470 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4471 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4473 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4474 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4475 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4477 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4479 brw_mark_surface_used(prog_data
, index
);
4483 case nir_intrinsic_load_subgroup_invocation
:
4484 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4485 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4488 case nir_intrinsic_load_subgroup_eq_mask
:
4489 case nir_intrinsic_load_subgroup_ge_mask
:
4490 case nir_intrinsic_load_subgroup_gt_mask
:
4491 case nir_intrinsic_load_subgroup_le_mask
:
4492 case nir_intrinsic_load_subgroup_lt_mask
:
4493 unreachable("not reached");
4495 case nir_intrinsic_vote_any
: {
4496 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4498 /* The any/all predicates do not consider channel enables. To prevent
4499 * dead channels from affecting the result, we initialize the flag with
4500 * with the identity value for the logical operation.
4502 if (dispatch_width
== 32) {
4503 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4504 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4507 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4509 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4511 /* For some reason, the any/all predicates don't work properly with
4512 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4513 * doesn't read the correct subset of the flag register and you end up
4514 * getting garbage in the second half. Work around this by using a pair
4515 * of 1-wide MOVs and scattering the result.
4517 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4518 ubld
.MOV(res1
, brw_imm_d(0));
4519 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4520 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4521 BRW_PREDICATE_ALIGN1_ANY32H
,
4522 ubld
.MOV(res1
, brw_imm_d(-1)));
4524 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4527 case nir_intrinsic_vote_all
: {
4528 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4530 /* The any/all predicates do not consider channel enables. To prevent
4531 * dead channels from affecting the result, we initialize the flag with
4532 * with the identity value for the logical operation.
4534 if (dispatch_width
== 32) {
4535 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4536 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4537 brw_imm_ud(0xffffffff));
4539 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4541 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4543 /* For some reason, the any/all predicates don't work properly with
4544 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4545 * doesn't read the correct subset of the flag register and you end up
4546 * getting garbage in the second half. Work around this by using a pair
4547 * of 1-wide MOVs and scattering the result.
4549 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4550 ubld
.MOV(res1
, brw_imm_d(0));
4551 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4552 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4553 BRW_PREDICATE_ALIGN1_ALL32H
,
4554 ubld
.MOV(res1
, brw_imm_d(-1)));
4556 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4559 case nir_intrinsic_vote_feq
:
4560 case nir_intrinsic_vote_ieq
: {
4561 fs_reg value
= get_nir_src(instr
->src
[0]);
4562 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4563 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4564 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4567 fs_reg uniformized
= bld
.emit_uniformize(value
);
4568 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4570 /* The any/all predicates do not consider channel enables. To prevent
4571 * dead channels from affecting the result, we initialize the flag with
4572 * with the identity value for the logical operation.
4574 if (dispatch_width
== 32) {
4575 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4576 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4577 brw_imm_ud(0xffffffff));
4579 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4581 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4583 /* For some reason, the any/all predicates don't work properly with
4584 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4585 * doesn't read the correct subset of the flag register and you end up
4586 * getting garbage in the second half. Work around this by using a pair
4587 * of 1-wide MOVs and scattering the result.
4589 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4590 ubld
.MOV(res1
, brw_imm_d(0));
4591 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4592 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4593 BRW_PREDICATE_ALIGN1_ALL32H
,
4594 ubld
.MOV(res1
, brw_imm_d(-1)));
4596 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4600 case nir_intrinsic_ballot
: {
4601 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4602 BRW_REGISTER_TYPE_UD
);
4603 struct brw_reg flag
= brw_flag_reg(0, 0);
4604 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4605 * as f0.0. This is a problem for fragment programs as we currently use
4606 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4607 * programs yet so this isn't a problem. When we do, something will
4610 if (dispatch_width
== 32)
4611 flag
.type
= BRW_REGISTER_TYPE_UD
;
4613 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4614 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4616 if (instr
->dest
.ssa
.bit_size
> 32) {
4617 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4619 dest
.type
= BRW_REGISTER_TYPE_UD
;
4621 bld
.MOV(dest
, flag
);
4625 case nir_intrinsic_read_invocation
: {
4626 const fs_reg value
= get_nir_src(instr
->src
[0]);
4627 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4628 fs_reg tmp
= bld
.vgrf(value
.type
);
4630 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4631 bld
.emit_uniformize(invocation
));
4633 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4637 case nir_intrinsic_read_first_invocation
: {
4638 const fs_reg value
= get_nir_src(instr
->src
[0]);
4639 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4643 case nir_intrinsic_shuffle
: {
4644 const fs_reg value
= get_nir_src(instr
->src
[0]);
4645 const fs_reg index
= get_nir_src(instr
->src
[1]);
4647 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4651 case nir_intrinsic_first_invocation
: {
4652 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4653 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4654 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4655 fs_reg(component(tmp
, 0)));
4659 case nir_intrinsic_quad_broadcast
: {
4660 const fs_reg value
= get_nir_src(instr
->src
[0]);
4661 nir_const_value
*index
= nir_src_as_const_value(instr
->src
[1]);
4662 assert(nir_src_bit_size(instr
->src
[1]) == 32);
4664 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4665 value
, brw_imm_ud(index
->u32
[0]), brw_imm_ud(4));
4669 case nir_intrinsic_quad_swap_horizontal
: {
4670 const fs_reg value
= get_nir_src(instr
->src
[0]);
4671 const fs_reg tmp
= bld
.vgrf(value
.type
);
4672 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4674 const fs_reg src_left
= horiz_stride(value
, 2);
4675 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4676 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4677 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4679 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4681 * "When source or destination datatype is 64b or operation is
4682 * integer DWord multiply, regioning in Align1 must follow
4687 * 3. Source and Destination offset must be the same, except
4688 * the case of scalar source."
4690 * In order to work around this, we have to emit two 32-bit MOVs instead
4691 * of a single 64-bit MOV to do the shuffle.
4693 if (type_sz(value
.type
) > 4 &&
4694 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4695 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4696 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4697 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4698 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4699 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4700 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4701 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4702 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4704 ubld
.MOV(tmp_left
, src_right
);
4705 ubld
.MOV(tmp_right
, src_left
);
4707 bld
.MOV(retype(dest
, value
.type
), tmp
);
4711 case nir_intrinsic_quad_swap_vertical
: {
4712 const fs_reg value
= get_nir_src(instr
->src
[0]);
4713 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4714 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4715 const fs_reg tmp
= bld
.vgrf(value
.type
);
4716 const fs_builder ubld
= bld
.exec_all();
4717 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4718 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4719 bld
.MOV(retype(dest
, value
.type
), tmp
);
4721 /* For larger data types, we have to either emit dispatch_width many
4722 * MOVs or else fall back to doing indirects.
4724 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4725 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4727 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4732 case nir_intrinsic_quad_swap_diagonal
: {
4733 const fs_reg value
= get_nir_src(instr
->src
[0]);
4734 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4735 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4736 const fs_reg tmp
= bld
.vgrf(value
.type
);
4737 const fs_builder ubld
= bld
.exec_all();
4738 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4739 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4740 bld
.MOV(retype(dest
, value
.type
), tmp
);
4742 /* For larger data types, we have to either emit dispatch_width many
4743 * MOVs or else fall back to doing indirects.
4745 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4746 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4748 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4753 case nir_intrinsic_reduce
: {
4754 fs_reg src
= get_nir_src(instr
->src
[0]);
4755 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4756 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4757 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4758 cluster_size
= dispatch_width
;
4760 /* Figure out the source type */
4761 src
.type
= brw_type_for_nir_type(devinfo
,
4762 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4763 nir_src_bit_size(instr
->src
[0])));
4765 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4766 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4767 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4769 /* Set up a register for all of our scratching around and initialize it
4770 * to reduction operation's identity value.
4772 fs_reg scan
= bld
.vgrf(src
.type
);
4773 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4775 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4777 dest
.type
= src
.type
;
4778 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4779 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4780 * the distance between clusters is at least 2 GRFs. In this case,
4781 * we don't need the weird striding of the CLUSTER_BROADCAST
4782 * instruction and can just do regular MOVs.
4784 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4785 const unsigned groups
=
4786 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4787 const unsigned group_size
= dispatch_width
/ groups
;
4788 for (unsigned i
= 0; i
< groups
; i
++) {
4789 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4790 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4791 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4792 component(scan
, comp
));
4795 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4796 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4801 case nir_intrinsic_inclusive_scan
:
4802 case nir_intrinsic_exclusive_scan
: {
4803 fs_reg src
= get_nir_src(instr
->src
[0]);
4804 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4806 /* Figure out the source type */
4807 src
.type
= brw_type_for_nir_type(devinfo
,
4808 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4809 nir_src_bit_size(instr
->src
[0])));
4811 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4812 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4813 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4815 /* Set up a register for all of our scratching around and initialize it
4816 * to reduction operation's identity value.
4818 fs_reg scan
= bld
.vgrf(src
.type
);
4819 const fs_builder allbld
= bld
.exec_all();
4820 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4822 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4823 /* Exclusive scan is a bit harder because we have to do an annoying
4824 * shift of the contents before we can begin. To make things worse,
4825 * we can't do this with a normal stride; we have to use indirects.
4827 fs_reg shifted
= bld
.vgrf(src
.type
);
4828 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4829 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4831 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4832 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4836 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4838 bld
.MOV(retype(dest
, src
.type
), scan
);
4842 case nir_intrinsic_begin_invocation_interlock
: {
4843 const fs_builder ubld
= bld
.group(8, 0);
4844 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4846 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4852 case nir_intrinsic_end_invocation_interlock
: {
4853 /* We don't need to do anything here */
4858 unreachable("unknown intrinsic");
4863 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4864 int op
, nir_intrinsic_instr
*instr
)
4866 if (stage
== MESA_SHADER_FRAGMENT
)
4867 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4870 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4871 dest
= get_nir_dest(instr
->dest
);
4874 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4875 if (const_surface
) {
4876 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4877 const_surface
->u32
[0];
4878 surface
= brw_imm_ud(surf_index
);
4879 brw_mark_surface_used(prog_data
, surf_index
);
4881 surface
= vgrf(glsl_type::uint_type
);
4882 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4883 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4885 /* Assume this may touch any SSBO. This is the same we do for other
4886 * UBO/SSBO accesses with non-constant surface.
4888 brw_mark_surface_used(prog_data
,
4889 stage_prog_data
->binding_table
.ssbo_start
+
4890 nir
->info
.num_ssbos
- 1);
4893 fs_reg offset
= get_nir_src(instr
->src
[1]);
4894 fs_reg data1
= get_nir_src(instr
->src
[2]);
4896 if (op
== BRW_AOP_CMPWR
)
4897 data2
= get_nir_src(instr
->src
[3]);
4899 /* Emit the actual atomic operation */
4901 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4903 1 /* dims */, 1 /* rsize */,
4905 BRW_PREDICATE_NONE
);
4906 dest
.type
= atomic_result
.type
;
4907 bld
.MOV(dest
, atomic_result
);
4911 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4912 int op
, nir_intrinsic_instr
*instr
)
4915 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4916 dest
= get_nir_dest(instr
->dest
);
4918 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4920 fs_reg data1
= get_nir_src(instr
->src
[1]);
4922 if (op
== BRW_AOP_CMPWR
)
4923 data2
= get_nir_src(instr
->src
[2]);
4925 /* Get the offset */
4926 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4928 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4930 offset
= vgrf(glsl_type::uint_type
);
4932 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4933 brw_imm_ud(instr
->const_index
[0]));
4936 /* Emit the actual atomic operation operation */
4938 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4940 1 /* dims */, 1 /* rsize */,
4942 BRW_PREDICATE_NONE
);
4943 dest
.type
= atomic_result
.type
;
4944 bld
.MOV(dest
, atomic_result
);
4948 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4950 unsigned texture
= instr
->texture_index
;
4951 unsigned sampler
= instr
->sampler_index
;
4953 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4955 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4956 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4958 int lod_components
= 0;
4960 /* The hardware requires a LOD for buffer textures */
4961 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4962 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4964 uint32_t header_bits
= 0;
4965 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4966 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4967 switch (instr
->src
[i
].src_type
) {
4968 case nir_tex_src_bias
:
4969 srcs
[TEX_LOGICAL_SRC_LOD
] =
4970 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4972 case nir_tex_src_comparator
:
4973 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4975 case nir_tex_src_coord
:
4976 switch (instr
->op
) {
4978 case nir_texop_txf_ms
:
4979 case nir_texop_txf_ms_mcs
:
4980 case nir_texop_samples_identical
:
4981 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4984 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4988 case nir_tex_src_ddx
:
4989 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4990 lod_components
= nir_tex_instr_src_size(instr
, i
);
4992 case nir_tex_src_ddy
:
4993 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4995 case nir_tex_src_lod
:
4996 switch (instr
->op
) {
4998 srcs
[TEX_LOGICAL_SRC_LOD
] =
4999 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5002 srcs
[TEX_LOGICAL_SRC_LOD
] =
5003 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5006 srcs
[TEX_LOGICAL_SRC_LOD
] =
5007 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5011 case nir_tex_src_ms_index
:
5012 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5015 case nir_tex_src_offset
: {
5016 nir_const_value
*const_offset
=
5017 nir_src_as_const_value(instr
->src
[i
].src
);
5018 unsigned offset_bits
= 0;
5020 brw_texture_offset(const_offset
->i32
,
5021 nir_tex_instr_src_size(instr
, i
),
5023 header_bits
|= offset_bits
;
5025 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5026 retype(src
, BRW_REGISTER_TYPE_D
);
5031 case nir_tex_src_projector
:
5032 unreachable("should be lowered");
5034 case nir_tex_src_texture_offset
: {
5035 /* Figure out the highest possible texture index and mark it as used */
5036 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
5037 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
5038 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
5040 max_used
+= stage_prog_data
->binding_table
.texture_start
;
5042 brw_mark_surface_used(prog_data
, max_used
);
5044 /* Emit code to evaluate the actual indexing expression */
5045 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5046 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5047 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5051 case nir_tex_src_sampler_offset
: {
5052 /* Emit code to evaluate the actual indexing expression */
5053 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5054 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5055 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5059 case nir_tex_src_ms_mcs
:
5060 assert(instr
->op
== nir_texop_txf_ms
);
5061 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5064 case nir_tex_src_plane
: {
5065 nir_const_value
*const_plane
=
5066 nir_src_as_const_value(instr
->src
[i
].src
);
5067 const uint32_t plane
= const_plane
->u32
[0];
5068 const uint32_t texture_index
=
5069 instr
->texture_index
+
5070 stage_prog_data
->binding_table
.plane_start
[plane
] -
5071 stage_prog_data
->binding_table
.texture_start
;
5073 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5078 unreachable("unknown texture source");
5082 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5083 (instr
->op
== nir_texop_txf_ms
||
5084 instr
->op
== nir_texop_samples_identical
)) {
5085 if (devinfo
->gen
>= 7 &&
5086 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5087 srcs
[TEX_LOGICAL_SRC_MCS
] =
5088 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5089 instr
->coord_components
,
5090 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5092 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5096 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5097 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5100 switch (instr
->op
) {
5102 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5103 SHADER_OPCODE_TXL_LOGICAL
);
5106 opcode
= FS_OPCODE_TXB_LOGICAL
;
5109 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5112 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5115 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5117 case nir_texop_txf_ms
:
5118 if ((key_tex
->msaa_16
& (1 << sampler
)))
5119 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5121 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5123 case nir_texop_txf_ms_mcs
:
5124 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5126 case nir_texop_query_levels
:
5128 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5131 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5134 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5135 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5137 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5139 case nir_texop_texture_samples
:
5140 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5142 case nir_texop_samples_identical
: {
5143 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5145 /* If mcs is an immediate value, it means there is no MCS. In that case
5146 * just return false.
5148 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5149 bld
.MOV(dst
, brw_imm_ud(0u));
5150 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5151 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5152 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5153 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5154 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5156 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5157 BRW_CONDITIONAL_EQ
);
5162 unreachable("unknown texture opcode");
5165 if (instr
->op
== nir_texop_tg4
) {
5166 if (instr
->component
== 1 &&
5167 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5168 /* gather4 sampler is broken for green channel on RG32F --
5169 * we must ask for blue instead.
5171 header_bits
|= 2 << 16;
5173 header_bits
|= instr
->component
<< 16;
5177 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5178 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5179 inst
->offset
= header_bits
;
5181 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5182 if (devinfo
->gen
>= 9 &&
5183 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5184 unsigned write_mask
= instr
->dest
.is_ssa
?
5185 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5186 (1 << dest_size
) - 1;
5187 assert(write_mask
!= 0); /* dead code should have been eliminated */
5188 inst
->size_written
= util_last_bit(write_mask
) *
5189 inst
->dst
.component_size(inst
->exec_size
);
5191 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5194 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5195 inst
->shadow_compare
= true;
5197 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5198 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5201 for (unsigned i
= 0; i
< dest_size
; i
++)
5202 nir_dest
[i
] = offset(dst
, bld
, i
);
5204 if (instr
->op
== nir_texop_query_levels
) {
5205 /* # levels is in .w */
5206 nir_dest
[0] = offset(dst
, bld
, 3);
5207 } else if (instr
->op
== nir_texop_txs
&&
5208 dest_size
>= 3 && devinfo
->gen
< 7) {
5209 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5210 fs_reg depth
= offset(dst
, bld
, 2);
5211 nir_dest
[2] = vgrf(glsl_type::int_type
);
5212 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5215 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5219 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5221 switch (instr
->type
) {
5222 case nir_jump_break
:
5223 bld
.emit(BRW_OPCODE_BREAK
);
5225 case nir_jump_continue
:
5226 bld
.emit(BRW_OPCODE_CONTINUE
);
5228 case nir_jump_return
:
5230 unreachable("unknown jump");
5235 * This helper takes a source register and un/shuffles it into the destination
5238 * If source type size is smaller than destination type size the operation
5239 * needed is a component shuffle. The opposite case would be an unshuffle. If
5240 * source/destination type size is equal a shuffle is done that would be
5241 * equivalent to a simple MOV.
5243 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5244 * components .xyz 16-bit vector on SIMD8 would be.
5246 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5247 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5249 * This helper will return the following 2 32-bit components with the 16-bit
5252 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5253 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5255 * For unshuffle, the example would be the opposite, a 64-bit type source
5256 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5259 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5260 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5261 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5262 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5264 * The returned result would be the following 4 32-bit components unshuffled:
5266 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5267 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5268 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5269 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5271 * - Source and destination register must not be overlapped.
5272 * - components units are measured in terms of the smaller type between
5273 * source and destination because we are un/shuffling the smaller
5274 * components from/into the bigger ones.
5275 * - first_component parameter allows skipping source components.
5278 shuffle_src_to_dst(const fs_builder
&bld
,
5281 uint32_t first_component
,
5282 uint32_t components
)
5284 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5285 assert(!regions_overlap(dst
,
5286 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5287 offset(src
, bld
, first_component
),
5288 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5289 for (unsigned i
= 0; i
< components
; i
++) {
5290 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5291 offset(src
, bld
, i
+ first_component
));
5293 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5294 /* Source is shuffled into destination */
5295 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5296 assert(!regions_overlap(dst
,
5297 type_sz(dst
.type
) * bld
.dispatch_width() *
5298 DIV_ROUND_UP(components
, size_ratio
),
5299 offset(src
, bld
, first_component
),
5300 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5302 brw_reg_type shuffle_type
=
5303 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5304 BRW_REGISTER_TYPE_D
);
5305 for (unsigned i
= 0; i
< components
; i
++) {
5306 fs_reg shuffle_component_i
=
5307 subscript(offset(dst
, bld
, i
/ size_ratio
),
5308 shuffle_type
, i
% size_ratio
);
5309 bld
.MOV(shuffle_component_i
,
5310 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5313 /* Source is unshuffled into destination */
5314 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5315 assert(!regions_overlap(dst
,
5316 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5317 offset(src
, bld
, first_component
/ size_ratio
),
5318 type_sz(src
.type
) * bld
.dispatch_width() *
5319 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5322 brw_reg_type shuffle_type
=
5323 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5324 BRW_REGISTER_TYPE_D
);
5325 for (unsigned i
= 0; i
< components
; i
++) {
5326 fs_reg shuffle_component_i
=
5327 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5328 shuffle_type
, (first_component
+ i
) % size_ratio
);
5329 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5330 shuffle_component_i
);
5336 shuffle_from_32bit_read(const fs_builder
&bld
,
5339 uint32_t first_component
,
5340 uint32_t components
)
5342 assert(type_sz(src
.type
) == 4);
5344 /* This function takes components in units of the destination type while
5345 * shuffle_src_to_dst takes components in units of the smallest type
5347 if (type_sz(dst
.type
) > 4) {
5348 assert(type_sz(dst
.type
) == 8);
5349 first_component
*= 2;
5353 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5357 shuffle_for_32bit_write(const fs_builder
&bld
,
5359 uint32_t first_component
,
5360 uint32_t components
)
5362 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5363 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5364 /* This function takes components in units of the source type while
5365 * shuffle_src_to_dst takes components in units of the smallest type
5367 if (type_sz(src
.type
) > 4) {
5368 assert(type_sz(src
.type
) == 8);
5369 first_component
*= 2;
5373 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5379 setup_imm_df(const fs_builder
&bld
, double v
)
5381 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5382 assert(devinfo
->gen
>= 7);
5384 if (devinfo
->gen
>= 8)
5385 return brw_imm_df(v
);
5387 /* gen7.5 does not support DF immediates straighforward but the DIM
5388 * instruction allows to set the 64-bit immediate value.
5390 if (devinfo
->is_haswell
) {
5391 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5392 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5393 ubld
.DIM(dst
, brw_imm_df(v
));
5394 return component(dst
, 0);
5397 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5398 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5399 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5401 * Alternatively, we could also produce a normal VGRF (without stride 0)
5402 * by writing to all the channels in the VGRF, however, that would hit the
5403 * gen7 bug where we have to split writes that span more than 1 register
5404 * into instructions with a width of 4 (otherwise the write to the second
5405 * register written runs into an execmask hardware bug) which isn't very
5418 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5419 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5420 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5421 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5423 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);