2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "util/u_math.h"
29 #include "util/bitscan.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
48 fs_visitor::nir_setup_outputs()
50 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
53 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
55 /* Calculate the size of output registers in a separate pass, before
56 * allocating them. With ARB_enhanced_layouts, multiple output variables
57 * may occupy the same slot, but have different type sizes.
59 nir_foreach_variable(var
, &nir
->outputs
) {
60 const int loc
= var
->data
.driver_location
;
61 const unsigned var_vec4s
=
62 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
63 : type_size_vec4(var
->type
);
64 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
67 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
68 if (vec4s
[loc
] == 0) {
73 unsigned reg_size
= vec4s
[loc
];
75 /* Check if there are any ranges that start within this range and extend
76 * past it. If so, include them in this allocation.
78 for (unsigned i
= 1; i
< reg_size
; i
++)
79 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
81 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
82 for (unsigned i
= 0; i
< reg_size
; i
++)
83 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
90 fs_visitor::nir_setup_uniforms()
92 /* Only the first compile gets to set up uniforms. */
93 if (push_constant_loc
) {
94 assert(pull_constant_loc
);
98 uniforms
= nir
->num_uniforms
/ 4;
100 if (stage
== MESA_SHADER_COMPUTE
) {
101 /* Add a uniform for the thread local id. It must be the last uniform
104 assert(uniforms
== prog_data
->nr_params
);
105 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
106 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
107 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
112 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
116 nir_foreach_instr(instr
, block
) {
117 if (instr
->type
!= nir_instr_type_intrinsic
)
120 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
121 switch (intrin
->intrinsic
) {
122 case nir_intrinsic_load_vertex_id
:
123 case nir_intrinsic_load_base_vertex
:
124 unreachable("should be lowered by nir_lower_system_values().");
126 case nir_intrinsic_load_vertex_id_zero_base
:
127 case nir_intrinsic_load_is_indexed_draw
:
128 case nir_intrinsic_load_first_vertex
:
129 case nir_intrinsic_load_instance_id
:
130 case nir_intrinsic_load_base_instance
:
131 case nir_intrinsic_load_draw_id
:
132 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
134 case nir_intrinsic_load_invocation_id
:
135 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
137 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
138 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
139 if (reg
->file
== BAD_FILE
) {
140 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
141 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
142 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
143 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
148 case nir_intrinsic_load_sample_pos
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_samplepos_setup();
155 case nir_intrinsic_load_sample_id
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_sampleid_setup();
162 case nir_intrinsic_load_sample_mask_in
:
163 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
164 assert(v
->devinfo
->gen
>= 7);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplemaskin_setup();
170 case nir_intrinsic_load_work_group_id
:
171 assert(v
->stage
== MESA_SHADER_COMPUTE
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_cs_work_group_id_setup();
177 case nir_intrinsic_load_helper_invocation
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
180 if (reg
->file
== BAD_FILE
) {
181 const fs_builder abld
=
182 v
->bld
.annotate("gl_HelperInvocation", NULL
);
184 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
185 * pixel mask is in g1.7 of the thread payload.
187 * We move the per-channel pixel enable bit to the low bit of each
188 * channel by shifting the byte containing the pixel mask by the
189 * vector immediate 0x76543210UV.
191 * The region of <1,8,0> reads only 1 byte (the pixel masks for
192 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
193 * masks for 2 and 3) in SIMD16.
195 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
197 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
198 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
199 hbld
.SHR(offset(shifted
, hbld
, i
),
200 stride(retype(brw_vec1_grf(1 + i
, 7),
201 BRW_REGISTER_TYPE_UB
),
203 brw_imm_v(0x76543210));
206 /* A set bit in the pixel mask means the channel is enabled, but
207 * that is the opposite of gl_HelperInvocation so we need to invert
210 * The negate source-modifier bit of logical instructions on Gen8+
211 * performs 1's complement negation, so we can use that instead of
214 fs_reg inverted
= negate(shifted
);
215 if (v
->devinfo
->gen
< 8) {
216 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
217 abld
.NOT(inverted
, shifted
);
220 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
221 * with 1 and negating.
223 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
224 abld
.AND(anded
, inverted
, brw_imm_uw(1));
226 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
227 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
241 fs_visitor::nir_emit_system_values()
243 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
244 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
245 nir_system_values
[i
] = fs_reg();
248 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
249 * never end up using it.
252 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
253 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
254 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
256 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
257 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
258 if (dispatch_width
> 8)
259 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
260 if (dispatch_width
> 16) {
261 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
262 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
266 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
267 nir_foreach_block(block
, impl
)
268 emit_system_values_block(block
, this);
272 * Returns a type based on a reference_type (word, float, half-float) and a
275 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
277 * @FIXME: 64-bit return types are always DF on integer types to maintain
278 * compability with uses of DF previously to the introduction of int64
282 brw_reg_type_from_bit_size(const unsigned bit_size
,
283 const brw_reg_type reference_type
)
285 switch(reference_type
) {
286 case BRW_REGISTER_TYPE_HF
:
287 case BRW_REGISTER_TYPE_F
:
288 case BRW_REGISTER_TYPE_DF
:
291 return BRW_REGISTER_TYPE_HF
;
293 return BRW_REGISTER_TYPE_F
;
295 return BRW_REGISTER_TYPE_DF
;
297 unreachable("Invalid bit size");
299 case BRW_REGISTER_TYPE_B
:
300 case BRW_REGISTER_TYPE_W
:
301 case BRW_REGISTER_TYPE_D
:
302 case BRW_REGISTER_TYPE_Q
:
305 return BRW_REGISTER_TYPE_B
;
307 return BRW_REGISTER_TYPE_W
;
309 return BRW_REGISTER_TYPE_D
;
311 return BRW_REGISTER_TYPE_Q
;
313 unreachable("Invalid bit size");
315 case BRW_REGISTER_TYPE_UB
:
316 case BRW_REGISTER_TYPE_UW
:
317 case BRW_REGISTER_TYPE_UD
:
318 case BRW_REGISTER_TYPE_UQ
:
321 return BRW_REGISTER_TYPE_UB
;
323 return BRW_REGISTER_TYPE_UW
;
325 return BRW_REGISTER_TYPE_UD
;
327 return BRW_REGISTER_TYPE_UQ
;
329 unreachable("Invalid bit size");
332 unreachable("Unknown type");
337 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
339 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
340 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
341 nir_locals
[i
] = fs_reg();
344 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
345 unsigned array_elems
=
346 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
347 unsigned size
= array_elems
* reg
->num_components
;
348 const brw_reg_type reg_type
=
349 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
350 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
353 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
356 nir_emit_cf_list(&impl
->body
);
360 fs_visitor::nir_emit_cf_list(exec_list
*list
)
362 exec_list_validate(list
);
363 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
364 switch (node
->type
) {
366 nir_emit_if(nir_cf_node_as_if(node
));
369 case nir_cf_node_loop
:
370 nir_emit_loop(nir_cf_node_as_loop(node
));
373 case nir_cf_node_block
:
374 nir_emit_block(nir_cf_node_as_block(node
));
378 unreachable("Invalid CFG node block");
384 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
386 /* first, put the condition into f0 */
387 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
388 retype(get_nir_src(if_stmt
->condition
),
389 BRW_REGISTER_TYPE_D
));
390 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
392 bld
.IF(BRW_PREDICATE_NORMAL
);
394 nir_emit_cf_list(&if_stmt
->then_list
);
396 /* note: if the else is empty, dead CF elimination will remove it */
397 bld
.emit(BRW_OPCODE_ELSE
);
399 nir_emit_cf_list(&if_stmt
->else_list
);
401 bld
.emit(BRW_OPCODE_ENDIF
);
403 if (devinfo
->gen
< 7)
404 limit_dispatch_width(16, "Non-uniform control flow unsupported "
409 fs_visitor::nir_emit_loop(nir_loop
*loop
)
411 bld
.emit(BRW_OPCODE_DO
);
413 nir_emit_cf_list(&loop
->body
);
415 bld
.emit(BRW_OPCODE_WHILE
);
417 if (devinfo
->gen
< 7)
418 limit_dispatch_width(16, "Non-uniform control flow unsupported "
423 fs_visitor::nir_emit_block(nir_block
*block
)
425 nir_foreach_instr(instr
, block
) {
426 nir_emit_instr(instr
);
431 fs_visitor::nir_emit_instr(nir_instr
*instr
)
433 const fs_builder abld
= bld
.annotate(NULL
, instr
);
435 switch (instr
->type
) {
436 case nir_instr_type_alu
:
437 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
440 case nir_instr_type_deref
:
441 /* Derefs can exist for images but they do nothing */
444 case nir_instr_type_intrinsic
:
446 case MESA_SHADER_VERTEX
:
447 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
449 case MESA_SHADER_TESS_CTRL
:
450 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
452 case MESA_SHADER_TESS_EVAL
:
453 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
455 case MESA_SHADER_GEOMETRY
:
456 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
458 case MESA_SHADER_FRAGMENT
:
459 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
461 case MESA_SHADER_COMPUTE
:
462 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 unreachable("unsupported shader stage");
469 case nir_instr_type_tex
:
470 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
473 case nir_instr_type_load_const
:
474 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
477 case nir_instr_type_ssa_undef
:
478 /* We create a new VGRF for undefs on every use (by handling
479 * them in get_nir_src()), rather than for each definition.
480 * This helps register coalescing eliminate MOVs from undef.
484 case nir_instr_type_jump
:
485 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
489 unreachable("unknown instruction type");
494 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
498 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
499 const fs_reg
&result
)
501 if (!instr
->src
[0].src
.is_ssa
||
502 !instr
->src
[0].src
.ssa
->parent_instr
)
505 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
508 nir_alu_instr
*src0
=
509 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
511 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
512 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
515 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
517 /* Element type to extract.*/
518 const brw_reg_type type
= brw_int_type(
519 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
520 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
522 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
523 op0
.type
= brw_type_for_nir_type(devinfo
,
524 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
525 nir_src_bit_size(src0
->src
[0].src
)));
526 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
528 set_saturate(instr
->dest
.saturate
,
529 bld
.MOV(result
, subscript(op0
, type
, element
)));
534 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
535 const fs_reg
&result
)
537 if (!instr
->src
[0].src
.is_ssa
||
538 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
541 nir_intrinsic_instr
*src0
=
542 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
544 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
547 if (!nir_src_is_const(instr
->src
[1].src
) ||
548 !nir_src_is_const(instr
->src
[2].src
))
551 const float value1
= nir_src_as_float(instr
->src
[1].src
);
552 const float value2
= nir_src_as_float(instr
->src
[2].src
);
553 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
556 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
557 assert(value1
== -value2
);
559 fs_reg tmp
= vgrf(glsl_type::int_type
);
561 if (devinfo
->gen
>= 6) {
562 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
563 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
565 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
567 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
568 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
570 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
572 * This negation looks like it's safe in practice, because bits 0:4 will
573 * surely be TRIANGLES
576 if (value1
== -1.0f
) {
580 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
581 g0
, brw_imm_uw(0x3f80));
583 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
584 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
586 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
588 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
589 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
591 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
593 * This negation looks like it's safe in practice, because bits 0:4 will
594 * surely be TRIANGLES
597 if (value1
== -1.0f
) {
601 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
603 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
609 emit_find_msb_using_lzd(const fs_builder
&bld
,
610 const fs_reg
&result
,
618 /* LZD of an absolute value source almost always does the right
619 * thing. There are two problem values:
621 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
622 * 0. However, findMSB(int(0x80000000)) == 30.
624 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
625 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
627 * For a value of zero or negative one, -1 will be returned.
629 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
630 * findMSB(-(1<<x)) should return x-1.
632 * For all negative number cases, including 0x80000000 and
633 * 0xffffffff, the correct value is obtained from LZD if instead of
634 * negating the (already negative) value the logical-not is used. A
635 * conditonal logical-not can be achieved in two instructions.
637 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
639 bld
.ASR(temp
, src
, brw_imm_d(31));
640 bld
.XOR(temp
, temp
, src
);
643 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
644 retype(temp
, BRW_REGISTER_TYPE_UD
));
646 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
647 * from the LSB side. Subtract the result from 31 to convert the MSB
648 * count into an LSB count. If no bits are set, LZD will return 32.
649 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
651 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
652 inst
->src
[0].negate
= true;
656 brw_rnd_mode_from_nir_op (const nir_op op
) {
658 case nir_op_f2f16_rtz
:
659 return BRW_RND_MODE_RTZ
;
660 case nir_op_f2f16_rtne
:
661 return BRW_RND_MODE_RTNE
;
663 unreachable("Operation doesn't support rounding mode");
668 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
670 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
673 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
674 result
.type
= brw_type_for_nir_type(devinfo
,
675 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
676 nir_dest_bit_size(instr
->dest
.dest
)));
679 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
680 op
[i
] = get_nir_src(instr
->src
[i
].src
);
681 op
[i
].type
= brw_type_for_nir_type(devinfo
,
682 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
683 nir_src_bit_size(instr
->src
[i
].src
)));
684 op
[i
].abs
= instr
->src
[i
].abs
;
685 op
[i
].negate
= instr
->src
[i
].negate
;
688 /* We get a bunch of mov's out of the from_ssa pass and they may still
689 * be vectorized. We'll handle them as a special-case. We'll also
690 * handle vecN here because it's basically the same thing.
698 fs_reg temp
= result
;
699 bool need_extra_copy
= false;
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 if (!instr
->src
[i
].src
.is_ssa
&&
702 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
703 need_extra_copy
= true;
704 temp
= bld
.vgrf(result
.type
, 4);
709 for (unsigned i
= 0; i
< 4; i
++) {
710 if (!(instr
->dest
.write_mask
& (1 << i
)))
713 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
714 inst
= bld
.MOV(offset(temp
, bld
, i
),
715 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
717 inst
= bld
.MOV(offset(temp
, bld
, i
),
718 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
720 inst
->saturate
= instr
->dest
.saturate
;
723 /* In this case the source and destination registers were the same,
724 * so we need to insert an extra set of moves in order to deal with
727 if (need_extra_copy
) {
728 for (unsigned i
= 0; i
< 4; i
++) {
729 if (!(instr
->dest
.write_mask
& (1 << i
)))
732 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
741 /* At this point, we have dealt with any instruction that operates on
742 * more than a single channel. Therefore, we can just adjust the source
743 * and destination registers for that channel and emit the instruction.
745 unsigned channel
= 0;
746 if (nir_op_infos
[instr
->op
].output_size
== 0) {
747 /* Since NIR is doing the scalarizing for us, we should only ever see
748 * vectorized operations with a single channel.
750 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
751 channel
= ffs(instr
->dest
.write_mask
) - 1;
753 result
= offset(result
, bld
, channel
);
756 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
757 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
758 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
764 if (optimize_extract_to_float(instr
, result
))
766 inst
= bld
.MOV(result
, op
[0]);
767 inst
->saturate
= instr
->dest
.saturate
;
770 case nir_op_f2f16_rtne
:
771 case nir_op_f2f16_rtz
:
772 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
773 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
776 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
777 * on the HW gen, it is a special hw opcode or just a MOV, and
778 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
780 * But if we want to use that opcode, we need to provide support on
781 * different optimizations and lowerings. As right now HF support is
782 * only for gen8+, it will be better to use directly the MOV, and use
783 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
787 inst
= bld
.MOV(result
, op
[0]);
788 inst
->saturate
= instr
->dest
.saturate
;
793 op
[0].type
= BRW_REGISTER_TYPE_D
;
794 op
[0].negate
= !op
[0].negate
;
803 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
805 * "When source or destination is 64b (...), regioning in Align1
806 * must follow these rules:
808 * 1. Source and destination horizontal stride must be aligned to
812 * This means that conversions from bit-sizes smaller than 64-bit to
813 * 64-bit need to have the source data elements aligned to 64-bit.
814 * This restriction does not apply to BDW and later.
816 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
817 nir_src_bit_size(instr
->src
[0].src
) < 64 &&
818 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
819 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
820 tmp
= subscript(tmp
, op
[0].type
, 0);
821 inst
= bld
.MOV(tmp
, op
[0]);
822 inst
= bld
.MOV(result
, tmp
);
823 inst
->saturate
= instr
->dest
.saturate
;
840 inst
= bld
.MOV(result
, op
[0]);
841 inst
->saturate
= instr
->dest
.saturate
;
845 assert(!instr
->dest
.saturate
);
847 /* Straightforward since the source can be assumed to be either
848 * strictly >= 0 or strictly <= 0 depending on the setting of the
851 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
853 inst
= (op
[0].negate
)
854 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
855 : bld
.MOV(result
, brw_imm_f(1.0f
));
857 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
858 } else if (type_sz(op
[0].type
) < 8) {
859 /* AND(val, 0x80000000) gives the sign bit.
861 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
864 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
866 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
867 op
[0].type
= BRW_REGISTER_TYPE_UD
;
868 result
.type
= BRW_REGISTER_TYPE_UD
;
869 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
871 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
872 inst
->predicate
= BRW_PREDICATE_NORMAL
;
874 /* For doubles we do the same but we need to consider:
876 * - 2-src instructions can't operate with 64-bit immediates
877 * - The sign is encoded in the high 32-bit of each DF
878 * - We need to produce a DF result.
881 fs_reg zero
= vgrf(glsl_type::double_type
);
882 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
883 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
885 bld
.MOV(result
, zero
);
887 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
888 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
889 brw_imm_ud(0x80000000u
));
891 set_predicate(BRW_PREDICATE_NORMAL
,
892 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
898 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
899 * -> non-negative val generates 0x00000000.
900 * Predicated OR sets 1 if val is positive.
902 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
903 assert(bit_size
== 32 || bit_size
== 16);
905 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
906 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
907 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
909 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
910 bld
.ASR(result
, op
[0], shift
);
911 inst
= bld
.OR(result
, result
, one
);
912 inst
->predicate
= BRW_PREDICATE_NORMAL
;
917 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
918 inst
->saturate
= instr
->dest
.saturate
;
922 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
923 inst
->saturate
= instr
->dest
.saturate
;
927 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
928 inst
->saturate
= instr
->dest
.saturate
;
932 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
933 inst
->saturate
= instr
->dest
.saturate
;
937 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
938 inst
->saturate
= instr
->dest
.saturate
;
942 if (fs_key
->high_quality_derivatives
) {
943 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
945 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
947 inst
->saturate
= instr
->dest
.saturate
;
949 case nir_op_fddx_fine
:
950 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
951 inst
->saturate
= instr
->dest
.saturate
;
953 case nir_op_fddx_coarse
:
954 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
955 inst
->saturate
= instr
->dest
.saturate
;
958 if (fs_key
->high_quality_derivatives
) {
959 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
961 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
963 inst
->saturate
= instr
->dest
.saturate
;
965 case nir_op_fddy_fine
:
966 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
967 inst
->saturate
= instr
->dest
.saturate
;
969 case nir_op_fddy_coarse
:
970 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
971 inst
->saturate
= instr
->dest
.saturate
;
976 inst
= bld
.ADD(result
, op
[0], op
[1]);
977 inst
->saturate
= instr
->dest
.saturate
;
981 inst
= bld
.MUL(result
, op
[0], op
[1]);
982 inst
->saturate
= instr
->dest
.saturate
;
986 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
987 bld
.MUL(result
, op
[0], op
[1]);
990 case nir_op_imul_high
:
991 case nir_op_umul_high
:
992 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
993 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
998 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
999 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1002 case nir_op_uadd_carry
:
1003 unreachable("Should have been lowered by carry_to_arith().");
1005 case nir_op_usub_borrow
:
1006 unreachable("Should have been lowered by borrow_to_arith().");
1010 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1011 * appears that our hardware just does the right thing for signed
1014 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1015 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1019 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1020 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1022 /* Math instructions don't support conditional mod */
1023 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1024 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1026 /* Now, we need to determine if signs of the sources are different.
1027 * When we XOR the sources, the top bit is 0 if they are the same and 1
1028 * if they are different. We can then use a conditional modifier to
1029 * turn that into a predicate. This leads us to an XOR.l instruction.
1031 * Technically, according to the PRM, you're not allowed to use .l on a
1032 * XOR instruction. However, emperical experiments and Curro's reading
1033 * of the simulator source both indicate that it's safe.
1035 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1036 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1037 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1038 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1040 /* If the result of the initial remainder operation is non-zero and the
1041 * two sources have different signs, add in a copy of op[1] to get the
1042 * final integer modulus value.
1044 inst
= bld
.ADD(result
, result
, op
[1]);
1045 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1053 fs_reg dest
= result
;
1055 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1057 dest
= bld
.vgrf(op
[0].type
, 1);
1059 brw_conditional_mod cond
;
1060 switch (instr
->op
) {
1062 cond
= BRW_CONDITIONAL_L
;
1065 cond
= BRW_CONDITIONAL_GE
;
1068 cond
= BRW_CONDITIONAL_Z
;
1071 cond
= BRW_CONDITIONAL_NZ
;
1074 unreachable("bad opcode");
1077 bld
.CMP(dest
, op
[0], op
[1], cond
);
1079 if (bit_size
> 32) {
1080 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1081 } else if(bit_size
< 32) {
1082 /* When we convert the result to 32-bit we need to be careful and do
1083 * it as a signed conversion to get sign extension (for 32-bit true)
1085 const brw_reg_type src_type
=
1086 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1088 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1099 fs_reg dest
= result
;
1101 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1103 dest
= bld
.vgrf(op
[0].type
, 1);
1105 brw_conditional_mod cond
;
1106 switch (instr
->op
) {
1109 cond
= BRW_CONDITIONAL_L
;
1113 cond
= BRW_CONDITIONAL_GE
;
1116 cond
= BRW_CONDITIONAL_Z
;
1119 cond
= BRW_CONDITIONAL_NZ
;
1122 unreachable("bad opcode");
1124 bld
.CMP(dest
, op
[0], op
[1], cond
);
1126 if (bit_size
> 32) {
1127 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1128 } else if (bit_size
< 32) {
1129 /* When we convert the result to 32-bit we need to be careful and do
1130 * it as a signed conversion to get sign extension (for 32-bit true)
1132 const brw_reg_type src_type
=
1133 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1135 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1141 if (devinfo
->gen
>= 8) {
1142 op
[0] = resolve_source_modifiers(op
[0]);
1144 bld
.NOT(result
, op
[0]);
1147 if (devinfo
->gen
>= 8) {
1148 op
[0] = resolve_source_modifiers(op
[0]);
1149 op
[1] = resolve_source_modifiers(op
[1]);
1151 bld
.XOR(result
, op
[0], op
[1]);
1154 if (devinfo
->gen
>= 8) {
1155 op
[0] = resolve_source_modifiers(op
[0]);
1156 op
[1] = resolve_source_modifiers(op
[1]);
1158 bld
.OR(result
, op
[0], op
[1]);
1161 if (devinfo
->gen
>= 8) {
1162 op
[0] = resolve_source_modifiers(op
[0]);
1163 op
[1] = resolve_source_modifiers(op
[1]);
1165 bld
.AND(result
, op
[0], op
[1]);
1171 case nir_op_ball_fequal2
:
1172 case nir_op_ball_iequal2
:
1173 case nir_op_ball_fequal3
:
1174 case nir_op_ball_iequal3
:
1175 case nir_op_ball_fequal4
:
1176 case nir_op_ball_iequal4
:
1177 case nir_op_bany_fnequal2
:
1178 case nir_op_bany_inequal2
:
1179 case nir_op_bany_fnequal3
:
1180 case nir_op_bany_inequal3
:
1181 case nir_op_bany_fnequal4
:
1182 case nir_op_bany_inequal4
:
1183 unreachable("Lowered by nir_lower_alu_reductions");
1185 case nir_op_fnoise1_1
:
1186 case nir_op_fnoise1_2
:
1187 case nir_op_fnoise1_3
:
1188 case nir_op_fnoise1_4
:
1189 case nir_op_fnoise2_1
:
1190 case nir_op_fnoise2_2
:
1191 case nir_op_fnoise2_3
:
1192 case nir_op_fnoise2_4
:
1193 case nir_op_fnoise3_1
:
1194 case nir_op_fnoise3_2
:
1195 case nir_op_fnoise3_3
:
1196 case nir_op_fnoise3_4
:
1197 case nir_op_fnoise4_1
:
1198 case nir_op_fnoise4_2
:
1199 case nir_op_fnoise4_3
:
1200 case nir_op_fnoise4_4
:
1201 unreachable("not reached: should be handled by lower_noise");
1204 unreachable("not reached: should be handled by ldexp_to_arith()");
1207 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1208 inst
->saturate
= instr
->dest
.saturate
;
1212 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1213 inst
->saturate
= instr
->dest
.saturate
;
1218 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1219 if (bit_size
== 64) {
1220 /* two-argument instructions can't take 64-bit immediates */
1224 if (instr
->op
== nir_op_f2b
) {
1225 zero
= vgrf(glsl_type::double_type
);
1226 tmp
= vgrf(glsl_type::double_type
);
1227 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1229 zero
= vgrf(glsl_type::int64_t_type
);
1230 tmp
= vgrf(glsl_type::int64_t_type
);
1231 bld
.MOV(zero
, brw_imm_q(0));
1234 /* A SIMD16 execution needs to be split in two instructions, so use
1235 * a vgrf instead of the flag register as dst so instruction splitting
1238 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1239 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1242 if (bit_size
== 32) {
1243 zero
= instr
->op
== nir_op_f2b
? brw_imm_f(0.0f
) : brw_imm_d(0);
1245 assert(bit_size
== 16);
1246 zero
= instr
->op
== nir_op_f2b
?
1247 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1249 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1255 inst
= bld
.RNDZ(result
, op
[0]);
1256 inst
->saturate
= instr
->dest
.saturate
;
1259 case nir_op_fceil
: {
1260 op
[0].negate
= !op
[0].negate
;
1261 fs_reg temp
= vgrf(glsl_type::float_type
);
1262 bld
.RNDD(temp
, op
[0]);
1264 inst
= bld
.MOV(result
, temp
);
1265 inst
->saturate
= instr
->dest
.saturate
;
1269 inst
= bld
.RNDD(result
, op
[0]);
1270 inst
->saturate
= instr
->dest
.saturate
;
1273 inst
= bld
.FRC(result
, op
[0]);
1274 inst
->saturate
= instr
->dest
.saturate
;
1276 case nir_op_fround_even
:
1277 inst
= bld
.RNDE(result
, op
[0]);
1278 inst
->saturate
= instr
->dest
.saturate
;
1281 case nir_op_fquantize2f16
: {
1282 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1283 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1284 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1286 /* The destination stride must be at least as big as the source stride. */
1287 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1290 /* Check for denormal */
1291 fs_reg abs_src0
= op
[0];
1292 abs_src0
.abs
= true;
1293 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1295 /* Get the appropriately signed zero */
1296 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1297 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1298 brw_imm_ud(0x80000000));
1299 /* Do the actual F32 -> F16 -> F32 conversion */
1300 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1301 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1302 /* Select that or zero based on normal status */
1303 inst
= bld
.SEL(result
, zero
, tmp32
);
1304 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1305 inst
->saturate
= instr
->dest
.saturate
;
1312 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1313 inst
->saturate
= instr
->dest
.saturate
;
1319 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1320 inst
->saturate
= instr
->dest
.saturate
;
1323 case nir_op_pack_snorm_2x16
:
1324 case nir_op_pack_snorm_4x8
:
1325 case nir_op_pack_unorm_2x16
:
1326 case nir_op_pack_unorm_4x8
:
1327 case nir_op_unpack_snorm_2x16
:
1328 case nir_op_unpack_snorm_4x8
:
1329 case nir_op_unpack_unorm_2x16
:
1330 case nir_op_unpack_unorm_4x8
:
1331 case nir_op_unpack_half_2x16
:
1332 case nir_op_pack_half_2x16
:
1333 unreachable("not reached: should be handled by lower_packing_builtins");
1335 case nir_op_unpack_half_2x16_split_x
:
1336 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1337 inst
->saturate
= instr
->dest
.saturate
;
1339 case nir_op_unpack_half_2x16_split_y
:
1340 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1341 inst
->saturate
= instr
->dest
.saturate
;
1344 case nir_op_pack_64_2x32_split
:
1345 case nir_op_pack_32_2x16_split
:
1346 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1349 case nir_op_unpack_64_2x32_split_x
:
1350 case nir_op_unpack_64_2x32_split_y
: {
1351 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1352 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1354 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1358 case nir_op_unpack_32_2x16_split_x
:
1359 case nir_op_unpack_32_2x16_split_y
: {
1360 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1361 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1363 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1368 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1369 inst
->saturate
= instr
->dest
.saturate
;
1372 case nir_op_bitfield_reverse
:
1373 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1374 bld
.BFREV(result
, op
[0]);
1377 case nir_op_bit_count
:
1378 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1379 bld
.CBIT(result
, op
[0]);
1382 case nir_op_ufind_msb
: {
1383 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1384 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1388 case nir_op_ifind_msb
: {
1389 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1391 if (devinfo
->gen
< 7) {
1392 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1394 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1396 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1397 * count from the LSB side. If FBH didn't return an error
1398 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1399 * count into an LSB count.
1401 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1403 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1404 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1405 inst
->src
[0].negate
= true;
1410 case nir_op_find_lsb
:
1411 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1413 if (devinfo
->gen
< 7) {
1414 fs_reg temp
= vgrf(glsl_type::int_type
);
1416 /* (x & -x) generates a value that consists of only the LSB of x.
1417 * For all powers of 2, findMSB(y) == findLSB(y).
1419 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1420 fs_reg negated_src
= src
;
1422 /* One must be negated, and the other must be non-negated. It
1423 * doesn't matter which is which.
1425 negated_src
.negate
= true;
1428 bld
.AND(temp
, src
, negated_src
);
1429 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1431 bld
.FBL(result
, op
[0]);
1435 case nir_op_ubitfield_extract
:
1436 case nir_op_ibitfield_extract
:
1437 unreachable("should have been lowered");
1440 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1441 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1444 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1445 bld
.BFI1(result
, op
[0], op
[1]);
1448 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1449 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1452 case nir_op_bitfield_insert
:
1453 unreachable("not reached: should have been lowered");
1458 fs_reg shift_count
= op
[1];
1460 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1461 if (op
[1].file
== VGRF
&&
1462 (result
.type
== BRW_REGISTER_TYPE_Q
||
1463 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1464 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1465 BRW_REGISTER_TYPE_UD
);
1466 shift_count
.stride
= 2;
1467 bld
.MOV(shift_count
, op
[1]);
1471 switch (instr
->op
) {
1473 bld
.SHL(result
, op
[0], shift_count
);
1476 bld
.ASR(result
, op
[0], shift_count
);
1479 bld
.SHR(result
, op
[0], shift_count
);
1482 unreachable("not reached");
1487 case nir_op_pack_half_2x16_split
:
1488 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1492 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1493 inst
->saturate
= instr
->dest
.saturate
;
1497 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1498 inst
->saturate
= instr
->dest
.saturate
;
1502 if (optimize_frontfacing_ternary(instr
, result
))
1505 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1506 inst
= bld
.SEL(result
, op
[1], op
[2]);
1507 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1510 case nir_op_extract_u8
:
1511 case nir_op_extract_i8
: {
1512 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1517 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1518 * Use two instructions and a word or DWord intermediate integer type.
1520 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1521 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1523 if (instr
->op
== nir_op_extract_i8
) {
1524 /* If we need to sign extend, extract to a word first */
1525 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1526 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1527 bld
.MOV(result
, w_temp
);
1529 /* Otherwise use an AND with 0xff and a word type */
1530 bld
.AND(result
, subscript(op
[0], type
, byte
/ 2), brw_imm_uw(0xff));
1533 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1534 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1539 case nir_op_extract_u16
:
1540 case nir_op_extract_i16
: {
1541 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1542 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1543 bld
.MOV(result
, subscript(op
[0], type
, word
));
1548 unreachable("unhandled instruction");
1551 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1552 * to sign extend the low bit to 0/~0
1554 if (devinfo
->gen
<= 5 &&
1555 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1556 fs_reg masked
= vgrf(glsl_type::int_type
);
1557 bld
.AND(masked
, result
, brw_imm_d(1));
1558 masked
.negate
= true;
1559 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1564 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1565 nir_load_const_instr
*instr
)
1567 const brw_reg_type reg_type
=
1568 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1569 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1571 switch (instr
->def
.bit_size
) {
1573 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1574 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1578 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1579 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1583 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1584 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1588 assert(devinfo
->gen
>= 7);
1589 if (devinfo
->gen
== 7) {
1590 /* We don't get 64-bit integer types until gen8 */
1591 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1592 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1593 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1596 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1597 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1602 unreachable("Invalid bit size");
1605 nir_ssa_values
[instr
->def
.index
] = reg
;
1609 fs_visitor::get_nir_src(const nir_src
&src
)
1613 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1614 const brw_reg_type reg_type
=
1615 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1616 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1618 reg
= nir_ssa_values
[src
.ssa
->index
];
1621 /* We don't handle indirects on locals */
1622 assert(src
.reg
.indirect
== NULL
);
1623 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1624 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1627 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1628 /* The only 64-bit type available on gen7 is DF, so use that. */
1629 reg
.type
= BRW_REGISTER_TYPE_DF
;
1631 /* To avoid floating-point denorm flushing problems, set the type by
1632 * default to an integer type - instructions that need floating point
1633 * semantics will set this to F if they need to
1635 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1636 BRW_REGISTER_TYPE_D
);
1643 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1645 * This function should not be called on any value which may be 64 bits.
1646 * We could theoretically support 64-bit on gen8+ but we choose not to
1647 * because it wouldn't work in general (no gen7 support) and there are
1648 * enough restrictions in 64-bit immediates that you can't take the return
1649 * value and treat it the same as the result of get_nir_src().
1652 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1654 assert(nir_src_bit_size(src
) == 32);
1655 return nir_src_is_const(src
) ?
1656 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1660 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1663 const brw_reg_type reg_type
=
1664 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1665 dest
.ssa
.bit_size
== 8 ?
1666 BRW_REGISTER_TYPE_D
:
1667 BRW_REGISTER_TYPE_F
);
1668 nir_ssa_values
[dest
.ssa
.index
] =
1669 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1670 return nir_ssa_values
[dest
.ssa
.index
];
1672 /* We don't handle indirects on locals */
1673 assert(dest
.reg
.indirect
== NULL
);
1674 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1675 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1680 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1683 for (unsigned i
= 0; i
< 4; i
++) {
1684 if (!((wr_mask
>> i
) & 1))
1687 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1688 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1689 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1690 if (new_inst
->src
[j
].file
== VGRF
)
1691 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1698 emit_pixel_interpolater_send(const fs_builder
&bld
,
1703 glsl_interp_mode interpolation
)
1705 struct brw_wm_prog_data
*wm_prog_data
=
1706 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1708 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1709 /* 2 floats per slot returned */
1710 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1711 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1713 wm_prog_data
->pulls_bary
= true;
1719 * Computes 1 << x, given a D/UD register containing some value x.
1722 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1724 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1726 fs_reg result
= bld
.vgrf(x
.type
, 1);
1727 fs_reg one
= bld
.vgrf(x
.type
, 1);
1729 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1730 bld
.SHL(result
, one
, x
);
1735 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1737 assert(stage
== MESA_SHADER_GEOMETRY
);
1739 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1741 if (gs_compile
->control_data_header_size_bits
== 0)
1744 /* We can only do EndPrimitive() functionality when the control data
1745 * consists of cut bits. Fortunately, the only time it isn't is when the
1746 * output type is points, in which case EndPrimitive() is a no-op.
1748 if (gs_prog_data
->control_data_format
!=
1749 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1753 /* Cut bits use one bit per vertex. */
1754 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1756 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1757 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1759 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1760 * vertex n, 0 otherwise. So all we need to do here is mark bit
1761 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1762 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1763 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1765 * Note that if EndPrimitive() is called before emitting any vertices, this
1766 * will cause us to set bit 31 of the control_data_bits register to 1.
1767 * That's fine because:
1769 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1770 * output, so the hardware will ignore cut bit 31.
1772 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1773 * last vertex, so setting cut bit 31 has no effect (since the primitive
1774 * is automatically ended when the GS terminates).
1776 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1777 * control_data_bits register to 0 when the first vertex is emitted.
1780 const fs_builder abld
= bld
.annotate("end primitive");
1782 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1783 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1784 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1785 fs_reg mask
= intexp2(abld
, prev_count
);
1786 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1787 * attention to the lower 5 bits of its second source argument, so on this
1788 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1789 * ((vertex_count - 1) % 32).
1791 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1795 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1797 assert(stage
== MESA_SHADER_GEOMETRY
);
1798 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1800 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1802 const fs_builder abld
= bld
.annotate("emit control data bits");
1803 const fs_builder fwa_bld
= bld
.exec_all();
1805 /* We use a single UD register to accumulate control data bits (32 bits
1806 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1809 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1810 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1811 * use the Channel Mask phase to enable/disable which DWord within that
1812 * group to write. (Remember, different SIMD8 channels may have emitted
1813 * different numbers of vertices, so we may need per-slot offsets.)
1815 * Channel masking presents an annoying problem: we may have to replicate
1816 * the data up to 4 times:
1818 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1820 * To avoid penalizing shaders that emit a small number of vertices, we
1821 * can avoid these sometimes: if the size of the control data header is
1822 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1823 * land in the same 128-bit group, so we can skip per-slot offsets.
1825 * Similarly, if the control data header is <= 32 bits, there is only one
1826 * DWord, so we can skip channel masks.
1828 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1830 fs_reg channel_mask
, per_slot_offset
;
1832 if (gs_compile
->control_data_header_size_bits
> 32) {
1833 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1834 channel_mask
= vgrf(glsl_type::uint_type
);
1837 if (gs_compile
->control_data_header_size_bits
> 128) {
1838 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1839 per_slot_offset
= vgrf(glsl_type::uint_type
);
1842 /* Figure out which DWord we're trying to write to using the formula:
1844 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1846 * Since bits_per_vertex is a power of two, and is known at compile
1847 * time, this can be optimized to:
1849 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1851 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1852 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1853 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1854 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1855 unsigned log2_bits_per_vertex
=
1856 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1857 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1859 if (per_slot_offset
.file
!= BAD_FILE
) {
1860 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1861 * the appropriate OWord within the control data header.
1863 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1866 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1867 * write to the appropriate DWORD within the OWORD.
1869 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1870 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1871 channel_mask
= intexp2(fwa_bld
, channel
);
1872 /* Then the channel masks need to be in bits 23:16. */
1873 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1876 /* Store the control data bits in the message payload and send it. */
1878 if (channel_mask
.file
!= BAD_FILE
)
1879 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1880 if (per_slot_offset
.file
!= BAD_FILE
)
1883 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1884 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1886 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1887 if (per_slot_offset
.file
!= BAD_FILE
)
1888 sources
[i
++] = per_slot_offset
;
1889 if (channel_mask
.file
!= BAD_FILE
)
1890 sources
[i
++] = channel_mask
;
1892 sources
[i
++] = this->control_data_bits
;
1895 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1896 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1898 /* We need to increment Global Offset by 256-bits to make room for
1899 * Broadwell's extra "Vertex Count" payload at the beginning of the
1900 * URB entry. Since this is an OWord message, Global Offset is counted
1901 * in 128-bit units, so we must set it to 2.
1903 if (gs_prog_data
->static_vertex_count
== -1)
1908 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1911 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1913 /* Note: we are calling this *before* increasing vertex_count, so
1914 * this->vertex_count == vertex_count - 1 in the formula above.
1917 /* Stream mode uses 2 bits per vertex */
1918 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1920 /* Must be a valid stream */
1921 assert(stream_id
< MAX_VERTEX_STREAMS
);
1923 /* Control data bits are initialized to 0 so we don't have to set any
1924 * bits when sending vertices to stream 0.
1929 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1931 /* reg::sid = stream_id */
1932 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1933 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1935 /* reg:shift_count = 2 * (vertex_count - 1) */
1936 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1937 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1939 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1940 * attention to the lower 5 bits of its second source argument, so on this
1941 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1942 * stream_id << ((2 * (vertex_count - 1)) % 32).
1944 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1945 abld
.SHL(mask
, sid
, shift_count
);
1946 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1950 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1953 assert(stage
== MESA_SHADER_GEOMETRY
);
1955 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1957 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1958 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1960 /* Haswell and later hardware ignores the "Render Stream Select" bits
1961 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1962 * and instead sends all primitives down the pipeline for rasterization.
1963 * If the SOL stage is enabled, "Render Stream Select" is honored and
1964 * primitives bound to non-zero streams are discarded after stream output.
1966 * Since the only purpose of primives sent to non-zero streams is to
1967 * be recorded by transform feedback, we can simply discard all geometry
1968 * bound to these streams when transform feedback is disabled.
1970 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1973 /* If we're outputting 32 control data bits or less, then we can wait
1974 * until the shader is over to output them all. Otherwise we need to
1975 * output them as we go. Now is the time to do it, since we're about to
1976 * output the vertex_count'th vertex, so it's guaranteed that the
1977 * control data bits associated with the (vertex_count - 1)th vertex are
1980 if (gs_compile
->control_data_header_size_bits
> 32) {
1981 const fs_builder abld
=
1982 bld
.annotate("emit vertex: emit control data bits");
1984 /* Only emit control data bits if we've finished accumulating a batch
1985 * of 32 bits. This is the case when:
1987 * (vertex_count * bits_per_vertex) % 32 == 0
1989 * (in other words, when the last 5 bits of vertex_count *
1990 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1991 * integer n (which is always the case, since bits_per_vertex is
1992 * always 1 or 2), this is equivalent to requiring that the last 5-n
1993 * bits of vertex_count are 0:
1995 * vertex_count & (2^(5-n) - 1) == 0
1997 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2000 * vertex_count & (32 / bits_per_vertex - 1) == 0
2002 * TODO: If vertex_count is an immediate, we could do some of this math
2003 * at compile time...
2006 abld
.AND(bld
.null_reg_d(), vertex_count
,
2007 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2008 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2010 abld
.IF(BRW_PREDICATE_NORMAL
);
2011 /* If vertex_count is 0, then no control data bits have been
2012 * accumulated yet, so we can skip emitting them.
2014 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2015 BRW_CONDITIONAL_NEQ
);
2016 abld
.IF(BRW_PREDICATE_NORMAL
);
2017 emit_gs_control_data_bits(vertex_count
);
2018 abld
.emit(BRW_OPCODE_ENDIF
);
2020 /* Reset control_data_bits to 0 so we can start accumulating a new
2023 * Note: in the case where vertex_count == 0, this neutralizes the
2024 * effect of any call to EndPrimitive() that the shader may have
2025 * made before outputting its first vertex.
2027 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2028 inst
->force_writemask_all
= true;
2029 abld
.emit(BRW_OPCODE_ENDIF
);
2032 emit_urb_writes(vertex_count
);
2034 /* In stream mode we have to set control data bits for all vertices
2035 * unless we have disabled control data bits completely (which we do
2036 * do for GL_POINTS outputs that don't use streams).
2038 if (gs_compile
->control_data_header_size_bits
> 0 &&
2039 gs_prog_data
->control_data_format
==
2040 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2041 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2046 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2047 const nir_src
&vertex_src
,
2048 unsigned base_offset
,
2049 const nir_src
&offset_src
,
2050 unsigned num_components
,
2051 unsigned first_component
)
2053 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2054 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2056 /* TODO: figure out push input layout for invocations == 1 */
2057 /* TODO: make this work with 64-bit inputs */
2058 if (gs_prog_data
->invocations
== 1 &&
2059 type_sz(dst
.type
) <= 4 &&
2060 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2061 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2062 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2063 nir_src_as_uint(vertex_src
) * push_reg_count
;
2064 for (unsigned i
= 0; i
< num_components
; i
++) {
2065 bld
.MOV(offset(dst
, bld
, i
),
2066 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2071 /* Resort to the pull model. Ensure the VUE handles are provided. */
2072 assert(gs_prog_data
->base
.include_vue_handles
);
2074 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2075 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2077 if (gs_prog_data
->invocations
== 1) {
2078 if (nir_src_is_const(vertex_src
)) {
2079 /* The vertex index is constant; just select the proper URB handle. */
2081 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2082 BRW_REGISTER_TYPE_UD
);
2084 /* The vertex index is non-constant. We need to use indirect
2085 * addressing to fetch the proper URB handle.
2087 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2088 * indicating that channel <n> should read the handle from
2089 * DWord <n>. We convert that to bytes by multiplying by 4.
2091 * Next, we convert the vertex index to bytes by multiplying
2092 * by 32 (shifting by 5), and add the two together. This is
2093 * the final indirect byte offset.
2095 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2096 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2097 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2098 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2100 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2101 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2102 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2103 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2104 /* Convert vertex_index to bytes (multiply by 32) */
2105 bld
.SHL(vertex_offset_bytes
,
2106 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2108 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2110 /* Use first_icp_handle as the base offset. There is one register
2111 * of URB handles per vertex, so inform the register allocator that
2112 * we might read up to nir->info.gs.vertices_in registers.
2114 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2115 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2116 fs_reg(icp_offset_bytes
),
2117 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2120 assert(gs_prog_data
->invocations
> 1);
2122 if (nir_src_is_const(vertex_src
)) {
2123 unsigned vertex
= nir_src_as_uint(vertex_src
);
2124 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2126 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2127 BRW_REGISTER_TYPE_UD
));
2129 /* The vertex index is non-constant. We need to use indirect
2130 * addressing to fetch the proper URB handle.
2133 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2135 /* Convert vertex_index to bytes (multiply by 4) */
2136 bld
.SHL(icp_offset_bytes
,
2137 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2140 /* Use first_icp_handle as the base offset. There is one DWord
2141 * of URB handles per vertex, so inform the register allocator that
2142 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2144 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2145 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2146 fs_reg(icp_offset_bytes
),
2147 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2154 fs_reg tmp_dst
= dst
;
2155 fs_reg indirect_offset
= get_nir_src(offset_src
);
2156 unsigned num_iterations
= 1;
2157 unsigned orig_num_components
= num_components
;
2159 if (type_sz(dst
.type
) == 8) {
2160 if (num_components
> 2) {
2164 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2166 first_component
= first_component
/ 2;
2169 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2170 if (nir_src_is_const(offset_src
)) {
2171 /* Constant indexing - use global offset. */
2172 if (first_component
!= 0) {
2173 unsigned read_components
= num_components
+ first_component
;
2174 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2175 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2176 inst
->size_written
= read_components
*
2177 tmp
.component_size(inst
->exec_size
);
2178 for (unsigned i
= 0; i
< num_components
; i
++) {
2179 bld
.MOV(offset(tmp_dst
, bld
, i
),
2180 offset(tmp
, bld
, i
+ first_component
));
2183 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2185 inst
->size_written
= num_components
*
2186 tmp_dst
.component_size(inst
->exec_size
);
2188 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2191 /* Indirect indexing - use per-slot offsets as well. */
2192 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2193 unsigned read_components
= num_components
+ first_component
;
2194 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2195 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2196 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2197 if (first_component
!= 0) {
2198 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2200 inst
->size_written
= read_components
*
2201 tmp
.component_size(inst
->exec_size
);
2202 for (unsigned i
= 0; i
< num_components
; i
++) {
2203 bld
.MOV(offset(tmp_dst
, bld
, i
),
2204 offset(tmp
, bld
, i
+ first_component
));
2207 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2209 inst
->size_written
= num_components
*
2210 tmp_dst
.component_size(inst
->exec_size
);
2212 inst
->offset
= base_offset
;
2216 if (type_sz(dst
.type
) == 8) {
2217 shuffle_from_32bit_read(bld
,
2218 offset(dst
, bld
, iter
* 2),
2219 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2224 if (num_iterations
> 1) {
2225 num_components
= orig_num_components
- 2;
2226 if(nir_src_is_const(offset_src
)) {
2229 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2230 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2231 indirect_offset
= new_indirect
;
2238 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2240 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2242 if (nir_src_is_const(*offset_src
)) {
2243 /* The only constant offset we should find is 0. brw_nir.c's
2244 * add_const_offset_to_base() will fold other constant offsets
2245 * into instr->const_index[0].
2247 assert(nir_src_as_uint(*offset_src
) == 0);
2251 return get_nir_src(*offset_src
);
2255 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2256 nir_intrinsic_instr
*instr
)
2258 assert(stage
== MESA_SHADER_VERTEX
);
2261 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2262 dest
= get_nir_dest(instr
->dest
);
2264 switch (instr
->intrinsic
) {
2265 case nir_intrinsic_load_vertex_id
:
2266 case nir_intrinsic_load_base_vertex
:
2267 unreachable("should be lowered by nir_lower_system_values()");
2269 case nir_intrinsic_load_input
: {
2270 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2271 unsigned first_component
= nir_intrinsic_component(instr
);
2272 unsigned num_components
= instr
->num_components
;
2274 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2276 if (type_sz(dest
.type
) == 8)
2277 first_component
/= 2;
2279 /* For 16-bit support maybe a temporary will be needed to copy from
2282 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2283 first_component
, num_components
);
2287 case nir_intrinsic_load_vertex_id_zero_base
:
2288 case nir_intrinsic_load_instance_id
:
2289 case nir_intrinsic_load_base_instance
:
2290 case nir_intrinsic_load_draw_id
:
2291 case nir_intrinsic_load_first_vertex
:
2292 case nir_intrinsic_load_is_indexed_draw
:
2293 unreachable("lowered by brw_nir_lower_vs_inputs");
2296 nir_emit_intrinsic(bld
, instr
);
2302 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2303 nir_intrinsic_instr
*instr
)
2305 assert(stage
== MESA_SHADER_TESS_CTRL
);
2306 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2307 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2310 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2311 dst
= get_nir_dest(instr
->dest
);
2313 switch (instr
->intrinsic
) {
2314 case nir_intrinsic_load_primitive_id
:
2315 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2317 case nir_intrinsic_load_invocation_id
:
2318 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2320 case nir_intrinsic_load_patch_vertices_in
:
2321 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2322 brw_imm_d(tcs_key
->input_vertices
));
2325 case nir_intrinsic_barrier
: {
2326 if (tcs_prog_data
->instances
== 1)
2329 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2330 fs_reg m0_2
= component(m0
, 2);
2332 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2334 /* Zero the message header */
2335 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2337 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2338 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2339 brw_imm_ud(INTEL_MASK(16, 13)));
2341 /* Shift it up to bits 27:24. */
2342 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2344 /* Set the Barrier Count and the enable bit */
2345 chanbld
.OR(m0_2
, m0_2
,
2346 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2348 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2352 case nir_intrinsic_load_input
:
2353 unreachable("nir_lower_io should never give us these.");
2356 case nir_intrinsic_load_per_vertex_input
: {
2357 fs_reg indirect_offset
= get_indirect_offset(instr
);
2358 unsigned imm_offset
= instr
->const_index
[0];
2360 const nir_src
&vertex_src
= instr
->src
[0];
2366 if (nir_src_is_const(vertex_src
)) {
2367 /* Emit a MOV to resolve <0,1,0> regioning. */
2368 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2369 unsigned vertex
= nir_src_as_uint(vertex_src
);
2371 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2372 BRW_REGISTER_TYPE_UD
));
2373 } else if (tcs_prog_data
->instances
== 1 &&
2374 vertex_src
.is_ssa
&&
2375 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2376 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2377 /* For the common case of only 1 instance, an array index of
2378 * gl_InvocationID means reading g1. Skip all the indirect work.
2380 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2382 /* The vertex index is non-constant. We need to use indirect
2383 * addressing to fetch the proper URB handle.
2385 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2387 /* Each ICP handle is a single DWord (4 bytes) */
2388 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2389 bld
.SHL(vertex_offset_bytes
,
2390 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2393 /* Start at g1. We might read up to 4 registers. */
2394 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2395 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2396 brw_imm_ud(4 * REG_SIZE
));
2399 /* We can only read two double components with each URB read, so
2400 * we send two read messages in that case, each one loading up to
2401 * two double components.
2403 unsigned num_iterations
= 1;
2404 unsigned num_components
= instr
->num_components
;
2405 unsigned first_component
= nir_intrinsic_component(instr
);
2406 fs_reg orig_dst
= dst
;
2407 if (type_sz(dst
.type
) == 8) {
2408 first_component
= first_component
/ 2;
2409 if (instr
->num_components
> 2) {
2414 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2418 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2419 if (indirect_offset
.file
== BAD_FILE
) {
2420 /* Constant indexing - use global offset. */
2421 if (first_component
!= 0) {
2422 unsigned read_components
= num_components
+ first_component
;
2423 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2424 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2425 for (unsigned i
= 0; i
< num_components
; i
++) {
2426 bld
.MOV(offset(dst
, bld
, i
),
2427 offset(tmp
, bld
, i
+ first_component
));
2430 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2432 inst
->offset
= imm_offset
;
2435 /* Indirect indexing - use per-slot offsets as well. */
2436 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2437 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2438 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2439 if (first_component
!= 0) {
2440 unsigned read_components
= num_components
+ first_component
;
2441 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2442 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2444 for (unsigned i
= 0; i
< num_components
; i
++) {
2445 bld
.MOV(offset(dst
, bld
, i
),
2446 offset(tmp
, bld
, i
+ first_component
));
2449 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2452 inst
->offset
= imm_offset
;
2455 inst
->size_written
= (num_components
+ first_component
) *
2456 inst
->dst
.component_size(inst
->exec_size
);
2458 /* If we are reading 64-bit data using 32-bit read messages we need
2459 * build proper 64-bit data elements by shuffling the low and high
2460 * 32-bit components around like we do for other things like UBOs
2463 if (type_sz(dst
.type
) == 8) {
2464 shuffle_from_32bit_read(bld
,
2465 offset(orig_dst
, bld
, iter
* 2),
2466 retype(dst
, BRW_REGISTER_TYPE_D
),
2470 /* Copy the temporary to the destination to deal with writemasking.
2472 * Also attempt to deal with gl_PointSize being in the .w component.
2474 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2475 assert(type_sz(dst
.type
) < 8);
2476 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2477 inst
->size_written
= 4 * REG_SIZE
;
2478 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2481 /* If we are loading double data and we need a second read message
2482 * adjust the write offset
2484 if (num_iterations
> 1) {
2485 num_components
= instr
->num_components
- 2;
2492 case nir_intrinsic_load_output
:
2493 case nir_intrinsic_load_per_vertex_output
: {
2494 fs_reg indirect_offset
= get_indirect_offset(instr
);
2495 unsigned imm_offset
= instr
->const_index
[0];
2496 unsigned first_component
= nir_intrinsic_component(instr
);
2499 if (indirect_offset
.file
== BAD_FILE
) {
2500 /* Replicate the patch handle to all enabled channels */
2501 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2502 bld
.MOV(patch_handle
,
2503 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2506 if (first_component
!= 0) {
2507 unsigned read_components
=
2508 instr
->num_components
+ first_component
;
2509 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2510 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2512 inst
->size_written
= read_components
* REG_SIZE
;
2513 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2514 bld
.MOV(offset(dst
, bld
, i
),
2515 offset(tmp
, bld
, i
+ first_component
));
2518 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2520 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2522 inst
->offset
= imm_offset
;
2526 /* Indirect indexing - use per-slot offsets as well. */
2527 const fs_reg srcs
[] = {
2528 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2531 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2532 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2533 if (first_component
!= 0) {
2534 unsigned read_components
=
2535 instr
->num_components
+ first_component
;
2536 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2537 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2539 inst
->size_written
= read_components
* REG_SIZE
;
2540 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2541 bld
.MOV(offset(dst
, bld
, i
),
2542 offset(tmp
, bld
, i
+ first_component
));
2545 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2547 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2549 inst
->offset
= imm_offset
;
2555 case nir_intrinsic_store_output
:
2556 case nir_intrinsic_store_per_vertex_output
: {
2557 fs_reg value
= get_nir_src(instr
->src
[0]);
2558 bool is_64bit
= (instr
->src
[0].is_ssa
?
2559 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2560 fs_reg indirect_offset
= get_indirect_offset(instr
);
2561 unsigned imm_offset
= instr
->const_index
[0];
2562 unsigned mask
= instr
->const_index
[1];
2563 unsigned header_regs
= 0;
2565 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2567 if (indirect_offset
.file
!= BAD_FILE
) {
2568 srcs
[header_regs
++] = indirect_offset
;
2574 unsigned num_components
= util_last_bit(mask
);
2577 /* We can only pack two 64-bit components in a single message, so send
2578 * 2 messages if we have more components
2580 unsigned num_iterations
= 1;
2581 unsigned iter_components
= num_components
;
2582 unsigned first_component
= nir_intrinsic_component(instr
);
2584 first_component
= first_component
/ 2;
2585 if (instr
->num_components
> 2) {
2587 iter_components
= 2;
2591 mask
= mask
<< first_component
;
2593 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2594 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2595 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2596 opcode
= indirect_offset
.file
!= BAD_FILE
?
2597 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2598 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2599 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2600 /* Expand the 64-bit mask to 32-bit channels. We only handle
2601 * two channels in each iteration, so we only care about X/Y.
2603 unsigned mask32
= 0;
2604 if (mask
& WRITEMASK_X
)
2605 mask32
|= WRITEMASK_XY
;
2606 if (mask
& WRITEMASK_Y
)
2607 mask32
|= WRITEMASK_ZW
;
2609 /* If the mask does not include any of the channels X or Y there
2610 * is nothing to do in this iteration. Move on to the next couple
2611 * of 64-bit channels.
2619 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2620 opcode
= indirect_offset
.file
!= BAD_FILE
?
2621 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2622 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2624 opcode
= indirect_offset
.file
!= BAD_FILE
?
2625 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2626 SHADER_OPCODE_URB_WRITE_SIMD8
;
2629 for (unsigned i
= 0; i
< iter_components
; i
++) {
2630 if (!(mask
& (1 << (i
+ first_component
))))
2634 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2636 /* We need to shuffle the 64-bit data to match the layout
2637 * expected by our 32-bit URB write messages. We use a temporary
2640 unsigned channel
= iter
* 2 + i
;
2641 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2643 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2644 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2645 offset(dest
, bld
, 1);
2650 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2651 (is_64bit
? 2 * first_component
: first_component
);
2653 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2654 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2656 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2657 inst
->offset
= imm_offset
;
2660 /* If this is a 64-bit attribute, select the next two 64-bit channels
2661 * to be handled in the next iteration.
2672 nir_emit_intrinsic(bld
, instr
);
2678 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2679 nir_intrinsic_instr
*instr
)
2681 assert(stage
== MESA_SHADER_TESS_EVAL
);
2682 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2685 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2686 dest
= get_nir_dest(instr
->dest
);
2688 switch (instr
->intrinsic
) {
2689 case nir_intrinsic_load_primitive_id
:
2690 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2692 case nir_intrinsic_load_tess_coord
:
2693 /* gl_TessCoord is part of the payload in g1-3 */
2694 for (unsigned i
= 0; i
< 3; i
++) {
2695 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2699 case nir_intrinsic_load_input
:
2700 case nir_intrinsic_load_per_vertex_input
: {
2701 fs_reg indirect_offset
= get_indirect_offset(instr
);
2702 unsigned imm_offset
= instr
->const_index
[0];
2703 unsigned first_component
= nir_intrinsic_component(instr
);
2705 if (type_sz(dest
.type
) == 8) {
2706 first_component
= first_component
/ 2;
2710 if (indirect_offset
.file
== BAD_FILE
) {
2711 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2712 * which is 16 registers (since each holds 2 vec4 slots).
2714 unsigned slot_count
= 1;
2715 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2718 const unsigned max_push_slots
= 32;
2719 if (imm_offset
+ slot_count
<= max_push_slots
) {
2720 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2721 for (int i
= 0; i
< instr
->num_components
; i
++) {
2722 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2723 i
+ first_component
;
2724 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2727 tes_prog_data
->base
.urb_read_length
=
2728 MAX2(tes_prog_data
->base
.urb_read_length
,
2729 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2731 /* Replicate the patch handle to all enabled channels */
2732 const fs_reg srcs
[] = {
2733 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2735 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2736 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2738 if (first_component
!= 0) {
2739 unsigned read_components
=
2740 instr
->num_components
+ first_component
;
2741 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2742 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2744 inst
->size_written
= read_components
* REG_SIZE
;
2745 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2746 bld
.MOV(offset(dest
, bld
, i
),
2747 offset(tmp
, bld
, i
+ first_component
));
2750 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2752 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2755 inst
->offset
= imm_offset
;
2758 /* Indirect indexing - use per-slot offsets as well. */
2760 /* We can only read two double components with each URB read, so
2761 * we send two read messages in that case, each one loading up to
2762 * two double components.
2764 unsigned num_iterations
= 1;
2765 unsigned num_components
= instr
->num_components
;
2766 fs_reg orig_dest
= dest
;
2767 if (type_sz(dest
.type
) == 8) {
2768 if (instr
->num_components
> 2) {
2772 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2776 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2777 const fs_reg srcs
[] = {
2778 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2781 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2782 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2784 if (first_component
!= 0) {
2785 unsigned read_components
=
2786 num_components
+ first_component
;
2787 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2788 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2790 for (unsigned i
= 0; i
< num_components
; i
++) {
2791 bld
.MOV(offset(dest
, bld
, i
),
2792 offset(tmp
, bld
, i
+ first_component
));
2795 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2799 inst
->offset
= imm_offset
;
2800 inst
->size_written
= (num_components
+ first_component
) *
2801 inst
->dst
.component_size(inst
->exec_size
);
2803 /* If we are reading 64-bit data using 32-bit read messages we need
2804 * build proper 64-bit data elements by shuffling the low and high
2805 * 32-bit components around like we do for other things like UBOs
2808 if (type_sz(dest
.type
) == 8) {
2809 shuffle_from_32bit_read(bld
,
2810 offset(orig_dest
, bld
, iter
* 2),
2811 retype(dest
, BRW_REGISTER_TYPE_D
),
2815 /* If we are loading double data and we need a second read message
2818 if (num_iterations
> 1) {
2819 num_components
= instr
->num_components
- 2;
2827 nir_emit_intrinsic(bld
, instr
);
2833 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2834 nir_intrinsic_instr
*instr
)
2836 assert(stage
== MESA_SHADER_GEOMETRY
);
2837 fs_reg indirect_offset
;
2840 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2841 dest
= get_nir_dest(instr
->dest
);
2843 switch (instr
->intrinsic
) {
2844 case nir_intrinsic_load_primitive_id
:
2845 assert(stage
== MESA_SHADER_GEOMETRY
);
2846 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2847 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2848 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2851 case nir_intrinsic_load_input
:
2852 unreachable("load_input intrinsics are invalid for the GS stage");
2854 case nir_intrinsic_load_per_vertex_input
:
2855 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2856 instr
->src
[1], instr
->num_components
,
2857 nir_intrinsic_component(instr
));
2860 case nir_intrinsic_emit_vertex_with_counter
:
2861 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2864 case nir_intrinsic_end_primitive_with_counter
:
2865 emit_gs_end_primitive(instr
->src
[0]);
2868 case nir_intrinsic_set_vertex_count
:
2869 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2872 case nir_intrinsic_load_invocation_id
: {
2873 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2874 assert(val
.file
!= BAD_FILE
);
2875 dest
.type
= val
.type
;
2881 nir_emit_intrinsic(bld
, instr
);
2887 * Fetch the current render target layer index.
2890 fetch_render_target_array_index(const fs_builder
&bld
)
2892 if (bld
.shader
->devinfo
->gen
>= 6) {
2893 /* The render target array index is provided in the thread payload as
2894 * bits 26:16 of r0.0.
2896 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2897 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2901 /* Pre-SNB we only ever render into the first layer of the framebuffer
2902 * since layered rendering is not implemented.
2904 return brw_imm_ud(0);
2909 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2910 * framebuffer at the current fragment coordinates and sample index.
2913 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2916 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2918 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2919 const brw_wm_prog_key
*wm_key
=
2920 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2921 assert(!wm_key
->coherent_fb_fetch
);
2922 const struct brw_wm_prog_data
*wm_prog_data
=
2923 brw_wm_prog_data(stage_prog_data
);
2925 /* Calculate the surface index relative to the start of the texture binding
2926 * table block, since that's what the texturing messages expect.
2928 const unsigned surface
= target
+
2929 wm_prog_data
->binding_table
.render_target_read_start
-
2930 wm_prog_data
->base
.binding_table
.texture_start
;
2932 brw_mark_surface_used(
2933 bld
.shader
->stage_prog_data
,
2934 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2936 /* Calculate the fragment coordinates. */
2937 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2938 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2939 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2940 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2942 /* Calculate the sample index and MCS payload when multisampling. Luckily
2943 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2944 * shouldn't be necessary to recompile based on whether the framebuffer is
2947 if (wm_key
->multisample_fbo
&&
2948 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2949 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2951 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2952 const fs_reg mcs
= wm_key
->multisample_fbo
?
2953 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2955 /* Use either a normal or a CMS texel fetch message depending on whether
2956 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2957 * message just in case the framebuffer uses 16x multisampling, it should
2958 * be equivalent to the normal CMS fetch for lower multisampling modes.
2960 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2961 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2962 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2964 /* Emit the instruction. */
2965 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
2967 brw_imm_ud(surface
), brw_imm_ud(0),
2968 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
2969 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
2971 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
2972 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2978 * Actual coherent framebuffer read implemented using the native render target
2979 * read message. Requires SKL+.
2982 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
2984 assert(bld
.shader
->devinfo
->gen
>= 9);
2985 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
2986 inst
->target
= target
;
2987 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2993 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
2995 if (n
&& regs
[0].file
!= BAD_FILE
) {
2999 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3001 for (unsigned i
= 0; i
< n
; i
++)
3009 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3011 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3012 const brw_wm_prog_key
*const key
=
3013 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3014 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3015 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3017 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3018 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3020 else if (l
== FRAG_RESULT_COLOR
)
3021 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3022 MAX2(key
->nr_color_regions
, 1));
3024 else if (l
== FRAG_RESULT_DEPTH
)
3025 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3027 else if (l
== FRAG_RESULT_STENCIL
)
3028 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3030 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3031 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3033 else if (l
>= FRAG_RESULT_DATA0
&&
3034 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3035 return alloc_temporary(v
->bld
, 4,
3036 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3039 unreachable("Invalid location");
3043 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3044 nir_intrinsic_instr
*instr
)
3046 assert(stage
== MESA_SHADER_FRAGMENT
);
3049 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3050 dest
= get_nir_dest(instr
->dest
);
3052 switch (instr
->intrinsic
) {
3053 case nir_intrinsic_load_front_face
:
3054 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3055 *emit_frontfacing_interpolation());
3058 case nir_intrinsic_load_sample_pos
: {
3059 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3060 assert(sample_pos
.file
!= BAD_FILE
);
3061 dest
.type
= sample_pos
.type
;
3062 bld
.MOV(dest
, sample_pos
);
3063 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3067 case nir_intrinsic_load_layer_id
:
3068 dest
.type
= BRW_REGISTER_TYPE_UD
;
3069 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3072 case nir_intrinsic_load_helper_invocation
:
3073 case nir_intrinsic_load_sample_mask_in
:
3074 case nir_intrinsic_load_sample_id
: {
3075 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3076 fs_reg val
= nir_system_values
[sv
];
3077 assert(val
.file
!= BAD_FILE
);
3078 dest
.type
= val
.type
;
3083 case nir_intrinsic_store_output
: {
3084 const fs_reg src
= get_nir_src(instr
->src
[0]);
3085 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3086 const unsigned location
= nir_intrinsic_base(instr
) +
3087 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3088 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3091 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3092 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3093 offset(src
, bld
, j
));
3098 case nir_intrinsic_load_output
: {
3099 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3100 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3101 assert(l
>= FRAG_RESULT_DATA0
);
3102 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3103 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3104 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3106 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3107 emit_coherent_fb_read(bld
, tmp
, target
);
3109 emit_non_coherent_fb_read(bld
, tmp
, target
);
3111 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3112 bld
.MOV(offset(dest
, bld
, j
),
3113 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3119 case nir_intrinsic_discard
:
3120 case nir_intrinsic_discard_if
: {
3121 /* We track our discarded pixels in f0.1. By predicating on it, we can
3122 * update just the flag bits that aren't yet discarded. If there's no
3123 * condition, we emit a CMP of g0 != g0, so all currently executing
3124 * channels will get turned off.
3127 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3128 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3129 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3131 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3132 BRW_REGISTER_TYPE_UW
));
3133 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3135 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3136 cmp
->flag_subreg
= 1;
3138 if (devinfo
->gen
>= 6) {
3139 emit_discard_jump();
3142 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3146 case nir_intrinsic_load_input
: {
3147 /* load_input is only used for flat inputs */
3148 unsigned base
= nir_intrinsic_base(instr
);
3149 unsigned comp
= nir_intrinsic_component(instr
);
3150 unsigned num_components
= instr
->num_components
;
3151 fs_reg orig_dest
= dest
;
3152 enum brw_reg_type type
= dest
.type
;
3154 /* Special case fields in the VUE header */
3155 if (base
== VARYING_SLOT_LAYER
)
3157 else if (base
== VARYING_SLOT_VIEWPORT
)
3160 if (nir_dest_bit_size(instr
->dest
) == 64) {
3161 /* const_index is in 32-bit type size units that could not be aligned
3162 * with DF. We need to read the double vector as if it was a float
3163 * vector of twice the number of components to fetch the right data.
3165 type
= BRW_REGISTER_TYPE_F
;
3166 num_components
*= 2;
3167 dest
= bld
.vgrf(type
, num_components
);
3170 for (unsigned int i
= 0; i
< num_components
; i
++) {
3171 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3172 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3175 if (nir_dest_bit_size(instr
->dest
) == 64) {
3176 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3177 instr
->num_components
);
3182 case nir_intrinsic_load_barycentric_pixel
:
3183 case nir_intrinsic_load_barycentric_centroid
:
3184 case nir_intrinsic_load_barycentric_sample
:
3185 /* Do nothing - load_interpolated_input handling will handle it later. */
3188 case nir_intrinsic_load_barycentric_at_sample
: {
3189 const glsl_interp_mode interpolation
=
3190 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3192 if (nir_src_is_const(instr
->src
[0])) {
3193 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3195 emit_pixel_interpolater_send(bld
,
3196 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3199 brw_imm_ud(msg_data
),
3202 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3203 BRW_REGISTER_TYPE_UD
);
3205 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3206 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3207 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3208 bld
.exec_all().group(1, 0)
3209 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3210 emit_pixel_interpolater_send(bld
,
3211 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3217 /* Make a loop that sends a message to the pixel interpolater
3218 * for the sample number in each live channel. If there are
3219 * multiple channels with the same sample number then these
3220 * will be handled simultaneously with a single interation of
3223 bld
.emit(BRW_OPCODE_DO
);
3225 /* Get the next live sample number into sample_id_reg */
3226 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3228 /* Set the flag register so that we can perform the send
3229 * message on all channels that have the same sample number
3231 bld
.CMP(bld
.null_reg_ud(),
3232 sample_src
, sample_id
,
3233 BRW_CONDITIONAL_EQ
);
3234 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3235 bld
.exec_all().group(1, 0)
3236 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3238 emit_pixel_interpolater_send(bld
,
3239 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3242 component(msg_data
, 0),
3244 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3246 /* Continue the loop if there are any live channels left */
3247 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3249 bld
.emit(BRW_OPCODE_WHILE
));
3255 case nir_intrinsic_load_barycentric_at_offset
: {
3256 const glsl_interp_mode interpolation
=
3257 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3259 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3262 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3263 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3264 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3266 emit_pixel_interpolater_send(bld
,
3267 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3270 brw_imm_ud(off_x
| (off_y
<< 4)),
3273 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3274 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3275 BRW_REGISTER_TYPE_F
);
3276 for (int i
= 0; i
< 2; i
++) {
3277 fs_reg temp
= vgrf(glsl_type::float_type
);
3278 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3279 fs_reg itemp
= vgrf(glsl_type::int_type
);
3281 bld
.MOV(itemp
, temp
);
3283 /* Clamp the upper end of the range to +7/16.
3284 * ARB_gpu_shader5 requires that we support a maximum offset
3285 * of +0.5, which isn't representable in a S0.4 value -- if
3286 * we didn't clamp it, we'd end up with -8/16, which is the
3287 * opposite of what the shader author wanted.
3289 * This is legal due to ARB_gpu_shader5's quantization
3292 * "Not all values of <offset> may be supported; x and y
3293 * offsets may be rounded to fixed-point values with the
3294 * number of fraction bits given by the
3295 * implementation-dependent constant
3296 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3298 set_condmod(BRW_CONDITIONAL_L
,
3299 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3302 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3303 emit_pixel_interpolater_send(bld
,
3313 case nir_intrinsic_load_interpolated_input
: {
3314 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3315 emit_fragcoord_interpolation(dest
);
3319 assert(instr
->src
[0].ssa
&&
3320 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3321 nir_intrinsic_instr
*bary_intrinsic
=
3322 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3323 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3324 enum glsl_interp_mode interp_mode
=
3325 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3328 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3329 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3330 /* Use the result of the PI message */
3331 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3333 /* Use the delta_xy values computed from the payload */
3334 enum brw_barycentric_mode bary
=
3335 brw_barycentric_mode(interp_mode
, bary_intrin
);
3337 dst_xy
= this->delta_xy
[bary
];
3340 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3342 component(interp_reg(nir_intrinsic_base(instr
),
3343 nir_intrinsic_component(instr
) + i
), 0);
3344 interp
.type
= BRW_REGISTER_TYPE_F
;
3345 dest
.type
= BRW_REGISTER_TYPE_F
;
3347 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3348 fs_reg tmp
= vgrf(glsl_type::float_type
);
3349 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3350 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3352 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3359 nir_emit_intrinsic(bld
, instr
);
3365 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3367 if (nir_src_is_const(instr
->src
[src
])) {
3368 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3371 else if (add_val
== -1)
3379 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3380 nir_intrinsic_instr
*instr
)
3382 assert(stage
== MESA_SHADER_COMPUTE
);
3383 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3386 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3387 dest
= get_nir_dest(instr
->dest
);
3389 switch (instr
->intrinsic
) {
3390 case nir_intrinsic_barrier
:
3392 cs_prog_data
->uses_barrier
= true;
3395 case nir_intrinsic_load_subgroup_id
:
3396 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3399 case nir_intrinsic_load_local_invocation_id
:
3400 case nir_intrinsic_load_work_group_id
: {
3401 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3402 fs_reg val
= nir_system_values
[sv
];
3403 assert(val
.file
!= BAD_FILE
);
3404 dest
.type
= val
.type
;
3405 for (unsigned i
= 0; i
< 3; i
++)
3406 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3410 case nir_intrinsic_load_num_work_groups
: {
3411 const unsigned surface
=
3412 cs_prog_data
->binding_table
.work_groups_start
;
3414 cs_prog_data
->uses_num_work_groups
= true;
3416 fs_reg surf_index
= brw_imm_ud(surface
);
3417 brw_mark_surface_used(prog_data
, surface
);
3419 /* Read the 3 GLuint components of gl_NumWorkGroups */
3420 for (unsigned i
= 0; i
< 3; i
++) {
3421 fs_reg read_result
=
3422 emit_untyped_read(bld
, surf_index
,
3424 1 /* dims */, 1 /* size */,
3425 BRW_PREDICATE_NONE
);
3426 read_result
.type
= dest
.type
;
3427 bld
.MOV(dest
, read_result
);
3428 dest
= offset(dest
, bld
, 1);
3433 case nir_intrinsic_shared_atomic_add
:
3434 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3436 case nir_intrinsic_shared_atomic_imin
:
3437 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3439 case nir_intrinsic_shared_atomic_umin
:
3440 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3442 case nir_intrinsic_shared_atomic_imax
:
3443 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3445 case nir_intrinsic_shared_atomic_umax
:
3446 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3448 case nir_intrinsic_shared_atomic_and
:
3449 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3451 case nir_intrinsic_shared_atomic_or
:
3452 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3454 case nir_intrinsic_shared_atomic_xor
:
3455 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3457 case nir_intrinsic_shared_atomic_exchange
:
3458 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3460 case nir_intrinsic_shared_atomic_comp_swap
:
3461 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3463 case nir_intrinsic_shared_atomic_fmin
:
3464 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3466 case nir_intrinsic_shared_atomic_fmax
:
3467 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3469 case nir_intrinsic_shared_atomic_fcomp_swap
:
3470 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3473 case nir_intrinsic_load_shared
: {
3474 assert(devinfo
->gen
>= 7);
3475 assert(stage
== MESA_SHADER_COMPUTE
);
3477 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3478 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[0]),
3479 BRW_REGISTER_TYPE_UD
);
3481 /* Make dest unsigned because that's what the temporary will be */
3482 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3484 /* Read the vector */
3485 if (nir_intrinsic_align(instr
) >= 4) {
3486 assert(nir_dest_bit_size(instr
->dest
) == 32);
3487 fs_reg read_result
= emit_untyped_read(bld
, brw_imm_ud(GEN7_BTI_SLM
),
3488 offset_reg
, 1 /* dims */,
3489 instr
->num_components
,
3490 BRW_PREDICATE_NONE
);
3491 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
3492 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
3494 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3495 assert(nir_dest_num_components(instr
->dest
) == 1);
3496 fs_reg read_result
=
3497 emit_byte_scattered_read(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
,
3498 1 /* dims */, 1, bit_size
,
3499 BRW_PREDICATE_NONE
);
3500 bld
.MOV(dest
, read_result
);
3505 case nir_intrinsic_store_shared
: {
3506 assert(devinfo
->gen
>= 7);
3507 assert(stage
== MESA_SHADER_COMPUTE
);
3509 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3510 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3511 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[1]),
3512 BRW_REGISTER_TYPE_UD
);
3514 val_reg
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3516 assert(nir_intrinsic_write_mask(instr
) ==
3517 (1 << instr
->num_components
) - 1);
3518 if (nir_intrinsic_align(instr
) >= 4) {
3519 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3520 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3521 emit_untyped_write(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
, val_reg
,
3522 1 /* dims */, instr
->num_components
,
3523 BRW_PREDICATE_NONE
);
3525 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3526 assert(nir_src_num_components(instr
->src
[0]) == 1);
3527 fs_reg write_src
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3528 bld
.MOV(write_src
, val_reg
);
3529 emit_byte_scattered_write(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
,
3530 write_src
, 1 /* dims */, bit_size
,
3531 BRW_PREDICATE_NONE
);
3537 nir_emit_intrinsic(bld
, instr
);
3543 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3544 nir_op op
, brw_reg_type type
)
3546 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3547 switch (type_sz(type
)) {
3549 assert(type
!= BRW_REGISTER_TYPE_HF
);
3550 return retype(brw_imm_uw(value
.u16
[0]), type
);
3552 return retype(brw_imm_ud(value
.u32
[0]), type
);
3554 if (type
== BRW_REGISTER_TYPE_DF
)
3555 return setup_imm_df(bld
, value
.f64
[0]);
3557 return retype(brw_imm_u64(value
.u64
[0]), type
);
3559 unreachable("Invalid type size");
3564 brw_op_for_nir_reduction_op(nir_op op
)
3567 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3568 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3569 case nir_op_imul
: return BRW_OPCODE_MUL
;
3570 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3571 case nir_op_imin
: return BRW_OPCODE_SEL
;
3572 case nir_op_umin
: return BRW_OPCODE_SEL
;
3573 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3574 case nir_op_imax
: return BRW_OPCODE_SEL
;
3575 case nir_op_umax
: return BRW_OPCODE_SEL
;
3576 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3577 case nir_op_iand
: return BRW_OPCODE_AND
;
3578 case nir_op_ior
: return BRW_OPCODE_OR
;
3579 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3581 unreachable("Invalid reduction operation");
3585 static brw_conditional_mod
3586 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3589 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3590 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3591 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3592 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3593 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3594 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3595 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3596 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3597 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3598 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3599 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3600 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3601 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3603 unreachable("Invalid reduction operation");
3608 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3609 nir_intrinsic_instr
*instr
)
3611 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3613 if (stage_prog_data
->binding_table
.image_start
> 0) {
3614 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3615 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3617 bld
.ADD(image
, image
,
3618 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3622 return bld
.emit_uniformize(image
);
3626 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3627 nir_intrinsic_instr
*instr
)
3629 /* SSBO stores are weird in that their index is in src[1] */
3630 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3633 if (nir_src_is_const(instr
->src
[src
])) {
3634 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3635 nir_src_as_uint(instr
->src
[src
]);
3636 surf_index
= brw_imm_ud(index
);
3637 brw_mark_surface_used(prog_data
, index
);
3639 surf_index
= vgrf(glsl_type::uint_type
);
3640 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3641 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3643 /* Assume this may touch any UBO. It would be nice to provide
3644 * a tighter bound, but the array information is already lowered away.
3646 brw_mark_surface_used(prog_data
,
3647 stage_prog_data
->binding_table
.ssbo_start
+
3648 nir
->info
.num_ssbos
- 1);
3655 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3657 switch (nir_intrinsic_image_dim(instr
)) {
3658 case GLSL_SAMPLER_DIM_1D
:
3659 return 1 + nir_intrinsic_image_array(instr
);
3660 case GLSL_SAMPLER_DIM_2D
:
3661 case GLSL_SAMPLER_DIM_RECT
:
3662 return 2 + nir_intrinsic_image_array(instr
);
3663 case GLSL_SAMPLER_DIM_3D
:
3664 case GLSL_SAMPLER_DIM_CUBE
:
3666 case GLSL_SAMPLER_DIM_BUF
:
3668 case GLSL_SAMPLER_DIM_MS
:
3669 return 2 + nir_intrinsic_image_array(instr
);
3671 unreachable("Invalid image dimension");
3676 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3679 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3680 dest
= get_nir_dest(instr
->dest
);
3682 switch (instr
->intrinsic
) {
3683 case nir_intrinsic_image_load
:
3684 case nir_intrinsic_image_store
:
3685 case nir_intrinsic_image_atomic_add
:
3686 case nir_intrinsic_image_atomic_min
:
3687 case nir_intrinsic_image_atomic_max
:
3688 case nir_intrinsic_image_atomic_and
:
3689 case nir_intrinsic_image_atomic_or
:
3690 case nir_intrinsic_image_atomic_xor
:
3691 case nir_intrinsic_image_atomic_exchange
:
3692 case nir_intrinsic_image_atomic_comp_swap
: {
3693 if (stage
== MESA_SHADER_FRAGMENT
&&
3694 instr
->intrinsic
!= nir_intrinsic_image_load
)
3695 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3697 /* Get some metadata from the image intrinsic. */
3698 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3699 const unsigned dims
= image_intrinsic_coord_components(instr
);
3700 const GLenum format
= nir_intrinsic_format(instr
);
3701 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3703 /* Get the arguments of the image intrinsic. */
3704 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3705 const fs_reg coords
= retype(get_nir_src(instr
->src
[1]),
3706 BRW_REGISTER_TYPE_UD
);
3709 /* Emit an image load, store or atomic op. */
3710 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3711 tmp
= emit_typed_read(bld
, image
, coords
, dims
,
3712 instr
->num_components
);
3713 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3714 const fs_reg src0
= get_nir_src(instr
->src
[3]);
3715 emit_typed_write(bld
, image
, coords
, src0
, dims
,
3716 instr
->num_components
);
3719 unsigned num_srcs
= info
->num_srcs
;
3721 switch (instr
->intrinsic
) {
3722 case nir_intrinsic_image_atomic_add
:
3723 assert(num_srcs
== 4);
3725 op
= get_op_for_atomic_add(instr
, 3);
3727 if (op
!= BRW_AOP_ADD
)
3730 case nir_intrinsic_image_atomic_min
:
3731 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3732 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3734 case nir_intrinsic_image_atomic_max
:
3735 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3736 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3738 case nir_intrinsic_image_atomic_and
:
3741 case nir_intrinsic_image_atomic_or
:
3744 case nir_intrinsic_image_atomic_xor
:
3747 case nir_intrinsic_image_atomic_exchange
:
3750 case nir_intrinsic_image_atomic_comp_swap
:
3754 unreachable("Not reachable.");
3757 const fs_reg src0
= (num_srcs
>= 4 ?
3758 get_nir_src(instr
->src
[3]) : fs_reg());
3759 const fs_reg src1
= (num_srcs
>= 5 ?
3760 get_nir_src(instr
->src
[4]) : fs_reg());
3762 tmp
= emit_typed_atomic(bld
, image
, coords
, src0
, src1
, dims
, 1, op
);
3765 /* Assign the result. */
3766 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3767 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3768 offset(tmp
, bld
, c
));
3773 case nir_intrinsic_image_size
: {
3774 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3775 * into will handle the binding table index for us in the geneerator.
3777 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3778 BRW_REGISTER_TYPE_UD
);
3779 image
= bld
.emit_uniformize(image
);
3781 /* Since the image size is always uniform, we can just emit a SIMD8
3782 * query instruction and splat the result out.
3784 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3786 /* The LOD also serves as the message payload */
3787 fs_reg lod
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3788 ubld
.MOV(lod
, brw_imm_ud(0));
3790 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3791 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE
, tmp
, lod
, image
);
3793 inst
->size_written
= 4 * REG_SIZE
;
3795 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3796 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3797 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3798 offset(retype(dest
, tmp
.type
), bld
, c
),
3799 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3801 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3802 component(offset(tmp
, ubld
, c
), 0));
3808 case nir_intrinsic_image_load_raw_intel
: {
3809 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3810 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3811 BRW_REGISTER_TYPE_UD
);
3813 fs_reg tmp
= emit_untyped_read(bld
, image
, addr
, 1,
3814 instr
->num_components
);
3816 for (unsigned c
= 0; c
< instr
->num_components
; ++c
) {
3817 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3818 offset(tmp
, bld
, c
));
3823 case nir_intrinsic_image_store_raw_intel
: {
3824 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3825 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3826 BRW_REGISTER_TYPE_UD
);
3827 const fs_reg data
= retype(get_nir_src(instr
->src
[2]),
3828 BRW_REGISTER_TYPE_UD
);
3830 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3832 emit_untyped_write(bld
, image
, addr
, data
, 1,
3833 instr
->num_components
);
3837 case nir_intrinsic_group_memory_barrier
:
3838 case nir_intrinsic_memory_barrier_shared
:
3839 case nir_intrinsic_memory_barrier_atomic_counter
:
3840 case nir_intrinsic_memory_barrier_buffer
:
3841 case nir_intrinsic_memory_barrier_image
:
3842 case nir_intrinsic_memory_barrier
: {
3843 const fs_builder ubld
= bld
.group(8, 0);
3844 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3845 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3846 ->size_written
= 2 * REG_SIZE
;
3850 case nir_intrinsic_shader_clock
: {
3851 /* We cannot do anything if there is an event, so ignore it for now */
3852 const fs_reg shader_clock
= get_timestamp(bld
);
3853 const fs_reg srcs
[] = { component(shader_clock
, 0),
3854 component(shader_clock
, 1) };
3855 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3859 case nir_intrinsic_image_samples
:
3860 /* The driver does not support multi-sampled images. */
3861 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3864 case nir_intrinsic_load_uniform
: {
3865 /* Offsets are in bytes but they should always aligned to
3868 assert(instr
->const_index
[0] % 4 == 0 ||
3869 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3871 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3873 if (nir_src_is_const(instr
->src
[0])) {
3874 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3875 assert(load_offset
% type_sz(dest
.type
) == 0);
3876 /* For 16-bit types we add the module of the const_index[0]
3877 * offset to access to not 32-bit aligned element
3879 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
3881 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3882 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3885 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3886 BRW_REGISTER_TYPE_UD
);
3888 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3889 * go past the end of the uniform. In order to keep the n'th
3890 * component from running past, we subtract off the size of all but
3891 * one component of the vector.
3893 assert(instr
->const_index
[1] >=
3894 instr
->num_components
* (int) type_sz(dest
.type
));
3895 unsigned read_size
= instr
->const_index
[1] -
3896 (instr
->num_components
- 1) * type_sz(dest
.type
);
3898 bool supports_64bit_indirects
=
3899 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3901 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3902 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3903 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3904 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3905 indirect
, brw_imm_ud(read_size
));
3908 const unsigned num_mov_indirects
=
3909 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3910 /* We read a little bit less per MOV INDIRECT, as they are now
3911 * 32-bits ones instead of 64-bit. Fix read_size then.
3913 const unsigned read_size_32bit
= read_size
-
3914 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3915 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3916 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3917 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3918 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3919 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3920 indirect
, brw_imm_ud(read_size_32bit
));
3928 case nir_intrinsic_load_ubo
: {
3930 if (nir_src_is_const(instr
->src
[0])) {
3931 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3932 nir_src_as_uint(instr
->src
[0]);
3933 surf_index
= brw_imm_ud(index
);
3934 brw_mark_surface_used(prog_data
, index
);
3936 /* The block index is not a constant. Evaluate the index expression
3937 * per-channel and add the base UBO index; we have to select a value
3938 * from any live channel.
3940 surf_index
= vgrf(glsl_type::uint_type
);
3941 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3942 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3943 surf_index
= bld
.emit_uniformize(surf_index
);
3945 /* Assume this may touch any UBO. It would be nice to provide
3946 * a tighter bound, but the array information is already lowered away.
3948 brw_mark_surface_used(prog_data
,
3949 stage_prog_data
->binding_table
.ubo_start
+
3950 nir
->info
.num_ubos
- 1);
3953 if (!nir_src_is_const(instr
->src
[1])) {
3954 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3955 BRW_REGISTER_TYPE_UD
);
3957 for (int i
= 0; i
< instr
->num_components
; i
++)
3958 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3959 base_offset
, i
* type_sz(dest
.type
));
3961 /* Even if we are loading doubles, a pull constant load will load
3962 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3963 * need to load a full dvec4 we will have to emit 2 loads. This is
3964 * similar to demote_pull_constants(), except that in that case we
3965 * see individual accesses to each component of the vector and then
3966 * we let CSE deal with duplicate loads. Here we see a vector access
3967 * and we have to split it if necessary.
3969 const unsigned type_size
= type_sz(dest
.type
);
3970 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
3972 /* See if we've selected this as a push constant candidate */
3973 if (nir_src_is_const(instr
->src
[0])) {
3974 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
3975 const unsigned offset_256b
= load_offset
/ 32;
3978 for (int i
= 0; i
< 4; i
++) {
3979 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3980 if (range
->block
== ubo_block
&&
3981 offset_256b
>= range
->start
&&
3982 offset_256b
< range
->start
+ range
->length
) {
3984 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3985 push_reg
.offset
= load_offset
- 32 * range
->start
;
3990 if (push_reg
.file
!= BAD_FILE
) {
3991 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3992 bld
.MOV(offset(dest
, bld
, i
),
3993 byte_offset(push_reg
, i
* type_size
));
3999 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4000 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4001 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4003 for (unsigned c
= 0; c
< instr
->num_components
;) {
4004 const unsigned base
= load_offset
+ c
* type_size
;
4005 /* Number of usable components in the next block-aligned load. */
4006 const unsigned count
= MIN2(instr
->num_components
- c
,
4007 (block_sz
- base
% block_sz
) / type_size
);
4009 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4010 packed_consts
, surf_index
,
4011 brw_imm_ud(base
& ~(block_sz
- 1)));
4013 const fs_reg consts
=
4014 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4017 for (unsigned d
= 0; d
< count
; d
++)
4018 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4026 case nir_intrinsic_load_ssbo
: {
4027 assert(devinfo
->gen
>= 7);
4029 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4030 fs_reg surf_index
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4031 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[1]),
4032 BRW_REGISTER_TYPE_UD
);
4034 /* Make dest unsigned because that's what the temporary will be */
4035 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4037 /* Read the vector */
4038 if (nir_intrinsic_align(instr
) >= 4) {
4039 assert(nir_dest_bit_size(instr
->dest
) == 32);
4040 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
4042 instr
->num_components
,
4043 BRW_PREDICATE_NONE
);
4044 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
4045 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
4047 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4048 assert(nir_dest_num_components(instr
->dest
) == 1);
4049 fs_reg read_result
=
4050 emit_byte_scattered_read(bld
, surf_index
, offset_reg
,
4051 1 /* dims */, 1, bit_size
,
4052 BRW_PREDICATE_NONE
);
4053 bld
.MOV(dest
, read_result
);
4058 case nir_intrinsic_store_ssbo
: {
4059 assert(devinfo
->gen
>= 7);
4061 if (stage
== MESA_SHADER_FRAGMENT
)
4062 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4064 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4065 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4066 fs_reg surf_index
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4067 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[2]),
4068 BRW_REGISTER_TYPE_UD
);
4070 val_reg
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4072 assert(nir_intrinsic_write_mask(instr
) ==
4073 (1 << instr
->num_components
) - 1);
4074 if (nir_intrinsic_align(instr
) >= 4) {
4075 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4076 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4077 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
4078 1 /* dims */, instr
->num_components
,
4079 BRW_PREDICATE_NONE
);
4081 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4082 assert(nir_src_num_components(instr
->src
[0]) == 1);
4083 fs_reg write_src
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4084 bld
.MOV(write_src
, val_reg
);
4085 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4086 write_src
, 1 /* dims */, bit_size
,
4087 BRW_PREDICATE_NONE
);
4092 case nir_intrinsic_store_output
: {
4093 fs_reg src
= get_nir_src(instr
->src
[0]);
4095 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4096 unsigned num_components
= instr
->num_components
;
4097 unsigned first_component
= nir_intrinsic_component(instr
);
4098 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4099 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4100 num_components
*= 2;
4103 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4104 4 * store_offset
), src
.type
);
4105 for (unsigned j
= 0; j
< num_components
; j
++) {
4106 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4107 offset(src
, bld
, j
));
4112 case nir_intrinsic_ssbo_atomic_add
:
4113 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4115 case nir_intrinsic_ssbo_atomic_imin
:
4116 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4118 case nir_intrinsic_ssbo_atomic_umin
:
4119 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4121 case nir_intrinsic_ssbo_atomic_imax
:
4122 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4124 case nir_intrinsic_ssbo_atomic_umax
:
4125 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4127 case nir_intrinsic_ssbo_atomic_and
:
4128 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4130 case nir_intrinsic_ssbo_atomic_or
:
4131 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4133 case nir_intrinsic_ssbo_atomic_xor
:
4134 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4136 case nir_intrinsic_ssbo_atomic_exchange
:
4137 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4139 case nir_intrinsic_ssbo_atomic_comp_swap
:
4140 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4142 case nir_intrinsic_ssbo_atomic_fmin
:
4143 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4145 case nir_intrinsic_ssbo_atomic_fmax
:
4146 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4148 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4149 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4152 case nir_intrinsic_get_buffer_size
: {
4153 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4154 nir_src_as_uint(instr
->src
[0]) : 0;
4156 /* A resinfo's sampler message is used to get the buffer size. The
4157 * SIMD8's writeback message consists of four registers and SIMD16's
4158 * writeback message consists of 8 destination registers (two per each
4159 * component). Because we are only interested on the first channel of
4160 * the first returned component, where resinfo returns the buffer size
4161 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4162 * the dispatch width.
4164 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4165 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4166 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4169 ubld
.MOV(src_payload
, brw_imm_d(0));
4171 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4172 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4173 src_payload
, brw_imm_ud(index
));
4174 inst
->header_size
= 0;
4176 inst
->size_written
= 4 * REG_SIZE
;
4178 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4180 * "Out-of-bounds checking is always performed at a DWord granularity. If
4181 * any part of the DWord is out-of-bounds then the whole DWord is
4182 * considered out-of-bounds."
4184 * This implies that types with size smaller than 4-bytes need to be
4185 * padded if they don't complete the last dword of the buffer. But as we
4186 * need to maintain the original size we need to reverse the padding
4187 * calculation to return the correct size to know the number of elements
4188 * of an unsized array. As we stored in the last two bits of the surface
4189 * size the needed padding for the buffer, we calculate here the
4190 * original buffer_size reversing the surface_size calculation:
4192 * surface_size = isl_align(buffer_size, 4) +
4193 * (isl_align(buffer_size) - buffer_size)
4195 * buffer_size = surface_size & ~3 - surface_size & 3
4198 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4199 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4200 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4202 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4203 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4204 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4206 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4208 brw_mark_surface_used(prog_data
, index
);
4212 case nir_intrinsic_load_subgroup_invocation
:
4213 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4214 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4217 case nir_intrinsic_load_subgroup_eq_mask
:
4218 case nir_intrinsic_load_subgroup_ge_mask
:
4219 case nir_intrinsic_load_subgroup_gt_mask
:
4220 case nir_intrinsic_load_subgroup_le_mask
:
4221 case nir_intrinsic_load_subgroup_lt_mask
:
4222 unreachable("not reached");
4224 case nir_intrinsic_vote_any
: {
4225 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4227 /* The any/all predicates do not consider channel enables. To prevent
4228 * dead channels from affecting the result, we initialize the flag with
4229 * with the identity value for the logical operation.
4231 if (dispatch_width
== 32) {
4232 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4233 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4236 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4238 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4240 /* For some reason, the any/all predicates don't work properly with
4241 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4242 * doesn't read the correct subset of the flag register and you end up
4243 * getting garbage in the second half. Work around this by using a pair
4244 * of 1-wide MOVs and scattering the result.
4246 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4247 ubld
.MOV(res1
, brw_imm_d(0));
4248 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4249 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4250 BRW_PREDICATE_ALIGN1_ANY32H
,
4251 ubld
.MOV(res1
, brw_imm_d(-1)));
4253 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4256 case nir_intrinsic_vote_all
: {
4257 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4259 /* The any/all predicates do not consider channel enables. To prevent
4260 * dead channels from affecting the result, we initialize the flag with
4261 * with the identity value for the logical operation.
4263 if (dispatch_width
== 32) {
4264 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4265 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4266 brw_imm_ud(0xffffffff));
4268 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4270 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4272 /* For some reason, the any/all predicates don't work properly with
4273 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4274 * doesn't read the correct subset of the flag register and you end up
4275 * getting garbage in the second half. Work around this by using a pair
4276 * of 1-wide MOVs and scattering the result.
4278 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4279 ubld
.MOV(res1
, brw_imm_d(0));
4280 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4281 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4282 BRW_PREDICATE_ALIGN1_ALL32H
,
4283 ubld
.MOV(res1
, brw_imm_d(-1)));
4285 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4288 case nir_intrinsic_vote_feq
:
4289 case nir_intrinsic_vote_ieq
: {
4290 fs_reg value
= get_nir_src(instr
->src
[0]);
4291 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4292 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4293 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4296 fs_reg uniformized
= bld
.emit_uniformize(value
);
4297 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4299 /* The any/all predicates do not consider channel enables. To prevent
4300 * dead channels from affecting the result, we initialize the flag with
4301 * with the identity value for the logical operation.
4303 if (dispatch_width
== 32) {
4304 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4305 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4306 brw_imm_ud(0xffffffff));
4308 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4310 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4312 /* For some reason, the any/all predicates don't work properly with
4313 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4314 * doesn't read the correct subset of the flag register and you end up
4315 * getting garbage in the second half. Work around this by using a pair
4316 * of 1-wide MOVs and scattering the result.
4318 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4319 ubld
.MOV(res1
, brw_imm_d(0));
4320 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4321 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4322 BRW_PREDICATE_ALIGN1_ALL32H
,
4323 ubld
.MOV(res1
, brw_imm_d(-1)));
4325 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4329 case nir_intrinsic_ballot
: {
4330 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4331 BRW_REGISTER_TYPE_UD
);
4332 struct brw_reg flag
= brw_flag_reg(0, 0);
4333 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4334 * as f0.0. This is a problem for fragment programs as we currently use
4335 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4336 * programs yet so this isn't a problem. When we do, something will
4339 if (dispatch_width
== 32)
4340 flag
.type
= BRW_REGISTER_TYPE_UD
;
4342 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4343 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4345 if (instr
->dest
.ssa
.bit_size
> 32) {
4346 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4348 dest
.type
= BRW_REGISTER_TYPE_UD
;
4350 bld
.MOV(dest
, flag
);
4354 case nir_intrinsic_read_invocation
: {
4355 const fs_reg value
= get_nir_src(instr
->src
[0]);
4356 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4357 fs_reg tmp
= bld
.vgrf(value
.type
);
4359 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4360 bld
.emit_uniformize(invocation
));
4362 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4366 case nir_intrinsic_read_first_invocation
: {
4367 const fs_reg value
= get_nir_src(instr
->src
[0]);
4368 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4372 case nir_intrinsic_shuffle
: {
4373 const fs_reg value
= get_nir_src(instr
->src
[0]);
4374 const fs_reg index
= get_nir_src(instr
->src
[1]);
4376 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4380 case nir_intrinsic_first_invocation
: {
4381 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4382 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4383 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4384 fs_reg(component(tmp
, 0)));
4388 case nir_intrinsic_quad_broadcast
: {
4389 const fs_reg value
= get_nir_src(instr
->src
[0]);
4390 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4392 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4393 value
, brw_imm_ud(index
), brw_imm_ud(4));
4397 case nir_intrinsic_quad_swap_horizontal
: {
4398 const fs_reg value
= get_nir_src(instr
->src
[0]);
4399 const fs_reg tmp
= bld
.vgrf(value
.type
);
4400 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4402 const fs_reg src_left
= horiz_stride(value
, 2);
4403 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4404 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4405 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4407 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4409 * "When source or destination datatype is 64b or operation is
4410 * integer DWord multiply, regioning in Align1 must follow
4415 * 3. Source and Destination offset must be the same, except
4416 * the case of scalar source."
4418 * In order to work around this, we have to emit two 32-bit MOVs instead
4419 * of a single 64-bit MOV to do the shuffle.
4421 if (type_sz(value
.type
) > 4 &&
4422 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4423 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4424 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4425 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4426 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4427 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4428 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4429 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4430 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4432 ubld
.MOV(tmp_left
, src_right
);
4433 ubld
.MOV(tmp_right
, src_left
);
4435 bld
.MOV(retype(dest
, value
.type
), tmp
);
4439 case nir_intrinsic_quad_swap_vertical
: {
4440 const fs_reg value
= get_nir_src(instr
->src
[0]);
4441 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4442 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4443 const fs_reg tmp
= bld
.vgrf(value
.type
);
4444 const fs_builder ubld
= bld
.exec_all();
4445 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4446 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4447 bld
.MOV(retype(dest
, value
.type
), tmp
);
4449 /* For larger data types, we have to either emit dispatch_width many
4450 * MOVs or else fall back to doing indirects.
4452 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4453 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4455 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4460 case nir_intrinsic_quad_swap_diagonal
: {
4461 const fs_reg value
= get_nir_src(instr
->src
[0]);
4462 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4463 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4464 const fs_reg tmp
= bld
.vgrf(value
.type
);
4465 const fs_builder ubld
= bld
.exec_all();
4466 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4467 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4468 bld
.MOV(retype(dest
, value
.type
), tmp
);
4470 /* For larger data types, we have to either emit dispatch_width many
4471 * MOVs or else fall back to doing indirects.
4473 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4474 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4476 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4481 case nir_intrinsic_reduce
: {
4482 fs_reg src
= get_nir_src(instr
->src
[0]);
4483 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4484 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4485 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4486 cluster_size
= dispatch_width
;
4488 /* Figure out the source type */
4489 src
.type
= brw_type_for_nir_type(devinfo
,
4490 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4491 nir_src_bit_size(instr
->src
[0])));
4493 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4494 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4495 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4497 /* Set up a register for all of our scratching around and initialize it
4498 * to reduction operation's identity value.
4500 fs_reg scan
= bld
.vgrf(src
.type
);
4501 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4503 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4505 dest
.type
= src
.type
;
4506 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4507 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4508 * the distance between clusters is at least 2 GRFs. In this case,
4509 * we don't need the weird striding of the CLUSTER_BROADCAST
4510 * instruction and can just do regular MOVs.
4512 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4513 const unsigned groups
=
4514 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4515 const unsigned group_size
= dispatch_width
/ groups
;
4516 for (unsigned i
= 0; i
< groups
; i
++) {
4517 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4518 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4519 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4520 component(scan
, comp
));
4523 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4524 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4529 case nir_intrinsic_inclusive_scan
:
4530 case nir_intrinsic_exclusive_scan
: {
4531 fs_reg src
= get_nir_src(instr
->src
[0]);
4532 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4534 /* Figure out the source type */
4535 src
.type
= brw_type_for_nir_type(devinfo
,
4536 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4537 nir_src_bit_size(instr
->src
[0])));
4539 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4540 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4541 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4543 /* Set up a register for all of our scratching around and initialize it
4544 * to reduction operation's identity value.
4546 fs_reg scan
= bld
.vgrf(src
.type
);
4547 const fs_builder allbld
= bld
.exec_all();
4548 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4550 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4551 /* Exclusive scan is a bit harder because we have to do an annoying
4552 * shift of the contents before we can begin. To make things worse,
4553 * we can't do this with a normal stride; we have to use indirects.
4555 fs_reg shifted
= bld
.vgrf(src
.type
);
4556 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4557 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4559 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4560 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4564 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4566 bld
.MOV(retype(dest
, src
.type
), scan
);
4570 case nir_intrinsic_begin_fragment_shader_ordering
:
4571 case nir_intrinsic_begin_invocation_interlock
: {
4572 const fs_builder ubld
= bld
.group(8, 0);
4573 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4575 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4581 case nir_intrinsic_end_invocation_interlock
: {
4582 /* We don't need to do anything here */
4587 unreachable("unknown intrinsic");
4592 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4593 int op
, nir_intrinsic_instr
*instr
)
4595 if (stage
== MESA_SHADER_FRAGMENT
)
4596 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4599 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4600 dest
= get_nir_dest(instr
->dest
);
4602 fs_reg surface
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4603 fs_reg offset
= get_nir_src(instr
->src
[1]);
4605 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4606 data1
= get_nir_src(instr
->src
[2]);
4608 if (op
== BRW_AOP_CMPWR
)
4609 data2
= get_nir_src(instr
->src
[3]);
4611 /* Emit the actual atomic operation */
4613 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4615 1 /* dims */, 1 /* rsize */,
4617 BRW_PREDICATE_NONE
);
4618 dest
.type
= atomic_result
.type
;
4619 bld
.MOV(dest
, atomic_result
);
4623 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4624 int op
, nir_intrinsic_instr
*instr
)
4626 if (stage
== MESA_SHADER_FRAGMENT
)
4627 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4630 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4631 dest
= get_nir_dest(instr
->dest
);
4633 fs_reg surface
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4634 fs_reg offset
= get_nir_src(instr
->src
[1]);
4635 fs_reg data1
= get_nir_src(instr
->src
[2]);
4637 if (op
== BRW_AOP_FCMPWR
)
4638 data2
= get_nir_src(instr
->src
[3]);
4640 /* Emit the actual atomic operation */
4642 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4644 1 /* dims */, 1 /* rsize */,
4646 BRW_PREDICATE_NONE
);
4647 dest
.type
= atomic_result
.type
;
4648 bld
.MOV(dest
, atomic_result
);
4652 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4653 int op
, nir_intrinsic_instr
*instr
)
4656 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4657 dest
= get_nir_dest(instr
->dest
);
4659 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4662 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4663 data1
= get_nir_src(instr
->src
[1]);
4665 if (op
== BRW_AOP_CMPWR
)
4666 data2
= get_nir_src(instr
->src
[2]);
4668 /* Get the offset */
4669 if (nir_src_is_const(instr
->src
[0])) {
4670 offset
= brw_imm_ud(instr
->const_index
[0] +
4671 nir_src_as_uint(instr
->src
[0]));
4673 offset
= vgrf(glsl_type::uint_type
);
4675 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4676 brw_imm_ud(instr
->const_index
[0]));
4679 /* Emit the actual atomic operation operation */
4681 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4683 1 /* dims */, 1 /* rsize */,
4685 BRW_PREDICATE_NONE
);
4686 dest
.type
= atomic_result
.type
;
4687 bld
.MOV(dest
, atomic_result
);
4691 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4692 int op
, nir_intrinsic_instr
*instr
)
4695 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4696 dest
= get_nir_dest(instr
->dest
);
4698 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4700 fs_reg data1
= get_nir_src(instr
->src
[1]);
4702 if (op
== BRW_AOP_FCMPWR
)
4703 data2
= get_nir_src(instr
->src
[2]);
4705 /* Get the offset */
4706 if (nir_src_is_const(instr
->src
[0])) {
4707 offset
= brw_imm_ud(instr
->const_index
[0] +
4708 nir_src_as_uint(instr
->src
[0]));
4710 offset
= vgrf(glsl_type::uint_type
);
4712 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4713 brw_imm_ud(instr
->const_index
[0]));
4716 /* Emit the actual atomic operation operation */
4718 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4720 1 /* dims */, 1 /* rsize */,
4722 BRW_PREDICATE_NONE
);
4723 dest
.type
= atomic_result
.type
;
4724 bld
.MOV(dest
, atomic_result
);
4728 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4730 unsigned texture
= instr
->texture_index
;
4731 unsigned sampler
= instr
->sampler_index
;
4733 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4735 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4736 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4738 int lod_components
= 0;
4740 /* The hardware requires a LOD for buffer textures */
4741 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4742 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4744 uint32_t header_bits
= 0;
4745 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4746 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4747 switch (instr
->src
[i
].src_type
) {
4748 case nir_tex_src_bias
:
4749 srcs
[TEX_LOGICAL_SRC_LOD
] =
4750 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4752 case nir_tex_src_comparator
:
4753 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4755 case nir_tex_src_coord
:
4756 switch (instr
->op
) {
4758 case nir_texop_txf_ms
:
4759 case nir_texop_txf_ms_mcs
:
4760 case nir_texop_samples_identical
:
4761 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4764 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4768 case nir_tex_src_ddx
:
4769 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4770 lod_components
= nir_tex_instr_src_size(instr
, i
);
4772 case nir_tex_src_ddy
:
4773 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4775 case nir_tex_src_lod
:
4776 switch (instr
->op
) {
4778 srcs
[TEX_LOGICAL_SRC_LOD
] =
4779 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4782 srcs
[TEX_LOGICAL_SRC_LOD
] =
4783 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4786 srcs
[TEX_LOGICAL_SRC_LOD
] =
4787 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4791 case nir_tex_src_ms_index
:
4792 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4795 case nir_tex_src_offset
: {
4796 nir_const_value
*const_offset
=
4797 nir_src_as_const_value(instr
->src
[i
].src
);
4798 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
4799 unsigned offset_bits
= 0;
4801 brw_texture_offset(const_offset
->i32
,
4802 nir_tex_instr_src_size(instr
, i
),
4804 header_bits
|= offset_bits
;
4806 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4807 retype(src
, BRW_REGISTER_TYPE_D
);
4812 case nir_tex_src_projector
:
4813 unreachable("should be lowered");
4815 case nir_tex_src_texture_offset
: {
4816 /* Figure out the highest possible texture index and mark it as used */
4817 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4818 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4819 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4821 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4823 brw_mark_surface_used(prog_data
, max_used
);
4825 /* Emit code to evaluate the actual indexing expression */
4826 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4827 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4828 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4832 case nir_tex_src_sampler_offset
: {
4833 /* Emit code to evaluate the actual indexing expression */
4834 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4835 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4836 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4840 case nir_tex_src_ms_mcs
:
4841 assert(instr
->op
== nir_texop_txf_ms
);
4842 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4845 case nir_tex_src_plane
: {
4846 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
4847 const uint32_t texture_index
=
4848 instr
->texture_index
+
4849 stage_prog_data
->binding_table
.plane_start
[plane
] -
4850 stage_prog_data
->binding_table
.texture_start
;
4852 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4857 unreachable("unknown texture source");
4861 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4862 (instr
->op
== nir_texop_txf_ms
||
4863 instr
->op
== nir_texop_samples_identical
)) {
4864 if (devinfo
->gen
>= 7 &&
4865 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4866 srcs
[TEX_LOGICAL_SRC_MCS
] =
4867 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4868 instr
->coord_components
,
4869 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4871 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4875 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4876 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4879 switch (instr
->op
) {
4881 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4882 SHADER_OPCODE_TXL_LOGICAL
);
4885 opcode
= FS_OPCODE_TXB_LOGICAL
;
4888 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4891 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4894 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4896 case nir_texop_txf_ms
:
4897 if ((key_tex
->msaa_16
& (1 << sampler
)))
4898 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4900 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4902 case nir_texop_txf_ms_mcs
:
4903 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4905 case nir_texop_query_levels
:
4907 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4910 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4913 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4914 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4916 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4918 case nir_texop_texture_samples
:
4919 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4921 case nir_texop_samples_identical
: {
4922 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4924 /* If mcs is an immediate value, it means there is no MCS. In that case
4925 * just return false.
4927 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4928 bld
.MOV(dst
, brw_imm_ud(0u));
4929 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4930 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4931 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4932 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4933 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4935 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4936 BRW_CONDITIONAL_EQ
);
4941 unreachable("unknown texture opcode");
4944 if (instr
->op
== nir_texop_tg4
) {
4945 if (instr
->component
== 1 &&
4946 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4947 /* gather4 sampler is broken for green channel on RG32F --
4948 * we must ask for blue instead.
4950 header_bits
|= 2 << 16;
4952 header_bits
|= instr
->component
<< 16;
4956 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4957 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4958 inst
->offset
= header_bits
;
4960 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4961 if (devinfo
->gen
>= 9 &&
4962 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4963 unsigned write_mask
= instr
->dest
.is_ssa
?
4964 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4965 (1 << dest_size
) - 1;
4966 assert(write_mask
!= 0); /* dead code should have been eliminated */
4967 inst
->size_written
= util_last_bit(write_mask
) *
4968 inst
->dst
.component_size(inst
->exec_size
);
4970 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4973 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4974 inst
->shadow_compare
= true;
4976 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4977 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4980 for (unsigned i
= 0; i
< dest_size
; i
++)
4981 nir_dest
[i
] = offset(dst
, bld
, i
);
4983 if (instr
->op
== nir_texop_query_levels
) {
4984 /* # levels is in .w */
4985 nir_dest
[0] = offset(dst
, bld
, 3);
4986 } else if (instr
->op
== nir_texop_txs
&&
4987 dest_size
>= 3 && devinfo
->gen
< 7) {
4988 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4989 fs_reg depth
= offset(dst
, bld
, 2);
4990 nir_dest
[2] = vgrf(glsl_type::int_type
);
4991 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4994 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4998 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5000 switch (instr
->type
) {
5001 case nir_jump_break
:
5002 bld
.emit(BRW_OPCODE_BREAK
);
5004 case nir_jump_continue
:
5005 bld
.emit(BRW_OPCODE_CONTINUE
);
5007 case nir_jump_return
:
5009 unreachable("unknown jump");
5014 * This helper takes a source register and un/shuffles it into the destination
5017 * If source type size is smaller than destination type size the operation
5018 * needed is a component shuffle. The opposite case would be an unshuffle. If
5019 * source/destination type size is equal a shuffle is done that would be
5020 * equivalent to a simple MOV.
5022 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5023 * components .xyz 16-bit vector on SIMD8 would be.
5025 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5026 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5028 * This helper will return the following 2 32-bit components with the 16-bit
5031 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5032 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5034 * For unshuffle, the example would be the opposite, a 64-bit type source
5035 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5038 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5039 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5040 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5041 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5043 * The returned result would be the following 4 32-bit components unshuffled:
5045 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5046 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5047 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5048 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5050 * - Source and destination register must not be overlapped.
5051 * - components units are measured in terms of the smaller type between
5052 * source and destination because we are un/shuffling the smaller
5053 * components from/into the bigger ones.
5054 * - first_component parameter allows skipping source components.
5057 shuffle_src_to_dst(const fs_builder
&bld
,
5060 uint32_t first_component
,
5061 uint32_t components
)
5063 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5064 assert(!regions_overlap(dst
,
5065 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5066 offset(src
, bld
, first_component
),
5067 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5068 for (unsigned i
= 0; i
< components
; i
++) {
5069 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5070 offset(src
, bld
, i
+ first_component
));
5072 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5073 /* Source is shuffled into destination */
5074 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5075 assert(!regions_overlap(dst
,
5076 type_sz(dst
.type
) * bld
.dispatch_width() *
5077 DIV_ROUND_UP(components
, size_ratio
),
5078 offset(src
, bld
, first_component
),
5079 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5081 brw_reg_type shuffle_type
=
5082 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5083 BRW_REGISTER_TYPE_D
);
5084 for (unsigned i
= 0; i
< components
; i
++) {
5085 fs_reg shuffle_component_i
=
5086 subscript(offset(dst
, bld
, i
/ size_ratio
),
5087 shuffle_type
, i
% size_ratio
);
5088 bld
.MOV(shuffle_component_i
,
5089 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5092 /* Source is unshuffled into destination */
5093 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5094 assert(!regions_overlap(dst
,
5095 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5096 offset(src
, bld
, first_component
/ size_ratio
),
5097 type_sz(src
.type
) * bld
.dispatch_width() *
5098 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5101 brw_reg_type shuffle_type
=
5102 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5103 BRW_REGISTER_TYPE_D
);
5104 for (unsigned i
= 0; i
< components
; i
++) {
5105 fs_reg shuffle_component_i
=
5106 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5107 shuffle_type
, (first_component
+ i
) % size_ratio
);
5108 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5109 shuffle_component_i
);
5115 shuffle_from_32bit_read(const fs_builder
&bld
,
5118 uint32_t first_component
,
5119 uint32_t components
)
5121 assert(type_sz(src
.type
) == 4);
5123 /* This function takes components in units of the destination type while
5124 * shuffle_src_to_dst takes components in units of the smallest type
5126 if (type_sz(dst
.type
) > 4) {
5127 assert(type_sz(dst
.type
) == 8);
5128 first_component
*= 2;
5132 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5136 shuffle_for_32bit_write(const fs_builder
&bld
,
5138 uint32_t first_component
,
5139 uint32_t components
)
5141 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5142 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5143 /* This function takes components in units of the source type while
5144 * shuffle_src_to_dst takes components in units of the smallest type
5146 if (type_sz(src
.type
) > 4) {
5147 assert(type_sz(src
.type
) == 8);
5148 first_component
*= 2;
5152 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5158 setup_imm_df(const fs_builder
&bld
, double v
)
5160 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5161 assert(devinfo
->gen
>= 7);
5163 if (devinfo
->gen
>= 8)
5164 return brw_imm_df(v
);
5166 /* gen7.5 does not support DF immediates straighforward but the DIM
5167 * instruction allows to set the 64-bit immediate value.
5169 if (devinfo
->is_haswell
) {
5170 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5171 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5172 ubld
.DIM(dst
, brw_imm_df(v
));
5173 return component(dst
, 0);
5176 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5177 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5178 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5180 * Alternatively, we could also produce a normal VGRF (without stride 0)
5181 * by writing to all the channels in the VGRF, however, that would hit the
5182 * gen7 bug where we have to split writes that span more than 1 register
5183 * into instructions with a width of 4 (otherwise the write to the second
5184 * register written runs into an execmask hardware bug) which isn't very
5197 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5198 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5199 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5200 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5202 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5206 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5208 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5209 bld
.MOV(tmp
, brw_imm_w(v
));
5214 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5216 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5217 bld
.MOV(tmp
, brw_imm_uw(v
));