2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "util/u_math.h"
28 #include "util/bitscan.h"
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
46 fs_visitor::nir_setup_outputs()
48 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
51 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
53 /* Calculate the size of output registers in a separate pass, before
54 * allocating them. With ARB_enhanced_layouts, multiple output variables
55 * may occupy the same slot, but have different type sizes.
57 nir_foreach_variable(var
, &nir
->outputs
) {
58 const int loc
= var
->data
.driver_location
;
59 const unsigned var_vec4s
=
60 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
61 : type_size_vec4(var
->type
);
62 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
65 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
66 if (vec4s
[loc
] == 0) {
71 unsigned reg_size
= vec4s
[loc
];
73 /* Check if there are any ranges that start within this range and extend
74 * past it. If so, include them in this allocation.
76 for (unsigned i
= 1; i
< reg_size
; i
++)
77 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
79 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
80 for (unsigned i
= 0; i
< reg_size
; i
++)
81 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
88 fs_visitor::nir_setup_uniforms()
90 /* Only the first compile gets to set up uniforms. */
91 if (push_constant_loc
) {
92 assert(pull_constant_loc
);
96 uniforms
= nir
->num_uniforms
/ 4;
98 if (stage
== MESA_SHADER_COMPUTE
) {
99 /* Add a uniform for the thread local id. It must be the last uniform
102 assert(uniforms
== prog_data
->nr_params
);
103 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
104 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
105 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
110 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
114 nir_foreach_instr(instr
, block
) {
115 if (instr
->type
!= nir_instr_type_intrinsic
)
118 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
119 switch (intrin
->intrinsic
) {
120 case nir_intrinsic_load_vertex_id
:
121 case nir_intrinsic_load_base_vertex
:
122 unreachable("should be lowered by nir_lower_system_values().");
124 case nir_intrinsic_load_vertex_id_zero_base
:
125 case nir_intrinsic_load_is_indexed_draw
:
126 case nir_intrinsic_load_first_vertex
:
127 case nir_intrinsic_load_instance_id
:
128 case nir_intrinsic_load_base_instance
:
129 case nir_intrinsic_load_draw_id
:
130 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
132 case nir_intrinsic_load_invocation_id
:
133 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
135 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
136 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
137 if (reg
->file
== BAD_FILE
) {
138 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
139 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
140 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
141 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
146 case nir_intrinsic_load_sample_pos
:
147 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
148 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
149 if (reg
->file
== BAD_FILE
)
150 *reg
= *v
->emit_samplepos_setup();
153 case nir_intrinsic_load_sample_id
:
154 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_sampleid_setup();
160 case nir_intrinsic_load_sample_mask_in
:
161 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
162 assert(v
->devinfo
->gen
>= 7);
163 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
164 if (reg
->file
== BAD_FILE
)
165 *reg
= *v
->emit_samplemaskin_setup();
168 case nir_intrinsic_load_work_group_id
:
169 assert(v
->stage
== MESA_SHADER_COMPUTE
);
170 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
171 if (reg
->file
== BAD_FILE
)
172 *reg
= *v
->emit_cs_work_group_id_setup();
175 case nir_intrinsic_load_helper_invocation
:
176 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
177 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
178 if (reg
->file
== BAD_FILE
) {
179 const fs_builder abld
=
180 v
->bld
.annotate("gl_HelperInvocation", NULL
);
182 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
183 * pixel mask is in g1.7 of the thread payload.
185 * We move the per-channel pixel enable bit to the low bit of each
186 * channel by shifting the byte containing the pixel mask by the
187 * vector immediate 0x76543210UV.
189 * The region of <1,8,0> reads only 1 byte (the pixel masks for
190 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
191 * masks for 2 and 3) in SIMD16.
193 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
195 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
196 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
197 hbld
.SHR(offset(shifted
, hbld
, i
),
198 stride(retype(brw_vec1_grf(1 + i
, 7),
199 BRW_REGISTER_TYPE_UB
),
201 brw_imm_v(0x76543210));
204 /* A set bit in the pixel mask means the channel is enabled, but
205 * that is the opposite of gl_HelperInvocation so we need to invert
208 * The negate source-modifier bit of logical instructions on Gen8+
209 * performs 1's complement negation, so we can use that instead of
212 fs_reg inverted
= negate(shifted
);
213 if (v
->devinfo
->gen
< 8) {
214 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
215 abld
.NOT(inverted
, shifted
);
218 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
219 * with 1 and negating.
221 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
222 abld
.AND(anded
, inverted
, brw_imm_uw(1));
224 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
225 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
239 fs_visitor::nir_emit_system_values()
241 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
242 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
243 nir_system_values
[i
] = fs_reg();
246 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
247 * never end up using it.
250 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
251 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
252 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
254 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
255 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
256 if (dispatch_width
> 8)
257 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
258 if (dispatch_width
> 16) {
259 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
260 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
264 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
265 nir_foreach_block(block
, impl
)
266 emit_system_values_block(block
, this);
270 * Returns a type based on a reference_type (word, float, half-float) and a
273 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
275 * @FIXME: 64-bit return types are always DF on integer types to maintain
276 * compability with uses of DF previously to the introduction of int64
280 brw_reg_type_from_bit_size(const unsigned bit_size
,
281 const brw_reg_type reference_type
)
283 switch(reference_type
) {
284 case BRW_REGISTER_TYPE_HF
:
285 case BRW_REGISTER_TYPE_F
:
286 case BRW_REGISTER_TYPE_DF
:
289 return BRW_REGISTER_TYPE_HF
;
291 return BRW_REGISTER_TYPE_F
;
293 return BRW_REGISTER_TYPE_DF
;
295 unreachable("Invalid bit size");
297 case BRW_REGISTER_TYPE_B
:
298 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_D
:
300 case BRW_REGISTER_TYPE_Q
:
303 return BRW_REGISTER_TYPE_B
;
305 return BRW_REGISTER_TYPE_W
;
307 return BRW_REGISTER_TYPE_D
;
309 return BRW_REGISTER_TYPE_Q
;
311 unreachable("Invalid bit size");
313 case BRW_REGISTER_TYPE_UB
:
314 case BRW_REGISTER_TYPE_UW
:
315 case BRW_REGISTER_TYPE_UD
:
316 case BRW_REGISTER_TYPE_UQ
:
319 return BRW_REGISTER_TYPE_UB
;
321 return BRW_REGISTER_TYPE_UW
;
323 return BRW_REGISTER_TYPE_UD
;
325 return BRW_REGISTER_TYPE_UQ
;
327 unreachable("Invalid bit size");
330 unreachable("Unknown type");
335 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
337 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
338 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
339 nir_locals
[i
] = fs_reg();
342 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
343 unsigned array_elems
=
344 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
345 unsigned size
= array_elems
* reg
->num_components
;
346 const brw_reg_type reg_type
=
347 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
348 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
351 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
354 nir_emit_cf_list(&impl
->body
);
358 fs_visitor::nir_emit_cf_list(exec_list
*list
)
360 exec_list_validate(list
);
361 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
362 switch (node
->type
) {
364 nir_emit_if(nir_cf_node_as_if(node
));
367 case nir_cf_node_loop
:
368 nir_emit_loop(nir_cf_node_as_loop(node
));
371 case nir_cf_node_block
:
372 nir_emit_block(nir_cf_node_as_block(node
));
376 unreachable("Invalid CFG node block");
382 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
384 /* first, put the condition into f0 */
385 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
386 retype(get_nir_src(if_stmt
->condition
),
387 BRW_REGISTER_TYPE_D
));
388 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
390 bld
.IF(BRW_PREDICATE_NORMAL
);
392 nir_emit_cf_list(&if_stmt
->then_list
);
394 /* note: if the else is empty, dead CF elimination will remove it */
395 bld
.emit(BRW_OPCODE_ELSE
);
397 nir_emit_cf_list(&if_stmt
->else_list
);
399 bld
.emit(BRW_OPCODE_ENDIF
);
401 if (devinfo
->gen
< 7)
402 limit_dispatch_width(16, "Non-uniform control flow unsupported "
407 fs_visitor::nir_emit_loop(nir_loop
*loop
)
409 bld
.emit(BRW_OPCODE_DO
);
411 nir_emit_cf_list(&loop
->body
);
413 bld
.emit(BRW_OPCODE_WHILE
);
415 if (devinfo
->gen
< 7)
416 limit_dispatch_width(16, "Non-uniform control flow unsupported "
421 fs_visitor::nir_emit_block(nir_block
*block
)
423 nir_foreach_instr(instr
, block
) {
424 nir_emit_instr(instr
);
429 fs_visitor::nir_emit_instr(nir_instr
*instr
)
431 const fs_builder abld
= bld
.annotate(NULL
, instr
);
433 switch (instr
->type
) {
434 case nir_instr_type_alu
:
435 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
438 case nir_instr_type_deref
:
439 /* Derefs can exist for images but they do nothing */
442 case nir_instr_type_intrinsic
:
444 case MESA_SHADER_VERTEX
:
445 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
447 case MESA_SHADER_TESS_CTRL
:
448 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
450 case MESA_SHADER_TESS_EVAL
:
451 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
453 case MESA_SHADER_GEOMETRY
:
454 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_FRAGMENT
:
457 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_COMPUTE
:
460 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
463 unreachable("unsupported shader stage");
467 case nir_instr_type_tex
:
468 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
471 case nir_instr_type_load_const
:
472 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
475 case nir_instr_type_ssa_undef
:
476 /* We create a new VGRF for undefs on every use (by handling
477 * them in get_nir_src()), rather than for each definition.
478 * This helps register coalescing eliminate MOVs from undef.
482 case nir_instr_type_jump
:
483 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
487 unreachable("unknown instruction type");
492 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
496 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
497 const fs_reg
&result
)
499 if (!instr
->src
[0].src
.is_ssa
||
500 !instr
->src
[0].src
.ssa
->parent_instr
)
503 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
506 nir_alu_instr
*src0
=
507 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
509 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
510 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
513 /* If either opcode has source modifiers, bail.
515 * TODO: We can potentially handle source modifiers if both of the opcodes
516 * we're combining are signed integers.
518 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
519 src0
->src
[0].abs
|| src0
->src
[0].negate
)
522 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
524 /* Element type to extract.*/
525 const brw_reg_type type
= brw_int_type(
526 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
527 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
529 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
530 op0
.type
= brw_type_for_nir_type(devinfo
,
531 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
532 nir_src_bit_size(src0
->src
[0].src
)));
533 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
535 set_saturate(instr
->dest
.saturate
,
536 bld
.MOV(result
, subscript(op0
, type
, element
)));
541 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
542 const fs_reg
&result
)
544 if (!instr
->src
[0].src
.is_ssa
||
545 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
548 nir_intrinsic_instr
*src0
=
549 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
551 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
554 if (!nir_src_is_const(instr
->src
[1].src
) ||
555 !nir_src_is_const(instr
->src
[2].src
))
558 const float value1
= nir_src_as_float(instr
->src
[1].src
);
559 const float value2
= nir_src_as_float(instr
->src
[2].src
);
560 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
563 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
564 assert(value1
== -value2
);
566 fs_reg tmp
= vgrf(glsl_type::int_type
);
568 if (devinfo
->gen
>= 6) {
569 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
570 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
572 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
574 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
575 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
577 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
579 * This negation looks like it's safe in practice, because bits 0:4 will
580 * surely be TRIANGLES
583 if (value1
== -1.0f
) {
587 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
588 g0
, brw_imm_uw(0x3f80));
590 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
591 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
593 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
595 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
596 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
598 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
600 * This negation looks like it's safe in practice, because bits 0:4 will
601 * surely be TRIANGLES
604 if (value1
== -1.0f
) {
608 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
610 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
616 emit_find_msb_using_lzd(const fs_builder
&bld
,
617 const fs_reg
&result
,
625 /* LZD of an absolute value source almost always does the right
626 * thing. There are two problem values:
628 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
629 * 0. However, findMSB(int(0x80000000)) == 30.
631 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
632 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
634 * For a value of zero or negative one, -1 will be returned.
636 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
637 * findMSB(-(1<<x)) should return x-1.
639 * For all negative number cases, including 0x80000000 and
640 * 0xffffffff, the correct value is obtained from LZD if instead of
641 * negating the (already negative) value the logical-not is used. A
642 * conditonal logical-not can be achieved in two instructions.
644 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
646 bld
.ASR(temp
, src
, brw_imm_d(31));
647 bld
.XOR(temp
, temp
, src
);
650 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
651 retype(temp
, BRW_REGISTER_TYPE_UD
));
653 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
654 * from the LSB side. Subtract the result from 31 to convert the MSB
655 * count into an LSB count. If no bits are set, LZD will return 32.
656 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
658 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
659 inst
->src
[0].negate
= true;
663 brw_rnd_mode_from_nir_op (const nir_op op
) {
665 case nir_op_f2f16_rtz
:
666 return BRW_RND_MODE_RTZ
;
667 case nir_op_f2f16_rtne
:
668 return BRW_RND_MODE_RTNE
;
670 unreachable("Operation doesn't support rounding mode");
675 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
677 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
680 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
681 result
.type
= brw_type_for_nir_type(devinfo
,
682 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
683 nir_dest_bit_size(instr
->dest
.dest
)));
686 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
687 op
[i
] = get_nir_src(instr
->src
[i
].src
);
688 op
[i
].type
= brw_type_for_nir_type(devinfo
,
689 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
690 nir_src_bit_size(instr
->src
[i
].src
)));
691 op
[i
].abs
= instr
->src
[i
].abs
;
692 op
[i
].negate
= instr
->src
[i
].negate
;
695 /* We get a bunch of mov's out of the from_ssa pass and they may still
696 * be vectorized. We'll handle them as a special-case. We'll also
697 * handle vecN here because it's basically the same thing.
705 fs_reg temp
= result
;
706 bool need_extra_copy
= false;
707 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
708 if (!instr
->src
[i
].src
.is_ssa
&&
709 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
710 need_extra_copy
= true;
711 temp
= bld
.vgrf(result
.type
, 4);
716 for (unsigned i
= 0; i
< 4; i
++) {
717 if (!(instr
->dest
.write_mask
& (1 << i
)))
720 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
721 inst
= bld
.MOV(offset(temp
, bld
, i
),
722 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
724 inst
= bld
.MOV(offset(temp
, bld
, i
),
725 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
727 inst
->saturate
= instr
->dest
.saturate
;
730 /* In this case the source and destination registers were the same,
731 * so we need to insert an extra set of moves in order to deal with
734 if (need_extra_copy
) {
735 for (unsigned i
= 0; i
< 4; i
++) {
736 if (!(instr
->dest
.write_mask
& (1 << i
)))
739 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
748 /* At this point, we have dealt with any instruction that operates on
749 * more than a single channel. Therefore, we can just adjust the source
750 * and destination registers for that channel and emit the instruction.
752 unsigned channel
= 0;
753 if (nir_op_infos
[instr
->op
].output_size
== 0) {
754 /* Since NIR is doing the scalarizing for us, we should only ever see
755 * vectorized operations with a single channel.
757 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
758 channel
= ffs(instr
->dest
.write_mask
) - 1;
760 result
= offset(result
, bld
, channel
);
763 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
764 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
765 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
771 if (optimize_extract_to_float(instr
, result
))
773 inst
= bld
.MOV(result
, op
[0]);
774 inst
->saturate
= instr
->dest
.saturate
;
777 case nir_op_f2f16_rtne
:
778 case nir_op_f2f16_rtz
:
779 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
780 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
783 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
784 * on the HW gen, it is a special hw opcode or just a MOV, and
785 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
787 * But if we want to use that opcode, we need to provide support on
788 * different optimizations and lowerings. As right now HF support is
789 * only for gen8+, it will be better to use directly the MOV, and use
790 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
794 inst
= bld
.MOV(result
, op
[0]);
795 inst
->saturate
= instr
->dest
.saturate
;
805 op
[0].type
= BRW_REGISTER_TYPE_D
;
806 op
[0].negate
= !op
[0].negate
;
828 inst
= bld
.MOV(result
, op
[0]);
829 inst
->saturate
= instr
->dest
.saturate
;
833 assert(!instr
->dest
.saturate
);
835 /* Straightforward since the source can be assumed to be either
836 * strictly >= 0 or strictly <= 0 depending on the setting of the
839 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
841 inst
= (op
[0].negate
)
842 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
843 : bld
.MOV(result
, brw_imm_f(1.0f
));
845 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
846 } else if (type_sz(op
[0].type
) < 8) {
847 /* AND(val, 0x80000000) gives the sign bit.
849 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
852 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
854 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
855 op
[0].type
= BRW_REGISTER_TYPE_UD
;
856 result
.type
= BRW_REGISTER_TYPE_UD
;
857 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
859 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
860 inst
->predicate
= BRW_PREDICATE_NORMAL
;
862 /* For doubles we do the same but we need to consider:
864 * - 2-src instructions can't operate with 64-bit immediates
865 * - The sign is encoded in the high 32-bit of each DF
866 * - We need to produce a DF result.
869 fs_reg zero
= vgrf(glsl_type::double_type
);
870 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
871 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
873 bld
.MOV(result
, zero
);
875 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
876 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
877 brw_imm_ud(0x80000000u
));
879 set_predicate(BRW_PREDICATE_NORMAL
,
880 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
886 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
887 inst
->saturate
= instr
->dest
.saturate
;
891 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
892 inst
->saturate
= instr
->dest
.saturate
;
896 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
897 inst
->saturate
= instr
->dest
.saturate
;
901 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
902 inst
->saturate
= instr
->dest
.saturate
;
906 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
907 inst
->saturate
= instr
->dest
.saturate
;
911 if (fs_key
->high_quality_derivatives
) {
912 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
914 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
916 inst
->saturate
= instr
->dest
.saturate
;
918 case nir_op_fddx_fine
:
919 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
920 inst
->saturate
= instr
->dest
.saturate
;
922 case nir_op_fddx_coarse
:
923 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
924 inst
->saturate
= instr
->dest
.saturate
;
927 if (fs_key
->high_quality_derivatives
) {
928 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
930 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
932 inst
->saturate
= instr
->dest
.saturate
;
934 case nir_op_fddy_fine
:
935 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
936 inst
->saturate
= instr
->dest
.saturate
;
938 case nir_op_fddy_coarse
:
939 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
940 inst
->saturate
= instr
->dest
.saturate
;
945 inst
= bld
.ADD(result
, op
[0], op
[1]);
946 inst
->saturate
= instr
->dest
.saturate
;
949 case nir_op_uadd_sat
:
950 inst
= bld
.ADD(result
, op
[0], op
[1]);
951 inst
->saturate
= true;
955 inst
= bld
.MUL(result
, op
[0], op
[1]);
956 inst
->saturate
= instr
->dest
.saturate
;
960 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
961 bld
.MUL(result
, op
[0], op
[1]);
964 case nir_op_imul_high
:
965 case nir_op_umul_high
:
966 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
967 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
972 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
973 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
976 case nir_op_uadd_carry
:
977 unreachable("Should have been lowered by carry_to_arith().");
979 case nir_op_usub_borrow
:
980 unreachable("Should have been lowered by borrow_to_arith().");
984 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
985 * appears that our hardware just does the right thing for signed
988 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
989 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
993 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
994 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
996 /* Math instructions don't support conditional mod */
997 inst
= bld
.MOV(bld
.null_reg_d(), result
);
998 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1000 /* Now, we need to determine if signs of the sources are different.
1001 * When we XOR the sources, the top bit is 0 if they are the same and 1
1002 * if they are different. We can then use a conditional modifier to
1003 * turn that into a predicate. This leads us to an XOR.l instruction.
1005 * Technically, according to the PRM, you're not allowed to use .l on a
1006 * XOR instruction. However, emperical experiments and Curro's reading
1007 * of the simulator source both indicate that it's safe.
1009 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1010 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1011 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1012 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1014 /* If the result of the initial remainder operation is non-zero and the
1015 * two sources have different signs, add in a copy of op[1] to get the
1016 * final integer modulus value.
1018 inst
= bld
.ADD(result
, result
, op
[1]);
1019 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1026 case nir_op_fne32
: {
1027 fs_reg dest
= result
;
1029 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1031 dest
= bld
.vgrf(op
[0].type
, 1);
1033 brw_conditional_mod cond
;
1034 switch (instr
->op
) {
1036 cond
= BRW_CONDITIONAL_L
;
1039 cond
= BRW_CONDITIONAL_GE
;
1042 cond
= BRW_CONDITIONAL_Z
;
1045 cond
= BRW_CONDITIONAL_NZ
;
1048 unreachable("bad opcode");
1051 bld
.CMP(dest
, op
[0], op
[1], cond
);
1053 if (bit_size
> 32) {
1054 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1055 } else if(bit_size
< 32) {
1056 /* When we convert the result to 32-bit we need to be careful and do
1057 * it as a signed conversion to get sign extension (for 32-bit true)
1059 const brw_reg_type src_type
=
1060 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1062 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1072 case nir_op_ine32
: {
1073 fs_reg dest
= result
;
1075 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1077 dest
= bld
.vgrf(op
[0].type
, 1);
1079 brw_conditional_mod cond
;
1080 switch (instr
->op
) {
1083 cond
= BRW_CONDITIONAL_L
;
1087 cond
= BRW_CONDITIONAL_GE
;
1090 cond
= BRW_CONDITIONAL_Z
;
1093 cond
= BRW_CONDITIONAL_NZ
;
1096 unreachable("bad opcode");
1098 bld
.CMP(dest
, op
[0], op
[1], cond
);
1100 if (bit_size
> 32) {
1101 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1102 } else if (bit_size
< 32) {
1103 /* When we convert the result to 32-bit we need to be careful and do
1104 * it as a signed conversion to get sign extension (for 32-bit true)
1106 const brw_reg_type src_type
=
1107 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1109 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1115 if (devinfo
->gen
>= 8) {
1116 op
[0] = resolve_source_modifiers(op
[0]);
1118 bld
.NOT(result
, op
[0]);
1121 if (devinfo
->gen
>= 8) {
1122 op
[0] = resolve_source_modifiers(op
[0]);
1123 op
[1] = resolve_source_modifiers(op
[1]);
1125 bld
.XOR(result
, op
[0], op
[1]);
1128 if (devinfo
->gen
>= 8) {
1129 op
[0] = resolve_source_modifiers(op
[0]);
1130 op
[1] = resolve_source_modifiers(op
[1]);
1132 bld
.OR(result
, op
[0], op
[1]);
1135 if (devinfo
->gen
>= 8) {
1136 op
[0] = resolve_source_modifiers(op
[0]);
1137 op
[1] = resolve_source_modifiers(op
[1]);
1139 bld
.AND(result
, op
[0], op
[1]);
1145 case nir_op_b32all_fequal2
:
1146 case nir_op_b32all_iequal2
:
1147 case nir_op_b32all_fequal3
:
1148 case nir_op_b32all_iequal3
:
1149 case nir_op_b32all_fequal4
:
1150 case nir_op_b32all_iequal4
:
1151 case nir_op_b32any_fnequal2
:
1152 case nir_op_b32any_inequal2
:
1153 case nir_op_b32any_fnequal3
:
1154 case nir_op_b32any_inequal3
:
1155 case nir_op_b32any_fnequal4
:
1156 case nir_op_b32any_inequal4
:
1157 unreachable("Lowered by nir_lower_alu_reductions");
1159 case nir_op_fnoise1_1
:
1160 case nir_op_fnoise1_2
:
1161 case nir_op_fnoise1_3
:
1162 case nir_op_fnoise1_4
:
1163 case nir_op_fnoise2_1
:
1164 case nir_op_fnoise2_2
:
1165 case nir_op_fnoise2_3
:
1166 case nir_op_fnoise2_4
:
1167 case nir_op_fnoise3_1
:
1168 case nir_op_fnoise3_2
:
1169 case nir_op_fnoise3_3
:
1170 case nir_op_fnoise3_4
:
1171 case nir_op_fnoise4_1
:
1172 case nir_op_fnoise4_2
:
1173 case nir_op_fnoise4_3
:
1174 case nir_op_fnoise4_4
:
1175 unreachable("not reached: should be handled by lower_noise");
1178 unreachable("not reached: should be handled by ldexp_to_arith()");
1181 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1182 inst
->saturate
= instr
->dest
.saturate
;
1186 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1187 inst
->saturate
= instr
->dest
.saturate
;
1191 case nir_op_f2b32
: {
1192 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1193 if (bit_size
== 64) {
1194 /* two-argument instructions can't take 64-bit immediates */
1198 if (instr
->op
== nir_op_f2b32
) {
1199 zero
= vgrf(glsl_type::double_type
);
1200 tmp
= vgrf(glsl_type::double_type
);
1201 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1203 zero
= vgrf(glsl_type::int64_t_type
);
1204 tmp
= vgrf(glsl_type::int64_t_type
);
1205 bld
.MOV(zero
, brw_imm_q(0));
1208 /* A SIMD16 execution needs to be split in two instructions, so use
1209 * a vgrf instead of the flag register as dst so instruction splitting
1212 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1213 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1216 if (bit_size
== 32) {
1217 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1219 assert(bit_size
== 16);
1220 zero
= instr
->op
== nir_op_f2b32
?
1221 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1223 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1229 inst
= bld
.RNDZ(result
, op
[0]);
1230 inst
->saturate
= instr
->dest
.saturate
;
1233 case nir_op_fceil
: {
1234 op
[0].negate
= !op
[0].negate
;
1235 fs_reg temp
= vgrf(glsl_type::float_type
);
1236 bld
.RNDD(temp
, op
[0]);
1238 inst
= bld
.MOV(result
, temp
);
1239 inst
->saturate
= instr
->dest
.saturate
;
1243 inst
= bld
.RNDD(result
, op
[0]);
1244 inst
->saturate
= instr
->dest
.saturate
;
1247 inst
= bld
.FRC(result
, op
[0]);
1248 inst
->saturate
= instr
->dest
.saturate
;
1250 case nir_op_fround_even
:
1251 inst
= bld
.RNDE(result
, op
[0]);
1252 inst
->saturate
= instr
->dest
.saturate
;
1255 case nir_op_fquantize2f16
: {
1256 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1257 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1258 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1260 /* The destination stride must be at least as big as the source stride. */
1261 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1264 /* Check for denormal */
1265 fs_reg abs_src0
= op
[0];
1266 abs_src0
.abs
= true;
1267 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1269 /* Get the appropriately signed zero */
1270 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1271 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1272 brw_imm_ud(0x80000000));
1273 /* Do the actual F32 -> F16 -> F32 conversion */
1274 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1275 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1276 /* Select that or zero based on normal status */
1277 inst
= bld
.SEL(result
, zero
, tmp32
);
1278 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1279 inst
->saturate
= instr
->dest
.saturate
;
1286 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1287 inst
->saturate
= instr
->dest
.saturate
;
1293 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1294 inst
->saturate
= instr
->dest
.saturate
;
1297 case nir_op_pack_snorm_2x16
:
1298 case nir_op_pack_snorm_4x8
:
1299 case nir_op_pack_unorm_2x16
:
1300 case nir_op_pack_unorm_4x8
:
1301 case nir_op_unpack_snorm_2x16
:
1302 case nir_op_unpack_snorm_4x8
:
1303 case nir_op_unpack_unorm_2x16
:
1304 case nir_op_unpack_unorm_4x8
:
1305 case nir_op_unpack_half_2x16
:
1306 case nir_op_pack_half_2x16
:
1307 unreachable("not reached: should be handled by lower_packing_builtins");
1309 case nir_op_unpack_half_2x16_split_x
:
1310 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1311 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1312 inst
->saturate
= instr
->dest
.saturate
;
1314 case nir_op_unpack_half_2x16_split_y
:
1315 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1316 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1317 inst
->saturate
= instr
->dest
.saturate
;
1320 case nir_op_pack_64_2x32_split
:
1321 case nir_op_pack_32_2x16_split
:
1322 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1325 case nir_op_unpack_64_2x32_split_x
:
1326 case nir_op_unpack_64_2x32_split_y
: {
1327 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1328 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1330 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1334 case nir_op_unpack_32_2x16_split_x
:
1335 case nir_op_unpack_32_2x16_split_y
: {
1336 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1337 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1339 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1344 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1345 inst
->saturate
= instr
->dest
.saturate
;
1348 case nir_op_bitfield_reverse
:
1349 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1350 bld
.BFREV(result
, op
[0]);
1353 case nir_op_bit_count
:
1354 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1355 bld
.CBIT(result
, op
[0]);
1358 case nir_op_ufind_msb
: {
1359 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1360 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1364 case nir_op_ifind_msb
: {
1365 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1367 if (devinfo
->gen
< 7) {
1368 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1370 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1372 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1373 * count from the LSB side. If FBH didn't return an error
1374 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1375 * count into an LSB count.
1377 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1379 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1380 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1381 inst
->src
[0].negate
= true;
1386 case nir_op_find_lsb
:
1387 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1389 if (devinfo
->gen
< 7) {
1390 fs_reg temp
= vgrf(glsl_type::int_type
);
1392 /* (x & -x) generates a value that consists of only the LSB of x.
1393 * For all powers of 2, findMSB(y) == findLSB(y).
1395 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1396 fs_reg negated_src
= src
;
1398 /* One must be negated, and the other must be non-negated. It
1399 * doesn't matter which is which.
1401 negated_src
.negate
= true;
1404 bld
.AND(temp
, src
, negated_src
);
1405 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1407 bld
.FBL(result
, op
[0]);
1411 case nir_op_ubitfield_extract
:
1412 case nir_op_ibitfield_extract
:
1413 unreachable("should have been lowered");
1416 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1417 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1420 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1421 bld
.BFI1(result
, op
[0], op
[1]);
1424 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1425 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1428 case nir_op_bitfield_insert
:
1429 unreachable("not reached: should have been lowered");
1432 bld
.SHL(result
, op
[0], op
[1]);
1435 bld
.ASR(result
, op
[0], op
[1]);
1438 bld
.SHR(result
, op
[0], op
[1]);
1441 case nir_op_pack_half_2x16_split
:
1442 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1446 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1447 inst
->saturate
= instr
->dest
.saturate
;
1451 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1452 inst
->saturate
= instr
->dest
.saturate
;
1455 case nir_op_b32csel
:
1456 if (optimize_frontfacing_ternary(instr
, result
))
1459 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1460 inst
= bld
.SEL(result
, op
[1], op
[2]);
1461 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1464 case nir_op_extract_u8
:
1465 case nir_op_extract_i8
: {
1466 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1471 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1472 * Use two instructions and a word or DWord intermediate integer type.
1474 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1475 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1477 if (instr
->op
== nir_op_extract_i8
) {
1478 /* If we need to sign extend, extract to a word first */
1479 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1480 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1481 bld
.MOV(result
, w_temp
);
1483 /* Otherwise use an AND with 0xff and a word type */
1484 bld
.AND(result
, subscript(op
[0], type
, byte
/ 2), brw_imm_uw(0xff));
1487 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1488 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1493 case nir_op_extract_u16
:
1494 case nir_op_extract_i16
: {
1495 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1496 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1497 bld
.MOV(result
, subscript(op
[0], type
, word
));
1502 unreachable("unhandled instruction");
1505 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1506 * to sign extend the low bit to 0/~0
1508 if (devinfo
->gen
<= 5 &&
1509 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1510 fs_reg masked
= vgrf(glsl_type::int_type
);
1511 bld
.AND(masked
, result
, brw_imm_d(1));
1512 masked
.negate
= true;
1513 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1518 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1519 nir_load_const_instr
*instr
)
1521 const brw_reg_type reg_type
=
1522 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1523 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1525 switch (instr
->def
.bit_size
) {
1527 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1528 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1532 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1533 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1537 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1538 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1542 assert(devinfo
->gen
>= 7);
1543 if (devinfo
->gen
== 7) {
1544 /* We don't get 64-bit integer types until gen8 */
1545 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1546 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1547 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1550 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1551 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1556 unreachable("Invalid bit size");
1559 nir_ssa_values
[instr
->def
.index
] = reg
;
1563 fs_visitor::get_nir_src(const nir_src
&src
)
1567 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1568 const brw_reg_type reg_type
=
1569 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1570 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1572 reg
= nir_ssa_values
[src
.ssa
->index
];
1575 /* We don't handle indirects on locals */
1576 assert(src
.reg
.indirect
== NULL
);
1577 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1578 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1581 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1582 /* The only 64-bit type available on gen7 is DF, so use that. */
1583 reg
.type
= BRW_REGISTER_TYPE_DF
;
1585 /* To avoid floating-point denorm flushing problems, set the type by
1586 * default to an integer type - instructions that need floating point
1587 * semantics will set this to F if they need to
1589 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1590 BRW_REGISTER_TYPE_D
);
1597 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1599 * This function should not be called on any value which may be 64 bits.
1600 * We could theoretically support 64-bit on gen8+ but we choose not to
1601 * because it wouldn't work in general (no gen7 support) and there are
1602 * enough restrictions in 64-bit immediates that you can't take the return
1603 * value and treat it the same as the result of get_nir_src().
1606 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1608 assert(nir_src_bit_size(src
) == 32);
1609 return nir_src_is_const(src
) ?
1610 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1614 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1617 const brw_reg_type reg_type
=
1618 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1619 dest
.ssa
.bit_size
== 8 ?
1620 BRW_REGISTER_TYPE_D
:
1621 BRW_REGISTER_TYPE_F
);
1622 nir_ssa_values
[dest
.ssa
.index
] =
1623 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1624 return nir_ssa_values
[dest
.ssa
.index
];
1626 /* We don't handle indirects on locals */
1627 assert(dest
.reg
.indirect
== NULL
);
1628 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1629 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1634 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1637 for (unsigned i
= 0; i
< 4; i
++) {
1638 if (!((wr_mask
>> i
) & 1))
1641 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1642 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1643 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1644 if (new_inst
->src
[j
].file
== VGRF
)
1645 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1652 emit_pixel_interpolater_send(const fs_builder
&bld
,
1657 glsl_interp_mode interpolation
)
1659 struct brw_wm_prog_data
*wm_prog_data
=
1660 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1662 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1663 /* 2 floats per slot returned */
1664 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1665 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1667 wm_prog_data
->pulls_bary
= true;
1673 * Computes 1 << x, given a D/UD register containing some value x.
1676 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1678 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1680 fs_reg result
= bld
.vgrf(x
.type
, 1);
1681 fs_reg one
= bld
.vgrf(x
.type
, 1);
1683 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1684 bld
.SHL(result
, one
, x
);
1689 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1691 assert(stage
== MESA_SHADER_GEOMETRY
);
1693 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1695 if (gs_compile
->control_data_header_size_bits
== 0)
1698 /* We can only do EndPrimitive() functionality when the control data
1699 * consists of cut bits. Fortunately, the only time it isn't is when the
1700 * output type is points, in which case EndPrimitive() is a no-op.
1702 if (gs_prog_data
->control_data_format
!=
1703 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1707 /* Cut bits use one bit per vertex. */
1708 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1710 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1711 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1713 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1714 * vertex n, 0 otherwise. So all we need to do here is mark bit
1715 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1716 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1717 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1719 * Note that if EndPrimitive() is called before emitting any vertices, this
1720 * will cause us to set bit 31 of the control_data_bits register to 1.
1721 * That's fine because:
1723 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1724 * output, so the hardware will ignore cut bit 31.
1726 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1727 * last vertex, so setting cut bit 31 has no effect (since the primitive
1728 * is automatically ended when the GS terminates).
1730 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1731 * control_data_bits register to 0 when the first vertex is emitted.
1734 const fs_builder abld
= bld
.annotate("end primitive");
1736 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1737 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1738 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1739 fs_reg mask
= intexp2(abld
, prev_count
);
1740 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1741 * attention to the lower 5 bits of its second source argument, so on this
1742 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1743 * ((vertex_count - 1) % 32).
1745 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1749 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1751 assert(stage
== MESA_SHADER_GEOMETRY
);
1752 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1754 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1756 const fs_builder abld
= bld
.annotate("emit control data bits");
1757 const fs_builder fwa_bld
= bld
.exec_all();
1759 /* We use a single UD register to accumulate control data bits (32 bits
1760 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1763 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1764 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1765 * use the Channel Mask phase to enable/disable which DWord within that
1766 * group to write. (Remember, different SIMD8 channels may have emitted
1767 * different numbers of vertices, so we may need per-slot offsets.)
1769 * Channel masking presents an annoying problem: we may have to replicate
1770 * the data up to 4 times:
1772 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1774 * To avoid penalizing shaders that emit a small number of vertices, we
1775 * can avoid these sometimes: if the size of the control data header is
1776 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1777 * land in the same 128-bit group, so we can skip per-slot offsets.
1779 * Similarly, if the control data header is <= 32 bits, there is only one
1780 * DWord, so we can skip channel masks.
1782 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1784 fs_reg channel_mask
, per_slot_offset
;
1786 if (gs_compile
->control_data_header_size_bits
> 32) {
1787 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1788 channel_mask
= vgrf(glsl_type::uint_type
);
1791 if (gs_compile
->control_data_header_size_bits
> 128) {
1792 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1793 per_slot_offset
= vgrf(glsl_type::uint_type
);
1796 /* Figure out which DWord we're trying to write to using the formula:
1798 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1800 * Since bits_per_vertex is a power of two, and is known at compile
1801 * time, this can be optimized to:
1803 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1805 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1806 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1807 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1808 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1809 unsigned log2_bits_per_vertex
=
1810 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1811 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1813 if (per_slot_offset
.file
!= BAD_FILE
) {
1814 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1815 * the appropriate OWord within the control data header.
1817 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1820 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1821 * write to the appropriate DWORD within the OWORD.
1823 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1824 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1825 channel_mask
= intexp2(fwa_bld
, channel
);
1826 /* Then the channel masks need to be in bits 23:16. */
1827 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1830 /* Store the control data bits in the message payload and send it. */
1832 if (channel_mask
.file
!= BAD_FILE
)
1833 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1834 if (per_slot_offset
.file
!= BAD_FILE
)
1837 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1838 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1840 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1841 if (per_slot_offset
.file
!= BAD_FILE
)
1842 sources
[i
++] = per_slot_offset
;
1843 if (channel_mask
.file
!= BAD_FILE
)
1844 sources
[i
++] = channel_mask
;
1846 sources
[i
++] = this->control_data_bits
;
1849 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1850 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1852 /* We need to increment Global Offset by 256-bits to make room for
1853 * Broadwell's extra "Vertex Count" payload at the beginning of the
1854 * URB entry. Since this is an OWord message, Global Offset is counted
1855 * in 128-bit units, so we must set it to 2.
1857 if (gs_prog_data
->static_vertex_count
== -1)
1862 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1865 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1867 /* Note: we are calling this *before* increasing vertex_count, so
1868 * this->vertex_count == vertex_count - 1 in the formula above.
1871 /* Stream mode uses 2 bits per vertex */
1872 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1874 /* Must be a valid stream */
1875 assert(stream_id
< MAX_VERTEX_STREAMS
);
1877 /* Control data bits are initialized to 0 so we don't have to set any
1878 * bits when sending vertices to stream 0.
1883 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1885 /* reg::sid = stream_id */
1886 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1887 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1889 /* reg:shift_count = 2 * (vertex_count - 1) */
1890 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1891 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1893 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1894 * attention to the lower 5 bits of its second source argument, so on this
1895 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1896 * stream_id << ((2 * (vertex_count - 1)) % 32).
1898 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1899 abld
.SHL(mask
, sid
, shift_count
);
1900 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1904 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1907 assert(stage
== MESA_SHADER_GEOMETRY
);
1909 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1911 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1912 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1914 /* Haswell and later hardware ignores the "Render Stream Select" bits
1915 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1916 * and instead sends all primitives down the pipeline for rasterization.
1917 * If the SOL stage is enabled, "Render Stream Select" is honored and
1918 * primitives bound to non-zero streams are discarded after stream output.
1920 * Since the only purpose of primives sent to non-zero streams is to
1921 * be recorded by transform feedback, we can simply discard all geometry
1922 * bound to these streams when transform feedback is disabled.
1924 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1927 /* If we're outputting 32 control data bits or less, then we can wait
1928 * until the shader is over to output them all. Otherwise we need to
1929 * output them as we go. Now is the time to do it, since we're about to
1930 * output the vertex_count'th vertex, so it's guaranteed that the
1931 * control data bits associated with the (vertex_count - 1)th vertex are
1934 if (gs_compile
->control_data_header_size_bits
> 32) {
1935 const fs_builder abld
=
1936 bld
.annotate("emit vertex: emit control data bits");
1938 /* Only emit control data bits if we've finished accumulating a batch
1939 * of 32 bits. This is the case when:
1941 * (vertex_count * bits_per_vertex) % 32 == 0
1943 * (in other words, when the last 5 bits of vertex_count *
1944 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1945 * integer n (which is always the case, since bits_per_vertex is
1946 * always 1 or 2), this is equivalent to requiring that the last 5-n
1947 * bits of vertex_count are 0:
1949 * vertex_count & (2^(5-n) - 1) == 0
1951 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1954 * vertex_count & (32 / bits_per_vertex - 1) == 0
1956 * TODO: If vertex_count is an immediate, we could do some of this math
1957 * at compile time...
1960 abld
.AND(bld
.null_reg_d(), vertex_count
,
1961 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1962 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1964 abld
.IF(BRW_PREDICATE_NORMAL
);
1965 /* If vertex_count is 0, then no control data bits have been
1966 * accumulated yet, so we can skip emitting them.
1968 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1969 BRW_CONDITIONAL_NEQ
);
1970 abld
.IF(BRW_PREDICATE_NORMAL
);
1971 emit_gs_control_data_bits(vertex_count
);
1972 abld
.emit(BRW_OPCODE_ENDIF
);
1974 /* Reset control_data_bits to 0 so we can start accumulating a new
1977 * Note: in the case where vertex_count == 0, this neutralizes the
1978 * effect of any call to EndPrimitive() that the shader may have
1979 * made before outputting its first vertex.
1981 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1982 inst
->force_writemask_all
= true;
1983 abld
.emit(BRW_OPCODE_ENDIF
);
1986 emit_urb_writes(vertex_count
);
1988 /* In stream mode we have to set control data bits for all vertices
1989 * unless we have disabled control data bits completely (which we do
1990 * do for GL_POINTS outputs that don't use streams).
1992 if (gs_compile
->control_data_header_size_bits
> 0 &&
1993 gs_prog_data
->control_data_format
==
1994 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1995 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2000 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2001 const nir_src
&vertex_src
,
2002 unsigned base_offset
,
2003 const nir_src
&offset_src
,
2004 unsigned num_components
,
2005 unsigned first_component
)
2007 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2008 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2010 /* TODO: figure out push input layout for invocations == 1 */
2011 /* TODO: make this work with 64-bit inputs */
2012 if (gs_prog_data
->invocations
== 1 &&
2013 type_sz(dst
.type
) <= 4 &&
2014 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2015 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2016 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2017 nir_src_as_uint(vertex_src
) * push_reg_count
;
2018 for (unsigned i
= 0; i
< num_components
; i
++) {
2019 bld
.MOV(offset(dst
, bld
, i
),
2020 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2025 /* Resort to the pull model. Ensure the VUE handles are provided. */
2026 assert(gs_prog_data
->base
.include_vue_handles
);
2028 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2029 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2031 if (gs_prog_data
->invocations
== 1) {
2032 if (nir_src_is_const(vertex_src
)) {
2033 /* The vertex index is constant; just select the proper URB handle. */
2035 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2036 BRW_REGISTER_TYPE_UD
);
2038 /* The vertex index is non-constant. We need to use indirect
2039 * addressing to fetch the proper URB handle.
2041 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2042 * indicating that channel <n> should read the handle from
2043 * DWord <n>. We convert that to bytes by multiplying by 4.
2045 * Next, we convert the vertex index to bytes by multiplying
2046 * by 32 (shifting by 5), and add the two together. This is
2047 * the final indirect byte offset.
2049 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2050 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2051 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2052 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2054 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2055 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2056 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2057 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2058 /* Convert vertex_index to bytes (multiply by 32) */
2059 bld
.SHL(vertex_offset_bytes
,
2060 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2062 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2064 /* Use first_icp_handle as the base offset. There is one register
2065 * of URB handles per vertex, so inform the register allocator that
2066 * we might read up to nir->info.gs.vertices_in registers.
2068 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2069 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2070 fs_reg(icp_offset_bytes
),
2071 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2074 assert(gs_prog_data
->invocations
> 1);
2076 if (nir_src_is_const(vertex_src
)) {
2077 unsigned vertex
= nir_src_as_uint(vertex_src
);
2078 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2080 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2081 BRW_REGISTER_TYPE_UD
));
2083 /* The vertex index is non-constant. We need to use indirect
2084 * addressing to fetch the proper URB handle.
2087 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2089 /* Convert vertex_index to bytes (multiply by 4) */
2090 bld
.SHL(icp_offset_bytes
,
2091 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2094 /* Use first_icp_handle as the base offset. There is one DWord
2095 * of URB handles per vertex, so inform the register allocator that
2096 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2098 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2099 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2100 fs_reg(icp_offset_bytes
),
2101 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2108 fs_reg tmp_dst
= dst
;
2109 fs_reg indirect_offset
= get_nir_src(offset_src
);
2110 unsigned num_iterations
= 1;
2111 unsigned orig_num_components
= num_components
;
2113 if (type_sz(dst
.type
) == 8) {
2114 if (num_components
> 2) {
2118 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2120 first_component
= first_component
/ 2;
2123 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2124 if (nir_src_is_const(offset_src
)) {
2125 /* Constant indexing - use global offset. */
2126 if (first_component
!= 0) {
2127 unsigned read_components
= num_components
+ first_component
;
2128 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2129 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2130 inst
->size_written
= read_components
*
2131 tmp
.component_size(inst
->exec_size
);
2132 for (unsigned i
= 0; i
< num_components
; i
++) {
2133 bld
.MOV(offset(tmp_dst
, bld
, i
),
2134 offset(tmp
, bld
, i
+ first_component
));
2137 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2139 inst
->size_written
= num_components
*
2140 tmp_dst
.component_size(inst
->exec_size
);
2142 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2145 /* Indirect indexing - use per-slot offsets as well. */
2146 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2147 unsigned read_components
= num_components
+ first_component
;
2148 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2149 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2150 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2151 if (first_component
!= 0) {
2152 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2154 inst
->size_written
= read_components
*
2155 tmp
.component_size(inst
->exec_size
);
2156 for (unsigned i
= 0; i
< num_components
; i
++) {
2157 bld
.MOV(offset(tmp_dst
, bld
, i
),
2158 offset(tmp
, bld
, i
+ first_component
));
2161 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2163 inst
->size_written
= num_components
*
2164 tmp_dst
.component_size(inst
->exec_size
);
2166 inst
->offset
= base_offset
;
2170 if (type_sz(dst
.type
) == 8) {
2171 shuffle_from_32bit_read(bld
,
2172 offset(dst
, bld
, iter
* 2),
2173 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2178 if (num_iterations
> 1) {
2179 num_components
= orig_num_components
- 2;
2180 if(nir_src_is_const(offset_src
)) {
2183 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2184 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2185 indirect_offset
= new_indirect
;
2192 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2194 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2196 if (nir_src_is_const(*offset_src
)) {
2197 /* The only constant offset we should find is 0. brw_nir.c's
2198 * add_const_offset_to_base() will fold other constant offsets
2199 * into instr->const_index[0].
2201 assert(nir_src_as_uint(*offset_src
) == 0);
2205 return get_nir_src(*offset_src
);
2209 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2210 nir_intrinsic_instr
*instr
)
2212 assert(stage
== MESA_SHADER_VERTEX
);
2215 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2216 dest
= get_nir_dest(instr
->dest
);
2218 switch (instr
->intrinsic
) {
2219 case nir_intrinsic_load_vertex_id
:
2220 case nir_intrinsic_load_base_vertex
:
2221 unreachable("should be lowered by nir_lower_system_values()");
2223 case nir_intrinsic_load_input
: {
2224 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2225 unsigned first_component
= nir_intrinsic_component(instr
);
2226 unsigned num_components
= instr
->num_components
;
2228 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2230 if (type_sz(dest
.type
) == 8)
2231 first_component
/= 2;
2233 /* For 16-bit support maybe a temporary will be needed to copy from
2236 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2237 first_component
, num_components
);
2241 case nir_intrinsic_load_vertex_id_zero_base
:
2242 case nir_intrinsic_load_instance_id
:
2243 case nir_intrinsic_load_base_instance
:
2244 case nir_intrinsic_load_draw_id
:
2245 case nir_intrinsic_load_first_vertex
:
2246 case nir_intrinsic_load_is_indexed_draw
:
2247 unreachable("lowered by brw_nir_lower_vs_inputs");
2250 nir_emit_intrinsic(bld
, instr
);
2256 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2257 nir_intrinsic_instr
*instr
)
2259 assert(stage
== MESA_SHADER_TESS_CTRL
);
2260 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2261 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2264 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2265 dst
= get_nir_dest(instr
->dest
);
2267 switch (instr
->intrinsic
) {
2268 case nir_intrinsic_load_primitive_id
:
2269 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2271 case nir_intrinsic_load_invocation_id
:
2272 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2274 case nir_intrinsic_load_patch_vertices_in
:
2275 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2276 brw_imm_d(tcs_key
->input_vertices
));
2279 case nir_intrinsic_barrier
: {
2280 if (tcs_prog_data
->instances
== 1)
2283 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2284 fs_reg m0_2
= component(m0
, 2);
2286 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2288 /* Zero the message header */
2289 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2291 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2292 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2293 brw_imm_ud(INTEL_MASK(16, 13)));
2295 /* Shift it up to bits 27:24. */
2296 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2298 /* Set the Barrier Count and the enable bit */
2299 chanbld
.OR(m0_2
, m0_2
,
2300 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2302 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2306 case nir_intrinsic_load_input
:
2307 unreachable("nir_lower_io should never give us these.");
2310 case nir_intrinsic_load_per_vertex_input
: {
2311 fs_reg indirect_offset
= get_indirect_offset(instr
);
2312 unsigned imm_offset
= instr
->const_index
[0];
2314 const nir_src
&vertex_src
= instr
->src
[0];
2320 if (nir_src_is_const(vertex_src
)) {
2321 /* Emit a MOV to resolve <0,1,0> regioning. */
2322 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2323 unsigned vertex
= nir_src_as_uint(vertex_src
);
2325 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2326 BRW_REGISTER_TYPE_UD
));
2327 } else if (tcs_prog_data
->instances
== 1 &&
2328 vertex_src
.is_ssa
&&
2329 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2330 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2331 /* For the common case of only 1 instance, an array index of
2332 * gl_InvocationID means reading g1. Skip all the indirect work.
2334 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2336 /* The vertex index is non-constant. We need to use indirect
2337 * addressing to fetch the proper URB handle.
2339 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2341 /* Each ICP handle is a single DWord (4 bytes) */
2342 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2343 bld
.SHL(vertex_offset_bytes
,
2344 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2347 /* Start at g1. We might read up to 4 registers. */
2348 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2349 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2350 brw_imm_ud(4 * REG_SIZE
));
2353 /* We can only read two double components with each URB read, so
2354 * we send two read messages in that case, each one loading up to
2355 * two double components.
2357 unsigned num_iterations
= 1;
2358 unsigned num_components
= instr
->num_components
;
2359 unsigned first_component
= nir_intrinsic_component(instr
);
2360 fs_reg orig_dst
= dst
;
2361 if (type_sz(dst
.type
) == 8) {
2362 first_component
= first_component
/ 2;
2363 if (instr
->num_components
> 2) {
2368 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2372 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2373 if (indirect_offset
.file
== BAD_FILE
) {
2374 /* Constant indexing - use global offset. */
2375 if (first_component
!= 0) {
2376 unsigned read_components
= num_components
+ first_component
;
2377 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2378 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2379 for (unsigned i
= 0; i
< num_components
; i
++) {
2380 bld
.MOV(offset(dst
, bld
, i
),
2381 offset(tmp
, bld
, i
+ first_component
));
2384 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2386 inst
->offset
= imm_offset
;
2389 /* Indirect indexing - use per-slot offsets as well. */
2390 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2391 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2392 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2393 if (first_component
!= 0) {
2394 unsigned read_components
= num_components
+ first_component
;
2395 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2396 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2398 for (unsigned i
= 0; i
< num_components
; i
++) {
2399 bld
.MOV(offset(dst
, bld
, i
),
2400 offset(tmp
, bld
, i
+ first_component
));
2403 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2406 inst
->offset
= imm_offset
;
2409 inst
->size_written
= (num_components
+ first_component
) *
2410 inst
->dst
.component_size(inst
->exec_size
);
2412 /* If we are reading 64-bit data using 32-bit read messages we need
2413 * build proper 64-bit data elements by shuffling the low and high
2414 * 32-bit components around like we do for other things like UBOs
2417 if (type_sz(dst
.type
) == 8) {
2418 shuffle_from_32bit_read(bld
,
2419 offset(orig_dst
, bld
, iter
* 2),
2420 retype(dst
, BRW_REGISTER_TYPE_D
),
2424 /* Copy the temporary to the destination to deal with writemasking.
2426 * Also attempt to deal with gl_PointSize being in the .w component.
2428 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2429 assert(type_sz(dst
.type
) < 8);
2430 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2431 inst
->size_written
= 4 * REG_SIZE
;
2432 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2435 /* If we are loading double data and we need a second read message
2436 * adjust the write offset
2438 if (num_iterations
> 1) {
2439 num_components
= instr
->num_components
- 2;
2446 case nir_intrinsic_load_output
:
2447 case nir_intrinsic_load_per_vertex_output
: {
2448 fs_reg indirect_offset
= get_indirect_offset(instr
);
2449 unsigned imm_offset
= instr
->const_index
[0];
2450 unsigned first_component
= nir_intrinsic_component(instr
);
2453 if (indirect_offset
.file
== BAD_FILE
) {
2454 /* Replicate the patch handle to all enabled channels */
2455 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2456 bld
.MOV(patch_handle
,
2457 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2460 if (first_component
!= 0) {
2461 unsigned read_components
=
2462 instr
->num_components
+ first_component
;
2463 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2464 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2466 inst
->size_written
= read_components
* REG_SIZE
;
2467 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2468 bld
.MOV(offset(dst
, bld
, i
),
2469 offset(tmp
, bld
, i
+ first_component
));
2472 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2474 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2476 inst
->offset
= imm_offset
;
2480 /* Indirect indexing - use per-slot offsets as well. */
2481 const fs_reg srcs
[] = {
2482 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2485 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2486 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2487 if (first_component
!= 0) {
2488 unsigned read_components
=
2489 instr
->num_components
+ first_component
;
2490 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2491 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2493 inst
->size_written
= read_components
* REG_SIZE
;
2494 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2495 bld
.MOV(offset(dst
, bld
, i
),
2496 offset(tmp
, bld
, i
+ first_component
));
2499 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2501 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2503 inst
->offset
= imm_offset
;
2509 case nir_intrinsic_store_output
:
2510 case nir_intrinsic_store_per_vertex_output
: {
2511 fs_reg value
= get_nir_src(instr
->src
[0]);
2512 bool is_64bit
= (instr
->src
[0].is_ssa
?
2513 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2514 fs_reg indirect_offset
= get_indirect_offset(instr
);
2515 unsigned imm_offset
= instr
->const_index
[0];
2516 unsigned mask
= instr
->const_index
[1];
2517 unsigned header_regs
= 0;
2519 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2521 if (indirect_offset
.file
!= BAD_FILE
) {
2522 srcs
[header_regs
++] = indirect_offset
;
2528 unsigned num_components
= util_last_bit(mask
);
2531 /* We can only pack two 64-bit components in a single message, so send
2532 * 2 messages if we have more components
2534 unsigned num_iterations
= 1;
2535 unsigned iter_components
= num_components
;
2536 unsigned first_component
= nir_intrinsic_component(instr
);
2538 first_component
= first_component
/ 2;
2539 if (instr
->num_components
> 2) {
2541 iter_components
= 2;
2545 mask
= mask
<< first_component
;
2547 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2548 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2549 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2550 opcode
= indirect_offset
.file
!= BAD_FILE
?
2551 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2552 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2553 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2554 /* Expand the 64-bit mask to 32-bit channels. We only handle
2555 * two channels in each iteration, so we only care about X/Y.
2557 unsigned mask32
= 0;
2558 if (mask
& WRITEMASK_X
)
2559 mask32
|= WRITEMASK_XY
;
2560 if (mask
& WRITEMASK_Y
)
2561 mask32
|= WRITEMASK_ZW
;
2563 /* If the mask does not include any of the channels X or Y there
2564 * is nothing to do in this iteration. Move on to the next couple
2565 * of 64-bit channels.
2573 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2574 opcode
= indirect_offset
.file
!= BAD_FILE
?
2575 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2576 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2578 opcode
= indirect_offset
.file
!= BAD_FILE
?
2579 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2580 SHADER_OPCODE_URB_WRITE_SIMD8
;
2583 for (unsigned i
= 0; i
< iter_components
; i
++) {
2584 if (!(mask
& (1 << (i
+ first_component
))))
2588 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2590 /* We need to shuffle the 64-bit data to match the layout
2591 * expected by our 32-bit URB write messages. We use a temporary
2594 unsigned channel
= iter
* 2 + i
;
2595 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2597 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2598 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2599 offset(dest
, bld
, 1);
2604 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2605 (is_64bit
? 2 * first_component
: first_component
);
2607 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2608 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2610 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2611 inst
->offset
= imm_offset
;
2614 /* If this is a 64-bit attribute, select the next two 64-bit channels
2615 * to be handled in the next iteration.
2626 nir_emit_intrinsic(bld
, instr
);
2632 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2633 nir_intrinsic_instr
*instr
)
2635 assert(stage
== MESA_SHADER_TESS_EVAL
);
2636 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2639 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2640 dest
= get_nir_dest(instr
->dest
);
2642 switch (instr
->intrinsic
) {
2643 case nir_intrinsic_load_primitive_id
:
2644 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2646 case nir_intrinsic_load_tess_coord
:
2647 /* gl_TessCoord is part of the payload in g1-3 */
2648 for (unsigned i
= 0; i
< 3; i
++) {
2649 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2653 case nir_intrinsic_load_input
:
2654 case nir_intrinsic_load_per_vertex_input
: {
2655 fs_reg indirect_offset
= get_indirect_offset(instr
);
2656 unsigned imm_offset
= instr
->const_index
[0];
2657 unsigned first_component
= nir_intrinsic_component(instr
);
2659 if (type_sz(dest
.type
) == 8) {
2660 first_component
= first_component
/ 2;
2664 if (indirect_offset
.file
== BAD_FILE
) {
2665 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2666 * which is 16 registers (since each holds 2 vec4 slots).
2668 unsigned slot_count
= 1;
2669 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2672 const unsigned max_push_slots
= 32;
2673 if (imm_offset
+ slot_count
<= max_push_slots
) {
2674 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2675 for (int i
= 0; i
< instr
->num_components
; i
++) {
2676 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2677 i
+ first_component
;
2678 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2681 tes_prog_data
->base
.urb_read_length
=
2682 MAX2(tes_prog_data
->base
.urb_read_length
,
2683 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2685 /* Replicate the patch handle to all enabled channels */
2686 const fs_reg srcs
[] = {
2687 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2689 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2690 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2692 if (first_component
!= 0) {
2693 unsigned read_components
=
2694 instr
->num_components
+ first_component
;
2695 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2696 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2698 inst
->size_written
= read_components
* REG_SIZE
;
2699 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2700 bld
.MOV(offset(dest
, bld
, i
),
2701 offset(tmp
, bld
, i
+ first_component
));
2704 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2706 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2709 inst
->offset
= imm_offset
;
2712 /* Indirect indexing - use per-slot offsets as well. */
2714 /* We can only read two double components with each URB read, so
2715 * we send two read messages in that case, each one loading up to
2716 * two double components.
2718 unsigned num_iterations
= 1;
2719 unsigned num_components
= instr
->num_components
;
2720 fs_reg orig_dest
= dest
;
2721 if (type_sz(dest
.type
) == 8) {
2722 if (instr
->num_components
> 2) {
2726 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2730 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2731 const fs_reg srcs
[] = {
2732 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2735 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2736 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2738 if (first_component
!= 0) {
2739 unsigned read_components
=
2740 num_components
+ first_component
;
2741 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2742 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2744 for (unsigned i
= 0; i
< num_components
; i
++) {
2745 bld
.MOV(offset(dest
, bld
, i
),
2746 offset(tmp
, bld
, i
+ first_component
));
2749 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2753 inst
->offset
= imm_offset
;
2754 inst
->size_written
= (num_components
+ first_component
) *
2755 inst
->dst
.component_size(inst
->exec_size
);
2757 /* If we are reading 64-bit data using 32-bit read messages we need
2758 * build proper 64-bit data elements by shuffling the low and high
2759 * 32-bit components around like we do for other things like UBOs
2762 if (type_sz(dest
.type
) == 8) {
2763 shuffle_from_32bit_read(bld
,
2764 offset(orig_dest
, bld
, iter
* 2),
2765 retype(dest
, BRW_REGISTER_TYPE_D
),
2769 /* If we are loading double data and we need a second read message
2772 if (num_iterations
> 1) {
2773 num_components
= instr
->num_components
- 2;
2781 nir_emit_intrinsic(bld
, instr
);
2787 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2788 nir_intrinsic_instr
*instr
)
2790 assert(stage
== MESA_SHADER_GEOMETRY
);
2791 fs_reg indirect_offset
;
2794 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2795 dest
= get_nir_dest(instr
->dest
);
2797 switch (instr
->intrinsic
) {
2798 case nir_intrinsic_load_primitive_id
:
2799 assert(stage
== MESA_SHADER_GEOMETRY
);
2800 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2801 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2802 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2805 case nir_intrinsic_load_input
:
2806 unreachable("load_input intrinsics are invalid for the GS stage");
2808 case nir_intrinsic_load_per_vertex_input
:
2809 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2810 instr
->src
[1], instr
->num_components
,
2811 nir_intrinsic_component(instr
));
2814 case nir_intrinsic_emit_vertex_with_counter
:
2815 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2818 case nir_intrinsic_end_primitive_with_counter
:
2819 emit_gs_end_primitive(instr
->src
[0]);
2822 case nir_intrinsic_set_vertex_count
:
2823 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2826 case nir_intrinsic_load_invocation_id
: {
2827 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2828 assert(val
.file
!= BAD_FILE
);
2829 dest
.type
= val
.type
;
2835 nir_emit_intrinsic(bld
, instr
);
2841 * Fetch the current render target layer index.
2844 fetch_render_target_array_index(const fs_builder
&bld
)
2846 if (bld
.shader
->devinfo
->gen
>= 6) {
2847 /* The render target array index is provided in the thread payload as
2848 * bits 26:16 of r0.0.
2850 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2851 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2855 /* Pre-SNB we only ever render into the first layer of the framebuffer
2856 * since layered rendering is not implemented.
2858 return brw_imm_ud(0);
2863 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2864 * framebuffer at the current fragment coordinates and sample index.
2867 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2870 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2872 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2873 const brw_wm_prog_key
*wm_key
=
2874 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2875 assert(!wm_key
->coherent_fb_fetch
);
2876 const struct brw_wm_prog_data
*wm_prog_data
=
2877 brw_wm_prog_data(stage_prog_data
);
2879 /* Calculate the surface index relative to the start of the texture binding
2880 * table block, since that's what the texturing messages expect.
2882 const unsigned surface
= target
+
2883 wm_prog_data
->binding_table
.render_target_read_start
-
2884 wm_prog_data
->base
.binding_table
.texture_start
;
2886 /* Calculate the fragment coordinates. */
2887 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2888 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2889 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2890 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2892 /* Calculate the sample index and MCS payload when multisampling. Luckily
2893 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2894 * shouldn't be necessary to recompile based on whether the framebuffer is
2897 if (wm_key
->multisample_fbo
&&
2898 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2899 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2901 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2902 const fs_reg mcs
= wm_key
->multisample_fbo
?
2903 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2905 /* Use either a normal or a CMS texel fetch message depending on whether
2906 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2907 * message just in case the framebuffer uses 16x multisampling, it should
2908 * be equivalent to the normal CMS fetch for lower multisampling modes.
2910 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2911 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2912 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2914 /* Emit the instruction. */
2915 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
2916 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
2917 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
2918 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
2919 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
2920 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
2921 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
2922 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
2923 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
2925 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
2926 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2932 * Actual coherent framebuffer read implemented using the native render target
2933 * read message. Requires SKL+.
2936 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
2938 assert(bld
.shader
->devinfo
->gen
>= 9);
2939 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
2940 inst
->target
= target
;
2941 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2947 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
2949 if (n
&& regs
[0].file
!= BAD_FILE
) {
2953 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
2955 for (unsigned i
= 0; i
< n
; i
++)
2963 alloc_frag_output(fs_visitor
*v
, unsigned location
)
2965 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
2966 const brw_wm_prog_key
*const key
=
2967 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
2968 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
2969 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
2971 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
2972 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
2974 else if (l
== FRAG_RESULT_COLOR
)
2975 return alloc_temporary(v
->bld
, 4, v
->outputs
,
2976 MAX2(key
->nr_color_regions
, 1));
2978 else if (l
== FRAG_RESULT_DEPTH
)
2979 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
2981 else if (l
== FRAG_RESULT_STENCIL
)
2982 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
2984 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
2985 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
2987 else if (l
>= FRAG_RESULT_DATA0
&&
2988 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
2989 return alloc_temporary(v
->bld
, 4,
2990 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
2993 unreachable("Invalid location");
2997 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2998 nir_intrinsic_instr
*instr
)
3000 assert(stage
== MESA_SHADER_FRAGMENT
);
3003 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3004 dest
= get_nir_dest(instr
->dest
);
3006 switch (instr
->intrinsic
) {
3007 case nir_intrinsic_load_front_face
:
3008 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3009 *emit_frontfacing_interpolation());
3012 case nir_intrinsic_load_sample_pos
: {
3013 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3014 assert(sample_pos
.file
!= BAD_FILE
);
3015 dest
.type
= sample_pos
.type
;
3016 bld
.MOV(dest
, sample_pos
);
3017 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3021 case nir_intrinsic_load_layer_id
:
3022 dest
.type
= BRW_REGISTER_TYPE_UD
;
3023 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3026 case nir_intrinsic_load_helper_invocation
:
3027 case nir_intrinsic_load_sample_mask_in
:
3028 case nir_intrinsic_load_sample_id
: {
3029 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3030 fs_reg val
= nir_system_values
[sv
];
3031 assert(val
.file
!= BAD_FILE
);
3032 dest
.type
= val
.type
;
3037 case nir_intrinsic_store_output
: {
3038 const fs_reg src
= get_nir_src(instr
->src
[0]);
3039 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3040 const unsigned location
= nir_intrinsic_base(instr
) +
3041 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3042 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3045 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3046 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3047 offset(src
, bld
, j
));
3052 case nir_intrinsic_load_output
: {
3053 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3054 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3055 assert(l
>= FRAG_RESULT_DATA0
);
3056 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3057 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3058 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3060 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3061 emit_coherent_fb_read(bld
, tmp
, target
);
3063 emit_non_coherent_fb_read(bld
, tmp
, target
);
3065 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3066 bld
.MOV(offset(dest
, bld
, j
),
3067 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3073 case nir_intrinsic_discard
:
3074 case nir_intrinsic_discard_if
: {
3075 /* We track our discarded pixels in f0.1. By predicating on it, we can
3076 * update just the flag bits that aren't yet discarded. If there's no
3077 * condition, we emit a CMP of g0 != g0, so all currently executing
3078 * channels will get turned off.
3081 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3082 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3083 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3085 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3086 BRW_REGISTER_TYPE_UW
));
3087 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3089 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3090 cmp
->flag_subreg
= 1;
3092 if (devinfo
->gen
>= 6) {
3093 emit_discard_jump();
3096 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3100 case nir_intrinsic_load_input
: {
3101 /* load_input is only used for flat inputs */
3102 unsigned base
= nir_intrinsic_base(instr
);
3103 unsigned comp
= nir_intrinsic_component(instr
);
3104 unsigned num_components
= instr
->num_components
;
3105 fs_reg orig_dest
= dest
;
3106 enum brw_reg_type type
= dest
.type
;
3108 /* Special case fields in the VUE header */
3109 if (base
== VARYING_SLOT_LAYER
)
3111 else if (base
== VARYING_SLOT_VIEWPORT
)
3114 if (nir_dest_bit_size(instr
->dest
) == 64) {
3115 /* const_index is in 32-bit type size units that could not be aligned
3116 * with DF. We need to read the double vector as if it was a float
3117 * vector of twice the number of components to fetch the right data.
3119 type
= BRW_REGISTER_TYPE_F
;
3120 num_components
*= 2;
3121 dest
= bld
.vgrf(type
, num_components
);
3124 for (unsigned int i
= 0; i
< num_components
; i
++) {
3125 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3126 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3129 if (nir_dest_bit_size(instr
->dest
) == 64) {
3130 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3131 instr
->num_components
);
3136 case nir_intrinsic_load_barycentric_pixel
:
3137 case nir_intrinsic_load_barycentric_centroid
:
3138 case nir_intrinsic_load_barycentric_sample
:
3139 /* Do nothing - load_interpolated_input handling will handle it later. */
3142 case nir_intrinsic_load_barycentric_at_sample
: {
3143 const glsl_interp_mode interpolation
=
3144 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3146 if (nir_src_is_const(instr
->src
[0])) {
3147 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3149 emit_pixel_interpolater_send(bld
,
3150 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3153 brw_imm_ud(msg_data
),
3156 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3157 BRW_REGISTER_TYPE_UD
);
3159 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3160 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3161 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3162 bld
.exec_all().group(1, 0)
3163 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3164 emit_pixel_interpolater_send(bld
,
3165 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3171 /* Make a loop that sends a message to the pixel interpolater
3172 * for the sample number in each live channel. If there are
3173 * multiple channels with the same sample number then these
3174 * will be handled simultaneously with a single interation of
3177 bld
.emit(BRW_OPCODE_DO
);
3179 /* Get the next live sample number into sample_id_reg */
3180 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3182 /* Set the flag register so that we can perform the send
3183 * message on all channels that have the same sample number
3185 bld
.CMP(bld
.null_reg_ud(),
3186 sample_src
, sample_id
,
3187 BRW_CONDITIONAL_EQ
);
3188 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3189 bld
.exec_all().group(1, 0)
3190 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3192 emit_pixel_interpolater_send(bld
,
3193 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3196 component(msg_data
, 0),
3198 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3200 /* Continue the loop if there are any live channels left */
3201 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3203 bld
.emit(BRW_OPCODE_WHILE
));
3209 case nir_intrinsic_load_barycentric_at_offset
: {
3210 const glsl_interp_mode interpolation
=
3211 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3213 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3216 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3217 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3218 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3220 emit_pixel_interpolater_send(bld
,
3221 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3224 brw_imm_ud(off_x
| (off_y
<< 4)),
3227 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3228 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3229 BRW_REGISTER_TYPE_F
);
3230 for (int i
= 0; i
< 2; i
++) {
3231 fs_reg temp
= vgrf(glsl_type::float_type
);
3232 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3233 fs_reg itemp
= vgrf(glsl_type::int_type
);
3235 bld
.MOV(itemp
, temp
);
3237 /* Clamp the upper end of the range to +7/16.
3238 * ARB_gpu_shader5 requires that we support a maximum offset
3239 * of +0.5, which isn't representable in a S0.4 value -- if
3240 * we didn't clamp it, we'd end up with -8/16, which is the
3241 * opposite of what the shader author wanted.
3243 * This is legal due to ARB_gpu_shader5's quantization
3246 * "Not all values of <offset> may be supported; x and y
3247 * offsets may be rounded to fixed-point values with the
3248 * number of fraction bits given by the
3249 * implementation-dependent constant
3250 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3252 set_condmod(BRW_CONDITIONAL_L
,
3253 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3256 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3257 emit_pixel_interpolater_send(bld
,
3267 case nir_intrinsic_load_interpolated_input
: {
3268 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3269 emit_fragcoord_interpolation(dest
);
3273 assert(instr
->src
[0].ssa
&&
3274 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3275 nir_intrinsic_instr
*bary_intrinsic
=
3276 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3277 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3278 enum glsl_interp_mode interp_mode
=
3279 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3282 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3283 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3284 /* Use the result of the PI message */
3285 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3287 /* Use the delta_xy values computed from the payload */
3288 enum brw_barycentric_mode bary
=
3289 brw_barycentric_mode(interp_mode
, bary_intrin
);
3291 dst_xy
= this->delta_xy
[bary
];
3294 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3296 component(interp_reg(nir_intrinsic_base(instr
),
3297 nir_intrinsic_component(instr
) + i
), 0);
3298 interp
.type
= BRW_REGISTER_TYPE_F
;
3299 dest
.type
= BRW_REGISTER_TYPE_F
;
3301 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3302 fs_reg tmp
= vgrf(glsl_type::float_type
);
3303 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3304 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3306 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3313 nir_emit_intrinsic(bld
, instr
);
3319 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3321 if (nir_src_is_const(instr
->src
[src
])) {
3322 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3325 else if (add_val
== -1)
3333 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3334 nir_intrinsic_instr
*instr
)
3336 assert(stage
== MESA_SHADER_COMPUTE
);
3337 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3340 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3341 dest
= get_nir_dest(instr
->dest
);
3343 switch (instr
->intrinsic
) {
3344 case nir_intrinsic_barrier
:
3346 cs_prog_data
->uses_barrier
= true;
3349 case nir_intrinsic_load_subgroup_id
:
3350 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3353 case nir_intrinsic_load_local_invocation_id
:
3354 case nir_intrinsic_load_work_group_id
: {
3355 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3356 fs_reg val
= nir_system_values
[sv
];
3357 assert(val
.file
!= BAD_FILE
);
3358 dest
.type
= val
.type
;
3359 for (unsigned i
= 0; i
< 3; i
++)
3360 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3364 case nir_intrinsic_load_num_work_groups
: {
3365 const unsigned surface
=
3366 cs_prog_data
->binding_table
.work_groups_start
;
3368 cs_prog_data
->uses_num_work_groups
= true;
3370 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3371 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3372 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3373 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3375 /* Read the 3 GLuint components of gl_NumWorkGroups */
3376 for (unsigned i
= 0; i
< 3; i
++) {
3377 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3378 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3379 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3384 case nir_intrinsic_shared_atomic_add
:
3385 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3387 case nir_intrinsic_shared_atomic_imin
:
3388 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3390 case nir_intrinsic_shared_atomic_umin
:
3391 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3393 case nir_intrinsic_shared_atomic_imax
:
3394 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3396 case nir_intrinsic_shared_atomic_umax
:
3397 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3399 case nir_intrinsic_shared_atomic_and
:
3400 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3402 case nir_intrinsic_shared_atomic_or
:
3403 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3405 case nir_intrinsic_shared_atomic_xor
:
3406 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3408 case nir_intrinsic_shared_atomic_exchange
:
3409 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3411 case nir_intrinsic_shared_atomic_comp_swap
:
3412 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3414 case nir_intrinsic_shared_atomic_fmin
:
3415 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3417 case nir_intrinsic_shared_atomic_fmax
:
3418 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3420 case nir_intrinsic_shared_atomic_fcomp_swap
:
3421 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3424 case nir_intrinsic_load_shared
: {
3425 assert(devinfo
->gen
>= 7);
3426 assert(stage
== MESA_SHADER_COMPUTE
);
3428 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3429 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3430 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3431 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3432 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3434 /* Make dest unsigned because that's what the temporary will be */
3435 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3437 /* Read the vector */
3438 if (nir_intrinsic_align(instr
) >= 4) {
3439 assert(nir_dest_bit_size(instr
->dest
) == 32);
3440 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3442 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3443 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3444 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3446 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3447 assert(nir_dest_num_components(instr
->dest
) == 1);
3448 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3450 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3451 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3452 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3453 bld
.MOV(dest
, read_result
);
3458 case nir_intrinsic_store_shared
: {
3459 assert(devinfo
->gen
>= 7);
3460 assert(stage
== MESA_SHADER_COMPUTE
);
3462 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3463 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3464 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3465 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3466 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3468 fs_reg data
= get_nir_src(instr
->src
[0]);
3469 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3471 assert(nir_intrinsic_write_mask(instr
) ==
3472 (1u << instr
->num_components
) - 1);
3473 if (nir_intrinsic_align(instr
) >= 4) {
3474 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3475 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3476 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3477 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3478 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3479 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3481 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3482 assert(nir_src_num_components(instr
->src
[0]) == 1);
3483 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3485 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3486 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3488 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3489 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3495 nir_emit_intrinsic(bld
, instr
);
3501 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3502 nir_op op
, brw_reg_type type
)
3504 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3505 switch (type_sz(type
)) {
3507 assert(type
!= BRW_REGISTER_TYPE_HF
);
3508 return retype(brw_imm_uw(value
.u16
[0]), type
);
3510 return retype(brw_imm_ud(value
.u32
[0]), type
);
3512 if (type
== BRW_REGISTER_TYPE_DF
)
3513 return setup_imm_df(bld
, value
.f64
[0]);
3515 return retype(brw_imm_u64(value
.u64
[0]), type
);
3517 unreachable("Invalid type size");
3522 brw_op_for_nir_reduction_op(nir_op op
)
3525 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3526 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3527 case nir_op_imul
: return BRW_OPCODE_MUL
;
3528 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3529 case nir_op_imin
: return BRW_OPCODE_SEL
;
3530 case nir_op_umin
: return BRW_OPCODE_SEL
;
3531 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3532 case nir_op_imax
: return BRW_OPCODE_SEL
;
3533 case nir_op_umax
: return BRW_OPCODE_SEL
;
3534 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3535 case nir_op_iand
: return BRW_OPCODE_AND
;
3536 case nir_op_ior
: return BRW_OPCODE_OR
;
3537 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3539 unreachable("Invalid reduction operation");
3543 static brw_conditional_mod
3544 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3547 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3548 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3549 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3550 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3551 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3552 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3553 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3554 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3555 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3556 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3557 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3558 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3559 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3561 unreachable("Invalid reduction operation");
3566 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3567 nir_intrinsic_instr
*instr
)
3569 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3571 if (stage_prog_data
->binding_table
.image_start
> 0) {
3572 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3573 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3575 bld
.ADD(image
, image
,
3576 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3580 return bld
.emit_uniformize(image
);
3584 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3585 nir_intrinsic_instr
*instr
)
3587 /* SSBO stores are weird in that their index is in src[1] */
3588 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3591 if (nir_src_is_const(instr
->src
[src
])) {
3592 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3593 nir_src_as_uint(instr
->src
[src
]);
3594 surf_index
= brw_imm_ud(index
);
3596 surf_index
= vgrf(glsl_type::uint_type
);
3597 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3598 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3601 return bld
.emit_uniformize(surf_index
);
3605 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3607 switch (nir_intrinsic_image_dim(instr
)) {
3608 case GLSL_SAMPLER_DIM_1D
:
3609 return 1 + nir_intrinsic_image_array(instr
);
3610 case GLSL_SAMPLER_DIM_2D
:
3611 case GLSL_SAMPLER_DIM_RECT
:
3612 return 2 + nir_intrinsic_image_array(instr
);
3613 case GLSL_SAMPLER_DIM_3D
:
3614 case GLSL_SAMPLER_DIM_CUBE
:
3616 case GLSL_SAMPLER_DIM_BUF
:
3618 case GLSL_SAMPLER_DIM_MS
:
3619 return 2 + nir_intrinsic_image_array(instr
);
3621 unreachable("Invalid image dimension");
3626 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3629 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3630 dest
= get_nir_dest(instr
->dest
);
3632 switch (instr
->intrinsic
) {
3633 case nir_intrinsic_image_load
:
3634 case nir_intrinsic_image_store
:
3635 case nir_intrinsic_image_atomic_add
:
3636 case nir_intrinsic_image_atomic_min
:
3637 case nir_intrinsic_image_atomic_max
:
3638 case nir_intrinsic_image_atomic_and
:
3639 case nir_intrinsic_image_atomic_or
:
3640 case nir_intrinsic_image_atomic_xor
:
3641 case nir_intrinsic_image_atomic_exchange
:
3642 case nir_intrinsic_image_atomic_comp_swap
: {
3643 if (stage
== MESA_SHADER_FRAGMENT
&&
3644 instr
->intrinsic
!= nir_intrinsic_image_load
)
3645 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3647 /* Get some metadata from the image intrinsic. */
3648 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3649 const GLenum format
= nir_intrinsic_format(instr
);
3651 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3652 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3653 get_nir_image_intrinsic_image(bld
, instr
);
3654 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3655 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
3656 brw_imm_ud(image_intrinsic_coord_components(instr
));
3658 /* Emit an image load, store or atomic op. */
3659 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3660 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3662 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
3663 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3664 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3665 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3666 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3667 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
3668 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
3669 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3672 unsigned num_srcs
= info
->num_srcs
;
3674 switch (instr
->intrinsic
) {
3675 case nir_intrinsic_image_atomic_add
:
3676 assert(num_srcs
== 4);
3678 op
= get_op_for_atomic_add(instr
, 3);
3680 if (op
!= BRW_AOP_ADD
)
3683 case nir_intrinsic_image_atomic_min
:
3684 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3685 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3687 case nir_intrinsic_image_atomic_max
:
3688 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3689 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3691 case nir_intrinsic_image_atomic_and
:
3694 case nir_intrinsic_image_atomic_or
:
3697 case nir_intrinsic_image_atomic_xor
:
3700 case nir_intrinsic_image_atomic_exchange
:
3703 case nir_intrinsic_image_atomic_comp_swap
:
3707 unreachable("Not reachable.");
3710 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
3714 data
= get_nir_src(instr
->src
[3]);
3715 if (num_srcs
>= 5) {
3716 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
3717 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
3718 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
3721 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3723 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
3724 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3729 case nir_intrinsic_image_size
: {
3730 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3731 * into will handle the binding table index for us in the geneerator.
3733 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3734 BRW_REGISTER_TYPE_UD
);
3735 image
= bld
.emit_uniformize(image
);
3737 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3738 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
3739 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
3740 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
3741 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
3743 /* Since the image size is always uniform, we can just emit a SIMD8
3744 * query instruction and splat the result out.
3746 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3748 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3749 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
3750 tmp
, srcs
, ARRAY_SIZE(srcs
));
3751 inst
->size_written
= 4 * REG_SIZE
;
3753 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3754 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3755 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3756 offset(retype(dest
, tmp
.type
), bld
, c
),
3757 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3759 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3760 component(offset(tmp
, ubld
, c
), 0));
3766 case nir_intrinsic_image_load_raw_intel
: {
3767 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3768 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3769 get_nir_image_intrinsic_image(bld
, instr
);
3770 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3771 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3772 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3775 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3776 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3777 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3781 case nir_intrinsic_image_store_raw_intel
: {
3782 if (stage
== MESA_SHADER_FRAGMENT
)
3783 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3785 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3786 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3787 get_nir_image_intrinsic_image(bld
, instr
);
3788 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3789 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
3790 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3791 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3793 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3794 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3798 case nir_intrinsic_group_memory_barrier
:
3799 case nir_intrinsic_memory_barrier_shared
:
3800 case nir_intrinsic_memory_barrier_atomic_counter
:
3801 case nir_intrinsic_memory_barrier_buffer
:
3802 case nir_intrinsic_memory_barrier_image
:
3803 case nir_intrinsic_memory_barrier
: {
3804 const fs_builder ubld
= bld
.group(8, 0);
3805 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3806 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3807 ->size_written
= 2 * REG_SIZE
;
3811 case nir_intrinsic_shader_clock
: {
3812 /* We cannot do anything if there is an event, so ignore it for now */
3813 const fs_reg shader_clock
= get_timestamp(bld
);
3814 const fs_reg srcs
[] = { component(shader_clock
, 0),
3815 component(shader_clock
, 1) };
3816 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3820 case nir_intrinsic_image_samples
:
3821 /* The driver does not support multi-sampled images. */
3822 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3825 case nir_intrinsic_load_uniform
: {
3826 /* Offsets are in bytes but they should always aligned to
3829 assert(instr
->const_index
[0] % 4 == 0 ||
3830 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3832 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3834 if (nir_src_is_const(instr
->src
[0])) {
3835 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3836 assert(load_offset
% type_sz(dest
.type
) == 0);
3837 /* For 16-bit types we add the module of the const_index[0]
3838 * offset to access to not 32-bit aligned element
3840 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
3842 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3843 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3846 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3847 BRW_REGISTER_TYPE_UD
);
3849 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3850 * go past the end of the uniform. In order to keep the n'th
3851 * component from running past, we subtract off the size of all but
3852 * one component of the vector.
3854 assert(instr
->const_index
[1] >=
3855 instr
->num_components
* (int) type_sz(dest
.type
));
3856 unsigned read_size
= instr
->const_index
[1] -
3857 (instr
->num_components
- 1) * type_sz(dest
.type
);
3859 bool supports_64bit_indirects
=
3860 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3862 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3863 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3864 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3865 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3866 indirect
, brw_imm_ud(read_size
));
3869 const unsigned num_mov_indirects
=
3870 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3871 /* We read a little bit less per MOV INDIRECT, as they are now
3872 * 32-bits ones instead of 64-bit. Fix read_size then.
3874 const unsigned read_size_32bit
= read_size
-
3875 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3876 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3877 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3878 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3879 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3880 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3881 indirect
, brw_imm_ud(read_size_32bit
));
3889 case nir_intrinsic_load_ubo
: {
3891 if (nir_src_is_const(instr
->src
[0])) {
3892 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3893 nir_src_as_uint(instr
->src
[0]);
3894 surf_index
= brw_imm_ud(index
);
3896 /* The block index is not a constant. Evaluate the index expression
3897 * per-channel and add the base UBO index; we have to select a value
3898 * from any live channel.
3900 surf_index
= vgrf(glsl_type::uint_type
);
3901 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3902 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3903 surf_index
= bld
.emit_uniformize(surf_index
);
3906 if (!nir_src_is_const(instr
->src
[1])) {
3907 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3908 BRW_REGISTER_TYPE_UD
);
3910 for (int i
= 0; i
< instr
->num_components
; i
++)
3911 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3912 base_offset
, i
* type_sz(dest
.type
));
3914 /* Even if we are loading doubles, a pull constant load will load
3915 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3916 * need to load a full dvec4 we will have to emit 2 loads. This is
3917 * similar to demote_pull_constants(), except that in that case we
3918 * see individual accesses to each component of the vector and then
3919 * we let CSE deal with duplicate loads. Here we see a vector access
3920 * and we have to split it if necessary.
3922 const unsigned type_size
= type_sz(dest
.type
);
3923 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
3925 /* See if we've selected this as a push constant candidate */
3926 if (nir_src_is_const(instr
->src
[0])) {
3927 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
3928 const unsigned offset_256b
= load_offset
/ 32;
3931 for (int i
= 0; i
< 4; i
++) {
3932 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3933 if (range
->block
== ubo_block
&&
3934 offset_256b
>= range
->start
&&
3935 offset_256b
< range
->start
+ range
->length
) {
3937 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3938 push_reg
.offset
= load_offset
- 32 * range
->start
;
3943 if (push_reg
.file
!= BAD_FILE
) {
3944 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3945 bld
.MOV(offset(dest
, bld
, i
),
3946 byte_offset(push_reg
, i
* type_size
));
3952 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3953 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3954 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3956 for (unsigned c
= 0; c
< instr
->num_components
;) {
3957 const unsigned base
= load_offset
+ c
* type_size
;
3958 /* Number of usable components in the next block-aligned load. */
3959 const unsigned count
= MIN2(instr
->num_components
- c
,
3960 (block_sz
- base
% block_sz
) / type_size
);
3962 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3963 packed_consts
, surf_index
,
3964 brw_imm_ud(base
& ~(block_sz
- 1)));
3966 const fs_reg consts
=
3967 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3970 for (unsigned d
= 0; d
< count
; d
++)
3971 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3979 case nir_intrinsic_load_global
: {
3980 assert(devinfo
->gen
>= 8);
3982 if (nir_intrinsic_align(instr
) >= 4) {
3983 assert(nir_dest_bit_size(instr
->dest
) == 32);
3984 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
3986 get_nir_src(instr
->src
[0]), /* Address */
3987 fs_reg(), /* No source data */
3988 brw_imm_ud(instr
->num_components
));
3989 inst
->size_written
= instr
->num_components
*
3990 inst
->dst
.component_size(inst
->exec_size
);
3992 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3993 assert(bit_size
<= 32);
3994 assert(nir_dest_num_components(instr
->dest
) == 1);
3995 brw_reg_type data_type
=
3996 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3997 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3998 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4000 get_nir_src(instr
->src
[0]), /* Address */
4001 fs_reg(), /* No source data */
4002 brw_imm_ud(bit_size
));
4003 bld
.MOV(retype(dest
, data_type
), tmp
);
4008 case nir_intrinsic_store_global
:
4009 assert(devinfo
->gen
>= 8);
4011 if (stage
== MESA_SHADER_FRAGMENT
)
4012 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4014 if (nir_intrinsic_align(instr
) >= 4) {
4015 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4016 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4018 get_nir_src(instr
->src
[1]), /* Address */
4019 get_nir_src(instr
->src
[0]), /* Data */
4020 brw_imm_ud(instr
->num_components
));
4022 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4023 assert(bit_size
<= 32);
4024 assert(nir_src_num_components(instr
->src
[0]) == 1);
4025 brw_reg_type data_type
=
4026 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4027 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4028 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4029 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4031 get_nir_src(instr
->src
[1]), /* Address */
4033 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4037 case nir_intrinsic_global_atomic_add
:
4038 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4040 case nir_intrinsic_global_atomic_imin
:
4041 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4043 case nir_intrinsic_global_atomic_umin
:
4044 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4046 case nir_intrinsic_global_atomic_imax
:
4047 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4049 case nir_intrinsic_global_atomic_umax
:
4050 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4052 case nir_intrinsic_global_atomic_and
:
4053 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4055 case nir_intrinsic_global_atomic_or
:
4056 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4058 case nir_intrinsic_global_atomic_xor
:
4059 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4061 case nir_intrinsic_global_atomic_exchange
:
4062 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4064 case nir_intrinsic_global_atomic_comp_swap
:
4065 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4067 case nir_intrinsic_global_atomic_fmin
:
4068 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4070 case nir_intrinsic_global_atomic_fmax
:
4071 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4073 case nir_intrinsic_global_atomic_fcomp_swap
:
4074 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4077 case nir_intrinsic_load_ssbo
: {
4078 assert(devinfo
->gen
>= 7);
4080 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4081 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4082 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4083 get_nir_ssbo_intrinsic_index(bld
, instr
);
4084 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4085 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4087 /* Make dest unsigned because that's what the temporary will be */
4088 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4090 /* Read the vector */
4091 if (nir_intrinsic_align(instr
) >= 4) {
4092 assert(nir_dest_bit_size(instr
->dest
) == 32);
4093 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4095 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4096 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4097 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4099 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4100 assert(nir_dest_num_components(instr
->dest
) == 1);
4101 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4103 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4104 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4105 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4106 bld
.MOV(dest
, read_result
);
4111 case nir_intrinsic_store_ssbo
: {
4112 assert(devinfo
->gen
>= 7);
4114 if (stage
== MESA_SHADER_FRAGMENT
)
4115 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4117 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4118 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4119 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4120 get_nir_ssbo_intrinsic_index(bld
, instr
);
4121 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4122 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4124 fs_reg data
= get_nir_src(instr
->src
[0]);
4125 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4127 assert(nir_intrinsic_write_mask(instr
) ==
4128 (1u << instr
->num_components
) - 1);
4129 if (nir_intrinsic_align(instr
) >= 4) {
4130 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4131 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4132 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4133 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4134 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4135 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4137 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4138 assert(nir_src_num_components(instr
->src
[0]) == 1);
4139 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4141 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4142 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4144 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4145 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4150 case nir_intrinsic_store_output
: {
4151 fs_reg src
= get_nir_src(instr
->src
[0]);
4153 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4154 unsigned num_components
= instr
->num_components
;
4155 unsigned first_component
= nir_intrinsic_component(instr
);
4156 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4157 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4158 num_components
*= 2;
4161 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4162 4 * store_offset
), src
.type
);
4163 for (unsigned j
= 0; j
< num_components
; j
++) {
4164 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4165 offset(src
, bld
, j
));
4170 case nir_intrinsic_ssbo_atomic_add
:
4171 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4173 case nir_intrinsic_ssbo_atomic_imin
:
4174 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4176 case nir_intrinsic_ssbo_atomic_umin
:
4177 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4179 case nir_intrinsic_ssbo_atomic_imax
:
4180 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4182 case nir_intrinsic_ssbo_atomic_umax
:
4183 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4185 case nir_intrinsic_ssbo_atomic_and
:
4186 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4188 case nir_intrinsic_ssbo_atomic_or
:
4189 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4191 case nir_intrinsic_ssbo_atomic_xor
:
4192 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4194 case nir_intrinsic_ssbo_atomic_exchange
:
4195 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4197 case nir_intrinsic_ssbo_atomic_comp_swap
:
4198 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4200 case nir_intrinsic_ssbo_atomic_fmin
:
4201 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4203 case nir_intrinsic_ssbo_atomic_fmax
:
4204 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4206 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4207 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4210 case nir_intrinsic_get_buffer_size
: {
4211 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4212 nir_src_as_uint(instr
->src
[0]) : 0;
4214 /* A resinfo's sampler message is used to get the buffer size. The
4215 * SIMD8's writeback message consists of four registers and SIMD16's
4216 * writeback message consists of 8 destination registers (two per each
4217 * component). Because we are only interested on the first channel of
4218 * the first returned component, where resinfo returns the buffer size
4219 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4220 * the dispatch width.
4222 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4223 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4224 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4227 ubld
.MOV(src_payload
, brw_imm_d(0));
4229 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4230 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4231 src_payload
, brw_imm_ud(index
));
4232 inst
->header_size
= 0;
4234 inst
->size_written
= 4 * REG_SIZE
;
4236 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4238 * "Out-of-bounds checking is always performed at a DWord granularity. If
4239 * any part of the DWord is out-of-bounds then the whole DWord is
4240 * considered out-of-bounds."
4242 * This implies that types with size smaller than 4-bytes need to be
4243 * padded if they don't complete the last dword of the buffer. But as we
4244 * need to maintain the original size we need to reverse the padding
4245 * calculation to return the correct size to know the number of elements
4246 * of an unsized array. As we stored in the last two bits of the surface
4247 * size the needed padding for the buffer, we calculate here the
4248 * original buffer_size reversing the surface_size calculation:
4250 * surface_size = isl_align(buffer_size, 4) +
4251 * (isl_align(buffer_size) - buffer_size)
4253 * buffer_size = surface_size & ~3 - surface_size & 3
4256 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4257 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4258 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4260 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4261 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4262 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4264 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4268 case nir_intrinsic_load_subgroup_invocation
:
4269 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4270 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4273 case nir_intrinsic_load_subgroup_eq_mask
:
4274 case nir_intrinsic_load_subgroup_ge_mask
:
4275 case nir_intrinsic_load_subgroup_gt_mask
:
4276 case nir_intrinsic_load_subgroup_le_mask
:
4277 case nir_intrinsic_load_subgroup_lt_mask
:
4278 unreachable("not reached");
4280 case nir_intrinsic_vote_any
: {
4281 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4283 /* The any/all predicates do not consider channel enables. To prevent
4284 * dead channels from affecting the result, we initialize the flag with
4285 * with the identity value for the logical operation.
4287 if (dispatch_width
== 32) {
4288 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4289 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4292 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4294 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4296 /* For some reason, the any/all predicates don't work properly with
4297 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4298 * doesn't read the correct subset of the flag register and you end up
4299 * getting garbage in the second half. Work around this by using a pair
4300 * of 1-wide MOVs and scattering the result.
4302 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4303 ubld
.MOV(res1
, brw_imm_d(0));
4304 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4305 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4306 BRW_PREDICATE_ALIGN1_ANY32H
,
4307 ubld
.MOV(res1
, brw_imm_d(-1)));
4309 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4312 case nir_intrinsic_vote_all
: {
4313 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4315 /* The any/all predicates do not consider channel enables. To prevent
4316 * dead channels from affecting the result, we initialize the flag with
4317 * with the identity value for the logical operation.
4319 if (dispatch_width
== 32) {
4320 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4321 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4322 brw_imm_ud(0xffffffff));
4324 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4326 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4328 /* For some reason, the any/all predicates don't work properly with
4329 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4330 * doesn't read the correct subset of the flag register and you end up
4331 * getting garbage in the second half. Work around this by using a pair
4332 * of 1-wide MOVs and scattering the result.
4334 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4335 ubld
.MOV(res1
, brw_imm_d(0));
4336 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4337 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4338 BRW_PREDICATE_ALIGN1_ALL32H
,
4339 ubld
.MOV(res1
, brw_imm_d(-1)));
4341 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4344 case nir_intrinsic_vote_feq
:
4345 case nir_intrinsic_vote_ieq
: {
4346 fs_reg value
= get_nir_src(instr
->src
[0]);
4347 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4348 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4349 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4352 fs_reg uniformized
= bld
.emit_uniformize(value
);
4353 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4355 /* The any/all predicates do not consider channel enables. To prevent
4356 * dead channels from affecting the result, we initialize the flag with
4357 * with the identity value for the logical operation.
4359 if (dispatch_width
== 32) {
4360 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4361 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4362 brw_imm_ud(0xffffffff));
4364 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4366 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4368 /* For some reason, the any/all predicates don't work properly with
4369 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4370 * doesn't read the correct subset of the flag register and you end up
4371 * getting garbage in the second half. Work around this by using a pair
4372 * of 1-wide MOVs and scattering the result.
4374 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4375 ubld
.MOV(res1
, brw_imm_d(0));
4376 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4377 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4378 BRW_PREDICATE_ALIGN1_ALL32H
,
4379 ubld
.MOV(res1
, brw_imm_d(-1)));
4381 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4385 case nir_intrinsic_ballot
: {
4386 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4387 BRW_REGISTER_TYPE_UD
);
4388 struct brw_reg flag
= brw_flag_reg(0, 0);
4389 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4390 * as f0.0. This is a problem for fragment programs as we currently use
4391 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4392 * programs yet so this isn't a problem. When we do, something will
4395 if (dispatch_width
== 32)
4396 flag
.type
= BRW_REGISTER_TYPE_UD
;
4398 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4399 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4401 if (instr
->dest
.ssa
.bit_size
> 32) {
4402 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4404 dest
.type
= BRW_REGISTER_TYPE_UD
;
4406 bld
.MOV(dest
, flag
);
4410 case nir_intrinsic_read_invocation
: {
4411 const fs_reg value
= get_nir_src(instr
->src
[0]);
4412 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4413 fs_reg tmp
= bld
.vgrf(value
.type
);
4415 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4416 bld
.emit_uniformize(invocation
));
4418 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4422 case nir_intrinsic_read_first_invocation
: {
4423 const fs_reg value
= get_nir_src(instr
->src
[0]);
4424 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4428 case nir_intrinsic_shuffle
: {
4429 const fs_reg value
= get_nir_src(instr
->src
[0]);
4430 const fs_reg index
= get_nir_src(instr
->src
[1]);
4432 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4436 case nir_intrinsic_first_invocation
: {
4437 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4438 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4439 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4440 fs_reg(component(tmp
, 0)));
4444 case nir_intrinsic_quad_broadcast
: {
4445 const fs_reg value
= get_nir_src(instr
->src
[0]);
4446 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4448 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4449 value
, brw_imm_ud(index
), brw_imm_ud(4));
4453 case nir_intrinsic_quad_swap_horizontal
: {
4454 const fs_reg value
= get_nir_src(instr
->src
[0]);
4455 const fs_reg tmp
= bld
.vgrf(value
.type
);
4456 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4458 const fs_reg src_left
= horiz_stride(value
, 2);
4459 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4460 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4461 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4463 ubld
.MOV(tmp_left
, src_right
);
4464 ubld
.MOV(tmp_right
, src_left
);
4466 bld
.MOV(retype(dest
, value
.type
), tmp
);
4470 case nir_intrinsic_quad_swap_vertical
: {
4471 const fs_reg value
= get_nir_src(instr
->src
[0]);
4472 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4473 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4474 const fs_reg tmp
= bld
.vgrf(value
.type
);
4475 const fs_builder ubld
= bld
.exec_all();
4476 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4477 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4478 bld
.MOV(retype(dest
, value
.type
), tmp
);
4480 /* For larger data types, we have to either emit dispatch_width many
4481 * MOVs or else fall back to doing indirects.
4483 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4484 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4486 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4491 case nir_intrinsic_quad_swap_diagonal
: {
4492 const fs_reg value
= get_nir_src(instr
->src
[0]);
4493 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4494 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4495 const fs_reg tmp
= bld
.vgrf(value
.type
);
4496 const fs_builder ubld
= bld
.exec_all();
4497 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4498 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4499 bld
.MOV(retype(dest
, value
.type
), tmp
);
4501 /* For larger data types, we have to either emit dispatch_width many
4502 * MOVs or else fall back to doing indirects.
4504 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4505 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4507 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4512 case nir_intrinsic_reduce
: {
4513 fs_reg src
= get_nir_src(instr
->src
[0]);
4514 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4515 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4516 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4517 cluster_size
= dispatch_width
;
4519 /* Figure out the source type */
4520 src
.type
= brw_type_for_nir_type(devinfo
,
4521 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4522 nir_src_bit_size(instr
->src
[0])));
4524 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4525 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4526 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4528 /* Set up a register for all of our scratching around and initialize it
4529 * to reduction operation's identity value.
4531 fs_reg scan
= bld
.vgrf(src
.type
);
4532 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4534 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4536 dest
.type
= src
.type
;
4537 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4538 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4539 * the distance between clusters is at least 2 GRFs. In this case,
4540 * we don't need the weird striding of the CLUSTER_BROADCAST
4541 * instruction and can just do regular MOVs.
4543 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4544 const unsigned groups
=
4545 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4546 const unsigned group_size
= dispatch_width
/ groups
;
4547 for (unsigned i
= 0; i
< groups
; i
++) {
4548 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4549 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4550 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4551 component(scan
, comp
));
4554 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4555 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4560 case nir_intrinsic_inclusive_scan
:
4561 case nir_intrinsic_exclusive_scan
: {
4562 fs_reg src
= get_nir_src(instr
->src
[0]);
4563 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4565 /* Figure out the source type */
4566 src
.type
= brw_type_for_nir_type(devinfo
,
4567 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4568 nir_src_bit_size(instr
->src
[0])));
4570 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4571 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4572 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4574 /* Set up a register for all of our scratching around and initialize it
4575 * to reduction operation's identity value.
4577 fs_reg scan
= bld
.vgrf(src
.type
);
4578 const fs_builder allbld
= bld
.exec_all();
4579 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4581 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4582 /* Exclusive scan is a bit harder because we have to do an annoying
4583 * shift of the contents before we can begin. To make things worse,
4584 * we can't do this with a normal stride; we have to use indirects.
4586 fs_reg shifted
= bld
.vgrf(src
.type
);
4587 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4588 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4590 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4591 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4595 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4597 bld
.MOV(retype(dest
, src
.type
), scan
);
4601 case nir_intrinsic_begin_invocation_interlock
: {
4602 const fs_builder ubld
= bld
.group(8, 0);
4603 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4605 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4611 case nir_intrinsic_end_invocation_interlock
: {
4612 /* We don't need to do anything here */
4617 unreachable("unknown intrinsic");
4622 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4623 int op
, nir_intrinsic_instr
*instr
)
4625 if (stage
== MESA_SHADER_FRAGMENT
)
4626 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4629 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4630 dest
= get_nir_dest(instr
->dest
);
4632 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4633 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4634 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4635 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4636 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4639 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4640 data
= get_nir_src(instr
->src
[2]);
4642 if (op
== BRW_AOP_CMPWR
) {
4643 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4644 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4645 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4648 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4650 /* Emit the actual atomic operation */
4652 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4653 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4657 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4658 int op
, nir_intrinsic_instr
*instr
)
4660 if (stage
== MESA_SHADER_FRAGMENT
)
4661 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4664 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4665 dest
= get_nir_dest(instr
->dest
);
4667 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4668 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4669 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4670 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4671 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4673 fs_reg data
= get_nir_src(instr
->src
[2]);
4674 if (op
== BRW_AOP_FCMPWR
) {
4675 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4676 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4677 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4680 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4682 /* Emit the actual atomic operation */
4684 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4685 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4689 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4690 int op
, nir_intrinsic_instr
*instr
)
4693 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4694 dest
= get_nir_dest(instr
->dest
);
4696 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4697 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4698 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4699 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4702 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4703 data
= get_nir_src(instr
->src
[1]);
4704 if (op
== BRW_AOP_CMPWR
) {
4705 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4706 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4707 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4710 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4712 /* Get the offset */
4713 if (nir_src_is_const(instr
->src
[0])) {
4714 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4715 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4717 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4718 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4719 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4720 brw_imm_ud(instr
->const_index
[0]));
4723 /* Emit the actual atomic operation operation */
4725 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4726 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4730 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4731 int op
, nir_intrinsic_instr
*instr
)
4734 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4735 dest
= get_nir_dest(instr
->dest
);
4737 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4738 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4739 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4740 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4742 fs_reg data
= get_nir_src(instr
->src
[1]);
4743 if (op
== BRW_AOP_FCMPWR
) {
4744 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4745 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4746 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4749 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4751 /* Get the offset */
4752 if (nir_src_is_const(instr
->src
[0])) {
4753 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4754 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4756 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4757 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4758 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4759 brw_imm_ud(instr
->const_index
[0]));
4762 /* Emit the actual atomic operation operation */
4764 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4765 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4769 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
4770 int op
, nir_intrinsic_instr
*instr
)
4772 if (stage
== MESA_SHADER_FRAGMENT
)
4773 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4776 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4777 dest
= get_nir_dest(instr
->dest
);
4779 fs_reg addr
= get_nir_src(instr
->src
[0]);
4782 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4783 data
= get_nir_src(instr
->src
[1]);
4785 if (op
== BRW_AOP_CMPWR
) {
4786 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4787 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4788 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4792 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4793 dest
, addr
, data
, brw_imm_ud(op
));
4797 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
4798 int op
, nir_intrinsic_instr
*instr
)
4800 if (stage
== MESA_SHADER_FRAGMENT
)
4801 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4803 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
4804 fs_reg dest
= get_nir_dest(instr
->dest
);
4806 fs_reg addr
= get_nir_src(instr
->src
[0]);
4808 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
4809 fs_reg data
= get_nir_src(instr
->src
[1]);
4811 if (op
== BRW_AOP_FCMPWR
) {
4812 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4813 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4814 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4818 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4819 dest
, addr
, data
, brw_imm_ud(op
));
4823 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4825 unsigned texture
= instr
->texture_index
;
4826 unsigned sampler
= instr
->sampler_index
;
4828 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4830 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4831 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4833 int lod_components
= 0;
4835 /* The hardware requires a LOD for buffer textures */
4836 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4837 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4839 uint32_t header_bits
= 0;
4840 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4841 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4842 switch (instr
->src
[i
].src_type
) {
4843 case nir_tex_src_bias
:
4844 srcs
[TEX_LOGICAL_SRC_LOD
] =
4845 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4847 case nir_tex_src_comparator
:
4848 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4850 case nir_tex_src_coord
:
4851 switch (instr
->op
) {
4853 case nir_texop_txf_ms
:
4854 case nir_texop_txf_ms_mcs
:
4855 case nir_texop_samples_identical
:
4856 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4859 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4863 case nir_tex_src_ddx
:
4864 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4865 lod_components
= nir_tex_instr_src_size(instr
, i
);
4867 case nir_tex_src_ddy
:
4868 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4870 case nir_tex_src_lod
:
4871 switch (instr
->op
) {
4873 srcs
[TEX_LOGICAL_SRC_LOD
] =
4874 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4877 srcs
[TEX_LOGICAL_SRC_LOD
] =
4878 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4881 srcs
[TEX_LOGICAL_SRC_LOD
] =
4882 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4886 case nir_tex_src_min_lod
:
4887 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
4888 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4890 case nir_tex_src_ms_index
:
4891 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4894 case nir_tex_src_offset
: {
4895 nir_const_value
*const_offset
=
4896 nir_src_as_const_value(instr
->src
[i
].src
);
4897 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
4898 unsigned offset_bits
= 0;
4900 brw_texture_offset(const_offset
->i32
,
4901 nir_tex_instr_src_size(instr
, i
),
4903 header_bits
|= offset_bits
;
4905 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4906 retype(src
, BRW_REGISTER_TYPE_D
);
4911 case nir_tex_src_projector
:
4912 unreachable("should be lowered");
4914 case nir_tex_src_texture_offset
: {
4915 /* Emit code to evaluate the actual indexing expression */
4916 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4917 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4918 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4922 case nir_tex_src_sampler_offset
: {
4923 /* Emit code to evaluate the actual indexing expression */
4924 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4925 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4926 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4930 case nir_tex_src_ms_mcs
:
4931 assert(instr
->op
== nir_texop_txf_ms
);
4932 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4935 case nir_tex_src_plane
: {
4936 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
4937 const uint32_t texture_index
=
4938 instr
->texture_index
+
4939 stage_prog_data
->binding_table
.plane_start
[plane
] -
4940 stage_prog_data
->binding_table
.texture_start
;
4942 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4947 unreachable("unknown texture source");
4951 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4952 (instr
->op
== nir_texop_txf_ms
||
4953 instr
->op
== nir_texop_samples_identical
)) {
4954 if (devinfo
->gen
>= 7 &&
4955 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4956 srcs
[TEX_LOGICAL_SRC_MCS
] =
4957 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4958 instr
->coord_components
,
4959 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4961 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4965 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4966 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4969 switch (instr
->op
) {
4971 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4972 SHADER_OPCODE_TXL_LOGICAL
);
4975 opcode
= FS_OPCODE_TXB_LOGICAL
;
4978 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4981 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4984 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4986 case nir_texop_txf_ms
:
4987 if ((key_tex
->msaa_16
& (1 << sampler
)))
4988 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4990 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4992 case nir_texop_txf_ms_mcs
:
4993 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4995 case nir_texop_query_levels
:
4997 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5000 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5003 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5004 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5006 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5008 case nir_texop_texture_samples
:
5009 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5011 case nir_texop_samples_identical
: {
5012 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5014 /* If mcs is an immediate value, it means there is no MCS. In that case
5015 * just return false.
5017 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5018 bld
.MOV(dst
, brw_imm_ud(0u));
5019 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5020 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5021 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5022 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5023 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5025 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5026 BRW_CONDITIONAL_EQ
);
5031 unreachable("unknown texture opcode");
5034 if (instr
->op
== nir_texop_tg4
) {
5035 if (instr
->component
== 1 &&
5036 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5037 /* gather4 sampler is broken for green channel on RG32F --
5038 * we must ask for blue instead.
5040 header_bits
|= 2 << 16;
5042 header_bits
|= instr
->component
<< 16;
5046 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5047 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5048 inst
->offset
= header_bits
;
5050 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5051 if (devinfo
->gen
>= 9 &&
5052 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5053 unsigned write_mask
= instr
->dest
.is_ssa
?
5054 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5055 (1 << dest_size
) - 1;
5056 assert(write_mask
!= 0); /* dead code should have been eliminated */
5057 inst
->size_written
= util_last_bit(write_mask
) *
5058 inst
->dst
.component_size(inst
->exec_size
);
5060 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5063 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5064 inst
->shadow_compare
= true;
5066 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5067 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5070 for (unsigned i
= 0; i
< dest_size
; i
++)
5071 nir_dest
[i
] = offset(dst
, bld
, i
);
5073 if (instr
->op
== nir_texop_query_levels
) {
5074 /* # levels is in .w */
5075 nir_dest
[0] = offset(dst
, bld
, 3);
5076 } else if (instr
->op
== nir_texop_txs
&&
5077 dest_size
>= 3 && devinfo
->gen
< 7) {
5078 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5079 fs_reg depth
= offset(dst
, bld
, 2);
5080 nir_dest
[2] = vgrf(glsl_type::int_type
);
5081 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5084 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5088 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5090 switch (instr
->type
) {
5091 case nir_jump_break
:
5092 bld
.emit(BRW_OPCODE_BREAK
);
5094 case nir_jump_continue
:
5095 bld
.emit(BRW_OPCODE_CONTINUE
);
5097 case nir_jump_return
:
5099 unreachable("unknown jump");
5104 * This helper takes a source register and un/shuffles it into the destination
5107 * If source type size is smaller than destination type size the operation
5108 * needed is a component shuffle. The opposite case would be an unshuffle. If
5109 * source/destination type size is equal a shuffle is done that would be
5110 * equivalent to a simple MOV.
5112 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5113 * components .xyz 16-bit vector on SIMD8 would be.
5115 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5116 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5118 * This helper will return the following 2 32-bit components with the 16-bit
5121 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5122 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5124 * For unshuffle, the example would be the opposite, a 64-bit type source
5125 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5128 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5129 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5130 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5131 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5133 * The returned result would be the following 4 32-bit components unshuffled:
5135 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5136 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5137 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5138 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5140 * - Source and destination register must not be overlapped.
5141 * - components units are measured in terms of the smaller type between
5142 * source and destination because we are un/shuffling the smaller
5143 * components from/into the bigger ones.
5144 * - first_component parameter allows skipping source components.
5147 shuffle_src_to_dst(const fs_builder
&bld
,
5150 uint32_t first_component
,
5151 uint32_t components
)
5153 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5154 assert(!regions_overlap(dst
,
5155 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5156 offset(src
, bld
, first_component
),
5157 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5158 for (unsigned i
= 0; i
< components
; i
++) {
5159 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5160 offset(src
, bld
, i
+ first_component
));
5162 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5163 /* Source is shuffled into destination */
5164 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5165 assert(!regions_overlap(dst
,
5166 type_sz(dst
.type
) * bld
.dispatch_width() *
5167 DIV_ROUND_UP(components
, size_ratio
),
5168 offset(src
, bld
, first_component
),
5169 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5171 brw_reg_type shuffle_type
=
5172 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5173 BRW_REGISTER_TYPE_D
);
5174 for (unsigned i
= 0; i
< components
; i
++) {
5175 fs_reg shuffle_component_i
=
5176 subscript(offset(dst
, bld
, i
/ size_ratio
),
5177 shuffle_type
, i
% size_ratio
);
5178 bld
.MOV(shuffle_component_i
,
5179 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5182 /* Source is unshuffled into destination */
5183 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5184 assert(!regions_overlap(dst
,
5185 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5186 offset(src
, bld
, first_component
/ size_ratio
),
5187 type_sz(src
.type
) * bld
.dispatch_width() *
5188 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5191 brw_reg_type shuffle_type
=
5192 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5193 BRW_REGISTER_TYPE_D
);
5194 for (unsigned i
= 0; i
< components
; i
++) {
5195 fs_reg shuffle_component_i
=
5196 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5197 shuffle_type
, (first_component
+ i
) % size_ratio
);
5198 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5199 shuffle_component_i
);
5205 shuffle_from_32bit_read(const fs_builder
&bld
,
5208 uint32_t first_component
,
5209 uint32_t components
)
5211 assert(type_sz(src
.type
) == 4);
5213 /* This function takes components in units of the destination type while
5214 * shuffle_src_to_dst takes components in units of the smallest type
5216 if (type_sz(dst
.type
) > 4) {
5217 assert(type_sz(dst
.type
) == 8);
5218 first_component
*= 2;
5222 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5226 shuffle_for_32bit_write(const fs_builder
&bld
,
5228 uint32_t first_component
,
5229 uint32_t components
)
5231 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5232 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5233 /* This function takes components in units of the source type while
5234 * shuffle_src_to_dst takes components in units of the smallest type
5236 if (type_sz(src
.type
) > 4) {
5237 assert(type_sz(src
.type
) == 8);
5238 first_component
*= 2;
5242 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5248 setup_imm_df(const fs_builder
&bld
, double v
)
5250 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5251 assert(devinfo
->gen
>= 7);
5253 if (devinfo
->gen
>= 8)
5254 return brw_imm_df(v
);
5256 /* gen7.5 does not support DF immediates straighforward but the DIM
5257 * instruction allows to set the 64-bit immediate value.
5259 if (devinfo
->is_haswell
) {
5260 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5261 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5262 ubld
.DIM(dst
, brw_imm_df(v
));
5263 return component(dst
, 0);
5266 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5267 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5268 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5270 * Alternatively, we could also produce a normal VGRF (without stride 0)
5271 * by writing to all the channels in the VGRF, however, that would hit the
5272 * gen7 bug where we have to split writes that span more than 1 register
5273 * into instructions with a width of 4 (otherwise the write to the second
5274 * register written runs into an execmask hardware bug) which isn't very
5287 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5288 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5289 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5290 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5292 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5296 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5298 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5299 bld
.MOV(tmp
, brw_imm_w(v
));
5304 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5306 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5307 bld
.MOV(tmp
, brw_imm_uw(v
));