2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "util/u_math.h"
29 #include "util/bitscan.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
48 fs_visitor::nir_setup_outputs()
50 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
53 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
55 /* Calculate the size of output registers in a separate pass, before
56 * allocating them. With ARB_enhanced_layouts, multiple output variables
57 * may occupy the same slot, but have different type sizes.
59 nir_foreach_variable(var
, &nir
->outputs
) {
60 const int loc
= var
->data
.driver_location
;
61 const unsigned var_vec4s
=
62 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
63 : type_size_vec4(var
->type
);
64 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
67 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
68 if (vec4s
[loc
] == 0) {
73 unsigned reg_size
= vec4s
[loc
];
75 /* Check if there are any ranges that start within this range and extend
76 * past it. If so, include them in this allocation.
78 for (unsigned i
= 1; i
< reg_size
; i
++)
79 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
81 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
82 for (unsigned i
= 0; i
< reg_size
; i
++)
83 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
90 fs_visitor::nir_setup_uniforms()
92 /* Only the first compile gets to set up uniforms. */
93 if (push_constant_loc
) {
94 assert(pull_constant_loc
);
98 uniforms
= nir
->num_uniforms
/ 4;
100 if (stage
== MESA_SHADER_COMPUTE
) {
101 /* Add a uniform for the thread local id. It must be the last uniform
104 assert(uniforms
== prog_data
->nr_params
);
105 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
106 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
107 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
112 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
116 nir_foreach_instr(instr
, block
) {
117 if (instr
->type
!= nir_instr_type_intrinsic
)
120 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
121 switch (intrin
->intrinsic
) {
122 case nir_intrinsic_load_vertex_id
:
123 case nir_intrinsic_load_base_vertex
:
124 unreachable("should be lowered by nir_lower_system_values().");
126 case nir_intrinsic_load_vertex_id_zero_base
:
127 case nir_intrinsic_load_is_indexed_draw
:
128 case nir_intrinsic_load_first_vertex
:
129 case nir_intrinsic_load_instance_id
:
130 case nir_intrinsic_load_base_instance
:
131 case nir_intrinsic_load_draw_id
:
132 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
134 case nir_intrinsic_load_invocation_id
:
135 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
137 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
138 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
139 if (reg
->file
== BAD_FILE
) {
140 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
141 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
142 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
143 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
148 case nir_intrinsic_load_sample_pos
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_samplepos_setup();
155 case nir_intrinsic_load_sample_id
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_sampleid_setup();
162 case nir_intrinsic_load_sample_mask_in
:
163 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
164 assert(v
->devinfo
->gen
>= 7);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplemaskin_setup();
170 case nir_intrinsic_load_work_group_id
:
171 assert(v
->stage
== MESA_SHADER_COMPUTE
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_cs_work_group_id_setup();
177 case nir_intrinsic_load_helper_invocation
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
180 if (reg
->file
== BAD_FILE
) {
181 const fs_builder abld
=
182 v
->bld
.annotate("gl_HelperInvocation", NULL
);
184 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
185 * pixel mask is in g1.7 of the thread payload.
187 * We move the per-channel pixel enable bit to the low bit of each
188 * channel by shifting the byte containing the pixel mask by the
189 * vector immediate 0x76543210UV.
191 * The region of <1,8,0> reads only 1 byte (the pixel masks for
192 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
193 * masks for 2 and 3) in SIMD16.
195 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
197 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
198 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
199 hbld
.SHR(offset(shifted
, hbld
, i
),
200 stride(retype(brw_vec1_grf(1 + i
, 7),
201 BRW_REGISTER_TYPE_UB
),
203 brw_imm_v(0x76543210));
206 /* A set bit in the pixel mask means the channel is enabled, but
207 * that is the opposite of gl_HelperInvocation so we need to invert
210 * The negate source-modifier bit of logical instructions on Gen8+
211 * performs 1's complement negation, so we can use that instead of
214 fs_reg inverted
= negate(shifted
);
215 if (v
->devinfo
->gen
< 8) {
216 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
217 abld
.NOT(inverted
, shifted
);
220 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
221 * with 1 and negating.
223 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
224 abld
.AND(anded
, inverted
, brw_imm_uw(1));
226 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
227 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
241 fs_visitor::nir_emit_system_values()
243 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
244 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
245 nir_system_values
[i
] = fs_reg();
248 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
249 * never end up using it.
252 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
253 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
254 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
256 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
257 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
258 if (dispatch_width
> 8)
259 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
260 if (dispatch_width
> 16) {
261 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
262 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
266 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
267 nir_foreach_block(block
, impl
)
268 emit_system_values_block(block
, this);
272 * Returns a type based on a reference_type (word, float, half-float) and a
275 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
277 * @FIXME: 64-bit return types are always DF on integer types to maintain
278 * compability with uses of DF previously to the introduction of int64
282 brw_reg_type_from_bit_size(const unsigned bit_size
,
283 const brw_reg_type reference_type
)
285 switch(reference_type
) {
286 case BRW_REGISTER_TYPE_HF
:
287 case BRW_REGISTER_TYPE_F
:
288 case BRW_REGISTER_TYPE_DF
:
291 return BRW_REGISTER_TYPE_HF
;
293 return BRW_REGISTER_TYPE_F
;
295 return BRW_REGISTER_TYPE_DF
;
297 unreachable("Invalid bit size");
299 case BRW_REGISTER_TYPE_B
:
300 case BRW_REGISTER_TYPE_W
:
301 case BRW_REGISTER_TYPE_D
:
302 case BRW_REGISTER_TYPE_Q
:
305 return BRW_REGISTER_TYPE_B
;
307 return BRW_REGISTER_TYPE_W
;
309 return BRW_REGISTER_TYPE_D
;
311 return BRW_REGISTER_TYPE_Q
;
313 unreachable("Invalid bit size");
315 case BRW_REGISTER_TYPE_UB
:
316 case BRW_REGISTER_TYPE_UW
:
317 case BRW_REGISTER_TYPE_UD
:
318 case BRW_REGISTER_TYPE_UQ
:
321 return BRW_REGISTER_TYPE_UB
;
323 return BRW_REGISTER_TYPE_UW
;
325 return BRW_REGISTER_TYPE_UD
;
327 return BRW_REGISTER_TYPE_UQ
;
329 unreachable("Invalid bit size");
332 unreachable("Unknown type");
337 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
339 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
340 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
341 nir_locals
[i
] = fs_reg();
344 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
345 unsigned array_elems
=
346 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
347 unsigned size
= array_elems
* reg
->num_components
;
348 const brw_reg_type reg_type
=
349 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
350 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
353 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
356 nir_emit_cf_list(&impl
->body
);
360 fs_visitor::nir_emit_cf_list(exec_list
*list
)
362 exec_list_validate(list
);
363 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
364 switch (node
->type
) {
366 nir_emit_if(nir_cf_node_as_if(node
));
369 case nir_cf_node_loop
:
370 nir_emit_loop(nir_cf_node_as_loop(node
));
373 case nir_cf_node_block
:
374 nir_emit_block(nir_cf_node_as_block(node
));
378 unreachable("Invalid CFG node block");
384 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
386 /* first, put the condition into f0 */
387 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
388 retype(get_nir_src(if_stmt
->condition
),
389 BRW_REGISTER_TYPE_D
));
390 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
392 bld
.IF(BRW_PREDICATE_NORMAL
);
394 nir_emit_cf_list(&if_stmt
->then_list
);
396 /* note: if the else is empty, dead CF elimination will remove it */
397 bld
.emit(BRW_OPCODE_ELSE
);
399 nir_emit_cf_list(&if_stmt
->else_list
);
401 bld
.emit(BRW_OPCODE_ENDIF
);
403 if (devinfo
->gen
< 7)
404 limit_dispatch_width(16, "Non-uniform control flow unsupported "
409 fs_visitor::nir_emit_loop(nir_loop
*loop
)
411 bld
.emit(BRW_OPCODE_DO
);
413 nir_emit_cf_list(&loop
->body
);
415 bld
.emit(BRW_OPCODE_WHILE
);
417 if (devinfo
->gen
< 7)
418 limit_dispatch_width(16, "Non-uniform control flow unsupported "
423 fs_visitor::nir_emit_block(nir_block
*block
)
425 nir_foreach_instr(instr
, block
) {
426 nir_emit_instr(instr
);
431 fs_visitor::nir_emit_instr(nir_instr
*instr
)
433 const fs_builder abld
= bld
.annotate(NULL
, instr
);
435 switch (instr
->type
) {
436 case nir_instr_type_alu
:
437 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
440 case nir_instr_type_deref
:
441 /* Derefs can exist for images but they do nothing */
444 case nir_instr_type_intrinsic
:
446 case MESA_SHADER_VERTEX
:
447 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
449 case MESA_SHADER_TESS_CTRL
:
450 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
452 case MESA_SHADER_TESS_EVAL
:
453 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
455 case MESA_SHADER_GEOMETRY
:
456 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
458 case MESA_SHADER_FRAGMENT
:
459 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
461 case MESA_SHADER_COMPUTE
:
462 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 unreachable("unsupported shader stage");
469 case nir_instr_type_tex
:
470 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
473 case nir_instr_type_load_const
:
474 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
477 case nir_instr_type_ssa_undef
:
478 /* We create a new VGRF for undefs on every use (by handling
479 * them in get_nir_src()), rather than for each definition.
480 * This helps register coalescing eliminate MOVs from undef.
484 case nir_instr_type_jump
:
485 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
489 unreachable("unknown instruction type");
494 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
498 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
499 const fs_reg
&result
)
501 if (!instr
->src
[0].src
.is_ssa
||
502 !instr
->src
[0].src
.ssa
->parent_instr
)
505 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
508 nir_alu_instr
*src0
=
509 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
511 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
512 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
515 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
517 /* Element type to extract.*/
518 const brw_reg_type type
= brw_int_type(
519 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
520 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
522 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
523 op0
.type
= brw_type_for_nir_type(devinfo
,
524 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
525 nir_src_bit_size(src0
->src
[0].src
)));
526 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
528 set_saturate(instr
->dest
.saturate
,
529 bld
.MOV(result
, subscript(op0
, type
, element
)));
534 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
535 const fs_reg
&result
)
537 if (!instr
->src
[0].src
.is_ssa
||
538 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
541 nir_intrinsic_instr
*src0
=
542 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
544 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
547 if (!nir_src_is_const(instr
->src
[1].src
) ||
548 !nir_src_is_const(instr
->src
[2].src
))
551 const float value1
= nir_src_as_float(instr
->src
[1].src
);
552 const float value2
= nir_src_as_float(instr
->src
[2].src
);
553 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
556 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
557 assert(value1
== -value2
);
559 fs_reg tmp
= vgrf(glsl_type::int_type
);
561 if (devinfo
->gen
>= 6) {
562 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
563 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
565 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
567 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
568 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
570 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
572 * This negation looks like it's safe in practice, because bits 0:4 will
573 * surely be TRIANGLES
576 if (value1
== -1.0f
) {
580 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
581 g0
, brw_imm_uw(0x3f80));
583 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
584 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
586 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
588 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
589 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
591 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
593 * This negation looks like it's safe in practice, because bits 0:4 will
594 * surely be TRIANGLES
597 if (value1
== -1.0f
) {
601 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
603 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
609 emit_find_msb_using_lzd(const fs_builder
&bld
,
610 const fs_reg
&result
,
618 /* LZD of an absolute value source almost always does the right
619 * thing. There are two problem values:
621 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
622 * 0. However, findMSB(int(0x80000000)) == 30.
624 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
625 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
627 * For a value of zero or negative one, -1 will be returned.
629 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
630 * findMSB(-(1<<x)) should return x-1.
632 * For all negative number cases, including 0x80000000 and
633 * 0xffffffff, the correct value is obtained from LZD if instead of
634 * negating the (already negative) value the logical-not is used. A
635 * conditonal logical-not can be achieved in two instructions.
637 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
639 bld
.ASR(temp
, src
, brw_imm_d(31));
640 bld
.XOR(temp
, temp
, src
);
643 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
644 retype(temp
, BRW_REGISTER_TYPE_UD
));
646 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
647 * from the LSB side. Subtract the result from 31 to convert the MSB
648 * count into an LSB count. If no bits are set, LZD will return 32.
649 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
651 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
652 inst
->src
[0].negate
= true;
656 brw_rnd_mode_from_nir_op (const nir_op op
) {
658 case nir_op_f2f16_rtz
:
659 return BRW_RND_MODE_RTZ
;
660 case nir_op_f2f16_rtne
:
661 return BRW_RND_MODE_RTNE
;
663 unreachable("Operation doesn't support rounding mode");
668 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
670 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
673 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
674 result
.type
= brw_type_for_nir_type(devinfo
,
675 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
676 nir_dest_bit_size(instr
->dest
.dest
)));
679 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
680 op
[i
] = get_nir_src(instr
->src
[i
].src
);
681 op
[i
].type
= brw_type_for_nir_type(devinfo
,
682 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
683 nir_src_bit_size(instr
->src
[i
].src
)));
684 op
[i
].abs
= instr
->src
[i
].abs
;
685 op
[i
].negate
= instr
->src
[i
].negate
;
688 /* We get a bunch of mov's out of the from_ssa pass and they may still
689 * be vectorized. We'll handle them as a special-case. We'll also
690 * handle vecN here because it's basically the same thing.
698 fs_reg temp
= result
;
699 bool need_extra_copy
= false;
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 if (!instr
->src
[i
].src
.is_ssa
&&
702 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
703 need_extra_copy
= true;
704 temp
= bld
.vgrf(result
.type
, 4);
709 for (unsigned i
= 0; i
< 4; i
++) {
710 if (!(instr
->dest
.write_mask
& (1 << i
)))
713 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
714 inst
= bld
.MOV(offset(temp
, bld
, i
),
715 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
717 inst
= bld
.MOV(offset(temp
, bld
, i
),
718 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
720 inst
->saturate
= instr
->dest
.saturate
;
723 /* In this case the source and destination registers were the same,
724 * so we need to insert an extra set of moves in order to deal with
727 if (need_extra_copy
) {
728 for (unsigned i
= 0; i
< 4; i
++) {
729 if (!(instr
->dest
.write_mask
& (1 << i
)))
732 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
741 /* At this point, we have dealt with any instruction that operates on
742 * more than a single channel. Therefore, we can just adjust the source
743 * and destination registers for that channel and emit the instruction.
745 unsigned channel
= 0;
746 if (nir_op_infos
[instr
->op
].output_size
== 0) {
747 /* Since NIR is doing the scalarizing for us, we should only ever see
748 * vectorized operations with a single channel.
750 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
751 channel
= ffs(instr
->dest
.write_mask
) - 1;
753 result
= offset(result
, bld
, channel
);
756 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
757 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
758 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
764 if (optimize_extract_to_float(instr
, result
))
766 inst
= bld
.MOV(result
, op
[0]);
767 inst
->saturate
= instr
->dest
.saturate
;
770 case nir_op_f2f16_rtne
:
771 case nir_op_f2f16_rtz
:
772 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
773 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
776 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
777 * on the HW gen, it is a special hw opcode or just a MOV, and
778 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
780 * But if we want to use that opcode, we need to provide support on
781 * different optimizations and lowerings. As right now HF support is
782 * only for gen8+, it will be better to use directly the MOV, and use
783 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
787 inst
= bld
.MOV(result
, op
[0]);
788 inst
->saturate
= instr
->dest
.saturate
;
798 op
[0].type
= BRW_REGISTER_TYPE_D
;
799 op
[0].negate
= !op
[0].negate
;
821 inst
= bld
.MOV(result
, op
[0]);
822 inst
->saturate
= instr
->dest
.saturate
;
826 assert(!instr
->dest
.saturate
);
828 /* Straightforward since the source can be assumed to be either
829 * strictly >= 0 or strictly <= 0 depending on the setting of the
832 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
834 inst
= (op
[0].negate
)
835 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
836 : bld
.MOV(result
, brw_imm_f(1.0f
));
838 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
839 } else if (type_sz(op
[0].type
) < 8) {
840 /* AND(val, 0x80000000) gives the sign bit.
842 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
845 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
847 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
848 op
[0].type
= BRW_REGISTER_TYPE_UD
;
849 result
.type
= BRW_REGISTER_TYPE_UD
;
850 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
852 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
853 inst
->predicate
= BRW_PREDICATE_NORMAL
;
855 /* For doubles we do the same but we need to consider:
857 * - 2-src instructions can't operate with 64-bit immediates
858 * - The sign is encoded in the high 32-bit of each DF
859 * - We need to produce a DF result.
862 fs_reg zero
= vgrf(glsl_type::double_type
);
863 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
864 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
866 bld
.MOV(result
, zero
);
868 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
869 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
870 brw_imm_ud(0x80000000u
));
872 set_predicate(BRW_PREDICATE_NORMAL
,
873 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
879 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
880 inst
->saturate
= instr
->dest
.saturate
;
884 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
885 inst
->saturate
= instr
->dest
.saturate
;
889 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
890 inst
->saturate
= instr
->dest
.saturate
;
894 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
895 inst
->saturate
= instr
->dest
.saturate
;
899 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
900 inst
->saturate
= instr
->dest
.saturate
;
904 if (fs_key
->high_quality_derivatives
) {
905 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
907 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
909 inst
->saturate
= instr
->dest
.saturate
;
911 case nir_op_fddx_fine
:
912 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
913 inst
->saturate
= instr
->dest
.saturate
;
915 case nir_op_fddx_coarse
:
916 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
917 inst
->saturate
= instr
->dest
.saturate
;
920 if (fs_key
->high_quality_derivatives
) {
921 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
923 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
925 inst
->saturate
= instr
->dest
.saturate
;
927 case nir_op_fddy_fine
:
928 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
929 inst
->saturate
= instr
->dest
.saturate
;
931 case nir_op_fddy_coarse
:
932 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
933 inst
->saturate
= instr
->dest
.saturate
;
938 inst
= bld
.ADD(result
, op
[0], op
[1]);
939 inst
->saturate
= instr
->dest
.saturate
;
942 case nir_op_uadd_sat
:
943 inst
= bld
.ADD(result
, op
[0], op
[1]);
944 inst
->saturate
= true;
948 inst
= bld
.MUL(result
, op
[0], op
[1]);
949 inst
->saturate
= instr
->dest
.saturate
;
953 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
954 bld
.MUL(result
, op
[0], op
[1]);
957 case nir_op_imul_high
:
958 case nir_op_umul_high
:
959 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
960 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
965 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
966 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
969 case nir_op_uadd_carry
:
970 unreachable("Should have been lowered by carry_to_arith().");
972 case nir_op_usub_borrow
:
973 unreachable("Should have been lowered by borrow_to_arith().");
977 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
978 * appears that our hardware just does the right thing for signed
981 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
982 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
986 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
987 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
989 /* Math instructions don't support conditional mod */
990 inst
= bld
.MOV(bld
.null_reg_d(), result
);
991 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
993 /* Now, we need to determine if signs of the sources are different.
994 * When we XOR the sources, the top bit is 0 if they are the same and 1
995 * if they are different. We can then use a conditional modifier to
996 * turn that into a predicate. This leads us to an XOR.l instruction.
998 * Technically, according to the PRM, you're not allowed to use .l on a
999 * XOR instruction. However, emperical experiments and Curro's reading
1000 * of the simulator source both indicate that it's safe.
1002 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1003 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1004 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1005 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1007 /* If the result of the initial remainder operation is non-zero and the
1008 * two sources have different signs, add in a copy of op[1] to get the
1009 * final integer modulus value.
1011 inst
= bld
.ADD(result
, result
, op
[1]);
1012 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1019 case nir_op_fne32
: {
1020 fs_reg dest
= result
;
1022 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1024 dest
= bld
.vgrf(op
[0].type
, 1);
1026 brw_conditional_mod cond
;
1027 switch (instr
->op
) {
1029 cond
= BRW_CONDITIONAL_L
;
1032 cond
= BRW_CONDITIONAL_GE
;
1035 cond
= BRW_CONDITIONAL_Z
;
1038 cond
= BRW_CONDITIONAL_NZ
;
1041 unreachable("bad opcode");
1044 bld
.CMP(dest
, op
[0], op
[1], cond
);
1046 if (bit_size
> 32) {
1047 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1048 } else if(bit_size
< 32) {
1049 /* When we convert the result to 32-bit we need to be careful and do
1050 * it as a signed conversion to get sign extension (for 32-bit true)
1052 const brw_reg_type src_type
=
1053 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1055 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1065 case nir_op_ine32
: {
1066 fs_reg dest
= result
;
1068 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1070 dest
= bld
.vgrf(op
[0].type
, 1);
1072 brw_conditional_mod cond
;
1073 switch (instr
->op
) {
1076 cond
= BRW_CONDITIONAL_L
;
1080 cond
= BRW_CONDITIONAL_GE
;
1083 cond
= BRW_CONDITIONAL_Z
;
1086 cond
= BRW_CONDITIONAL_NZ
;
1089 unreachable("bad opcode");
1091 bld
.CMP(dest
, op
[0], op
[1], cond
);
1093 if (bit_size
> 32) {
1094 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1095 } else if (bit_size
< 32) {
1096 /* When we convert the result to 32-bit we need to be careful and do
1097 * it as a signed conversion to get sign extension (for 32-bit true)
1099 const brw_reg_type src_type
=
1100 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1102 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1108 if (devinfo
->gen
>= 8) {
1109 op
[0] = resolve_source_modifiers(op
[0]);
1111 bld
.NOT(result
, op
[0]);
1114 if (devinfo
->gen
>= 8) {
1115 op
[0] = resolve_source_modifiers(op
[0]);
1116 op
[1] = resolve_source_modifiers(op
[1]);
1118 bld
.XOR(result
, op
[0], op
[1]);
1121 if (devinfo
->gen
>= 8) {
1122 op
[0] = resolve_source_modifiers(op
[0]);
1123 op
[1] = resolve_source_modifiers(op
[1]);
1125 bld
.OR(result
, op
[0], op
[1]);
1128 if (devinfo
->gen
>= 8) {
1129 op
[0] = resolve_source_modifiers(op
[0]);
1130 op
[1] = resolve_source_modifiers(op
[1]);
1132 bld
.AND(result
, op
[0], op
[1]);
1138 case nir_op_b32all_fequal2
:
1139 case nir_op_b32all_iequal2
:
1140 case nir_op_b32all_fequal3
:
1141 case nir_op_b32all_iequal3
:
1142 case nir_op_b32all_fequal4
:
1143 case nir_op_b32all_iequal4
:
1144 case nir_op_b32any_fnequal2
:
1145 case nir_op_b32any_inequal2
:
1146 case nir_op_b32any_fnequal3
:
1147 case nir_op_b32any_inequal3
:
1148 case nir_op_b32any_fnequal4
:
1149 case nir_op_b32any_inequal4
:
1150 unreachable("Lowered by nir_lower_alu_reductions");
1152 case nir_op_fnoise1_1
:
1153 case nir_op_fnoise1_2
:
1154 case nir_op_fnoise1_3
:
1155 case nir_op_fnoise1_4
:
1156 case nir_op_fnoise2_1
:
1157 case nir_op_fnoise2_2
:
1158 case nir_op_fnoise2_3
:
1159 case nir_op_fnoise2_4
:
1160 case nir_op_fnoise3_1
:
1161 case nir_op_fnoise3_2
:
1162 case nir_op_fnoise3_3
:
1163 case nir_op_fnoise3_4
:
1164 case nir_op_fnoise4_1
:
1165 case nir_op_fnoise4_2
:
1166 case nir_op_fnoise4_3
:
1167 case nir_op_fnoise4_4
:
1168 unreachable("not reached: should be handled by lower_noise");
1171 unreachable("not reached: should be handled by ldexp_to_arith()");
1174 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1175 inst
->saturate
= instr
->dest
.saturate
;
1179 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1180 inst
->saturate
= instr
->dest
.saturate
;
1184 case nir_op_f2b32
: {
1185 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1186 if (bit_size
== 64) {
1187 /* two-argument instructions can't take 64-bit immediates */
1191 if (instr
->op
== nir_op_f2b32
) {
1192 zero
= vgrf(glsl_type::double_type
);
1193 tmp
= vgrf(glsl_type::double_type
);
1194 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1196 zero
= vgrf(glsl_type::int64_t_type
);
1197 tmp
= vgrf(glsl_type::int64_t_type
);
1198 bld
.MOV(zero
, brw_imm_q(0));
1201 /* A SIMD16 execution needs to be split in two instructions, so use
1202 * a vgrf instead of the flag register as dst so instruction splitting
1205 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1206 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1209 if (bit_size
== 32) {
1210 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1212 assert(bit_size
== 16);
1213 zero
= instr
->op
== nir_op_f2b32
?
1214 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1216 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1222 inst
= bld
.RNDZ(result
, op
[0]);
1223 inst
->saturate
= instr
->dest
.saturate
;
1226 case nir_op_fceil
: {
1227 op
[0].negate
= !op
[0].negate
;
1228 fs_reg temp
= vgrf(glsl_type::float_type
);
1229 bld
.RNDD(temp
, op
[0]);
1231 inst
= bld
.MOV(result
, temp
);
1232 inst
->saturate
= instr
->dest
.saturate
;
1236 inst
= bld
.RNDD(result
, op
[0]);
1237 inst
->saturate
= instr
->dest
.saturate
;
1240 inst
= bld
.FRC(result
, op
[0]);
1241 inst
->saturate
= instr
->dest
.saturate
;
1243 case nir_op_fround_even
:
1244 inst
= bld
.RNDE(result
, op
[0]);
1245 inst
->saturate
= instr
->dest
.saturate
;
1248 case nir_op_fquantize2f16
: {
1249 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1250 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1251 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1253 /* The destination stride must be at least as big as the source stride. */
1254 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1257 /* Check for denormal */
1258 fs_reg abs_src0
= op
[0];
1259 abs_src0
.abs
= true;
1260 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1262 /* Get the appropriately signed zero */
1263 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1264 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1265 brw_imm_ud(0x80000000));
1266 /* Do the actual F32 -> F16 -> F32 conversion */
1267 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1268 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1269 /* Select that or zero based on normal status */
1270 inst
= bld
.SEL(result
, zero
, tmp32
);
1271 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1272 inst
->saturate
= instr
->dest
.saturate
;
1279 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1280 inst
->saturate
= instr
->dest
.saturate
;
1286 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1287 inst
->saturate
= instr
->dest
.saturate
;
1290 case nir_op_pack_snorm_2x16
:
1291 case nir_op_pack_snorm_4x8
:
1292 case nir_op_pack_unorm_2x16
:
1293 case nir_op_pack_unorm_4x8
:
1294 case nir_op_unpack_snorm_2x16
:
1295 case nir_op_unpack_snorm_4x8
:
1296 case nir_op_unpack_unorm_2x16
:
1297 case nir_op_unpack_unorm_4x8
:
1298 case nir_op_unpack_half_2x16
:
1299 case nir_op_pack_half_2x16
:
1300 unreachable("not reached: should be handled by lower_packing_builtins");
1302 case nir_op_unpack_half_2x16_split_x
:
1303 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1304 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1305 inst
->saturate
= instr
->dest
.saturate
;
1307 case nir_op_unpack_half_2x16_split_y
:
1308 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1309 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1310 inst
->saturate
= instr
->dest
.saturate
;
1313 case nir_op_pack_64_2x32_split
:
1314 case nir_op_pack_32_2x16_split
:
1315 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1318 case nir_op_unpack_64_2x32_split_x
:
1319 case nir_op_unpack_64_2x32_split_y
: {
1320 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1321 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1323 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1327 case nir_op_unpack_32_2x16_split_x
:
1328 case nir_op_unpack_32_2x16_split_y
: {
1329 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1330 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1332 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1337 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1338 inst
->saturate
= instr
->dest
.saturate
;
1341 case nir_op_bitfield_reverse
:
1342 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1343 bld
.BFREV(result
, op
[0]);
1346 case nir_op_bit_count
:
1347 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1348 bld
.CBIT(result
, op
[0]);
1351 case nir_op_ufind_msb
: {
1352 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1353 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1357 case nir_op_ifind_msb
: {
1358 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1360 if (devinfo
->gen
< 7) {
1361 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1363 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1365 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1366 * count from the LSB side. If FBH didn't return an error
1367 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1368 * count into an LSB count.
1370 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1372 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1373 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1374 inst
->src
[0].negate
= true;
1379 case nir_op_find_lsb
:
1380 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1382 if (devinfo
->gen
< 7) {
1383 fs_reg temp
= vgrf(glsl_type::int_type
);
1385 /* (x & -x) generates a value that consists of only the LSB of x.
1386 * For all powers of 2, findMSB(y) == findLSB(y).
1388 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1389 fs_reg negated_src
= src
;
1391 /* One must be negated, and the other must be non-negated. It
1392 * doesn't matter which is which.
1394 negated_src
.negate
= true;
1397 bld
.AND(temp
, src
, negated_src
);
1398 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1400 bld
.FBL(result
, op
[0]);
1404 case nir_op_ubitfield_extract
:
1405 case nir_op_ibitfield_extract
:
1406 unreachable("should have been lowered");
1409 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1410 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1413 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1414 bld
.BFI1(result
, op
[0], op
[1]);
1417 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1418 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1421 case nir_op_bitfield_insert
:
1422 unreachable("not reached: should have been lowered");
1425 bld
.SHL(result
, op
[0], op
[1]);
1428 bld
.ASR(result
, op
[0], op
[1]);
1431 bld
.SHR(result
, op
[0], op
[1]);
1434 case nir_op_pack_half_2x16_split
:
1435 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1439 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1440 inst
->saturate
= instr
->dest
.saturate
;
1444 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1445 inst
->saturate
= instr
->dest
.saturate
;
1448 case nir_op_b32csel
:
1449 if (optimize_frontfacing_ternary(instr
, result
))
1452 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1453 inst
= bld
.SEL(result
, op
[1], op
[2]);
1454 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1457 case nir_op_extract_u8
:
1458 case nir_op_extract_i8
: {
1459 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1464 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1465 * Use two instructions and a word or DWord intermediate integer type.
1467 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1468 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1470 if (instr
->op
== nir_op_extract_i8
) {
1471 /* If we need to sign extend, extract to a word first */
1472 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1473 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1474 bld
.MOV(result
, w_temp
);
1476 /* Otherwise use an AND with 0xff and a word type */
1477 bld
.AND(result
, subscript(op
[0], type
, byte
/ 2), brw_imm_uw(0xff));
1480 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1481 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1486 case nir_op_extract_u16
:
1487 case nir_op_extract_i16
: {
1488 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1489 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1490 bld
.MOV(result
, subscript(op
[0], type
, word
));
1495 unreachable("unhandled instruction");
1498 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1499 * to sign extend the low bit to 0/~0
1501 if (devinfo
->gen
<= 5 &&
1502 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1503 fs_reg masked
= vgrf(glsl_type::int_type
);
1504 bld
.AND(masked
, result
, brw_imm_d(1));
1505 masked
.negate
= true;
1506 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1511 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1512 nir_load_const_instr
*instr
)
1514 const brw_reg_type reg_type
=
1515 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1516 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1518 switch (instr
->def
.bit_size
) {
1520 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1521 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1525 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1526 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1530 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1531 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1535 assert(devinfo
->gen
>= 7);
1536 if (devinfo
->gen
== 7) {
1537 /* We don't get 64-bit integer types until gen8 */
1538 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1539 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1540 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1543 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1544 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1549 unreachable("Invalid bit size");
1552 nir_ssa_values
[instr
->def
.index
] = reg
;
1556 fs_visitor::get_nir_src(const nir_src
&src
)
1560 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1561 const brw_reg_type reg_type
=
1562 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1563 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1565 reg
= nir_ssa_values
[src
.ssa
->index
];
1568 /* We don't handle indirects on locals */
1569 assert(src
.reg
.indirect
== NULL
);
1570 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1571 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1574 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1575 /* The only 64-bit type available on gen7 is DF, so use that. */
1576 reg
.type
= BRW_REGISTER_TYPE_DF
;
1578 /* To avoid floating-point denorm flushing problems, set the type by
1579 * default to an integer type - instructions that need floating point
1580 * semantics will set this to F if they need to
1582 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1583 BRW_REGISTER_TYPE_D
);
1590 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1592 * This function should not be called on any value which may be 64 bits.
1593 * We could theoretically support 64-bit on gen8+ but we choose not to
1594 * because it wouldn't work in general (no gen7 support) and there are
1595 * enough restrictions in 64-bit immediates that you can't take the return
1596 * value and treat it the same as the result of get_nir_src().
1599 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1601 assert(nir_src_bit_size(src
) == 32);
1602 return nir_src_is_const(src
) ?
1603 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1607 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1610 const brw_reg_type reg_type
=
1611 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1612 dest
.ssa
.bit_size
== 8 ?
1613 BRW_REGISTER_TYPE_D
:
1614 BRW_REGISTER_TYPE_F
);
1615 nir_ssa_values
[dest
.ssa
.index
] =
1616 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1617 return nir_ssa_values
[dest
.ssa
.index
];
1619 /* We don't handle indirects on locals */
1620 assert(dest
.reg
.indirect
== NULL
);
1621 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1622 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1627 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1630 for (unsigned i
= 0; i
< 4; i
++) {
1631 if (!((wr_mask
>> i
) & 1))
1634 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1635 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1636 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1637 if (new_inst
->src
[j
].file
== VGRF
)
1638 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1645 emit_pixel_interpolater_send(const fs_builder
&bld
,
1650 glsl_interp_mode interpolation
)
1652 struct brw_wm_prog_data
*wm_prog_data
=
1653 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1655 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1656 /* 2 floats per slot returned */
1657 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1658 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1660 wm_prog_data
->pulls_bary
= true;
1666 * Computes 1 << x, given a D/UD register containing some value x.
1669 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1671 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1673 fs_reg result
= bld
.vgrf(x
.type
, 1);
1674 fs_reg one
= bld
.vgrf(x
.type
, 1);
1676 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1677 bld
.SHL(result
, one
, x
);
1682 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1684 assert(stage
== MESA_SHADER_GEOMETRY
);
1686 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1688 if (gs_compile
->control_data_header_size_bits
== 0)
1691 /* We can only do EndPrimitive() functionality when the control data
1692 * consists of cut bits. Fortunately, the only time it isn't is when the
1693 * output type is points, in which case EndPrimitive() is a no-op.
1695 if (gs_prog_data
->control_data_format
!=
1696 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1700 /* Cut bits use one bit per vertex. */
1701 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1703 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1704 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1706 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1707 * vertex n, 0 otherwise. So all we need to do here is mark bit
1708 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1709 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1710 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1712 * Note that if EndPrimitive() is called before emitting any vertices, this
1713 * will cause us to set bit 31 of the control_data_bits register to 1.
1714 * That's fine because:
1716 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1717 * output, so the hardware will ignore cut bit 31.
1719 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1720 * last vertex, so setting cut bit 31 has no effect (since the primitive
1721 * is automatically ended when the GS terminates).
1723 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1724 * control_data_bits register to 0 when the first vertex is emitted.
1727 const fs_builder abld
= bld
.annotate("end primitive");
1729 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1730 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1731 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1732 fs_reg mask
= intexp2(abld
, prev_count
);
1733 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1734 * attention to the lower 5 bits of its second source argument, so on this
1735 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1736 * ((vertex_count - 1) % 32).
1738 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1742 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1744 assert(stage
== MESA_SHADER_GEOMETRY
);
1745 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1747 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1749 const fs_builder abld
= bld
.annotate("emit control data bits");
1750 const fs_builder fwa_bld
= bld
.exec_all();
1752 /* We use a single UD register to accumulate control data bits (32 bits
1753 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1756 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1757 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1758 * use the Channel Mask phase to enable/disable which DWord within that
1759 * group to write. (Remember, different SIMD8 channels may have emitted
1760 * different numbers of vertices, so we may need per-slot offsets.)
1762 * Channel masking presents an annoying problem: we may have to replicate
1763 * the data up to 4 times:
1765 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1767 * To avoid penalizing shaders that emit a small number of vertices, we
1768 * can avoid these sometimes: if the size of the control data header is
1769 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1770 * land in the same 128-bit group, so we can skip per-slot offsets.
1772 * Similarly, if the control data header is <= 32 bits, there is only one
1773 * DWord, so we can skip channel masks.
1775 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1777 fs_reg channel_mask
, per_slot_offset
;
1779 if (gs_compile
->control_data_header_size_bits
> 32) {
1780 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1781 channel_mask
= vgrf(glsl_type::uint_type
);
1784 if (gs_compile
->control_data_header_size_bits
> 128) {
1785 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1786 per_slot_offset
= vgrf(glsl_type::uint_type
);
1789 /* Figure out which DWord we're trying to write to using the formula:
1791 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1793 * Since bits_per_vertex is a power of two, and is known at compile
1794 * time, this can be optimized to:
1796 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1798 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1799 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1800 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1801 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1802 unsigned log2_bits_per_vertex
=
1803 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1804 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1806 if (per_slot_offset
.file
!= BAD_FILE
) {
1807 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1808 * the appropriate OWord within the control data header.
1810 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1813 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1814 * write to the appropriate DWORD within the OWORD.
1816 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1817 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1818 channel_mask
= intexp2(fwa_bld
, channel
);
1819 /* Then the channel masks need to be in bits 23:16. */
1820 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1823 /* Store the control data bits in the message payload and send it. */
1825 if (channel_mask
.file
!= BAD_FILE
)
1826 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1827 if (per_slot_offset
.file
!= BAD_FILE
)
1830 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1831 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1833 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1834 if (per_slot_offset
.file
!= BAD_FILE
)
1835 sources
[i
++] = per_slot_offset
;
1836 if (channel_mask
.file
!= BAD_FILE
)
1837 sources
[i
++] = channel_mask
;
1839 sources
[i
++] = this->control_data_bits
;
1842 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1843 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1845 /* We need to increment Global Offset by 256-bits to make room for
1846 * Broadwell's extra "Vertex Count" payload at the beginning of the
1847 * URB entry. Since this is an OWord message, Global Offset is counted
1848 * in 128-bit units, so we must set it to 2.
1850 if (gs_prog_data
->static_vertex_count
== -1)
1855 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1858 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1860 /* Note: we are calling this *before* increasing vertex_count, so
1861 * this->vertex_count == vertex_count - 1 in the formula above.
1864 /* Stream mode uses 2 bits per vertex */
1865 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1867 /* Must be a valid stream */
1868 assert(stream_id
< MAX_VERTEX_STREAMS
);
1870 /* Control data bits are initialized to 0 so we don't have to set any
1871 * bits when sending vertices to stream 0.
1876 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1878 /* reg::sid = stream_id */
1879 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1880 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1882 /* reg:shift_count = 2 * (vertex_count - 1) */
1883 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1884 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1886 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1887 * attention to the lower 5 bits of its second source argument, so on this
1888 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1889 * stream_id << ((2 * (vertex_count - 1)) % 32).
1891 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1892 abld
.SHL(mask
, sid
, shift_count
);
1893 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1897 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1900 assert(stage
== MESA_SHADER_GEOMETRY
);
1902 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1904 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1905 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1907 /* Haswell and later hardware ignores the "Render Stream Select" bits
1908 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1909 * and instead sends all primitives down the pipeline for rasterization.
1910 * If the SOL stage is enabled, "Render Stream Select" is honored and
1911 * primitives bound to non-zero streams are discarded after stream output.
1913 * Since the only purpose of primives sent to non-zero streams is to
1914 * be recorded by transform feedback, we can simply discard all geometry
1915 * bound to these streams when transform feedback is disabled.
1917 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1920 /* If we're outputting 32 control data bits or less, then we can wait
1921 * until the shader is over to output them all. Otherwise we need to
1922 * output them as we go. Now is the time to do it, since we're about to
1923 * output the vertex_count'th vertex, so it's guaranteed that the
1924 * control data bits associated with the (vertex_count - 1)th vertex are
1927 if (gs_compile
->control_data_header_size_bits
> 32) {
1928 const fs_builder abld
=
1929 bld
.annotate("emit vertex: emit control data bits");
1931 /* Only emit control data bits if we've finished accumulating a batch
1932 * of 32 bits. This is the case when:
1934 * (vertex_count * bits_per_vertex) % 32 == 0
1936 * (in other words, when the last 5 bits of vertex_count *
1937 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1938 * integer n (which is always the case, since bits_per_vertex is
1939 * always 1 or 2), this is equivalent to requiring that the last 5-n
1940 * bits of vertex_count are 0:
1942 * vertex_count & (2^(5-n) - 1) == 0
1944 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1947 * vertex_count & (32 / bits_per_vertex - 1) == 0
1949 * TODO: If vertex_count is an immediate, we could do some of this math
1950 * at compile time...
1953 abld
.AND(bld
.null_reg_d(), vertex_count
,
1954 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1955 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1957 abld
.IF(BRW_PREDICATE_NORMAL
);
1958 /* If vertex_count is 0, then no control data bits have been
1959 * accumulated yet, so we can skip emitting them.
1961 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1962 BRW_CONDITIONAL_NEQ
);
1963 abld
.IF(BRW_PREDICATE_NORMAL
);
1964 emit_gs_control_data_bits(vertex_count
);
1965 abld
.emit(BRW_OPCODE_ENDIF
);
1967 /* Reset control_data_bits to 0 so we can start accumulating a new
1970 * Note: in the case where vertex_count == 0, this neutralizes the
1971 * effect of any call to EndPrimitive() that the shader may have
1972 * made before outputting its first vertex.
1974 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1975 inst
->force_writemask_all
= true;
1976 abld
.emit(BRW_OPCODE_ENDIF
);
1979 emit_urb_writes(vertex_count
);
1981 /* In stream mode we have to set control data bits for all vertices
1982 * unless we have disabled control data bits completely (which we do
1983 * do for GL_POINTS outputs that don't use streams).
1985 if (gs_compile
->control_data_header_size_bits
> 0 &&
1986 gs_prog_data
->control_data_format
==
1987 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1988 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1993 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1994 const nir_src
&vertex_src
,
1995 unsigned base_offset
,
1996 const nir_src
&offset_src
,
1997 unsigned num_components
,
1998 unsigned first_component
)
2000 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2001 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2003 /* TODO: figure out push input layout for invocations == 1 */
2004 /* TODO: make this work with 64-bit inputs */
2005 if (gs_prog_data
->invocations
== 1 &&
2006 type_sz(dst
.type
) <= 4 &&
2007 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2008 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2009 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2010 nir_src_as_uint(vertex_src
) * push_reg_count
;
2011 for (unsigned i
= 0; i
< num_components
; i
++) {
2012 bld
.MOV(offset(dst
, bld
, i
),
2013 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2018 /* Resort to the pull model. Ensure the VUE handles are provided. */
2019 assert(gs_prog_data
->base
.include_vue_handles
);
2021 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2022 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2024 if (gs_prog_data
->invocations
== 1) {
2025 if (nir_src_is_const(vertex_src
)) {
2026 /* The vertex index is constant; just select the proper URB handle. */
2028 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2029 BRW_REGISTER_TYPE_UD
);
2031 /* The vertex index is non-constant. We need to use indirect
2032 * addressing to fetch the proper URB handle.
2034 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2035 * indicating that channel <n> should read the handle from
2036 * DWord <n>. We convert that to bytes by multiplying by 4.
2038 * Next, we convert the vertex index to bytes by multiplying
2039 * by 32 (shifting by 5), and add the two together. This is
2040 * the final indirect byte offset.
2042 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2043 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2044 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2045 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2047 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2048 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2049 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2050 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2051 /* Convert vertex_index to bytes (multiply by 32) */
2052 bld
.SHL(vertex_offset_bytes
,
2053 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2055 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2057 /* Use first_icp_handle as the base offset. There is one register
2058 * of URB handles per vertex, so inform the register allocator that
2059 * we might read up to nir->info.gs.vertices_in registers.
2061 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2062 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2063 fs_reg(icp_offset_bytes
),
2064 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2067 assert(gs_prog_data
->invocations
> 1);
2069 if (nir_src_is_const(vertex_src
)) {
2070 unsigned vertex
= nir_src_as_uint(vertex_src
);
2071 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2073 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2074 BRW_REGISTER_TYPE_UD
));
2076 /* The vertex index is non-constant. We need to use indirect
2077 * addressing to fetch the proper URB handle.
2080 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2082 /* Convert vertex_index to bytes (multiply by 4) */
2083 bld
.SHL(icp_offset_bytes
,
2084 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2087 /* Use first_icp_handle as the base offset. There is one DWord
2088 * of URB handles per vertex, so inform the register allocator that
2089 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2091 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2092 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2093 fs_reg(icp_offset_bytes
),
2094 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2101 fs_reg tmp_dst
= dst
;
2102 fs_reg indirect_offset
= get_nir_src(offset_src
);
2103 unsigned num_iterations
= 1;
2104 unsigned orig_num_components
= num_components
;
2106 if (type_sz(dst
.type
) == 8) {
2107 if (num_components
> 2) {
2111 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2113 first_component
= first_component
/ 2;
2116 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2117 if (nir_src_is_const(offset_src
)) {
2118 /* Constant indexing - use global offset. */
2119 if (first_component
!= 0) {
2120 unsigned read_components
= num_components
+ first_component
;
2121 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2122 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2123 inst
->size_written
= read_components
*
2124 tmp
.component_size(inst
->exec_size
);
2125 for (unsigned i
= 0; i
< num_components
; i
++) {
2126 bld
.MOV(offset(tmp_dst
, bld
, i
),
2127 offset(tmp
, bld
, i
+ first_component
));
2130 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2132 inst
->size_written
= num_components
*
2133 tmp_dst
.component_size(inst
->exec_size
);
2135 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2138 /* Indirect indexing - use per-slot offsets as well. */
2139 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2140 unsigned read_components
= num_components
+ first_component
;
2141 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2142 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2143 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2144 if (first_component
!= 0) {
2145 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2147 inst
->size_written
= read_components
*
2148 tmp
.component_size(inst
->exec_size
);
2149 for (unsigned i
= 0; i
< num_components
; i
++) {
2150 bld
.MOV(offset(tmp_dst
, bld
, i
),
2151 offset(tmp
, bld
, i
+ first_component
));
2154 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2156 inst
->size_written
= num_components
*
2157 tmp_dst
.component_size(inst
->exec_size
);
2159 inst
->offset
= base_offset
;
2163 if (type_sz(dst
.type
) == 8) {
2164 shuffle_from_32bit_read(bld
,
2165 offset(dst
, bld
, iter
* 2),
2166 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2171 if (num_iterations
> 1) {
2172 num_components
= orig_num_components
- 2;
2173 if(nir_src_is_const(offset_src
)) {
2176 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2177 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2178 indirect_offset
= new_indirect
;
2185 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2187 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2189 if (nir_src_is_const(*offset_src
)) {
2190 /* The only constant offset we should find is 0. brw_nir.c's
2191 * add_const_offset_to_base() will fold other constant offsets
2192 * into instr->const_index[0].
2194 assert(nir_src_as_uint(*offset_src
) == 0);
2198 return get_nir_src(*offset_src
);
2202 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2203 nir_intrinsic_instr
*instr
)
2205 assert(stage
== MESA_SHADER_VERTEX
);
2208 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2209 dest
= get_nir_dest(instr
->dest
);
2211 switch (instr
->intrinsic
) {
2212 case nir_intrinsic_load_vertex_id
:
2213 case nir_intrinsic_load_base_vertex
:
2214 unreachable("should be lowered by nir_lower_system_values()");
2216 case nir_intrinsic_load_input
: {
2217 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2218 unsigned first_component
= nir_intrinsic_component(instr
);
2219 unsigned num_components
= instr
->num_components
;
2221 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2223 if (type_sz(dest
.type
) == 8)
2224 first_component
/= 2;
2226 /* For 16-bit support maybe a temporary will be needed to copy from
2229 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2230 first_component
, num_components
);
2234 case nir_intrinsic_load_vertex_id_zero_base
:
2235 case nir_intrinsic_load_instance_id
:
2236 case nir_intrinsic_load_base_instance
:
2237 case nir_intrinsic_load_draw_id
:
2238 case nir_intrinsic_load_first_vertex
:
2239 case nir_intrinsic_load_is_indexed_draw
:
2240 unreachable("lowered by brw_nir_lower_vs_inputs");
2243 nir_emit_intrinsic(bld
, instr
);
2249 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2250 nir_intrinsic_instr
*instr
)
2252 assert(stage
== MESA_SHADER_TESS_CTRL
);
2253 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2254 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2257 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2258 dst
= get_nir_dest(instr
->dest
);
2260 switch (instr
->intrinsic
) {
2261 case nir_intrinsic_load_primitive_id
:
2262 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2264 case nir_intrinsic_load_invocation_id
:
2265 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2267 case nir_intrinsic_load_patch_vertices_in
:
2268 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2269 brw_imm_d(tcs_key
->input_vertices
));
2272 case nir_intrinsic_barrier
: {
2273 if (tcs_prog_data
->instances
== 1)
2276 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2277 fs_reg m0_2
= component(m0
, 2);
2279 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2281 /* Zero the message header */
2282 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2284 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2285 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2286 brw_imm_ud(INTEL_MASK(16, 13)));
2288 /* Shift it up to bits 27:24. */
2289 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2291 /* Set the Barrier Count and the enable bit */
2292 chanbld
.OR(m0_2
, m0_2
,
2293 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2295 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2299 case nir_intrinsic_load_input
:
2300 unreachable("nir_lower_io should never give us these.");
2303 case nir_intrinsic_load_per_vertex_input
: {
2304 fs_reg indirect_offset
= get_indirect_offset(instr
);
2305 unsigned imm_offset
= instr
->const_index
[0];
2307 const nir_src
&vertex_src
= instr
->src
[0];
2313 if (nir_src_is_const(vertex_src
)) {
2314 /* Emit a MOV to resolve <0,1,0> regioning. */
2315 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2316 unsigned vertex
= nir_src_as_uint(vertex_src
);
2318 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2319 BRW_REGISTER_TYPE_UD
));
2320 } else if (tcs_prog_data
->instances
== 1 &&
2321 vertex_src
.is_ssa
&&
2322 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2323 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2324 /* For the common case of only 1 instance, an array index of
2325 * gl_InvocationID means reading g1. Skip all the indirect work.
2327 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2329 /* The vertex index is non-constant. We need to use indirect
2330 * addressing to fetch the proper URB handle.
2332 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2334 /* Each ICP handle is a single DWord (4 bytes) */
2335 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2336 bld
.SHL(vertex_offset_bytes
,
2337 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2340 /* Start at g1. We might read up to 4 registers. */
2341 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2342 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2343 brw_imm_ud(4 * REG_SIZE
));
2346 /* We can only read two double components with each URB read, so
2347 * we send two read messages in that case, each one loading up to
2348 * two double components.
2350 unsigned num_iterations
= 1;
2351 unsigned num_components
= instr
->num_components
;
2352 unsigned first_component
= nir_intrinsic_component(instr
);
2353 fs_reg orig_dst
= dst
;
2354 if (type_sz(dst
.type
) == 8) {
2355 first_component
= first_component
/ 2;
2356 if (instr
->num_components
> 2) {
2361 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2365 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2366 if (indirect_offset
.file
== BAD_FILE
) {
2367 /* Constant indexing - use global offset. */
2368 if (first_component
!= 0) {
2369 unsigned read_components
= num_components
+ first_component
;
2370 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2371 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2372 for (unsigned i
= 0; i
< num_components
; i
++) {
2373 bld
.MOV(offset(dst
, bld
, i
),
2374 offset(tmp
, bld
, i
+ first_component
));
2377 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2379 inst
->offset
= imm_offset
;
2382 /* Indirect indexing - use per-slot offsets as well. */
2383 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2384 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2385 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2386 if (first_component
!= 0) {
2387 unsigned read_components
= num_components
+ first_component
;
2388 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2389 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2391 for (unsigned i
= 0; i
< num_components
; i
++) {
2392 bld
.MOV(offset(dst
, bld
, i
),
2393 offset(tmp
, bld
, i
+ first_component
));
2396 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2399 inst
->offset
= imm_offset
;
2402 inst
->size_written
= (num_components
+ first_component
) *
2403 inst
->dst
.component_size(inst
->exec_size
);
2405 /* If we are reading 64-bit data using 32-bit read messages we need
2406 * build proper 64-bit data elements by shuffling the low and high
2407 * 32-bit components around like we do for other things like UBOs
2410 if (type_sz(dst
.type
) == 8) {
2411 shuffle_from_32bit_read(bld
,
2412 offset(orig_dst
, bld
, iter
* 2),
2413 retype(dst
, BRW_REGISTER_TYPE_D
),
2417 /* Copy the temporary to the destination to deal with writemasking.
2419 * Also attempt to deal with gl_PointSize being in the .w component.
2421 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2422 assert(type_sz(dst
.type
) < 8);
2423 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2424 inst
->size_written
= 4 * REG_SIZE
;
2425 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2428 /* If we are loading double data and we need a second read message
2429 * adjust the write offset
2431 if (num_iterations
> 1) {
2432 num_components
= instr
->num_components
- 2;
2439 case nir_intrinsic_load_output
:
2440 case nir_intrinsic_load_per_vertex_output
: {
2441 fs_reg indirect_offset
= get_indirect_offset(instr
);
2442 unsigned imm_offset
= instr
->const_index
[0];
2443 unsigned first_component
= nir_intrinsic_component(instr
);
2446 if (indirect_offset
.file
== BAD_FILE
) {
2447 /* Replicate the patch handle to all enabled channels */
2448 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2449 bld
.MOV(patch_handle
,
2450 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2453 if (first_component
!= 0) {
2454 unsigned read_components
=
2455 instr
->num_components
+ first_component
;
2456 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2457 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2459 inst
->size_written
= read_components
* REG_SIZE
;
2460 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2461 bld
.MOV(offset(dst
, bld
, i
),
2462 offset(tmp
, bld
, i
+ first_component
));
2465 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2467 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2469 inst
->offset
= imm_offset
;
2473 /* Indirect indexing - use per-slot offsets as well. */
2474 const fs_reg srcs
[] = {
2475 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2478 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2479 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2480 if (first_component
!= 0) {
2481 unsigned read_components
=
2482 instr
->num_components
+ first_component
;
2483 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2484 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2486 inst
->size_written
= read_components
* REG_SIZE
;
2487 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2488 bld
.MOV(offset(dst
, bld
, i
),
2489 offset(tmp
, bld
, i
+ first_component
));
2492 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2494 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2496 inst
->offset
= imm_offset
;
2502 case nir_intrinsic_store_output
:
2503 case nir_intrinsic_store_per_vertex_output
: {
2504 fs_reg value
= get_nir_src(instr
->src
[0]);
2505 bool is_64bit
= (instr
->src
[0].is_ssa
?
2506 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2507 fs_reg indirect_offset
= get_indirect_offset(instr
);
2508 unsigned imm_offset
= instr
->const_index
[0];
2509 unsigned mask
= instr
->const_index
[1];
2510 unsigned header_regs
= 0;
2512 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2514 if (indirect_offset
.file
!= BAD_FILE
) {
2515 srcs
[header_regs
++] = indirect_offset
;
2521 unsigned num_components
= util_last_bit(mask
);
2524 /* We can only pack two 64-bit components in a single message, so send
2525 * 2 messages if we have more components
2527 unsigned num_iterations
= 1;
2528 unsigned iter_components
= num_components
;
2529 unsigned first_component
= nir_intrinsic_component(instr
);
2531 first_component
= first_component
/ 2;
2532 if (instr
->num_components
> 2) {
2534 iter_components
= 2;
2538 mask
= mask
<< first_component
;
2540 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2541 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2542 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2543 opcode
= indirect_offset
.file
!= BAD_FILE
?
2544 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2545 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2546 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2547 /* Expand the 64-bit mask to 32-bit channels. We only handle
2548 * two channels in each iteration, so we only care about X/Y.
2550 unsigned mask32
= 0;
2551 if (mask
& WRITEMASK_X
)
2552 mask32
|= WRITEMASK_XY
;
2553 if (mask
& WRITEMASK_Y
)
2554 mask32
|= WRITEMASK_ZW
;
2556 /* If the mask does not include any of the channels X or Y there
2557 * is nothing to do in this iteration. Move on to the next couple
2558 * of 64-bit channels.
2566 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2567 opcode
= indirect_offset
.file
!= BAD_FILE
?
2568 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2569 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2571 opcode
= indirect_offset
.file
!= BAD_FILE
?
2572 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2573 SHADER_OPCODE_URB_WRITE_SIMD8
;
2576 for (unsigned i
= 0; i
< iter_components
; i
++) {
2577 if (!(mask
& (1 << (i
+ first_component
))))
2581 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2583 /* We need to shuffle the 64-bit data to match the layout
2584 * expected by our 32-bit URB write messages. We use a temporary
2587 unsigned channel
= iter
* 2 + i
;
2588 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2590 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2591 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2592 offset(dest
, bld
, 1);
2597 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2598 (is_64bit
? 2 * first_component
: first_component
);
2600 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2601 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2603 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2604 inst
->offset
= imm_offset
;
2607 /* If this is a 64-bit attribute, select the next two 64-bit channels
2608 * to be handled in the next iteration.
2619 nir_emit_intrinsic(bld
, instr
);
2625 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2626 nir_intrinsic_instr
*instr
)
2628 assert(stage
== MESA_SHADER_TESS_EVAL
);
2629 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2632 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2633 dest
= get_nir_dest(instr
->dest
);
2635 switch (instr
->intrinsic
) {
2636 case nir_intrinsic_load_primitive_id
:
2637 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2639 case nir_intrinsic_load_tess_coord
:
2640 /* gl_TessCoord is part of the payload in g1-3 */
2641 for (unsigned i
= 0; i
< 3; i
++) {
2642 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2646 case nir_intrinsic_load_input
:
2647 case nir_intrinsic_load_per_vertex_input
: {
2648 fs_reg indirect_offset
= get_indirect_offset(instr
);
2649 unsigned imm_offset
= instr
->const_index
[0];
2650 unsigned first_component
= nir_intrinsic_component(instr
);
2652 if (type_sz(dest
.type
) == 8) {
2653 first_component
= first_component
/ 2;
2657 if (indirect_offset
.file
== BAD_FILE
) {
2658 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2659 * which is 16 registers (since each holds 2 vec4 slots).
2661 unsigned slot_count
= 1;
2662 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2665 const unsigned max_push_slots
= 32;
2666 if (imm_offset
+ slot_count
<= max_push_slots
) {
2667 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2668 for (int i
= 0; i
< instr
->num_components
; i
++) {
2669 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2670 i
+ first_component
;
2671 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2674 tes_prog_data
->base
.urb_read_length
=
2675 MAX2(tes_prog_data
->base
.urb_read_length
,
2676 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2678 /* Replicate the patch handle to all enabled channels */
2679 const fs_reg srcs
[] = {
2680 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2682 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2683 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2685 if (first_component
!= 0) {
2686 unsigned read_components
=
2687 instr
->num_components
+ first_component
;
2688 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2689 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2691 inst
->size_written
= read_components
* REG_SIZE
;
2692 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2693 bld
.MOV(offset(dest
, bld
, i
),
2694 offset(tmp
, bld
, i
+ first_component
));
2697 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2699 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2702 inst
->offset
= imm_offset
;
2705 /* Indirect indexing - use per-slot offsets as well. */
2707 /* We can only read two double components with each URB read, so
2708 * we send two read messages in that case, each one loading up to
2709 * two double components.
2711 unsigned num_iterations
= 1;
2712 unsigned num_components
= instr
->num_components
;
2713 fs_reg orig_dest
= dest
;
2714 if (type_sz(dest
.type
) == 8) {
2715 if (instr
->num_components
> 2) {
2719 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2723 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2724 const fs_reg srcs
[] = {
2725 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2728 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2729 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2731 if (first_component
!= 0) {
2732 unsigned read_components
=
2733 num_components
+ first_component
;
2734 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2735 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2737 for (unsigned i
= 0; i
< num_components
; i
++) {
2738 bld
.MOV(offset(dest
, bld
, i
),
2739 offset(tmp
, bld
, i
+ first_component
));
2742 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2746 inst
->offset
= imm_offset
;
2747 inst
->size_written
= (num_components
+ first_component
) *
2748 inst
->dst
.component_size(inst
->exec_size
);
2750 /* If we are reading 64-bit data using 32-bit read messages we need
2751 * build proper 64-bit data elements by shuffling the low and high
2752 * 32-bit components around like we do for other things like UBOs
2755 if (type_sz(dest
.type
) == 8) {
2756 shuffle_from_32bit_read(bld
,
2757 offset(orig_dest
, bld
, iter
* 2),
2758 retype(dest
, BRW_REGISTER_TYPE_D
),
2762 /* If we are loading double data and we need a second read message
2765 if (num_iterations
> 1) {
2766 num_components
= instr
->num_components
- 2;
2774 nir_emit_intrinsic(bld
, instr
);
2780 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2781 nir_intrinsic_instr
*instr
)
2783 assert(stage
== MESA_SHADER_GEOMETRY
);
2784 fs_reg indirect_offset
;
2787 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2788 dest
= get_nir_dest(instr
->dest
);
2790 switch (instr
->intrinsic
) {
2791 case nir_intrinsic_load_primitive_id
:
2792 assert(stage
== MESA_SHADER_GEOMETRY
);
2793 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2794 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2795 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2798 case nir_intrinsic_load_input
:
2799 unreachable("load_input intrinsics are invalid for the GS stage");
2801 case nir_intrinsic_load_per_vertex_input
:
2802 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2803 instr
->src
[1], instr
->num_components
,
2804 nir_intrinsic_component(instr
));
2807 case nir_intrinsic_emit_vertex_with_counter
:
2808 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2811 case nir_intrinsic_end_primitive_with_counter
:
2812 emit_gs_end_primitive(instr
->src
[0]);
2815 case nir_intrinsic_set_vertex_count
:
2816 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2819 case nir_intrinsic_load_invocation_id
: {
2820 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2821 assert(val
.file
!= BAD_FILE
);
2822 dest
.type
= val
.type
;
2828 nir_emit_intrinsic(bld
, instr
);
2834 * Fetch the current render target layer index.
2837 fetch_render_target_array_index(const fs_builder
&bld
)
2839 if (bld
.shader
->devinfo
->gen
>= 6) {
2840 /* The render target array index is provided in the thread payload as
2841 * bits 26:16 of r0.0.
2843 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2844 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2848 /* Pre-SNB we only ever render into the first layer of the framebuffer
2849 * since layered rendering is not implemented.
2851 return brw_imm_ud(0);
2856 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2857 * framebuffer at the current fragment coordinates and sample index.
2860 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2863 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2865 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2866 const brw_wm_prog_key
*wm_key
=
2867 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2868 assert(!wm_key
->coherent_fb_fetch
);
2869 const struct brw_wm_prog_data
*wm_prog_data
=
2870 brw_wm_prog_data(stage_prog_data
);
2872 /* Calculate the surface index relative to the start of the texture binding
2873 * table block, since that's what the texturing messages expect.
2875 const unsigned surface
= target
+
2876 wm_prog_data
->binding_table
.render_target_read_start
-
2877 wm_prog_data
->base
.binding_table
.texture_start
;
2879 /* Calculate the fragment coordinates. */
2880 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2881 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2882 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2883 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2885 /* Calculate the sample index and MCS payload when multisampling. Luckily
2886 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2887 * shouldn't be necessary to recompile based on whether the framebuffer is
2890 if (wm_key
->multisample_fbo
&&
2891 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2892 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2894 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2895 const fs_reg mcs
= wm_key
->multisample_fbo
?
2896 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2898 /* Use either a normal or a CMS texel fetch message depending on whether
2899 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2900 * message just in case the framebuffer uses 16x multisampling, it should
2901 * be equivalent to the normal CMS fetch for lower multisampling modes.
2903 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2904 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2905 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2907 /* Emit the instruction. */
2908 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
2909 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
2910 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
2911 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
2912 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
2913 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
2914 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
2915 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
2916 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
2918 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
2919 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2925 * Actual coherent framebuffer read implemented using the native render target
2926 * read message. Requires SKL+.
2929 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
2931 assert(bld
.shader
->devinfo
->gen
>= 9);
2932 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
2933 inst
->target
= target
;
2934 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2940 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
2942 if (n
&& regs
[0].file
!= BAD_FILE
) {
2946 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
2948 for (unsigned i
= 0; i
< n
; i
++)
2956 alloc_frag_output(fs_visitor
*v
, unsigned location
)
2958 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
2959 const brw_wm_prog_key
*const key
=
2960 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
2961 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
2962 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
2964 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
2965 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
2967 else if (l
== FRAG_RESULT_COLOR
)
2968 return alloc_temporary(v
->bld
, 4, v
->outputs
,
2969 MAX2(key
->nr_color_regions
, 1));
2971 else if (l
== FRAG_RESULT_DEPTH
)
2972 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
2974 else if (l
== FRAG_RESULT_STENCIL
)
2975 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
2977 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
2978 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
2980 else if (l
>= FRAG_RESULT_DATA0
&&
2981 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
2982 return alloc_temporary(v
->bld
, 4,
2983 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
2986 unreachable("Invalid location");
2990 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2991 nir_intrinsic_instr
*instr
)
2993 assert(stage
== MESA_SHADER_FRAGMENT
);
2996 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2997 dest
= get_nir_dest(instr
->dest
);
2999 switch (instr
->intrinsic
) {
3000 case nir_intrinsic_load_front_face
:
3001 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3002 *emit_frontfacing_interpolation());
3005 case nir_intrinsic_load_sample_pos
: {
3006 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3007 assert(sample_pos
.file
!= BAD_FILE
);
3008 dest
.type
= sample_pos
.type
;
3009 bld
.MOV(dest
, sample_pos
);
3010 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3014 case nir_intrinsic_load_layer_id
:
3015 dest
.type
= BRW_REGISTER_TYPE_UD
;
3016 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3019 case nir_intrinsic_load_helper_invocation
:
3020 case nir_intrinsic_load_sample_mask_in
:
3021 case nir_intrinsic_load_sample_id
: {
3022 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3023 fs_reg val
= nir_system_values
[sv
];
3024 assert(val
.file
!= BAD_FILE
);
3025 dest
.type
= val
.type
;
3030 case nir_intrinsic_store_output
: {
3031 const fs_reg src
= get_nir_src(instr
->src
[0]);
3032 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3033 const unsigned location
= nir_intrinsic_base(instr
) +
3034 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3035 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3038 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3039 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3040 offset(src
, bld
, j
));
3045 case nir_intrinsic_load_output
: {
3046 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3047 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3048 assert(l
>= FRAG_RESULT_DATA0
);
3049 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3050 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3051 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3053 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3054 emit_coherent_fb_read(bld
, tmp
, target
);
3056 emit_non_coherent_fb_read(bld
, tmp
, target
);
3058 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3059 bld
.MOV(offset(dest
, bld
, j
),
3060 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3066 case nir_intrinsic_discard
:
3067 case nir_intrinsic_discard_if
: {
3068 /* We track our discarded pixels in f0.1. By predicating on it, we can
3069 * update just the flag bits that aren't yet discarded. If there's no
3070 * condition, we emit a CMP of g0 != g0, so all currently executing
3071 * channels will get turned off.
3074 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3075 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3076 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3078 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3079 BRW_REGISTER_TYPE_UW
));
3080 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3082 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3083 cmp
->flag_subreg
= 1;
3085 if (devinfo
->gen
>= 6) {
3086 emit_discard_jump();
3089 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3093 case nir_intrinsic_load_input
: {
3094 /* load_input is only used for flat inputs */
3095 unsigned base
= nir_intrinsic_base(instr
);
3096 unsigned comp
= nir_intrinsic_component(instr
);
3097 unsigned num_components
= instr
->num_components
;
3098 fs_reg orig_dest
= dest
;
3099 enum brw_reg_type type
= dest
.type
;
3101 /* Special case fields in the VUE header */
3102 if (base
== VARYING_SLOT_LAYER
)
3104 else if (base
== VARYING_SLOT_VIEWPORT
)
3107 if (nir_dest_bit_size(instr
->dest
) == 64) {
3108 /* const_index is in 32-bit type size units that could not be aligned
3109 * with DF. We need to read the double vector as if it was a float
3110 * vector of twice the number of components to fetch the right data.
3112 type
= BRW_REGISTER_TYPE_F
;
3113 num_components
*= 2;
3114 dest
= bld
.vgrf(type
, num_components
);
3117 for (unsigned int i
= 0; i
< num_components
; i
++) {
3118 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3119 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3122 if (nir_dest_bit_size(instr
->dest
) == 64) {
3123 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3124 instr
->num_components
);
3129 case nir_intrinsic_load_barycentric_pixel
:
3130 case nir_intrinsic_load_barycentric_centroid
:
3131 case nir_intrinsic_load_barycentric_sample
:
3132 /* Do nothing - load_interpolated_input handling will handle it later. */
3135 case nir_intrinsic_load_barycentric_at_sample
: {
3136 const glsl_interp_mode interpolation
=
3137 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3139 if (nir_src_is_const(instr
->src
[0])) {
3140 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3142 emit_pixel_interpolater_send(bld
,
3143 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3146 brw_imm_ud(msg_data
),
3149 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3150 BRW_REGISTER_TYPE_UD
);
3152 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3153 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3154 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3155 bld
.exec_all().group(1, 0)
3156 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3157 emit_pixel_interpolater_send(bld
,
3158 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3164 /* Make a loop that sends a message to the pixel interpolater
3165 * for the sample number in each live channel. If there are
3166 * multiple channels with the same sample number then these
3167 * will be handled simultaneously with a single interation of
3170 bld
.emit(BRW_OPCODE_DO
);
3172 /* Get the next live sample number into sample_id_reg */
3173 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3175 /* Set the flag register so that we can perform the send
3176 * message on all channels that have the same sample number
3178 bld
.CMP(bld
.null_reg_ud(),
3179 sample_src
, sample_id
,
3180 BRW_CONDITIONAL_EQ
);
3181 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3182 bld
.exec_all().group(1, 0)
3183 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3185 emit_pixel_interpolater_send(bld
,
3186 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3189 component(msg_data
, 0),
3191 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3193 /* Continue the loop if there are any live channels left */
3194 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3196 bld
.emit(BRW_OPCODE_WHILE
));
3202 case nir_intrinsic_load_barycentric_at_offset
: {
3203 const glsl_interp_mode interpolation
=
3204 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3206 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3209 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3210 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3211 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3213 emit_pixel_interpolater_send(bld
,
3214 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3217 brw_imm_ud(off_x
| (off_y
<< 4)),
3220 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3221 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3222 BRW_REGISTER_TYPE_F
);
3223 for (int i
= 0; i
< 2; i
++) {
3224 fs_reg temp
= vgrf(glsl_type::float_type
);
3225 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3226 fs_reg itemp
= vgrf(glsl_type::int_type
);
3228 bld
.MOV(itemp
, temp
);
3230 /* Clamp the upper end of the range to +7/16.
3231 * ARB_gpu_shader5 requires that we support a maximum offset
3232 * of +0.5, which isn't representable in a S0.4 value -- if
3233 * we didn't clamp it, we'd end up with -8/16, which is the
3234 * opposite of what the shader author wanted.
3236 * This is legal due to ARB_gpu_shader5's quantization
3239 * "Not all values of <offset> may be supported; x and y
3240 * offsets may be rounded to fixed-point values with the
3241 * number of fraction bits given by the
3242 * implementation-dependent constant
3243 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3245 set_condmod(BRW_CONDITIONAL_L
,
3246 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3249 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3250 emit_pixel_interpolater_send(bld
,
3260 case nir_intrinsic_load_interpolated_input
: {
3261 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3262 emit_fragcoord_interpolation(dest
);
3266 assert(instr
->src
[0].ssa
&&
3267 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3268 nir_intrinsic_instr
*bary_intrinsic
=
3269 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3270 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3271 enum glsl_interp_mode interp_mode
=
3272 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3275 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3276 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3277 /* Use the result of the PI message */
3278 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3280 /* Use the delta_xy values computed from the payload */
3281 enum brw_barycentric_mode bary
=
3282 brw_barycentric_mode(interp_mode
, bary_intrin
);
3284 dst_xy
= this->delta_xy
[bary
];
3287 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3289 component(interp_reg(nir_intrinsic_base(instr
),
3290 nir_intrinsic_component(instr
) + i
), 0);
3291 interp
.type
= BRW_REGISTER_TYPE_F
;
3292 dest
.type
= BRW_REGISTER_TYPE_F
;
3294 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3295 fs_reg tmp
= vgrf(glsl_type::float_type
);
3296 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3297 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3299 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3306 nir_emit_intrinsic(bld
, instr
);
3312 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3314 if (nir_src_is_const(instr
->src
[src
])) {
3315 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3318 else if (add_val
== -1)
3326 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3327 nir_intrinsic_instr
*instr
)
3329 assert(stage
== MESA_SHADER_COMPUTE
);
3330 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3333 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3334 dest
= get_nir_dest(instr
->dest
);
3336 switch (instr
->intrinsic
) {
3337 case nir_intrinsic_barrier
:
3339 cs_prog_data
->uses_barrier
= true;
3342 case nir_intrinsic_load_subgroup_id
:
3343 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3346 case nir_intrinsic_load_local_invocation_id
:
3347 case nir_intrinsic_load_work_group_id
: {
3348 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3349 fs_reg val
= nir_system_values
[sv
];
3350 assert(val
.file
!= BAD_FILE
);
3351 dest
.type
= val
.type
;
3352 for (unsigned i
= 0; i
< 3; i
++)
3353 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3357 case nir_intrinsic_load_num_work_groups
: {
3358 const unsigned surface
=
3359 cs_prog_data
->binding_table
.work_groups_start
;
3361 cs_prog_data
->uses_num_work_groups
= true;
3363 fs_reg surf_index
= brw_imm_ud(surface
);
3365 /* Read the 3 GLuint components of gl_NumWorkGroups */
3366 for (unsigned i
= 0; i
< 3; i
++) {
3367 fs_reg read_result
=
3368 emit_untyped_read(bld
, surf_index
,
3370 1 /* dims */, 1 /* size */,
3371 BRW_PREDICATE_NONE
);
3372 read_result
.type
= dest
.type
;
3373 bld
.MOV(dest
, read_result
);
3374 dest
= offset(dest
, bld
, 1);
3379 case nir_intrinsic_shared_atomic_add
:
3380 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3382 case nir_intrinsic_shared_atomic_imin
:
3383 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3385 case nir_intrinsic_shared_atomic_umin
:
3386 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3388 case nir_intrinsic_shared_atomic_imax
:
3389 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3391 case nir_intrinsic_shared_atomic_umax
:
3392 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3394 case nir_intrinsic_shared_atomic_and
:
3395 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3397 case nir_intrinsic_shared_atomic_or
:
3398 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3400 case nir_intrinsic_shared_atomic_xor
:
3401 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3403 case nir_intrinsic_shared_atomic_exchange
:
3404 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3406 case nir_intrinsic_shared_atomic_comp_swap
:
3407 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3409 case nir_intrinsic_shared_atomic_fmin
:
3410 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3412 case nir_intrinsic_shared_atomic_fmax
:
3413 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3415 case nir_intrinsic_shared_atomic_fcomp_swap
:
3416 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3419 case nir_intrinsic_load_shared
: {
3420 assert(devinfo
->gen
>= 7);
3421 assert(stage
== MESA_SHADER_COMPUTE
);
3423 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3424 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[0]),
3425 BRW_REGISTER_TYPE_UD
);
3427 /* Make dest unsigned because that's what the temporary will be */
3428 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3430 /* Read the vector */
3431 if (nir_intrinsic_align(instr
) >= 4) {
3432 assert(nir_dest_bit_size(instr
->dest
) == 32);
3433 fs_reg read_result
= emit_untyped_read(bld
, brw_imm_ud(GEN7_BTI_SLM
),
3434 offset_reg
, 1 /* dims */,
3435 instr
->num_components
,
3436 BRW_PREDICATE_NONE
);
3437 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
3438 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
3440 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3441 assert(nir_dest_num_components(instr
->dest
) == 1);
3442 fs_reg read_result
=
3443 emit_byte_scattered_read(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
,
3444 1 /* dims */, 1, bit_size
,
3445 BRW_PREDICATE_NONE
);
3446 bld
.MOV(dest
, read_result
);
3451 case nir_intrinsic_store_shared
: {
3452 assert(devinfo
->gen
>= 7);
3453 assert(stage
== MESA_SHADER_COMPUTE
);
3455 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3456 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3457 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[1]),
3458 BRW_REGISTER_TYPE_UD
);
3460 val_reg
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3462 assert(nir_intrinsic_write_mask(instr
) ==
3463 (1u << instr
->num_components
) - 1);
3464 if (nir_intrinsic_align(instr
) >= 4) {
3465 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3466 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3467 emit_untyped_write(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
, val_reg
,
3468 1 /* dims */, instr
->num_components
,
3469 BRW_PREDICATE_NONE
);
3471 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3472 assert(nir_src_num_components(instr
->src
[0]) == 1);
3473 fs_reg write_src
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3474 bld
.MOV(write_src
, val_reg
);
3475 emit_byte_scattered_write(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
,
3476 write_src
, 1 /* dims */, bit_size
,
3477 BRW_PREDICATE_NONE
);
3483 nir_emit_intrinsic(bld
, instr
);
3489 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3490 nir_op op
, brw_reg_type type
)
3492 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3493 switch (type_sz(type
)) {
3495 assert(type
!= BRW_REGISTER_TYPE_HF
);
3496 return retype(brw_imm_uw(value
.u16
[0]), type
);
3498 return retype(brw_imm_ud(value
.u32
[0]), type
);
3500 if (type
== BRW_REGISTER_TYPE_DF
)
3501 return setup_imm_df(bld
, value
.f64
[0]);
3503 return retype(brw_imm_u64(value
.u64
[0]), type
);
3505 unreachable("Invalid type size");
3510 brw_op_for_nir_reduction_op(nir_op op
)
3513 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3514 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3515 case nir_op_imul
: return BRW_OPCODE_MUL
;
3516 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3517 case nir_op_imin
: return BRW_OPCODE_SEL
;
3518 case nir_op_umin
: return BRW_OPCODE_SEL
;
3519 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3520 case nir_op_imax
: return BRW_OPCODE_SEL
;
3521 case nir_op_umax
: return BRW_OPCODE_SEL
;
3522 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3523 case nir_op_iand
: return BRW_OPCODE_AND
;
3524 case nir_op_ior
: return BRW_OPCODE_OR
;
3525 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3527 unreachable("Invalid reduction operation");
3531 static brw_conditional_mod
3532 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3535 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3536 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3537 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3538 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3539 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3540 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3541 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3542 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3543 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3544 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3545 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3546 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3547 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3549 unreachable("Invalid reduction operation");
3554 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3555 nir_intrinsic_instr
*instr
)
3557 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3559 if (stage_prog_data
->binding_table
.image_start
> 0) {
3560 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3561 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3563 bld
.ADD(image
, image
,
3564 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3568 return bld
.emit_uniformize(image
);
3572 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3573 nir_intrinsic_instr
*instr
)
3575 /* SSBO stores are weird in that their index is in src[1] */
3576 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3579 if (nir_src_is_const(instr
->src
[src
])) {
3580 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3581 nir_src_as_uint(instr
->src
[src
]);
3582 surf_index
= brw_imm_ud(index
);
3584 surf_index
= vgrf(glsl_type::uint_type
);
3585 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3586 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3593 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3595 switch (nir_intrinsic_image_dim(instr
)) {
3596 case GLSL_SAMPLER_DIM_1D
:
3597 return 1 + nir_intrinsic_image_array(instr
);
3598 case GLSL_SAMPLER_DIM_2D
:
3599 case GLSL_SAMPLER_DIM_RECT
:
3600 return 2 + nir_intrinsic_image_array(instr
);
3601 case GLSL_SAMPLER_DIM_3D
:
3602 case GLSL_SAMPLER_DIM_CUBE
:
3604 case GLSL_SAMPLER_DIM_BUF
:
3606 case GLSL_SAMPLER_DIM_MS
:
3607 return 2 + nir_intrinsic_image_array(instr
);
3609 unreachable("Invalid image dimension");
3614 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3617 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3618 dest
= get_nir_dest(instr
->dest
);
3620 switch (instr
->intrinsic
) {
3621 case nir_intrinsic_image_load
:
3622 case nir_intrinsic_image_store
:
3623 case nir_intrinsic_image_atomic_add
:
3624 case nir_intrinsic_image_atomic_min
:
3625 case nir_intrinsic_image_atomic_max
:
3626 case nir_intrinsic_image_atomic_and
:
3627 case nir_intrinsic_image_atomic_or
:
3628 case nir_intrinsic_image_atomic_xor
:
3629 case nir_intrinsic_image_atomic_exchange
:
3630 case nir_intrinsic_image_atomic_comp_swap
: {
3631 if (stage
== MESA_SHADER_FRAGMENT
&&
3632 instr
->intrinsic
!= nir_intrinsic_image_load
)
3633 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3635 /* Get some metadata from the image intrinsic. */
3636 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3637 const unsigned dims
= image_intrinsic_coord_components(instr
);
3638 const GLenum format
= nir_intrinsic_format(instr
);
3639 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3641 /* Get the arguments of the image intrinsic. */
3642 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3643 const fs_reg coords
= retype(get_nir_src(instr
->src
[1]),
3644 BRW_REGISTER_TYPE_UD
);
3647 /* Emit an image load, store or atomic op. */
3648 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3649 tmp
= emit_typed_read(bld
, image
, coords
, dims
,
3650 instr
->num_components
);
3651 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3652 const fs_reg src0
= get_nir_src(instr
->src
[3]);
3653 emit_typed_write(bld
, image
, coords
, src0
, dims
,
3654 instr
->num_components
);
3657 unsigned num_srcs
= info
->num_srcs
;
3659 switch (instr
->intrinsic
) {
3660 case nir_intrinsic_image_atomic_add
:
3661 assert(num_srcs
== 4);
3663 op
= get_op_for_atomic_add(instr
, 3);
3665 if (op
!= BRW_AOP_ADD
)
3668 case nir_intrinsic_image_atomic_min
:
3669 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3670 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3672 case nir_intrinsic_image_atomic_max
:
3673 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3674 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3676 case nir_intrinsic_image_atomic_and
:
3679 case nir_intrinsic_image_atomic_or
:
3682 case nir_intrinsic_image_atomic_xor
:
3685 case nir_intrinsic_image_atomic_exchange
:
3688 case nir_intrinsic_image_atomic_comp_swap
:
3692 unreachable("Not reachable.");
3695 const fs_reg src0
= (num_srcs
>= 4 ?
3696 get_nir_src(instr
->src
[3]) : fs_reg());
3697 const fs_reg src1
= (num_srcs
>= 5 ?
3698 get_nir_src(instr
->src
[4]) : fs_reg());
3700 tmp
= emit_typed_atomic(bld
, image
, coords
, src0
, src1
, dims
, 1, op
);
3703 /* Assign the result. */
3704 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3705 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3706 offset(tmp
, bld
, c
));
3711 case nir_intrinsic_image_size
: {
3712 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3713 * into will handle the binding table index for us in the geneerator.
3715 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3716 BRW_REGISTER_TYPE_UD
);
3717 image
= bld
.emit_uniformize(image
);
3719 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3720 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
3721 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
3722 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
3723 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
3725 /* Since the image size is always uniform, we can just emit a SIMD8
3726 * query instruction and splat the result out.
3728 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3730 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3731 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
3732 tmp
, srcs
, ARRAY_SIZE(srcs
));
3733 inst
->size_written
= 4 * REG_SIZE
;
3735 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3736 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3737 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3738 offset(retype(dest
, tmp
.type
), bld
, c
),
3739 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3741 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3742 component(offset(tmp
, ubld
, c
), 0));
3748 case nir_intrinsic_image_load_raw_intel
: {
3749 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3750 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3751 BRW_REGISTER_TYPE_UD
);
3753 fs_reg tmp
= emit_untyped_read(bld
, image
, addr
, 1,
3754 instr
->num_components
);
3756 for (unsigned c
= 0; c
< instr
->num_components
; ++c
) {
3757 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3758 offset(tmp
, bld
, c
));
3763 case nir_intrinsic_image_store_raw_intel
: {
3764 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3765 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3766 BRW_REGISTER_TYPE_UD
);
3767 const fs_reg data
= retype(get_nir_src(instr
->src
[2]),
3768 BRW_REGISTER_TYPE_UD
);
3770 if (stage
== MESA_SHADER_FRAGMENT
)
3771 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3773 emit_untyped_write(bld
, image
, addr
, data
, 1,
3774 instr
->num_components
);
3778 case nir_intrinsic_group_memory_barrier
:
3779 case nir_intrinsic_memory_barrier_shared
:
3780 case nir_intrinsic_memory_barrier_atomic_counter
:
3781 case nir_intrinsic_memory_barrier_buffer
:
3782 case nir_intrinsic_memory_barrier_image
:
3783 case nir_intrinsic_memory_barrier
: {
3784 const fs_builder ubld
= bld
.group(8, 0);
3785 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3786 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3787 ->size_written
= 2 * REG_SIZE
;
3791 case nir_intrinsic_shader_clock
: {
3792 /* We cannot do anything if there is an event, so ignore it for now */
3793 const fs_reg shader_clock
= get_timestamp(bld
);
3794 const fs_reg srcs
[] = { component(shader_clock
, 0),
3795 component(shader_clock
, 1) };
3796 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3800 case nir_intrinsic_image_samples
:
3801 /* The driver does not support multi-sampled images. */
3802 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3805 case nir_intrinsic_load_uniform
: {
3806 /* Offsets are in bytes but they should always aligned to
3809 assert(instr
->const_index
[0] % 4 == 0 ||
3810 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3812 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3814 if (nir_src_is_const(instr
->src
[0])) {
3815 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3816 assert(load_offset
% type_sz(dest
.type
) == 0);
3817 /* For 16-bit types we add the module of the const_index[0]
3818 * offset to access to not 32-bit aligned element
3820 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
3822 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3823 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3826 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3827 BRW_REGISTER_TYPE_UD
);
3829 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3830 * go past the end of the uniform. In order to keep the n'th
3831 * component from running past, we subtract off the size of all but
3832 * one component of the vector.
3834 assert(instr
->const_index
[1] >=
3835 instr
->num_components
* (int) type_sz(dest
.type
));
3836 unsigned read_size
= instr
->const_index
[1] -
3837 (instr
->num_components
- 1) * type_sz(dest
.type
);
3839 bool supports_64bit_indirects
=
3840 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3842 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3843 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3844 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3845 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3846 indirect
, brw_imm_ud(read_size
));
3849 const unsigned num_mov_indirects
=
3850 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3851 /* We read a little bit less per MOV INDIRECT, as they are now
3852 * 32-bits ones instead of 64-bit. Fix read_size then.
3854 const unsigned read_size_32bit
= read_size
-
3855 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3856 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3857 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3858 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3859 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3860 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3861 indirect
, brw_imm_ud(read_size_32bit
));
3869 case nir_intrinsic_load_ubo
: {
3871 if (nir_src_is_const(instr
->src
[0])) {
3872 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3873 nir_src_as_uint(instr
->src
[0]);
3874 surf_index
= brw_imm_ud(index
);
3876 /* The block index is not a constant. Evaluate the index expression
3877 * per-channel and add the base UBO index; we have to select a value
3878 * from any live channel.
3880 surf_index
= vgrf(glsl_type::uint_type
);
3881 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3882 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3883 surf_index
= bld
.emit_uniformize(surf_index
);
3886 if (!nir_src_is_const(instr
->src
[1])) {
3887 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3888 BRW_REGISTER_TYPE_UD
);
3890 for (int i
= 0; i
< instr
->num_components
; i
++)
3891 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3892 base_offset
, i
* type_sz(dest
.type
));
3894 /* Even if we are loading doubles, a pull constant load will load
3895 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3896 * need to load a full dvec4 we will have to emit 2 loads. This is
3897 * similar to demote_pull_constants(), except that in that case we
3898 * see individual accesses to each component of the vector and then
3899 * we let CSE deal with duplicate loads. Here we see a vector access
3900 * and we have to split it if necessary.
3902 const unsigned type_size
= type_sz(dest
.type
);
3903 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
3905 /* See if we've selected this as a push constant candidate */
3906 if (nir_src_is_const(instr
->src
[0])) {
3907 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
3908 const unsigned offset_256b
= load_offset
/ 32;
3911 for (int i
= 0; i
< 4; i
++) {
3912 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3913 if (range
->block
== ubo_block
&&
3914 offset_256b
>= range
->start
&&
3915 offset_256b
< range
->start
+ range
->length
) {
3917 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3918 push_reg
.offset
= load_offset
- 32 * range
->start
;
3923 if (push_reg
.file
!= BAD_FILE
) {
3924 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3925 bld
.MOV(offset(dest
, bld
, i
),
3926 byte_offset(push_reg
, i
* type_size
));
3932 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3933 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3934 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3936 for (unsigned c
= 0; c
< instr
->num_components
;) {
3937 const unsigned base
= load_offset
+ c
* type_size
;
3938 /* Number of usable components in the next block-aligned load. */
3939 const unsigned count
= MIN2(instr
->num_components
- c
,
3940 (block_sz
- base
% block_sz
) / type_size
);
3942 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3943 packed_consts
, surf_index
,
3944 brw_imm_ud(base
& ~(block_sz
- 1)));
3946 const fs_reg consts
=
3947 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3950 for (unsigned d
= 0; d
< count
; d
++)
3951 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3959 case nir_intrinsic_load_global
: {
3960 assert(devinfo
->gen
>= 8);
3962 if (nir_intrinsic_align(instr
) >= 4) {
3963 assert(nir_dest_bit_size(instr
->dest
) == 32);
3964 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
3966 get_nir_src(instr
->src
[0]), /* Address */
3967 fs_reg(), /* No source data */
3968 brw_imm_ud(instr
->num_components
));
3969 inst
->size_written
= instr
->num_components
*
3970 inst
->dst
.component_size(inst
->exec_size
);
3972 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3973 assert(bit_size
<= 32);
3974 assert(nir_dest_num_components(instr
->dest
) == 1);
3975 brw_reg_type data_type
=
3976 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3977 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3978 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
3980 get_nir_src(instr
->src
[0]), /* Address */
3981 fs_reg(), /* No source data */
3982 brw_imm_ud(bit_size
));
3983 bld
.MOV(retype(dest
, data_type
), tmp
);
3988 case nir_intrinsic_store_global
:
3989 assert(devinfo
->gen
>= 8);
3991 if (stage
== MESA_SHADER_FRAGMENT
)
3992 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3994 if (nir_intrinsic_align(instr
) >= 4) {
3995 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3996 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
3998 get_nir_src(instr
->src
[1]), /* Address */
3999 get_nir_src(instr
->src
[0]), /* Data */
4000 brw_imm_ud(instr
->num_components
));
4002 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4003 assert(bit_size
<= 32);
4004 assert(nir_src_num_components(instr
->src
[0]) == 1);
4005 brw_reg_type data_type
=
4006 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4007 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4008 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4009 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4011 get_nir_src(instr
->src
[1]), /* Address */
4013 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4017 case nir_intrinsic_global_atomic_add
:
4018 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4020 case nir_intrinsic_global_atomic_imin
:
4021 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4023 case nir_intrinsic_global_atomic_umin
:
4024 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4026 case nir_intrinsic_global_atomic_imax
:
4027 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4029 case nir_intrinsic_global_atomic_umax
:
4030 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4032 case nir_intrinsic_global_atomic_and
:
4033 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4035 case nir_intrinsic_global_atomic_or
:
4036 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4038 case nir_intrinsic_global_atomic_xor
:
4039 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4041 case nir_intrinsic_global_atomic_exchange
:
4042 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4044 case nir_intrinsic_global_atomic_comp_swap
:
4045 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4047 case nir_intrinsic_global_atomic_fmin
:
4048 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4050 case nir_intrinsic_global_atomic_fmax
:
4051 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4053 case nir_intrinsic_global_atomic_fcomp_swap
:
4054 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4057 case nir_intrinsic_load_ssbo
: {
4058 assert(devinfo
->gen
>= 7);
4060 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4061 fs_reg surf_index
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4062 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[1]),
4063 BRW_REGISTER_TYPE_UD
);
4065 /* Make dest unsigned because that's what the temporary will be */
4066 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4068 /* Read the vector */
4069 if (nir_intrinsic_align(instr
) >= 4) {
4070 assert(nir_dest_bit_size(instr
->dest
) == 32);
4071 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
4073 instr
->num_components
,
4074 BRW_PREDICATE_NONE
);
4075 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
4076 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
4078 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4079 assert(nir_dest_num_components(instr
->dest
) == 1);
4080 fs_reg read_result
=
4081 emit_byte_scattered_read(bld
, surf_index
, offset_reg
,
4082 1 /* dims */, 1, bit_size
,
4083 BRW_PREDICATE_NONE
);
4084 bld
.MOV(dest
, read_result
);
4089 case nir_intrinsic_store_ssbo
: {
4090 assert(devinfo
->gen
>= 7);
4092 if (stage
== MESA_SHADER_FRAGMENT
)
4093 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4095 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4096 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4097 fs_reg surf_index
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4098 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[2]),
4099 BRW_REGISTER_TYPE_UD
);
4101 val_reg
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4103 assert(nir_intrinsic_write_mask(instr
) ==
4104 (1u << instr
->num_components
) - 1);
4105 if (nir_intrinsic_align(instr
) >= 4) {
4106 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4107 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4108 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
4109 1 /* dims */, instr
->num_components
,
4110 BRW_PREDICATE_NONE
);
4112 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4113 assert(nir_src_num_components(instr
->src
[0]) == 1);
4114 fs_reg write_src
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4115 bld
.MOV(write_src
, val_reg
);
4116 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4117 write_src
, 1 /* dims */, bit_size
,
4118 BRW_PREDICATE_NONE
);
4123 case nir_intrinsic_store_output
: {
4124 fs_reg src
= get_nir_src(instr
->src
[0]);
4126 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4127 unsigned num_components
= instr
->num_components
;
4128 unsigned first_component
= nir_intrinsic_component(instr
);
4129 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4130 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4131 num_components
*= 2;
4134 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4135 4 * store_offset
), src
.type
);
4136 for (unsigned j
= 0; j
< num_components
; j
++) {
4137 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4138 offset(src
, bld
, j
));
4143 case nir_intrinsic_ssbo_atomic_add
:
4144 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4146 case nir_intrinsic_ssbo_atomic_imin
:
4147 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4149 case nir_intrinsic_ssbo_atomic_umin
:
4150 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4152 case nir_intrinsic_ssbo_atomic_imax
:
4153 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4155 case nir_intrinsic_ssbo_atomic_umax
:
4156 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4158 case nir_intrinsic_ssbo_atomic_and
:
4159 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4161 case nir_intrinsic_ssbo_atomic_or
:
4162 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4164 case nir_intrinsic_ssbo_atomic_xor
:
4165 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4167 case nir_intrinsic_ssbo_atomic_exchange
:
4168 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4170 case nir_intrinsic_ssbo_atomic_comp_swap
:
4171 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4173 case nir_intrinsic_ssbo_atomic_fmin
:
4174 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4176 case nir_intrinsic_ssbo_atomic_fmax
:
4177 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4179 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4180 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4183 case nir_intrinsic_get_buffer_size
: {
4184 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4185 nir_src_as_uint(instr
->src
[0]) : 0;
4187 /* A resinfo's sampler message is used to get the buffer size. The
4188 * SIMD8's writeback message consists of four registers and SIMD16's
4189 * writeback message consists of 8 destination registers (two per each
4190 * component). Because we are only interested on the first channel of
4191 * the first returned component, where resinfo returns the buffer size
4192 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4193 * the dispatch width.
4195 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4196 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4197 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4200 ubld
.MOV(src_payload
, brw_imm_d(0));
4202 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4203 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4204 src_payload
, brw_imm_ud(index
));
4205 inst
->header_size
= 0;
4207 inst
->size_written
= 4 * REG_SIZE
;
4209 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4211 * "Out-of-bounds checking is always performed at a DWord granularity. If
4212 * any part of the DWord is out-of-bounds then the whole DWord is
4213 * considered out-of-bounds."
4215 * This implies that types with size smaller than 4-bytes need to be
4216 * padded if they don't complete the last dword of the buffer. But as we
4217 * need to maintain the original size we need to reverse the padding
4218 * calculation to return the correct size to know the number of elements
4219 * of an unsized array. As we stored in the last two bits of the surface
4220 * size the needed padding for the buffer, we calculate here the
4221 * original buffer_size reversing the surface_size calculation:
4223 * surface_size = isl_align(buffer_size, 4) +
4224 * (isl_align(buffer_size) - buffer_size)
4226 * buffer_size = surface_size & ~3 - surface_size & 3
4229 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4230 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4231 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4233 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4234 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4235 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4237 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4241 case nir_intrinsic_load_subgroup_invocation
:
4242 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4243 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4246 case nir_intrinsic_load_subgroup_eq_mask
:
4247 case nir_intrinsic_load_subgroup_ge_mask
:
4248 case nir_intrinsic_load_subgroup_gt_mask
:
4249 case nir_intrinsic_load_subgroup_le_mask
:
4250 case nir_intrinsic_load_subgroup_lt_mask
:
4251 unreachable("not reached");
4253 case nir_intrinsic_vote_any
: {
4254 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4256 /* The any/all predicates do not consider channel enables. To prevent
4257 * dead channels from affecting the result, we initialize the flag with
4258 * with the identity value for the logical operation.
4260 if (dispatch_width
== 32) {
4261 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4262 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4265 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4267 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4269 /* For some reason, the any/all predicates don't work properly with
4270 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4271 * doesn't read the correct subset of the flag register and you end up
4272 * getting garbage in the second half. Work around this by using a pair
4273 * of 1-wide MOVs and scattering the result.
4275 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4276 ubld
.MOV(res1
, brw_imm_d(0));
4277 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4278 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4279 BRW_PREDICATE_ALIGN1_ANY32H
,
4280 ubld
.MOV(res1
, brw_imm_d(-1)));
4282 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4285 case nir_intrinsic_vote_all
: {
4286 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4288 /* The any/all predicates do not consider channel enables. To prevent
4289 * dead channels from affecting the result, we initialize the flag with
4290 * with the identity value for the logical operation.
4292 if (dispatch_width
== 32) {
4293 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4294 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4295 brw_imm_ud(0xffffffff));
4297 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4299 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4301 /* For some reason, the any/all predicates don't work properly with
4302 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4303 * doesn't read the correct subset of the flag register and you end up
4304 * getting garbage in the second half. Work around this by using a pair
4305 * of 1-wide MOVs and scattering the result.
4307 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4308 ubld
.MOV(res1
, brw_imm_d(0));
4309 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4310 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4311 BRW_PREDICATE_ALIGN1_ALL32H
,
4312 ubld
.MOV(res1
, brw_imm_d(-1)));
4314 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4317 case nir_intrinsic_vote_feq
:
4318 case nir_intrinsic_vote_ieq
: {
4319 fs_reg value
= get_nir_src(instr
->src
[0]);
4320 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4321 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4322 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4325 fs_reg uniformized
= bld
.emit_uniformize(value
);
4326 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4328 /* The any/all predicates do not consider channel enables. To prevent
4329 * dead channels from affecting the result, we initialize the flag with
4330 * with the identity value for the logical operation.
4332 if (dispatch_width
== 32) {
4333 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4334 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4335 brw_imm_ud(0xffffffff));
4337 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4339 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4341 /* For some reason, the any/all predicates don't work properly with
4342 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4343 * doesn't read the correct subset of the flag register and you end up
4344 * getting garbage in the second half. Work around this by using a pair
4345 * of 1-wide MOVs and scattering the result.
4347 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4348 ubld
.MOV(res1
, brw_imm_d(0));
4349 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4350 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4351 BRW_PREDICATE_ALIGN1_ALL32H
,
4352 ubld
.MOV(res1
, brw_imm_d(-1)));
4354 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4358 case nir_intrinsic_ballot
: {
4359 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4360 BRW_REGISTER_TYPE_UD
);
4361 struct brw_reg flag
= brw_flag_reg(0, 0);
4362 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4363 * as f0.0. This is a problem for fragment programs as we currently use
4364 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4365 * programs yet so this isn't a problem. When we do, something will
4368 if (dispatch_width
== 32)
4369 flag
.type
= BRW_REGISTER_TYPE_UD
;
4371 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4372 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4374 if (instr
->dest
.ssa
.bit_size
> 32) {
4375 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4377 dest
.type
= BRW_REGISTER_TYPE_UD
;
4379 bld
.MOV(dest
, flag
);
4383 case nir_intrinsic_read_invocation
: {
4384 const fs_reg value
= get_nir_src(instr
->src
[0]);
4385 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4386 fs_reg tmp
= bld
.vgrf(value
.type
);
4388 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4389 bld
.emit_uniformize(invocation
));
4391 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4395 case nir_intrinsic_read_first_invocation
: {
4396 const fs_reg value
= get_nir_src(instr
->src
[0]);
4397 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4401 case nir_intrinsic_shuffle
: {
4402 const fs_reg value
= get_nir_src(instr
->src
[0]);
4403 const fs_reg index
= get_nir_src(instr
->src
[1]);
4405 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4409 case nir_intrinsic_first_invocation
: {
4410 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4411 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4412 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4413 fs_reg(component(tmp
, 0)));
4417 case nir_intrinsic_quad_broadcast
: {
4418 const fs_reg value
= get_nir_src(instr
->src
[0]);
4419 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4421 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4422 value
, brw_imm_ud(index
), brw_imm_ud(4));
4426 case nir_intrinsic_quad_swap_horizontal
: {
4427 const fs_reg value
= get_nir_src(instr
->src
[0]);
4428 const fs_reg tmp
= bld
.vgrf(value
.type
);
4429 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4431 const fs_reg src_left
= horiz_stride(value
, 2);
4432 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4433 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4434 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4436 ubld
.MOV(tmp_left
, src_right
);
4437 ubld
.MOV(tmp_right
, src_left
);
4439 bld
.MOV(retype(dest
, value
.type
), tmp
);
4443 case nir_intrinsic_quad_swap_vertical
: {
4444 const fs_reg value
= get_nir_src(instr
->src
[0]);
4445 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4446 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4447 const fs_reg tmp
= bld
.vgrf(value
.type
);
4448 const fs_builder ubld
= bld
.exec_all();
4449 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4450 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4451 bld
.MOV(retype(dest
, value
.type
), tmp
);
4453 /* For larger data types, we have to either emit dispatch_width many
4454 * MOVs or else fall back to doing indirects.
4456 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4457 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4459 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4464 case nir_intrinsic_quad_swap_diagonal
: {
4465 const fs_reg value
= get_nir_src(instr
->src
[0]);
4466 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4467 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4468 const fs_reg tmp
= bld
.vgrf(value
.type
);
4469 const fs_builder ubld
= bld
.exec_all();
4470 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4471 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4472 bld
.MOV(retype(dest
, value
.type
), tmp
);
4474 /* For larger data types, we have to either emit dispatch_width many
4475 * MOVs or else fall back to doing indirects.
4477 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4478 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4480 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4485 case nir_intrinsic_reduce
: {
4486 fs_reg src
= get_nir_src(instr
->src
[0]);
4487 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4488 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4489 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4490 cluster_size
= dispatch_width
;
4492 /* Figure out the source type */
4493 src
.type
= brw_type_for_nir_type(devinfo
,
4494 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4495 nir_src_bit_size(instr
->src
[0])));
4497 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4498 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4499 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4501 /* Set up a register for all of our scratching around and initialize it
4502 * to reduction operation's identity value.
4504 fs_reg scan
= bld
.vgrf(src
.type
);
4505 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4507 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4509 dest
.type
= src
.type
;
4510 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4511 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4512 * the distance between clusters is at least 2 GRFs. In this case,
4513 * we don't need the weird striding of the CLUSTER_BROADCAST
4514 * instruction and can just do regular MOVs.
4516 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4517 const unsigned groups
=
4518 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4519 const unsigned group_size
= dispatch_width
/ groups
;
4520 for (unsigned i
= 0; i
< groups
; i
++) {
4521 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4522 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4523 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4524 component(scan
, comp
));
4527 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4528 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4533 case nir_intrinsic_inclusive_scan
:
4534 case nir_intrinsic_exclusive_scan
: {
4535 fs_reg src
= get_nir_src(instr
->src
[0]);
4536 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4538 /* Figure out the source type */
4539 src
.type
= brw_type_for_nir_type(devinfo
,
4540 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4541 nir_src_bit_size(instr
->src
[0])));
4543 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4544 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4545 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4547 /* Set up a register for all of our scratching around and initialize it
4548 * to reduction operation's identity value.
4550 fs_reg scan
= bld
.vgrf(src
.type
);
4551 const fs_builder allbld
= bld
.exec_all();
4552 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4554 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4555 /* Exclusive scan is a bit harder because we have to do an annoying
4556 * shift of the contents before we can begin. To make things worse,
4557 * we can't do this with a normal stride; we have to use indirects.
4559 fs_reg shifted
= bld
.vgrf(src
.type
);
4560 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4561 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4563 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4564 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4568 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4570 bld
.MOV(retype(dest
, src
.type
), scan
);
4574 case nir_intrinsic_begin_invocation_interlock
: {
4575 const fs_builder ubld
= bld
.group(8, 0);
4576 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4578 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4584 case nir_intrinsic_end_invocation_interlock
: {
4585 /* We don't need to do anything here */
4590 unreachable("unknown intrinsic");
4595 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4596 int op
, nir_intrinsic_instr
*instr
)
4598 if (stage
== MESA_SHADER_FRAGMENT
)
4599 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4602 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4603 dest
= get_nir_dest(instr
->dest
);
4605 fs_reg surface
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4606 fs_reg offset
= get_nir_src(instr
->src
[1]);
4608 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4609 data1
= get_nir_src(instr
->src
[2]);
4611 if (op
== BRW_AOP_CMPWR
)
4612 data2
= get_nir_src(instr
->src
[3]);
4614 /* Emit the actual atomic operation */
4616 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4618 1 /* dims */, 1 /* rsize */,
4620 BRW_PREDICATE_NONE
);
4621 dest
.type
= atomic_result
.type
;
4622 bld
.MOV(dest
, atomic_result
);
4626 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4627 int op
, nir_intrinsic_instr
*instr
)
4629 if (stage
== MESA_SHADER_FRAGMENT
)
4630 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4633 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4634 dest
= get_nir_dest(instr
->dest
);
4636 fs_reg surface
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4637 fs_reg offset
= get_nir_src(instr
->src
[1]);
4638 fs_reg data1
= get_nir_src(instr
->src
[2]);
4640 if (op
== BRW_AOP_FCMPWR
)
4641 data2
= get_nir_src(instr
->src
[3]);
4643 /* Emit the actual atomic operation */
4645 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4647 1 /* dims */, 1 /* rsize */,
4649 BRW_PREDICATE_NONE
);
4650 dest
.type
= atomic_result
.type
;
4651 bld
.MOV(dest
, atomic_result
);
4655 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4656 int op
, nir_intrinsic_instr
*instr
)
4659 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4660 dest
= get_nir_dest(instr
->dest
);
4662 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4665 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4666 data1
= get_nir_src(instr
->src
[1]);
4668 if (op
== BRW_AOP_CMPWR
)
4669 data2
= get_nir_src(instr
->src
[2]);
4671 /* Get the offset */
4672 if (nir_src_is_const(instr
->src
[0])) {
4673 offset
= brw_imm_ud(instr
->const_index
[0] +
4674 nir_src_as_uint(instr
->src
[0]));
4676 offset
= vgrf(glsl_type::uint_type
);
4678 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4679 brw_imm_ud(instr
->const_index
[0]));
4682 /* Emit the actual atomic operation operation */
4684 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4686 1 /* dims */, 1 /* rsize */,
4688 BRW_PREDICATE_NONE
);
4689 dest
.type
= atomic_result
.type
;
4690 bld
.MOV(dest
, atomic_result
);
4694 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4695 int op
, nir_intrinsic_instr
*instr
)
4698 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4699 dest
= get_nir_dest(instr
->dest
);
4701 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4703 fs_reg data1
= get_nir_src(instr
->src
[1]);
4705 if (op
== BRW_AOP_FCMPWR
)
4706 data2
= get_nir_src(instr
->src
[2]);
4708 /* Get the offset */
4709 if (nir_src_is_const(instr
->src
[0])) {
4710 offset
= brw_imm_ud(instr
->const_index
[0] +
4711 nir_src_as_uint(instr
->src
[0]));
4713 offset
= vgrf(glsl_type::uint_type
);
4715 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4716 brw_imm_ud(instr
->const_index
[0]));
4719 /* Emit the actual atomic operation operation */
4721 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4723 1 /* dims */, 1 /* rsize */,
4725 BRW_PREDICATE_NONE
);
4726 dest
.type
= atomic_result
.type
;
4727 bld
.MOV(dest
, atomic_result
);
4731 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
4732 int op
, nir_intrinsic_instr
*instr
)
4734 if (stage
== MESA_SHADER_FRAGMENT
)
4735 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4738 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4739 dest
= get_nir_dest(instr
->dest
);
4741 fs_reg addr
= get_nir_src(instr
->src
[0]);
4744 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4745 data
= get_nir_src(instr
->src
[1]);
4747 if (op
== BRW_AOP_CMPWR
) {
4748 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4749 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4750 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4754 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4755 dest
, addr
, data
, brw_imm_ud(op
));
4759 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
4760 int op
, nir_intrinsic_instr
*instr
)
4762 if (stage
== MESA_SHADER_FRAGMENT
)
4763 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4765 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
4766 fs_reg dest
= get_nir_dest(instr
->dest
);
4768 fs_reg addr
= get_nir_src(instr
->src
[0]);
4770 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
4771 fs_reg data
= get_nir_src(instr
->src
[1]);
4773 if (op
== BRW_AOP_FCMPWR
) {
4774 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4775 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4776 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4780 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4781 dest
, addr
, data
, brw_imm_ud(op
));
4785 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4787 unsigned texture
= instr
->texture_index
;
4788 unsigned sampler
= instr
->sampler_index
;
4790 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4792 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4793 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4795 int lod_components
= 0;
4797 /* The hardware requires a LOD for buffer textures */
4798 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4799 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4801 uint32_t header_bits
= 0;
4802 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4803 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4804 switch (instr
->src
[i
].src_type
) {
4805 case nir_tex_src_bias
:
4806 srcs
[TEX_LOGICAL_SRC_LOD
] =
4807 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4809 case nir_tex_src_comparator
:
4810 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4812 case nir_tex_src_coord
:
4813 switch (instr
->op
) {
4815 case nir_texop_txf_ms
:
4816 case nir_texop_txf_ms_mcs
:
4817 case nir_texop_samples_identical
:
4818 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4821 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4825 case nir_tex_src_ddx
:
4826 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4827 lod_components
= nir_tex_instr_src_size(instr
, i
);
4829 case nir_tex_src_ddy
:
4830 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4832 case nir_tex_src_lod
:
4833 switch (instr
->op
) {
4835 srcs
[TEX_LOGICAL_SRC_LOD
] =
4836 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4839 srcs
[TEX_LOGICAL_SRC_LOD
] =
4840 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4843 srcs
[TEX_LOGICAL_SRC_LOD
] =
4844 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4848 case nir_tex_src_min_lod
:
4849 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
4850 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4852 case nir_tex_src_ms_index
:
4853 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4856 case nir_tex_src_offset
: {
4857 nir_const_value
*const_offset
=
4858 nir_src_as_const_value(instr
->src
[i
].src
);
4859 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
4860 unsigned offset_bits
= 0;
4862 brw_texture_offset(const_offset
->i32
,
4863 nir_tex_instr_src_size(instr
, i
),
4865 header_bits
|= offset_bits
;
4867 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4868 retype(src
, BRW_REGISTER_TYPE_D
);
4873 case nir_tex_src_projector
:
4874 unreachable("should be lowered");
4876 case nir_tex_src_texture_offset
: {
4877 /* Emit code to evaluate the actual indexing expression */
4878 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4879 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4880 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4884 case nir_tex_src_sampler_offset
: {
4885 /* Emit code to evaluate the actual indexing expression */
4886 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4887 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4888 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4892 case nir_tex_src_ms_mcs
:
4893 assert(instr
->op
== nir_texop_txf_ms
);
4894 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4897 case nir_tex_src_plane
: {
4898 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
4899 const uint32_t texture_index
=
4900 instr
->texture_index
+
4901 stage_prog_data
->binding_table
.plane_start
[plane
] -
4902 stage_prog_data
->binding_table
.texture_start
;
4904 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4909 unreachable("unknown texture source");
4913 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4914 (instr
->op
== nir_texop_txf_ms
||
4915 instr
->op
== nir_texop_samples_identical
)) {
4916 if (devinfo
->gen
>= 7 &&
4917 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4918 srcs
[TEX_LOGICAL_SRC_MCS
] =
4919 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4920 instr
->coord_components
,
4921 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4923 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4927 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4928 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4931 switch (instr
->op
) {
4933 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4934 SHADER_OPCODE_TXL_LOGICAL
);
4937 opcode
= FS_OPCODE_TXB_LOGICAL
;
4940 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4943 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4946 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4948 case nir_texop_txf_ms
:
4949 if ((key_tex
->msaa_16
& (1 << sampler
)))
4950 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4952 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4954 case nir_texop_txf_ms_mcs
:
4955 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4957 case nir_texop_query_levels
:
4959 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4962 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4965 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4966 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4968 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4970 case nir_texop_texture_samples
:
4971 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4973 case nir_texop_samples_identical
: {
4974 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4976 /* If mcs is an immediate value, it means there is no MCS. In that case
4977 * just return false.
4979 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4980 bld
.MOV(dst
, brw_imm_ud(0u));
4981 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4982 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4983 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4984 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4985 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4987 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4988 BRW_CONDITIONAL_EQ
);
4993 unreachable("unknown texture opcode");
4996 if (instr
->op
== nir_texop_tg4
) {
4997 if (instr
->component
== 1 &&
4998 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4999 /* gather4 sampler is broken for green channel on RG32F --
5000 * we must ask for blue instead.
5002 header_bits
|= 2 << 16;
5004 header_bits
|= instr
->component
<< 16;
5008 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5009 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5010 inst
->offset
= header_bits
;
5012 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5013 if (devinfo
->gen
>= 9 &&
5014 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5015 unsigned write_mask
= instr
->dest
.is_ssa
?
5016 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5017 (1 << dest_size
) - 1;
5018 assert(write_mask
!= 0); /* dead code should have been eliminated */
5019 inst
->size_written
= util_last_bit(write_mask
) *
5020 inst
->dst
.component_size(inst
->exec_size
);
5022 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5025 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5026 inst
->shadow_compare
= true;
5028 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5029 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5032 for (unsigned i
= 0; i
< dest_size
; i
++)
5033 nir_dest
[i
] = offset(dst
, bld
, i
);
5035 if (instr
->op
== nir_texop_query_levels
) {
5036 /* # levels is in .w */
5037 nir_dest
[0] = offset(dst
, bld
, 3);
5038 } else if (instr
->op
== nir_texop_txs
&&
5039 dest_size
>= 3 && devinfo
->gen
< 7) {
5040 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5041 fs_reg depth
= offset(dst
, bld
, 2);
5042 nir_dest
[2] = vgrf(glsl_type::int_type
);
5043 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5046 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5050 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5052 switch (instr
->type
) {
5053 case nir_jump_break
:
5054 bld
.emit(BRW_OPCODE_BREAK
);
5056 case nir_jump_continue
:
5057 bld
.emit(BRW_OPCODE_CONTINUE
);
5059 case nir_jump_return
:
5061 unreachable("unknown jump");
5066 * This helper takes a source register and un/shuffles it into the destination
5069 * If source type size is smaller than destination type size the operation
5070 * needed is a component shuffle. The opposite case would be an unshuffle. If
5071 * source/destination type size is equal a shuffle is done that would be
5072 * equivalent to a simple MOV.
5074 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5075 * components .xyz 16-bit vector on SIMD8 would be.
5077 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5078 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5080 * This helper will return the following 2 32-bit components with the 16-bit
5083 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5084 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5086 * For unshuffle, the example would be the opposite, a 64-bit type source
5087 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5090 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5091 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5092 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5093 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5095 * The returned result would be the following 4 32-bit components unshuffled:
5097 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5098 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5099 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5100 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5102 * - Source and destination register must not be overlapped.
5103 * - components units are measured in terms of the smaller type between
5104 * source and destination because we are un/shuffling the smaller
5105 * components from/into the bigger ones.
5106 * - first_component parameter allows skipping source components.
5109 shuffle_src_to_dst(const fs_builder
&bld
,
5112 uint32_t first_component
,
5113 uint32_t components
)
5115 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5116 assert(!regions_overlap(dst
,
5117 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5118 offset(src
, bld
, first_component
),
5119 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5120 for (unsigned i
= 0; i
< components
; i
++) {
5121 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5122 offset(src
, bld
, i
+ first_component
));
5124 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5125 /* Source is shuffled into destination */
5126 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5127 assert(!regions_overlap(dst
,
5128 type_sz(dst
.type
) * bld
.dispatch_width() *
5129 DIV_ROUND_UP(components
, size_ratio
),
5130 offset(src
, bld
, first_component
),
5131 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5133 brw_reg_type shuffle_type
=
5134 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5135 BRW_REGISTER_TYPE_D
);
5136 for (unsigned i
= 0; i
< components
; i
++) {
5137 fs_reg shuffle_component_i
=
5138 subscript(offset(dst
, bld
, i
/ size_ratio
),
5139 shuffle_type
, i
% size_ratio
);
5140 bld
.MOV(shuffle_component_i
,
5141 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5144 /* Source is unshuffled into destination */
5145 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5146 assert(!regions_overlap(dst
,
5147 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5148 offset(src
, bld
, first_component
/ size_ratio
),
5149 type_sz(src
.type
) * bld
.dispatch_width() *
5150 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5153 brw_reg_type shuffle_type
=
5154 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5155 BRW_REGISTER_TYPE_D
);
5156 for (unsigned i
= 0; i
< components
; i
++) {
5157 fs_reg shuffle_component_i
=
5158 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5159 shuffle_type
, (first_component
+ i
) % size_ratio
);
5160 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5161 shuffle_component_i
);
5167 shuffle_from_32bit_read(const fs_builder
&bld
,
5170 uint32_t first_component
,
5171 uint32_t components
)
5173 assert(type_sz(src
.type
) == 4);
5175 /* This function takes components in units of the destination type while
5176 * shuffle_src_to_dst takes components in units of the smallest type
5178 if (type_sz(dst
.type
) > 4) {
5179 assert(type_sz(dst
.type
) == 8);
5180 first_component
*= 2;
5184 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5188 shuffle_for_32bit_write(const fs_builder
&bld
,
5190 uint32_t first_component
,
5191 uint32_t components
)
5193 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5194 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5195 /* This function takes components in units of the source type while
5196 * shuffle_src_to_dst takes components in units of the smallest type
5198 if (type_sz(src
.type
) > 4) {
5199 assert(type_sz(src
.type
) == 8);
5200 first_component
*= 2;
5204 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5210 setup_imm_df(const fs_builder
&bld
, double v
)
5212 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5213 assert(devinfo
->gen
>= 7);
5215 if (devinfo
->gen
>= 8)
5216 return brw_imm_df(v
);
5218 /* gen7.5 does not support DF immediates straighforward but the DIM
5219 * instruction allows to set the 64-bit immediate value.
5221 if (devinfo
->is_haswell
) {
5222 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5223 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5224 ubld
.DIM(dst
, brw_imm_df(v
));
5225 return component(dst
, 0);
5228 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5229 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5230 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5232 * Alternatively, we could also produce a normal VGRF (without stride 0)
5233 * by writing to all the channels in the VGRF, however, that would hit the
5234 * gen7 bug where we have to split writes that span more than 1 register
5235 * into instructions with a width of 4 (otherwise the write to the second
5236 * register written runs into an execmask hardware bug) which isn't very
5249 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5250 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5251 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5252 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5254 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5258 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5260 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5261 bld
.MOV(tmp
, brw_imm_w(v
));
5266 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5268 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5269 bld
.MOV(tmp
, brw_imm_uw(v
));