2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
) {
104 /* Add a uniform for the thread local id. It must be the last uniform
107 assert(uniforms
== prog_data
->nr_params
);
108 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
109 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
110 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
115 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
119 nir_foreach_instr(instr
, block
) {
120 if (instr
->type
!= nir_instr_type_intrinsic
)
123 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
124 switch (intrin
->intrinsic
) {
125 case nir_intrinsic_load_vertex_id
:
126 case nir_intrinsic_load_base_vertex
:
127 unreachable("should be lowered by nir_lower_system_values().");
129 case nir_intrinsic_load_vertex_id_zero_base
:
130 case nir_intrinsic_load_is_indexed_draw
:
131 case nir_intrinsic_load_first_vertex
:
132 case nir_intrinsic_load_instance_id
:
133 case nir_intrinsic_load_base_instance
:
134 case nir_intrinsic_load_draw_id
:
135 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
137 case nir_intrinsic_load_invocation_id
:
138 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
140 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
141 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
142 if (reg
->file
== BAD_FILE
) {
143 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
144 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
145 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
146 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
151 case nir_intrinsic_load_sample_pos
:
152 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
153 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
154 if (reg
->file
== BAD_FILE
)
155 *reg
= *v
->emit_samplepos_setup();
158 case nir_intrinsic_load_sample_id
:
159 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
160 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
161 if (reg
->file
== BAD_FILE
)
162 *reg
= *v
->emit_sampleid_setup();
165 case nir_intrinsic_load_sample_mask_in
:
166 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
167 assert(v
->devinfo
->gen
>= 7);
168 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
169 if (reg
->file
== BAD_FILE
)
170 *reg
= *v
->emit_samplemaskin_setup();
173 case nir_intrinsic_load_work_group_id
:
174 assert(v
->stage
== MESA_SHADER_COMPUTE
);
175 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
176 if (reg
->file
== BAD_FILE
)
177 *reg
= *v
->emit_cs_work_group_id_setup();
180 case nir_intrinsic_load_helper_invocation
:
181 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
182 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
183 if (reg
->file
== BAD_FILE
) {
184 const fs_builder abld
=
185 v
->bld
.annotate("gl_HelperInvocation", NULL
);
187 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
188 * pixel mask is in g1.7 of the thread payload.
190 * We move the per-channel pixel enable bit to the low bit of each
191 * channel by shifting the byte containing the pixel mask by the
192 * vector immediate 0x76543210UV.
194 * The region of <1,8,0> reads only 1 byte (the pixel masks for
195 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
196 * masks for 2 and 3) in SIMD16.
198 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
200 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
201 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
202 hbld
.SHR(offset(shifted
, hbld
, i
),
203 stride(retype(brw_vec1_grf(1 + i
, 7),
204 BRW_REGISTER_TYPE_UB
),
206 brw_imm_v(0x76543210));
209 /* A set bit in the pixel mask means the channel is enabled, but
210 * that is the opposite of gl_HelperInvocation so we need to invert
213 * The negate source-modifier bit of logical instructions on Gen8+
214 * performs 1's complement negation, so we can use that instead of
217 fs_reg inverted
= negate(shifted
);
218 if (v
->devinfo
->gen
< 8) {
219 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
220 abld
.NOT(inverted
, shifted
);
223 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
224 * with 1 and negating.
226 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
227 abld
.AND(anded
, inverted
, brw_imm_uw(1));
229 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
230 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
244 fs_visitor::nir_emit_system_values()
246 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
247 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
248 nir_system_values
[i
] = fs_reg();
251 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
252 * never end up using it.
255 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
256 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
257 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
259 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
260 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
261 if (dispatch_width
> 8)
262 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
263 if (dispatch_width
> 16) {
264 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
265 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
269 nir_foreach_function(function
, nir
) {
270 assert(strcmp(function
->name
, "main") == 0);
271 assert(function
->impl
);
272 nir_foreach_block(block
, function
->impl
) {
273 emit_system_values_block(block
, this);
279 * Returns a type based on a reference_type (word, float, half-float) and a
282 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
284 * @FIXME: 64-bit return types are always DF on integer types to maintain
285 * compability with uses of DF previously to the introduction of int64
289 brw_reg_type_from_bit_size(const unsigned bit_size
,
290 const brw_reg_type reference_type
)
292 switch(reference_type
) {
293 case BRW_REGISTER_TYPE_HF
:
294 case BRW_REGISTER_TYPE_F
:
295 case BRW_REGISTER_TYPE_DF
:
298 return BRW_REGISTER_TYPE_HF
;
300 return BRW_REGISTER_TYPE_F
;
302 return BRW_REGISTER_TYPE_DF
;
304 unreachable("Invalid bit size");
306 case BRW_REGISTER_TYPE_B
:
307 case BRW_REGISTER_TYPE_W
:
308 case BRW_REGISTER_TYPE_D
:
309 case BRW_REGISTER_TYPE_Q
:
312 return BRW_REGISTER_TYPE_B
;
314 return BRW_REGISTER_TYPE_W
;
316 return BRW_REGISTER_TYPE_D
;
318 return BRW_REGISTER_TYPE_Q
;
320 unreachable("Invalid bit size");
322 case BRW_REGISTER_TYPE_UB
:
323 case BRW_REGISTER_TYPE_UW
:
324 case BRW_REGISTER_TYPE_UD
:
325 case BRW_REGISTER_TYPE_UQ
:
328 return BRW_REGISTER_TYPE_UB
;
330 return BRW_REGISTER_TYPE_UW
;
332 return BRW_REGISTER_TYPE_UD
;
334 return BRW_REGISTER_TYPE_UQ
;
336 unreachable("Invalid bit size");
339 unreachable("Unknown type");
344 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
346 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
347 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
348 nir_locals
[i
] = fs_reg();
351 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
352 unsigned array_elems
=
353 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
354 unsigned size
= array_elems
* reg
->num_components
;
355 const brw_reg_type reg_type
=
356 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
357 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
360 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
363 nir_emit_cf_list(&impl
->body
);
367 fs_visitor::nir_emit_cf_list(exec_list
*list
)
369 exec_list_validate(list
);
370 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
371 switch (node
->type
) {
373 nir_emit_if(nir_cf_node_as_if(node
));
376 case nir_cf_node_loop
:
377 nir_emit_loop(nir_cf_node_as_loop(node
));
380 case nir_cf_node_block
:
381 nir_emit_block(nir_cf_node_as_block(node
));
385 unreachable("Invalid CFG node block");
391 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
393 /* first, put the condition into f0 */
394 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
395 retype(get_nir_src(if_stmt
->condition
),
396 BRW_REGISTER_TYPE_D
));
397 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
399 bld
.IF(BRW_PREDICATE_NORMAL
);
401 nir_emit_cf_list(&if_stmt
->then_list
);
403 /* note: if the else is empty, dead CF elimination will remove it */
404 bld
.emit(BRW_OPCODE_ELSE
);
406 nir_emit_cf_list(&if_stmt
->else_list
);
408 bld
.emit(BRW_OPCODE_ENDIF
);
410 if (devinfo
->gen
< 7)
411 limit_dispatch_width(16, "Non-uniform control flow unsupported "
416 fs_visitor::nir_emit_loop(nir_loop
*loop
)
418 bld
.emit(BRW_OPCODE_DO
);
420 nir_emit_cf_list(&loop
->body
);
422 bld
.emit(BRW_OPCODE_WHILE
);
424 if (devinfo
->gen
< 7)
425 limit_dispatch_width(16, "Non-uniform control flow unsupported "
430 fs_visitor::nir_emit_block(nir_block
*block
)
432 nir_foreach_instr(instr
, block
) {
433 nir_emit_instr(instr
);
438 fs_visitor::nir_emit_instr(nir_instr
*instr
)
440 const fs_builder abld
= bld
.annotate(NULL
, instr
);
442 switch (instr
->type
) {
443 case nir_instr_type_alu
:
444 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
447 case nir_instr_type_deref
:
448 /* Derefs can exist for images but they do nothing */
451 case nir_instr_type_intrinsic
:
453 case MESA_SHADER_VERTEX
:
454 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_TESS_CTRL
:
457 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_TESS_EVAL
:
460 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case MESA_SHADER_GEOMETRY
:
463 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_FRAGMENT
:
466 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_COMPUTE
:
469 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 unreachable("unsupported shader stage");
476 case nir_instr_type_tex
:
477 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
480 case nir_instr_type_load_const
:
481 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
484 case nir_instr_type_ssa_undef
:
485 /* We create a new VGRF for undefs on every use (by handling
486 * them in get_nir_src()), rather than for each definition.
487 * This helps register coalescing eliminate MOVs from undef.
491 case nir_instr_type_jump
:
492 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
496 unreachable("unknown instruction type");
501 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
505 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
506 const fs_reg
&result
)
508 if (!instr
->src
[0].src
.is_ssa
||
509 !instr
->src
[0].src
.ssa
->parent_instr
)
512 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
515 nir_alu_instr
*src0
=
516 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
518 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
519 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
522 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
523 assert(element
!= NULL
);
525 /* Element type to extract.*/
526 const brw_reg_type type
= brw_int_type(
527 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
528 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
530 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
531 op0
.type
= brw_type_for_nir_type(devinfo
,
532 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
533 nir_src_bit_size(src0
->src
[0].src
)));
534 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
536 set_saturate(instr
->dest
.saturate
,
537 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
542 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
543 const fs_reg
&result
)
545 if (!instr
->src
[0].src
.is_ssa
||
546 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
549 nir_intrinsic_instr
*src0
=
550 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
552 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
555 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
556 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
559 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
560 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
563 fs_reg tmp
= vgrf(glsl_type::int_type
);
565 if (devinfo
->gen
>= 6) {
566 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
567 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
569 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
571 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
572 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
574 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
576 * This negation looks like it's safe in practice, because bits 0:4 will
577 * surely be TRIANGLES
580 if (value1
->f32
[0] == -1.0f
) {
584 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
585 g0
, brw_imm_uw(0x3f80));
587 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
588 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
590 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
592 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
593 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
595 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
597 * This negation looks like it's safe in practice, because bits 0:4 will
598 * surely be TRIANGLES
601 if (value1
->f32
[0] == -1.0f
) {
605 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
607 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
613 emit_find_msb_using_lzd(const fs_builder
&bld
,
614 const fs_reg
&result
,
622 /* LZD of an absolute value source almost always does the right
623 * thing. There are two problem values:
625 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
626 * 0. However, findMSB(int(0x80000000)) == 30.
628 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
629 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
631 * For a value of zero or negative one, -1 will be returned.
633 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
634 * findMSB(-(1<<x)) should return x-1.
636 * For all negative number cases, including 0x80000000 and
637 * 0xffffffff, the correct value is obtained from LZD if instead of
638 * negating the (already negative) value the logical-not is used. A
639 * conditonal logical-not can be achieved in two instructions.
641 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
643 bld
.ASR(temp
, src
, brw_imm_d(31));
644 bld
.XOR(temp
, temp
, src
);
647 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
648 retype(temp
, BRW_REGISTER_TYPE_UD
));
650 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
651 * from the LSB side. Subtract the result from 31 to convert the MSB
652 * count into an LSB count. If no bits are set, LZD will return 32.
653 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
655 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
656 inst
->src
[0].negate
= true;
660 brw_rnd_mode_from_nir_op (const nir_op op
) {
662 case nir_op_f2f16_rtz
:
663 return BRW_RND_MODE_RTZ
;
664 case nir_op_f2f16_rtne
:
665 return BRW_RND_MODE_RTNE
;
667 unreachable("Operation doesn't support rounding mode");
672 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
674 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
677 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
678 result
.type
= brw_type_for_nir_type(devinfo
,
679 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
680 nir_dest_bit_size(instr
->dest
.dest
)));
683 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
684 op
[i
] = get_nir_src(instr
->src
[i
].src
);
685 op
[i
].type
= brw_type_for_nir_type(devinfo
,
686 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
687 nir_src_bit_size(instr
->src
[i
].src
)));
688 op
[i
].abs
= instr
->src
[i
].abs
;
689 op
[i
].negate
= instr
->src
[i
].negate
;
692 /* We get a bunch of mov's out of the from_ssa pass and they may still
693 * be vectorized. We'll handle them as a special-case. We'll also
694 * handle vecN here because it's basically the same thing.
702 fs_reg temp
= result
;
703 bool need_extra_copy
= false;
704 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
705 if (!instr
->src
[i
].src
.is_ssa
&&
706 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
707 need_extra_copy
= true;
708 temp
= bld
.vgrf(result
.type
, 4);
713 for (unsigned i
= 0; i
< 4; i
++) {
714 if (!(instr
->dest
.write_mask
& (1 << i
)))
717 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
718 inst
= bld
.MOV(offset(temp
, bld
, i
),
719 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
721 inst
= bld
.MOV(offset(temp
, bld
, i
),
722 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
724 inst
->saturate
= instr
->dest
.saturate
;
727 /* In this case the source and destination registers were the same,
728 * so we need to insert an extra set of moves in order to deal with
731 if (need_extra_copy
) {
732 for (unsigned i
= 0; i
< 4; i
++) {
733 if (!(instr
->dest
.write_mask
& (1 << i
)))
736 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
745 /* At this point, we have dealt with any instruction that operates on
746 * more than a single channel. Therefore, we can just adjust the source
747 * and destination registers for that channel and emit the instruction.
749 unsigned channel
= 0;
750 if (nir_op_infos
[instr
->op
].output_size
== 0) {
751 /* Since NIR is doing the scalarizing for us, we should only ever see
752 * vectorized operations with a single channel.
754 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
755 channel
= ffs(instr
->dest
.write_mask
) - 1;
757 result
= offset(result
, bld
, channel
);
760 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
761 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
762 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
768 if (optimize_extract_to_float(instr
, result
))
770 inst
= bld
.MOV(result
, op
[0]);
771 inst
->saturate
= instr
->dest
.saturate
;
774 case nir_op_f2f16_rtne
:
775 case nir_op_f2f16_rtz
:
776 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
777 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
780 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
781 * on the HW gen, it is a special hw opcode or just a MOV, and
782 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
784 * But if we want to use that opcode, we need to provide support on
785 * different optimizations and lowerings. As right now HF support is
786 * only for gen8+, it will be better to use directly the MOV, and use
787 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
791 inst
= bld
.MOV(result
, op
[0]);
792 inst
->saturate
= instr
->dest
.saturate
;
802 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
804 * "When source or destination is 64b (...), regioning in Align1
805 * must follow these rules:
807 * 1. Source and destination horizontal stride must be aligned to
811 * This means that conversions from bit-sizes smaller than 64-bit to
812 * 64-bit need to have the source data elements aligned to 64-bit.
813 * This restriction does not apply to BDW and later.
815 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
816 nir_src_bit_size(instr
->src
[0].src
) < 64 &&
817 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
818 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
819 tmp
= subscript(tmp
, op
[0].type
, 0);
820 inst
= bld
.MOV(tmp
, op
[0]);
821 inst
= bld
.MOV(result
, tmp
);
822 inst
->saturate
= instr
->dest
.saturate
;
839 inst
= bld
.MOV(result
, op
[0]);
840 inst
->saturate
= instr
->dest
.saturate
;
845 /* Straightforward since the source can be assumed to be either
846 * strictly >= 0 or strictly <= 0 depending on the setting of the
849 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
851 inst
= (op
[0].negate
)
852 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
853 : bld
.MOV(result
, brw_imm_f(1.0f
));
855 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
857 if (instr
->dest
.saturate
)
858 inst
->saturate
= true;
860 } else if (type_sz(op
[0].type
) < 8) {
861 /* AND(val, 0x80000000) gives the sign bit.
863 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
866 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
868 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
869 op
[0].type
= BRW_REGISTER_TYPE_UD
;
870 result
.type
= BRW_REGISTER_TYPE_UD
;
871 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
873 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
874 inst
->predicate
= BRW_PREDICATE_NORMAL
;
875 if (instr
->dest
.saturate
) {
876 inst
= bld
.MOV(result
, result
);
877 inst
->saturate
= true;
880 /* For doubles we do the same but we need to consider:
882 * - 2-src instructions can't operate with 64-bit immediates
883 * - The sign is encoded in the high 32-bit of each DF
884 * - We need to produce a DF result.
887 fs_reg zero
= vgrf(glsl_type::double_type
);
888 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
889 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
891 bld
.MOV(result
, zero
);
893 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
894 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
895 brw_imm_ud(0x80000000u
));
897 set_predicate(BRW_PREDICATE_NORMAL
,
898 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
900 if (instr
->dest
.saturate
) {
901 inst
= bld
.MOV(result
, result
);
902 inst
->saturate
= true;
909 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
910 * -> non-negative val generates 0x00000000.
911 * Predicated OR sets 1 if val is positive.
913 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
914 assert(bit_size
== 32 || bit_size
== 16);
916 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
917 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
918 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
920 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
921 bld
.ASR(result
, op
[0], shift
);
922 inst
= bld
.OR(result
, result
, one
);
923 inst
->predicate
= BRW_PREDICATE_NORMAL
;
928 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
929 inst
->saturate
= instr
->dest
.saturate
;
933 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
934 inst
->saturate
= instr
->dest
.saturate
;
938 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
939 inst
->saturate
= instr
->dest
.saturate
;
943 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
944 inst
->saturate
= instr
->dest
.saturate
;
948 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
949 inst
->saturate
= instr
->dest
.saturate
;
953 if (fs_key
->high_quality_derivatives
) {
954 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
956 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
958 inst
->saturate
= instr
->dest
.saturate
;
960 case nir_op_fddx_fine
:
961 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
962 inst
->saturate
= instr
->dest
.saturate
;
964 case nir_op_fddx_coarse
:
965 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
966 inst
->saturate
= instr
->dest
.saturate
;
969 if (fs_key
->high_quality_derivatives
) {
970 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
972 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
974 inst
->saturate
= instr
->dest
.saturate
;
976 case nir_op_fddy_fine
:
977 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
978 inst
->saturate
= instr
->dest
.saturate
;
980 case nir_op_fddy_coarse
:
981 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
982 inst
->saturate
= instr
->dest
.saturate
;
987 inst
= bld
.ADD(result
, op
[0], op
[1]);
988 inst
->saturate
= instr
->dest
.saturate
;
992 inst
= bld
.MUL(result
, op
[0], op
[1]);
993 inst
->saturate
= instr
->dest
.saturate
;
997 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
998 bld
.MUL(result
, op
[0], op
[1]);
1001 case nir_op_imul_high
:
1002 case nir_op_umul_high
:
1003 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1004 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1009 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1010 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1013 case nir_op_uadd_carry
:
1014 unreachable("Should have been lowered by carry_to_arith().");
1016 case nir_op_usub_borrow
:
1017 unreachable("Should have been lowered by borrow_to_arith().");
1021 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1022 * appears that our hardware just does the right thing for signed
1025 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1026 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1030 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1031 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1033 /* Math instructions don't support conditional mod */
1034 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1035 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1037 /* Now, we need to determine if signs of the sources are different.
1038 * When we XOR the sources, the top bit is 0 if they are the same and 1
1039 * if they are different. We can then use a conditional modifier to
1040 * turn that into a predicate. This leads us to an XOR.l instruction.
1042 * Technically, according to the PRM, you're not allowed to use .l on a
1043 * XOR instruction. However, emperical experiments and Curro's reading
1044 * of the simulator source both indicate that it's safe.
1046 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1047 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1048 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1049 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1051 /* If the result of the initial remainder operation is non-zero and the
1052 * two sources have different signs, add in a copy of op[1] to get the
1053 * final integer modulus value.
1055 inst
= bld
.ADD(result
, result
, op
[1]);
1056 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1064 fs_reg dest
= result
;
1066 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1068 dest
= bld
.vgrf(op
[0].type
, 1);
1070 brw_conditional_mod cond
;
1071 switch (instr
->op
) {
1073 cond
= BRW_CONDITIONAL_L
;
1076 cond
= BRW_CONDITIONAL_GE
;
1079 cond
= BRW_CONDITIONAL_Z
;
1082 cond
= BRW_CONDITIONAL_NZ
;
1085 unreachable("bad opcode");
1088 bld
.CMP(dest
, op
[0], op
[1], cond
);
1090 if (bit_size
> 32) {
1091 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1092 } else if(bit_size
< 32) {
1093 /* When we convert the result to 32-bit we need to be careful and do
1094 * it as a signed conversion to get sign extension (for 32-bit true)
1096 const brw_reg_type src_type
=
1097 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1099 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1110 fs_reg dest
= result
;
1112 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1114 dest
= bld
.vgrf(op
[0].type
, 1);
1116 brw_conditional_mod cond
;
1117 switch (instr
->op
) {
1120 cond
= BRW_CONDITIONAL_L
;
1124 cond
= BRW_CONDITIONAL_GE
;
1127 cond
= BRW_CONDITIONAL_Z
;
1130 cond
= BRW_CONDITIONAL_NZ
;
1133 unreachable("bad opcode");
1135 bld
.CMP(dest
, op
[0], op
[1], cond
);
1137 if (bit_size
> 32) {
1138 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1139 } else if (bit_size
< 32) {
1140 /* When we convert the result to 32-bit we need to be careful and do
1141 * it as a signed conversion to get sign extension (for 32-bit true)
1143 const brw_reg_type src_type
=
1144 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1146 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1152 if (devinfo
->gen
>= 8) {
1153 op
[0] = resolve_source_modifiers(op
[0]);
1155 bld
.NOT(result
, op
[0]);
1158 if (devinfo
->gen
>= 8) {
1159 op
[0] = resolve_source_modifiers(op
[0]);
1160 op
[1] = resolve_source_modifiers(op
[1]);
1162 bld
.XOR(result
, op
[0], op
[1]);
1165 if (devinfo
->gen
>= 8) {
1166 op
[0] = resolve_source_modifiers(op
[0]);
1167 op
[1] = resolve_source_modifiers(op
[1]);
1169 bld
.OR(result
, op
[0], op
[1]);
1172 if (devinfo
->gen
>= 8) {
1173 op
[0] = resolve_source_modifiers(op
[0]);
1174 op
[1] = resolve_source_modifiers(op
[1]);
1176 bld
.AND(result
, op
[0], op
[1]);
1182 case nir_op_ball_fequal2
:
1183 case nir_op_ball_iequal2
:
1184 case nir_op_ball_fequal3
:
1185 case nir_op_ball_iequal3
:
1186 case nir_op_ball_fequal4
:
1187 case nir_op_ball_iequal4
:
1188 case nir_op_bany_fnequal2
:
1189 case nir_op_bany_inequal2
:
1190 case nir_op_bany_fnequal3
:
1191 case nir_op_bany_inequal3
:
1192 case nir_op_bany_fnequal4
:
1193 case nir_op_bany_inequal4
:
1194 unreachable("Lowered by nir_lower_alu_reductions");
1196 case nir_op_fnoise1_1
:
1197 case nir_op_fnoise1_2
:
1198 case nir_op_fnoise1_3
:
1199 case nir_op_fnoise1_4
:
1200 case nir_op_fnoise2_1
:
1201 case nir_op_fnoise2_2
:
1202 case nir_op_fnoise2_3
:
1203 case nir_op_fnoise2_4
:
1204 case nir_op_fnoise3_1
:
1205 case nir_op_fnoise3_2
:
1206 case nir_op_fnoise3_3
:
1207 case nir_op_fnoise3_4
:
1208 case nir_op_fnoise4_1
:
1209 case nir_op_fnoise4_2
:
1210 case nir_op_fnoise4_3
:
1211 case nir_op_fnoise4_4
:
1212 unreachable("not reached: should be handled by lower_noise");
1215 unreachable("not reached: should be handled by ldexp_to_arith()");
1218 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1219 inst
->saturate
= instr
->dest
.saturate
;
1223 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1224 inst
->saturate
= instr
->dest
.saturate
;
1229 bld
.MOV(result
, negate(op
[0]));
1234 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1235 if (bit_size
== 64) {
1236 /* two-argument instructions can't take 64-bit immediates */
1240 if (instr
->op
== nir_op_f2b
) {
1241 zero
= vgrf(glsl_type::double_type
);
1242 tmp
= vgrf(glsl_type::double_type
);
1243 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1245 zero
= vgrf(glsl_type::int64_t_type
);
1246 tmp
= vgrf(glsl_type::int64_t_type
);
1247 bld
.MOV(zero
, brw_imm_q(0));
1250 /* A SIMD16 execution needs to be split in two instructions, so use
1251 * a vgrf instead of the flag register as dst so instruction splitting
1254 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1255 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1258 if (bit_size
== 32) {
1259 zero
= instr
->op
== nir_op_f2b
? brw_imm_f(0.0f
) : brw_imm_d(0);
1261 assert(bit_size
== 16);
1262 zero
= instr
->op
== nir_op_f2b
?
1263 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1265 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1271 inst
= bld
.RNDZ(result
, op
[0]);
1272 inst
->saturate
= instr
->dest
.saturate
;
1275 case nir_op_fceil
: {
1276 op
[0].negate
= !op
[0].negate
;
1277 fs_reg temp
= vgrf(glsl_type::float_type
);
1278 bld
.RNDD(temp
, op
[0]);
1280 inst
= bld
.MOV(result
, temp
);
1281 inst
->saturate
= instr
->dest
.saturate
;
1285 inst
= bld
.RNDD(result
, op
[0]);
1286 inst
->saturate
= instr
->dest
.saturate
;
1289 inst
= bld
.FRC(result
, op
[0]);
1290 inst
->saturate
= instr
->dest
.saturate
;
1292 case nir_op_fround_even
:
1293 inst
= bld
.RNDE(result
, op
[0]);
1294 inst
->saturate
= instr
->dest
.saturate
;
1297 case nir_op_fquantize2f16
: {
1298 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1299 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1300 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1302 /* The destination stride must be at least as big as the source stride. */
1303 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1306 /* Check for denormal */
1307 fs_reg abs_src0
= op
[0];
1308 abs_src0
.abs
= true;
1309 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1311 /* Get the appropriately signed zero */
1312 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1313 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1314 brw_imm_ud(0x80000000));
1315 /* Do the actual F32 -> F16 -> F32 conversion */
1316 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1317 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1318 /* Select that or zero based on normal status */
1319 inst
= bld
.SEL(result
, zero
, tmp32
);
1320 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1321 inst
->saturate
= instr
->dest
.saturate
;
1328 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1329 inst
->saturate
= instr
->dest
.saturate
;
1335 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1336 inst
->saturate
= instr
->dest
.saturate
;
1339 case nir_op_pack_snorm_2x16
:
1340 case nir_op_pack_snorm_4x8
:
1341 case nir_op_pack_unorm_2x16
:
1342 case nir_op_pack_unorm_4x8
:
1343 case nir_op_unpack_snorm_2x16
:
1344 case nir_op_unpack_snorm_4x8
:
1345 case nir_op_unpack_unorm_2x16
:
1346 case nir_op_unpack_unorm_4x8
:
1347 case nir_op_unpack_half_2x16
:
1348 case nir_op_pack_half_2x16
:
1349 unreachable("not reached: should be handled by lower_packing_builtins");
1351 case nir_op_unpack_half_2x16_split_x
:
1352 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1353 inst
->saturate
= instr
->dest
.saturate
;
1355 case nir_op_unpack_half_2x16_split_y
:
1356 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1357 inst
->saturate
= instr
->dest
.saturate
;
1360 case nir_op_pack_64_2x32_split
:
1361 case nir_op_pack_32_2x16_split
:
1362 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1365 case nir_op_unpack_64_2x32_split_x
:
1366 case nir_op_unpack_64_2x32_split_y
: {
1367 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1368 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1370 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1374 case nir_op_unpack_32_2x16_split_x
:
1375 case nir_op_unpack_32_2x16_split_y
: {
1376 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1377 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1379 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1384 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1385 inst
->saturate
= instr
->dest
.saturate
;
1388 case nir_op_bitfield_reverse
:
1389 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1390 bld
.BFREV(result
, op
[0]);
1393 case nir_op_bit_count
:
1394 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1395 bld
.CBIT(result
, op
[0]);
1398 case nir_op_ufind_msb
: {
1399 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1400 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1404 case nir_op_ifind_msb
: {
1405 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1407 if (devinfo
->gen
< 7) {
1408 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1410 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1412 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1413 * count from the LSB side. If FBH didn't return an error
1414 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1415 * count into an LSB count.
1417 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1419 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1420 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1421 inst
->src
[0].negate
= true;
1426 case nir_op_find_lsb
:
1427 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1429 if (devinfo
->gen
< 7) {
1430 fs_reg temp
= vgrf(glsl_type::int_type
);
1432 /* (x & -x) generates a value that consists of only the LSB of x.
1433 * For all powers of 2, findMSB(y) == findLSB(y).
1435 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1436 fs_reg negated_src
= src
;
1438 /* One must be negated, and the other must be non-negated. It
1439 * doesn't matter which is which.
1441 negated_src
.negate
= true;
1444 bld
.AND(temp
, src
, negated_src
);
1445 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1447 bld
.FBL(result
, op
[0]);
1451 case nir_op_ubitfield_extract
:
1452 case nir_op_ibitfield_extract
:
1453 unreachable("should have been lowered");
1456 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1457 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1460 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1461 bld
.BFI1(result
, op
[0], op
[1]);
1464 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1465 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1468 case nir_op_bitfield_insert
:
1469 unreachable("not reached: should have been lowered");
1474 fs_reg shift_count
= op
[1];
1476 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1477 if (op
[1].file
== VGRF
&&
1478 (result
.type
== BRW_REGISTER_TYPE_Q
||
1479 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1480 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1481 BRW_REGISTER_TYPE_UD
);
1482 shift_count
.stride
= 2;
1483 bld
.MOV(shift_count
, op
[1]);
1487 switch (instr
->op
) {
1489 bld
.SHL(result
, op
[0], shift_count
);
1492 bld
.ASR(result
, op
[0], shift_count
);
1495 bld
.SHR(result
, op
[0], shift_count
);
1498 unreachable("not reached");
1503 case nir_op_pack_half_2x16_split
:
1504 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1508 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1509 inst
->saturate
= instr
->dest
.saturate
;
1513 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1514 inst
->saturate
= instr
->dest
.saturate
;
1518 if (optimize_frontfacing_ternary(instr
, result
))
1521 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1522 inst
= bld
.SEL(result
, op
[1], op
[2]);
1523 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1526 case nir_op_extract_u8
:
1527 case nir_op_extract_i8
: {
1528 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1529 assert(byte
!= NULL
);
1534 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1535 * Use two instructions and a word or DWord intermediate integer type.
1537 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1538 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1540 if (instr
->op
== nir_op_extract_i8
) {
1541 /* If we need to sign extend, extract to a word first */
1542 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1543 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
->u32
[0]));
1544 bld
.MOV(result
, w_temp
);
1546 /* Otherwise use an AND with 0xff and a word type */
1547 bld
.AND(result
, subscript(op
[0], type
, byte
->u32
[0] / 2), brw_imm_uw(0xff));
1550 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1551 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1556 case nir_op_extract_u16
:
1557 case nir_op_extract_i16
: {
1558 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1559 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1560 assert(word
!= NULL
);
1561 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1566 unreachable("unhandled instruction");
1569 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1570 * to sign extend the low bit to 0/~0
1572 if (devinfo
->gen
<= 5 &&
1573 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1574 fs_reg masked
= vgrf(glsl_type::int_type
);
1575 bld
.AND(masked
, result
, brw_imm_d(1));
1576 masked
.negate
= true;
1577 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1582 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1583 nir_load_const_instr
*instr
)
1585 const brw_reg_type reg_type
=
1586 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1587 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1589 switch (instr
->def
.bit_size
) {
1591 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1592 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1596 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1597 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1601 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1602 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1606 assert(devinfo
->gen
>= 7);
1607 if (devinfo
->gen
== 7) {
1608 /* We don't get 64-bit integer types until gen8 */
1609 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1610 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1611 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1614 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1615 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1620 unreachable("Invalid bit size");
1623 nir_ssa_values
[instr
->def
.index
] = reg
;
1627 fs_visitor::get_nir_src(const nir_src
&src
)
1631 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1632 const brw_reg_type reg_type
=
1633 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1634 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1636 reg
= nir_ssa_values
[src
.ssa
->index
];
1639 /* We don't handle indirects on locals */
1640 assert(src
.reg
.indirect
== NULL
);
1641 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1642 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1645 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1646 /* The only 64-bit type available on gen7 is DF, so use that. */
1647 reg
.type
= BRW_REGISTER_TYPE_DF
;
1649 /* To avoid floating-point denorm flushing problems, set the type by
1650 * default to an integer type - instructions that need floating point
1651 * semantics will set this to F if they need to
1653 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1654 BRW_REGISTER_TYPE_D
);
1661 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1663 * This function should not be called on any value which may be 64 bits.
1664 * We could theoretically support 64-bit on gen8+ but we choose not to
1665 * because it wouldn't work in general (no gen7 support) and there are
1666 * enough restrictions in 64-bit immediates that you can't take the return
1667 * value and treat it the same as the result of get_nir_src().
1670 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1672 nir_const_value
*val
= nir_src_as_const_value(src
);
1673 assert(nir_src_bit_size(src
) == 32);
1674 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1678 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1681 const brw_reg_type reg_type
=
1682 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1683 dest
.ssa
.bit_size
== 8 ?
1684 BRW_REGISTER_TYPE_D
:
1685 BRW_REGISTER_TYPE_F
);
1686 nir_ssa_values
[dest
.ssa
.index
] =
1687 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1688 return nir_ssa_values
[dest
.ssa
.index
];
1690 /* We don't handle indirects on locals */
1691 assert(dest
.reg
.indirect
== NULL
);
1692 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1693 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1698 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1701 for (unsigned i
= 0; i
< 4; i
++) {
1702 if (!((wr_mask
>> i
) & 1))
1705 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1706 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1707 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1708 if (new_inst
->src
[j
].file
== VGRF
)
1709 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1716 * Get the matching channel register datatype for an image intrinsic of the
1717 * specified GLSL image type.
1720 get_image_base_type(const glsl_type
*type
)
1722 switch ((glsl_base_type
)type
->sampled_type
) {
1723 case GLSL_TYPE_UINT
:
1724 return BRW_REGISTER_TYPE_UD
;
1726 return BRW_REGISTER_TYPE_D
;
1727 case GLSL_TYPE_FLOAT
:
1728 return BRW_REGISTER_TYPE_F
;
1730 unreachable("Not reached.");
1735 emit_pixel_interpolater_send(const fs_builder
&bld
,
1740 glsl_interp_mode interpolation
)
1742 struct brw_wm_prog_data
*wm_prog_data
=
1743 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1745 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1746 /* 2 floats per slot returned */
1747 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1748 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1750 wm_prog_data
->pulls_bary
= true;
1756 * Computes 1 << x, given a D/UD register containing some value x.
1759 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1761 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1763 fs_reg result
= bld
.vgrf(x
.type
, 1);
1764 fs_reg one
= bld
.vgrf(x
.type
, 1);
1766 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1767 bld
.SHL(result
, one
, x
);
1772 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1774 assert(stage
== MESA_SHADER_GEOMETRY
);
1776 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1778 if (gs_compile
->control_data_header_size_bits
== 0)
1781 /* We can only do EndPrimitive() functionality when the control data
1782 * consists of cut bits. Fortunately, the only time it isn't is when the
1783 * output type is points, in which case EndPrimitive() is a no-op.
1785 if (gs_prog_data
->control_data_format
!=
1786 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1790 /* Cut bits use one bit per vertex. */
1791 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1793 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1794 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1796 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1797 * vertex n, 0 otherwise. So all we need to do here is mark bit
1798 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1799 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1800 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1802 * Note that if EndPrimitive() is called before emitting any vertices, this
1803 * will cause us to set bit 31 of the control_data_bits register to 1.
1804 * That's fine because:
1806 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1807 * output, so the hardware will ignore cut bit 31.
1809 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1810 * last vertex, so setting cut bit 31 has no effect (since the primitive
1811 * is automatically ended when the GS terminates).
1813 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1814 * control_data_bits register to 0 when the first vertex is emitted.
1817 const fs_builder abld
= bld
.annotate("end primitive");
1819 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1820 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1821 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1822 fs_reg mask
= intexp2(abld
, prev_count
);
1823 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1824 * attention to the lower 5 bits of its second source argument, so on this
1825 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1826 * ((vertex_count - 1) % 32).
1828 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1832 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1834 assert(stage
== MESA_SHADER_GEOMETRY
);
1835 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1837 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1839 const fs_builder abld
= bld
.annotate("emit control data bits");
1840 const fs_builder fwa_bld
= bld
.exec_all();
1842 /* We use a single UD register to accumulate control data bits (32 bits
1843 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1846 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1847 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1848 * use the Channel Mask phase to enable/disable which DWord within that
1849 * group to write. (Remember, different SIMD8 channels may have emitted
1850 * different numbers of vertices, so we may need per-slot offsets.)
1852 * Channel masking presents an annoying problem: we may have to replicate
1853 * the data up to 4 times:
1855 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1857 * To avoid penalizing shaders that emit a small number of vertices, we
1858 * can avoid these sometimes: if the size of the control data header is
1859 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1860 * land in the same 128-bit group, so we can skip per-slot offsets.
1862 * Similarly, if the control data header is <= 32 bits, there is only one
1863 * DWord, so we can skip channel masks.
1865 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1867 fs_reg channel_mask
, per_slot_offset
;
1869 if (gs_compile
->control_data_header_size_bits
> 32) {
1870 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1871 channel_mask
= vgrf(glsl_type::uint_type
);
1874 if (gs_compile
->control_data_header_size_bits
> 128) {
1875 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1876 per_slot_offset
= vgrf(glsl_type::uint_type
);
1879 /* Figure out which DWord we're trying to write to using the formula:
1881 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1883 * Since bits_per_vertex is a power of two, and is known at compile
1884 * time, this can be optimized to:
1886 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1888 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1889 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1890 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1891 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1892 unsigned log2_bits_per_vertex
=
1893 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1894 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1896 if (per_slot_offset
.file
!= BAD_FILE
) {
1897 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1898 * the appropriate OWord within the control data header.
1900 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1903 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1904 * write to the appropriate DWORD within the OWORD.
1906 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1907 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1908 channel_mask
= intexp2(fwa_bld
, channel
);
1909 /* Then the channel masks need to be in bits 23:16. */
1910 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1913 /* Store the control data bits in the message payload and send it. */
1915 if (channel_mask
.file
!= BAD_FILE
)
1916 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1917 if (per_slot_offset
.file
!= BAD_FILE
)
1920 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1921 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1923 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1924 if (per_slot_offset
.file
!= BAD_FILE
)
1925 sources
[i
++] = per_slot_offset
;
1926 if (channel_mask
.file
!= BAD_FILE
)
1927 sources
[i
++] = channel_mask
;
1929 sources
[i
++] = this->control_data_bits
;
1932 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1933 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1935 /* We need to increment Global Offset by 256-bits to make room for
1936 * Broadwell's extra "Vertex Count" payload at the beginning of the
1937 * URB entry. Since this is an OWord message, Global Offset is counted
1938 * in 128-bit units, so we must set it to 2.
1940 if (gs_prog_data
->static_vertex_count
== -1)
1945 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1948 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1950 /* Note: we are calling this *before* increasing vertex_count, so
1951 * this->vertex_count == vertex_count - 1 in the formula above.
1954 /* Stream mode uses 2 bits per vertex */
1955 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1957 /* Must be a valid stream */
1958 assert(stream_id
< MAX_VERTEX_STREAMS
);
1960 /* Control data bits are initialized to 0 so we don't have to set any
1961 * bits when sending vertices to stream 0.
1966 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1968 /* reg::sid = stream_id */
1969 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1970 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1972 /* reg:shift_count = 2 * (vertex_count - 1) */
1973 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1974 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1976 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1977 * attention to the lower 5 bits of its second source argument, so on this
1978 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1979 * stream_id << ((2 * (vertex_count - 1)) % 32).
1981 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1982 abld
.SHL(mask
, sid
, shift_count
);
1983 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1987 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1990 assert(stage
== MESA_SHADER_GEOMETRY
);
1992 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1994 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1995 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1997 /* Haswell and later hardware ignores the "Render Stream Select" bits
1998 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1999 * and instead sends all primitives down the pipeline for rasterization.
2000 * If the SOL stage is enabled, "Render Stream Select" is honored and
2001 * primitives bound to non-zero streams are discarded after stream output.
2003 * Since the only purpose of primives sent to non-zero streams is to
2004 * be recorded by transform feedback, we can simply discard all geometry
2005 * bound to these streams when transform feedback is disabled.
2007 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2010 /* If we're outputting 32 control data bits or less, then we can wait
2011 * until the shader is over to output them all. Otherwise we need to
2012 * output them as we go. Now is the time to do it, since we're about to
2013 * output the vertex_count'th vertex, so it's guaranteed that the
2014 * control data bits associated with the (vertex_count - 1)th vertex are
2017 if (gs_compile
->control_data_header_size_bits
> 32) {
2018 const fs_builder abld
=
2019 bld
.annotate("emit vertex: emit control data bits");
2021 /* Only emit control data bits if we've finished accumulating a batch
2022 * of 32 bits. This is the case when:
2024 * (vertex_count * bits_per_vertex) % 32 == 0
2026 * (in other words, when the last 5 bits of vertex_count *
2027 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2028 * integer n (which is always the case, since bits_per_vertex is
2029 * always 1 or 2), this is equivalent to requiring that the last 5-n
2030 * bits of vertex_count are 0:
2032 * vertex_count & (2^(5-n) - 1) == 0
2034 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2037 * vertex_count & (32 / bits_per_vertex - 1) == 0
2039 * TODO: If vertex_count is an immediate, we could do some of this math
2040 * at compile time...
2043 abld
.AND(bld
.null_reg_d(), vertex_count
,
2044 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2045 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2047 abld
.IF(BRW_PREDICATE_NORMAL
);
2048 /* If vertex_count is 0, then no control data bits have been
2049 * accumulated yet, so we can skip emitting them.
2051 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2052 BRW_CONDITIONAL_NEQ
);
2053 abld
.IF(BRW_PREDICATE_NORMAL
);
2054 emit_gs_control_data_bits(vertex_count
);
2055 abld
.emit(BRW_OPCODE_ENDIF
);
2057 /* Reset control_data_bits to 0 so we can start accumulating a new
2060 * Note: in the case where vertex_count == 0, this neutralizes the
2061 * effect of any call to EndPrimitive() that the shader may have
2062 * made before outputting its first vertex.
2064 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2065 inst
->force_writemask_all
= true;
2066 abld
.emit(BRW_OPCODE_ENDIF
);
2069 emit_urb_writes(vertex_count
);
2071 /* In stream mode we have to set control data bits for all vertices
2072 * unless we have disabled control data bits completely (which we do
2073 * do for GL_POINTS outputs that don't use streams).
2075 if (gs_compile
->control_data_header_size_bits
> 0 &&
2076 gs_prog_data
->control_data_format
==
2077 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2078 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2083 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2084 const nir_src
&vertex_src
,
2085 unsigned base_offset
,
2086 const nir_src
&offset_src
,
2087 unsigned num_components
,
2088 unsigned first_component
)
2090 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2092 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2093 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2094 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2096 /* TODO: figure out push input layout for invocations == 1 */
2097 /* TODO: make this work with 64-bit inputs */
2098 if (gs_prog_data
->invocations
== 1 &&
2099 type_sz(dst
.type
) <= 4 &&
2100 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2101 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2102 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2103 vertex_const
->u32
[0] * push_reg_count
;
2104 for (unsigned i
= 0; i
< num_components
; i
++) {
2105 bld
.MOV(offset(dst
, bld
, i
),
2106 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2111 /* Resort to the pull model. Ensure the VUE handles are provided. */
2112 assert(gs_prog_data
->base
.include_vue_handles
);
2114 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2115 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2117 if (gs_prog_data
->invocations
== 1) {
2119 /* The vertex index is constant; just select the proper URB handle. */
2121 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2122 BRW_REGISTER_TYPE_UD
);
2124 /* The vertex index is non-constant. We need to use indirect
2125 * addressing to fetch the proper URB handle.
2127 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2128 * indicating that channel <n> should read the handle from
2129 * DWord <n>. We convert that to bytes by multiplying by 4.
2131 * Next, we convert the vertex index to bytes by multiplying
2132 * by 32 (shifting by 5), and add the two together. This is
2133 * the final indirect byte offset.
2135 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2136 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2137 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2138 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2140 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2141 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2142 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2143 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2144 /* Convert vertex_index to bytes (multiply by 32) */
2145 bld
.SHL(vertex_offset_bytes
,
2146 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2148 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2150 /* Use first_icp_handle as the base offset. There is one register
2151 * of URB handles per vertex, so inform the register allocator that
2152 * we might read up to nir->info.gs.vertices_in registers.
2154 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2155 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2156 fs_reg(icp_offset_bytes
),
2157 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2160 assert(gs_prog_data
->invocations
> 1);
2163 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2165 retype(brw_vec1_grf(first_icp_handle
+
2166 vertex_const
->i32
[0] / 8,
2167 vertex_const
->i32
[0] % 8),
2168 BRW_REGISTER_TYPE_UD
));
2170 /* The vertex index is non-constant. We need to use indirect
2171 * addressing to fetch the proper URB handle.
2174 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2176 /* Convert vertex_index to bytes (multiply by 4) */
2177 bld
.SHL(icp_offset_bytes
,
2178 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2181 /* Use first_icp_handle as the base offset. There is one DWord
2182 * of URB handles per vertex, so inform the register allocator that
2183 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2185 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2186 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2187 fs_reg(icp_offset_bytes
),
2188 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2195 fs_reg tmp_dst
= dst
;
2196 fs_reg indirect_offset
= get_nir_src(offset_src
);
2197 unsigned num_iterations
= 1;
2198 unsigned orig_num_components
= num_components
;
2200 if (type_sz(dst
.type
) == 8) {
2201 if (num_components
> 2) {
2205 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2207 first_component
= first_component
/ 2;
2210 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2212 /* Constant indexing - use global offset. */
2213 if (first_component
!= 0) {
2214 unsigned read_components
= num_components
+ first_component
;
2215 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2216 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2217 inst
->size_written
= read_components
*
2218 tmp
.component_size(inst
->exec_size
);
2219 for (unsigned i
= 0; i
< num_components
; i
++) {
2220 bld
.MOV(offset(tmp_dst
, bld
, i
),
2221 offset(tmp
, bld
, i
+ first_component
));
2224 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2226 inst
->size_written
= num_components
*
2227 tmp_dst
.component_size(inst
->exec_size
);
2229 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2232 /* Indirect indexing - use per-slot offsets as well. */
2233 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2234 unsigned read_components
= num_components
+ first_component
;
2235 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2236 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2237 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2238 if (first_component
!= 0) {
2239 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2241 inst
->size_written
= read_components
*
2242 tmp
.component_size(inst
->exec_size
);
2243 for (unsigned i
= 0; i
< num_components
; i
++) {
2244 bld
.MOV(offset(tmp_dst
, bld
, i
),
2245 offset(tmp
, bld
, i
+ first_component
));
2248 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2250 inst
->size_written
= num_components
*
2251 tmp_dst
.component_size(inst
->exec_size
);
2253 inst
->offset
= base_offset
;
2257 if (type_sz(dst
.type
) == 8) {
2258 shuffle_from_32bit_read(bld
,
2259 offset(dst
, bld
, iter
* 2),
2260 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2265 if (num_iterations
> 1) {
2266 num_components
= orig_num_components
- 2;
2270 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2271 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2272 indirect_offset
= new_indirect
;
2279 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2281 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2282 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2285 /* The only constant offset we should find is 0. brw_nir.c's
2286 * add_const_offset_to_base() will fold other constant offsets
2287 * into instr->const_index[0].
2289 assert(const_value
->u32
[0] == 0);
2293 return get_nir_src(*offset_src
);
2297 do_untyped_vector_read(const fs_builder
&bld
,
2299 const fs_reg surf_index
,
2300 const fs_reg offset_reg
,
2301 unsigned num_components
)
2303 if (type_sz(dest
.type
) <= 2) {
2304 assert(dest
.stride
== 1);
2305 boolean is_const_offset
= offset_reg
.file
== BRW_IMMEDIATE_VALUE
;
2307 if (is_const_offset
) {
2308 uint32_t start
= offset_reg
.ud
& ~3;
2309 uint32_t end
= offset_reg
.ud
+ num_components
* type_sz(dest
.type
);
2310 end
= ALIGN(end
, 4);
2311 assert (end
- start
<= 16);
2313 /* At this point we have 16-bit component/s that have constant
2314 * offset aligned to 4-bytes that can be read with untyped_reads.
2315 * untyped_read message requires 32-bit aligned offsets.
2317 unsigned first_component
= (offset_reg
.ud
& 3) / type_sz(dest
.type
);
2318 unsigned num_components_32bit
= (end
- start
) / 4;
2320 fs_reg read_result
=
2321 emit_untyped_read(bld
, surf_index
, brw_imm_ud(start
),
2323 num_components_32bit
,
2324 BRW_PREDICATE_NONE
);
2325 shuffle_from_32bit_read(bld
, dest
, read_result
, first_component
,
2328 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2329 for (unsigned i
= 0; i
< num_components
; i
++) {
2331 bld
.MOV(read_offset
, offset_reg
);
2333 bld
.ADD(read_offset
, offset_reg
,
2334 brw_imm_ud(i
* type_sz(dest
.type
)));
2336 /* Non constant offsets are not guaranteed to be aligned 32-bits
2337 * so they are read using one byte_scattered_read message
2338 * for each component.
2340 fs_reg read_result
=
2341 emit_byte_scattered_read(bld
, surf_index
, read_offset
,
2343 type_sz(dest
.type
) * 8 /* bit_size */,
2344 BRW_PREDICATE_NONE
);
2345 bld
.MOV(offset(dest
, bld
, i
),
2346 subscript (read_result
, dest
.type
, 0));
2349 } else if (type_sz(dest
.type
) == 4) {
2350 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2353 BRW_PREDICATE_NONE
);
2354 read_result
.type
= dest
.type
;
2355 for (unsigned i
= 0; i
< num_components
; i
++)
2356 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2357 } else if (type_sz(dest
.type
) == 8) {
2358 /* Reading a dvec, so we need to:
2360 * 1. Multiply num_components by 2, to account for the fact that we
2361 * need to read 64-bit components.
2362 * 2. Shuffle the result of the load to form valid 64-bit elements
2363 * 3. Emit a second load (for components z/w) if needed.
2365 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2366 bld
.MOV(read_offset
, offset_reg
);
2368 int iters
= num_components
<= 2 ? 1 : 2;
2370 /* Load the dvec, the first iteration loads components x/y, the second
2371 * iteration, if needed, loads components z/w
2373 for (int it
= 0; it
< iters
; it
++) {
2374 /* Compute number of components to read in this iteration */
2375 int iter_components
= MIN2(2, num_components
);
2376 num_components
-= iter_components
;
2378 /* Read. Since this message reads 32-bit components, we need to
2379 * read twice as many components.
2381 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2383 iter_components
* 2,
2384 BRW_PREDICATE_NONE
);
2386 /* Shuffle the 32-bit load result into valid 64-bit data */
2387 shuffle_from_32bit_read(bld
, offset(dest
, bld
, it
* 2),
2388 read_result
, 0, iter_components
);
2390 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2393 unreachable("Unsupported type");
2398 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2399 nir_intrinsic_instr
*instr
)
2401 assert(stage
== MESA_SHADER_VERTEX
);
2404 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2405 dest
= get_nir_dest(instr
->dest
);
2407 switch (instr
->intrinsic
) {
2408 case nir_intrinsic_load_vertex_id
:
2409 case nir_intrinsic_load_base_vertex
:
2410 unreachable("should be lowered by nir_lower_system_values()");
2412 case nir_intrinsic_load_input
: {
2413 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2414 unsigned first_component
= nir_intrinsic_component(instr
);
2415 unsigned num_components
= instr
->num_components
;
2417 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2418 assert(const_offset
&& "Indirect input loads not allowed");
2419 src
= offset(src
, bld
, const_offset
->u32
[0]);
2421 if (type_sz(dest
.type
) == 8)
2422 first_component
/= 2;
2424 /* For 16-bit support maybe a temporary will be needed to copy from
2427 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2428 first_component
, num_components
);
2432 case nir_intrinsic_load_vertex_id_zero_base
:
2433 case nir_intrinsic_load_instance_id
:
2434 case nir_intrinsic_load_base_instance
:
2435 case nir_intrinsic_load_draw_id
:
2436 case nir_intrinsic_load_first_vertex
:
2437 case nir_intrinsic_load_is_indexed_draw
:
2438 unreachable("lowered by brw_nir_lower_vs_inputs");
2441 nir_emit_intrinsic(bld
, instr
);
2447 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2448 nir_intrinsic_instr
*instr
)
2450 assert(stage
== MESA_SHADER_TESS_CTRL
);
2451 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2452 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2455 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2456 dst
= get_nir_dest(instr
->dest
);
2458 switch (instr
->intrinsic
) {
2459 case nir_intrinsic_load_primitive_id
:
2460 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2462 case nir_intrinsic_load_invocation_id
:
2463 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2465 case nir_intrinsic_load_patch_vertices_in
:
2466 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2467 brw_imm_d(tcs_key
->input_vertices
));
2470 case nir_intrinsic_barrier
: {
2471 if (tcs_prog_data
->instances
== 1)
2474 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2475 fs_reg m0_2
= component(m0
, 2);
2477 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2479 /* Zero the message header */
2480 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2482 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2483 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2484 brw_imm_ud(INTEL_MASK(16, 13)));
2486 /* Shift it up to bits 27:24. */
2487 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2489 /* Set the Barrier Count and the enable bit */
2490 chanbld
.OR(m0_2
, m0_2
,
2491 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2493 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2497 case nir_intrinsic_load_input
:
2498 unreachable("nir_lower_io should never give us these.");
2501 case nir_intrinsic_load_per_vertex_input
: {
2502 fs_reg indirect_offset
= get_indirect_offset(instr
);
2503 unsigned imm_offset
= instr
->const_index
[0];
2505 const nir_src
&vertex_src
= instr
->src
[0];
2506 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2513 /* Emit a MOV to resolve <0,1,0> regioning. */
2514 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2516 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2517 vertex_const
->i32
[0] & 7),
2518 BRW_REGISTER_TYPE_UD
));
2519 } else if (tcs_prog_data
->instances
== 1 &&
2520 vertex_src
.is_ssa
&&
2521 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2522 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2523 /* For the common case of only 1 instance, an array index of
2524 * gl_InvocationID means reading g1. Skip all the indirect work.
2526 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2528 /* The vertex index is non-constant. We need to use indirect
2529 * addressing to fetch the proper URB handle.
2531 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2533 /* Each ICP handle is a single DWord (4 bytes) */
2534 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2535 bld
.SHL(vertex_offset_bytes
,
2536 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2539 /* Start at g1. We might read up to 4 registers. */
2540 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2541 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2542 brw_imm_ud(4 * REG_SIZE
));
2545 /* We can only read two double components with each URB read, so
2546 * we send two read messages in that case, each one loading up to
2547 * two double components.
2549 unsigned num_iterations
= 1;
2550 unsigned num_components
= instr
->num_components
;
2551 unsigned first_component
= nir_intrinsic_component(instr
);
2552 fs_reg orig_dst
= dst
;
2553 if (type_sz(dst
.type
) == 8) {
2554 first_component
= first_component
/ 2;
2555 if (instr
->num_components
> 2) {
2560 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2564 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2565 if (indirect_offset
.file
== BAD_FILE
) {
2566 /* Constant indexing - use global offset. */
2567 if (first_component
!= 0) {
2568 unsigned read_components
= num_components
+ first_component
;
2569 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2570 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2571 for (unsigned i
= 0; i
< num_components
; i
++) {
2572 bld
.MOV(offset(dst
, bld
, i
),
2573 offset(tmp
, bld
, i
+ first_component
));
2576 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2578 inst
->offset
= imm_offset
;
2581 /* Indirect indexing - use per-slot offsets as well. */
2582 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2583 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2584 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2585 if (first_component
!= 0) {
2586 unsigned read_components
= num_components
+ first_component
;
2587 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2588 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2590 for (unsigned i
= 0; i
< num_components
; i
++) {
2591 bld
.MOV(offset(dst
, bld
, i
),
2592 offset(tmp
, bld
, i
+ first_component
));
2595 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2598 inst
->offset
= imm_offset
;
2601 inst
->size_written
= (num_components
+ first_component
) *
2602 inst
->dst
.component_size(inst
->exec_size
);
2604 /* If we are reading 64-bit data using 32-bit read messages we need
2605 * build proper 64-bit data elements by shuffling the low and high
2606 * 32-bit components around like we do for other things like UBOs
2609 if (type_sz(dst
.type
) == 8) {
2610 shuffle_from_32bit_read(bld
,
2611 offset(orig_dst
, bld
, iter
* 2),
2612 retype(dst
, BRW_REGISTER_TYPE_D
),
2616 /* Copy the temporary to the destination to deal with writemasking.
2618 * Also attempt to deal with gl_PointSize being in the .w component.
2620 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2621 assert(type_sz(dst
.type
) < 8);
2622 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2623 inst
->size_written
= 4 * REG_SIZE
;
2624 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2627 /* If we are loading double data and we need a second read message
2628 * adjust the write offset
2630 if (num_iterations
> 1) {
2631 num_components
= instr
->num_components
- 2;
2638 case nir_intrinsic_load_output
:
2639 case nir_intrinsic_load_per_vertex_output
: {
2640 fs_reg indirect_offset
= get_indirect_offset(instr
);
2641 unsigned imm_offset
= instr
->const_index
[0];
2642 unsigned first_component
= nir_intrinsic_component(instr
);
2645 if (indirect_offset
.file
== BAD_FILE
) {
2646 /* Replicate the patch handle to all enabled channels */
2647 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2648 bld
.MOV(patch_handle
,
2649 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2652 if (first_component
!= 0) {
2653 unsigned read_components
=
2654 instr
->num_components
+ first_component
;
2655 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2656 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2658 inst
->size_written
= read_components
* REG_SIZE
;
2659 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2660 bld
.MOV(offset(dst
, bld
, i
),
2661 offset(tmp
, bld
, i
+ first_component
));
2664 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2666 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2668 inst
->offset
= imm_offset
;
2672 /* Indirect indexing - use per-slot offsets as well. */
2673 const fs_reg srcs
[] = {
2674 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2677 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2678 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2679 if (first_component
!= 0) {
2680 unsigned read_components
=
2681 instr
->num_components
+ first_component
;
2682 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2683 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2685 inst
->size_written
= read_components
* REG_SIZE
;
2686 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2687 bld
.MOV(offset(dst
, bld
, i
),
2688 offset(tmp
, bld
, i
+ first_component
));
2691 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2693 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2695 inst
->offset
= imm_offset
;
2701 case nir_intrinsic_store_output
:
2702 case nir_intrinsic_store_per_vertex_output
: {
2703 fs_reg value
= get_nir_src(instr
->src
[0]);
2704 bool is_64bit
= (instr
->src
[0].is_ssa
?
2705 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2706 fs_reg indirect_offset
= get_indirect_offset(instr
);
2707 unsigned imm_offset
= instr
->const_index
[0];
2708 unsigned mask
= instr
->const_index
[1];
2709 unsigned header_regs
= 0;
2711 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2713 if (indirect_offset
.file
!= BAD_FILE
) {
2714 srcs
[header_regs
++] = indirect_offset
;
2720 unsigned num_components
= util_last_bit(mask
);
2723 /* We can only pack two 64-bit components in a single message, so send
2724 * 2 messages if we have more components
2726 unsigned num_iterations
= 1;
2727 unsigned iter_components
= num_components
;
2728 unsigned first_component
= nir_intrinsic_component(instr
);
2730 first_component
= first_component
/ 2;
2731 if (instr
->num_components
> 2) {
2733 iter_components
= 2;
2737 mask
= mask
<< first_component
;
2739 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2740 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2741 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2742 opcode
= indirect_offset
.file
!= BAD_FILE
?
2743 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2744 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2745 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2746 /* Expand the 64-bit mask to 32-bit channels. We only handle
2747 * two channels in each iteration, so we only care about X/Y.
2749 unsigned mask32
= 0;
2750 if (mask
& WRITEMASK_X
)
2751 mask32
|= WRITEMASK_XY
;
2752 if (mask
& WRITEMASK_Y
)
2753 mask32
|= WRITEMASK_ZW
;
2755 /* If the mask does not include any of the channels X or Y there
2756 * is nothing to do in this iteration. Move on to the next couple
2757 * of 64-bit channels.
2765 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2766 opcode
= indirect_offset
.file
!= BAD_FILE
?
2767 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2768 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2770 opcode
= indirect_offset
.file
!= BAD_FILE
?
2771 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2772 SHADER_OPCODE_URB_WRITE_SIMD8
;
2775 for (unsigned i
= 0; i
< iter_components
; i
++) {
2776 if (!(mask
& (1 << (i
+ first_component
))))
2780 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2782 /* We need to shuffle the 64-bit data to match the layout
2783 * expected by our 32-bit URB write messages. We use a temporary
2786 unsigned channel
= iter
* 2 + i
;
2787 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2789 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2790 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2791 offset(dest
, bld
, 1);
2796 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2797 (is_64bit
? 2 * first_component
: first_component
);
2799 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2800 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2802 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2803 inst
->offset
= imm_offset
;
2806 /* If this is a 64-bit attribute, select the next two 64-bit channels
2807 * to be handled in the next iteration.
2818 nir_emit_intrinsic(bld
, instr
);
2824 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2825 nir_intrinsic_instr
*instr
)
2827 assert(stage
== MESA_SHADER_TESS_EVAL
);
2828 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2831 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2832 dest
= get_nir_dest(instr
->dest
);
2834 switch (instr
->intrinsic
) {
2835 case nir_intrinsic_load_primitive_id
:
2836 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2838 case nir_intrinsic_load_tess_coord
:
2839 /* gl_TessCoord is part of the payload in g1-3 */
2840 for (unsigned i
= 0; i
< 3; i
++) {
2841 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2845 case nir_intrinsic_load_input
:
2846 case nir_intrinsic_load_per_vertex_input
: {
2847 fs_reg indirect_offset
= get_indirect_offset(instr
);
2848 unsigned imm_offset
= instr
->const_index
[0];
2849 unsigned first_component
= nir_intrinsic_component(instr
);
2851 if (type_sz(dest
.type
) == 8) {
2852 first_component
= first_component
/ 2;
2856 if (indirect_offset
.file
== BAD_FILE
) {
2857 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2858 * which is 16 registers (since each holds 2 vec4 slots).
2860 unsigned slot_count
= 1;
2861 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2864 const unsigned max_push_slots
= 32;
2865 if (imm_offset
+ slot_count
<= max_push_slots
) {
2866 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2867 for (int i
= 0; i
< instr
->num_components
; i
++) {
2868 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2869 i
+ first_component
;
2870 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2873 tes_prog_data
->base
.urb_read_length
=
2874 MAX2(tes_prog_data
->base
.urb_read_length
,
2875 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2877 /* Replicate the patch handle to all enabled channels */
2878 const fs_reg srcs
[] = {
2879 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2881 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2882 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2884 if (first_component
!= 0) {
2885 unsigned read_components
=
2886 instr
->num_components
+ first_component
;
2887 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2888 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2890 inst
->size_written
= read_components
* REG_SIZE
;
2891 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2892 bld
.MOV(offset(dest
, bld
, i
),
2893 offset(tmp
, bld
, i
+ first_component
));
2896 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2898 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2901 inst
->offset
= imm_offset
;
2904 /* Indirect indexing - use per-slot offsets as well. */
2906 /* We can only read two double components with each URB read, so
2907 * we send two read messages in that case, each one loading up to
2908 * two double components.
2910 unsigned num_iterations
= 1;
2911 unsigned num_components
= instr
->num_components
;
2912 fs_reg orig_dest
= dest
;
2913 if (type_sz(dest
.type
) == 8) {
2914 if (instr
->num_components
> 2) {
2918 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2922 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2923 const fs_reg srcs
[] = {
2924 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2927 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2928 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2930 if (first_component
!= 0) {
2931 unsigned read_components
=
2932 num_components
+ first_component
;
2933 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2934 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2936 for (unsigned i
= 0; i
< num_components
; i
++) {
2937 bld
.MOV(offset(dest
, bld
, i
),
2938 offset(tmp
, bld
, i
+ first_component
));
2941 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2945 inst
->offset
= imm_offset
;
2946 inst
->size_written
= (num_components
+ first_component
) *
2947 inst
->dst
.component_size(inst
->exec_size
);
2949 /* If we are reading 64-bit data using 32-bit read messages we need
2950 * build proper 64-bit data elements by shuffling the low and high
2951 * 32-bit components around like we do for other things like UBOs
2954 if (type_sz(dest
.type
) == 8) {
2955 shuffle_from_32bit_read(bld
,
2956 offset(orig_dest
, bld
, iter
* 2),
2957 retype(dest
, BRW_REGISTER_TYPE_D
),
2961 /* If we are loading double data and we need a second read message
2964 if (num_iterations
> 1) {
2965 num_components
= instr
->num_components
- 2;
2973 nir_emit_intrinsic(bld
, instr
);
2979 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2980 nir_intrinsic_instr
*instr
)
2982 assert(stage
== MESA_SHADER_GEOMETRY
);
2983 fs_reg indirect_offset
;
2986 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2987 dest
= get_nir_dest(instr
->dest
);
2989 switch (instr
->intrinsic
) {
2990 case nir_intrinsic_load_primitive_id
:
2991 assert(stage
== MESA_SHADER_GEOMETRY
);
2992 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2993 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2994 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2997 case nir_intrinsic_load_input
:
2998 unreachable("load_input intrinsics are invalid for the GS stage");
3000 case nir_intrinsic_load_per_vertex_input
:
3001 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3002 instr
->src
[1], instr
->num_components
,
3003 nir_intrinsic_component(instr
));
3006 case nir_intrinsic_emit_vertex_with_counter
:
3007 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3010 case nir_intrinsic_end_primitive_with_counter
:
3011 emit_gs_end_primitive(instr
->src
[0]);
3014 case nir_intrinsic_set_vertex_count
:
3015 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3018 case nir_intrinsic_load_invocation_id
: {
3019 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3020 assert(val
.file
!= BAD_FILE
);
3021 dest
.type
= val
.type
;
3027 nir_emit_intrinsic(bld
, instr
);
3033 * Fetch the current render target layer index.
3036 fetch_render_target_array_index(const fs_builder
&bld
)
3038 if (bld
.shader
->devinfo
->gen
>= 6) {
3039 /* The render target array index is provided in the thread payload as
3040 * bits 26:16 of r0.0.
3042 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3043 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3047 /* Pre-SNB we only ever render into the first layer of the framebuffer
3048 * since layered rendering is not implemented.
3050 return brw_imm_ud(0);
3055 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3056 * framebuffer at the current fragment coordinates and sample index.
3059 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3062 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3064 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3065 const brw_wm_prog_key
*wm_key
=
3066 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3067 assert(!wm_key
->coherent_fb_fetch
);
3068 const struct brw_wm_prog_data
*wm_prog_data
=
3069 brw_wm_prog_data(stage_prog_data
);
3071 /* Calculate the surface index relative to the start of the texture binding
3072 * table block, since that's what the texturing messages expect.
3074 const unsigned surface
= target
+
3075 wm_prog_data
->binding_table
.render_target_read_start
-
3076 wm_prog_data
->base
.binding_table
.texture_start
;
3078 brw_mark_surface_used(
3079 bld
.shader
->stage_prog_data
,
3080 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3082 /* Calculate the fragment coordinates. */
3083 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3084 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3085 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3086 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3088 /* Calculate the sample index and MCS payload when multisampling. Luckily
3089 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3090 * shouldn't be necessary to recompile based on whether the framebuffer is
3093 if (wm_key
->multisample_fbo
&&
3094 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3095 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3097 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3098 const fs_reg mcs
= wm_key
->multisample_fbo
?
3099 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3101 /* Use either a normal or a CMS texel fetch message depending on whether
3102 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3103 * message just in case the framebuffer uses 16x multisampling, it should
3104 * be equivalent to the normal CMS fetch for lower multisampling modes.
3106 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3107 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3108 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3110 /* Emit the instruction. */
3111 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3113 brw_imm_ud(surface
), brw_imm_ud(0),
3114 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3115 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3117 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3118 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3124 * Actual coherent framebuffer read implemented using the native render target
3125 * read message. Requires SKL+.
3128 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3130 assert(bld
.shader
->devinfo
->gen
>= 9);
3131 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3132 inst
->target
= target
;
3133 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3139 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3141 if (n
&& regs
[0].file
!= BAD_FILE
) {
3145 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3147 for (unsigned i
= 0; i
< n
; i
++)
3155 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3157 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3158 const brw_wm_prog_key
*const key
=
3159 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3160 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3161 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3163 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3164 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3166 else if (l
== FRAG_RESULT_COLOR
)
3167 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3168 MAX2(key
->nr_color_regions
, 1));
3170 else if (l
== FRAG_RESULT_DEPTH
)
3171 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3173 else if (l
== FRAG_RESULT_STENCIL
)
3174 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3176 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3177 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3179 else if (l
>= FRAG_RESULT_DATA0
&&
3180 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3181 return alloc_temporary(v
->bld
, 4,
3182 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3185 unreachable("Invalid location");
3189 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3190 nir_intrinsic_instr
*instr
)
3192 assert(stage
== MESA_SHADER_FRAGMENT
);
3195 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3196 dest
= get_nir_dest(instr
->dest
);
3198 switch (instr
->intrinsic
) {
3199 case nir_intrinsic_load_front_face
:
3200 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3201 *emit_frontfacing_interpolation());
3204 case nir_intrinsic_load_sample_pos
: {
3205 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3206 assert(sample_pos
.file
!= BAD_FILE
);
3207 dest
.type
= sample_pos
.type
;
3208 bld
.MOV(dest
, sample_pos
);
3209 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3213 case nir_intrinsic_load_layer_id
:
3214 dest
.type
= BRW_REGISTER_TYPE_UD
;
3215 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3218 case nir_intrinsic_load_helper_invocation
:
3219 case nir_intrinsic_load_sample_mask_in
:
3220 case nir_intrinsic_load_sample_id
: {
3221 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3222 fs_reg val
= nir_system_values
[sv
];
3223 assert(val
.file
!= BAD_FILE
);
3224 dest
.type
= val
.type
;
3229 case nir_intrinsic_store_output
: {
3230 const fs_reg src
= get_nir_src(instr
->src
[0]);
3231 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3232 assert(const_offset
&& "Indirect output stores not allowed");
3233 const unsigned location
= nir_intrinsic_base(instr
) +
3234 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3235 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3238 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3239 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3240 offset(src
, bld
, j
));
3245 case nir_intrinsic_load_output
: {
3246 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3247 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3248 assert(l
>= FRAG_RESULT_DATA0
);
3249 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3250 assert(const_offset
&& "Indirect output loads not allowed");
3251 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3252 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3254 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3255 emit_coherent_fb_read(bld
, tmp
, target
);
3257 emit_non_coherent_fb_read(bld
, tmp
, target
);
3259 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3260 bld
.MOV(offset(dest
, bld
, j
),
3261 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3267 case nir_intrinsic_discard
:
3268 case nir_intrinsic_discard_if
: {
3269 /* We track our discarded pixels in f0.1. By predicating on it, we can
3270 * update just the flag bits that aren't yet discarded. If there's no
3271 * condition, we emit a CMP of g0 != g0, so all currently executing
3272 * channels will get turned off.
3275 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3276 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3277 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3279 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3280 BRW_REGISTER_TYPE_UW
));
3281 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3283 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3284 cmp
->flag_subreg
= 1;
3286 if (devinfo
->gen
>= 6) {
3287 emit_discard_jump();
3290 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3294 case nir_intrinsic_load_input
: {
3295 /* load_input is only used for flat inputs */
3296 unsigned base
= nir_intrinsic_base(instr
);
3297 unsigned comp
= nir_intrinsic_component(instr
);
3298 unsigned num_components
= instr
->num_components
;
3299 fs_reg orig_dest
= dest
;
3300 enum brw_reg_type type
= dest
.type
;
3302 /* Special case fields in the VUE header */
3303 if (base
== VARYING_SLOT_LAYER
)
3305 else if (base
== VARYING_SLOT_VIEWPORT
)
3308 if (nir_dest_bit_size(instr
->dest
) == 64) {
3309 /* const_index is in 32-bit type size units that could not be aligned
3310 * with DF. We need to read the double vector as if it was a float
3311 * vector of twice the number of components to fetch the right data.
3313 type
= BRW_REGISTER_TYPE_F
;
3314 num_components
*= 2;
3315 dest
= bld
.vgrf(type
, num_components
);
3318 for (unsigned int i
= 0; i
< num_components
; i
++) {
3319 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3320 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3323 if (nir_dest_bit_size(instr
->dest
) == 64) {
3324 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3325 instr
->num_components
);
3330 case nir_intrinsic_load_barycentric_pixel
:
3331 case nir_intrinsic_load_barycentric_centroid
:
3332 case nir_intrinsic_load_barycentric_sample
:
3333 /* Do nothing - load_interpolated_input handling will handle it later. */
3336 case nir_intrinsic_load_barycentric_at_sample
: {
3337 const glsl_interp_mode interpolation
=
3338 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3340 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3343 unsigned msg_data
= const_sample
->i32
[0] << 4;
3345 emit_pixel_interpolater_send(bld
,
3346 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3349 brw_imm_ud(msg_data
),
3352 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3353 BRW_REGISTER_TYPE_UD
);
3355 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3356 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3357 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3358 bld
.exec_all().group(1, 0)
3359 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3360 emit_pixel_interpolater_send(bld
,
3361 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3367 /* Make a loop that sends a message to the pixel interpolater
3368 * for the sample number in each live channel. If there are
3369 * multiple channels with the same sample number then these
3370 * will be handled simultaneously with a single interation of
3373 bld
.emit(BRW_OPCODE_DO
);
3375 /* Get the next live sample number into sample_id_reg */
3376 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3378 /* Set the flag register so that we can perform the send
3379 * message on all channels that have the same sample number
3381 bld
.CMP(bld
.null_reg_ud(),
3382 sample_src
, sample_id
,
3383 BRW_CONDITIONAL_EQ
);
3384 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3385 bld
.exec_all().group(1, 0)
3386 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3388 emit_pixel_interpolater_send(bld
,
3389 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3392 component(msg_data
, 0),
3394 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3396 /* Continue the loop if there are any live channels left */
3397 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3399 bld
.emit(BRW_OPCODE_WHILE
));
3405 case nir_intrinsic_load_barycentric_at_offset
: {
3406 const glsl_interp_mode interpolation
=
3407 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3409 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3412 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3413 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3415 emit_pixel_interpolater_send(bld
,
3416 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3419 brw_imm_ud(off_x
| (off_y
<< 4)),
3422 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3423 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3424 BRW_REGISTER_TYPE_F
);
3425 for (int i
= 0; i
< 2; i
++) {
3426 fs_reg temp
= vgrf(glsl_type::float_type
);
3427 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3428 fs_reg itemp
= vgrf(glsl_type::int_type
);
3430 bld
.MOV(itemp
, temp
);
3432 /* Clamp the upper end of the range to +7/16.
3433 * ARB_gpu_shader5 requires that we support a maximum offset
3434 * of +0.5, which isn't representable in a S0.4 value -- if
3435 * we didn't clamp it, we'd end up with -8/16, which is the
3436 * opposite of what the shader author wanted.
3438 * This is legal due to ARB_gpu_shader5's quantization
3441 * "Not all values of <offset> may be supported; x and y
3442 * offsets may be rounded to fixed-point values with the
3443 * number of fraction bits given by the
3444 * implementation-dependent constant
3445 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3447 set_condmod(BRW_CONDITIONAL_L
,
3448 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3451 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3452 emit_pixel_interpolater_send(bld
,
3462 case nir_intrinsic_load_interpolated_input
: {
3463 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3464 emit_fragcoord_interpolation(dest
);
3468 assert(instr
->src
[0].ssa
&&
3469 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3470 nir_intrinsic_instr
*bary_intrinsic
=
3471 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3472 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3473 enum glsl_interp_mode interp_mode
=
3474 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3477 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3478 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3479 /* Use the result of the PI message */
3480 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3482 /* Use the delta_xy values computed from the payload */
3483 enum brw_barycentric_mode bary
=
3484 brw_barycentric_mode(interp_mode
, bary_intrin
);
3486 dst_xy
= this->delta_xy
[bary
];
3489 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3491 component(interp_reg(nir_intrinsic_base(instr
),
3492 nir_intrinsic_component(instr
) + i
), 0);
3493 interp
.type
= BRW_REGISTER_TYPE_F
;
3494 dest
.type
= BRW_REGISTER_TYPE_F
;
3496 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3497 fs_reg tmp
= vgrf(glsl_type::float_type
);
3498 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3499 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3501 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3508 nir_emit_intrinsic(bld
, instr
);
3514 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3516 const nir_const_value
*const val
= nir_src_as_const_value(instr
->src
[src
]);
3519 if (val
->i32
[0] == 1)
3521 else if (val
->i32
[0] == -1)
3529 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3530 nir_intrinsic_instr
*instr
)
3532 assert(stage
== MESA_SHADER_COMPUTE
);
3533 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3536 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3537 dest
= get_nir_dest(instr
->dest
);
3539 switch (instr
->intrinsic
) {
3540 case nir_intrinsic_barrier
:
3542 cs_prog_data
->uses_barrier
= true;
3545 case nir_intrinsic_load_subgroup_id
:
3546 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3549 case nir_intrinsic_load_local_invocation_id
:
3550 case nir_intrinsic_load_work_group_id
: {
3551 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3552 fs_reg val
= nir_system_values
[sv
];
3553 assert(val
.file
!= BAD_FILE
);
3554 dest
.type
= val
.type
;
3555 for (unsigned i
= 0; i
< 3; i
++)
3556 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3560 case nir_intrinsic_load_num_work_groups
: {
3561 const unsigned surface
=
3562 cs_prog_data
->binding_table
.work_groups_start
;
3564 cs_prog_data
->uses_num_work_groups
= true;
3566 fs_reg surf_index
= brw_imm_ud(surface
);
3567 brw_mark_surface_used(prog_data
, surface
);
3569 /* Read the 3 GLuint components of gl_NumWorkGroups */
3570 for (unsigned i
= 0; i
< 3; i
++) {
3571 fs_reg read_result
=
3572 emit_untyped_read(bld
, surf_index
,
3574 1 /* dims */, 1 /* size */,
3575 BRW_PREDICATE_NONE
);
3576 read_result
.type
= dest
.type
;
3577 bld
.MOV(dest
, read_result
);
3578 dest
= offset(dest
, bld
, 1);
3583 case nir_intrinsic_shared_atomic_add
:
3584 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3586 case nir_intrinsic_shared_atomic_imin
:
3587 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3589 case nir_intrinsic_shared_atomic_umin
:
3590 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3592 case nir_intrinsic_shared_atomic_imax
:
3593 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3595 case nir_intrinsic_shared_atomic_umax
:
3596 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3598 case nir_intrinsic_shared_atomic_and
:
3599 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3601 case nir_intrinsic_shared_atomic_or
:
3602 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3604 case nir_intrinsic_shared_atomic_xor
:
3605 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3607 case nir_intrinsic_shared_atomic_exchange
:
3608 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3610 case nir_intrinsic_shared_atomic_comp_swap
:
3611 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3613 case nir_intrinsic_shared_atomic_fmin
:
3614 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3616 case nir_intrinsic_shared_atomic_fmax
:
3617 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3619 case nir_intrinsic_shared_atomic_fcomp_swap
:
3620 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3623 case nir_intrinsic_load_shared
: {
3624 assert(devinfo
->gen
>= 7);
3626 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3628 /* Get the offset to read from */
3630 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3632 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3634 offset_reg
= vgrf(glsl_type::uint_type
);
3636 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3637 brw_imm_ud(instr
->const_index
[0]));
3640 /* Read the vector */
3641 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3642 instr
->num_components
);
3646 case nir_intrinsic_store_shared
: {
3647 assert(devinfo
->gen
>= 7);
3650 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3653 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3656 unsigned writemask
= instr
->const_index
[1];
3658 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3659 * since the untyped writes below operate in units of 32-bits, which
3660 * means that we need to write twice as many components each time.
3661 * Also, we have to suffle 64-bit data to be in the appropriate layout
3662 * expected by our 32-bit write messages.
3664 unsigned type_size
= 4;
3665 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3667 val_reg
= shuffle_for_32bit_write(bld
, val_reg
, 0,
3668 instr
->num_components
);
3671 unsigned type_slots
= type_size
/ 4;
3673 /* Combine groups of consecutive enabled channels in one write
3674 * message. We use ffs to find the first enabled channel and then ffs on
3675 * the bit-inverse, down-shifted writemask to determine the length of
3676 * the block of enabled bits.
3679 unsigned first_component
= ffs(writemask
) - 1;
3680 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3682 /* We can't write more than 2 64-bit components at once. Limit the
3683 * length of the write to what we can do and let the next iteration
3687 length
= MIN2(2, length
);
3690 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3692 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3693 type_size
* first_component
);
3695 offset_reg
= vgrf(glsl_type::uint_type
);
3697 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3698 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3701 emit_untyped_write(bld
, surf_index
, offset_reg
,
3702 offset(val_reg
, bld
, first_component
* type_slots
),
3703 1 /* dims */, length
* type_slots
,
3704 BRW_PREDICATE_NONE
);
3706 /* Clear the bits in the writemask that we just wrote, then try
3707 * again to see if more channels are left.
3709 writemask
&= (15 << (first_component
+ length
));
3716 nir_emit_intrinsic(bld
, instr
);
3722 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3723 nir_op op
, brw_reg_type type
)
3725 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3726 switch (type_sz(type
)) {
3728 assert(type
!= BRW_REGISTER_TYPE_HF
);
3729 return retype(brw_imm_uw(value
.u16
[0]), type
);
3731 return retype(brw_imm_ud(value
.u32
[0]), type
);
3733 if (type
== BRW_REGISTER_TYPE_DF
)
3734 return setup_imm_df(bld
, value
.f64
[0]);
3736 return retype(brw_imm_u64(value
.u64
[0]), type
);
3738 unreachable("Invalid type size");
3743 brw_op_for_nir_reduction_op(nir_op op
)
3746 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3747 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3748 case nir_op_imul
: return BRW_OPCODE_MUL
;
3749 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3750 case nir_op_imin
: return BRW_OPCODE_SEL
;
3751 case nir_op_umin
: return BRW_OPCODE_SEL
;
3752 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3753 case nir_op_imax
: return BRW_OPCODE_SEL
;
3754 case nir_op_umax
: return BRW_OPCODE_SEL
;
3755 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3756 case nir_op_iand
: return BRW_OPCODE_AND
;
3757 case nir_op_ior
: return BRW_OPCODE_OR
;
3758 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3760 unreachable("Invalid reduction operation");
3764 static brw_conditional_mod
3765 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3768 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3769 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3770 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3771 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3772 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3773 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3774 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3775 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3776 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3777 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3778 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3779 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3780 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3782 unreachable("Invalid reduction operation");
3787 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3788 nir_intrinsic_instr
*instr
)
3790 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3792 if (stage_prog_data
->binding_table
.image_start
> 0) {
3793 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3794 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3796 bld
.ADD(image
, image
,
3797 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3801 return bld
.emit_uniformize(image
);
3805 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3807 switch (nir_intrinsic_image_dim(instr
)) {
3808 case GLSL_SAMPLER_DIM_1D
:
3809 return 1 + nir_intrinsic_image_array(instr
);
3810 case GLSL_SAMPLER_DIM_2D
:
3811 case GLSL_SAMPLER_DIM_RECT
:
3812 return 2 + nir_intrinsic_image_array(instr
);
3813 case GLSL_SAMPLER_DIM_3D
:
3814 case GLSL_SAMPLER_DIM_CUBE
:
3816 case GLSL_SAMPLER_DIM_BUF
:
3819 unreachable("Invalid image dimension");
3824 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3827 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3828 dest
= get_nir_dest(instr
->dest
);
3830 switch (instr
->intrinsic
) {
3831 case nir_intrinsic_image_load
:
3832 case nir_intrinsic_image_store
:
3833 case nir_intrinsic_image_atomic_add
:
3834 case nir_intrinsic_image_atomic_min
:
3835 case nir_intrinsic_image_atomic_max
:
3836 case nir_intrinsic_image_atomic_and
:
3837 case nir_intrinsic_image_atomic_or
:
3838 case nir_intrinsic_image_atomic_xor
:
3839 case nir_intrinsic_image_atomic_exchange
:
3840 case nir_intrinsic_image_atomic_comp_swap
: {
3841 if (stage
== MESA_SHADER_FRAGMENT
&&
3842 instr
->intrinsic
!= nir_intrinsic_image_load
)
3843 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3845 /* Get some metadata from the image intrinsic. */
3846 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3847 const unsigned dims
= image_intrinsic_coord_components(instr
);
3848 const GLenum format
= nir_intrinsic_format(instr
);
3849 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3851 /* Get the arguments of the image intrinsic. */
3852 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3853 const fs_reg coords
= retype(get_nir_src(instr
->src
[1]),
3854 BRW_REGISTER_TYPE_UD
);
3857 /* Emit an image load, store or atomic op. */
3858 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3859 tmp
= emit_typed_read(bld
, image
, coords
, dims
,
3860 instr
->num_components
);
3861 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3862 const fs_reg src0
= get_nir_src(instr
->src
[3]);
3863 emit_typed_write(bld
, image
, coords
, src0
, dims
,
3864 instr
->num_components
);
3867 unsigned num_srcs
= info
->num_srcs
;
3869 switch (instr
->intrinsic
) {
3870 case nir_intrinsic_image_atomic_add
:
3871 assert(num_srcs
== 4);
3873 op
= get_op_for_atomic_add(instr
, 3);
3875 if (op
!= BRW_AOP_ADD
)
3878 case nir_intrinsic_image_atomic_min
:
3879 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3880 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3882 case nir_intrinsic_image_atomic_max
:
3883 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3884 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3886 case nir_intrinsic_image_atomic_and
:
3889 case nir_intrinsic_image_atomic_or
:
3892 case nir_intrinsic_image_atomic_xor
:
3895 case nir_intrinsic_image_atomic_exchange
:
3898 case nir_intrinsic_image_atomic_comp_swap
:
3902 unreachable("Not reachable.");
3905 const fs_reg src0
= (num_srcs
>= 4 ?
3906 get_nir_src(instr
->src
[3]) : fs_reg());
3907 const fs_reg src1
= (num_srcs
>= 5 ?
3908 get_nir_src(instr
->src
[4]) : fs_reg());
3910 tmp
= emit_typed_atomic(bld
, image
, coords
, src0
, src1
, dims
, 1, op
);
3913 /* Assign the result. */
3914 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3915 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3916 offset(tmp
, bld
, c
));
3921 case nir_intrinsic_image_load_raw_intel
: {
3922 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3923 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3924 BRW_REGISTER_TYPE_UD
);
3926 fs_reg tmp
= emit_untyped_read(bld
, image
, addr
, 1,
3927 instr
->num_components
);
3929 for (unsigned c
= 0; c
< instr
->num_components
; ++c
) {
3930 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3931 offset(tmp
, bld
, c
));
3936 case nir_intrinsic_image_store_raw_intel
: {
3937 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3938 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3939 BRW_REGISTER_TYPE_UD
);
3940 const fs_reg data
= retype(get_nir_src(instr
->src
[2]),
3941 BRW_REGISTER_TYPE_UD
);
3943 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3945 emit_untyped_write(bld
, image
, addr
, data
, 1,
3946 instr
->num_components
);
3950 case nir_intrinsic_group_memory_barrier
:
3951 case nir_intrinsic_memory_barrier_shared
:
3952 case nir_intrinsic_memory_barrier_atomic_counter
:
3953 case nir_intrinsic_memory_barrier_buffer
:
3954 case nir_intrinsic_memory_barrier_image
:
3955 case nir_intrinsic_memory_barrier
: {
3956 const fs_builder ubld
= bld
.group(8, 0);
3957 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3958 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3959 ->size_written
= 2 * REG_SIZE
;
3963 case nir_intrinsic_shader_clock
: {
3964 /* We cannot do anything if there is an event, so ignore it for now */
3965 const fs_reg shader_clock
= get_timestamp(bld
);
3966 const fs_reg srcs
[] = { component(shader_clock
, 0),
3967 component(shader_clock
, 1) };
3968 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3972 case nir_intrinsic_image_samples
:
3973 /* The driver does not support multi-sampled images. */
3974 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3977 case nir_intrinsic_load_uniform
: {
3978 /* Offsets are in bytes but they should always aligned to
3981 assert(instr
->const_index
[0] % 4 == 0 ||
3982 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3984 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3986 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3988 assert(const_offset
->u32
[0] % type_sz(dest
.type
) == 0);
3989 /* For 16-bit types we add the module of the const_index[0]
3990 * offset to access to not 32-bit aligned element
3992 src
.offset
= const_offset
->u32
[0] + instr
->const_index
[0] % 4;
3994 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3995 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3998 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3999 BRW_REGISTER_TYPE_UD
);
4001 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4002 * go past the end of the uniform. In order to keep the n'th
4003 * component from running past, we subtract off the size of all but
4004 * one component of the vector.
4006 assert(instr
->const_index
[1] >=
4007 instr
->num_components
* (int) type_sz(dest
.type
));
4008 unsigned read_size
= instr
->const_index
[1] -
4009 (instr
->num_components
- 1) * type_sz(dest
.type
);
4011 bool supports_64bit_indirects
=
4012 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4014 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4015 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4016 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4017 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4018 indirect
, brw_imm_ud(read_size
));
4021 const unsigned num_mov_indirects
=
4022 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4023 /* We read a little bit less per MOV INDIRECT, as they are now
4024 * 32-bits ones instead of 64-bit. Fix read_size then.
4026 const unsigned read_size_32bit
= read_size
-
4027 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4028 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4029 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4030 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4031 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4032 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4033 indirect
, brw_imm_ud(read_size_32bit
));
4041 case nir_intrinsic_load_ubo
: {
4042 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4046 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4047 const_index
->u32
[0];
4048 surf_index
= brw_imm_ud(index
);
4049 brw_mark_surface_used(prog_data
, index
);
4051 /* The block index is not a constant. Evaluate the index expression
4052 * per-channel and add the base UBO index; we have to select a value
4053 * from any live channel.
4055 surf_index
= vgrf(glsl_type::uint_type
);
4056 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4057 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4058 surf_index
= bld
.emit_uniformize(surf_index
);
4060 /* Assume this may touch any UBO. It would be nice to provide
4061 * a tighter bound, but the array information is already lowered away.
4063 brw_mark_surface_used(prog_data
,
4064 stage_prog_data
->binding_table
.ubo_start
+
4065 nir
->info
.num_ubos
- 1);
4068 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4069 if (const_offset
== NULL
) {
4070 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4071 BRW_REGISTER_TYPE_UD
);
4073 for (int i
= 0; i
< instr
->num_components
; i
++)
4074 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4075 base_offset
, i
* type_sz(dest
.type
));
4077 /* Even if we are loading doubles, a pull constant load will load
4078 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4079 * need to load a full dvec4 we will have to emit 2 loads. This is
4080 * similar to demote_pull_constants(), except that in that case we
4081 * see individual accesses to each component of the vector and then
4082 * we let CSE deal with duplicate loads. Here we see a vector access
4083 * and we have to split it if necessary.
4085 const unsigned type_size
= type_sz(dest
.type
);
4087 /* See if we've selected this as a push constant candidate */
4089 const unsigned ubo_block
= const_index
->u32
[0];
4090 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
4093 for (int i
= 0; i
< 4; i
++) {
4094 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4095 if (range
->block
== ubo_block
&&
4096 offset_256b
>= range
->start
&&
4097 offset_256b
< range
->start
+ range
->length
) {
4099 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4100 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
4105 if (push_reg
.file
!= BAD_FILE
) {
4106 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4107 bld
.MOV(offset(dest
, bld
, i
),
4108 byte_offset(push_reg
, i
* type_size
));
4114 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4115 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4116 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4118 for (unsigned c
= 0; c
< instr
->num_components
;) {
4119 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4120 /* Number of usable components in the next block-aligned load. */
4121 const unsigned count
= MIN2(instr
->num_components
- c
,
4122 (block_sz
- base
% block_sz
) / type_size
);
4124 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4125 packed_consts
, surf_index
,
4126 brw_imm_ud(base
& ~(block_sz
- 1)));
4128 const fs_reg consts
=
4129 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4132 for (unsigned d
= 0; d
< count
; d
++)
4133 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4141 case nir_intrinsic_load_ssbo
: {
4142 assert(devinfo
->gen
>= 7);
4144 nir_const_value
*const_uniform_block
=
4145 nir_src_as_const_value(instr
->src
[0]);
4148 if (const_uniform_block
) {
4149 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4150 const_uniform_block
->u32
[0];
4151 surf_index
= brw_imm_ud(index
);
4152 brw_mark_surface_used(prog_data
, index
);
4154 surf_index
= vgrf(glsl_type::uint_type
);
4155 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4156 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4158 /* Assume this may touch any UBO. It would be nice to provide
4159 * a tighter bound, but the array information is already lowered away.
4161 brw_mark_surface_used(prog_data
,
4162 stage_prog_data
->binding_table
.ssbo_start
+
4163 nir
->info
.num_ssbos
- 1);
4167 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4169 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4171 offset_reg
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
);
4174 /* Read the vector */
4175 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4176 instr
->num_components
);
4181 case nir_intrinsic_store_ssbo
: {
4182 assert(devinfo
->gen
>= 7);
4184 if (stage
== MESA_SHADER_FRAGMENT
)
4185 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4189 nir_const_value
*const_uniform_block
=
4190 nir_src_as_const_value(instr
->src
[1]);
4191 if (const_uniform_block
) {
4192 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4193 const_uniform_block
->u32
[0];
4194 surf_index
= brw_imm_ud(index
);
4195 brw_mark_surface_used(prog_data
, index
);
4197 surf_index
= vgrf(glsl_type::uint_type
);
4198 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4199 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4201 brw_mark_surface_used(prog_data
,
4202 stage_prog_data
->binding_table
.ssbo_start
+
4203 nir
->info
.num_ssbos
- 1);
4207 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4210 unsigned writemask
= instr
->const_index
[0];
4212 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4213 * since the untyped writes below operate in units of 32-bits, which
4214 * means that we need to write twice as many components each time.
4215 * Also, we have to suffle 64-bit data to be in the appropriate layout
4216 * expected by our 32-bit write messages.
4218 unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4219 unsigned type_size
= bit_size
/ 8;
4221 /* Combine groups of consecutive enabled channels in one write
4222 * message. We use ffs to find the first enabled channel and then ffs on
4223 * the bit-inverse, down-shifted writemask to determine the num_components
4224 * of the block of enabled bits.
4227 unsigned first_component
= ffs(writemask
) - 1;
4228 unsigned num_components
= ffs(~(writemask
>> first_component
)) - 1;
4229 fs_reg write_src
= offset(val_reg
, bld
, first_component
);
4231 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4233 if (type_size
> 4) {
4234 /* We can't write more than 2 64-bit components at once. Limit
4235 * the num_components of the write to what we can do and let the next
4236 * iteration handle the rest.
4238 num_components
= MIN2(2, num_components
);
4239 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4241 } else if (type_size
< 4) {
4242 /* For 16-bit types we pack two consecutive values into a 32-bit
4243 * word and use an untyped write message. For single values or not
4244 * 32-bit-aligned we need to use byte-scattered writes because
4245 * untyped writes works with 32-bit components with 32-bit
4246 * alignment. byte_scattered_write messages only support one
4247 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4248 * could be enabled we can not guarantee that not constant offsets
4249 * to be 32-bit aligned for 16-bit types. For example an array, of
4250 * 16-bit vec3 with array element stride of 6.
4252 * In the case of 32-bit aligned constant offsets if there is
4253 * a 3-components vector we submit one untyped-write message
4254 * of 32-bit (first two components), and one byte-scattered
4255 * write message (the last component).
4258 if ( !const_offset
|| ((const_offset
->u32
[0] +
4259 type_size
* first_component
) % 4)) {
4260 /* If we use a .yz writemask we also need to emit 2
4261 * byte-scattered write messages because of y-component not
4262 * being aligned to 32-bit.
4265 } else if (num_components
* type_size
> 4 &&
4266 (num_components
* type_size
% 4)) {
4267 /* If the pending components size is not a multiple of 4 bytes
4268 * we left the not aligned components for following emits of
4269 * length == 1 with byte_scattered_write.
4271 num_components
-= (num_components
* type_size
% 4) / type_size
;
4272 } else if (num_components
* type_size
< 4) {
4275 /* For num_components == 1 we are also shuffling the component
4276 * because byte scattered writes of 16-bit need values to be dword
4277 * aligned. Shuffling only one component would be the same as
4280 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4287 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4288 type_size
* first_component
);
4290 offset_reg
= vgrf(glsl_type::uint_type
);
4292 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4293 brw_imm_ud(type_size
* first_component
));
4296 if (type_size
< 4 && num_components
== 1) {
4297 /* Untyped Surface messages have a fixed 32-bit size, so we need
4298 * to rely on byte scattered in order to write 16-bit elements.
4299 * The byte_scattered_write message needs that every written 16-bit
4300 * type to be aligned 32-bits (stride=2).
4302 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4306 BRW_PREDICATE_NONE
);
4308 assert(num_components
* type_size
<= 16);
4309 assert((num_components
* type_size
) % 4 == 0);
4310 assert(offset_reg
.file
!= BRW_IMMEDIATE_VALUE
||
4311 offset_reg
.ud
% 4 == 0);
4312 unsigned num_slots
= (num_components
* type_size
) / 4;
4314 emit_untyped_write(bld
, surf_index
, offset_reg
,
4316 1 /* dims */, num_slots
,
4317 BRW_PREDICATE_NONE
);
4320 /* Clear the bits in the writemask that we just wrote, then try
4321 * again to see if more channels are left.
4323 writemask
&= (15 << (first_component
+ num_components
));
4328 case nir_intrinsic_store_output
: {
4329 fs_reg src
= get_nir_src(instr
->src
[0]);
4331 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4332 assert(const_offset
&& "Indirect output stores not allowed");
4334 unsigned num_components
= instr
->num_components
;
4335 unsigned first_component
= nir_intrinsic_component(instr
);
4336 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4337 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4338 num_components
*= 2;
4341 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4342 4 * const_offset
->u32
[0]), src
.type
);
4343 for (unsigned j
= 0; j
< num_components
; j
++) {
4344 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4345 offset(src
, bld
, j
));
4350 case nir_intrinsic_ssbo_atomic_add
:
4351 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4353 case nir_intrinsic_ssbo_atomic_imin
:
4354 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4356 case nir_intrinsic_ssbo_atomic_umin
:
4357 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4359 case nir_intrinsic_ssbo_atomic_imax
:
4360 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4362 case nir_intrinsic_ssbo_atomic_umax
:
4363 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4365 case nir_intrinsic_ssbo_atomic_and
:
4366 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4368 case nir_intrinsic_ssbo_atomic_or
:
4369 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4371 case nir_intrinsic_ssbo_atomic_xor
:
4372 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4374 case nir_intrinsic_ssbo_atomic_exchange
:
4375 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4377 case nir_intrinsic_ssbo_atomic_comp_swap
:
4378 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4380 case nir_intrinsic_ssbo_atomic_fmin
:
4381 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4383 case nir_intrinsic_ssbo_atomic_fmax
:
4384 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4386 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4387 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4390 case nir_intrinsic_get_buffer_size
: {
4391 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4392 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4394 /* A resinfo's sampler message is used to get the buffer size. The
4395 * SIMD8's writeback message consists of four registers and SIMD16's
4396 * writeback message consists of 8 destination registers (two per each
4397 * component). Because we are only interested on the first channel of
4398 * the first returned component, where resinfo returns the buffer size
4399 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4400 * the dispatch width.
4402 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4403 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4404 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4407 ubld
.MOV(src_payload
, brw_imm_d(0));
4409 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4410 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4411 src_payload
, brw_imm_ud(index
));
4412 inst
->header_size
= 0;
4414 inst
->size_written
= 4 * REG_SIZE
;
4416 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4418 * "Out-of-bounds checking is always performed at a DWord granularity. If
4419 * any part of the DWord is out-of-bounds then the whole DWord is
4420 * considered out-of-bounds."
4422 * This implies that types with size smaller than 4-bytes need to be
4423 * padded if they don't complete the last dword of the buffer. But as we
4424 * need to maintain the original size we need to reverse the padding
4425 * calculation to return the correct size to know the number of elements
4426 * of an unsized array. As we stored in the last two bits of the surface
4427 * size the needed padding for the buffer, we calculate here the
4428 * original buffer_size reversing the surface_size calculation:
4430 * surface_size = isl_align(buffer_size, 4) +
4431 * (isl_align(buffer_size) - buffer_size)
4433 * buffer_size = surface_size & ~3 - surface_size & 3
4436 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4437 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4438 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4440 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4441 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4442 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4444 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4446 brw_mark_surface_used(prog_data
, index
);
4450 case nir_intrinsic_load_subgroup_invocation
:
4451 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4452 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4455 case nir_intrinsic_load_subgroup_eq_mask
:
4456 case nir_intrinsic_load_subgroup_ge_mask
:
4457 case nir_intrinsic_load_subgroup_gt_mask
:
4458 case nir_intrinsic_load_subgroup_le_mask
:
4459 case nir_intrinsic_load_subgroup_lt_mask
:
4460 unreachable("not reached");
4462 case nir_intrinsic_vote_any
: {
4463 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4465 /* The any/all predicates do not consider channel enables. To prevent
4466 * dead channels from affecting the result, we initialize the flag with
4467 * with the identity value for the logical operation.
4469 if (dispatch_width
== 32) {
4470 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4471 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4474 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4476 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4478 /* For some reason, the any/all predicates don't work properly with
4479 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4480 * doesn't read the correct subset of the flag register and you end up
4481 * getting garbage in the second half. Work around this by using a pair
4482 * of 1-wide MOVs and scattering the result.
4484 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4485 ubld
.MOV(res1
, brw_imm_d(0));
4486 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4487 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4488 BRW_PREDICATE_ALIGN1_ANY32H
,
4489 ubld
.MOV(res1
, brw_imm_d(-1)));
4491 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4494 case nir_intrinsic_vote_all
: {
4495 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4497 /* The any/all predicates do not consider channel enables. To prevent
4498 * dead channels from affecting the result, we initialize the flag with
4499 * with the identity value for the logical operation.
4501 if (dispatch_width
== 32) {
4502 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4503 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4504 brw_imm_ud(0xffffffff));
4506 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4508 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4510 /* For some reason, the any/all predicates don't work properly with
4511 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4512 * doesn't read the correct subset of the flag register and you end up
4513 * getting garbage in the second half. Work around this by using a pair
4514 * of 1-wide MOVs and scattering the result.
4516 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4517 ubld
.MOV(res1
, brw_imm_d(0));
4518 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4519 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4520 BRW_PREDICATE_ALIGN1_ALL32H
,
4521 ubld
.MOV(res1
, brw_imm_d(-1)));
4523 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4526 case nir_intrinsic_vote_feq
:
4527 case nir_intrinsic_vote_ieq
: {
4528 fs_reg value
= get_nir_src(instr
->src
[0]);
4529 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4530 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4531 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4534 fs_reg uniformized
= bld
.emit_uniformize(value
);
4535 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4537 /* The any/all predicates do not consider channel enables. To prevent
4538 * dead channels from affecting the result, we initialize the flag with
4539 * with the identity value for the logical operation.
4541 if (dispatch_width
== 32) {
4542 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4543 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4544 brw_imm_ud(0xffffffff));
4546 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4548 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4550 /* For some reason, the any/all predicates don't work properly with
4551 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4552 * doesn't read the correct subset of the flag register and you end up
4553 * getting garbage in the second half. Work around this by using a pair
4554 * of 1-wide MOVs and scattering the result.
4556 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4557 ubld
.MOV(res1
, brw_imm_d(0));
4558 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4559 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4560 BRW_PREDICATE_ALIGN1_ALL32H
,
4561 ubld
.MOV(res1
, brw_imm_d(-1)));
4563 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4567 case nir_intrinsic_ballot
: {
4568 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4569 BRW_REGISTER_TYPE_UD
);
4570 struct brw_reg flag
= brw_flag_reg(0, 0);
4571 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4572 * as f0.0. This is a problem for fragment programs as we currently use
4573 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4574 * programs yet so this isn't a problem. When we do, something will
4577 if (dispatch_width
== 32)
4578 flag
.type
= BRW_REGISTER_TYPE_UD
;
4580 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4581 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4583 if (instr
->dest
.ssa
.bit_size
> 32) {
4584 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4586 dest
.type
= BRW_REGISTER_TYPE_UD
;
4588 bld
.MOV(dest
, flag
);
4592 case nir_intrinsic_read_invocation
: {
4593 const fs_reg value
= get_nir_src(instr
->src
[0]);
4594 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4595 fs_reg tmp
= bld
.vgrf(value
.type
);
4597 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4598 bld
.emit_uniformize(invocation
));
4600 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4604 case nir_intrinsic_read_first_invocation
: {
4605 const fs_reg value
= get_nir_src(instr
->src
[0]);
4606 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4610 case nir_intrinsic_shuffle
: {
4611 const fs_reg value
= get_nir_src(instr
->src
[0]);
4612 const fs_reg index
= get_nir_src(instr
->src
[1]);
4614 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4618 case nir_intrinsic_first_invocation
: {
4619 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4620 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4621 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4622 fs_reg(component(tmp
, 0)));
4626 case nir_intrinsic_quad_broadcast
: {
4627 const fs_reg value
= get_nir_src(instr
->src
[0]);
4628 nir_const_value
*index
= nir_src_as_const_value(instr
->src
[1]);
4629 assert(nir_src_bit_size(instr
->src
[1]) == 32);
4631 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4632 value
, brw_imm_ud(index
->u32
[0]), brw_imm_ud(4));
4636 case nir_intrinsic_quad_swap_horizontal
: {
4637 const fs_reg value
= get_nir_src(instr
->src
[0]);
4638 const fs_reg tmp
= bld
.vgrf(value
.type
);
4639 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4641 const fs_reg src_left
= horiz_stride(value
, 2);
4642 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4643 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4644 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4646 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4648 * "When source or destination datatype is 64b or operation is
4649 * integer DWord multiply, regioning in Align1 must follow
4654 * 3. Source and Destination offset must be the same, except
4655 * the case of scalar source."
4657 * In order to work around this, we have to emit two 32-bit MOVs instead
4658 * of a single 64-bit MOV to do the shuffle.
4660 if (type_sz(value
.type
) > 4 &&
4661 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4662 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4663 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4664 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4665 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4666 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4667 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4668 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4669 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4671 ubld
.MOV(tmp_left
, src_right
);
4672 ubld
.MOV(tmp_right
, src_left
);
4674 bld
.MOV(retype(dest
, value
.type
), tmp
);
4678 case nir_intrinsic_quad_swap_vertical
: {
4679 const fs_reg value
= get_nir_src(instr
->src
[0]);
4680 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4681 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4682 const fs_reg tmp
= bld
.vgrf(value
.type
);
4683 const fs_builder ubld
= bld
.exec_all();
4684 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4685 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4686 bld
.MOV(retype(dest
, value
.type
), tmp
);
4688 /* For larger data types, we have to either emit dispatch_width many
4689 * MOVs or else fall back to doing indirects.
4691 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4692 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4694 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4699 case nir_intrinsic_quad_swap_diagonal
: {
4700 const fs_reg value
= get_nir_src(instr
->src
[0]);
4701 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4702 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4703 const fs_reg tmp
= bld
.vgrf(value
.type
);
4704 const fs_builder ubld
= bld
.exec_all();
4705 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4706 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4707 bld
.MOV(retype(dest
, value
.type
), tmp
);
4709 /* For larger data types, we have to either emit dispatch_width many
4710 * MOVs or else fall back to doing indirects.
4712 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4713 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4715 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4720 case nir_intrinsic_reduce
: {
4721 fs_reg src
= get_nir_src(instr
->src
[0]);
4722 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4723 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4724 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4725 cluster_size
= dispatch_width
;
4727 /* Figure out the source type */
4728 src
.type
= brw_type_for_nir_type(devinfo
,
4729 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4730 nir_src_bit_size(instr
->src
[0])));
4732 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4733 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4734 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4736 /* Set up a register for all of our scratching around and initialize it
4737 * to reduction operation's identity value.
4739 fs_reg scan
= bld
.vgrf(src
.type
);
4740 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4742 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4744 dest
.type
= src
.type
;
4745 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4746 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4747 * the distance between clusters is at least 2 GRFs. In this case,
4748 * we don't need the weird striding of the CLUSTER_BROADCAST
4749 * instruction and can just do regular MOVs.
4751 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4752 const unsigned groups
=
4753 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4754 const unsigned group_size
= dispatch_width
/ groups
;
4755 for (unsigned i
= 0; i
< groups
; i
++) {
4756 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4757 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4758 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4759 component(scan
, comp
));
4762 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4763 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4768 case nir_intrinsic_inclusive_scan
:
4769 case nir_intrinsic_exclusive_scan
: {
4770 fs_reg src
= get_nir_src(instr
->src
[0]);
4771 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4773 /* Figure out the source type */
4774 src
.type
= brw_type_for_nir_type(devinfo
,
4775 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4776 nir_src_bit_size(instr
->src
[0])));
4778 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4779 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4780 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4782 /* Set up a register for all of our scratching around and initialize it
4783 * to reduction operation's identity value.
4785 fs_reg scan
= bld
.vgrf(src
.type
);
4786 const fs_builder allbld
= bld
.exec_all();
4787 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4789 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4790 /* Exclusive scan is a bit harder because we have to do an annoying
4791 * shift of the contents before we can begin. To make things worse,
4792 * we can't do this with a normal stride; we have to use indirects.
4794 fs_reg shifted
= bld
.vgrf(src
.type
);
4795 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4796 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4798 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4799 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4803 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4805 bld
.MOV(retype(dest
, src
.type
), scan
);
4809 case nir_intrinsic_begin_fragment_shader_ordering
:
4810 case nir_intrinsic_begin_invocation_interlock
: {
4811 const fs_builder ubld
= bld
.group(8, 0);
4812 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4814 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4820 case nir_intrinsic_end_invocation_interlock
: {
4821 /* We don't need to do anything here */
4826 unreachable("unknown intrinsic");
4831 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4832 int op
, nir_intrinsic_instr
*instr
)
4834 if (stage
== MESA_SHADER_FRAGMENT
)
4835 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4838 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4839 dest
= get_nir_dest(instr
->dest
);
4842 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4843 if (const_surface
) {
4844 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4845 const_surface
->u32
[0];
4846 surface
= brw_imm_ud(surf_index
);
4847 brw_mark_surface_used(prog_data
, surf_index
);
4849 surface
= vgrf(glsl_type::uint_type
);
4850 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4851 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4853 /* Assume this may touch any SSBO. This is the same we do for other
4854 * UBO/SSBO accesses with non-constant surface.
4856 brw_mark_surface_used(prog_data
,
4857 stage_prog_data
->binding_table
.ssbo_start
+
4858 nir
->info
.num_ssbos
- 1);
4861 fs_reg offset
= get_nir_src(instr
->src
[1]);
4863 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4864 data1
= get_nir_src(instr
->src
[2]);
4866 if (op
== BRW_AOP_CMPWR
)
4867 data2
= get_nir_src(instr
->src
[3]);
4869 /* Emit the actual atomic operation */
4871 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4873 1 /* dims */, 1 /* rsize */,
4875 BRW_PREDICATE_NONE
);
4876 dest
.type
= atomic_result
.type
;
4877 bld
.MOV(dest
, atomic_result
);
4881 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4882 int op
, nir_intrinsic_instr
*instr
)
4884 if (stage
== MESA_SHADER_FRAGMENT
)
4885 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4888 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4889 dest
= get_nir_dest(instr
->dest
);
4892 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4893 if (const_surface
) {
4894 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4895 const_surface
->u32
[0];
4896 surface
= brw_imm_ud(surf_index
);
4897 brw_mark_surface_used(prog_data
, surf_index
);
4899 surface
= vgrf(glsl_type::uint_type
);
4900 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4901 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4903 /* Assume this may touch any SSBO. This is the same we do for other
4904 * UBO/SSBO accesses with non-constant surface.
4906 brw_mark_surface_used(prog_data
,
4907 stage_prog_data
->binding_table
.ssbo_start
+
4908 nir
->info
.num_ssbos
- 1);
4911 fs_reg offset
= get_nir_src(instr
->src
[1]);
4912 fs_reg data1
= get_nir_src(instr
->src
[2]);
4914 if (op
== BRW_AOP_FCMPWR
)
4915 data2
= get_nir_src(instr
->src
[3]);
4917 /* Emit the actual atomic operation */
4919 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4921 1 /* dims */, 1 /* rsize */,
4923 BRW_PREDICATE_NONE
);
4924 dest
.type
= atomic_result
.type
;
4925 bld
.MOV(dest
, atomic_result
);
4929 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4930 int op
, nir_intrinsic_instr
*instr
)
4933 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4934 dest
= get_nir_dest(instr
->dest
);
4936 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4939 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4940 data1
= get_nir_src(instr
->src
[1]);
4942 if (op
== BRW_AOP_CMPWR
)
4943 data2
= get_nir_src(instr
->src
[2]);
4945 /* Get the offset */
4946 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4948 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4950 offset
= vgrf(glsl_type::uint_type
);
4952 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4953 brw_imm_ud(instr
->const_index
[0]));
4956 /* Emit the actual atomic operation operation */
4958 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4960 1 /* dims */, 1 /* rsize */,
4962 BRW_PREDICATE_NONE
);
4963 dest
.type
= atomic_result
.type
;
4964 bld
.MOV(dest
, atomic_result
);
4968 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4969 int op
, nir_intrinsic_instr
*instr
)
4972 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4973 dest
= get_nir_dest(instr
->dest
);
4975 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4977 fs_reg data1
= get_nir_src(instr
->src
[1]);
4979 if (op
== BRW_AOP_FCMPWR
)
4980 data2
= get_nir_src(instr
->src
[2]);
4982 /* Get the offset */
4983 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4985 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4987 offset
= vgrf(glsl_type::uint_type
);
4989 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4990 brw_imm_ud(instr
->const_index
[0]));
4993 /* Emit the actual atomic operation operation */
4995 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4997 1 /* dims */, 1 /* rsize */,
4999 BRW_PREDICATE_NONE
);
5000 dest
.type
= atomic_result
.type
;
5001 bld
.MOV(dest
, atomic_result
);
5005 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5007 unsigned texture
= instr
->texture_index
;
5008 unsigned sampler
= instr
->sampler_index
;
5010 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5012 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5013 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5015 int lod_components
= 0;
5017 /* The hardware requires a LOD for buffer textures */
5018 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5019 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5021 uint32_t header_bits
= 0;
5022 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5023 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5024 switch (instr
->src
[i
].src_type
) {
5025 case nir_tex_src_bias
:
5026 srcs
[TEX_LOGICAL_SRC_LOD
] =
5027 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5029 case nir_tex_src_comparator
:
5030 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5032 case nir_tex_src_coord
:
5033 switch (instr
->op
) {
5035 case nir_texop_txf_ms
:
5036 case nir_texop_txf_ms_mcs
:
5037 case nir_texop_samples_identical
:
5038 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5041 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5045 case nir_tex_src_ddx
:
5046 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5047 lod_components
= nir_tex_instr_src_size(instr
, i
);
5049 case nir_tex_src_ddy
:
5050 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5052 case nir_tex_src_lod
:
5053 switch (instr
->op
) {
5055 srcs
[TEX_LOGICAL_SRC_LOD
] =
5056 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5059 srcs
[TEX_LOGICAL_SRC_LOD
] =
5060 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5063 srcs
[TEX_LOGICAL_SRC_LOD
] =
5064 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5068 case nir_tex_src_ms_index
:
5069 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5072 case nir_tex_src_offset
: {
5073 nir_const_value
*const_offset
=
5074 nir_src_as_const_value(instr
->src
[i
].src
);
5075 unsigned offset_bits
= 0;
5077 brw_texture_offset(const_offset
->i32
,
5078 nir_tex_instr_src_size(instr
, i
),
5080 header_bits
|= offset_bits
;
5082 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5083 retype(src
, BRW_REGISTER_TYPE_D
);
5088 case nir_tex_src_projector
:
5089 unreachable("should be lowered");
5091 case nir_tex_src_texture_offset
: {
5092 /* Figure out the highest possible texture index and mark it as used */
5093 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
5094 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
5095 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
5097 max_used
+= stage_prog_data
->binding_table
.texture_start
;
5099 brw_mark_surface_used(prog_data
, max_used
);
5101 /* Emit code to evaluate the actual indexing expression */
5102 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5103 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5104 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5108 case nir_tex_src_sampler_offset
: {
5109 /* Emit code to evaluate the actual indexing expression */
5110 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5111 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5112 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5116 case nir_tex_src_ms_mcs
:
5117 assert(instr
->op
== nir_texop_txf_ms
);
5118 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5121 case nir_tex_src_plane
: {
5122 nir_const_value
*const_plane
=
5123 nir_src_as_const_value(instr
->src
[i
].src
);
5124 const uint32_t plane
= const_plane
->u32
[0];
5125 const uint32_t texture_index
=
5126 instr
->texture_index
+
5127 stage_prog_data
->binding_table
.plane_start
[plane
] -
5128 stage_prog_data
->binding_table
.texture_start
;
5130 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5135 unreachable("unknown texture source");
5139 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5140 (instr
->op
== nir_texop_txf_ms
||
5141 instr
->op
== nir_texop_samples_identical
)) {
5142 if (devinfo
->gen
>= 7 &&
5143 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5144 srcs
[TEX_LOGICAL_SRC_MCS
] =
5145 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5146 instr
->coord_components
,
5147 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5149 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5153 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5154 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5157 switch (instr
->op
) {
5159 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5160 SHADER_OPCODE_TXL_LOGICAL
);
5163 opcode
= FS_OPCODE_TXB_LOGICAL
;
5166 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5169 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5172 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5174 case nir_texop_txf_ms
:
5175 if ((key_tex
->msaa_16
& (1 << sampler
)))
5176 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5178 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5180 case nir_texop_txf_ms_mcs
:
5181 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5183 case nir_texop_query_levels
:
5185 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5188 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5191 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5192 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5194 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5196 case nir_texop_texture_samples
:
5197 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5199 case nir_texop_samples_identical
: {
5200 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5202 /* If mcs is an immediate value, it means there is no MCS. In that case
5203 * just return false.
5205 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5206 bld
.MOV(dst
, brw_imm_ud(0u));
5207 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5208 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5209 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5210 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5211 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5213 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5214 BRW_CONDITIONAL_EQ
);
5219 unreachable("unknown texture opcode");
5222 if (instr
->op
== nir_texop_tg4
) {
5223 if (instr
->component
== 1 &&
5224 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5225 /* gather4 sampler is broken for green channel on RG32F --
5226 * we must ask for blue instead.
5228 header_bits
|= 2 << 16;
5230 header_bits
|= instr
->component
<< 16;
5234 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5235 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5236 inst
->offset
= header_bits
;
5238 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5239 if (devinfo
->gen
>= 9 &&
5240 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5241 unsigned write_mask
= instr
->dest
.is_ssa
?
5242 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5243 (1 << dest_size
) - 1;
5244 assert(write_mask
!= 0); /* dead code should have been eliminated */
5245 inst
->size_written
= util_last_bit(write_mask
) *
5246 inst
->dst
.component_size(inst
->exec_size
);
5248 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5251 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5252 inst
->shadow_compare
= true;
5254 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5255 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5258 for (unsigned i
= 0; i
< dest_size
; i
++)
5259 nir_dest
[i
] = offset(dst
, bld
, i
);
5261 if (instr
->op
== nir_texop_query_levels
) {
5262 /* # levels is in .w */
5263 nir_dest
[0] = offset(dst
, bld
, 3);
5264 } else if (instr
->op
== nir_texop_txs
&&
5265 dest_size
>= 3 && devinfo
->gen
< 7) {
5266 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5267 fs_reg depth
= offset(dst
, bld
, 2);
5268 nir_dest
[2] = vgrf(glsl_type::int_type
);
5269 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5272 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5276 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5278 switch (instr
->type
) {
5279 case nir_jump_break
:
5280 bld
.emit(BRW_OPCODE_BREAK
);
5282 case nir_jump_continue
:
5283 bld
.emit(BRW_OPCODE_CONTINUE
);
5285 case nir_jump_return
:
5287 unreachable("unknown jump");
5292 * This helper takes a source register and un/shuffles it into the destination
5295 * If source type size is smaller than destination type size the operation
5296 * needed is a component shuffle. The opposite case would be an unshuffle. If
5297 * source/destination type size is equal a shuffle is done that would be
5298 * equivalent to a simple MOV.
5300 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5301 * components .xyz 16-bit vector on SIMD8 would be.
5303 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5304 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5306 * This helper will return the following 2 32-bit components with the 16-bit
5309 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5310 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5312 * For unshuffle, the example would be the opposite, a 64-bit type source
5313 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5316 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5317 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5318 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5319 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5321 * The returned result would be the following 4 32-bit components unshuffled:
5323 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5324 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5325 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5326 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5328 * - Source and destination register must not be overlapped.
5329 * - components units are measured in terms of the smaller type between
5330 * source and destination because we are un/shuffling the smaller
5331 * components from/into the bigger ones.
5332 * - first_component parameter allows skipping source components.
5335 shuffle_src_to_dst(const fs_builder
&bld
,
5338 uint32_t first_component
,
5339 uint32_t components
)
5341 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5342 assert(!regions_overlap(dst
,
5343 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5344 offset(src
, bld
, first_component
),
5345 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5346 for (unsigned i
= 0; i
< components
; i
++) {
5347 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5348 offset(src
, bld
, i
+ first_component
));
5350 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5351 /* Source is shuffled into destination */
5352 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5353 assert(!regions_overlap(dst
,
5354 type_sz(dst
.type
) * bld
.dispatch_width() *
5355 DIV_ROUND_UP(components
, size_ratio
),
5356 offset(src
, bld
, first_component
),
5357 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5359 brw_reg_type shuffle_type
=
5360 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5361 BRW_REGISTER_TYPE_D
);
5362 for (unsigned i
= 0; i
< components
; i
++) {
5363 fs_reg shuffle_component_i
=
5364 subscript(offset(dst
, bld
, i
/ size_ratio
),
5365 shuffle_type
, i
% size_ratio
);
5366 bld
.MOV(shuffle_component_i
,
5367 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5370 /* Source is unshuffled into destination */
5371 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5372 assert(!regions_overlap(dst
,
5373 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5374 offset(src
, bld
, first_component
/ size_ratio
),
5375 type_sz(src
.type
) * bld
.dispatch_width() *
5376 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5379 brw_reg_type shuffle_type
=
5380 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5381 BRW_REGISTER_TYPE_D
);
5382 for (unsigned i
= 0; i
< components
; i
++) {
5383 fs_reg shuffle_component_i
=
5384 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5385 shuffle_type
, (first_component
+ i
) % size_ratio
);
5386 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5387 shuffle_component_i
);
5393 shuffle_from_32bit_read(const fs_builder
&bld
,
5396 uint32_t first_component
,
5397 uint32_t components
)
5399 assert(type_sz(src
.type
) == 4);
5401 /* This function takes components in units of the destination type while
5402 * shuffle_src_to_dst takes components in units of the smallest type
5404 if (type_sz(dst
.type
) > 4) {
5405 assert(type_sz(dst
.type
) == 8);
5406 first_component
*= 2;
5410 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5414 shuffle_for_32bit_write(const fs_builder
&bld
,
5416 uint32_t first_component
,
5417 uint32_t components
)
5419 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5420 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5421 /* This function takes components in units of the source type while
5422 * shuffle_src_to_dst takes components in units of the smallest type
5424 if (type_sz(src
.type
) > 4) {
5425 assert(type_sz(src
.type
) == 8);
5426 first_component
*= 2;
5430 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5436 setup_imm_df(const fs_builder
&bld
, double v
)
5438 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5439 assert(devinfo
->gen
>= 7);
5441 if (devinfo
->gen
>= 8)
5442 return brw_imm_df(v
);
5444 /* gen7.5 does not support DF immediates straighforward but the DIM
5445 * instruction allows to set the 64-bit immediate value.
5447 if (devinfo
->is_haswell
) {
5448 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5449 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5450 ubld
.DIM(dst
, brw_imm_df(v
));
5451 return component(dst
, 0);
5454 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5455 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5456 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5458 * Alternatively, we could also produce a normal VGRF (without stride 0)
5459 * by writing to all the channels in the VGRF, however, that would hit the
5460 * gen7 bug where we have to split writes that span more than 1 register
5461 * into instructions with a width of 4 (otherwise the write to the second
5462 * register written runs into an execmask hardware bug) which isn't very
5475 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5476 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5477 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5478 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5480 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5484 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5486 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5487 bld
.MOV(tmp
, brw_imm_w(v
));
5492 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5494 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5495 bld
.MOV(tmp
, brw_imm_uw(v
));