2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "util/u_math.h"
28 #include "util/bitscan.h"
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
46 fs_visitor::nir_setup_outputs()
48 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
51 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
53 /* Calculate the size of output registers in a separate pass, before
54 * allocating them. With ARB_enhanced_layouts, multiple output variables
55 * may occupy the same slot, but have different type sizes.
57 nir_foreach_variable(var
, &nir
->outputs
) {
58 const int loc
= var
->data
.driver_location
;
59 const unsigned var_vec4s
=
60 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
61 : type_size_vec4(var
->type
);
62 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
65 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
66 if (vec4s
[loc
] == 0) {
71 unsigned reg_size
= vec4s
[loc
];
73 /* Check if there are any ranges that start within this range and extend
74 * past it. If so, include them in this allocation.
76 for (unsigned i
= 1; i
< reg_size
; i
++)
77 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
79 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
80 for (unsigned i
= 0; i
< reg_size
; i
++)
81 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
88 fs_visitor::nir_setup_uniforms()
90 /* Only the first compile gets to set up uniforms. */
91 if (push_constant_loc
) {
92 assert(pull_constant_loc
);
96 uniforms
= nir
->num_uniforms
/ 4;
98 if (stage
== MESA_SHADER_COMPUTE
) {
99 /* Add a uniform for the thread local id. It must be the last uniform
102 assert(uniforms
== prog_data
->nr_params
);
103 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
104 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
105 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
110 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
114 nir_foreach_instr(instr
, block
) {
115 if (instr
->type
!= nir_instr_type_intrinsic
)
118 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
119 switch (intrin
->intrinsic
) {
120 case nir_intrinsic_load_vertex_id
:
121 case nir_intrinsic_load_base_vertex
:
122 unreachable("should be lowered by nir_lower_system_values().");
124 case nir_intrinsic_load_vertex_id_zero_base
:
125 case nir_intrinsic_load_is_indexed_draw
:
126 case nir_intrinsic_load_first_vertex
:
127 case nir_intrinsic_load_instance_id
:
128 case nir_intrinsic_load_base_instance
:
129 case nir_intrinsic_load_draw_id
:
130 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
132 case nir_intrinsic_load_invocation_id
:
133 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
135 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
136 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
137 if (reg
->file
== BAD_FILE
) {
138 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
139 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
140 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
141 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
146 case nir_intrinsic_load_sample_pos
:
147 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
148 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
149 if (reg
->file
== BAD_FILE
)
150 *reg
= *v
->emit_samplepos_setup();
153 case nir_intrinsic_load_sample_id
:
154 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_sampleid_setup();
160 case nir_intrinsic_load_sample_mask_in
:
161 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
162 assert(v
->devinfo
->gen
>= 7);
163 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
164 if (reg
->file
== BAD_FILE
)
165 *reg
= *v
->emit_samplemaskin_setup();
168 case nir_intrinsic_load_work_group_id
:
169 assert(v
->stage
== MESA_SHADER_COMPUTE
);
170 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
171 if (reg
->file
== BAD_FILE
)
172 *reg
= *v
->emit_cs_work_group_id_setup();
175 case nir_intrinsic_load_helper_invocation
:
176 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
177 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
178 if (reg
->file
== BAD_FILE
) {
179 const fs_builder abld
=
180 v
->bld
.annotate("gl_HelperInvocation", NULL
);
182 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
183 * pixel mask is in g1.7 of the thread payload.
185 * We move the per-channel pixel enable bit to the low bit of each
186 * channel by shifting the byte containing the pixel mask by the
187 * vector immediate 0x76543210UV.
189 * The region of <1,8,0> reads only 1 byte (the pixel masks for
190 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
191 * masks for 2 and 3) in SIMD16.
193 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
195 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
196 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
197 hbld
.SHR(offset(shifted
, hbld
, i
),
198 stride(retype(brw_vec1_grf(1 + i
, 7),
199 BRW_REGISTER_TYPE_UB
),
201 brw_imm_v(0x76543210));
204 /* A set bit in the pixel mask means the channel is enabled, but
205 * that is the opposite of gl_HelperInvocation so we need to invert
208 * The negate source-modifier bit of logical instructions on Gen8+
209 * performs 1's complement negation, so we can use that instead of
212 fs_reg inverted
= negate(shifted
);
213 if (v
->devinfo
->gen
< 8) {
214 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
215 abld
.NOT(inverted
, shifted
);
218 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
219 * with 1 and negating.
221 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
222 abld
.AND(anded
, inverted
, brw_imm_uw(1));
224 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
225 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
239 fs_visitor::nir_emit_system_values()
241 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
242 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
243 nir_system_values
[i
] = fs_reg();
246 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
247 * never end up using it.
250 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
251 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
252 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
254 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
255 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
256 if (dispatch_width
> 8)
257 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
258 if (dispatch_width
> 16) {
259 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
260 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
264 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
265 nir_foreach_block(block
, impl
)
266 emit_system_values_block(block
, this);
270 * Returns a type based on a reference_type (word, float, half-float) and a
273 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
275 * @FIXME: 64-bit return types are always DF on integer types to maintain
276 * compability with uses of DF previously to the introduction of int64
280 brw_reg_type_from_bit_size(const unsigned bit_size
,
281 const brw_reg_type reference_type
)
283 switch(reference_type
) {
284 case BRW_REGISTER_TYPE_HF
:
285 case BRW_REGISTER_TYPE_F
:
286 case BRW_REGISTER_TYPE_DF
:
289 return BRW_REGISTER_TYPE_HF
;
291 return BRW_REGISTER_TYPE_F
;
293 return BRW_REGISTER_TYPE_DF
;
295 unreachable("Invalid bit size");
297 case BRW_REGISTER_TYPE_B
:
298 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_D
:
300 case BRW_REGISTER_TYPE_Q
:
303 return BRW_REGISTER_TYPE_B
;
305 return BRW_REGISTER_TYPE_W
;
307 return BRW_REGISTER_TYPE_D
;
309 return BRW_REGISTER_TYPE_Q
;
311 unreachable("Invalid bit size");
313 case BRW_REGISTER_TYPE_UB
:
314 case BRW_REGISTER_TYPE_UW
:
315 case BRW_REGISTER_TYPE_UD
:
316 case BRW_REGISTER_TYPE_UQ
:
319 return BRW_REGISTER_TYPE_UB
;
321 return BRW_REGISTER_TYPE_UW
;
323 return BRW_REGISTER_TYPE_UD
;
325 return BRW_REGISTER_TYPE_UQ
;
327 unreachable("Invalid bit size");
330 unreachable("Unknown type");
335 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
337 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
338 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
339 nir_locals
[i
] = fs_reg();
342 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
343 unsigned array_elems
=
344 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
345 unsigned size
= array_elems
* reg
->num_components
;
346 const brw_reg_type reg_type
=
347 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
348 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
351 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
354 nir_emit_cf_list(&impl
->body
);
358 fs_visitor::nir_emit_cf_list(exec_list
*list
)
360 exec_list_validate(list
);
361 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
362 switch (node
->type
) {
364 nir_emit_if(nir_cf_node_as_if(node
));
367 case nir_cf_node_loop
:
368 nir_emit_loop(nir_cf_node_as_loop(node
));
371 case nir_cf_node_block
:
372 nir_emit_block(nir_cf_node_as_block(node
));
376 unreachable("Invalid CFG node block");
382 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
384 /* first, put the condition into f0 */
385 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
386 retype(get_nir_src(if_stmt
->condition
),
387 BRW_REGISTER_TYPE_D
));
388 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
390 bld
.IF(BRW_PREDICATE_NORMAL
);
392 nir_emit_cf_list(&if_stmt
->then_list
);
394 /* note: if the else is empty, dead CF elimination will remove it */
395 bld
.emit(BRW_OPCODE_ELSE
);
397 nir_emit_cf_list(&if_stmt
->else_list
);
399 bld
.emit(BRW_OPCODE_ENDIF
);
401 if (devinfo
->gen
< 7)
402 limit_dispatch_width(16, "Non-uniform control flow unsupported "
407 fs_visitor::nir_emit_loop(nir_loop
*loop
)
409 bld
.emit(BRW_OPCODE_DO
);
411 nir_emit_cf_list(&loop
->body
);
413 bld
.emit(BRW_OPCODE_WHILE
);
415 if (devinfo
->gen
< 7)
416 limit_dispatch_width(16, "Non-uniform control flow unsupported "
421 fs_visitor::nir_emit_block(nir_block
*block
)
423 nir_foreach_instr(instr
, block
) {
424 nir_emit_instr(instr
);
429 fs_visitor::nir_emit_instr(nir_instr
*instr
)
431 const fs_builder abld
= bld
.annotate(NULL
, instr
);
433 switch (instr
->type
) {
434 case nir_instr_type_alu
:
435 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
438 case nir_instr_type_deref
:
439 /* Derefs can exist for images but they do nothing */
442 case nir_instr_type_intrinsic
:
444 case MESA_SHADER_VERTEX
:
445 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
447 case MESA_SHADER_TESS_CTRL
:
448 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
450 case MESA_SHADER_TESS_EVAL
:
451 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
453 case MESA_SHADER_GEOMETRY
:
454 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_FRAGMENT
:
457 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_COMPUTE
:
460 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
463 unreachable("unsupported shader stage");
467 case nir_instr_type_tex
:
468 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
471 case nir_instr_type_load_const
:
472 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
475 case nir_instr_type_ssa_undef
:
476 /* We create a new VGRF for undefs on every use (by handling
477 * them in get_nir_src()), rather than for each definition.
478 * This helps register coalescing eliminate MOVs from undef.
482 case nir_instr_type_jump
:
483 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
487 unreachable("unknown instruction type");
492 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
496 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
497 const fs_reg
&result
)
499 if (!instr
->src
[0].src
.is_ssa
||
500 !instr
->src
[0].src
.ssa
->parent_instr
)
503 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
506 nir_alu_instr
*src0
=
507 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
509 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
510 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
513 /* If either opcode has source modifiers, bail.
515 * TODO: We can potentially handle source modifiers if both of the opcodes
516 * we're combining are signed integers.
518 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
519 src0
->src
[0].abs
|| src0
->src
[0].negate
)
522 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
524 /* Element type to extract.*/
525 const brw_reg_type type
= brw_int_type(
526 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
527 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
529 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
530 op0
.type
= brw_type_for_nir_type(devinfo
,
531 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
532 nir_src_bit_size(src0
->src
[0].src
)));
533 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
535 set_saturate(instr
->dest
.saturate
,
536 bld
.MOV(result
, subscript(op0
, type
, element
)));
541 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
542 const fs_reg
&result
)
544 if (!instr
->src
[0].src
.is_ssa
||
545 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
548 nir_intrinsic_instr
*src0
=
549 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
551 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
554 if (!nir_src_is_const(instr
->src
[1].src
) ||
555 !nir_src_is_const(instr
->src
[2].src
))
558 const float value1
= nir_src_as_float(instr
->src
[1].src
);
559 const float value2
= nir_src_as_float(instr
->src
[2].src
);
560 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
563 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
564 assert(value1
== -value2
);
566 fs_reg tmp
= vgrf(glsl_type::int_type
);
568 if (devinfo
->gen
>= 6) {
569 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
570 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
572 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
574 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
575 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
577 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
579 * This negation looks like it's safe in practice, because bits 0:4 will
580 * surely be TRIANGLES
583 if (value1
== -1.0f
) {
587 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
588 g0
, brw_imm_uw(0x3f80));
590 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
591 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
593 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
595 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
596 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
598 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
600 * This negation looks like it's safe in practice, because bits 0:4 will
601 * surely be TRIANGLES
604 if (value1
== -1.0f
) {
608 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
610 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
616 emit_find_msb_using_lzd(const fs_builder
&bld
,
617 const fs_reg
&result
,
625 /* LZD of an absolute value source almost always does the right
626 * thing. There are two problem values:
628 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
629 * 0. However, findMSB(int(0x80000000)) == 30.
631 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
632 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
634 * For a value of zero or negative one, -1 will be returned.
636 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
637 * findMSB(-(1<<x)) should return x-1.
639 * For all negative number cases, including 0x80000000 and
640 * 0xffffffff, the correct value is obtained from LZD if instead of
641 * negating the (already negative) value the logical-not is used. A
642 * conditonal logical-not can be achieved in two instructions.
644 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
646 bld
.ASR(temp
, src
, brw_imm_d(31));
647 bld
.XOR(temp
, temp
, src
);
650 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
651 retype(temp
, BRW_REGISTER_TYPE_UD
));
653 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
654 * from the LSB side. Subtract the result from 31 to convert the MSB
655 * count into an LSB count. If no bits are set, LZD will return 32.
656 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
658 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
659 inst
->src
[0].negate
= true;
663 brw_rnd_mode_from_nir_op (const nir_op op
) {
665 case nir_op_f2f16_rtz
:
666 return BRW_RND_MODE_RTZ
;
667 case nir_op_f2f16_rtne
:
668 return BRW_RND_MODE_RTNE
;
670 unreachable("Operation doesn't support rounding mode");
675 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
676 nir_alu_instr
*instr
,
681 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
683 result
.type
= brw_type_for_nir_type(devinfo
,
684 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
685 nir_dest_bit_size(instr
->dest
.dest
)));
687 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
688 op
[i
] = get_nir_src(instr
->src
[i
].src
);
689 op
[i
].type
= brw_type_for_nir_type(devinfo
,
690 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
691 nir_src_bit_size(instr
->src
[i
].src
)));
692 op
[i
].abs
= instr
->src
[i
].abs
;
693 op
[i
].negate
= instr
->src
[i
].negate
;
696 /* Move and vecN instrutions may still be vectored. Return the raw,
697 * vectored source and destination so that fs_visitor::nir_emit_alu can
698 * handle it. Other callers should not have to handle these kinds of
712 /* At this point, we have dealt with any instruction that operates on
713 * more than a single channel. Therefore, we can just adjust the source
714 * and destination registers for that channel and emit the instruction.
716 unsigned channel
= 0;
717 if (nir_op_infos
[instr
->op
].output_size
== 0) {
718 /* Since NIR is doing the scalarizing for us, we should only ever see
719 * vectorized operations with a single channel.
721 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
722 channel
= ffs(instr
->dest
.write_mask
) - 1;
724 result
= offset(result
, bld
, channel
);
727 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
728 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
729 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
736 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
738 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
742 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, true);
750 fs_reg temp
= result
;
751 bool need_extra_copy
= false;
752 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
753 if (!instr
->src
[i
].src
.is_ssa
&&
754 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
755 need_extra_copy
= true;
756 temp
= bld
.vgrf(result
.type
, 4);
761 for (unsigned i
= 0; i
< 4; i
++) {
762 if (!(instr
->dest
.write_mask
& (1 << i
)))
765 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
766 inst
= bld
.MOV(offset(temp
, bld
, i
),
767 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
769 inst
= bld
.MOV(offset(temp
, bld
, i
),
770 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
772 inst
->saturate
= instr
->dest
.saturate
;
775 /* In this case the source and destination registers were the same,
776 * so we need to insert an extra set of moves in order to deal with
779 if (need_extra_copy
) {
780 for (unsigned i
= 0; i
< 4; i
++) {
781 if (!(instr
->dest
.write_mask
& (1 << i
)))
784 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
792 if (optimize_extract_to_float(instr
, result
))
794 inst
= bld
.MOV(result
, op
[0]);
795 inst
->saturate
= instr
->dest
.saturate
;
798 case nir_op_f2f16_rtne
:
799 case nir_op_f2f16_rtz
:
800 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
801 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
804 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
805 * on the HW gen, it is a special hw opcode or just a MOV, and
806 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
808 * But if we want to use that opcode, we need to provide support on
809 * different optimizations and lowerings. As right now HF support is
810 * only for gen8+, it will be better to use directly the MOV, and use
811 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
815 inst
= bld
.MOV(result
, op
[0]);
816 inst
->saturate
= instr
->dest
.saturate
;
826 op
[0].type
= BRW_REGISTER_TYPE_D
;
827 op
[0].negate
= !op
[0].negate
;
849 inst
= bld
.MOV(result
, op
[0]);
850 inst
->saturate
= instr
->dest
.saturate
;
854 assert(!instr
->dest
.saturate
);
856 /* Straightforward since the source can be assumed to be either
857 * strictly >= 0 or strictly <= 0 depending on the setting of the
860 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
862 inst
= (op
[0].negate
)
863 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
864 : bld
.MOV(result
, brw_imm_f(1.0f
));
866 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
867 } else if (type_sz(op
[0].type
) < 8) {
868 /* AND(val, 0x80000000) gives the sign bit.
870 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
873 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
875 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
876 op
[0].type
= BRW_REGISTER_TYPE_UD
;
877 result
.type
= BRW_REGISTER_TYPE_UD
;
878 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
880 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
881 inst
->predicate
= BRW_PREDICATE_NORMAL
;
883 /* For doubles we do the same but we need to consider:
885 * - 2-src instructions can't operate with 64-bit immediates
886 * - The sign is encoded in the high 32-bit of each DF
887 * - We need to produce a DF result.
890 fs_reg zero
= vgrf(glsl_type::double_type
);
891 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
892 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
894 bld
.MOV(result
, zero
);
896 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
897 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
898 brw_imm_ud(0x80000000u
));
900 set_predicate(BRW_PREDICATE_NORMAL
,
901 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
907 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
908 inst
->saturate
= instr
->dest
.saturate
;
912 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
913 inst
->saturate
= instr
->dest
.saturate
;
917 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
918 inst
->saturate
= instr
->dest
.saturate
;
922 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
923 inst
->saturate
= instr
->dest
.saturate
;
927 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
928 inst
->saturate
= instr
->dest
.saturate
;
932 if (fs_key
->high_quality_derivatives
) {
933 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
935 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
937 inst
->saturate
= instr
->dest
.saturate
;
939 case nir_op_fddx_fine
:
940 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
941 inst
->saturate
= instr
->dest
.saturate
;
943 case nir_op_fddx_coarse
:
944 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
945 inst
->saturate
= instr
->dest
.saturate
;
948 if (fs_key
->high_quality_derivatives
) {
949 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
951 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
953 inst
->saturate
= instr
->dest
.saturate
;
955 case nir_op_fddy_fine
:
956 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
957 inst
->saturate
= instr
->dest
.saturate
;
959 case nir_op_fddy_coarse
:
960 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
961 inst
->saturate
= instr
->dest
.saturate
;
966 inst
= bld
.ADD(result
, op
[0], op
[1]);
967 inst
->saturate
= instr
->dest
.saturate
;
970 case nir_op_uadd_sat
:
971 inst
= bld
.ADD(result
, op
[0], op
[1]);
972 inst
->saturate
= true;
976 inst
= bld
.MUL(result
, op
[0], op
[1]);
977 inst
->saturate
= instr
->dest
.saturate
;
981 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
982 bld
.MUL(result
, op
[0], op
[1]);
985 case nir_op_imul_high
:
986 case nir_op_umul_high
:
987 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
988 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
993 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
994 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
997 case nir_op_uadd_carry
:
998 unreachable("Should have been lowered by carry_to_arith().");
1000 case nir_op_usub_borrow
:
1001 unreachable("Should have been lowered by borrow_to_arith().");
1005 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1006 * appears that our hardware just does the right thing for signed
1009 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1010 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1014 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1015 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1017 /* Math instructions don't support conditional mod */
1018 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1019 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1021 /* Now, we need to determine if signs of the sources are different.
1022 * When we XOR the sources, the top bit is 0 if they are the same and 1
1023 * if they are different. We can then use a conditional modifier to
1024 * turn that into a predicate. This leads us to an XOR.l instruction.
1026 * Technically, according to the PRM, you're not allowed to use .l on a
1027 * XOR instruction. However, emperical experiments and Curro's reading
1028 * of the simulator source both indicate that it's safe.
1030 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1031 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1032 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1033 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1035 /* If the result of the initial remainder operation is non-zero and the
1036 * two sources have different signs, add in a copy of op[1] to get the
1037 * final integer modulus value.
1039 inst
= bld
.ADD(result
, result
, op
[1]);
1040 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1047 case nir_op_fne32
: {
1048 fs_reg dest
= result
;
1050 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1052 dest
= bld
.vgrf(op
[0].type
, 1);
1054 brw_conditional_mod cond
;
1055 switch (instr
->op
) {
1057 cond
= BRW_CONDITIONAL_L
;
1060 cond
= BRW_CONDITIONAL_GE
;
1063 cond
= BRW_CONDITIONAL_Z
;
1066 cond
= BRW_CONDITIONAL_NZ
;
1069 unreachable("bad opcode");
1072 bld
.CMP(dest
, op
[0], op
[1], cond
);
1074 if (bit_size
> 32) {
1075 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1076 } else if(bit_size
< 32) {
1077 /* When we convert the result to 32-bit we need to be careful and do
1078 * it as a signed conversion to get sign extension (for 32-bit true)
1080 const brw_reg_type src_type
=
1081 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1083 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1093 case nir_op_ine32
: {
1094 fs_reg dest
= result
;
1096 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1098 dest
= bld
.vgrf(op
[0].type
, 1);
1100 brw_conditional_mod cond
;
1101 switch (instr
->op
) {
1104 cond
= BRW_CONDITIONAL_L
;
1108 cond
= BRW_CONDITIONAL_GE
;
1111 cond
= BRW_CONDITIONAL_Z
;
1114 cond
= BRW_CONDITIONAL_NZ
;
1117 unreachable("bad opcode");
1119 bld
.CMP(dest
, op
[0], op
[1], cond
);
1121 if (bit_size
> 32) {
1122 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1123 } else if (bit_size
< 32) {
1124 /* When we convert the result to 32-bit we need to be careful and do
1125 * it as a signed conversion to get sign extension (for 32-bit true)
1127 const brw_reg_type src_type
=
1128 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1130 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1136 if (devinfo
->gen
>= 8) {
1137 op
[0] = resolve_source_modifiers(op
[0]);
1139 bld
.NOT(result
, op
[0]);
1142 if (devinfo
->gen
>= 8) {
1143 op
[0] = resolve_source_modifiers(op
[0]);
1144 op
[1] = resolve_source_modifiers(op
[1]);
1146 bld
.XOR(result
, op
[0], op
[1]);
1149 if (devinfo
->gen
>= 8) {
1150 op
[0] = resolve_source_modifiers(op
[0]);
1151 op
[1] = resolve_source_modifiers(op
[1]);
1153 bld
.OR(result
, op
[0], op
[1]);
1156 if (devinfo
->gen
>= 8) {
1157 op
[0] = resolve_source_modifiers(op
[0]);
1158 op
[1] = resolve_source_modifiers(op
[1]);
1160 bld
.AND(result
, op
[0], op
[1]);
1166 case nir_op_b32all_fequal2
:
1167 case nir_op_b32all_iequal2
:
1168 case nir_op_b32all_fequal3
:
1169 case nir_op_b32all_iequal3
:
1170 case nir_op_b32all_fequal4
:
1171 case nir_op_b32all_iequal4
:
1172 case nir_op_b32any_fnequal2
:
1173 case nir_op_b32any_inequal2
:
1174 case nir_op_b32any_fnequal3
:
1175 case nir_op_b32any_inequal3
:
1176 case nir_op_b32any_fnequal4
:
1177 case nir_op_b32any_inequal4
:
1178 unreachable("Lowered by nir_lower_alu_reductions");
1180 case nir_op_fnoise1_1
:
1181 case nir_op_fnoise1_2
:
1182 case nir_op_fnoise1_3
:
1183 case nir_op_fnoise1_4
:
1184 case nir_op_fnoise2_1
:
1185 case nir_op_fnoise2_2
:
1186 case nir_op_fnoise2_3
:
1187 case nir_op_fnoise2_4
:
1188 case nir_op_fnoise3_1
:
1189 case nir_op_fnoise3_2
:
1190 case nir_op_fnoise3_3
:
1191 case nir_op_fnoise3_4
:
1192 case nir_op_fnoise4_1
:
1193 case nir_op_fnoise4_2
:
1194 case nir_op_fnoise4_3
:
1195 case nir_op_fnoise4_4
:
1196 unreachable("not reached: should be handled by lower_noise");
1199 unreachable("not reached: should be handled by ldexp_to_arith()");
1202 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1203 inst
->saturate
= instr
->dest
.saturate
;
1207 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1208 inst
->saturate
= instr
->dest
.saturate
;
1212 case nir_op_f2b32
: {
1213 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1214 if (bit_size
== 64) {
1215 /* two-argument instructions can't take 64-bit immediates */
1219 if (instr
->op
== nir_op_f2b32
) {
1220 zero
= vgrf(glsl_type::double_type
);
1221 tmp
= vgrf(glsl_type::double_type
);
1222 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1224 zero
= vgrf(glsl_type::int64_t_type
);
1225 tmp
= vgrf(glsl_type::int64_t_type
);
1226 bld
.MOV(zero
, brw_imm_q(0));
1229 /* A SIMD16 execution needs to be split in two instructions, so use
1230 * a vgrf instead of the flag register as dst so instruction splitting
1233 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1234 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1237 if (bit_size
== 32) {
1238 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1240 assert(bit_size
== 16);
1241 zero
= instr
->op
== nir_op_f2b32
?
1242 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1244 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1250 inst
= bld
.RNDZ(result
, op
[0]);
1251 inst
->saturate
= instr
->dest
.saturate
;
1254 case nir_op_fceil
: {
1255 op
[0].negate
= !op
[0].negate
;
1256 fs_reg temp
= vgrf(glsl_type::float_type
);
1257 bld
.RNDD(temp
, op
[0]);
1259 inst
= bld
.MOV(result
, temp
);
1260 inst
->saturate
= instr
->dest
.saturate
;
1264 inst
= bld
.RNDD(result
, op
[0]);
1265 inst
->saturate
= instr
->dest
.saturate
;
1268 inst
= bld
.FRC(result
, op
[0]);
1269 inst
->saturate
= instr
->dest
.saturate
;
1271 case nir_op_fround_even
:
1272 inst
= bld
.RNDE(result
, op
[0]);
1273 inst
->saturate
= instr
->dest
.saturate
;
1276 case nir_op_fquantize2f16
: {
1277 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1278 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1279 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1281 /* The destination stride must be at least as big as the source stride. */
1282 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1285 /* Check for denormal */
1286 fs_reg abs_src0
= op
[0];
1287 abs_src0
.abs
= true;
1288 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1290 /* Get the appropriately signed zero */
1291 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1292 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1293 brw_imm_ud(0x80000000));
1294 /* Do the actual F32 -> F16 -> F32 conversion */
1295 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1296 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1297 /* Select that or zero based on normal status */
1298 inst
= bld
.SEL(result
, zero
, tmp32
);
1299 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1300 inst
->saturate
= instr
->dest
.saturate
;
1307 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1308 inst
->saturate
= instr
->dest
.saturate
;
1314 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1315 inst
->saturate
= instr
->dest
.saturate
;
1318 case nir_op_pack_snorm_2x16
:
1319 case nir_op_pack_snorm_4x8
:
1320 case nir_op_pack_unorm_2x16
:
1321 case nir_op_pack_unorm_4x8
:
1322 case nir_op_unpack_snorm_2x16
:
1323 case nir_op_unpack_snorm_4x8
:
1324 case nir_op_unpack_unorm_2x16
:
1325 case nir_op_unpack_unorm_4x8
:
1326 case nir_op_unpack_half_2x16
:
1327 case nir_op_pack_half_2x16
:
1328 unreachable("not reached: should be handled by lower_packing_builtins");
1330 case nir_op_unpack_half_2x16_split_x
:
1331 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1332 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1333 inst
->saturate
= instr
->dest
.saturate
;
1335 case nir_op_unpack_half_2x16_split_y
:
1336 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1337 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1338 inst
->saturate
= instr
->dest
.saturate
;
1341 case nir_op_pack_64_2x32_split
:
1342 case nir_op_pack_32_2x16_split
:
1343 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1346 case nir_op_unpack_64_2x32_split_x
:
1347 case nir_op_unpack_64_2x32_split_y
: {
1348 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1349 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1351 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1355 case nir_op_unpack_32_2x16_split_x
:
1356 case nir_op_unpack_32_2x16_split_y
: {
1357 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1358 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1360 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1365 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1366 inst
->saturate
= instr
->dest
.saturate
;
1369 case nir_op_bitfield_reverse
:
1370 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1371 bld
.BFREV(result
, op
[0]);
1374 case nir_op_bit_count
:
1375 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1376 bld
.CBIT(result
, op
[0]);
1379 case nir_op_ufind_msb
: {
1380 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1381 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1385 case nir_op_ifind_msb
: {
1386 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1388 if (devinfo
->gen
< 7) {
1389 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1391 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1393 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1394 * count from the LSB side. If FBH didn't return an error
1395 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1396 * count into an LSB count.
1398 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1400 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1401 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1402 inst
->src
[0].negate
= true;
1407 case nir_op_find_lsb
:
1408 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1410 if (devinfo
->gen
< 7) {
1411 fs_reg temp
= vgrf(glsl_type::int_type
);
1413 /* (x & -x) generates a value that consists of only the LSB of x.
1414 * For all powers of 2, findMSB(y) == findLSB(y).
1416 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1417 fs_reg negated_src
= src
;
1419 /* One must be negated, and the other must be non-negated. It
1420 * doesn't matter which is which.
1422 negated_src
.negate
= true;
1425 bld
.AND(temp
, src
, negated_src
);
1426 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1428 bld
.FBL(result
, op
[0]);
1432 case nir_op_ubitfield_extract
:
1433 case nir_op_ibitfield_extract
:
1434 unreachable("should have been lowered");
1437 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1438 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1441 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1442 bld
.BFI1(result
, op
[0], op
[1]);
1445 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1446 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1449 case nir_op_bitfield_insert
:
1450 unreachable("not reached: should have been lowered");
1453 bld
.SHL(result
, op
[0], op
[1]);
1456 bld
.ASR(result
, op
[0], op
[1]);
1459 bld
.SHR(result
, op
[0], op
[1]);
1462 case nir_op_pack_half_2x16_split
:
1463 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1467 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1468 inst
->saturate
= instr
->dest
.saturate
;
1472 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1473 inst
->saturate
= instr
->dest
.saturate
;
1476 case nir_op_b32csel
:
1477 if (optimize_frontfacing_ternary(instr
, result
))
1480 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1481 inst
= bld
.SEL(result
, op
[1], op
[2]);
1482 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1485 case nir_op_extract_u8
:
1486 case nir_op_extract_i8
: {
1487 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1492 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1493 * Use two instructions and a word or DWord intermediate integer type.
1495 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1496 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1498 if (instr
->op
== nir_op_extract_i8
) {
1499 /* If we need to sign extend, extract to a word first */
1500 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1501 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1502 bld
.MOV(result
, w_temp
);
1504 /* Otherwise use an AND with 0xff and a word type */
1505 bld
.AND(result
, subscript(op
[0], type
, byte
/ 2), brw_imm_uw(0xff));
1508 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1509 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1514 case nir_op_extract_u16
:
1515 case nir_op_extract_i16
: {
1516 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1517 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1518 bld
.MOV(result
, subscript(op
[0], type
, word
));
1523 unreachable("unhandled instruction");
1526 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1527 * to sign extend the low bit to 0/~0
1529 if (devinfo
->gen
<= 5 &&
1530 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1531 fs_reg masked
= vgrf(glsl_type::int_type
);
1532 bld
.AND(masked
, result
, brw_imm_d(1));
1533 masked
.negate
= true;
1534 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1539 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1540 nir_load_const_instr
*instr
)
1542 const brw_reg_type reg_type
=
1543 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1544 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1546 switch (instr
->def
.bit_size
) {
1548 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1549 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1553 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1554 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1558 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1559 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1563 assert(devinfo
->gen
>= 7);
1564 if (devinfo
->gen
== 7) {
1565 /* We don't get 64-bit integer types until gen8 */
1566 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1567 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1568 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1571 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1572 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1577 unreachable("Invalid bit size");
1580 nir_ssa_values
[instr
->def
.index
] = reg
;
1584 fs_visitor::get_nir_src(const nir_src
&src
)
1588 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1589 const brw_reg_type reg_type
=
1590 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1591 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1593 reg
= nir_ssa_values
[src
.ssa
->index
];
1596 /* We don't handle indirects on locals */
1597 assert(src
.reg
.indirect
== NULL
);
1598 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1599 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1602 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1603 /* The only 64-bit type available on gen7 is DF, so use that. */
1604 reg
.type
= BRW_REGISTER_TYPE_DF
;
1606 /* To avoid floating-point denorm flushing problems, set the type by
1607 * default to an integer type - instructions that need floating point
1608 * semantics will set this to F if they need to
1610 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1611 BRW_REGISTER_TYPE_D
);
1618 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1620 * This function should not be called on any value which may be 64 bits.
1621 * We could theoretically support 64-bit on gen8+ but we choose not to
1622 * because it wouldn't work in general (no gen7 support) and there are
1623 * enough restrictions in 64-bit immediates that you can't take the return
1624 * value and treat it the same as the result of get_nir_src().
1627 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1629 assert(nir_src_bit_size(src
) == 32);
1630 return nir_src_is_const(src
) ?
1631 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1635 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1638 const brw_reg_type reg_type
=
1639 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1640 dest
.ssa
.bit_size
== 8 ?
1641 BRW_REGISTER_TYPE_D
:
1642 BRW_REGISTER_TYPE_F
);
1643 nir_ssa_values
[dest
.ssa
.index
] =
1644 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1645 return nir_ssa_values
[dest
.ssa
.index
];
1647 /* We don't handle indirects on locals */
1648 assert(dest
.reg
.indirect
== NULL
);
1649 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1650 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1655 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1658 for (unsigned i
= 0; i
< 4; i
++) {
1659 if (!((wr_mask
>> i
) & 1))
1662 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1663 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1664 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1665 if (new_inst
->src
[j
].file
== VGRF
)
1666 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1673 emit_pixel_interpolater_send(const fs_builder
&bld
,
1678 glsl_interp_mode interpolation
)
1680 struct brw_wm_prog_data
*wm_prog_data
=
1681 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1683 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1684 /* 2 floats per slot returned */
1685 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1686 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1688 wm_prog_data
->pulls_bary
= true;
1694 * Computes 1 << x, given a D/UD register containing some value x.
1697 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1699 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1701 fs_reg result
= bld
.vgrf(x
.type
, 1);
1702 fs_reg one
= bld
.vgrf(x
.type
, 1);
1704 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1705 bld
.SHL(result
, one
, x
);
1710 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1712 assert(stage
== MESA_SHADER_GEOMETRY
);
1714 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1716 if (gs_compile
->control_data_header_size_bits
== 0)
1719 /* We can only do EndPrimitive() functionality when the control data
1720 * consists of cut bits. Fortunately, the only time it isn't is when the
1721 * output type is points, in which case EndPrimitive() is a no-op.
1723 if (gs_prog_data
->control_data_format
!=
1724 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1728 /* Cut bits use one bit per vertex. */
1729 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1731 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1732 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1734 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1735 * vertex n, 0 otherwise. So all we need to do here is mark bit
1736 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1737 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1738 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1740 * Note that if EndPrimitive() is called before emitting any vertices, this
1741 * will cause us to set bit 31 of the control_data_bits register to 1.
1742 * That's fine because:
1744 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1745 * output, so the hardware will ignore cut bit 31.
1747 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1748 * last vertex, so setting cut bit 31 has no effect (since the primitive
1749 * is automatically ended when the GS terminates).
1751 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1752 * control_data_bits register to 0 when the first vertex is emitted.
1755 const fs_builder abld
= bld
.annotate("end primitive");
1757 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1758 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1759 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1760 fs_reg mask
= intexp2(abld
, prev_count
);
1761 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1762 * attention to the lower 5 bits of its second source argument, so on this
1763 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1764 * ((vertex_count - 1) % 32).
1766 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1770 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1772 assert(stage
== MESA_SHADER_GEOMETRY
);
1773 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1775 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1777 const fs_builder abld
= bld
.annotate("emit control data bits");
1778 const fs_builder fwa_bld
= bld
.exec_all();
1780 /* We use a single UD register to accumulate control data bits (32 bits
1781 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1784 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1785 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1786 * use the Channel Mask phase to enable/disable which DWord within that
1787 * group to write. (Remember, different SIMD8 channels may have emitted
1788 * different numbers of vertices, so we may need per-slot offsets.)
1790 * Channel masking presents an annoying problem: we may have to replicate
1791 * the data up to 4 times:
1793 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1795 * To avoid penalizing shaders that emit a small number of vertices, we
1796 * can avoid these sometimes: if the size of the control data header is
1797 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1798 * land in the same 128-bit group, so we can skip per-slot offsets.
1800 * Similarly, if the control data header is <= 32 bits, there is only one
1801 * DWord, so we can skip channel masks.
1803 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1805 fs_reg channel_mask
, per_slot_offset
;
1807 if (gs_compile
->control_data_header_size_bits
> 32) {
1808 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1809 channel_mask
= vgrf(glsl_type::uint_type
);
1812 if (gs_compile
->control_data_header_size_bits
> 128) {
1813 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1814 per_slot_offset
= vgrf(glsl_type::uint_type
);
1817 /* Figure out which DWord we're trying to write to using the formula:
1819 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1821 * Since bits_per_vertex is a power of two, and is known at compile
1822 * time, this can be optimized to:
1824 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1826 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1827 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1828 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1829 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1830 unsigned log2_bits_per_vertex
=
1831 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1832 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1834 if (per_slot_offset
.file
!= BAD_FILE
) {
1835 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1836 * the appropriate OWord within the control data header.
1838 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1841 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1842 * write to the appropriate DWORD within the OWORD.
1844 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1845 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1846 channel_mask
= intexp2(fwa_bld
, channel
);
1847 /* Then the channel masks need to be in bits 23:16. */
1848 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1851 /* Store the control data bits in the message payload and send it. */
1853 if (channel_mask
.file
!= BAD_FILE
)
1854 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1855 if (per_slot_offset
.file
!= BAD_FILE
)
1858 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1859 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1861 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1862 if (per_slot_offset
.file
!= BAD_FILE
)
1863 sources
[i
++] = per_slot_offset
;
1864 if (channel_mask
.file
!= BAD_FILE
)
1865 sources
[i
++] = channel_mask
;
1867 sources
[i
++] = this->control_data_bits
;
1870 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1871 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1873 /* We need to increment Global Offset by 256-bits to make room for
1874 * Broadwell's extra "Vertex Count" payload at the beginning of the
1875 * URB entry. Since this is an OWord message, Global Offset is counted
1876 * in 128-bit units, so we must set it to 2.
1878 if (gs_prog_data
->static_vertex_count
== -1)
1883 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1886 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1888 /* Note: we are calling this *before* increasing vertex_count, so
1889 * this->vertex_count == vertex_count - 1 in the formula above.
1892 /* Stream mode uses 2 bits per vertex */
1893 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1895 /* Must be a valid stream */
1896 assert(stream_id
< MAX_VERTEX_STREAMS
);
1898 /* Control data bits are initialized to 0 so we don't have to set any
1899 * bits when sending vertices to stream 0.
1904 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1906 /* reg::sid = stream_id */
1907 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1908 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1910 /* reg:shift_count = 2 * (vertex_count - 1) */
1911 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1912 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1914 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1915 * attention to the lower 5 bits of its second source argument, so on this
1916 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1917 * stream_id << ((2 * (vertex_count - 1)) % 32).
1919 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1920 abld
.SHL(mask
, sid
, shift_count
);
1921 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1925 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1928 assert(stage
== MESA_SHADER_GEOMETRY
);
1930 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1932 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1933 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1935 /* Haswell and later hardware ignores the "Render Stream Select" bits
1936 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1937 * and instead sends all primitives down the pipeline for rasterization.
1938 * If the SOL stage is enabled, "Render Stream Select" is honored and
1939 * primitives bound to non-zero streams are discarded after stream output.
1941 * Since the only purpose of primives sent to non-zero streams is to
1942 * be recorded by transform feedback, we can simply discard all geometry
1943 * bound to these streams when transform feedback is disabled.
1945 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1948 /* If we're outputting 32 control data bits or less, then we can wait
1949 * until the shader is over to output them all. Otherwise we need to
1950 * output them as we go. Now is the time to do it, since we're about to
1951 * output the vertex_count'th vertex, so it's guaranteed that the
1952 * control data bits associated with the (vertex_count - 1)th vertex are
1955 if (gs_compile
->control_data_header_size_bits
> 32) {
1956 const fs_builder abld
=
1957 bld
.annotate("emit vertex: emit control data bits");
1959 /* Only emit control data bits if we've finished accumulating a batch
1960 * of 32 bits. This is the case when:
1962 * (vertex_count * bits_per_vertex) % 32 == 0
1964 * (in other words, when the last 5 bits of vertex_count *
1965 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1966 * integer n (which is always the case, since bits_per_vertex is
1967 * always 1 or 2), this is equivalent to requiring that the last 5-n
1968 * bits of vertex_count are 0:
1970 * vertex_count & (2^(5-n) - 1) == 0
1972 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1975 * vertex_count & (32 / bits_per_vertex - 1) == 0
1977 * TODO: If vertex_count is an immediate, we could do some of this math
1978 * at compile time...
1981 abld
.AND(bld
.null_reg_d(), vertex_count
,
1982 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1983 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1985 abld
.IF(BRW_PREDICATE_NORMAL
);
1986 /* If vertex_count is 0, then no control data bits have been
1987 * accumulated yet, so we can skip emitting them.
1989 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1990 BRW_CONDITIONAL_NEQ
);
1991 abld
.IF(BRW_PREDICATE_NORMAL
);
1992 emit_gs_control_data_bits(vertex_count
);
1993 abld
.emit(BRW_OPCODE_ENDIF
);
1995 /* Reset control_data_bits to 0 so we can start accumulating a new
1998 * Note: in the case where vertex_count == 0, this neutralizes the
1999 * effect of any call to EndPrimitive() that the shader may have
2000 * made before outputting its first vertex.
2002 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2003 inst
->force_writemask_all
= true;
2004 abld
.emit(BRW_OPCODE_ENDIF
);
2007 emit_urb_writes(vertex_count
);
2009 /* In stream mode we have to set control data bits for all vertices
2010 * unless we have disabled control data bits completely (which we do
2011 * do for GL_POINTS outputs that don't use streams).
2013 if (gs_compile
->control_data_header_size_bits
> 0 &&
2014 gs_prog_data
->control_data_format
==
2015 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2016 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2021 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2022 const nir_src
&vertex_src
,
2023 unsigned base_offset
,
2024 const nir_src
&offset_src
,
2025 unsigned num_components
,
2026 unsigned first_component
)
2028 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2029 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2031 /* TODO: figure out push input layout for invocations == 1 */
2032 /* TODO: make this work with 64-bit inputs */
2033 if (gs_prog_data
->invocations
== 1 &&
2034 type_sz(dst
.type
) <= 4 &&
2035 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2036 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2037 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2038 nir_src_as_uint(vertex_src
) * push_reg_count
;
2039 for (unsigned i
= 0; i
< num_components
; i
++) {
2040 bld
.MOV(offset(dst
, bld
, i
),
2041 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2046 /* Resort to the pull model. Ensure the VUE handles are provided. */
2047 assert(gs_prog_data
->base
.include_vue_handles
);
2049 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2050 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2052 if (gs_prog_data
->invocations
== 1) {
2053 if (nir_src_is_const(vertex_src
)) {
2054 /* The vertex index is constant; just select the proper URB handle. */
2056 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2057 BRW_REGISTER_TYPE_UD
);
2059 /* The vertex index is non-constant. We need to use indirect
2060 * addressing to fetch the proper URB handle.
2062 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2063 * indicating that channel <n> should read the handle from
2064 * DWord <n>. We convert that to bytes by multiplying by 4.
2066 * Next, we convert the vertex index to bytes by multiplying
2067 * by 32 (shifting by 5), and add the two together. This is
2068 * the final indirect byte offset.
2070 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2071 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2072 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2073 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2075 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2076 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2077 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2078 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2079 /* Convert vertex_index to bytes (multiply by 32) */
2080 bld
.SHL(vertex_offset_bytes
,
2081 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2083 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2085 /* Use first_icp_handle as the base offset. There is one register
2086 * of URB handles per vertex, so inform the register allocator that
2087 * we might read up to nir->info.gs.vertices_in registers.
2089 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2090 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2091 fs_reg(icp_offset_bytes
),
2092 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2095 assert(gs_prog_data
->invocations
> 1);
2097 if (nir_src_is_const(vertex_src
)) {
2098 unsigned vertex
= nir_src_as_uint(vertex_src
);
2099 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2101 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2102 BRW_REGISTER_TYPE_UD
));
2104 /* The vertex index is non-constant. We need to use indirect
2105 * addressing to fetch the proper URB handle.
2108 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2110 /* Convert vertex_index to bytes (multiply by 4) */
2111 bld
.SHL(icp_offset_bytes
,
2112 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2115 /* Use first_icp_handle as the base offset. There is one DWord
2116 * of URB handles per vertex, so inform the register allocator that
2117 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2119 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2120 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2121 fs_reg(icp_offset_bytes
),
2122 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2129 fs_reg tmp_dst
= dst
;
2130 fs_reg indirect_offset
= get_nir_src(offset_src
);
2131 unsigned num_iterations
= 1;
2132 unsigned orig_num_components
= num_components
;
2134 if (type_sz(dst
.type
) == 8) {
2135 if (num_components
> 2) {
2139 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2141 first_component
= first_component
/ 2;
2144 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2145 if (nir_src_is_const(offset_src
)) {
2146 /* Constant indexing - use global offset. */
2147 if (first_component
!= 0) {
2148 unsigned read_components
= num_components
+ first_component
;
2149 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2150 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2151 inst
->size_written
= read_components
*
2152 tmp
.component_size(inst
->exec_size
);
2153 for (unsigned i
= 0; i
< num_components
; i
++) {
2154 bld
.MOV(offset(tmp_dst
, bld
, i
),
2155 offset(tmp
, bld
, i
+ first_component
));
2158 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2160 inst
->size_written
= num_components
*
2161 tmp_dst
.component_size(inst
->exec_size
);
2163 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2166 /* Indirect indexing - use per-slot offsets as well. */
2167 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2168 unsigned read_components
= num_components
+ first_component
;
2169 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2170 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2171 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2172 if (first_component
!= 0) {
2173 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2175 inst
->size_written
= read_components
*
2176 tmp
.component_size(inst
->exec_size
);
2177 for (unsigned i
= 0; i
< num_components
; i
++) {
2178 bld
.MOV(offset(tmp_dst
, bld
, i
),
2179 offset(tmp
, bld
, i
+ first_component
));
2182 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2184 inst
->size_written
= num_components
*
2185 tmp_dst
.component_size(inst
->exec_size
);
2187 inst
->offset
= base_offset
;
2191 if (type_sz(dst
.type
) == 8) {
2192 shuffle_from_32bit_read(bld
,
2193 offset(dst
, bld
, iter
* 2),
2194 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2199 if (num_iterations
> 1) {
2200 num_components
= orig_num_components
- 2;
2201 if(nir_src_is_const(offset_src
)) {
2204 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2205 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2206 indirect_offset
= new_indirect
;
2213 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2215 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2217 if (nir_src_is_const(*offset_src
)) {
2218 /* The only constant offset we should find is 0. brw_nir.c's
2219 * add_const_offset_to_base() will fold other constant offsets
2220 * into instr->const_index[0].
2222 assert(nir_src_as_uint(*offset_src
) == 0);
2226 return get_nir_src(*offset_src
);
2230 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2231 nir_intrinsic_instr
*instr
)
2233 assert(stage
== MESA_SHADER_VERTEX
);
2236 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2237 dest
= get_nir_dest(instr
->dest
);
2239 switch (instr
->intrinsic
) {
2240 case nir_intrinsic_load_vertex_id
:
2241 case nir_intrinsic_load_base_vertex
:
2242 unreachable("should be lowered by nir_lower_system_values()");
2244 case nir_intrinsic_load_input
: {
2245 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2246 unsigned first_component
= nir_intrinsic_component(instr
);
2247 unsigned num_components
= instr
->num_components
;
2249 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2251 if (type_sz(dest
.type
) == 8)
2252 first_component
/= 2;
2254 /* For 16-bit support maybe a temporary will be needed to copy from
2257 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2258 first_component
, num_components
);
2262 case nir_intrinsic_load_vertex_id_zero_base
:
2263 case nir_intrinsic_load_instance_id
:
2264 case nir_intrinsic_load_base_instance
:
2265 case nir_intrinsic_load_draw_id
:
2266 case nir_intrinsic_load_first_vertex
:
2267 case nir_intrinsic_load_is_indexed_draw
:
2268 unreachable("lowered by brw_nir_lower_vs_inputs");
2271 nir_emit_intrinsic(bld
, instr
);
2277 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2278 nir_intrinsic_instr
*instr
)
2280 assert(stage
== MESA_SHADER_TESS_CTRL
);
2281 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2282 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2285 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2286 dst
= get_nir_dest(instr
->dest
);
2288 switch (instr
->intrinsic
) {
2289 case nir_intrinsic_load_primitive_id
:
2290 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2292 case nir_intrinsic_load_invocation_id
:
2293 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2295 case nir_intrinsic_load_patch_vertices_in
:
2296 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2297 brw_imm_d(tcs_key
->input_vertices
));
2300 case nir_intrinsic_barrier
: {
2301 if (tcs_prog_data
->instances
== 1)
2304 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2305 fs_reg m0_2
= component(m0
, 2);
2307 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2309 /* Zero the message header */
2310 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2312 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2313 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2314 brw_imm_ud(INTEL_MASK(16, 13)));
2316 /* Shift it up to bits 27:24. */
2317 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2319 /* Set the Barrier Count and the enable bit */
2320 chanbld
.OR(m0_2
, m0_2
,
2321 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2323 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2327 case nir_intrinsic_load_input
:
2328 unreachable("nir_lower_io should never give us these.");
2331 case nir_intrinsic_load_per_vertex_input
: {
2332 fs_reg indirect_offset
= get_indirect_offset(instr
);
2333 unsigned imm_offset
= instr
->const_index
[0];
2335 const nir_src
&vertex_src
= instr
->src
[0];
2341 if (nir_src_is_const(vertex_src
)) {
2342 /* Emit a MOV to resolve <0,1,0> regioning. */
2343 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2344 unsigned vertex
= nir_src_as_uint(vertex_src
);
2346 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2347 BRW_REGISTER_TYPE_UD
));
2348 } else if (tcs_prog_data
->instances
== 1 &&
2349 vertex_src
.is_ssa
&&
2350 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2351 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2352 /* For the common case of only 1 instance, an array index of
2353 * gl_InvocationID means reading g1. Skip all the indirect work.
2355 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2357 /* The vertex index is non-constant. We need to use indirect
2358 * addressing to fetch the proper URB handle.
2360 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2362 /* Each ICP handle is a single DWord (4 bytes) */
2363 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2364 bld
.SHL(vertex_offset_bytes
,
2365 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2368 /* Start at g1. We might read up to 4 registers. */
2369 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2370 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2371 brw_imm_ud(4 * REG_SIZE
));
2374 /* We can only read two double components with each URB read, so
2375 * we send two read messages in that case, each one loading up to
2376 * two double components.
2378 unsigned num_iterations
= 1;
2379 unsigned num_components
= instr
->num_components
;
2380 unsigned first_component
= nir_intrinsic_component(instr
);
2381 fs_reg orig_dst
= dst
;
2382 if (type_sz(dst
.type
) == 8) {
2383 first_component
= first_component
/ 2;
2384 if (instr
->num_components
> 2) {
2389 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2393 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2394 if (indirect_offset
.file
== BAD_FILE
) {
2395 /* Constant indexing - use global offset. */
2396 if (first_component
!= 0) {
2397 unsigned read_components
= num_components
+ first_component
;
2398 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2399 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2400 for (unsigned i
= 0; i
< num_components
; i
++) {
2401 bld
.MOV(offset(dst
, bld
, i
),
2402 offset(tmp
, bld
, i
+ first_component
));
2405 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2407 inst
->offset
= imm_offset
;
2410 /* Indirect indexing - use per-slot offsets as well. */
2411 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2412 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2413 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2414 if (first_component
!= 0) {
2415 unsigned read_components
= num_components
+ first_component
;
2416 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2417 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2419 for (unsigned i
= 0; i
< num_components
; i
++) {
2420 bld
.MOV(offset(dst
, bld
, i
),
2421 offset(tmp
, bld
, i
+ first_component
));
2424 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2427 inst
->offset
= imm_offset
;
2430 inst
->size_written
= (num_components
+ first_component
) *
2431 inst
->dst
.component_size(inst
->exec_size
);
2433 /* If we are reading 64-bit data using 32-bit read messages we need
2434 * build proper 64-bit data elements by shuffling the low and high
2435 * 32-bit components around like we do for other things like UBOs
2438 if (type_sz(dst
.type
) == 8) {
2439 shuffle_from_32bit_read(bld
,
2440 offset(orig_dst
, bld
, iter
* 2),
2441 retype(dst
, BRW_REGISTER_TYPE_D
),
2445 /* Copy the temporary to the destination to deal with writemasking.
2447 * Also attempt to deal with gl_PointSize being in the .w component.
2449 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2450 assert(type_sz(dst
.type
) < 8);
2451 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2452 inst
->size_written
= 4 * REG_SIZE
;
2453 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2456 /* If we are loading double data and we need a second read message
2457 * adjust the write offset
2459 if (num_iterations
> 1) {
2460 num_components
= instr
->num_components
- 2;
2467 case nir_intrinsic_load_output
:
2468 case nir_intrinsic_load_per_vertex_output
: {
2469 fs_reg indirect_offset
= get_indirect_offset(instr
);
2470 unsigned imm_offset
= instr
->const_index
[0];
2471 unsigned first_component
= nir_intrinsic_component(instr
);
2474 if (indirect_offset
.file
== BAD_FILE
) {
2475 /* Replicate the patch handle to all enabled channels */
2476 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2477 bld
.MOV(patch_handle
,
2478 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2481 if (first_component
!= 0) {
2482 unsigned read_components
=
2483 instr
->num_components
+ first_component
;
2484 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2485 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2487 inst
->size_written
= read_components
* REG_SIZE
;
2488 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2489 bld
.MOV(offset(dst
, bld
, i
),
2490 offset(tmp
, bld
, i
+ first_component
));
2493 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2495 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2497 inst
->offset
= imm_offset
;
2501 /* Indirect indexing - use per-slot offsets as well. */
2502 const fs_reg srcs
[] = {
2503 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2506 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2507 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2508 if (first_component
!= 0) {
2509 unsigned read_components
=
2510 instr
->num_components
+ first_component
;
2511 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2512 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2514 inst
->size_written
= read_components
* REG_SIZE
;
2515 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2516 bld
.MOV(offset(dst
, bld
, i
),
2517 offset(tmp
, bld
, i
+ first_component
));
2520 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2522 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2524 inst
->offset
= imm_offset
;
2530 case nir_intrinsic_store_output
:
2531 case nir_intrinsic_store_per_vertex_output
: {
2532 fs_reg value
= get_nir_src(instr
->src
[0]);
2533 bool is_64bit
= (instr
->src
[0].is_ssa
?
2534 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2535 fs_reg indirect_offset
= get_indirect_offset(instr
);
2536 unsigned imm_offset
= instr
->const_index
[0];
2537 unsigned mask
= instr
->const_index
[1];
2538 unsigned header_regs
= 0;
2540 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2542 if (indirect_offset
.file
!= BAD_FILE
) {
2543 srcs
[header_regs
++] = indirect_offset
;
2549 unsigned num_components
= util_last_bit(mask
);
2552 /* We can only pack two 64-bit components in a single message, so send
2553 * 2 messages if we have more components
2555 unsigned num_iterations
= 1;
2556 unsigned iter_components
= num_components
;
2557 unsigned first_component
= nir_intrinsic_component(instr
);
2559 first_component
= first_component
/ 2;
2560 if (instr
->num_components
> 2) {
2562 iter_components
= 2;
2566 mask
= mask
<< first_component
;
2568 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2569 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2570 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2571 opcode
= indirect_offset
.file
!= BAD_FILE
?
2572 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2573 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2574 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2575 /* Expand the 64-bit mask to 32-bit channels. We only handle
2576 * two channels in each iteration, so we only care about X/Y.
2578 unsigned mask32
= 0;
2579 if (mask
& WRITEMASK_X
)
2580 mask32
|= WRITEMASK_XY
;
2581 if (mask
& WRITEMASK_Y
)
2582 mask32
|= WRITEMASK_ZW
;
2584 /* If the mask does not include any of the channels X or Y there
2585 * is nothing to do in this iteration. Move on to the next couple
2586 * of 64-bit channels.
2594 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2595 opcode
= indirect_offset
.file
!= BAD_FILE
?
2596 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2597 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2599 opcode
= indirect_offset
.file
!= BAD_FILE
?
2600 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2601 SHADER_OPCODE_URB_WRITE_SIMD8
;
2604 for (unsigned i
= 0; i
< iter_components
; i
++) {
2605 if (!(mask
& (1 << (i
+ first_component
))))
2609 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2611 /* We need to shuffle the 64-bit data to match the layout
2612 * expected by our 32-bit URB write messages. We use a temporary
2615 unsigned channel
= iter
* 2 + i
;
2616 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2618 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2619 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2620 offset(dest
, bld
, 1);
2625 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2626 (is_64bit
? 2 * first_component
: first_component
);
2628 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2629 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2631 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2632 inst
->offset
= imm_offset
;
2635 /* If this is a 64-bit attribute, select the next two 64-bit channels
2636 * to be handled in the next iteration.
2647 nir_emit_intrinsic(bld
, instr
);
2653 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2654 nir_intrinsic_instr
*instr
)
2656 assert(stage
== MESA_SHADER_TESS_EVAL
);
2657 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2660 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2661 dest
= get_nir_dest(instr
->dest
);
2663 switch (instr
->intrinsic
) {
2664 case nir_intrinsic_load_primitive_id
:
2665 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2667 case nir_intrinsic_load_tess_coord
:
2668 /* gl_TessCoord is part of the payload in g1-3 */
2669 for (unsigned i
= 0; i
< 3; i
++) {
2670 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2674 case nir_intrinsic_load_input
:
2675 case nir_intrinsic_load_per_vertex_input
: {
2676 fs_reg indirect_offset
= get_indirect_offset(instr
);
2677 unsigned imm_offset
= instr
->const_index
[0];
2678 unsigned first_component
= nir_intrinsic_component(instr
);
2680 if (type_sz(dest
.type
) == 8) {
2681 first_component
= first_component
/ 2;
2685 if (indirect_offset
.file
== BAD_FILE
) {
2686 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2687 * which is 16 registers (since each holds 2 vec4 slots).
2689 unsigned slot_count
= 1;
2690 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2693 const unsigned max_push_slots
= 32;
2694 if (imm_offset
+ slot_count
<= max_push_slots
) {
2695 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2696 for (int i
= 0; i
< instr
->num_components
; i
++) {
2697 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2698 i
+ first_component
;
2699 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2702 tes_prog_data
->base
.urb_read_length
=
2703 MAX2(tes_prog_data
->base
.urb_read_length
,
2704 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2706 /* Replicate the patch handle to all enabled channels */
2707 const fs_reg srcs
[] = {
2708 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2710 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2711 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2713 if (first_component
!= 0) {
2714 unsigned read_components
=
2715 instr
->num_components
+ first_component
;
2716 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2717 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2719 inst
->size_written
= read_components
* REG_SIZE
;
2720 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2721 bld
.MOV(offset(dest
, bld
, i
),
2722 offset(tmp
, bld
, i
+ first_component
));
2725 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2727 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2730 inst
->offset
= imm_offset
;
2733 /* Indirect indexing - use per-slot offsets as well. */
2735 /* We can only read two double components with each URB read, so
2736 * we send two read messages in that case, each one loading up to
2737 * two double components.
2739 unsigned num_iterations
= 1;
2740 unsigned num_components
= instr
->num_components
;
2741 fs_reg orig_dest
= dest
;
2742 if (type_sz(dest
.type
) == 8) {
2743 if (instr
->num_components
> 2) {
2747 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2751 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2752 const fs_reg srcs
[] = {
2753 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2756 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2757 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2759 if (first_component
!= 0) {
2760 unsigned read_components
=
2761 num_components
+ first_component
;
2762 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2763 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2765 for (unsigned i
= 0; i
< num_components
; i
++) {
2766 bld
.MOV(offset(dest
, bld
, i
),
2767 offset(tmp
, bld
, i
+ first_component
));
2770 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2774 inst
->offset
= imm_offset
;
2775 inst
->size_written
= (num_components
+ first_component
) *
2776 inst
->dst
.component_size(inst
->exec_size
);
2778 /* If we are reading 64-bit data using 32-bit read messages we need
2779 * build proper 64-bit data elements by shuffling the low and high
2780 * 32-bit components around like we do for other things like UBOs
2783 if (type_sz(dest
.type
) == 8) {
2784 shuffle_from_32bit_read(bld
,
2785 offset(orig_dest
, bld
, iter
* 2),
2786 retype(dest
, BRW_REGISTER_TYPE_D
),
2790 /* If we are loading double data and we need a second read message
2793 if (num_iterations
> 1) {
2794 num_components
= instr
->num_components
- 2;
2802 nir_emit_intrinsic(bld
, instr
);
2808 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2809 nir_intrinsic_instr
*instr
)
2811 assert(stage
== MESA_SHADER_GEOMETRY
);
2812 fs_reg indirect_offset
;
2815 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2816 dest
= get_nir_dest(instr
->dest
);
2818 switch (instr
->intrinsic
) {
2819 case nir_intrinsic_load_primitive_id
:
2820 assert(stage
== MESA_SHADER_GEOMETRY
);
2821 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2822 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2823 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2826 case nir_intrinsic_load_input
:
2827 unreachable("load_input intrinsics are invalid for the GS stage");
2829 case nir_intrinsic_load_per_vertex_input
:
2830 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2831 instr
->src
[1], instr
->num_components
,
2832 nir_intrinsic_component(instr
));
2835 case nir_intrinsic_emit_vertex_with_counter
:
2836 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2839 case nir_intrinsic_end_primitive_with_counter
:
2840 emit_gs_end_primitive(instr
->src
[0]);
2843 case nir_intrinsic_set_vertex_count
:
2844 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2847 case nir_intrinsic_load_invocation_id
: {
2848 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2849 assert(val
.file
!= BAD_FILE
);
2850 dest
.type
= val
.type
;
2856 nir_emit_intrinsic(bld
, instr
);
2862 * Fetch the current render target layer index.
2865 fetch_render_target_array_index(const fs_builder
&bld
)
2867 if (bld
.shader
->devinfo
->gen
>= 6) {
2868 /* The render target array index is provided in the thread payload as
2869 * bits 26:16 of r0.0.
2871 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2872 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2876 /* Pre-SNB we only ever render into the first layer of the framebuffer
2877 * since layered rendering is not implemented.
2879 return brw_imm_ud(0);
2884 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2885 * framebuffer at the current fragment coordinates and sample index.
2888 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2891 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2893 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2894 const brw_wm_prog_key
*wm_key
=
2895 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2896 assert(!wm_key
->coherent_fb_fetch
);
2897 const struct brw_wm_prog_data
*wm_prog_data
=
2898 brw_wm_prog_data(stage_prog_data
);
2900 /* Calculate the surface index relative to the start of the texture binding
2901 * table block, since that's what the texturing messages expect.
2903 const unsigned surface
= target
+
2904 wm_prog_data
->binding_table
.render_target_read_start
-
2905 wm_prog_data
->base
.binding_table
.texture_start
;
2907 /* Calculate the fragment coordinates. */
2908 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2909 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2910 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2911 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2913 /* Calculate the sample index and MCS payload when multisampling. Luckily
2914 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2915 * shouldn't be necessary to recompile based on whether the framebuffer is
2918 if (wm_key
->multisample_fbo
&&
2919 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2920 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2922 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2923 const fs_reg mcs
= wm_key
->multisample_fbo
?
2924 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2926 /* Use either a normal or a CMS texel fetch message depending on whether
2927 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2928 * message just in case the framebuffer uses 16x multisampling, it should
2929 * be equivalent to the normal CMS fetch for lower multisampling modes.
2931 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2932 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2933 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2935 /* Emit the instruction. */
2936 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
2937 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
2938 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
2939 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
2940 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
2941 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
2942 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
2943 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
2944 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
2946 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
2947 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2953 * Actual coherent framebuffer read implemented using the native render target
2954 * read message. Requires SKL+.
2957 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
2959 assert(bld
.shader
->devinfo
->gen
>= 9);
2960 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
2961 inst
->target
= target
;
2962 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2968 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
2970 if (n
&& regs
[0].file
!= BAD_FILE
) {
2974 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
2976 for (unsigned i
= 0; i
< n
; i
++)
2984 alloc_frag_output(fs_visitor
*v
, unsigned location
)
2986 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
2987 const brw_wm_prog_key
*const key
=
2988 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
2989 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
2990 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
2992 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
2993 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
2995 else if (l
== FRAG_RESULT_COLOR
)
2996 return alloc_temporary(v
->bld
, 4, v
->outputs
,
2997 MAX2(key
->nr_color_regions
, 1));
2999 else if (l
== FRAG_RESULT_DEPTH
)
3000 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3002 else if (l
== FRAG_RESULT_STENCIL
)
3003 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3005 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3006 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3008 else if (l
>= FRAG_RESULT_DATA0
&&
3009 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3010 return alloc_temporary(v
->bld
, 4,
3011 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3014 unreachable("Invalid location");
3018 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3019 nir_intrinsic_instr
*instr
)
3021 assert(stage
== MESA_SHADER_FRAGMENT
);
3024 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3025 dest
= get_nir_dest(instr
->dest
);
3027 switch (instr
->intrinsic
) {
3028 case nir_intrinsic_load_front_face
:
3029 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3030 *emit_frontfacing_interpolation());
3033 case nir_intrinsic_load_sample_pos
: {
3034 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3035 assert(sample_pos
.file
!= BAD_FILE
);
3036 dest
.type
= sample_pos
.type
;
3037 bld
.MOV(dest
, sample_pos
);
3038 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3042 case nir_intrinsic_load_layer_id
:
3043 dest
.type
= BRW_REGISTER_TYPE_UD
;
3044 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3047 case nir_intrinsic_load_helper_invocation
:
3048 case nir_intrinsic_load_sample_mask_in
:
3049 case nir_intrinsic_load_sample_id
: {
3050 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3051 fs_reg val
= nir_system_values
[sv
];
3052 assert(val
.file
!= BAD_FILE
);
3053 dest
.type
= val
.type
;
3058 case nir_intrinsic_store_output
: {
3059 const fs_reg src
= get_nir_src(instr
->src
[0]);
3060 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3061 const unsigned location
= nir_intrinsic_base(instr
) +
3062 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3063 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3066 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3067 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3068 offset(src
, bld
, j
));
3073 case nir_intrinsic_load_output
: {
3074 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3075 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3076 assert(l
>= FRAG_RESULT_DATA0
);
3077 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3078 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3079 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3081 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3082 emit_coherent_fb_read(bld
, tmp
, target
);
3084 emit_non_coherent_fb_read(bld
, tmp
, target
);
3086 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3087 bld
.MOV(offset(dest
, bld
, j
),
3088 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3094 case nir_intrinsic_discard
:
3095 case nir_intrinsic_discard_if
: {
3096 /* We track our discarded pixels in f0.1. By predicating on it, we can
3097 * update just the flag bits that aren't yet discarded. If there's no
3098 * condition, we emit a CMP of g0 != g0, so all currently executing
3099 * channels will get turned off.
3102 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3103 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3104 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3106 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3107 BRW_REGISTER_TYPE_UW
));
3108 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3110 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3111 cmp
->flag_subreg
= 1;
3113 if (devinfo
->gen
>= 6) {
3114 emit_discard_jump();
3117 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3121 case nir_intrinsic_load_input
: {
3122 /* load_input is only used for flat inputs */
3123 unsigned base
= nir_intrinsic_base(instr
);
3124 unsigned comp
= nir_intrinsic_component(instr
);
3125 unsigned num_components
= instr
->num_components
;
3126 fs_reg orig_dest
= dest
;
3127 enum brw_reg_type type
= dest
.type
;
3129 /* Special case fields in the VUE header */
3130 if (base
== VARYING_SLOT_LAYER
)
3132 else if (base
== VARYING_SLOT_VIEWPORT
)
3135 if (nir_dest_bit_size(instr
->dest
) == 64) {
3136 /* const_index is in 32-bit type size units that could not be aligned
3137 * with DF. We need to read the double vector as if it was a float
3138 * vector of twice the number of components to fetch the right data.
3140 type
= BRW_REGISTER_TYPE_F
;
3141 num_components
*= 2;
3142 dest
= bld
.vgrf(type
, num_components
);
3145 for (unsigned int i
= 0; i
< num_components
; i
++) {
3146 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3147 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3150 if (nir_dest_bit_size(instr
->dest
) == 64) {
3151 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3152 instr
->num_components
);
3157 case nir_intrinsic_load_barycentric_pixel
:
3158 case nir_intrinsic_load_barycentric_centroid
:
3159 case nir_intrinsic_load_barycentric_sample
:
3160 /* Do nothing - load_interpolated_input handling will handle it later. */
3163 case nir_intrinsic_load_barycentric_at_sample
: {
3164 const glsl_interp_mode interpolation
=
3165 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3167 if (nir_src_is_const(instr
->src
[0])) {
3168 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3170 emit_pixel_interpolater_send(bld
,
3171 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3174 brw_imm_ud(msg_data
),
3177 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3178 BRW_REGISTER_TYPE_UD
);
3180 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3181 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3182 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3183 bld
.exec_all().group(1, 0)
3184 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3185 emit_pixel_interpolater_send(bld
,
3186 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3192 /* Make a loop that sends a message to the pixel interpolater
3193 * for the sample number in each live channel. If there are
3194 * multiple channels with the same sample number then these
3195 * will be handled simultaneously with a single interation of
3198 bld
.emit(BRW_OPCODE_DO
);
3200 /* Get the next live sample number into sample_id_reg */
3201 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3203 /* Set the flag register so that we can perform the send
3204 * message on all channels that have the same sample number
3206 bld
.CMP(bld
.null_reg_ud(),
3207 sample_src
, sample_id
,
3208 BRW_CONDITIONAL_EQ
);
3209 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3210 bld
.exec_all().group(1, 0)
3211 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3213 emit_pixel_interpolater_send(bld
,
3214 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3217 component(msg_data
, 0),
3219 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3221 /* Continue the loop if there are any live channels left */
3222 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3224 bld
.emit(BRW_OPCODE_WHILE
));
3230 case nir_intrinsic_load_barycentric_at_offset
: {
3231 const glsl_interp_mode interpolation
=
3232 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3234 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3237 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3238 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3239 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3241 emit_pixel_interpolater_send(bld
,
3242 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3245 brw_imm_ud(off_x
| (off_y
<< 4)),
3248 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3249 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3250 BRW_REGISTER_TYPE_F
);
3251 for (int i
= 0; i
< 2; i
++) {
3252 fs_reg temp
= vgrf(glsl_type::float_type
);
3253 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3254 fs_reg itemp
= vgrf(glsl_type::int_type
);
3256 bld
.MOV(itemp
, temp
);
3258 /* Clamp the upper end of the range to +7/16.
3259 * ARB_gpu_shader5 requires that we support a maximum offset
3260 * of +0.5, which isn't representable in a S0.4 value -- if
3261 * we didn't clamp it, we'd end up with -8/16, which is the
3262 * opposite of what the shader author wanted.
3264 * This is legal due to ARB_gpu_shader5's quantization
3267 * "Not all values of <offset> may be supported; x and y
3268 * offsets may be rounded to fixed-point values with the
3269 * number of fraction bits given by the
3270 * implementation-dependent constant
3271 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3273 set_condmod(BRW_CONDITIONAL_L
,
3274 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3277 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3278 emit_pixel_interpolater_send(bld
,
3288 case nir_intrinsic_load_interpolated_input
: {
3289 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3290 emit_fragcoord_interpolation(dest
);
3294 assert(instr
->src
[0].ssa
&&
3295 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3296 nir_intrinsic_instr
*bary_intrinsic
=
3297 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3298 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3299 enum glsl_interp_mode interp_mode
=
3300 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3303 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3304 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3305 /* Use the result of the PI message */
3306 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3308 /* Use the delta_xy values computed from the payload */
3309 enum brw_barycentric_mode bary
=
3310 brw_barycentric_mode(interp_mode
, bary_intrin
);
3312 dst_xy
= this->delta_xy
[bary
];
3315 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3317 component(interp_reg(nir_intrinsic_base(instr
),
3318 nir_intrinsic_component(instr
) + i
), 0);
3319 interp
.type
= BRW_REGISTER_TYPE_F
;
3320 dest
.type
= BRW_REGISTER_TYPE_F
;
3322 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3323 fs_reg tmp
= vgrf(glsl_type::float_type
);
3324 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3325 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3327 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3334 nir_emit_intrinsic(bld
, instr
);
3340 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3342 if (nir_src_is_const(instr
->src
[src
])) {
3343 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3346 else if (add_val
== -1)
3354 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3355 nir_intrinsic_instr
*instr
)
3357 assert(stage
== MESA_SHADER_COMPUTE
);
3358 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3361 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3362 dest
= get_nir_dest(instr
->dest
);
3364 switch (instr
->intrinsic
) {
3365 case nir_intrinsic_barrier
:
3367 cs_prog_data
->uses_barrier
= true;
3370 case nir_intrinsic_load_subgroup_id
:
3371 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3374 case nir_intrinsic_load_local_invocation_id
:
3375 case nir_intrinsic_load_work_group_id
: {
3376 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3377 fs_reg val
= nir_system_values
[sv
];
3378 assert(val
.file
!= BAD_FILE
);
3379 dest
.type
= val
.type
;
3380 for (unsigned i
= 0; i
< 3; i
++)
3381 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3385 case nir_intrinsic_load_num_work_groups
: {
3386 const unsigned surface
=
3387 cs_prog_data
->binding_table
.work_groups_start
;
3389 cs_prog_data
->uses_num_work_groups
= true;
3391 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3392 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3393 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3394 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3396 /* Read the 3 GLuint components of gl_NumWorkGroups */
3397 for (unsigned i
= 0; i
< 3; i
++) {
3398 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3399 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3400 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3405 case nir_intrinsic_shared_atomic_add
:
3406 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3408 case nir_intrinsic_shared_atomic_imin
:
3409 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3411 case nir_intrinsic_shared_atomic_umin
:
3412 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3414 case nir_intrinsic_shared_atomic_imax
:
3415 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3417 case nir_intrinsic_shared_atomic_umax
:
3418 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3420 case nir_intrinsic_shared_atomic_and
:
3421 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3423 case nir_intrinsic_shared_atomic_or
:
3424 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3426 case nir_intrinsic_shared_atomic_xor
:
3427 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3429 case nir_intrinsic_shared_atomic_exchange
:
3430 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3432 case nir_intrinsic_shared_atomic_comp_swap
:
3433 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3435 case nir_intrinsic_shared_atomic_fmin
:
3436 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3438 case nir_intrinsic_shared_atomic_fmax
:
3439 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3441 case nir_intrinsic_shared_atomic_fcomp_swap
:
3442 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3445 case nir_intrinsic_load_shared
: {
3446 assert(devinfo
->gen
>= 7);
3447 assert(stage
== MESA_SHADER_COMPUTE
);
3449 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3450 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3451 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3452 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3453 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3455 /* Make dest unsigned because that's what the temporary will be */
3456 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3458 /* Read the vector */
3459 if (nir_intrinsic_align(instr
) >= 4) {
3460 assert(nir_dest_bit_size(instr
->dest
) == 32);
3461 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3463 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3464 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3465 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3467 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3468 assert(nir_dest_num_components(instr
->dest
) == 1);
3469 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3471 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3472 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3473 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3474 bld
.MOV(dest
, read_result
);
3479 case nir_intrinsic_store_shared
: {
3480 assert(devinfo
->gen
>= 7);
3481 assert(stage
== MESA_SHADER_COMPUTE
);
3483 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3484 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3485 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3486 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3487 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3489 fs_reg data
= get_nir_src(instr
->src
[0]);
3490 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3492 assert(nir_intrinsic_write_mask(instr
) ==
3493 (1u << instr
->num_components
) - 1);
3494 if (nir_intrinsic_align(instr
) >= 4) {
3495 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3496 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3497 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3498 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3499 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3500 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3502 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3503 assert(nir_src_num_components(instr
->src
[0]) == 1);
3504 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3506 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3507 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3509 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3510 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3516 nir_emit_intrinsic(bld
, instr
);
3522 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3523 nir_op op
, brw_reg_type type
)
3525 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3526 switch (type_sz(type
)) {
3528 assert(type
!= BRW_REGISTER_TYPE_HF
);
3529 return retype(brw_imm_uw(value
.u16
[0]), type
);
3531 return retype(brw_imm_ud(value
.u32
[0]), type
);
3533 if (type
== BRW_REGISTER_TYPE_DF
)
3534 return setup_imm_df(bld
, value
.f64
[0]);
3536 return retype(brw_imm_u64(value
.u64
[0]), type
);
3538 unreachable("Invalid type size");
3543 brw_op_for_nir_reduction_op(nir_op op
)
3546 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3547 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3548 case nir_op_imul
: return BRW_OPCODE_MUL
;
3549 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3550 case nir_op_imin
: return BRW_OPCODE_SEL
;
3551 case nir_op_umin
: return BRW_OPCODE_SEL
;
3552 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3553 case nir_op_imax
: return BRW_OPCODE_SEL
;
3554 case nir_op_umax
: return BRW_OPCODE_SEL
;
3555 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3556 case nir_op_iand
: return BRW_OPCODE_AND
;
3557 case nir_op_ior
: return BRW_OPCODE_OR
;
3558 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3560 unreachable("Invalid reduction operation");
3564 static brw_conditional_mod
3565 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3568 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3569 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3570 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3571 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3572 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3573 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3574 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3575 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3576 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3577 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3578 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3579 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3580 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3582 unreachable("Invalid reduction operation");
3587 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3588 nir_intrinsic_instr
*instr
)
3590 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3592 if (stage_prog_data
->binding_table
.image_start
> 0) {
3593 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3594 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3596 bld
.ADD(image
, image
,
3597 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3601 return bld
.emit_uniformize(image
);
3605 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3606 nir_intrinsic_instr
*instr
)
3608 /* SSBO stores are weird in that their index is in src[1] */
3609 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3612 if (nir_src_is_const(instr
->src
[src
])) {
3613 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3614 nir_src_as_uint(instr
->src
[src
]);
3615 surf_index
= brw_imm_ud(index
);
3617 surf_index
= vgrf(glsl_type::uint_type
);
3618 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3619 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3622 return bld
.emit_uniformize(surf_index
);
3626 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3628 switch (nir_intrinsic_image_dim(instr
)) {
3629 case GLSL_SAMPLER_DIM_1D
:
3630 return 1 + nir_intrinsic_image_array(instr
);
3631 case GLSL_SAMPLER_DIM_2D
:
3632 case GLSL_SAMPLER_DIM_RECT
:
3633 return 2 + nir_intrinsic_image_array(instr
);
3634 case GLSL_SAMPLER_DIM_3D
:
3635 case GLSL_SAMPLER_DIM_CUBE
:
3637 case GLSL_SAMPLER_DIM_BUF
:
3639 case GLSL_SAMPLER_DIM_MS
:
3640 return 2 + nir_intrinsic_image_array(instr
);
3642 unreachable("Invalid image dimension");
3647 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3650 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3651 dest
= get_nir_dest(instr
->dest
);
3653 switch (instr
->intrinsic
) {
3654 case nir_intrinsic_image_load
:
3655 case nir_intrinsic_image_store
:
3656 case nir_intrinsic_image_atomic_add
:
3657 case nir_intrinsic_image_atomic_min
:
3658 case nir_intrinsic_image_atomic_max
:
3659 case nir_intrinsic_image_atomic_and
:
3660 case nir_intrinsic_image_atomic_or
:
3661 case nir_intrinsic_image_atomic_xor
:
3662 case nir_intrinsic_image_atomic_exchange
:
3663 case nir_intrinsic_image_atomic_comp_swap
: {
3664 if (stage
== MESA_SHADER_FRAGMENT
&&
3665 instr
->intrinsic
!= nir_intrinsic_image_load
)
3666 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3668 /* Get some metadata from the image intrinsic. */
3669 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3670 const GLenum format
= nir_intrinsic_format(instr
);
3672 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3673 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3674 get_nir_image_intrinsic_image(bld
, instr
);
3675 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3676 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
3677 brw_imm_ud(image_intrinsic_coord_components(instr
));
3679 /* Emit an image load, store or atomic op. */
3680 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3681 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3683 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
3684 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3685 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3686 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3687 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3688 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
3689 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
3690 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3693 unsigned num_srcs
= info
->num_srcs
;
3695 switch (instr
->intrinsic
) {
3696 case nir_intrinsic_image_atomic_add
:
3697 assert(num_srcs
== 4);
3699 op
= get_op_for_atomic_add(instr
, 3);
3701 if (op
!= BRW_AOP_ADD
)
3704 case nir_intrinsic_image_atomic_min
:
3705 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3706 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3708 case nir_intrinsic_image_atomic_max
:
3709 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3710 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3712 case nir_intrinsic_image_atomic_and
:
3715 case nir_intrinsic_image_atomic_or
:
3718 case nir_intrinsic_image_atomic_xor
:
3721 case nir_intrinsic_image_atomic_exchange
:
3724 case nir_intrinsic_image_atomic_comp_swap
:
3728 unreachable("Not reachable.");
3731 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
3735 data
= get_nir_src(instr
->src
[3]);
3736 if (num_srcs
>= 5) {
3737 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
3738 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
3739 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
3742 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3744 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
3745 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3750 case nir_intrinsic_image_size
: {
3751 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3752 * into will handle the binding table index for us in the geneerator.
3754 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3755 BRW_REGISTER_TYPE_UD
);
3756 image
= bld
.emit_uniformize(image
);
3758 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3759 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
3760 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
3761 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
3762 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
3764 /* Since the image size is always uniform, we can just emit a SIMD8
3765 * query instruction and splat the result out.
3767 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3769 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3770 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
3771 tmp
, srcs
, ARRAY_SIZE(srcs
));
3772 inst
->size_written
= 4 * REG_SIZE
;
3774 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3775 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3776 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3777 offset(retype(dest
, tmp
.type
), bld
, c
),
3778 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3780 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3781 component(offset(tmp
, ubld
, c
), 0));
3787 case nir_intrinsic_image_load_raw_intel
: {
3788 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3789 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3790 get_nir_image_intrinsic_image(bld
, instr
);
3791 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3792 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3793 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3796 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3797 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3798 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3802 case nir_intrinsic_image_store_raw_intel
: {
3803 if (stage
== MESA_SHADER_FRAGMENT
)
3804 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3806 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3807 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3808 get_nir_image_intrinsic_image(bld
, instr
);
3809 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3810 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
3811 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3812 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3814 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3815 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3819 case nir_intrinsic_group_memory_barrier
:
3820 case nir_intrinsic_memory_barrier_shared
:
3821 case nir_intrinsic_memory_barrier_atomic_counter
:
3822 case nir_intrinsic_memory_barrier_buffer
:
3823 case nir_intrinsic_memory_barrier_image
:
3824 case nir_intrinsic_memory_barrier
: {
3825 const fs_builder ubld
= bld
.group(8, 0);
3826 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3827 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3828 ->size_written
= 2 * REG_SIZE
;
3832 case nir_intrinsic_shader_clock
: {
3833 /* We cannot do anything if there is an event, so ignore it for now */
3834 const fs_reg shader_clock
= get_timestamp(bld
);
3835 const fs_reg srcs
[] = { component(shader_clock
, 0),
3836 component(shader_clock
, 1) };
3837 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3841 case nir_intrinsic_image_samples
:
3842 /* The driver does not support multi-sampled images. */
3843 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3846 case nir_intrinsic_load_uniform
: {
3847 /* Offsets are in bytes but they should always aligned to
3850 assert(instr
->const_index
[0] % 4 == 0 ||
3851 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3853 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3855 if (nir_src_is_const(instr
->src
[0])) {
3856 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3857 assert(load_offset
% type_sz(dest
.type
) == 0);
3858 /* For 16-bit types we add the module of the const_index[0]
3859 * offset to access to not 32-bit aligned element
3861 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
3863 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3864 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3867 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3868 BRW_REGISTER_TYPE_UD
);
3870 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3871 * go past the end of the uniform. In order to keep the n'th
3872 * component from running past, we subtract off the size of all but
3873 * one component of the vector.
3875 assert(instr
->const_index
[1] >=
3876 instr
->num_components
* (int) type_sz(dest
.type
));
3877 unsigned read_size
= instr
->const_index
[1] -
3878 (instr
->num_components
- 1) * type_sz(dest
.type
);
3880 bool supports_64bit_indirects
=
3881 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3883 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3884 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3885 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3886 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3887 indirect
, brw_imm_ud(read_size
));
3890 const unsigned num_mov_indirects
=
3891 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3892 /* We read a little bit less per MOV INDIRECT, as they are now
3893 * 32-bits ones instead of 64-bit. Fix read_size then.
3895 const unsigned read_size_32bit
= read_size
-
3896 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3897 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3898 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3899 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3900 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3901 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3902 indirect
, brw_imm_ud(read_size_32bit
));
3910 case nir_intrinsic_load_ubo
: {
3912 if (nir_src_is_const(instr
->src
[0])) {
3913 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3914 nir_src_as_uint(instr
->src
[0]);
3915 surf_index
= brw_imm_ud(index
);
3917 /* The block index is not a constant. Evaluate the index expression
3918 * per-channel and add the base UBO index; we have to select a value
3919 * from any live channel.
3921 surf_index
= vgrf(glsl_type::uint_type
);
3922 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3923 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3924 surf_index
= bld
.emit_uniformize(surf_index
);
3927 if (!nir_src_is_const(instr
->src
[1])) {
3928 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3929 BRW_REGISTER_TYPE_UD
);
3931 for (int i
= 0; i
< instr
->num_components
; i
++)
3932 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3933 base_offset
, i
* type_sz(dest
.type
));
3935 /* Even if we are loading doubles, a pull constant load will load
3936 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3937 * need to load a full dvec4 we will have to emit 2 loads. This is
3938 * similar to demote_pull_constants(), except that in that case we
3939 * see individual accesses to each component of the vector and then
3940 * we let CSE deal with duplicate loads. Here we see a vector access
3941 * and we have to split it if necessary.
3943 const unsigned type_size
= type_sz(dest
.type
);
3944 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
3946 /* See if we've selected this as a push constant candidate */
3947 if (nir_src_is_const(instr
->src
[0])) {
3948 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
3949 const unsigned offset_256b
= load_offset
/ 32;
3952 for (int i
= 0; i
< 4; i
++) {
3953 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3954 if (range
->block
== ubo_block
&&
3955 offset_256b
>= range
->start
&&
3956 offset_256b
< range
->start
+ range
->length
) {
3958 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3959 push_reg
.offset
= load_offset
- 32 * range
->start
;
3964 if (push_reg
.file
!= BAD_FILE
) {
3965 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3966 bld
.MOV(offset(dest
, bld
, i
),
3967 byte_offset(push_reg
, i
* type_size
));
3973 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3974 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3975 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3977 for (unsigned c
= 0; c
< instr
->num_components
;) {
3978 const unsigned base
= load_offset
+ c
* type_size
;
3979 /* Number of usable components in the next block-aligned load. */
3980 const unsigned count
= MIN2(instr
->num_components
- c
,
3981 (block_sz
- base
% block_sz
) / type_size
);
3983 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3984 packed_consts
, surf_index
,
3985 brw_imm_ud(base
& ~(block_sz
- 1)));
3987 const fs_reg consts
=
3988 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3991 for (unsigned d
= 0; d
< count
; d
++)
3992 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4000 case nir_intrinsic_load_global
: {
4001 assert(devinfo
->gen
>= 8);
4003 if (nir_intrinsic_align(instr
) >= 4) {
4004 assert(nir_dest_bit_size(instr
->dest
) == 32);
4005 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4007 get_nir_src(instr
->src
[0]), /* Address */
4008 fs_reg(), /* No source data */
4009 brw_imm_ud(instr
->num_components
));
4010 inst
->size_written
= instr
->num_components
*
4011 inst
->dst
.component_size(inst
->exec_size
);
4013 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4014 assert(bit_size
<= 32);
4015 assert(nir_dest_num_components(instr
->dest
) == 1);
4016 brw_reg_type data_type
=
4017 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4018 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4019 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4021 get_nir_src(instr
->src
[0]), /* Address */
4022 fs_reg(), /* No source data */
4023 brw_imm_ud(bit_size
));
4024 bld
.MOV(retype(dest
, data_type
), tmp
);
4029 case nir_intrinsic_store_global
:
4030 assert(devinfo
->gen
>= 8);
4032 if (stage
== MESA_SHADER_FRAGMENT
)
4033 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4035 if (nir_intrinsic_align(instr
) >= 4) {
4036 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4037 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4039 get_nir_src(instr
->src
[1]), /* Address */
4040 get_nir_src(instr
->src
[0]), /* Data */
4041 brw_imm_ud(instr
->num_components
));
4043 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4044 assert(bit_size
<= 32);
4045 assert(nir_src_num_components(instr
->src
[0]) == 1);
4046 brw_reg_type data_type
=
4047 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4048 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4049 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4050 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4052 get_nir_src(instr
->src
[1]), /* Address */
4054 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4058 case nir_intrinsic_global_atomic_add
:
4059 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4061 case nir_intrinsic_global_atomic_imin
:
4062 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4064 case nir_intrinsic_global_atomic_umin
:
4065 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4067 case nir_intrinsic_global_atomic_imax
:
4068 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4070 case nir_intrinsic_global_atomic_umax
:
4071 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4073 case nir_intrinsic_global_atomic_and
:
4074 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4076 case nir_intrinsic_global_atomic_or
:
4077 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4079 case nir_intrinsic_global_atomic_xor
:
4080 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4082 case nir_intrinsic_global_atomic_exchange
:
4083 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4085 case nir_intrinsic_global_atomic_comp_swap
:
4086 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4088 case nir_intrinsic_global_atomic_fmin
:
4089 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4091 case nir_intrinsic_global_atomic_fmax
:
4092 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4094 case nir_intrinsic_global_atomic_fcomp_swap
:
4095 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4098 case nir_intrinsic_load_ssbo
: {
4099 assert(devinfo
->gen
>= 7);
4101 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4102 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4103 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4104 get_nir_ssbo_intrinsic_index(bld
, instr
);
4105 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4106 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4108 /* Make dest unsigned because that's what the temporary will be */
4109 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4111 /* Read the vector */
4112 if (nir_intrinsic_align(instr
) >= 4) {
4113 assert(nir_dest_bit_size(instr
->dest
) == 32);
4114 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4116 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4117 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4118 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4120 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4121 assert(nir_dest_num_components(instr
->dest
) == 1);
4122 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4124 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4125 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4126 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4127 bld
.MOV(dest
, read_result
);
4132 case nir_intrinsic_store_ssbo
: {
4133 assert(devinfo
->gen
>= 7);
4135 if (stage
== MESA_SHADER_FRAGMENT
)
4136 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4138 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4139 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4140 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4141 get_nir_ssbo_intrinsic_index(bld
, instr
);
4142 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4143 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4145 fs_reg data
= get_nir_src(instr
->src
[0]);
4146 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4148 assert(nir_intrinsic_write_mask(instr
) ==
4149 (1u << instr
->num_components
) - 1);
4150 if (nir_intrinsic_align(instr
) >= 4) {
4151 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4152 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4153 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4154 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4155 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4156 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4158 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4159 assert(nir_src_num_components(instr
->src
[0]) == 1);
4160 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4162 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4163 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4165 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4166 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4171 case nir_intrinsic_store_output
: {
4172 fs_reg src
= get_nir_src(instr
->src
[0]);
4174 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4175 unsigned num_components
= instr
->num_components
;
4176 unsigned first_component
= nir_intrinsic_component(instr
);
4177 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4178 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4179 num_components
*= 2;
4182 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4183 4 * store_offset
), src
.type
);
4184 for (unsigned j
= 0; j
< num_components
; j
++) {
4185 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4186 offset(src
, bld
, j
));
4191 case nir_intrinsic_ssbo_atomic_add
:
4192 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4194 case nir_intrinsic_ssbo_atomic_imin
:
4195 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4197 case nir_intrinsic_ssbo_atomic_umin
:
4198 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4200 case nir_intrinsic_ssbo_atomic_imax
:
4201 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4203 case nir_intrinsic_ssbo_atomic_umax
:
4204 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4206 case nir_intrinsic_ssbo_atomic_and
:
4207 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4209 case nir_intrinsic_ssbo_atomic_or
:
4210 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4212 case nir_intrinsic_ssbo_atomic_xor
:
4213 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4215 case nir_intrinsic_ssbo_atomic_exchange
:
4216 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4218 case nir_intrinsic_ssbo_atomic_comp_swap
:
4219 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4221 case nir_intrinsic_ssbo_atomic_fmin
:
4222 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4224 case nir_intrinsic_ssbo_atomic_fmax
:
4225 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4227 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4228 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4231 case nir_intrinsic_get_buffer_size
: {
4232 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4233 nir_src_as_uint(instr
->src
[0]) : 0;
4235 /* A resinfo's sampler message is used to get the buffer size. The
4236 * SIMD8's writeback message consists of four registers and SIMD16's
4237 * writeback message consists of 8 destination registers (two per each
4238 * component). Because we are only interested on the first channel of
4239 * the first returned component, where resinfo returns the buffer size
4240 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4241 * the dispatch width.
4243 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4244 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4245 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4248 ubld
.MOV(src_payload
, brw_imm_d(0));
4250 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4251 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4252 src_payload
, brw_imm_ud(index
));
4253 inst
->header_size
= 0;
4255 inst
->size_written
= 4 * REG_SIZE
;
4257 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4259 * "Out-of-bounds checking is always performed at a DWord granularity. If
4260 * any part of the DWord is out-of-bounds then the whole DWord is
4261 * considered out-of-bounds."
4263 * This implies that types with size smaller than 4-bytes need to be
4264 * padded if they don't complete the last dword of the buffer. But as we
4265 * need to maintain the original size we need to reverse the padding
4266 * calculation to return the correct size to know the number of elements
4267 * of an unsized array. As we stored in the last two bits of the surface
4268 * size the needed padding for the buffer, we calculate here the
4269 * original buffer_size reversing the surface_size calculation:
4271 * surface_size = isl_align(buffer_size, 4) +
4272 * (isl_align(buffer_size) - buffer_size)
4274 * buffer_size = surface_size & ~3 - surface_size & 3
4277 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4278 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4279 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4281 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4282 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4283 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4285 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4289 case nir_intrinsic_load_subgroup_invocation
:
4290 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4291 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4294 case nir_intrinsic_load_subgroup_eq_mask
:
4295 case nir_intrinsic_load_subgroup_ge_mask
:
4296 case nir_intrinsic_load_subgroup_gt_mask
:
4297 case nir_intrinsic_load_subgroup_le_mask
:
4298 case nir_intrinsic_load_subgroup_lt_mask
:
4299 unreachable("not reached");
4301 case nir_intrinsic_vote_any
: {
4302 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4304 /* The any/all predicates do not consider channel enables. To prevent
4305 * dead channels from affecting the result, we initialize the flag with
4306 * with the identity value for the logical operation.
4308 if (dispatch_width
== 32) {
4309 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4310 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4313 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4315 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4317 /* For some reason, the any/all predicates don't work properly with
4318 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4319 * doesn't read the correct subset of the flag register and you end up
4320 * getting garbage in the second half. Work around this by using a pair
4321 * of 1-wide MOVs and scattering the result.
4323 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4324 ubld
.MOV(res1
, brw_imm_d(0));
4325 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4326 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4327 BRW_PREDICATE_ALIGN1_ANY32H
,
4328 ubld
.MOV(res1
, brw_imm_d(-1)));
4330 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4333 case nir_intrinsic_vote_all
: {
4334 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4336 /* The any/all predicates do not consider channel enables. To prevent
4337 * dead channels from affecting the result, we initialize the flag with
4338 * with the identity value for the logical operation.
4340 if (dispatch_width
== 32) {
4341 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4342 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4343 brw_imm_ud(0xffffffff));
4345 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4347 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4349 /* For some reason, the any/all predicates don't work properly with
4350 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4351 * doesn't read the correct subset of the flag register and you end up
4352 * getting garbage in the second half. Work around this by using a pair
4353 * of 1-wide MOVs and scattering the result.
4355 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4356 ubld
.MOV(res1
, brw_imm_d(0));
4357 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4358 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4359 BRW_PREDICATE_ALIGN1_ALL32H
,
4360 ubld
.MOV(res1
, brw_imm_d(-1)));
4362 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4365 case nir_intrinsic_vote_feq
:
4366 case nir_intrinsic_vote_ieq
: {
4367 fs_reg value
= get_nir_src(instr
->src
[0]);
4368 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4369 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4370 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4373 fs_reg uniformized
= bld
.emit_uniformize(value
);
4374 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4376 /* The any/all predicates do not consider channel enables. To prevent
4377 * dead channels from affecting the result, we initialize the flag with
4378 * with the identity value for the logical operation.
4380 if (dispatch_width
== 32) {
4381 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4382 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4383 brw_imm_ud(0xffffffff));
4385 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4387 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4389 /* For some reason, the any/all predicates don't work properly with
4390 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4391 * doesn't read the correct subset of the flag register and you end up
4392 * getting garbage in the second half. Work around this by using a pair
4393 * of 1-wide MOVs and scattering the result.
4395 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4396 ubld
.MOV(res1
, brw_imm_d(0));
4397 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4398 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4399 BRW_PREDICATE_ALIGN1_ALL32H
,
4400 ubld
.MOV(res1
, brw_imm_d(-1)));
4402 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4406 case nir_intrinsic_ballot
: {
4407 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4408 BRW_REGISTER_TYPE_UD
);
4409 struct brw_reg flag
= brw_flag_reg(0, 0);
4410 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4411 * as f0.0. This is a problem for fragment programs as we currently use
4412 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4413 * programs yet so this isn't a problem. When we do, something will
4416 if (dispatch_width
== 32)
4417 flag
.type
= BRW_REGISTER_TYPE_UD
;
4419 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4420 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4422 if (instr
->dest
.ssa
.bit_size
> 32) {
4423 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4425 dest
.type
= BRW_REGISTER_TYPE_UD
;
4427 bld
.MOV(dest
, flag
);
4431 case nir_intrinsic_read_invocation
: {
4432 const fs_reg value
= get_nir_src(instr
->src
[0]);
4433 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4434 fs_reg tmp
= bld
.vgrf(value
.type
);
4436 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4437 bld
.emit_uniformize(invocation
));
4439 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4443 case nir_intrinsic_read_first_invocation
: {
4444 const fs_reg value
= get_nir_src(instr
->src
[0]);
4445 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4449 case nir_intrinsic_shuffle
: {
4450 const fs_reg value
= get_nir_src(instr
->src
[0]);
4451 const fs_reg index
= get_nir_src(instr
->src
[1]);
4453 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4457 case nir_intrinsic_first_invocation
: {
4458 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4459 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4460 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4461 fs_reg(component(tmp
, 0)));
4465 case nir_intrinsic_quad_broadcast
: {
4466 const fs_reg value
= get_nir_src(instr
->src
[0]);
4467 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4469 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4470 value
, brw_imm_ud(index
), brw_imm_ud(4));
4474 case nir_intrinsic_quad_swap_horizontal
: {
4475 const fs_reg value
= get_nir_src(instr
->src
[0]);
4476 const fs_reg tmp
= bld
.vgrf(value
.type
);
4477 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4479 const fs_reg src_left
= horiz_stride(value
, 2);
4480 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4481 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4482 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4484 ubld
.MOV(tmp_left
, src_right
);
4485 ubld
.MOV(tmp_right
, src_left
);
4487 bld
.MOV(retype(dest
, value
.type
), tmp
);
4491 case nir_intrinsic_quad_swap_vertical
: {
4492 const fs_reg value
= get_nir_src(instr
->src
[0]);
4493 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4494 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4495 const fs_reg tmp
= bld
.vgrf(value
.type
);
4496 const fs_builder ubld
= bld
.exec_all();
4497 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4498 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4499 bld
.MOV(retype(dest
, value
.type
), tmp
);
4501 /* For larger data types, we have to either emit dispatch_width many
4502 * MOVs or else fall back to doing indirects.
4504 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4505 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4507 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4512 case nir_intrinsic_quad_swap_diagonal
: {
4513 const fs_reg value
= get_nir_src(instr
->src
[0]);
4514 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4515 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4516 const fs_reg tmp
= bld
.vgrf(value
.type
);
4517 const fs_builder ubld
= bld
.exec_all();
4518 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4519 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4520 bld
.MOV(retype(dest
, value
.type
), tmp
);
4522 /* For larger data types, we have to either emit dispatch_width many
4523 * MOVs or else fall back to doing indirects.
4525 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4526 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4528 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4533 case nir_intrinsic_reduce
: {
4534 fs_reg src
= get_nir_src(instr
->src
[0]);
4535 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4536 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4537 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4538 cluster_size
= dispatch_width
;
4540 /* Figure out the source type */
4541 src
.type
= brw_type_for_nir_type(devinfo
,
4542 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4543 nir_src_bit_size(instr
->src
[0])));
4545 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4546 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4547 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4549 /* Set up a register for all of our scratching around and initialize it
4550 * to reduction operation's identity value.
4552 fs_reg scan
= bld
.vgrf(src
.type
);
4553 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4555 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4557 dest
.type
= src
.type
;
4558 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4559 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4560 * the distance between clusters is at least 2 GRFs. In this case,
4561 * we don't need the weird striding of the CLUSTER_BROADCAST
4562 * instruction and can just do regular MOVs.
4564 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4565 const unsigned groups
=
4566 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4567 const unsigned group_size
= dispatch_width
/ groups
;
4568 for (unsigned i
= 0; i
< groups
; i
++) {
4569 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4570 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4571 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4572 component(scan
, comp
));
4575 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4576 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4581 case nir_intrinsic_inclusive_scan
:
4582 case nir_intrinsic_exclusive_scan
: {
4583 fs_reg src
= get_nir_src(instr
->src
[0]);
4584 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4586 /* Figure out the source type */
4587 src
.type
= brw_type_for_nir_type(devinfo
,
4588 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4589 nir_src_bit_size(instr
->src
[0])));
4591 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4592 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4593 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4595 /* Set up a register for all of our scratching around and initialize it
4596 * to reduction operation's identity value.
4598 fs_reg scan
= bld
.vgrf(src
.type
);
4599 const fs_builder allbld
= bld
.exec_all();
4600 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4602 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4603 /* Exclusive scan is a bit harder because we have to do an annoying
4604 * shift of the contents before we can begin. To make things worse,
4605 * we can't do this with a normal stride; we have to use indirects.
4607 fs_reg shifted
= bld
.vgrf(src
.type
);
4608 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4609 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4611 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4612 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4616 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4618 bld
.MOV(retype(dest
, src
.type
), scan
);
4622 case nir_intrinsic_begin_invocation_interlock
: {
4623 const fs_builder ubld
= bld
.group(8, 0);
4624 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4626 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4632 case nir_intrinsic_end_invocation_interlock
: {
4633 /* We don't need to do anything here */
4638 unreachable("unknown intrinsic");
4643 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4644 int op
, nir_intrinsic_instr
*instr
)
4646 if (stage
== MESA_SHADER_FRAGMENT
)
4647 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4650 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4651 dest
= get_nir_dest(instr
->dest
);
4653 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4654 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4655 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4656 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4657 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4660 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4661 data
= get_nir_src(instr
->src
[2]);
4663 if (op
== BRW_AOP_CMPWR
) {
4664 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4665 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4666 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4669 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4671 /* Emit the actual atomic operation */
4673 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4674 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4678 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4679 int op
, nir_intrinsic_instr
*instr
)
4681 if (stage
== MESA_SHADER_FRAGMENT
)
4682 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4685 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4686 dest
= get_nir_dest(instr
->dest
);
4688 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4689 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4690 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4691 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4692 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4694 fs_reg data
= get_nir_src(instr
->src
[2]);
4695 if (op
== BRW_AOP_FCMPWR
) {
4696 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4697 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4698 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4701 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4703 /* Emit the actual atomic operation */
4705 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4706 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4710 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4711 int op
, nir_intrinsic_instr
*instr
)
4714 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4715 dest
= get_nir_dest(instr
->dest
);
4717 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4718 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4719 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4720 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4723 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4724 data
= get_nir_src(instr
->src
[1]);
4725 if (op
== BRW_AOP_CMPWR
) {
4726 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4727 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4728 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4731 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4733 /* Get the offset */
4734 if (nir_src_is_const(instr
->src
[0])) {
4735 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4736 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4738 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4739 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4740 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4741 brw_imm_ud(instr
->const_index
[0]));
4744 /* Emit the actual atomic operation operation */
4746 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4747 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4751 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4752 int op
, nir_intrinsic_instr
*instr
)
4755 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4756 dest
= get_nir_dest(instr
->dest
);
4758 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4759 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4760 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4761 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4763 fs_reg data
= get_nir_src(instr
->src
[1]);
4764 if (op
== BRW_AOP_FCMPWR
) {
4765 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4766 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4767 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4770 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4772 /* Get the offset */
4773 if (nir_src_is_const(instr
->src
[0])) {
4774 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4775 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4777 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4778 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4779 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4780 brw_imm_ud(instr
->const_index
[0]));
4783 /* Emit the actual atomic operation operation */
4785 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4786 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4790 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
4791 int op
, nir_intrinsic_instr
*instr
)
4793 if (stage
== MESA_SHADER_FRAGMENT
)
4794 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4797 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4798 dest
= get_nir_dest(instr
->dest
);
4800 fs_reg addr
= get_nir_src(instr
->src
[0]);
4803 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4804 data
= get_nir_src(instr
->src
[1]);
4806 if (op
== BRW_AOP_CMPWR
) {
4807 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4808 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4809 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4813 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4814 dest
, addr
, data
, brw_imm_ud(op
));
4818 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
4819 int op
, nir_intrinsic_instr
*instr
)
4821 if (stage
== MESA_SHADER_FRAGMENT
)
4822 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4824 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
4825 fs_reg dest
= get_nir_dest(instr
->dest
);
4827 fs_reg addr
= get_nir_src(instr
->src
[0]);
4829 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
4830 fs_reg data
= get_nir_src(instr
->src
[1]);
4832 if (op
== BRW_AOP_FCMPWR
) {
4833 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4834 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4835 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4839 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4840 dest
, addr
, data
, brw_imm_ud(op
));
4844 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4846 unsigned texture
= instr
->texture_index
;
4847 unsigned sampler
= instr
->sampler_index
;
4849 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4851 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4852 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4854 int lod_components
= 0;
4856 /* The hardware requires a LOD for buffer textures */
4857 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4858 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4860 uint32_t header_bits
= 0;
4861 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4862 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4863 switch (instr
->src
[i
].src_type
) {
4864 case nir_tex_src_bias
:
4865 srcs
[TEX_LOGICAL_SRC_LOD
] =
4866 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4868 case nir_tex_src_comparator
:
4869 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4871 case nir_tex_src_coord
:
4872 switch (instr
->op
) {
4874 case nir_texop_txf_ms
:
4875 case nir_texop_txf_ms_mcs
:
4876 case nir_texop_samples_identical
:
4877 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4880 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4884 case nir_tex_src_ddx
:
4885 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4886 lod_components
= nir_tex_instr_src_size(instr
, i
);
4888 case nir_tex_src_ddy
:
4889 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4891 case nir_tex_src_lod
:
4892 switch (instr
->op
) {
4894 srcs
[TEX_LOGICAL_SRC_LOD
] =
4895 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4898 srcs
[TEX_LOGICAL_SRC_LOD
] =
4899 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4902 srcs
[TEX_LOGICAL_SRC_LOD
] =
4903 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4907 case nir_tex_src_min_lod
:
4908 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
4909 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4911 case nir_tex_src_ms_index
:
4912 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4915 case nir_tex_src_offset
: {
4916 nir_const_value
*const_offset
=
4917 nir_src_as_const_value(instr
->src
[i
].src
);
4918 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
4919 unsigned offset_bits
= 0;
4921 brw_texture_offset(const_offset
->i32
,
4922 nir_tex_instr_src_size(instr
, i
),
4924 header_bits
|= offset_bits
;
4926 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4927 retype(src
, BRW_REGISTER_TYPE_D
);
4932 case nir_tex_src_projector
:
4933 unreachable("should be lowered");
4935 case nir_tex_src_texture_offset
: {
4936 /* Emit code to evaluate the actual indexing expression */
4937 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4938 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4939 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4943 case nir_tex_src_sampler_offset
: {
4944 /* Emit code to evaluate the actual indexing expression */
4945 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4946 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4947 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4951 case nir_tex_src_ms_mcs
:
4952 assert(instr
->op
== nir_texop_txf_ms
);
4953 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4956 case nir_tex_src_plane
: {
4957 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
4958 const uint32_t texture_index
=
4959 instr
->texture_index
+
4960 stage_prog_data
->binding_table
.plane_start
[plane
] -
4961 stage_prog_data
->binding_table
.texture_start
;
4963 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4968 unreachable("unknown texture source");
4972 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4973 (instr
->op
== nir_texop_txf_ms
||
4974 instr
->op
== nir_texop_samples_identical
)) {
4975 if (devinfo
->gen
>= 7 &&
4976 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4977 srcs
[TEX_LOGICAL_SRC_MCS
] =
4978 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4979 instr
->coord_components
,
4980 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4982 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4986 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4987 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4990 switch (instr
->op
) {
4992 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4993 SHADER_OPCODE_TXL_LOGICAL
);
4996 opcode
= FS_OPCODE_TXB_LOGICAL
;
4999 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5002 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5005 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5007 case nir_texop_txf_ms
:
5008 if ((key_tex
->msaa_16
& (1 << sampler
)))
5009 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5011 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5013 case nir_texop_txf_ms_mcs
:
5014 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5016 case nir_texop_query_levels
:
5018 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5021 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5024 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5025 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5027 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5029 case nir_texop_texture_samples
:
5030 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5032 case nir_texop_samples_identical
: {
5033 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5035 /* If mcs is an immediate value, it means there is no MCS. In that case
5036 * just return false.
5038 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5039 bld
.MOV(dst
, brw_imm_ud(0u));
5040 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5041 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5042 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5043 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5044 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5046 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5047 BRW_CONDITIONAL_EQ
);
5052 unreachable("unknown texture opcode");
5055 if (instr
->op
== nir_texop_tg4
) {
5056 if (instr
->component
== 1 &&
5057 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5058 /* gather4 sampler is broken for green channel on RG32F --
5059 * we must ask for blue instead.
5061 header_bits
|= 2 << 16;
5063 header_bits
|= instr
->component
<< 16;
5067 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5068 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5069 inst
->offset
= header_bits
;
5071 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5072 if (devinfo
->gen
>= 9 &&
5073 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5074 unsigned write_mask
= instr
->dest
.is_ssa
?
5075 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5076 (1 << dest_size
) - 1;
5077 assert(write_mask
!= 0); /* dead code should have been eliminated */
5078 inst
->size_written
= util_last_bit(write_mask
) *
5079 inst
->dst
.component_size(inst
->exec_size
);
5081 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5084 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5085 inst
->shadow_compare
= true;
5087 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5088 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5091 for (unsigned i
= 0; i
< dest_size
; i
++)
5092 nir_dest
[i
] = offset(dst
, bld
, i
);
5094 if (instr
->op
== nir_texop_query_levels
) {
5095 /* # levels is in .w */
5096 nir_dest
[0] = offset(dst
, bld
, 3);
5097 } else if (instr
->op
== nir_texop_txs
&&
5098 dest_size
>= 3 && devinfo
->gen
< 7) {
5099 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5100 fs_reg depth
= offset(dst
, bld
, 2);
5101 nir_dest
[2] = vgrf(glsl_type::int_type
);
5102 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5105 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5109 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5111 switch (instr
->type
) {
5112 case nir_jump_break
:
5113 bld
.emit(BRW_OPCODE_BREAK
);
5115 case nir_jump_continue
:
5116 bld
.emit(BRW_OPCODE_CONTINUE
);
5118 case nir_jump_return
:
5120 unreachable("unknown jump");
5125 * This helper takes a source register and un/shuffles it into the destination
5128 * If source type size is smaller than destination type size the operation
5129 * needed is a component shuffle. The opposite case would be an unshuffle. If
5130 * source/destination type size is equal a shuffle is done that would be
5131 * equivalent to a simple MOV.
5133 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5134 * components .xyz 16-bit vector on SIMD8 would be.
5136 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5137 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5139 * This helper will return the following 2 32-bit components with the 16-bit
5142 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5143 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5145 * For unshuffle, the example would be the opposite, a 64-bit type source
5146 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5149 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5150 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5151 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5152 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5154 * The returned result would be the following 4 32-bit components unshuffled:
5156 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5157 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5158 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5159 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5161 * - Source and destination register must not be overlapped.
5162 * - components units are measured in terms of the smaller type between
5163 * source and destination because we are un/shuffling the smaller
5164 * components from/into the bigger ones.
5165 * - first_component parameter allows skipping source components.
5168 shuffle_src_to_dst(const fs_builder
&bld
,
5171 uint32_t first_component
,
5172 uint32_t components
)
5174 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5175 assert(!regions_overlap(dst
,
5176 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5177 offset(src
, bld
, first_component
),
5178 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5179 for (unsigned i
= 0; i
< components
; i
++) {
5180 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5181 offset(src
, bld
, i
+ first_component
));
5183 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5184 /* Source is shuffled into destination */
5185 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5186 assert(!regions_overlap(dst
,
5187 type_sz(dst
.type
) * bld
.dispatch_width() *
5188 DIV_ROUND_UP(components
, size_ratio
),
5189 offset(src
, bld
, first_component
),
5190 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5192 brw_reg_type shuffle_type
=
5193 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5194 BRW_REGISTER_TYPE_D
);
5195 for (unsigned i
= 0; i
< components
; i
++) {
5196 fs_reg shuffle_component_i
=
5197 subscript(offset(dst
, bld
, i
/ size_ratio
),
5198 shuffle_type
, i
% size_ratio
);
5199 bld
.MOV(shuffle_component_i
,
5200 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5203 /* Source is unshuffled into destination */
5204 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5205 assert(!regions_overlap(dst
,
5206 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5207 offset(src
, bld
, first_component
/ size_ratio
),
5208 type_sz(src
.type
) * bld
.dispatch_width() *
5209 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5212 brw_reg_type shuffle_type
=
5213 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5214 BRW_REGISTER_TYPE_D
);
5215 for (unsigned i
= 0; i
< components
; i
++) {
5216 fs_reg shuffle_component_i
=
5217 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5218 shuffle_type
, (first_component
+ i
) % size_ratio
);
5219 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5220 shuffle_component_i
);
5226 shuffle_from_32bit_read(const fs_builder
&bld
,
5229 uint32_t first_component
,
5230 uint32_t components
)
5232 assert(type_sz(src
.type
) == 4);
5234 /* This function takes components in units of the destination type while
5235 * shuffle_src_to_dst takes components in units of the smallest type
5237 if (type_sz(dst
.type
) > 4) {
5238 assert(type_sz(dst
.type
) == 8);
5239 first_component
*= 2;
5243 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5247 shuffle_for_32bit_write(const fs_builder
&bld
,
5249 uint32_t first_component
,
5250 uint32_t components
)
5252 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5253 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5254 /* This function takes components in units of the source type while
5255 * shuffle_src_to_dst takes components in units of the smallest type
5257 if (type_sz(src
.type
) > 4) {
5258 assert(type_sz(src
.type
) == 8);
5259 first_component
*= 2;
5263 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5269 setup_imm_df(const fs_builder
&bld
, double v
)
5271 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5272 assert(devinfo
->gen
>= 7);
5274 if (devinfo
->gen
>= 8)
5275 return brw_imm_df(v
);
5277 /* gen7.5 does not support DF immediates straighforward but the DIM
5278 * instruction allows to set the 64-bit immediate value.
5280 if (devinfo
->is_haswell
) {
5281 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5282 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5283 ubld
.DIM(dst
, brw_imm_df(v
));
5284 return component(dst
, 0);
5287 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5288 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5289 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5291 * Alternatively, we could also produce a normal VGRF (without stride 0)
5292 * by writing to all the channels in the VGRF, however, that would hit the
5293 * gen7 bug where we have to split writes that span more than 1 register
5294 * into instructions with a width of 4 (otherwise the write to the second
5295 * register written runs into an execmask hardware bug) which isn't very
5308 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5309 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5310 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5311 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5313 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5317 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5319 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5320 bld
.MOV(tmp
, brw_imm_w(v
));
5325 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5327 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5328 bld
.MOV(tmp
, brw_imm_uw(v
));