2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
48 fs_visitor::nir_setup_outputs()
50 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
53 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
55 /* Calculate the size of output registers in a separate pass, before
56 * allocating them. With ARB_enhanced_layouts, multiple output variables
57 * may occupy the same slot, but have different type sizes.
59 nir_foreach_variable(var
, &nir
->outputs
) {
60 const int loc
= var
->data
.driver_location
;
61 const unsigned var_vec4s
=
62 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
63 : type_size_vec4(var
->type
, true);
64 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
67 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
68 if (vec4s
[loc
] == 0) {
73 unsigned reg_size
= vec4s
[loc
];
75 /* Check if there are any ranges that start within this range and extend
76 * past it. If so, include them in this allocation.
78 for (unsigned i
= 1; i
< reg_size
; i
++)
79 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
81 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
82 for (unsigned i
= 0; i
< reg_size
; i
++)
83 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
90 fs_visitor::nir_setup_uniforms()
92 /* Only the first compile gets to set up uniforms. */
93 if (push_constant_loc
) {
94 assert(pull_constant_loc
);
98 uniforms
= nir
->num_uniforms
/ 4;
100 if (stage
== MESA_SHADER_COMPUTE
) {
101 /* Add a uniform for the thread local id. It must be the last uniform
104 assert(uniforms
== prog_data
->nr_params
);
105 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
106 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
107 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
112 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
116 nir_foreach_instr(instr
, block
) {
117 if (instr
->type
!= nir_instr_type_intrinsic
)
120 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
121 switch (intrin
->intrinsic
) {
122 case nir_intrinsic_load_vertex_id
:
123 case nir_intrinsic_load_base_vertex
:
124 unreachable("should be lowered by nir_lower_system_values().");
126 case nir_intrinsic_load_vertex_id_zero_base
:
127 case nir_intrinsic_load_is_indexed_draw
:
128 case nir_intrinsic_load_first_vertex
:
129 case nir_intrinsic_load_instance_id
:
130 case nir_intrinsic_load_base_instance
:
131 case nir_intrinsic_load_draw_id
:
132 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
134 case nir_intrinsic_load_invocation_id
:
135 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
137 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
138 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
139 if (reg
->file
== BAD_FILE
) {
140 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
141 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
142 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
143 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
148 case nir_intrinsic_load_sample_pos
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_samplepos_setup();
155 case nir_intrinsic_load_sample_id
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_sampleid_setup();
162 case nir_intrinsic_load_sample_mask_in
:
163 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
164 assert(v
->devinfo
->gen
>= 7);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplemaskin_setup();
170 case nir_intrinsic_load_work_group_id
:
171 assert(v
->stage
== MESA_SHADER_COMPUTE
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_cs_work_group_id_setup();
177 case nir_intrinsic_load_helper_invocation
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
180 if (reg
->file
== BAD_FILE
) {
181 const fs_builder abld
=
182 v
->bld
.annotate("gl_HelperInvocation", NULL
);
184 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
185 * pixel mask is in g1.7 of the thread payload.
187 * We move the per-channel pixel enable bit to the low bit of each
188 * channel by shifting the byte containing the pixel mask by the
189 * vector immediate 0x76543210UV.
191 * The region of <1,8,0> reads only 1 byte (the pixel masks for
192 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
193 * masks for 2 and 3) in SIMD16.
195 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
197 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
198 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
199 hbld
.SHR(offset(shifted
, hbld
, i
),
200 stride(retype(brw_vec1_grf(1 + i
, 7),
201 BRW_REGISTER_TYPE_UB
),
203 brw_imm_v(0x76543210));
206 /* A set bit in the pixel mask means the channel is enabled, but
207 * that is the opposite of gl_HelperInvocation so we need to invert
210 * The negate source-modifier bit of logical instructions on Gen8+
211 * performs 1's complement negation, so we can use that instead of
214 fs_reg inverted
= negate(shifted
);
215 if (v
->devinfo
->gen
< 8) {
216 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
217 abld
.NOT(inverted
, shifted
);
220 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
221 * with 1 and negating.
223 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
224 abld
.AND(anded
, inverted
, brw_imm_uw(1));
226 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
227 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
241 fs_visitor::nir_emit_system_values()
243 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
244 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
245 nir_system_values
[i
] = fs_reg();
248 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
249 * never end up using it.
252 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
253 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
254 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
256 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
257 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
258 if (dispatch_width
> 8)
259 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
260 if (dispatch_width
> 16) {
261 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
262 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
266 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
267 nir_foreach_block(block
, impl
)
268 emit_system_values_block(block
, this);
272 * Returns a type based on a reference_type (word, float, half-float) and a
275 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
277 * @FIXME: 64-bit return types are always DF on integer types to maintain
278 * compability with uses of DF previously to the introduction of int64
282 brw_reg_type_from_bit_size(const unsigned bit_size
,
283 const brw_reg_type reference_type
)
285 switch(reference_type
) {
286 case BRW_REGISTER_TYPE_HF
:
287 case BRW_REGISTER_TYPE_F
:
288 case BRW_REGISTER_TYPE_DF
:
291 return BRW_REGISTER_TYPE_HF
;
293 return BRW_REGISTER_TYPE_F
;
295 return BRW_REGISTER_TYPE_DF
;
297 unreachable("Invalid bit size");
299 case BRW_REGISTER_TYPE_B
:
300 case BRW_REGISTER_TYPE_W
:
301 case BRW_REGISTER_TYPE_D
:
302 case BRW_REGISTER_TYPE_Q
:
305 return BRW_REGISTER_TYPE_B
;
307 return BRW_REGISTER_TYPE_W
;
309 return BRW_REGISTER_TYPE_D
;
311 return BRW_REGISTER_TYPE_Q
;
313 unreachable("Invalid bit size");
315 case BRW_REGISTER_TYPE_UB
:
316 case BRW_REGISTER_TYPE_UW
:
317 case BRW_REGISTER_TYPE_UD
:
318 case BRW_REGISTER_TYPE_UQ
:
321 return BRW_REGISTER_TYPE_UB
;
323 return BRW_REGISTER_TYPE_UW
;
325 return BRW_REGISTER_TYPE_UD
;
327 return BRW_REGISTER_TYPE_UQ
;
329 unreachable("Invalid bit size");
332 unreachable("Unknown type");
337 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
339 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
340 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
341 nir_locals
[i
] = fs_reg();
344 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
345 unsigned array_elems
=
346 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
347 unsigned size
= array_elems
* reg
->num_components
;
348 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
349 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
350 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
353 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
356 nir_emit_cf_list(&impl
->body
);
360 fs_visitor::nir_emit_cf_list(exec_list
*list
)
362 exec_list_validate(list
);
363 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
364 switch (node
->type
) {
366 nir_emit_if(nir_cf_node_as_if(node
));
369 case nir_cf_node_loop
:
370 nir_emit_loop(nir_cf_node_as_loop(node
));
373 case nir_cf_node_block
:
374 nir_emit_block(nir_cf_node_as_block(node
));
378 unreachable("Invalid CFG node block");
384 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
389 /* If the condition has the form !other_condition, use other_condition as
390 * the source, but invert the predicate on the if instruction.
392 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
393 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
394 assert(!cond
->src
[0].negate
);
395 assert(!cond
->src
[0].abs
);
398 cond_reg
= get_nir_src(cond
->src
[0].src
);
401 cond_reg
= get_nir_src(if_stmt
->condition
);
404 /* first, put the condition into f0 */
405 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
406 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
407 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
409 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
411 nir_emit_cf_list(&if_stmt
->then_list
);
413 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
414 bld
.emit(BRW_OPCODE_ELSE
);
415 nir_emit_cf_list(&if_stmt
->else_list
);
418 bld
.emit(BRW_OPCODE_ENDIF
);
420 if (devinfo
->gen
< 7)
421 limit_dispatch_width(16, "Non-uniform control flow unsupported "
426 fs_visitor::nir_emit_loop(nir_loop
*loop
)
428 bld
.emit(BRW_OPCODE_DO
);
430 nir_emit_cf_list(&loop
->body
);
432 bld
.emit(BRW_OPCODE_WHILE
);
434 if (devinfo
->gen
< 7)
435 limit_dispatch_width(16, "Non-uniform control flow unsupported "
440 fs_visitor::nir_emit_block(nir_block
*block
)
442 nir_foreach_instr(instr
, block
) {
443 nir_emit_instr(instr
);
448 fs_visitor::nir_emit_instr(nir_instr
*instr
)
450 const fs_builder abld
= bld
.annotate(NULL
, instr
);
452 switch (instr
->type
) {
453 case nir_instr_type_alu
:
454 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
457 case nir_instr_type_deref
:
458 unreachable("All derefs should've been lowered");
461 case nir_instr_type_intrinsic
:
463 case MESA_SHADER_VERTEX
:
464 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
466 case MESA_SHADER_TESS_CTRL
:
467 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 case MESA_SHADER_TESS_EVAL
:
470 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 case MESA_SHADER_GEOMETRY
:
473 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
475 case MESA_SHADER_FRAGMENT
:
476 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 case MESA_SHADER_COMPUTE
:
479 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
482 unreachable("unsupported shader stage");
486 case nir_instr_type_tex
:
487 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
490 case nir_instr_type_load_const
:
491 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
494 case nir_instr_type_ssa_undef
:
495 /* We create a new VGRF for undefs on every use (by handling
496 * them in get_nir_src()), rather than for each definition.
497 * This helps register coalescing eliminate MOVs from undef.
501 case nir_instr_type_jump
:
502 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
506 unreachable("unknown instruction type");
511 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
515 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
516 const fs_reg
&result
)
518 if (!instr
->src
[0].src
.is_ssa
||
519 !instr
->src
[0].src
.ssa
->parent_instr
)
522 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
525 nir_alu_instr
*src0
=
526 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
528 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
529 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
532 /* If either opcode has source modifiers, bail.
534 * TODO: We can potentially handle source modifiers if both of the opcodes
535 * we're combining are signed integers.
537 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
538 src0
->src
[0].abs
|| src0
->src
[0].negate
)
541 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
543 /* Element type to extract.*/
544 const brw_reg_type type
= brw_int_type(
545 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
546 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
548 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
549 op0
.type
= brw_type_for_nir_type(devinfo
,
550 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
551 nir_src_bit_size(src0
->src
[0].src
)));
552 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
554 set_saturate(instr
->dest
.saturate
,
555 bld
.MOV(result
, subscript(op0
, type
, element
)));
560 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
561 const fs_reg
&result
)
563 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
564 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
567 if (!nir_src_is_const(instr
->src
[1].src
) ||
568 !nir_src_is_const(instr
->src
[2].src
))
571 const float value1
= nir_src_as_float(instr
->src
[1].src
);
572 const float value2
= nir_src_as_float(instr
->src
[2].src
);
573 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
576 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
577 assert(value1
== -value2
);
579 fs_reg tmp
= vgrf(glsl_type::int_type
);
581 if (devinfo
->gen
>= 6) {
582 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
583 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
585 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
587 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
588 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
590 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
592 * This negation looks like it's safe in practice, because bits 0:4 will
593 * surely be TRIANGLES
596 if (value1
== -1.0f
) {
600 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
601 g0
, brw_imm_uw(0x3f80));
603 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
604 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
606 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
608 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
609 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
611 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
613 * This negation looks like it's safe in practice, because bits 0:4 will
614 * surely be TRIANGLES
617 if (value1
== -1.0f
) {
621 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
623 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
629 emit_find_msb_using_lzd(const fs_builder
&bld
,
630 const fs_reg
&result
,
638 /* LZD of an absolute value source almost always does the right
639 * thing. There are two problem values:
641 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
642 * 0. However, findMSB(int(0x80000000)) == 30.
644 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
645 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
647 * For a value of zero or negative one, -1 will be returned.
649 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
650 * findMSB(-(1<<x)) should return x-1.
652 * For all negative number cases, including 0x80000000 and
653 * 0xffffffff, the correct value is obtained from LZD if instead of
654 * negating the (already negative) value the logical-not is used. A
655 * conditonal logical-not can be achieved in two instructions.
657 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
659 bld
.ASR(temp
, src
, brw_imm_d(31));
660 bld
.XOR(temp
, temp
, src
);
663 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
664 retype(temp
, BRW_REGISTER_TYPE_UD
));
666 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
667 * from the LSB side. Subtract the result from 31 to convert the MSB
668 * count into an LSB count. If no bits are set, LZD will return 32.
669 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
671 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
672 inst
->src
[0].negate
= true;
676 brw_rnd_mode_from_nir_op (const nir_op op
) {
678 case nir_op_f2f16_rtz
:
679 return BRW_RND_MODE_RTZ
;
680 case nir_op_f2f16_rtne
:
681 return BRW_RND_MODE_RTNE
;
683 unreachable("Operation doesn't support rounding mode");
688 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
689 nir_alu_instr
*instr
,
694 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
696 result
.type
= brw_type_for_nir_type(devinfo
,
697 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
698 nir_dest_bit_size(instr
->dest
.dest
)));
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 op
[i
] = get_nir_src(instr
->src
[i
].src
);
702 op
[i
].type
= brw_type_for_nir_type(devinfo
,
703 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
704 nir_src_bit_size(instr
->src
[i
].src
)));
705 op
[i
].abs
= instr
->src
[i
].abs
;
706 op
[i
].negate
= instr
->src
[i
].negate
;
709 /* Move and vecN instrutions may still be vectored. Return the raw,
710 * vectored source and destination so that fs_visitor::nir_emit_alu can
711 * handle it. Other callers should not have to handle these kinds of
724 /* At this point, we have dealt with any instruction that operates on
725 * more than a single channel. Therefore, we can just adjust the source
726 * and destination registers for that channel and emit the instruction.
728 unsigned channel
= 0;
729 if (nir_op_infos
[instr
->op
].output_size
== 0) {
730 /* Since NIR is doing the scalarizing for us, we should only ever see
731 * vectorized operations with a single channel.
733 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
734 channel
= ffs(instr
->dest
.write_mask
) - 1;
736 result
= offset(result
, bld
, channel
);
739 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
740 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
741 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
748 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
751 for (unsigned i
= 0; i
< 2; i
++) {
752 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
754 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
755 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
756 /* The source of the inot is now the source of instr. */
757 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
759 assert(!op
[i
].negate
);
762 op
[i
] = resolve_source_modifiers(op
[i
]);
768 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
770 nir_alu_instr
*instr
)
772 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
775 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
777 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
780 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
781 * of valid size-changing combinations is a bit more complex.
783 * The source restriction is just because I was lazy about generating the
786 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
787 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
790 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
791 * this is float(1 + a).
795 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
797 /* Ignore the saturate modifier, if there is one. The result of the
798 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
800 bld
.ADD(result
, op
, brw_imm_d(1));
806 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
808 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
809 * the source of \c instr that is a \c nir_op_fsign.
812 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
813 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
817 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
818 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
820 if (instr
->op
!= nir_op_fsign
) {
821 const nir_alu_instr
*const fsign_instr
=
822 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
824 assert(!fsign_instr
->dest
.saturate
);
826 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
827 * fsign_src] has the other multiply source. This must be rearranged so
828 * that op[0] is the source of the fsign op[1] is the other multiply
834 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
836 const nir_alu_type t
=
837 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
838 nir_src_bit_size(fsign_instr
->src
[0].src
));
840 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
841 op
[0].abs
= fsign_instr
->src
[0].abs
;
842 op
[0].negate
= fsign_instr
->src
[0].negate
;
844 unsigned channel
= 0;
845 if (nir_op_infos
[instr
->op
].output_size
== 0) {
846 /* Since NIR is doing the scalarizing for us, we should only ever see
847 * vectorized operations with a single channel.
849 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
850 channel
= ffs(instr
->dest
.write_mask
) - 1;
853 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
855 assert(!instr
->dest
.saturate
);
859 /* Straightforward since the source can be assumed to be either strictly
860 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
862 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
864 if (instr
->op
== nir_op_fsign
) {
865 inst
= (op
[0].negate
)
866 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
867 : bld
.MOV(result
, brw_imm_f(1.0f
));
869 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
870 inst
= bld
.MOV(result
, op
[1]);
873 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
874 } else if (type_sz(op
[0].type
) == 2) {
875 /* AND(val, 0x8000) gives the sign bit.
877 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
879 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
880 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
882 op
[0].type
= BRW_REGISTER_TYPE_UW
;
883 result
.type
= BRW_REGISTER_TYPE_UW
;
884 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
886 if (instr
->op
== nir_op_fsign
)
887 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
889 /* Use XOR here to get the result sign correct. */
890 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
893 inst
->predicate
= BRW_PREDICATE_NORMAL
;
894 } else if (type_sz(op
[0].type
) == 4) {
895 /* AND(val, 0x80000000) gives the sign bit.
897 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
900 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
902 op
[0].type
= BRW_REGISTER_TYPE_UD
;
903 result
.type
= BRW_REGISTER_TYPE_UD
;
904 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
906 if (instr
->op
== nir_op_fsign
)
907 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
909 /* Use XOR here to get the result sign correct. */
910 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
913 inst
->predicate
= BRW_PREDICATE_NORMAL
;
915 /* For doubles we do the same but we need to consider:
917 * - 2-src instructions can't operate with 64-bit immediates
918 * - The sign is encoded in the high 32-bit of each DF
919 * - We need to produce a DF result.
922 fs_reg zero
= vgrf(glsl_type::double_type
);
923 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
924 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
926 bld
.MOV(result
, zero
);
928 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
929 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
930 brw_imm_ud(0x80000000u
));
932 if (instr
->op
== nir_op_fsign
) {
933 set_predicate(BRW_PREDICATE_NORMAL
,
934 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
936 /* This could be done better in some cases. If the scale is an
937 * immediate with the low 32-bits all 0, emitting a separate XOR and
938 * OR would allow an algebraic optimization to remove the OR. There
939 * are currently zero instances of fsign(double(x))*IMM in shader-db
940 * or any test suite, so it is hard to care at this time.
942 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
943 inst
= bld
.XOR(result_int64
, result_int64
,
944 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
950 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
952 * Checks the operands of a \c nir_op_fmul to determine whether or not
953 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
955 * \param instr The multiplication instruction
957 * \param fsign_src The source of \c instr that may or may not be a
961 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
963 assert(instr
->op
== nir_op_fmul
);
965 nir_alu_instr
*const fsign_instr
=
966 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
970 * 1. instr->src[fsign_src] must be a nir_op_fsign.
971 * 2. The nir_op_fsign can only be used by this multiplication.
972 * 3. The source that is the nir_op_fsign does not have source modifiers.
973 * \c emit_fsign only examines the source modifiers of the source of the
976 * The nir_op_fsign must also not have the saturate modifier, but steps
977 * have already been taken (in nir_opt_algebraic) to ensure that.
979 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
980 is_used_once(fsign_instr
) &&
981 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
985 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
988 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
992 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
999 fs_reg temp
= result
;
1000 bool need_extra_copy
= false;
1001 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1002 if (!instr
->src
[i
].src
.is_ssa
&&
1003 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1004 need_extra_copy
= true;
1005 temp
= bld
.vgrf(result
.type
, 4);
1010 for (unsigned i
= 0; i
< 4; i
++) {
1011 if (!(instr
->dest
.write_mask
& (1 << i
)))
1014 if (instr
->op
== nir_op_mov
) {
1015 inst
= bld
.MOV(offset(temp
, bld
, i
),
1016 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1018 inst
= bld
.MOV(offset(temp
, bld
, i
),
1019 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1021 inst
->saturate
= instr
->dest
.saturate
;
1024 /* In this case the source and destination registers were the same,
1025 * so we need to insert an extra set of moves in order to deal with
1028 if (need_extra_copy
) {
1029 for (unsigned i
= 0; i
< 4; i
++) {
1030 if (!(instr
->dest
.write_mask
& (1 << i
)))
1033 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1041 if (optimize_extract_to_float(instr
, result
))
1043 inst
= bld
.MOV(result
, op
[0]);
1044 inst
->saturate
= instr
->dest
.saturate
;
1047 case nir_op_f2f16_rtne
:
1048 case nir_op_f2f16_rtz
:
1049 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1050 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
1053 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1054 * on the HW gen, it is a special hw opcode or just a MOV, and
1055 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1057 * But if we want to use that opcode, we need to provide support on
1058 * different optimizations and lowerings. As right now HF support is
1059 * only for gen8+, it will be better to use directly the MOV, and use
1060 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1062 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1063 inst
= bld
.MOV(result
, op
[0]);
1064 inst
->saturate
= instr
->dest
.saturate
;
1074 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1076 op
[0].type
= BRW_REGISTER_TYPE_D
;
1077 op
[0].negate
= !op
[0].negate
;
1101 if (result
.type
== BRW_REGISTER_TYPE_B
||
1102 result
.type
== BRW_REGISTER_TYPE_UB
||
1103 result
.type
== BRW_REGISTER_TYPE_HF
)
1104 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1106 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1107 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1108 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1109 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1111 inst
= bld
.MOV(result
, op
[0]);
1112 inst
->saturate
= instr
->dest
.saturate
;
1116 inst
= bld
.MOV(result
, op
[0]);
1117 inst
->saturate
= true;
1122 op
[0].negate
= true;
1123 inst
= bld
.MOV(result
, op
[0]);
1124 if (instr
->op
== nir_op_fneg
)
1125 inst
->saturate
= instr
->dest
.saturate
;
1130 op
[0].negate
= false;
1132 inst
= bld
.MOV(result
, op
[0]);
1133 if (instr
->op
== nir_op_fabs
)
1134 inst
->saturate
= instr
->dest
.saturate
;
1138 emit_fsign(bld
, instr
, result
, op
, 0);
1142 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1143 inst
->saturate
= instr
->dest
.saturate
;
1147 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1148 inst
->saturate
= instr
->dest
.saturate
;
1152 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1153 inst
->saturate
= instr
->dest
.saturate
;
1157 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1158 inst
->saturate
= instr
->dest
.saturate
;
1162 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1163 inst
->saturate
= instr
->dest
.saturate
;
1167 if (fs_key
->high_quality_derivatives
) {
1168 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1170 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1172 inst
->saturate
= instr
->dest
.saturate
;
1174 case nir_op_fddx_fine
:
1175 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1176 inst
->saturate
= instr
->dest
.saturate
;
1178 case nir_op_fddx_coarse
:
1179 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1180 inst
->saturate
= instr
->dest
.saturate
;
1183 if (fs_key
->high_quality_derivatives
) {
1184 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1186 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1188 inst
->saturate
= instr
->dest
.saturate
;
1190 case nir_op_fddy_fine
:
1191 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1192 inst
->saturate
= instr
->dest
.saturate
;
1194 case nir_op_fddy_coarse
:
1195 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1196 inst
->saturate
= instr
->dest
.saturate
;
1201 inst
= bld
.ADD(result
, op
[0], op
[1]);
1202 inst
->saturate
= instr
->dest
.saturate
;
1205 case nir_op_uadd_sat
:
1206 inst
= bld
.ADD(result
, op
[0], op
[1]);
1207 inst
->saturate
= true;
1211 for (unsigned i
= 0; i
< 2; i
++) {
1212 if (can_fuse_fmul_fsign(instr
, i
)) {
1213 emit_fsign(bld
, instr
, result
, op
, i
);
1218 inst
= bld
.MUL(result
, op
[0], op
[1]);
1219 inst
->saturate
= instr
->dest
.saturate
;
1222 case nir_op_imul_2x32_64
:
1223 case nir_op_umul_2x32_64
:
1224 bld
.MUL(result
, op
[0], op
[1]);
1228 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1229 bld
.MUL(result
, op
[0], op
[1]);
1232 case nir_op_imul_high
:
1233 case nir_op_umul_high
:
1234 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1235 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1240 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1241 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1244 case nir_op_uadd_carry
:
1245 unreachable("Should have been lowered by carry_to_arith().");
1247 case nir_op_usub_borrow
:
1248 unreachable("Should have been lowered by borrow_to_arith().");
1252 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1253 * appears that our hardware just does the right thing for signed
1256 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1257 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1261 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1262 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1264 /* Math instructions don't support conditional mod */
1265 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1266 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1268 /* Now, we need to determine if signs of the sources are different.
1269 * When we XOR the sources, the top bit is 0 if they are the same and 1
1270 * if they are different. We can then use a conditional modifier to
1271 * turn that into a predicate. This leads us to an XOR.l instruction.
1273 * Technically, according to the PRM, you're not allowed to use .l on a
1274 * XOR instruction. However, emperical experiments and Curro's reading
1275 * of the simulator source both indicate that it's safe.
1277 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1278 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1279 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1280 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1282 /* If the result of the initial remainder operation is non-zero and the
1283 * two sources have different signs, add in a copy of op[1] to get the
1284 * final integer modulus value.
1286 inst
= bld
.ADD(result
, result
, op
[1]);
1287 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1294 case nir_op_fne32
: {
1295 fs_reg dest
= result
;
1297 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1299 dest
= bld
.vgrf(op
[0].type
, 1);
1301 brw_conditional_mod cond
;
1302 switch (instr
->op
) {
1304 cond
= BRW_CONDITIONAL_L
;
1307 cond
= BRW_CONDITIONAL_GE
;
1310 cond
= BRW_CONDITIONAL_Z
;
1313 cond
= BRW_CONDITIONAL_NZ
;
1316 unreachable("bad opcode");
1319 bld
.CMP(dest
, op
[0], op
[1], cond
);
1321 if (bit_size
> 32) {
1322 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1323 } else if(bit_size
< 32) {
1324 /* When we convert the result to 32-bit we need to be careful and do
1325 * it as a signed conversion to get sign extension (for 32-bit true)
1327 const brw_reg_type src_type
=
1328 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1330 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1340 case nir_op_ine32
: {
1341 fs_reg dest
= result
;
1343 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1344 * type. So we convert both operands for the comparison.
1347 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1348 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1350 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1352 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1354 brw_conditional_mod cond
;
1355 switch (instr
->op
) {
1358 cond
= BRW_CONDITIONAL_L
;
1362 cond
= BRW_CONDITIONAL_GE
;
1365 cond
= BRW_CONDITIONAL_Z
;
1368 cond
= BRW_CONDITIONAL_NZ
;
1371 unreachable("bad opcode");
1373 bld
.CMP(dest
, temp_op
[0], temp_op
[1], cond
);
1375 if (bit_size
> 32) {
1376 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1377 } else if (bit_size
< 32) {
1378 /* When we convert the result to 32-bit we need to be careful and do
1379 * it as a signed conversion to get sign extension (for 32-bit true)
1381 const brw_reg_type src_type
=
1382 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1384 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1390 if (devinfo
->gen
>= 8) {
1391 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1393 if (inot_src_instr
!= NULL
&&
1394 (inot_src_instr
->op
== nir_op_ior
||
1395 inot_src_instr
->op
== nir_op_ixor
||
1396 inot_src_instr
->op
== nir_op_iand
) &&
1397 !inot_src_instr
->src
[0].abs
&&
1398 !inot_src_instr
->src
[0].negate
&&
1399 !inot_src_instr
->src
[1].abs
&&
1400 !inot_src_instr
->src
[1].negate
) {
1401 /* The sources of the source logical instruction are now the
1402 * sources of the instruction that will be generated.
1404 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1405 resolve_inot_sources(bld
, inot_src_instr
, op
);
1407 /* Smash all of the sources and destination to be signed. This
1408 * doesn't matter for the operation of the instruction, but cmod
1409 * propagation fails on unsigned sources with negation (due to
1410 * fs_inst::can_do_cmod returning false).
1413 brw_type_for_nir_type(devinfo
,
1414 (nir_alu_type
)(nir_type_int
|
1415 nir_dest_bit_size(instr
->dest
.dest
)));
1417 brw_type_for_nir_type(devinfo
,
1418 (nir_alu_type
)(nir_type_int
|
1419 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1421 brw_type_for_nir_type(devinfo
,
1422 (nir_alu_type
)(nir_type_int
|
1423 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1425 /* For XOR, only invert one of the sources. Arbitrarily choose
1428 op
[0].negate
= !op
[0].negate
;
1429 if (inot_src_instr
->op
!= nir_op_ixor
)
1430 op
[1].negate
= !op
[1].negate
;
1432 switch (inot_src_instr
->op
) {
1434 bld
.AND(result
, op
[0], op
[1]);
1438 bld
.OR(result
, op
[0], op
[1]);
1442 bld
.XOR(result
, op
[0], op
[1]);
1446 unreachable("impossible opcode");
1449 op
[0] = resolve_source_modifiers(op
[0]);
1451 bld
.NOT(result
, op
[0]);
1454 if (devinfo
->gen
>= 8) {
1455 resolve_inot_sources(bld
, instr
, op
);
1457 bld
.XOR(result
, op
[0], op
[1]);
1460 if (devinfo
->gen
>= 8) {
1461 resolve_inot_sources(bld
, instr
, op
);
1463 bld
.OR(result
, op
[0], op
[1]);
1466 if (devinfo
->gen
>= 8) {
1467 resolve_inot_sources(bld
, instr
, op
);
1469 bld
.AND(result
, op
[0], op
[1]);
1475 case nir_op_b32all_fequal2
:
1476 case nir_op_b32all_iequal2
:
1477 case nir_op_b32all_fequal3
:
1478 case nir_op_b32all_iequal3
:
1479 case nir_op_b32all_fequal4
:
1480 case nir_op_b32all_iequal4
:
1481 case nir_op_b32any_fnequal2
:
1482 case nir_op_b32any_inequal2
:
1483 case nir_op_b32any_fnequal3
:
1484 case nir_op_b32any_inequal3
:
1485 case nir_op_b32any_fnequal4
:
1486 case nir_op_b32any_inequal4
:
1487 unreachable("Lowered by nir_lower_alu_reductions");
1489 case nir_op_fnoise1_1
:
1490 case nir_op_fnoise1_2
:
1491 case nir_op_fnoise1_3
:
1492 case nir_op_fnoise1_4
:
1493 case nir_op_fnoise2_1
:
1494 case nir_op_fnoise2_2
:
1495 case nir_op_fnoise2_3
:
1496 case nir_op_fnoise2_4
:
1497 case nir_op_fnoise3_1
:
1498 case nir_op_fnoise3_2
:
1499 case nir_op_fnoise3_3
:
1500 case nir_op_fnoise3_4
:
1501 case nir_op_fnoise4_1
:
1502 case nir_op_fnoise4_2
:
1503 case nir_op_fnoise4_3
:
1504 case nir_op_fnoise4_4
:
1505 unreachable("not reached: should be handled by lower_noise");
1508 unreachable("not reached: should be handled by ldexp_to_arith()");
1511 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1512 inst
->saturate
= instr
->dest
.saturate
;
1516 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1517 inst
->saturate
= instr
->dest
.saturate
;
1521 case nir_op_f2b32
: {
1522 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1523 if (bit_size
== 64) {
1524 /* two-argument instructions can't take 64-bit immediates */
1528 if (instr
->op
== nir_op_f2b32
) {
1529 zero
= vgrf(glsl_type::double_type
);
1530 tmp
= vgrf(glsl_type::double_type
);
1531 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1533 zero
= vgrf(glsl_type::int64_t_type
);
1534 tmp
= vgrf(glsl_type::int64_t_type
);
1535 bld
.MOV(zero
, brw_imm_q(0));
1538 /* A SIMD16 execution needs to be split in two instructions, so use
1539 * a vgrf instead of the flag register as dst so instruction splitting
1542 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1543 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1546 if (bit_size
== 32) {
1547 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1549 assert(bit_size
== 16);
1550 zero
= instr
->op
== nir_op_f2b32
?
1551 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1553 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1559 inst
= bld
.RNDZ(result
, op
[0]);
1560 inst
->saturate
= instr
->dest
.saturate
;
1563 case nir_op_fceil
: {
1564 op
[0].negate
= !op
[0].negate
;
1565 fs_reg temp
= vgrf(glsl_type::float_type
);
1566 bld
.RNDD(temp
, op
[0]);
1568 inst
= bld
.MOV(result
, temp
);
1569 inst
->saturate
= instr
->dest
.saturate
;
1573 inst
= bld
.RNDD(result
, op
[0]);
1574 inst
->saturate
= instr
->dest
.saturate
;
1577 inst
= bld
.FRC(result
, op
[0]);
1578 inst
->saturate
= instr
->dest
.saturate
;
1580 case nir_op_fround_even
:
1581 inst
= bld
.RNDE(result
, op
[0]);
1582 inst
->saturate
= instr
->dest
.saturate
;
1585 case nir_op_fquantize2f16
: {
1586 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1587 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1588 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1590 /* The destination stride must be at least as big as the source stride. */
1591 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1594 /* Check for denormal */
1595 fs_reg abs_src0
= op
[0];
1596 abs_src0
.abs
= true;
1597 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1599 /* Get the appropriately signed zero */
1600 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1601 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1602 brw_imm_ud(0x80000000));
1603 /* Do the actual F32 -> F16 -> F32 conversion */
1604 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1605 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1606 /* Select that or zero based on normal status */
1607 inst
= bld
.SEL(result
, zero
, tmp32
);
1608 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1609 inst
->saturate
= instr
->dest
.saturate
;
1616 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1617 inst
->saturate
= instr
->dest
.saturate
;
1623 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1624 inst
->saturate
= instr
->dest
.saturate
;
1627 case nir_op_pack_snorm_2x16
:
1628 case nir_op_pack_snorm_4x8
:
1629 case nir_op_pack_unorm_2x16
:
1630 case nir_op_pack_unorm_4x8
:
1631 case nir_op_unpack_snorm_2x16
:
1632 case nir_op_unpack_snorm_4x8
:
1633 case nir_op_unpack_unorm_2x16
:
1634 case nir_op_unpack_unorm_4x8
:
1635 case nir_op_unpack_half_2x16
:
1636 case nir_op_pack_half_2x16
:
1637 unreachable("not reached: should be handled by lower_packing_builtins");
1639 case nir_op_unpack_half_2x16_split_x
:
1640 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1641 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1642 inst
->saturate
= instr
->dest
.saturate
;
1644 case nir_op_unpack_half_2x16_split_y
:
1645 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1646 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1647 inst
->saturate
= instr
->dest
.saturate
;
1650 case nir_op_pack_64_2x32_split
:
1651 case nir_op_pack_32_2x16_split
:
1652 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1655 case nir_op_unpack_64_2x32_split_x
:
1656 case nir_op_unpack_64_2x32_split_y
: {
1657 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1658 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1660 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1664 case nir_op_unpack_32_2x16_split_x
:
1665 case nir_op_unpack_32_2x16_split_y
: {
1666 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1667 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1669 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1674 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1675 inst
->saturate
= instr
->dest
.saturate
;
1678 case nir_op_bitfield_reverse
:
1679 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1680 bld
.BFREV(result
, op
[0]);
1683 case nir_op_bit_count
:
1684 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1685 bld
.CBIT(result
, op
[0]);
1688 case nir_op_ufind_msb
: {
1689 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1690 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1694 case nir_op_ifind_msb
: {
1695 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1697 if (devinfo
->gen
< 7) {
1698 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1700 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1702 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1703 * count from the LSB side. If FBH didn't return an error
1704 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1705 * count into an LSB count.
1707 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1709 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1710 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1711 inst
->src
[0].negate
= true;
1716 case nir_op_find_lsb
:
1717 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1719 if (devinfo
->gen
< 7) {
1720 fs_reg temp
= vgrf(glsl_type::int_type
);
1722 /* (x & -x) generates a value that consists of only the LSB of x.
1723 * For all powers of 2, findMSB(y) == findLSB(y).
1725 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1726 fs_reg negated_src
= src
;
1728 /* One must be negated, and the other must be non-negated. It
1729 * doesn't matter which is which.
1731 negated_src
.negate
= true;
1734 bld
.AND(temp
, src
, negated_src
);
1735 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1737 bld
.FBL(result
, op
[0]);
1741 case nir_op_ubitfield_extract
:
1742 case nir_op_ibitfield_extract
:
1743 unreachable("should have been lowered");
1746 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1747 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1750 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1751 bld
.BFI1(result
, op
[0], op
[1]);
1754 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1755 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1758 case nir_op_bitfield_insert
:
1759 unreachable("not reached: should have been lowered");
1762 bld
.SHL(result
, op
[0], op
[1]);
1765 bld
.ASR(result
, op
[0], op
[1]);
1768 bld
.SHR(result
, op
[0], op
[1]);
1772 bld
.ROL(result
, op
[0], op
[1]);
1775 bld
.ROR(result
, op
[0], op
[1]);
1778 case nir_op_pack_half_2x16_split
:
1779 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1783 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1784 inst
->saturate
= instr
->dest
.saturate
;
1788 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1789 inst
->saturate
= instr
->dest
.saturate
;
1792 case nir_op_b32csel
:
1793 if (optimize_frontfacing_ternary(instr
, result
))
1796 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1797 inst
= bld
.SEL(result
, op
[1], op
[2]);
1798 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1801 case nir_op_extract_u8
:
1802 case nir_op_extract_i8
: {
1803 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1808 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1809 * Use two instructions and a word or DWord intermediate integer type.
1811 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1812 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1814 if (instr
->op
== nir_op_extract_i8
) {
1815 /* If we need to sign extend, extract to a word first */
1816 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1817 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1818 bld
.MOV(result
, w_temp
);
1819 } else if (byte
& 1) {
1820 /* Extract the high byte from the word containing the desired byte
1824 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1827 /* Otherwise use an AND with 0xff and a word type */
1829 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1833 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1834 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1839 case nir_op_extract_u16
:
1840 case nir_op_extract_i16
: {
1841 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1842 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1843 bld
.MOV(result
, subscript(op
[0], type
, word
));
1848 unreachable("unhandled instruction");
1851 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1852 * to sign extend the low bit to 0/~0
1854 if (devinfo
->gen
<= 5 &&
1855 !result
.is_null() &&
1856 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1857 fs_reg masked
= vgrf(glsl_type::int_type
);
1858 bld
.AND(masked
, result
, brw_imm_d(1));
1859 masked
.negate
= true;
1860 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1865 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1866 nir_load_const_instr
*instr
)
1868 const brw_reg_type reg_type
=
1869 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1870 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1872 switch (instr
->def
.bit_size
) {
1874 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1875 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1879 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1880 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1884 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1885 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1889 assert(devinfo
->gen
>= 7);
1890 if (devinfo
->gen
== 7) {
1891 /* We don't get 64-bit integer types until gen8 */
1892 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1893 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1894 setup_imm_df(bld
, instr
->value
[i
].f64
));
1897 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1898 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1903 unreachable("Invalid bit size");
1906 nir_ssa_values
[instr
->def
.index
] = reg
;
1910 fs_visitor::get_nir_src(const nir_src
&src
)
1914 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1915 const brw_reg_type reg_type
=
1916 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1917 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1919 reg
= nir_ssa_values
[src
.ssa
->index
];
1922 /* We don't handle indirects on locals */
1923 assert(src
.reg
.indirect
== NULL
);
1924 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1925 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1928 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1929 /* The only 64-bit type available on gen7 is DF, so use that. */
1930 reg
.type
= BRW_REGISTER_TYPE_DF
;
1932 /* To avoid floating-point denorm flushing problems, set the type by
1933 * default to an integer type - instructions that need floating point
1934 * semantics will set this to F if they need to
1936 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1937 BRW_REGISTER_TYPE_D
);
1944 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1946 * This function should not be called on any value which may be 64 bits.
1947 * We could theoretically support 64-bit on gen8+ but we choose not to
1948 * because it wouldn't work in general (no gen7 support) and there are
1949 * enough restrictions in 64-bit immediates that you can't take the return
1950 * value and treat it the same as the result of get_nir_src().
1953 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1955 assert(nir_src_bit_size(src
) == 32);
1956 return nir_src_is_const(src
) ?
1957 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1961 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1964 const brw_reg_type reg_type
=
1965 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1966 dest
.ssa
.bit_size
== 8 ?
1967 BRW_REGISTER_TYPE_D
:
1968 BRW_REGISTER_TYPE_F
);
1969 nir_ssa_values
[dest
.ssa
.index
] =
1970 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1971 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
1972 return nir_ssa_values
[dest
.ssa
.index
];
1974 /* We don't handle indirects on locals */
1975 assert(dest
.reg
.indirect
== NULL
);
1976 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1977 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1982 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1985 for (unsigned i
= 0; i
< 4; i
++) {
1986 if (!((wr_mask
>> i
) & 1))
1989 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1990 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1991 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1992 if (new_inst
->src
[j
].file
== VGRF
)
1993 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2000 emit_pixel_interpolater_send(const fs_builder
&bld
,
2005 glsl_interp_mode interpolation
)
2007 struct brw_wm_prog_data
*wm_prog_data
=
2008 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2010 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2011 /* 2 floats per slot returned */
2012 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2013 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2015 wm_prog_data
->pulls_bary
= true;
2021 * Computes 1 << x, given a D/UD register containing some value x.
2024 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2026 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2028 fs_reg result
= bld
.vgrf(x
.type
, 1);
2029 fs_reg one
= bld
.vgrf(x
.type
, 1);
2031 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2032 bld
.SHL(result
, one
, x
);
2037 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2039 assert(stage
== MESA_SHADER_GEOMETRY
);
2041 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2043 if (gs_compile
->control_data_header_size_bits
== 0)
2046 /* We can only do EndPrimitive() functionality when the control data
2047 * consists of cut bits. Fortunately, the only time it isn't is when the
2048 * output type is points, in which case EndPrimitive() is a no-op.
2050 if (gs_prog_data
->control_data_format
!=
2051 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2055 /* Cut bits use one bit per vertex. */
2056 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2058 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2059 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2061 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2062 * vertex n, 0 otherwise. So all we need to do here is mark bit
2063 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2064 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2065 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2067 * Note that if EndPrimitive() is called before emitting any vertices, this
2068 * will cause us to set bit 31 of the control_data_bits register to 1.
2069 * That's fine because:
2071 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2072 * output, so the hardware will ignore cut bit 31.
2074 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2075 * last vertex, so setting cut bit 31 has no effect (since the primitive
2076 * is automatically ended when the GS terminates).
2078 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2079 * control_data_bits register to 0 when the first vertex is emitted.
2082 const fs_builder abld
= bld
.annotate("end primitive");
2084 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2085 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2086 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2087 fs_reg mask
= intexp2(abld
, prev_count
);
2088 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2089 * attention to the lower 5 bits of its second source argument, so on this
2090 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2091 * ((vertex_count - 1) % 32).
2093 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2097 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2099 assert(stage
== MESA_SHADER_GEOMETRY
);
2100 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2102 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2104 const fs_builder abld
= bld
.annotate("emit control data bits");
2105 const fs_builder fwa_bld
= bld
.exec_all();
2107 /* We use a single UD register to accumulate control data bits (32 bits
2108 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2111 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2112 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2113 * use the Channel Mask phase to enable/disable which DWord within that
2114 * group to write. (Remember, different SIMD8 channels may have emitted
2115 * different numbers of vertices, so we may need per-slot offsets.)
2117 * Channel masking presents an annoying problem: we may have to replicate
2118 * the data up to 4 times:
2120 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2122 * To avoid penalizing shaders that emit a small number of vertices, we
2123 * can avoid these sometimes: if the size of the control data header is
2124 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2125 * land in the same 128-bit group, so we can skip per-slot offsets.
2127 * Similarly, if the control data header is <= 32 bits, there is only one
2128 * DWord, so we can skip channel masks.
2130 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2132 fs_reg channel_mask
, per_slot_offset
;
2134 if (gs_compile
->control_data_header_size_bits
> 32) {
2135 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2136 channel_mask
= vgrf(glsl_type::uint_type
);
2139 if (gs_compile
->control_data_header_size_bits
> 128) {
2140 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2141 per_slot_offset
= vgrf(glsl_type::uint_type
);
2144 /* Figure out which DWord we're trying to write to using the formula:
2146 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2148 * Since bits_per_vertex is a power of two, and is known at compile
2149 * time, this can be optimized to:
2151 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2153 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2154 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2155 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2156 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2157 unsigned log2_bits_per_vertex
=
2158 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2159 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2161 if (per_slot_offset
.file
!= BAD_FILE
) {
2162 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2163 * the appropriate OWord within the control data header.
2165 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2168 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2169 * write to the appropriate DWORD within the OWORD.
2171 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2172 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2173 channel_mask
= intexp2(fwa_bld
, channel
);
2174 /* Then the channel masks need to be in bits 23:16. */
2175 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2178 /* Store the control data bits in the message payload and send it. */
2180 if (channel_mask
.file
!= BAD_FILE
)
2181 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2182 if (per_slot_offset
.file
!= BAD_FILE
)
2185 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2186 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2188 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2189 if (per_slot_offset
.file
!= BAD_FILE
)
2190 sources
[i
++] = per_slot_offset
;
2191 if (channel_mask
.file
!= BAD_FILE
)
2192 sources
[i
++] = channel_mask
;
2194 sources
[i
++] = this->control_data_bits
;
2197 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2198 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2200 /* We need to increment Global Offset by 256-bits to make room for
2201 * Broadwell's extra "Vertex Count" payload at the beginning of the
2202 * URB entry. Since this is an OWord message, Global Offset is counted
2203 * in 128-bit units, so we must set it to 2.
2205 if (gs_prog_data
->static_vertex_count
== -1)
2210 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2213 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2215 /* Note: we are calling this *before* increasing vertex_count, so
2216 * this->vertex_count == vertex_count - 1 in the formula above.
2219 /* Stream mode uses 2 bits per vertex */
2220 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2222 /* Must be a valid stream */
2223 assert(stream_id
< MAX_VERTEX_STREAMS
);
2225 /* Control data bits are initialized to 0 so we don't have to set any
2226 * bits when sending vertices to stream 0.
2231 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2233 /* reg::sid = stream_id */
2234 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2235 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2237 /* reg:shift_count = 2 * (vertex_count - 1) */
2238 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2239 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2241 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2242 * attention to the lower 5 bits of its second source argument, so on this
2243 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2244 * stream_id << ((2 * (vertex_count - 1)) % 32).
2246 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2247 abld
.SHL(mask
, sid
, shift_count
);
2248 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2252 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2255 assert(stage
== MESA_SHADER_GEOMETRY
);
2257 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2259 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2260 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2262 /* Haswell and later hardware ignores the "Render Stream Select" bits
2263 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2264 * and instead sends all primitives down the pipeline for rasterization.
2265 * If the SOL stage is enabled, "Render Stream Select" is honored and
2266 * primitives bound to non-zero streams are discarded after stream output.
2268 * Since the only purpose of primives sent to non-zero streams is to
2269 * be recorded by transform feedback, we can simply discard all geometry
2270 * bound to these streams when transform feedback is disabled.
2272 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2275 /* If we're outputting 32 control data bits or less, then we can wait
2276 * until the shader is over to output them all. Otherwise we need to
2277 * output them as we go. Now is the time to do it, since we're about to
2278 * output the vertex_count'th vertex, so it's guaranteed that the
2279 * control data bits associated with the (vertex_count - 1)th vertex are
2282 if (gs_compile
->control_data_header_size_bits
> 32) {
2283 const fs_builder abld
=
2284 bld
.annotate("emit vertex: emit control data bits");
2286 /* Only emit control data bits if we've finished accumulating a batch
2287 * of 32 bits. This is the case when:
2289 * (vertex_count * bits_per_vertex) % 32 == 0
2291 * (in other words, when the last 5 bits of vertex_count *
2292 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2293 * integer n (which is always the case, since bits_per_vertex is
2294 * always 1 or 2), this is equivalent to requiring that the last 5-n
2295 * bits of vertex_count are 0:
2297 * vertex_count & (2^(5-n) - 1) == 0
2299 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2302 * vertex_count & (32 / bits_per_vertex - 1) == 0
2304 * TODO: If vertex_count is an immediate, we could do some of this math
2305 * at compile time...
2308 abld
.AND(bld
.null_reg_d(), vertex_count
,
2309 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2310 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2312 abld
.IF(BRW_PREDICATE_NORMAL
);
2313 /* If vertex_count is 0, then no control data bits have been
2314 * accumulated yet, so we can skip emitting them.
2316 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2317 BRW_CONDITIONAL_NEQ
);
2318 abld
.IF(BRW_PREDICATE_NORMAL
);
2319 emit_gs_control_data_bits(vertex_count
);
2320 abld
.emit(BRW_OPCODE_ENDIF
);
2322 /* Reset control_data_bits to 0 so we can start accumulating a new
2325 * Note: in the case where vertex_count == 0, this neutralizes the
2326 * effect of any call to EndPrimitive() that the shader may have
2327 * made before outputting its first vertex.
2329 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2330 inst
->force_writemask_all
= true;
2331 abld
.emit(BRW_OPCODE_ENDIF
);
2334 emit_urb_writes(vertex_count
);
2336 /* In stream mode we have to set control data bits for all vertices
2337 * unless we have disabled control data bits completely (which we do
2338 * do for GL_POINTS outputs that don't use streams).
2340 if (gs_compile
->control_data_header_size_bits
> 0 &&
2341 gs_prog_data
->control_data_format
==
2342 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2343 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2348 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2349 const nir_src
&vertex_src
,
2350 unsigned base_offset
,
2351 const nir_src
&offset_src
,
2352 unsigned num_components
,
2353 unsigned first_component
)
2355 assert(type_sz(dst
.type
) == 4);
2356 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2357 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2359 /* TODO: figure out push input layout for invocations == 1 */
2360 if (gs_prog_data
->invocations
== 1 &&
2361 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2362 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2363 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2364 nir_src_as_uint(vertex_src
) * push_reg_count
;
2365 for (unsigned i
= 0; i
< num_components
; i
++) {
2366 bld
.MOV(offset(dst
, bld
, i
),
2367 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2372 /* Resort to the pull model. Ensure the VUE handles are provided. */
2373 assert(gs_prog_data
->base
.include_vue_handles
);
2375 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2376 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2378 if (gs_prog_data
->invocations
== 1) {
2379 if (nir_src_is_const(vertex_src
)) {
2380 /* The vertex index is constant; just select the proper URB handle. */
2382 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2383 BRW_REGISTER_TYPE_UD
);
2385 /* The vertex index is non-constant. We need to use indirect
2386 * addressing to fetch the proper URB handle.
2388 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2389 * indicating that channel <n> should read the handle from
2390 * DWord <n>. We convert that to bytes by multiplying by 4.
2392 * Next, we convert the vertex index to bytes by multiplying
2393 * by 32 (shifting by 5), and add the two together. This is
2394 * the final indirect byte offset.
2396 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2397 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2398 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2399 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2401 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2402 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2403 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2404 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2405 /* Convert vertex_index to bytes (multiply by 32) */
2406 bld
.SHL(vertex_offset_bytes
,
2407 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2409 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2411 /* Use first_icp_handle as the base offset. There is one register
2412 * of URB handles per vertex, so inform the register allocator that
2413 * we might read up to nir->info.gs.vertices_in registers.
2415 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2416 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2417 fs_reg(icp_offset_bytes
),
2418 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2421 assert(gs_prog_data
->invocations
> 1);
2423 if (nir_src_is_const(vertex_src
)) {
2424 unsigned vertex
= nir_src_as_uint(vertex_src
);
2425 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2427 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2428 BRW_REGISTER_TYPE_UD
));
2430 /* The vertex index is non-constant. We need to use indirect
2431 * addressing to fetch the proper URB handle.
2434 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2436 /* Convert vertex_index to bytes (multiply by 4) */
2437 bld
.SHL(icp_offset_bytes
,
2438 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2441 /* Use first_icp_handle as the base offset. There is one DWord
2442 * of URB handles per vertex, so inform the register allocator that
2443 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2445 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2446 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2447 fs_reg(icp_offset_bytes
),
2448 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2454 fs_reg indirect_offset
= get_nir_src(offset_src
);
2456 if (nir_src_is_const(offset_src
)) {
2457 /* Constant indexing - use global offset. */
2458 if (first_component
!= 0) {
2459 unsigned read_components
= num_components
+ first_component
;
2460 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2461 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2462 inst
->size_written
= read_components
*
2463 tmp
.component_size(inst
->exec_size
);
2464 for (unsigned i
= 0; i
< num_components
; i
++) {
2465 bld
.MOV(offset(dst
, bld
, i
),
2466 offset(tmp
, bld
, i
+ first_component
));
2469 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2470 inst
->size_written
= num_components
*
2471 dst
.component_size(inst
->exec_size
);
2473 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2476 /* Indirect indexing - use per-slot offsets as well. */
2477 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2478 unsigned read_components
= num_components
+ first_component
;
2479 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2480 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2481 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2482 if (first_component
!= 0) {
2483 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2485 inst
->size_written
= read_components
*
2486 tmp
.component_size(inst
->exec_size
);
2487 for (unsigned i
= 0; i
< num_components
; i
++) {
2488 bld
.MOV(offset(dst
, bld
, i
),
2489 offset(tmp
, bld
, i
+ first_component
));
2492 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2493 inst
->size_written
= num_components
*
2494 dst
.component_size(inst
->exec_size
);
2496 inst
->offset
= base_offset
;
2502 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2504 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2506 if (nir_src_is_const(*offset_src
)) {
2507 /* The only constant offset we should find is 0. brw_nir.c's
2508 * add_const_offset_to_base() will fold other constant offsets
2509 * into instr->const_index[0].
2511 assert(nir_src_as_uint(*offset_src
) == 0);
2515 return get_nir_src(*offset_src
);
2519 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2520 nir_intrinsic_instr
*instr
)
2522 assert(stage
== MESA_SHADER_VERTEX
);
2525 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2526 dest
= get_nir_dest(instr
->dest
);
2528 switch (instr
->intrinsic
) {
2529 case nir_intrinsic_load_vertex_id
:
2530 case nir_intrinsic_load_base_vertex
:
2531 unreachable("should be lowered by nir_lower_system_values()");
2533 case nir_intrinsic_load_input
: {
2534 assert(nir_dest_bit_size(instr
->dest
) == 32);
2535 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2536 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2537 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2539 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2540 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2544 case nir_intrinsic_load_vertex_id_zero_base
:
2545 case nir_intrinsic_load_instance_id
:
2546 case nir_intrinsic_load_base_instance
:
2547 case nir_intrinsic_load_draw_id
:
2548 case nir_intrinsic_load_first_vertex
:
2549 case nir_intrinsic_load_is_indexed_draw
:
2550 unreachable("lowered by brw_nir_lower_vs_inputs");
2553 nir_emit_intrinsic(bld
, instr
);
2559 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2560 nir_intrinsic_instr
*instr
)
2562 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2563 const nir_src
&vertex_src
= instr
->src
[0];
2564 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2567 if (nir_src_is_const(vertex_src
)) {
2568 /* Emit a MOV to resolve <0,1,0> regioning. */
2569 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2570 unsigned vertex
= nir_src_as_uint(vertex_src
);
2572 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2573 BRW_REGISTER_TYPE_UD
));
2574 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2575 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2576 /* For the common case of only 1 instance, an array index of
2577 * gl_InvocationID means reading g1. Skip all the indirect work.
2579 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2581 /* The vertex index is non-constant. We need to use indirect
2582 * addressing to fetch the proper URB handle.
2584 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2586 /* Each ICP handle is a single DWord (4 bytes) */
2587 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2588 bld
.SHL(vertex_offset_bytes
,
2589 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2592 /* Start at g1. We might read up to 4 registers. */
2593 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2594 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2595 brw_imm_ud(4 * REG_SIZE
));
2602 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2603 nir_intrinsic_instr
*instr
)
2605 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2606 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2607 const nir_src
&vertex_src
= instr
->src
[0];
2609 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2611 if (nir_src_is_const(vertex_src
)) {
2612 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2613 nir_src_as_uint(vertex_src
), 0),
2614 BRW_REGISTER_TYPE_UD
));
2617 /* The vertex index is non-constant. We need to use indirect
2618 * addressing to fetch the proper URB handle.
2620 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2621 * indicating that channel <n> should read the handle from
2622 * DWord <n>. We convert that to bytes by multiplying by 4.
2624 * Next, we convert the vertex index to bytes by multiplying
2625 * by 32 (shifting by 5), and add the two together. This is
2626 * the final indirect byte offset.
2628 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2629 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2630 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2631 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2632 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2634 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2635 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2636 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2637 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2638 /* Convert vertex_index to bytes (multiply by 32) */
2639 bld
.SHL(vertex_offset_bytes
,
2640 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2642 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2644 /* Use first_icp_handle as the base offset. There is one register
2645 * of URB handles per vertex, so inform the register allocator that
2646 * we might read up to nir->info.gs.vertices_in registers.
2648 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2649 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2650 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2656 fs_visitor::get_tcs_output_urb_handle()
2658 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2660 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2661 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2663 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2664 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2669 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2670 nir_intrinsic_instr
*instr
)
2672 assert(stage
== MESA_SHADER_TESS_CTRL
);
2673 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2674 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2675 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2678 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2681 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2682 dst
= get_nir_dest(instr
->dest
);
2684 switch (instr
->intrinsic
) {
2685 case nir_intrinsic_load_primitive_id
:
2686 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2687 : brw_vec1_grf(0, 1)));
2689 case nir_intrinsic_load_invocation_id
:
2690 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2692 case nir_intrinsic_load_patch_vertices_in
:
2693 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2694 brw_imm_d(tcs_key
->input_vertices
));
2697 case nir_intrinsic_barrier
: {
2698 if (tcs_prog_data
->instances
== 1)
2701 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2702 fs_reg m0_2
= component(m0
, 2);
2704 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2706 /* Zero the message header */
2707 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2709 if (devinfo
->gen
< 11) {
2710 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2711 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2712 brw_imm_ud(INTEL_MASK(16, 13)));
2714 /* Shift it up to bits 27:24. */
2715 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2717 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2718 brw_imm_ud(INTEL_MASK(30, 24)));
2721 /* Set the Barrier Count and the enable bit */
2722 if (devinfo
->gen
< 11) {
2723 chanbld
.OR(m0_2
, m0_2
,
2724 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2726 chanbld
.OR(m0_2
, m0_2
,
2727 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2730 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2734 case nir_intrinsic_load_input
:
2735 unreachable("nir_lower_io should never give us these.");
2738 case nir_intrinsic_load_per_vertex_input
: {
2739 assert(nir_dest_bit_size(instr
->dest
) == 32);
2740 fs_reg indirect_offset
= get_indirect_offset(instr
);
2741 unsigned imm_offset
= instr
->const_index
[0];
2745 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2746 : get_tcs_single_patch_icp_handle(bld
, instr
);
2748 /* We can only read two double components with each URB read, so
2749 * we send two read messages in that case, each one loading up to
2750 * two double components.
2752 unsigned num_components
= instr
->num_components
;
2753 unsigned first_component
= nir_intrinsic_component(instr
);
2755 if (indirect_offset
.file
== BAD_FILE
) {
2756 /* Constant indexing - use global offset. */
2757 if (first_component
!= 0) {
2758 unsigned read_components
= num_components
+ first_component
;
2759 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2760 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2761 for (unsigned i
= 0; i
< num_components
; i
++) {
2762 bld
.MOV(offset(dst
, bld
, i
),
2763 offset(tmp
, bld
, i
+ first_component
));
2766 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2768 inst
->offset
= imm_offset
;
2771 /* Indirect indexing - use per-slot offsets as well. */
2772 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2773 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2774 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2775 if (first_component
!= 0) {
2776 unsigned read_components
= num_components
+ first_component
;
2777 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2778 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2780 for (unsigned i
= 0; i
< num_components
; i
++) {
2781 bld
.MOV(offset(dst
, bld
, i
),
2782 offset(tmp
, bld
, i
+ first_component
));
2785 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2788 inst
->offset
= imm_offset
;
2791 inst
->size_written
= (num_components
+ first_component
) *
2792 inst
->dst
.component_size(inst
->exec_size
);
2794 /* Copy the temporary to the destination to deal with writemasking.
2796 * Also attempt to deal with gl_PointSize being in the .w component.
2798 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2799 assert(type_sz(dst
.type
) == 4);
2800 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2801 inst
->size_written
= 4 * REG_SIZE
;
2802 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2807 case nir_intrinsic_load_output
:
2808 case nir_intrinsic_load_per_vertex_output
: {
2809 assert(nir_dest_bit_size(instr
->dest
) == 32);
2810 fs_reg indirect_offset
= get_indirect_offset(instr
);
2811 unsigned imm_offset
= instr
->const_index
[0];
2812 unsigned first_component
= nir_intrinsic_component(instr
);
2814 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2817 if (indirect_offset
.file
== BAD_FILE
) {
2818 /* This MOV replicates the output handle to all enabled channels
2819 * is SINGLE_PATCH mode.
2821 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2822 bld
.MOV(patch_handle
, output_handles
);
2825 if (first_component
!= 0) {
2826 unsigned read_components
=
2827 instr
->num_components
+ first_component
;
2828 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2829 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2831 inst
->size_written
= read_components
* REG_SIZE
;
2832 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2833 bld
.MOV(offset(dst
, bld
, i
),
2834 offset(tmp
, bld
, i
+ first_component
));
2837 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2839 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2841 inst
->offset
= imm_offset
;
2845 /* Indirect indexing - use per-slot offsets as well. */
2846 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2847 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2848 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2849 if (first_component
!= 0) {
2850 unsigned read_components
=
2851 instr
->num_components
+ first_component
;
2852 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2853 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2855 inst
->size_written
= read_components
* REG_SIZE
;
2856 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2857 bld
.MOV(offset(dst
, bld
, i
),
2858 offset(tmp
, bld
, i
+ first_component
));
2861 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2863 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2865 inst
->offset
= imm_offset
;
2871 case nir_intrinsic_store_output
:
2872 case nir_intrinsic_store_per_vertex_output
: {
2873 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2874 fs_reg value
= get_nir_src(instr
->src
[0]);
2875 fs_reg indirect_offset
= get_indirect_offset(instr
);
2876 unsigned imm_offset
= instr
->const_index
[0];
2877 unsigned mask
= instr
->const_index
[1];
2878 unsigned header_regs
= 0;
2879 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2882 srcs
[header_regs
++] = output_handles
;
2884 if (indirect_offset
.file
!= BAD_FILE
) {
2885 srcs
[header_regs
++] = indirect_offset
;
2891 unsigned num_components
= util_last_bit(mask
);
2894 /* We can only pack two 64-bit components in a single message, so send
2895 * 2 messages if we have more components
2897 unsigned first_component
= nir_intrinsic_component(instr
);
2898 mask
= mask
<< first_component
;
2900 if (mask
!= WRITEMASK_XYZW
) {
2901 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2902 opcode
= indirect_offset
.file
!= BAD_FILE
?
2903 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2904 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2906 opcode
= indirect_offset
.file
!= BAD_FILE
?
2907 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2908 SHADER_OPCODE_URB_WRITE_SIMD8
;
2911 for (unsigned i
= 0; i
< num_components
; i
++) {
2912 if (!(mask
& (1 << (i
+ first_component
))))
2915 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2918 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2920 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2921 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2923 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2924 inst
->offset
= imm_offset
;
2930 nir_emit_intrinsic(bld
, instr
);
2936 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2937 nir_intrinsic_instr
*instr
)
2939 assert(stage
== MESA_SHADER_TESS_EVAL
);
2940 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2943 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2944 dest
= get_nir_dest(instr
->dest
);
2946 switch (instr
->intrinsic
) {
2947 case nir_intrinsic_load_primitive_id
:
2948 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2950 case nir_intrinsic_load_tess_coord
:
2951 /* gl_TessCoord is part of the payload in g1-3 */
2952 for (unsigned i
= 0; i
< 3; i
++) {
2953 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2957 case nir_intrinsic_load_input
:
2958 case nir_intrinsic_load_per_vertex_input
: {
2959 assert(nir_dest_bit_size(instr
->dest
) == 32);
2960 fs_reg indirect_offset
= get_indirect_offset(instr
);
2961 unsigned imm_offset
= instr
->const_index
[0];
2962 unsigned first_component
= nir_intrinsic_component(instr
);
2965 if (indirect_offset
.file
== BAD_FILE
) {
2966 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2967 * which is 16 registers (since each holds 2 vec4 slots).
2969 const unsigned max_push_slots
= 32;
2970 if (imm_offset
< max_push_slots
) {
2971 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2972 for (int i
= 0; i
< instr
->num_components
; i
++) {
2973 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
2974 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2977 tes_prog_data
->base
.urb_read_length
=
2978 MAX2(tes_prog_data
->base
.urb_read_length
,
2979 (imm_offset
/ 2) + 1);
2981 /* Replicate the patch handle to all enabled channels */
2982 const fs_reg srcs
[] = {
2983 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2985 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2986 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2988 if (first_component
!= 0) {
2989 unsigned read_components
=
2990 instr
->num_components
+ first_component
;
2991 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2992 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2994 inst
->size_written
= read_components
* REG_SIZE
;
2995 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2996 bld
.MOV(offset(dest
, bld
, i
),
2997 offset(tmp
, bld
, i
+ first_component
));
3000 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3002 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3005 inst
->offset
= imm_offset
;
3008 /* Indirect indexing - use per-slot offsets as well. */
3010 /* We can only read two double components with each URB read, so
3011 * we send two read messages in that case, each one loading up to
3012 * two double components.
3014 unsigned num_components
= instr
->num_components
;
3015 const fs_reg srcs
[] = {
3016 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3019 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3020 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3022 if (first_component
!= 0) {
3023 unsigned read_components
=
3024 num_components
+ first_component
;
3025 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3026 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3028 for (unsigned i
= 0; i
< num_components
; i
++) {
3029 bld
.MOV(offset(dest
, bld
, i
),
3030 offset(tmp
, bld
, i
+ first_component
));
3033 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3037 inst
->offset
= imm_offset
;
3038 inst
->size_written
= (num_components
+ first_component
) *
3039 inst
->dst
.component_size(inst
->exec_size
);
3044 nir_emit_intrinsic(bld
, instr
);
3050 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3051 nir_intrinsic_instr
*instr
)
3053 assert(stage
== MESA_SHADER_GEOMETRY
);
3054 fs_reg indirect_offset
;
3057 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3058 dest
= get_nir_dest(instr
->dest
);
3060 switch (instr
->intrinsic
) {
3061 case nir_intrinsic_load_primitive_id
:
3062 assert(stage
== MESA_SHADER_GEOMETRY
);
3063 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3064 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3065 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3068 case nir_intrinsic_load_input
:
3069 unreachable("load_input intrinsics are invalid for the GS stage");
3071 case nir_intrinsic_load_per_vertex_input
:
3072 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3073 instr
->src
[1], instr
->num_components
,
3074 nir_intrinsic_component(instr
));
3077 case nir_intrinsic_emit_vertex_with_counter
:
3078 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3081 case nir_intrinsic_end_primitive_with_counter
:
3082 emit_gs_end_primitive(instr
->src
[0]);
3085 case nir_intrinsic_set_vertex_count
:
3086 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3089 case nir_intrinsic_load_invocation_id
: {
3090 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3091 assert(val
.file
!= BAD_FILE
);
3092 dest
.type
= val
.type
;
3098 nir_emit_intrinsic(bld
, instr
);
3104 * Fetch the current render target layer index.
3107 fetch_render_target_array_index(const fs_builder
&bld
)
3109 if (bld
.shader
->devinfo
->gen
>= 6) {
3110 /* The render target array index is provided in the thread payload as
3111 * bits 26:16 of r0.0.
3113 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3114 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3118 /* Pre-SNB we only ever render into the first layer of the framebuffer
3119 * since layered rendering is not implemented.
3121 return brw_imm_ud(0);
3126 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3127 * framebuffer at the current fragment coordinates and sample index.
3130 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3133 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3135 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3136 const brw_wm_prog_key
*wm_key
=
3137 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3138 assert(!wm_key
->coherent_fb_fetch
);
3139 const struct brw_wm_prog_data
*wm_prog_data
=
3140 brw_wm_prog_data(stage_prog_data
);
3142 /* Calculate the surface index relative to the start of the texture binding
3143 * table block, since that's what the texturing messages expect.
3145 const unsigned surface
= target
+
3146 wm_prog_data
->binding_table
.render_target_read_start
-
3147 wm_prog_data
->base
.binding_table
.texture_start
;
3149 /* Calculate the fragment coordinates. */
3150 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3151 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3152 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3153 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3155 /* Calculate the sample index and MCS payload when multisampling. Luckily
3156 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3157 * shouldn't be necessary to recompile based on whether the framebuffer is
3160 if (wm_key
->multisample_fbo
&&
3161 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3162 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3164 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3165 const fs_reg mcs
= wm_key
->multisample_fbo
?
3166 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3168 /* Use either a normal or a CMS texel fetch message depending on whether
3169 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3170 * message just in case the framebuffer uses 16x multisampling, it should
3171 * be equivalent to the normal CMS fetch for lower multisampling modes.
3173 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3174 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3175 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3177 /* Emit the instruction. */
3178 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3179 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3180 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3181 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3182 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3183 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3184 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3185 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3186 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3188 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3189 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3195 * Actual coherent framebuffer read implemented using the native render target
3196 * read message. Requires SKL+.
3199 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3201 assert(bld
.shader
->devinfo
->gen
>= 9);
3202 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3203 inst
->target
= target
;
3204 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3210 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3212 if (n
&& regs
[0].file
!= BAD_FILE
) {
3216 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3218 for (unsigned i
= 0; i
< n
; i
++)
3226 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3228 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3229 const brw_wm_prog_key
*const key
=
3230 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3231 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3232 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3234 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3235 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3237 else if (l
== FRAG_RESULT_COLOR
)
3238 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3239 MAX2(key
->nr_color_regions
, 1));
3241 else if (l
== FRAG_RESULT_DEPTH
)
3242 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3244 else if (l
== FRAG_RESULT_STENCIL
)
3245 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3247 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3248 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3250 else if (l
>= FRAG_RESULT_DATA0
&&
3251 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3252 return alloc_temporary(v
->bld
, 4,
3253 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3256 unreachable("Invalid location");
3259 /* Annoyingly, we get the barycentrics into the shader in a layout that's
3260 * optimized for PLN but it doesn't work nearly as well as one would like for
3261 * manual interpolation.
3264 shuffle_from_pln_layout(const fs_builder
&bld
, fs_reg dest
, fs_reg pln_data
)
3266 dest
.type
= BRW_REGISTER_TYPE_F
;
3267 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3268 const fs_reg dest_u
= offset(dest
, bld
, 0);
3269 const fs_reg dest_v
= offset(dest
, bld
, 1);
3271 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3272 const fs_builder gbld
= bld
.group(8, g
);
3273 gbld
.MOV(horiz_offset(dest_u
, g
* 8),
3274 byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
));
3275 gbld
.MOV(horiz_offset(dest_v
, g
* 8),
3276 byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
));
3281 shuffle_to_pln_layout(const fs_builder
&bld
, fs_reg pln_data
, fs_reg src
)
3283 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3284 src
.type
= BRW_REGISTER_TYPE_F
;
3285 const fs_reg src_u
= offset(src
, bld
, 0);
3286 const fs_reg src_v
= offset(src
, bld
, 1);
3288 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3289 const fs_builder gbld
= bld
.group(8, g
);
3290 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
),
3291 horiz_offset(src_u
, g
* 8));
3292 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
),
3293 horiz_offset(src_v
, g
* 8));
3298 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3299 nir_intrinsic_instr
*instr
)
3301 assert(stage
== MESA_SHADER_FRAGMENT
);
3304 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3305 dest
= get_nir_dest(instr
->dest
);
3307 switch (instr
->intrinsic
) {
3308 case nir_intrinsic_load_front_face
:
3309 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3310 *emit_frontfacing_interpolation());
3313 case nir_intrinsic_load_sample_pos
: {
3314 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3315 assert(sample_pos
.file
!= BAD_FILE
);
3316 dest
.type
= sample_pos
.type
;
3317 bld
.MOV(dest
, sample_pos
);
3318 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3322 case nir_intrinsic_load_layer_id
:
3323 dest
.type
= BRW_REGISTER_TYPE_UD
;
3324 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3327 case nir_intrinsic_is_helper_invocation
: {
3328 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3329 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3330 * consideration demoted invocations. That information is stored in
3333 dest
.type
= BRW_REGISTER_TYPE_UD
;
3335 bld
.MOV(dest
, brw_imm_ud(0));
3337 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3338 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3339 mov
->predicate_inverse
= true;
3340 mov
->flag_subreg
= 1;
3344 case nir_intrinsic_load_helper_invocation
:
3345 case nir_intrinsic_load_sample_mask_in
:
3346 case nir_intrinsic_load_sample_id
: {
3347 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3348 fs_reg val
= nir_system_values
[sv
];
3349 assert(val
.file
!= BAD_FILE
);
3350 dest
.type
= val
.type
;
3355 case nir_intrinsic_store_output
: {
3356 const fs_reg src
= get_nir_src(instr
->src
[0]);
3357 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3358 const unsigned location
= nir_intrinsic_base(instr
) +
3359 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3360 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3363 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3364 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3365 offset(src
, bld
, j
));
3370 case nir_intrinsic_load_output
: {
3371 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3372 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3373 assert(l
>= FRAG_RESULT_DATA0
);
3374 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3375 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3376 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3378 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3379 emit_coherent_fb_read(bld
, tmp
, target
);
3381 emit_non_coherent_fb_read(bld
, tmp
, target
);
3383 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3384 bld
.MOV(offset(dest
, bld
, j
),
3385 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3391 case nir_intrinsic_demote
:
3392 case nir_intrinsic_discard
:
3393 case nir_intrinsic_demote_if
:
3394 case nir_intrinsic_discard_if
: {
3395 /* We track our discarded pixels in f0.1. By predicating on it, we can
3396 * update just the flag bits that aren't yet discarded. If there's no
3397 * condition, we emit a CMP of g0 != g0, so all currently executing
3398 * channels will get turned off.
3400 fs_inst
*cmp
= NULL
;
3401 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3402 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3403 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3406 alu
->op
!= nir_op_bcsel
&&
3407 alu
->op
!= nir_op_inot
) {
3408 /* Re-emit the instruction that generated the Boolean value, but
3409 * do not store it. Since this instruction will be conditional,
3410 * other instructions that want to use the real Boolean value may
3411 * get garbage. This was a problem for piglit's fs-discard-exit-2
3414 * Ideally we'd detect that the instruction cannot have a
3415 * conditional modifier before emitting the instructions. Alas,
3416 * that is nigh impossible. Instead, we're going to assume the
3417 * instruction (or last instruction) generated can have a
3418 * conditional modifier. If it cannot, fallback to the old-style
3419 * compare, and hope dead code elimination will clean up the
3420 * extra instructions generated.
3422 nir_emit_alu(bld
, alu
, false);
3424 cmp
= (fs_inst
*) instructions
.get_tail();
3425 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3426 if (cmp
->can_do_cmod())
3427 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3431 /* The old sequence that would have been generated is,
3432 * basically, bool_result == false. This is equivalent to
3433 * !bool_result, so negate the old modifier.
3435 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3440 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3441 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3444 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3445 BRW_REGISTER_TYPE_UW
));
3446 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3449 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3450 cmp
->flag_subreg
= 1;
3452 if (devinfo
->gen
>= 6) {
3453 /* Due to the way we implement discard, the jump will only happen
3454 * when the whole quad is discarded. So we can do this even for
3455 * demote as it won't break its uniformity promises.
3457 emit_discard_jump();
3460 limit_dispatch_width(16, "Fragment discard/demote not implemented in SIMD32 mode.");
3464 case nir_intrinsic_load_input
: {
3465 /* load_input is only used for flat inputs */
3466 assert(nir_dest_bit_size(instr
->dest
) == 32);
3467 unsigned base
= nir_intrinsic_base(instr
);
3468 unsigned comp
= nir_intrinsic_component(instr
);
3469 unsigned num_components
= instr
->num_components
;
3471 /* Special case fields in the VUE header */
3472 if (base
== VARYING_SLOT_LAYER
)
3474 else if (base
== VARYING_SLOT_VIEWPORT
)
3477 for (unsigned int i
= 0; i
< num_components
; i
++) {
3478 bld
.MOV(offset(dest
, bld
, i
),
3479 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3484 case nir_intrinsic_load_fs_input_interp_deltas
: {
3485 assert(stage
== MESA_SHADER_FRAGMENT
);
3486 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3487 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3488 nir_intrinsic_component(instr
));
3489 dest
.type
= BRW_REGISTER_TYPE_F
;
3490 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3491 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3492 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3496 case nir_intrinsic_load_barycentric_pixel
:
3497 case nir_intrinsic_load_barycentric_centroid
:
3498 case nir_intrinsic_load_barycentric_sample
: {
3499 /* Use the delta_xy values computed from the payload */
3500 const glsl_interp_mode interp_mode
=
3501 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3502 enum brw_barycentric_mode bary
=
3503 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3505 shuffle_from_pln_layout(bld
, dest
, this->delta_xy
[bary
]);
3509 case nir_intrinsic_load_barycentric_at_sample
: {
3510 const glsl_interp_mode interpolation
=
3511 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3513 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3514 if (nir_src_is_const(instr
->src
[0])) {
3515 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3517 emit_pixel_interpolater_send(bld
,
3518 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3521 brw_imm_ud(msg_data
),
3524 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3525 BRW_REGISTER_TYPE_UD
);
3527 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3528 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3529 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3530 bld
.exec_all().group(1, 0)
3531 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3532 emit_pixel_interpolater_send(bld
,
3533 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3539 /* Make a loop that sends a message to the pixel interpolater
3540 * for the sample number in each live channel. If there are
3541 * multiple channels with the same sample number then these
3542 * will be handled simultaneously with a single interation of
3545 bld
.emit(BRW_OPCODE_DO
);
3547 /* Get the next live sample number into sample_id_reg */
3548 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3550 /* Set the flag register so that we can perform the send
3551 * message on all channels that have the same sample number
3553 bld
.CMP(bld
.null_reg_ud(),
3554 sample_src
, sample_id
,
3555 BRW_CONDITIONAL_EQ
);
3556 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3557 bld
.exec_all().group(1, 0)
3558 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3560 emit_pixel_interpolater_send(bld
,
3561 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3564 component(msg_data
, 0),
3566 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3568 /* Continue the loop if there are any live channels left */
3569 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3571 bld
.emit(BRW_OPCODE_WHILE
));
3574 shuffle_from_pln_layout(bld
, dest
, tmp
);
3578 case nir_intrinsic_load_barycentric_at_offset
: {
3579 const glsl_interp_mode interpolation
=
3580 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3582 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3584 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3586 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3587 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3588 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3590 emit_pixel_interpolater_send(bld
,
3591 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3594 brw_imm_ud(off_x
| (off_y
<< 4)),
3597 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3598 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3599 BRW_REGISTER_TYPE_F
);
3600 for (int i
= 0; i
< 2; i
++) {
3601 fs_reg temp
= vgrf(glsl_type::float_type
);
3602 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3603 fs_reg itemp
= vgrf(glsl_type::int_type
);
3605 bld
.MOV(itemp
, temp
);
3607 /* Clamp the upper end of the range to +7/16.
3608 * ARB_gpu_shader5 requires that we support a maximum offset
3609 * of +0.5, which isn't representable in a S0.4 value -- if
3610 * we didn't clamp it, we'd end up with -8/16, which is the
3611 * opposite of what the shader author wanted.
3613 * This is legal due to ARB_gpu_shader5's quantization
3616 * "Not all values of <offset> may be supported; x and y
3617 * offsets may be rounded to fixed-point values with the
3618 * number of fraction bits given by the
3619 * implementation-dependent constant
3620 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3622 set_condmod(BRW_CONDITIONAL_L
,
3623 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3626 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3627 emit_pixel_interpolater_send(bld
,
3634 shuffle_from_pln_layout(bld
, dest
, tmp
);
3638 case nir_intrinsic_load_frag_coord
:
3639 emit_fragcoord_interpolation(dest
);
3642 case nir_intrinsic_load_interpolated_input
: {
3643 assert(instr
->src
[0].ssa
&&
3644 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3645 nir_intrinsic_instr
*bary_intrinsic
=
3646 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3647 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3648 enum glsl_interp_mode interp_mode
=
3649 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3652 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3653 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3654 /* Use the result of the PI message. Because the load_barycentric
3655 * intrinsics return a regular vec2 and we need it in PLN layout, we
3656 * have to do a translation. Fortunately, copy-prop cleans this up
3659 dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3660 shuffle_to_pln_layout(bld
, dst_xy
, get_nir_src(instr
->src
[0]));
3662 /* Use the delta_xy values computed from the payload */
3663 enum brw_barycentric_mode bary
=
3664 brw_barycentric_mode(interp_mode
, bary_intrin
);
3666 dst_xy
= this->delta_xy
[bary
];
3669 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3671 interp_reg(nir_intrinsic_base(instr
),
3672 nir_intrinsic_component(instr
) + i
);
3673 interp
.type
= BRW_REGISTER_TYPE_F
;
3674 dest
.type
= BRW_REGISTER_TYPE_F
;
3676 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3677 fs_reg tmp
= vgrf(glsl_type::float_type
);
3678 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3679 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3681 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3688 nir_emit_intrinsic(bld
, instr
);
3694 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3696 if (nir_src_is_const(instr
->src
[src
])) {
3697 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3700 else if (add_val
== -1)
3708 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3709 nir_intrinsic_instr
*instr
)
3711 assert(stage
== MESA_SHADER_COMPUTE
);
3712 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3715 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3716 dest
= get_nir_dest(instr
->dest
);
3718 switch (instr
->intrinsic
) {
3719 case nir_intrinsic_barrier
:
3721 cs_prog_data
->uses_barrier
= true;
3724 case nir_intrinsic_load_subgroup_id
:
3725 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3728 case nir_intrinsic_load_local_invocation_id
:
3729 case nir_intrinsic_load_work_group_id
: {
3730 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3731 fs_reg val
= nir_system_values
[sv
];
3732 assert(val
.file
!= BAD_FILE
);
3733 dest
.type
= val
.type
;
3734 for (unsigned i
= 0; i
< 3; i
++)
3735 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3739 case nir_intrinsic_load_num_work_groups
: {
3740 const unsigned surface
=
3741 cs_prog_data
->binding_table
.work_groups_start
;
3743 cs_prog_data
->uses_num_work_groups
= true;
3745 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3746 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3747 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3748 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3750 /* Read the 3 GLuint components of gl_NumWorkGroups */
3751 for (unsigned i
= 0; i
< 3; i
++) {
3752 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3753 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3754 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3759 case nir_intrinsic_shared_atomic_add
:
3760 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3762 case nir_intrinsic_shared_atomic_imin
:
3763 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3765 case nir_intrinsic_shared_atomic_umin
:
3766 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3768 case nir_intrinsic_shared_atomic_imax
:
3769 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3771 case nir_intrinsic_shared_atomic_umax
:
3772 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3774 case nir_intrinsic_shared_atomic_and
:
3775 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3777 case nir_intrinsic_shared_atomic_or
:
3778 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3780 case nir_intrinsic_shared_atomic_xor
:
3781 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3783 case nir_intrinsic_shared_atomic_exchange
:
3784 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3786 case nir_intrinsic_shared_atomic_comp_swap
:
3787 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3789 case nir_intrinsic_shared_atomic_fmin
:
3790 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3792 case nir_intrinsic_shared_atomic_fmax
:
3793 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3795 case nir_intrinsic_shared_atomic_fcomp_swap
:
3796 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3799 case nir_intrinsic_load_shared
: {
3800 assert(devinfo
->gen
>= 7);
3801 assert(stage
== MESA_SHADER_COMPUTE
);
3803 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3804 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3805 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3806 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3807 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3809 /* Make dest unsigned because that's what the temporary will be */
3810 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3812 /* Read the vector */
3813 if (nir_intrinsic_align(instr
) >= 4) {
3814 assert(nir_dest_bit_size(instr
->dest
) == 32);
3815 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3817 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3818 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3819 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3821 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3822 assert(nir_dest_num_components(instr
->dest
) == 1);
3823 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3825 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3826 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3827 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3828 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3833 case nir_intrinsic_store_shared
: {
3834 assert(devinfo
->gen
>= 7);
3835 assert(stage
== MESA_SHADER_COMPUTE
);
3837 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3838 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3839 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3840 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3841 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3843 fs_reg data
= get_nir_src(instr
->src
[0]);
3844 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3846 assert(nir_intrinsic_write_mask(instr
) ==
3847 (1u << instr
->num_components
) - 1);
3848 if (nir_intrinsic_align(instr
) >= 4) {
3849 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3850 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3851 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3852 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3853 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3854 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3856 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3857 assert(nir_src_num_components(instr
->src
[0]) == 1);
3858 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3860 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3861 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3863 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3864 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3870 nir_emit_intrinsic(bld
, instr
);
3876 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3877 nir_op op
, brw_reg_type type
)
3879 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3880 switch (type_sz(type
)) {
3882 assert(type
!= BRW_REGISTER_TYPE_HF
);
3883 return retype(brw_imm_uw(value
.u16
), type
);
3885 return retype(brw_imm_ud(value
.u32
), type
);
3887 if (type
== BRW_REGISTER_TYPE_DF
)
3888 return setup_imm_df(bld
, value
.f64
);
3890 return retype(brw_imm_u64(value
.u64
), type
);
3892 unreachable("Invalid type size");
3897 brw_op_for_nir_reduction_op(nir_op op
)
3900 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3901 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3902 case nir_op_imul
: return BRW_OPCODE_MUL
;
3903 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3904 case nir_op_imin
: return BRW_OPCODE_SEL
;
3905 case nir_op_umin
: return BRW_OPCODE_SEL
;
3906 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3907 case nir_op_imax
: return BRW_OPCODE_SEL
;
3908 case nir_op_umax
: return BRW_OPCODE_SEL
;
3909 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3910 case nir_op_iand
: return BRW_OPCODE_AND
;
3911 case nir_op_ior
: return BRW_OPCODE_OR
;
3912 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3914 unreachable("Invalid reduction operation");
3918 static brw_conditional_mod
3919 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3922 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3923 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3924 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3925 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3926 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3927 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3928 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3929 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3930 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3931 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3932 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3933 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3934 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3936 unreachable("Invalid reduction operation");
3941 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3942 nir_intrinsic_instr
*instr
)
3944 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3946 if (stage_prog_data
->binding_table
.image_start
> 0) {
3947 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3948 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3950 bld
.ADD(image
, image
,
3951 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3955 return bld
.emit_uniformize(image
);
3959 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3960 nir_intrinsic_instr
*instr
)
3962 /* SSBO stores are weird in that their index is in src[1] */
3963 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3966 if (nir_src_is_const(instr
->src
[src
])) {
3967 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3968 nir_src_as_uint(instr
->src
[src
]);
3969 surf_index
= brw_imm_ud(index
);
3971 surf_index
= vgrf(glsl_type::uint_type
);
3972 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3973 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3976 return bld
.emit_uniformize(surf_index
);
3980 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3982 switch (nir_intrinsic_image_dim(instr
)) {
3983 case GLSL_SAMPLER_DIM_1D
:
3984 return 1 + nir_intrinsic_image_array(instr
);
3985 case GLSL_SAMPLER_DIM_2D
:
3986 case GLSL_SAMPLER_DIM_RECT
:
3987 return 2 + nir_intrinsic_image_array(instr
);
3988 case GLSL_SAMPLER_DIM_3D
:
3989 case GLSL_SAMPLER_DIM_CUBE
:
3991 case GLSL_SAMPLER_DIM_BUF
:
3993 case GLSL_SAMPLER_DIM_MS
:
3994 return 2 + nir_intrinsic_image_array(instr
);
3996 unreachable("Invalid image dimension");
4001 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4004 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4005 dest
= get_nir_dest(instr
->dest
);
4007 switch (instr
->intrinsic
) {
4008 case nir_intrinsic_image_load
:
4009 case nir_intrinsic_image_store
:
4010 case nir_intrinsic_image_atomic_add
:
4011 case nir_intrinsic_image_atomic_min
:
4012 case nir_intrinsic_image_atomic_max
:
4013 case nir_intrinsic_image_atomic_and
:
4014 case nir_intrinsic_image_atomic_or
:
4015 case nir_intrinsic_image_atomic_xor
:
4016 case nir_intrinsic_image_atomic_exchange
:
4017 case nir_intrinsic_image_atomic_comp_swap
:
4018 case nir_intrinsic_bindless_image_load
:
4019 case nir_intrinsic_bindless_image_store
:
4020 case nir_intrinsic_bindless_image_atomic_add
:
4021 case nir_intrinsic_bindless_image_atomic_min
:
4022 case nir_intrinsic_bindless_image_atomic_max
:
4023 case nir_intrinsic_bindless_image_atomic_and
:
4024 case nir_intrinsic_bindless_image_atomic_or
:
4025 case nir_intrinsic_bindless_image_atomic_xor
:
4026 case nir_intrinsic_bindless_image_atomic_exchange
:
4027 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4028 if (stage
== MESA_SHADER_FRAGMENT
&&
4029 instr
->intrinsic
!= nir_intrinsic_image_load
)
4030 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4032 /* Get some metadata from the image intrinsic. */
4033 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4034 const GLenum format
= nir_intrinsic_format(instr
);
4036 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4038 switch (instr
->intrinsic
) {
4039 case nir_intrinsic_image_load
:
4040 case nir_intrinsic_image_store
:
4041 case nir_intrinsic_image_atomic_add
:
4042 case nir_intrinsic_image_atomic_min
:
4043 case nir_intrinsic_image_atomic_max
:
4044 case nir_intrinsic_image_atomic_and
:
4045 case nir_intrinsic_image_atomic_or
:
4046 case nir_intrinsic_image_atomic_xor
:
4047 case nir_intrinsic_image_atomic_exchange
:
4048 case nir_intrinsic_image_atomic_comp_swap
:
4049 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4050 get_nir_image_intrinsic_image(bld
, instr
);
4055 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4056 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4060 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4061 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4062 brw_imm_ud(image_intrinsic_coord_components(instr
));
4064 /* Emit an image load, store or atomic op. */
4065 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4066 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4067 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4069 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4070 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4071 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4072 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4073 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4074 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4075 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4076 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4077 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4080 unsigned num_srcs
= info
->num_srcs
;
4082 switch (instr
->intrinsic
) {
4083 case nir_intrinsic_image_atomic_add
:
4084 case nir_intrinsic_bindless_image_atomic_add
:
4085 assert(num_srcs
== 4);
4087 op
= get_op_for_atomic_add(instr
, 3);
4089 if (op
!= BRW_AOP_ADD
)
4092 case nir_intrinsic_image_atomic_min
:
4093 case nir_intrinsic_bindless_image_atomic_min
:
4094 assert(format
== GL_R32UI
|| format
== GL_R32I
);
4095 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
4097 case nir_intrinsic_image_atomic_max
:
4098 case nir_intrinsic_bindless_image_atomic_max
:
4099 assert(format
== GL_R32UI
|| format
== GL_R32I
);
4100 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
4102 case nir_intrinsic_image_atomic_and
:
4103 case nir_intrinsic_bindless_image_atomic_and
:
4106 case nir_intrinsic_image_atomic_or
:
4107 case nir_intrinsic_bindless_image_atomic_or
:
4110 case nir_intrinsic_image_atomic_xor
:
4111 case nir_intrinsic_bindless_image_atomic_xor
:
4114 case nir_intrinsic_image_atomic_exchange
:
4115 case nir_intrinsic_bindless_image_atomic_exchange
:
4118 case nir_intrinsic_image_atomic_comp_swap
:
4119 case nir_intrinsic_bindless_image_atomic_comp_swap
:
4123 unreachable("Not reachable.");
4126 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4130 data
= get_nir_src(instr
->src
[3]);
4131 if (num_srcs
>= 5) {
4132 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4133 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4134 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4137 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4139 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4140 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4145 case nir_intrinsic_image_size
:
4146 case nir_intrinsic_bindless_image_size
: {
4147 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4148 * into will handle the binding table index for us in the geneerator.
4149 * Incidentally, this means that we can handle bindless with exactly the
4152 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4153 BRW_REGISTER_TYPE_UD
);
4154 image
= bld
.emit_uniformize(image
);
4156 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4157 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4158 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4160 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4161 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4162 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4163 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4165 /* Since the image size is always uniform, we can just emit a SIMD8
4166 * query instruction and splat the result out.
4168 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4170 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4171 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4172 tmp
, srcs
, ARRAY_SIZE(srcs
));
4173 inst
->size_written
= 4 * REG_SIZE
;
4175 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4176 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4177 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4178 offset(retype(dest
, tmp
.type
), bld
, c
),
4179 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4181 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4182 component(offset(tmp
, ubld
, c
), 0));
4188 case nir_intrinsic_image_load_raw_intel
: {
4189 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4190 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4191 get_nir_image_intrinsic_image(bld
, instr
);
4192 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4193 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4194 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4197 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4198 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4199 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4203 case nir_intrinsic_image_store_raw_intel
: {
4204 if (stage
== MESA_SHADER_FRAGMENT
)
4205 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4207 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4208 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4209 get_nir_image_intrinsic_image(bld
, instr
);
4210 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4211 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4212 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4213 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4215 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4216 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4220 case nir_intrinsic_group_memory_barrier
:
4221 case nir_intrinsic_memory_barrier_shared
:
4222 case nir_intrinsic_memory_barrier_atomic_counter
:
4223 case nir_intrinsic_memory_barrier_buffer
:
4224 case nir_intrinsic_memory_barrier_image
:
4225 case nir_intrinsic_memory_barrier
: {
4226 bool l3_fence
, slm_fence
;
4227 if (devinfo
->gen
>= 11) {
4228 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4229 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4230 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4231 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4233 /* Prior to gen11, we only have one kind of fence. */
4238 /* Be conservative in Gen11+ and always stall in a fence. Since there
4239 * are two different fences, and shader might want to synchronize
4242 * TODO: Improve NIR so that scope and visibility information for the
4243 * barriers is available here to make a better decision.
4245 * TODO: When emitting more than one fence, it might help emit all
4246 * the fences first and then generate the stall moves.
4248 const bool stall
= devinfo
->gen
>= 11;
4250 const fs_builder ubld
= bld
.group(8, 0);
4251 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4254 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4255 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4256 /* bti */ brw_imm_ud(0))
4257 ->size_written
= 2 * REG_SIZE
;
4261 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4262 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4263 brw_imm_ud(GEN7_BTI_SLM
))
4264 ->size_written
= 2 * REG_SIZE
;
4270 case nir_intrinsic_shader_clock
: {
4271 /* We cannot do anything if there is an event, so ignore it for now */
4272 const fs_reg shader_clock
= get_timestamp(bld
);
4273 const fs_reg srcs
[] = { component(shader_clock
, 0),
4274 component(shader_clock
, 1) };
4275 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4279 case nir_intrinsic_image_samples
:
4280 /* The driver does not support multi-sampled images. */
4281 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4284 case nir_intrinsic_load_uniform
: {
4285 /* Offsets are in bytes but they should always aligned to
4288 assert(instr
->const_index
[0] % 4 == 0 ||
4289 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4291 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4293 if (nir_src_is_const(instr
->src
[0])) {
4294 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4295 assert(load_offset
% type_sz(dest
.type
) == 0);
4296 /* For 16-bit types we add the module of the const_index[0]
4297 * offset to access to not 32-bit aligned element
4299 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4301 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4302 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4305 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4306 BRW_REGISTER_TYPE_UD
);
4308 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4309 * go past the end of the uniform. In order to keep the n'th
4310 * component from running past, we subtract off the size of all but
4311 * one component of the vector.
4313 assert(instr
->const_index
[1] >=
4314 instr
->num_components
* (int) type_sz(dest
.type
));
4315 unsigned read_size
= instr
->const_index
[1] -
4316 (instr
->num_components
- 1) * type_sz(dest
.type
);
4318 bool supports_64bit_indirects
=
4319 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4321 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4322 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4323 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4324 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4325 indirect
, brw_imm_ud(read_size
));
4328 const unsigned num_mov_indirects
=
4329 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4330 /* We read a little bit less per MOV INDIRECT, as they are now
4331 * 32-bits ones instead of 64-bit. Fix read_size then.
4333 const unsigned read_size_32bit
= read_size
-
4334 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4335 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4336 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4337 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4338 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4339 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4340 indirect
, brw_imm_ud(read_size_32bit
));
4348 case nir_intrinsic_load_ubo
: {
4350 if (nir_src_is_const(instr
->src
[0])) {
4351 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4352 nir_src_as_uint(instr
->src
[0]);
4353 surf_index
= brw_imm_ud(index
);
4355 /* The block index is not a constant. Evaluate the index expression
4356 * per-channel and add the base UBO index; we have to select a value
4357 * from any live channel.
4359 surf_index
= vgrf(glsl_type::uint_type
);
4360 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4361 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4362 surf_index
= bld
.emit_uniformize(surf_index
);
4365 if (!nir_src_is_const(instr
->src
[1])) {
4366 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4367 BRW_REGISTER_TYPE_UD
);
4369 for (int i
= 0; i
< instr
->num_components
; i
++)
4370 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4371 base_offset
, i
* type_sz(dest
.type
));
4373 /* Even if we are loading doubles, a pull constant load will load
4374 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4375 * need to load a full dvec4 we will have to emit 2 loads. This is
4376 * similar to demote_pull_constants(), except that in that case we
4377 * see individual accesses to each component of the vector and then
4378 * we let CSE deal with duplicate loads. Here we see a vector access
4379 * and we have to split it if necessary.
4381 const unsigned type_size
= type_sz(dest
.type
);
4382 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4384 /* See if we've selected this as a push constant candidate */
4385 if (nir_src_is_const(instr
->src
[0])) {
4386 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4387 const unsigned offset_256b
= load_offset
/ 32;
4390 for (int i
= 0; i
< 4; i
++) {
4391 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4392 if (range
->block
== ubo_block
&&
4393 offset_256b
>= range
->start
&&
4394 offset_256b
< range
->start
+ range
->length
) {
4396 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4397 push_reg
.offset
= load_offset
- 32 * range
->start
;
4402 if (push_reg
.file
!= BAD_FILE
) {
4403 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4404 bld
.MOV(offset(dest
, bld
, i
),
4405 byte_offset(push_reg
, i
* type_size
));
4411 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4412 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4413 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4415 for (unsigned c
= 0; c
< instr
->num_components
;) {
4416 const unsigned base
= load_offset
+ c
* type_size
;
4417 /* Number of usable components in the next block-aligned load. */
4418 const unsigned count
= MIN2(instr
->num_components
- c
,
4419 (block_sz
- base
% block_sz
) / type_size
);
4421 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4422 packed_consts
, surf_index
,
4423 brw_imm_ud(base
& ~(block_sz
- 1)));
4425 const fs_reg consts
=
4426 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4429 for (unsigned d
= 0; d
< count
; d
++)
4430 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4438 case nir_intrinsic_load_global
: {
4439 assert(devinfo
->gen
>= 8);
4441 if (nir_intrinsic_align(instr
) >= 4) {
4442 assert(nir_dest_bit_size(instr
->dest
) == 32);
4443 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4445 get_nir_src(instr
->src
[0]), /* Address */
4446 fs_reg(), /* No source data */
4447 brw_imm_ud(instr
->num_components
));
4448 inst
->size_written
= instr
->num_components
*
4449 inst
->dst
.component_size(inst
->exec_size
);
4451 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4452 assert(bit_size
<= 32);
4453 assert(nir_dest_num_components(instr
->dest
) == 1);
4454 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4455 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4457 get_nir_src(instr
->src
[0]), /* Address */
4458 fs_reg(), /* No source data */
4459 brw_imm_ud(bit_size
));
4460 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4465 case nir_intrinsic_store_global
:
4466 assert(devinfo
->gen
>= 8);
4468 if (stage
== MESA_SHADER_FRAGMENT
)
4469 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4471 if (nir_intrinsic_align(instr
) >= 4) {
4472 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4473 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4475 get_nir_src(instr
->src
[1]), /* Address */
4476 get_nir_src(instr
->src
[0]), /* Data */
4477 brw_imm_ud(instr
->num_components
));
4479 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4480 assert(bit_size
<= 32);
4481 assert(nir_src_num_components(instr
->src
[0]) == 1);
4482 brw_reg_type data_type
=
4483 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4484 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4485 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4486 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4488 get_nir_src(instr
->src
[1]), /* Address */
4490 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4494 case nir_intrinsic_global_atomic_add
:
4495 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4497 case nir_intrinsic_global_atomic_imin
:
4498 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4500 case nir_intrinsic_global_atomic_umin
:
4501 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4503 case nir_intrinsic_global_atomic_imax
:
4504 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4506 case nir_intrinsic_global_atomic_umax
:
4507 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4509 case nir_intrinsic_global_atomic_and
:
4510 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4512 case nir_intrinsic_global_atomic_or
:
4513 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4515 case nir_intrinsic_global_atomic_xor
:
4516 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4518 case nir_intrinsic_global_atomic_exchange
:
4519 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4521 case nir_intrinsic_global_atomic_comp_swap
:
4522 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4524 case nir_intrinsic_global_atomic_fmin
:
4525 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4527 case nir_intrinsic_global_atomic_fmax
:
4528 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4530 case nir_intrinsic_global_atomic_fcomp_swap
:
4531 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4534 case nir_intrinsic_load_ssbo
: {
4535 assert(devinfo
->gen
>= 7);
4537 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4538 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4539 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4540 get_nir_ssbo_intrinsic_index(bld
, instr
);
4541 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4542 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4544 /* Make dest unsigned because that's what the temporary will be */
4545 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4547 /* Read the vector */
4548 if (nir_intrinsic_align(instr
) >= 4) {
4549 assert(nir_dest_bit_size(instr
->dest
) == 32);
4550 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4552 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4553 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4554 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4556 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4557 assert(nir_dest_num_components(instr
->dest
) == 1);
4558 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4560 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4561 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4562 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4563 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4568 case nir_intrinsic_store_ssbo
: {
4569 assert(devinfo
->gen
>= 7);
4571 if (stage
== MESA_SHADER_FRAGMENT
)
4572 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4574 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4575 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4576 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4577 get_nir_ssbo_intrinsic_index(bld
, instr
);
4578 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4579 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4581 fs_reg data
= get_nir_src(instr
->src
[0]);
4582 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4584 assert(nir_intrinsic_write_mask(instr
) ==
4585 (1u << instr
->num_components
) - 1);
4586 if (nir_intrinsic_align(instr
) >= 4) {
4587 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4588 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4589 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4590 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4591 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4592 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4594 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4595 assert(nir_src_num_components(instr
->src
[0]) == 1);
4596 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4598 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4599 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4601 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4602 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4607 case nir_intrinsic_store_output
: {
4608 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4609 fs_reg src
= get_nir_src(instr
->src
[0]);
4611 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4612 unsigned num_components
= instr
->num_components
;
4613 unsigned first_component
= nir_intrinsic_component(instr
);
4615 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4616 4 * store_offset
), src
.type
);
4617 for (unsigned j
= 0; j
< num_components
; j
++) {
4618 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4619 offset(src
, bld
, j
));
4624 case nir_intrinsic_ssbo_atomic_add
:
4625 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4627 case nir_intrinsic_ssbo_atomic_imin
:
4628 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4630 case nir_intrinsic_ssbo_atomic_umin
:
4631 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4633 case nir_intrinsic_ssbo_atomic_imax
:
4634 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4636 case nir_intrinsic_ssbo_atomic_umax
:
4637 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4639 case nir_intrinsic_ssbo_atomic_and
:
4640 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4642 case nir_intrinsic_ssbo_atomic_or
:
4643 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4645 case nir_intrinsic_ssbo_atomic_xor
:
4646 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4648 case nir_intrinsic_ssbo_atomic_exchange
:
4649 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4651 case nir_intrinsic_ssbo_atomic_comp_swap
:
4652 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4654 case nir_intrinsic_ssbo_atomic_fmin
:
4655 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4657 case nir_intrinsic_ssbo_atomic_fmax
:
4658 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4660 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4661 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4664 case nir_intrinsic_get_buffer_size
: {
4665 assert(nir_src_num_components(instr
->src
[0]) == 1);
4666 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4667 nir_src_as_uint(instr
->src
[0]) : 0;
4669 /* A resinfo's sampler message is used to get the buffer size. The
4670 * SIMD8's writeback message consists of four registers and SIMD16's
4671 * writeback message consists of 8 destination registers (two per each
4672 * component). Because we are only interested on the first channel of
4673 * the first returned component, where resinfo returns the buffer size
4674 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4675 * the dispatch width.
4677 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4678 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4679 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4682 ubld
.MOV(src_payload
, brw_imm_d(0));
4684 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4685 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4686 src_payload
, brw_imm_ud(index
));
4687 inst
->header_size
= 0;
4689 inst
->size_written
= 4 * REG_SIZE
;
4691 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4693 * "Out-of-bounds checking is always performed at a DWord granularity. If
4694 * any part of the DWord is out-of-bounds then the whole DWord is
4695 * considered out-of-bounds."
4697 * This implies that types with size smaller than 4-bytes need to be
4698 * padded if they don't complete the last dword of the buffer. But as we
4699 * need to maintain the original size we need to reverse the padding
4700 * calculation to return the correct size to know the number of elements
4701 * of an unsized array. As we stored in the last two bits of the surface
4702 * size the needed padding for the buffer, we calculate here the
4703 * original buffer_size reversing the surface_size calculation:
4705 * surface_size = isl_align(buffer_size, 4) +
4706 * (isl_align(buffer_size) - buffer_size)
4708 * buffer_size = surface_size & ~3 - surface_size & 3
4711 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4712 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4713 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4715 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4716 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4717 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4719 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4723 case nir_intrinsic_load_subgroup_size
:
4724 /* This should only happen for fragment shaders because every other case
4725 * is lowered in NIR so we can optimize on it.
4727 assert(stage
== MESA_SHADER_FRAGMENT
);
4728 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4731 case nir_intrinsic_load_subgroup_invocation
:
4732 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4733 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4736 case nir_intrinsic_load_subgroup_eq_mask
:
4737 case nir_intrinsic_load_subgroup_ge_mask
:
4738 case nir_intrinsic_load_subgroup_gt_mask
:
4739 case nir_intrinsic_load_subgroup_le_mask
:
4740 case nir_intrinsic_load_subgroup_lt_mask
:
4741 unreachable("not reached");
4743 case nir_intrinsic_vote_any
: {
4744 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4746 /* The any/all predicates do not consider channel enables. To prevent
4747 * dead channels from affecting the result, we initialize the flag with
4748 * with the identity value for the logical operation.
4750 if (dispatch_width
== 32) {
4751 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4752 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4755 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4757 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4759 /* For some reason, the any/all predicates don't work properly with
4760 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4761 * doesn't read the correct subset of the flag register and you end up
4762 * getting garbage in the second half. Work around this by using a pair
4763 * of 1-wide MOVs and scattering the result.
4765 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4766 ubld
.MOV(res1
, brw_imm_d(0));
4767 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4768 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4769 BRW_PREDICATE_ALIGN1_ANY32H
,
4770 ubld
.MOV(res1
, brw_imm_d(-1)));
4772 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4775 case nir_intrinsic_vote_all
: {
4776 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4778 /* The any/all predicates do not consider channel enables. To prevent
4779 * dead channels from affecting the result, we initialize the flag with
4780 * with the identity value for the logical operation.
4782 if (dispatch_width
== 32) {
4783 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4784 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4785 brw_imm_ud(0xffffffff));
4787 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4789 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4791 /* For some reason, the any/all predicates don't work properly with
4792 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4793 * doesn't read the correct subset of the flag register and you end up
4794 * getting garbage in the second half. Work around this by using a pair
4795 * of 1-wide MOVs and scattering the result.
4797 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4798 ubld
.MOV(res1
, brw_imm_d(0));
4799 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4800 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4801 BRW_PREDICATE_ALIGN1_ALL32H
,
4802 ubld
.MOV(res1
, brw_imm_d(-1)));
4804 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4807 case nir_intrinsic_vote_feq
:
4808 case nir_intrinsic_vote_ieq
: {
4809 fs_reg value
= get_nir_src(instr
->src
[0]);
4810 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4811 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4812 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4813 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4816 fs_reg uniformized
= bld
.emit_uniformize(value
);
4817 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4819 /* The any/all predicates do not consider channel enables. To prevent
4820 * dead channels from affecting the result, we initialize the flag with
4821 * with the identity value for the logical operation.
4823 if (dispatch_width
== 32) {
4824 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4825 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4826 brw_imm_ud(0xffffffff));
4828 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4830 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4832 /* For some reason, the any/all predicates don't work properly with
4833 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4834 * doesn't read the correct subset of the flag register and you end up
4835 * getting garbage in the second half. Work around this by using a pair
4836 * of 1-wide MOVs and scattering the result.
4838 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4839 ubld
.MOV(res1
, brw_imm_d(0));
4840 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4841 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4842 BRW_PREDICATE_ALIGN1_ALL32H
,
4843 ubld
.MOV(res1
, brw_imm_d(-1)));
4845 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4849 case nir_intrinsic_ballot
: {
4850 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4851 BRW_REGISTER_TYPE_UD
);
4852 struct brw_reg flag
= brw_flag_reg(0, 0);
4853 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4854 * as f0.0. This is a problem for fragment programs as we currently use
4855 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4856 * programs yet so this isn't a problem. When we do, something will
4859 if (dispatch_width
== 32)
4860 flag
.type
= BRW_REGISTER_TYPE_UD
;
4862 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4863 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4865 if (instr
->dest
.ssa
.bit_size
> 32) {
4866 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4868 dest
.type
= BRW_REGISTER_TYPE_UD
;
4870 bld
.MOV(dest
, flag
);
4874 case nir_intrinsic_read_invocation
: {
4875 const fs_reg value
= get_nir_src(instr
->src
[0]);
4876 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4877 fs_reg tmp
= bld
.vgrf(value
.type
);
4879 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4880 bld
.emit_uniformize(invocation
));
4882 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4886 case nir_intrinsic_read_first_invocation
: {
4887 const fs_reg value
= get_nir_src(instr
->src
[0]);
4888 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4892 case nir_intrinsic_shuffle
: {
4893 const fs_reg value
= get_nir_src(instr
->src
[0]);
4894 const fs_reg index
= get_nir_src(instr
->src
[1]);
4896 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4900 case nir_intrinsic_first_invocation
: {
4901 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4902 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4903 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4904 fs_reg(component(tmp
, 0)));
4908 case nir_intrinsic_quad_broadcast
: {
4909 const fs_reg value
= get_nir_src(instr
->src
[0]);
4910 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4912 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4913 value
, brw_imm_ud(index
), brw_imm_ud(4));
4917 case nir_intrinsic_quad_swap_horizontal
: {
4918 const fs_reg value
= get_nir_src(instr
->src
[0]);
4919 const fs_reg tmp
= bld
.vgrf(value
.type
);
4920 if (devinfo
->gen
<= 7) {
4921 /* The hardware doesn't seem to support these crazy regions with
4922 * compressed instructions on gen7 and earlier so we fall back to
4923 * using quad swizzles. Fortunately, we don't support 64-bit
4924 * anything in Vulkan on gen7.
4926 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4927 const fs_builder ubld
= bld
.exec_all();
4928 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4929 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
4930 bld
.MOV(retype(dest
, value
.type
), tmp
);
4932 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4934 const fs_reg src_left
= horiz_stride(value
, 2);
4935 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4936 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4937 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4939 ubld
.MOV(tmp_left
, src_right
);
4940 ubld
.MOV(tmp_right
, src_left
);
4943 bld
.MOV(retype(dest
, value
.type
), tmp
);
4947 case nir_intrinsic_quad_swap_vertical
: {
4948 const fs_reg value
= get_nir_src(instr
->src
[0]);
4949 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4950 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4951 const fs_reg tmp
= bld
.vgrf(value
.type
);
4952 const fs_builder ubld
= bld
.exec_all();
4953 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4954 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4955 bld
.MOV(retype(dest
, value
.type
), tmp
);
4957 /* For larger data types, we have to either emit dispatch_width many
4958 * MOVs or else fall back to doing indirects.
4960 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4961 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4963 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4968 case nir_intrinsic_quad_swap_diagonal
: {
4969 const fs_reg value
= get_nir_src(instr
->src
[0]);
4970 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4971 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4972 const fs_reg tmp
= bld
.vgrf(value
.type
);
4973 const fs_builder ubld
= bld
.exec_all();
4974 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4975 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4976 bld
.MOV(retype(dest
, value
.type
), tmp
);
4978 /* For larger data types, we have to either emit dispatch_width many
4979 * MOVs or else fall back to doing indirects.
4981 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4982 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4984 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4989 case nir_intrinsic_reduce
: {
4990 fs_reg src
= get_nir_src(instr
->src
[0]);
4991 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4992 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4993 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4994 cluster_size
= dispatch_width
;
4996 /* Figure out the source type */
4997 src
.type
= brw_type_for_nir_type(devinfo
,
4998 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4999 nir_src_bit_size(instr
->src
[0])));
5001 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5002 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5003 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5005 /* Set up a register for all of our scratching around and initialize it
5006 * to reduction operation's identity value.
5008 fs_reg scan
= bld
.vgrf(src
.type
);
5009 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5011 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
5013 dest
.type
= src
.type
;
5014 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
5015 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
5016 * the distance between clusters is at least 2 GRFs. In this case,
5017 * we don't need the weird striding of the CLUSTER_BROADCAST
5018 * instruction and can just do regular MOVs.
5020 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5021 const unsigned groups
=
5022 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5023 const unsigned group_size
= dispatch_width
/ groups
;
5024 for (unsigned i
= 0; i
< groups
; i
++) {
5025 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5026 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5027 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5028 component(scan
, comp
));
5031 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5032 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5037 case nir_intrinsic_inclusive_scan
:
5038 case nir_intrinsic_exclusive_scan
: {
5039 fs_reg src
= get_nir_src(instr
->src
[0]);
5040 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5042 /* Figure out the source type */
5043 src
.type
= brw_type_for_nir_type(devinfo
,
5044 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5045 nir_src_bit_size(instr
->src
[0])));
5047 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5048 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5049 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5051 /* Set up a register for all of our scratching around and initialize it
5052 * to reduction operation's identity value.
5054 fs_reg scan
= bld
.vgrf(src
.type
);
5055 const fs_builder allbld
= bld
.exec_all();
5056 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5058 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5059 /* Exclusive scan is a bit harder because we have to do an annoying
5060 * shift of the contents before we can begin. To make things worse,
5061 * we can't do this with a normal stride; we have to use indirects.
5063 fs_reg shifted
= bld
.vgrf(src
.type
);
5064 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5065 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5067 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5068 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5072 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5074 bld
.MOV(retype(dest
, src
.type
), scan
);
5078 case nir_intrinsic_begin_invocation_interlock
: {
5079 const fs_builder ubld
= bld
.group(8, 0);
5080 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5082 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
5083 ->size_written
= 2 * REG_SIZE
;
5087 case nir_intrinsic_end_invocation_interlock
: {
5088 /* For endInvocationInterlock(), we need to insert a memory fence which
5089 * stalls in the shader until the memory transactions prior to that
5090 * fence are complete. This ensures that the shader does not end before
5091 * any writes from its critical section have landed. Otherwise, you can
5092 * end up with a case where the next invocation on that pixel properly
5093 * stalls for previous FS invocation on its pixel to complete but
5094 * doesn't actually wait for the dataport memory transactions from that
5095 * thread to land before submitting its own.
5097 const fs_builder ubld
= bld
.group(8, 0);
5098 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5099 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
5100 brw_vec8_grf(0, 0), brw_imm_ud(1), brw_imm_ud(0))
5101 ->size_written
= 2 * REG_SIZE
;
5106 unreachable("unknown intrinsic");
5111 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5112 int op
, nir_intrinsic_instr
*instr
)
5114 if (stage
== MESA_SHADER_FRAGMENT
)
5115 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5117 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5118 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5119 * appear to exist. However, if you look at Vol 2a, there are no message
5120 * descriptors provided for Qword atomic ops except for A64 messages.
5122 assert(nir_dest_bit_size(instr
->dest
) == 32);
5125 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5126 dest
= get_nir_dest(instr
->dest
);
5128 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5129 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5130 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5131 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5132 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5135 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5136 data
= get_nir_src(instr
->src
[2]);
5138 if (op
== BRW_AOP_CMPWR
) {
5139 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5140 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5141 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5144 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5146 /* Emit the actual atomic operation */
5148 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5149 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5153 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5154 int op
, nir_intrinsic_instr
*instr
)
5156 if (stage
== MESA_SHADER_FRAGMENT
)
5157 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5160 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5161 dest
= get_nir_dest(instr
->dest
);
5163 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5164 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5165 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5166 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5167 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5169 fs_reg data
= get_nir_src(instr
->src
[2]);
5170 if (op
== BRW_AOP_FCMPWR
) {
5171 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5172 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5173 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5176 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5178 /* Emit the actual atomic operation */
5180 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5181 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5185 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5186 int op
, nir_intrinsic_instr
*instr
)
5189 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5190 dest
= get_nir_dest(instr
->dest
);
5192 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5193 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5194 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5195 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5198 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5199 data
= get_nir_src(instr
->src
[1]);
5200 if (op
== BRW_AOP_CMPWR
) {
5201 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5202 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5203 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5206 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5208 /* Get the offset */
5209 if (nir_src_is_const(instr
->src
[0])) {
5210 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5211 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5213 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5214 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5215 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5216 brw_imm_ud(instr
->const_index
[0]));
5219 /* Emit the actual atomic operation operation */
5221 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5222 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5226 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5227 int op
, nir_intrinsic_instr
*instr
)
5230 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5231 dest
= get_nir_dest(instr
->dest
);
5233 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5234 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5235 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5236 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5238 fs_reg data
= get_nir_src(instr
->src
[1]);
5239 if (op
== BRW_AOP_FCMPWR
) {
5240 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5241 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5242 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5245 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5247 /* Get the offset */
5248 if (nir_src_is_const(instr
->src
[0])) {
5249 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5250 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5252 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5253 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5254 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5255 brw_imm_ud(instr
->const_index
[0]));
5258 /* Emit the actual atomic operation operation */
5260 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5261 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5265 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5266 int op
, nir_intrinsic_instr
*instr
)
5268 if (stage
== MESA_SHADER_FRAGMENT
)
5269 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5272 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5273 dest
= get_nir_dest(instr
->dest
);
5275 fs_reg addr
= get_nir_src(instr
->src
[0]);
5278 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5279 data
= get_nir_src(instr
->src
[1]);
5281 if (op
== BRW_AOP_CMPWR
) {
5282 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5283 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5284 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5288 if (nir_dest_bit_size(instr
->dest
) == 64) {
5289 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5290 dest
, addr
, data
, brw_imm_ud(op
));
5292 assert(nir_dest_bit_size(instr
->dest
) == 32);
5293 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5294 dest
, addr
, data
, brw_imm_ud(op
));
5299 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5300 int op
, nir_intrinsic_instr
*instr
)
5302 if (stage
== MESA_SHADER_FRAGMENT
)
5303 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5305 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5306 fs_reg dest
= get_nir_dest(instr
->dest
);
5308 fs_reg addr
= get_nir_src(instr
->src
[0]);
5310 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5311 fs_reg data
= get_nir_src(instr
->src
[1]);
5313 if (op
== BRW_AOP_FCMPWR
) {
5314 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5315 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5316 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5320 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5321 dest
, addr
, data
, brw_imm_ud(op
));
5325 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5327 unsigned texture
= instr
->texture_index
;
5328 unsigned sampler
= instr
->sampler_index
;
5330 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5332 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5333 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5335 int lod_components
= 0;
5337 /* The hardware requires a LOD for buffer textures */
5338 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5339 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5341 uint32_t header_bits
= 0;
5342 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5343 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5344 switch (instr
->src
[i
].src_type
) {
5345 case nir_tex_src_bias
:
5346 srcs
[TEX_LOGICAL_SRC_LOD
] =
5347 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5349 case nir_tex_src_comparator
:
5350 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5352 case nir_tex_src_coord
:
5353 switch (instr
->op
) {
5355 case nir_texop_txf_ms
:
5356 case nir_texop_txf_ms_mcs
:
5357 case nir_texop_samples_identical
:
5358 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5361 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5365 case nir_tex_src_ddx
:
5366 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5367 lod_components
= nir_tex_instr_src_size(instr
, i
);
5369 case nir_tex_src_ddy
:
5370 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5372 case nir_tex_src_lod
:
5373 switch (instr
->op
) {
5375 srcs
[TEX_LOGICAL_SRC_LOD
] =
5376 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5379 srcs
[TEX_LOGICAL_SRC_LOD
] =
5380 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5383 srcs
[TEX_LOGICAL_SRC_LOD
] =
5384 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5388 case nir_tex_src_min_lod
:
5389 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5390 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5392 case nir_tex_src_ms_index
:
5393 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5396 case nir_tex_src_offset
: {
5397 uint32_t offset_bits
= 0;
5398 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5399 header_bits
|= offset_bits
;
5401 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5402 retype(src
, BRW_REGISTER_TYPE_D
);
5407 case nir_tex_src_projector
:
5408 unreachable("should be lowered");
5410 case nir_tex_src_texture_offset
: {
5411 /* Emit code to evaluate the actual indexing expression */
5412 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5413 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5414 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5418 case nir_tex_src_sampler_offset
: {
5419 /* Emit code to evaluate the actual indexing expression */
5420 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5421 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5422 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5426 case nir_tex_src_texture_handle
:
5427 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5428 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5429 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5432 case nir_tex_src_sampler_handle
:
5433 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5434 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5435 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5438 case nir_tex_src_ms_mcs
:
5439 assert(instr
->op
== nir_texop_txf_ms
);
5440 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5443 case nir_tex_src_plane
: {
5444 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5445 const uint32_t texture_index
=
5446 instr
->texture_index
+
5447 stage_prog_data
->binding_table
.plane_start
[plane
] -
5448 stage_prog_data
->binding_table
.texture_start
;
5450 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5455 unreachable("unknown texture source");
5459 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5460 (instr
->op
== nir_texop_txf_ms
||
5461 instr
->op
== nir_texop_samples_identical
)) {
5462 if (devinfo
->gen
>= 7 &&
5463 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5464 srcs
[TEX_LOGICAL_SRC_MCS
] =
5465 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5466 instr
->coord_components
,
5467 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5468 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5470 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5474 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5475 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5478 switch (instr
->op
) {
5480 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5483 opcode
= FS_OPCODE_TXB_LOGICAL
;
5486 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5489 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5492 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5494 case nir_texop_txf_ms
:
5495 if ((key_tex
->msaa_16
& (1 << sampler
)))
5496 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5498 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5500 case nir_texop_txf_ms_mcs
:
5501 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5503 case nir_texop_query_levels
:
5505 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5508 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5511 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5512 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5514 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5516 case nir_texop_texture_samples
:
5517 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5519 case nir_texop_samples_identical
: {
5520 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5522 /* If mcs is an immediate value, it means there is no MCS. In that case
5523 * just return false.
5525 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5526 bld
.MOV(dst
, brw_imm_ud(0u));
5527 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5528 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5529 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5530 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5531 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5533 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5534 BRW_CONDITIONAL_EQ
);
5539 unreachable("unknown texture opcode");
5542 if (instr
->op
== nir_texop_tg4
) {
5543 if (instr
->component
== 1 &&
5544 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5545 /* gather4 sampler is broken for green channel on RG32F --
5546 * we must ask for blue instead.
5548 header_bits
|= 2 << 16;
5550 header_bits
|= instr
->component
<< 16;
5554 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5555 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5556 inst
->offset
= header_bits
;
5558 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5559 if (devinfo
->gen
>= 9 &&
5560 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5561 unsigned write_mask
= instr
->dest
.is_ssa
?
5562 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5563 (1 << dest_size
) - 1;
5564 assert(write_mask
!= 0); /* dead code should have been eliminated */
5565 inst
->size_written
= util_last_bit(write_mask
) *
5566 inst
->dst
.component_size(inst
->exec_size
);
5568 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5571 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5572 inst
->shadow_compare
= true;
5574 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5575 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5578 for (unsigned i
= 0; i
< dest_size
; i
++)
5579 nir_dest
[i
] = offset(dst
, bld
, i
);
5581 if (instr
->op
== nir_texop_query_levels
) {
5582 /* # levels is in .w */
5583 nir_dest
[0] = offset(dst
, bld
, 3);
5584 } else if (instr
->op
== nir_texop_txs
&&
5585 dest_size
>= 3 && devinfo
->gen
< 7) {
5586 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5587 fs_reg depth
= offset(dst
, bld
, 2);
5588 nir_dest
[2] = vgrf(glsl_type::int_type
);
5589 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5592 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5596 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5598 switch (instr
->type
) {
5599 case nir_jump_break
:
5600 bld
.emit(BRW_OPCODE_BREAK
);
5602 case nir_jump_continue
:
5603 bld
.emit(BRW_OPCODE_CONTINUE
);
5605 case nir_jump_return
:
5607 unreachable("unknown jump");
5612 * This helper takes a source register and un/shuffles it into the destination
5615 * If source type size is smaller than destination type size the operation
5616 * needed is a component shuffle. The opposite case would be an unshuffle. If
5617 * source/destination type size is equal a shuffle is done that would be
5618 * equivalent to a simple MOV.
5620 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5621 * components .xyz 16-bit vector on SIMD8 would be.
5623 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5624 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5626 * This helper will return the following 2 32-bit components with the 16-bit
5629 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5630 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5632 * For unshuffle, the example would be the opposite, a 64-bit type source
5633 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5636 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5637 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5638 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5639 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5641 * The returned result would be the following 4 32-bit components unshuffled:
5643 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5644 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5645 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5646 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5648 * - Source and destination register must not be overlapped.
5649 * - components units are measured in terms of the smaller type between
5650 * source and destination because we are un/shuffling the smaller
5651 * components from/into the bigger ones.
5652 * - first_component parameter allows skipping source components.
5655 shuffle_src_to_dst(const fs_builder
&bld
,
5658 uint32_t first_component
,
5659 uint32_t components
)
5661 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5662 assert(!regions_overlap(dst
,
5663 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5664 offset(src
, bld
, first_component
),
5665 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5666 for (unsigned i
= 0; i
< components
; i
++) {
5667 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5668 offset(src
, bld
, i
+ first_component
));
5670 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5671 /* Source is shuffled into destination */
5672 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5673 assert(!regions_overlap(dst
,
5674 type_sz(dst
.type
) * bld
.dispatch_width() *
5675 DIV_ROUND_UP(components
, size_ratio
),
5676 offset(src
, bld
, first_component
),
5677 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5679 brw_reg_type shuffle_type
=
5680 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5681 BRW_REGISTER_TYPE_D
);
5682 for (unsigned i
= 0; i
< components
; i
++) {
5683 fs_reg shuffle_component_i
=
5684 subscript(offset(dst
, bld
, i
/ size_ratio
),
5685 shuffle_type
, i
% size_ratio
);
5686 bld
.MOV(shuffle_component_i
,
5687 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5690 /* Source is unshuffled into destination */
5691 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5692 assert(!regions_overlap(dst
,
5693 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5694 offset(src
, bld
, first_component
/ size_ratio
),
5695 type_sz(src
.type
) * bld
.dispatch_width() *
5696 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5699 brw_reg_type shuffle_type
=
5700 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5701 BRW_REGISTER_TYPE_D
);
5702 for (unsigned i
= 0; i
< components
; i
++) {
5703 fs_reg shuffle_component_i
=
5704 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5705 shuffle_type
, (first_component
+ i
) % size_ratio
);
5706 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5707 shuffle_component_i
);
5713 shuffle_from_32bit_read(const fs_builder
&bld
,
5716 uint32_t first_component
,
5717 uint32_t components
)
5719 assert(type_sz(src
.type
) == 4);
5721 /* This function takes components in units of the destination type while
5722 * shuffle_src_to_dst takes components in units of the smallest type
5724 if (type_sz(dst
.type
) > 4) {
5725 assert(type_sz(dst
.type
) == 8);
5726 first_component
*= 2;
5730 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5734 setup_imm_df(const fs_builder
&bld
, double v
)
5736 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5737 assert(devinfo
->gen
>= 7);
5739 if (devinfo
->gen
>= 8)
5740 return brw_imm_df(v
);
5742 /* gen7.5 does not support DF immediates straighforward but the DIM
5743 * instruction allows to set the 64-bit immediate value.
5745 if (devinfo
->is_haswell
) {
5746 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5747 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5748 ubld
.DIM(dst
, brw_imm_df(v
));
5749 return component(dst
, 0);
5752 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5753 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5754 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5756 * Alternatively, we could also produce a normal VGRF (without stride 0)
5757 * by writing to all the channels in the VGRF, however, that would hit the
5758 * gen7 bug where we have to split writes that span more than 1 register
5759 * into instructions with a width of 4 (otherwise the write to the second
5760 * register written runs into an execmask hardware bug) which isn't very
5773 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5774 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5775 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5776 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5778 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5782 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5784 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5785 bld
.MOV(tmp
, brw_imm_w(v
));
5790 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5792 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5793 bld
.MOV(tmp
, brw_imm_uw(v
));