2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
48 fs_visitor::nir_setup_outputs()
50 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
53 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
55 /* Calculate the size of output registers in a separate pass, before
56 * allocating them. With ARB_enhanced_layouts, multiple output variables
57 * may occupy the same slot, but have different type sizes.
59 nir_foreach_variable(var
, &nir
->outputs
) {
60 const int loc
= var
->data
.driver_location
;
61 const unsigned var_vec4s
=
62 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
63 : type_size_vec4(var
->type
, true);
64 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
67 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
68 if (vec4s
[loc
] == 0) {
73 unsigned reg_size
= vec4s
[loc
];
75 /* Check if there are any ranges that start within this range and extend
76 * past it. If so, include them in this allocation.
78 for (unsigned i
= 1; i
< reg_size
; i
++)
79 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
81 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
82 for (unsigned i
= 0; i
< reg_size
; i
++)
83 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
90 fs_visitor::nir_setup_uniforms()
92 /* Only the first compile gets to set up uniforms. */
93 if (push_constant_loc
) {
94 assert(pull_constant_loc
);
98 uniforms
= nir
->num_uniforms
/ 4;
100 if (stage
== MESA_SHADER_COMPUTE
) {
101 /* Add a uniform for the thread local id. It must be the last uniform
104 assert(uniforms
== prog_data
->nr_params
);
105 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
106 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
107 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
112 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
116 nir_foreach_instr(instr
, block
) {
117 if (instr
->type
!= nir_instr_type_intrinsic
)
120 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
121 switch (intrin
->intrinsic
) {
122 case nir_intrinsic_load_vertex_id
:
123 case nir_intrinsic_load_base_vertex
:
124 unreachable("should be lowered by nir_lower_system_values().");
126 case nir_intrinsic_load_vertex_id_zero_base
:
127 case nir_intrinsic_load_is_indexed_draw
:
128 case nir_intrinsic_load_first_vertex
:
129 case nir_intrinsic_load_instance_id
:
130 case nir_intrinsic_load_base_instance
:
131 case nir_intrinsic_load_draw_id
:
132 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
134 case nir_intrinsic_load_invocation_id
:
135 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
137 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
138 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
139 if (reg
->file
== BAD_FILE
) {
140 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
141 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
142 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
143 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
148 case nir_intrinsic_load_sample_pos
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_samplepos_setup();
155 case nir_intrinsic_load_sample_id
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_sampleid_setup();
162 case nir_intrinsic_load_sample_mask_in
:
163 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
164 assert(v
->devinfo
->gen
>= 7);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplemaskin_setup();
170 case nir_intrinsic_load_work_group_id
:
171 assert(v
->stage
== MESA_SHADER_COMPUTE
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_cs_work_group_id_setup();
177 case nir_intrinsic_load_helper_invocation
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
180 if (reg
->file
== BAD_FILE
) {
181 const fs_builder abld
=
182 v
->bld
.annotate("gl_HelperInvocation", NULL
);
184 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
185 * pixel mask is in g1.7 of the thread payload.
187 * We move the per-channel pixel enable bit to the low bit of each
188 * channel by shifting the byte containing the pixel mask by the
189 * vector immediate 0x76543210UV.
191 * The region of <1,8,0> reads only 1 byte (the pixel masks for
192 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
193 * masks for 2 and 3) in SIMD16.
195 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
197 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
198 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
199 hbld
.SHR(offset(shifted
, hbld
, i
),
200 stride(retype(brw_vec1_grf(1 + i
, 7),
201 BRW_REGISTER_TYPE_UB
),
203 brw_imm_v(0x76543210));
206 /* A set bit in the pixel mask means the channel is enabled, but
207 * that is the opposite of gl_HelperInvocation so we need to invert
210 * The negate source-modifier bit of logical instructions on Gen8+
211 * performs 1's complement negation, so we can use that instead of
214 fs_reg inverted
= negate(shifted
);
215 if (v
->devinfo
->gen
< 8) {
216 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
217 abld
.NOT(inverted
, shifted
);
220 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
221 * with 1 and negating.
223 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
224 abld
.AND(anded
, inverted
, brw_imm_uw(1));
226 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
227 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
241 fs_visitor::nir_emit_system_values()
243 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
244 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
245 nir_system_values
[i
] = fs_reg();
248 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
249 * never end up using it.
252 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
253 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
254 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
256 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
257 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
258 if (dispatch_width
> 8)
259 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
260 if (dispatch_width
> 16) {
261 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
262 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
266 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
267 nir_foreach_block(block
, impl
)
268 emit_system_values_block(block
, this);
272 * Returns a type based on a reference_type (word, float, half-float) and a
275 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
277 * @FIXME: 64-bit return types are always DF on integer types to maintain
278 * compability with uses of DF previously to the introduction of int64
282 brw_reg_type_from_bit_size(const unsigned bit_size
,
283 const brw_reg_type reference_type
)
285 switch(reference_type
) {
286 case BRW_REGISTER_TYPE_HF
:
287 case BRW_REGISTER_TYPE_F
:
288 case BRW_REGISTER_TYPE_DF
:
291 return BRW_REGISTER_TYPE_HF
;
293 return BRW_REGISTER_TYPE_F
;
295 return BRW_REGISTER_TYPE_DF
;
297 unreachable("Invalid bit size");
299 case BRW_REGISTER_TYPE_B
:
300 case BRW_REGISTER_TYPE_W
:
301 case BRW_REGISTER_TYPE_D
:
302 case BRW_REGISTER_TYPE_Q
:
305 return BRW_REGISTER_TYPE_B
;
307 return BRW_REGISTER_TYPE_W
;
309 return BRW_REGISTER_TYPE_D
;
311 return BRW_REGISTER_TYPE_Q
;
313 unreachable("Invalid bit size");
315 case BRW_REGISTER_TYPE_UB
:
316 case BRW_REGISTER_TYPE_UW
:
317 case BRW_REGISTER_TYPE_UD
:
318 case BRW_REGISTER_TYPE_UQ
:
321 return BRW_REGISTER_TYPE_UB
;
323 return BRW_REGISTER_TYPE_UW
;
325 return BRW_REGISTER_TYPE_UD
;
327 return BRW_REGISTER_TYPE_UQ
;
329 unreachable("Invalid bit size");
332 unreachable("Unknown type");
337 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
339 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
340 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
341 nir_locals
[i
] = fs_reg();
344 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
345 unsigned array_elems
=
346 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
347 unsigned size
= array_elems
* reg
->num_components
;
348 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
349 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
350 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
353 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
356 nir_emit_cf_list(&impl
->body
);
360 fs_visitor::nir_emit_cf_list(exec_list
*list
)
362 exec_list_validate(list
);
363 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
364 switch (node
->type
) {
366 nir_emit_if(nir_cf_node_as_if(node
));
369 case nir_cf_node_loop
:
370 nir_emit_loop(nir_cf_node_as_loop(node
));
373 case nir_cf_node_block
:
374 nir_emit_block(nir_cf_node_as_block(node
));
378 unreachable("Invalid CFG node block");
384 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
389 /* If the condition has the form !other_condition, use other_condition as
390 * the source, but invert the predicate on the if instruction.
392 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
393 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
394 assert(!cond
->src
[0].negate
);
395 assert(!cond
->src
[0].abs
);
398 cond_reg
= get_nir_src(cond
->src
[0].src
);
401 cond_reg
= get_nir_src(if_stmt
->condition
);
404 /* first, put the condition into f0 */
405 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
406 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
407 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
409 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
411 nir_emit_cf_list(&if_stmt
->then_list
);
413 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
414 bld
.emit(BRW_OPCODE_ELSE
);
415 nir_emit_cf_list(&if_stmt
->else_list
);
418 bld
.emit(BRW_OPCODE_ENDIF
);
420 if (devinfo
->gen
< 7)
421 limit_dispatch_width(16, "Non-uniform control flow unsupported "
426 fs_visitor::nir_emit_loop(nir_loop
*loop
)
428 bld
.emit(BRW_OPCODE_DO
);
430 nir_emit_cf_list(&loop
->body
);
432 bld
.emit(BRW_OPCODE_WHILE
);
434 if (devinfo
->gen
< 7)
435 limit_dispatch_width(16, "Non-uniform control flow unsupported "
440 fs_visitor::nir_emit_block(nir_block
*block
)
442 nir_foreach_instr(instr
, block
) {
443 nir_emit_instr(instr
);
448 fs_visitor::nir_emit_instr(nir_instr
*instr
)
450 const fs_builder abld
= bld
.annotate(NULL
, instr
);
452 switch (instr
->type
) {
453 case nir_instr_type_alu
:
454 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
457 case nir_instr_type_deref
:
458 unreachable("All derefs should've been lowered");
461 case nir_instr_type_intrinsic
:
463 case MESA_SHADER_VERTEX
:
464 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
466 case MESA_SHADER_TESS_CTRL
:
467 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 case MESA_SHADER_TESS_EVAL
:
470 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 case MESA_SHADER_GEOMETRY
:
473 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
475 case MESA_SHADER_FRAGMENT
:
476 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 case MESA_SHADER_COMPUTE
:
479 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
482 unreachable("unsupported shader stage");
486 case nir_instr_type_tex
:
487 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
490 case nir_instr_type_load_const
:
491 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
494 case nir_instr_type_ssa_undef
:
495 /* We create a new VGRF for undefs on every use (by handling
496 * them in get_nir_src()), rather than for each definition.
497 * This helps register coalescing eliminate MOVs from undef.
501 case nir_instr_type_jump
:
502 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
506 unreachable("unknown instruction type");
511 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
515 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
516 const fs_reg
&result
)
518 if (!instr
->src
[0].src
.is_ssa
||
519 !instr
->src
[0].src
.ssa
->parent_instr
)
522 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
525 nir_alu_instr
*src0
=
526 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
528 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
529 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
532 /* If either opcode has source modifiers, bail.
534 * TODO: We can potentially handle source modifiers if both of the opcodes
535 * we're combining are signed integers.
537 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
538 src0
->src
[0].abs
|| src0
->src
[0].negate
)
541 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
543 /* Element type to extract.*/
544 const brw_reg_type type
= brw_int_type(
545 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
546 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
548 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
549 op0
.type
= brw_type_for_nir_type(devinfo
,
550 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
551 nir_src_bit_size(src0
->src
[0].src
)));
552 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
554 set_saturate(instr
->dest
.saturate
,
555 bld
.MOV(result
, subscript(op0
, type
, element
)));
560 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
561 const fs_reg
&result
)
563 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
564 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
567 if (!nir_src_is_const(instr
->src
[1].src
) ||
568 !nir_src_is_const(instr
->src
[2].src
))
571 const float value1
= nir_src_as_float(instr
->src
[1].src
);
572 const float value2
= nir_src_as_float(instr
->src
[2].src
);
573 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
576 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
577 assert(value1
== -value2
);
579 fs_reg tmp
= vgrf(glsl_type::int_type
);
581 if (devinfo
->gen
>= 6) {
582 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
583 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
585 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
587 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
588 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
590 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
592 * This negation looks like it's safe in practice, because bits 0:4 will
593 * surely be TRIANGLES
596 if (value1
== -1.0f
) {
600 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
601 g0
, brw_imm_uw(0x3f80));
603 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
604 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
606 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
608 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
609 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
611 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
613 * This negation looks like it's safe in practice, because bits 0:4 will
614 * surely be TRIANGLES
617 if (value1
== -1.0f
) {
621 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
623 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
629 emit_find_msb_using_lzd(const fs_builder
&bld
,
630 const fs_reg
&result
,
638 /* LZD of an absolute value source almost always does the right
639 * thing. There are two problem values:
641 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
642 * 0. However, findMSB(int(0x80000000)) == 30.
644 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
645 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
647 * For a value of zero or negative one, -1 will be returned.
649 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
650 * findMSB(-(1<<x)) should return x-1.
652 * For all negative number cases, including 0x80000000 and
653 * 0xffffffff, the correct value is obtained from LZD if instead of
654 * negating the (already negative) value the logical-not is used. A
655 * conditonal logical-not can be achieved in two instructions.
657 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
659 bld
.ASR(temp
, src
, brw_imm_d(31));
660 bld
.XOR(temp
, temp
, src
);
663 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
664 retype(temp
, BRW_REGISTER_TYPE_UD
));
666 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
667 * from the LSB side. Subtract the result from 31 to convert the MSB
668 * count into an LSB count. If no bits are set, LZD will return 32.
669 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
671 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
672 inst
->src
[0].negate
= true;
676 brw_rnd_mode_from_nir_op (const nir_op op
) {
678 case nir_op_f2f16_rtz
:
679 return BRW_RND_MODE_RTZ
;
680 case nir_op_f2f16_rtne
:
681 return BRW_RND_MODE_RTNE
;
683 unreachable("Operation doesn't support rounding mode");
688 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
689 nir_alu_instr
*instr
,
694 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
696 result
.type
= brw_type_for_nir_type(devinfo
,
697 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
698 nir_dest_bit_size(instr
->dest
.dest
)));
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 op
[i
] = get_nir_src(instr
->src
[i
].src
);
702 op
[i
].type
= brw_type_for_nir_type(devinfo
,
703 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
704 nir_src_bit_size(instr
->src
[i
].src
)));
705 op
[i
].abs
= instr
->src
[i
].abs
;
706 op
[i
].negate
= instr
->src
[i
].negate
;
709 /* Move and vecN instrutions may still be vectored. Return the raw,
710 * vectored source and destination so that fs_visitor::nir_emit_alu can
711 * handle it. Other callers should not have to handle these kinds of
724 /* At this point, we have dealt with any instruction that operates on
725 * more than a single channel. Therefore, we can just adjust the source
726 * and destination registers for that channel and emit the instruction.
728 unsigned channel
= 0;
729 if (nir_op_infos
[instr
->op
].output_size
== 0) {
730 /* Since NIR is doing the scalarizing for us, we should only ever see
731 * vectorized operations with a single channel.
733 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
734 channel
= ffs(instr
->dest
.write_mask
) - 1;
736 result
= offset(result
, bld
, channel
);
739 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
740 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
741 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
748 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
751 for (unsigned i
= 0; i
< 2; i
++) {
752 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
754 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
755 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
756 /* The source of the inot is now the source of instr. */
757 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
759 assert(!op
[i
].negate
);
762 op
[i
] = resolve_source_modifiers(op
[i
]);
768 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
770 nir_alu_instr
*instr
)
772 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
775 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
777 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
780 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
781 * of valid size-changing combinations is a bit more complex.
783 * The source restriction is just because I was lazy about generating the
786 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
787 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
790 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
791 * this is float(1 + a).
795 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
797 /* Ignore the saturate modifier, if there is one. The result of the
798 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
800 bld
.ADD(result
, op
, brw_imm_d(1));
806 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
808 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
809 * the source of \c instr that is a \c nir_op_fsign.
812 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
813 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
817 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
818 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
820 if (instr
->op
!= nir_op_fsign
) {
821 const nir_alu_instr
*const fsign_instr
=
822 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
824 assert(!fsign_instr
->dest
.saturate
);
826 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
827 * fsign_src] has the other multiply source. This must be rearranged so
828 * that op[0] is the source of the fsign op[1] is the other multiply
834 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
836 const nir_alu_type t
=
837 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
838 nir_src_bit_size(fsign_instr
->src
[0].src
));
840 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
841 op
[0].abs
= fsign_instr
->src
[0].abs
;
842 op
[0].negate
= fsign_instr
->src
[0].negate
;
844 unsigned channel
= 0;
845 if (nir_op_infos
[instr
->op
].output_size
== 0) {
846 /* Since NIR is doing the scalarizing for us, we should only ever see
847 * vectorized operations with a single channel.
849 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
850 channel
= ffs(instr
->dest
.write_mask
) - 1;
853 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
855 assert(!instr
->dest
.saturate
);
859 /* Straightforward since the source can be assumed to be either strictly
860 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
862 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
864 if (instr
->op
== nir_op_fsign
) {
865 inst
= (op
[0].negate
)
866 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
867 : bld
.MOV(result
, brw_imm_f(1.0f
));
869 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
870 inst
= bld
.MOV(result
, op
[1]);
873 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
874 } else if (type_sz(op
[0].type
) == 2) {
875 /* AND(val, 0x8000) gives the sign bit.
877 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
879 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
880 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
882 op
[0].type
= BRW_REGISTER_TYPE_UW
;
883 result
.type
= BRW_REGISTER_TYPE_UW
;
884 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
886 if (instr
->op
== nir_op_fsign
)
887 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
889 /* Use XOR here to get the result sign correct. */
890 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
893 inst
->predicate
= BRW_PREDICATE_NORMAL
;
894 } else if (type_sz(op
[0].type
) == 4) {
895 /* AND(val, 0x80000000) gives the sign bit.
897 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
900 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
902 op
[0].type
= BRW_REGISTER_TYPE_UD
;
903 result
.type
= BRW_REGISTER_TYPE_UD
;
904 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
906 if (instr
->op
== nir_op_fsign
)
907 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
909 /* Use XOR here to get the result sign correct. */
910 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
913 inst
->predicate
= BRW_PREDICATE_NORMAL
;
915 /* For doubles we do the same but we need to consider:
917 * - 2-src instructions can't operate with 64-bit immediates
918 * - The sign is encoded in the high 32-bit of each DF
919 * - We need to produce a DF result.
922 fs_reg zero
= vgrf(glsl_type::double_type
);
923 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
924 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
926 bld
.MOV(result
, zero
);
928 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
929 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
930 brw_imm_ud(0x80000000u
));
932 if (instr
->op
== nir_op_fsign
) {
933 set_predicate(BRW_PREDICATE_NORMAL
,
934 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
936 /* This could be done better in some cases. If the scale is an
937 * immediate with the low 32-bits all 0, emitting a separate XOR and
938 * OR would allow an algebraic optimization to remove the OR. There
939 * are currently zero instances of fsign(double(x))*IMM in shader-db
940 * or any test suite, so it is hard to care at this time.
942 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
943 inst
= bld
.XOR(result_int64
, result_int64
,
944 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
950 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
952 * Checks the operands of a \c nir_op_fmul to determine whether or not
953 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
955 * \param instr The multiplication instruction
957 * \param fsign_src The source of \c instr that may or may not be a
961 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
963 assert(instr
->op
== nir_op_fmul
);
965 nir_alu_instr
*const fsign_instr
=
966 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
970 * 1. instr->src[fsign_src] must be a nir_op_fsign.
971 * 2. The nir_op_fsign can only be used by this multiplication.
972 * 3. The source that is the nir_op_fsign does not have source modifiers.
973 * \c emit_fsign only examines the source modifiers of the source of the
976 * The nir_op_fsign must also not have the saturate modifier, but steps
977 * have already been taken (in nir_opt_algebraic) to ensure that.
979 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
980 is_used_once(fsign_instr
) &&
981 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
985 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
988 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
992 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
999 fs_reg temp
= result
;
1000 bool need_extra_copy
= false;
1001 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1002 if (!instr
->src
[i
].src
.is_ssa
&&
1003 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1004 need_extra_copy
= true;
1005 temp
= bld
.vgrf(result
.type
, 4);
1010 for (unsigned i
= 0; i
< 4; i
++) {
1011 if (!(instr
->dest
.write_mask
& (1 << i
)))
1014 if (instr
->op
== nir_op_mov
) {
1015 inst
= bld
.MOV(offset(temp
, bld
, i
),
1016 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1018 inst
= bld
.MOV(offset(temp
, bld
, i
),
1019 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1021 inst
->saturate
= instr
->dest
.saturate
;
1024 /* In this case the source and destination registers were the same,
1025 * so we need to insert an extra set of moves in order to deal with
1028 if (need_extra_copy
) {
1029 for (unsigned i
= 0; i
< 4; i
++) {
1030 if (!(instr
->dest
.write_mask
& (1 << i
)))
1033 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1041 if (optimize_extract_to_float(instr
, result
))
1043 inst
= bld
.MOV(result
, op
[0]);
1044 inst
->saturate
= instr
->dest
.saturate
;
1047 case nir_op_f2f16_rtne
:
1048 case nir_op_f2f16_rtz
:
1049 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1050 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
1053 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1054 * on the HW gen, it is a special hw opcode or just a MOV, and
1055 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1057 * But if we want to use that opcode, we need to provide support on
1058 * different optimizations and lowerings. As right now HF support is
1059 * only for gen8+, it will be better to use directly the MOV, and use
1060 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1062 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1063 inst
= bld
.MOV(result
, op
[0]);
1064 inst
->saturate
= instr
->dest
.saturate
;
1074 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1076 op
[0].type
= BRW_REGISTER_TYPE_D
;
1077 op
[0].negate
= !op
[0].negate
;
1101 if (result
.type
== BRW_REGISTER_TYPE_B
||
1102 result
.type
== BRW_REGISTER_TYPE_UB
||
1103 result
.type
== BRW_REGISTER_TYPE_HF
)
1104 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1106 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1107 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1108 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1109 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1111 inst
= bld
.MOV(result
, op
[0]);
1112 inst
->saturate
= instr
->dest
.saturate
;
1116 inst
= bld
.MOV(result
, op
[0]);
1117 inst
->saturate
= true;
1122 op
[0].negate
= true;
1123 inst
= bld
.MOV(result
, op
[0]);
1124 if (instr
->op
== nir_op_fneg
)
1125 inst
->saturate
= instr
->dest
.saturate
;
1130 op
[0].negate
= false;
1132 inst
= bld
.MOV(result
, op
[0]);
1133 if (instr
->op
== nir_op_fabs
)
1134 inst
->saturate
= instr
->dest
.saturate
;
1138 emit_fsign(bld
, instr
, result
, op
, 0);
1142 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1143 inst
->saturate
= instr
->dest
.saturate
;
1147 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1148 inst
->saturate
= instr
->dest
.saturate
;
1152 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1153 inst
->saturate
= instr
->dest
.saturate
;
1157 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1158 inst
->saturate
= instr
->dest
.saturate
;
1162 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1163 inst
->saturate
= instr
->dest
.saturate
;
1167 if (fs_key
->high_quality_derivatives
) {
1168 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1170 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1172 inst
->saturate
= instr
->dest
.saturate
;
1174 case nir_op_fddx_fine
:
1175 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1176 inst
->saturate
= instr
->dest
.saturate
;
1178 case nir_op_fddx_coarse
:
1179 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1180 inst
->saturate
= instr
->dest
.saturate
;
1183 if (fs_key
->high_quality_derivatives
) {
1184 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1186 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1188 inst
->saturate
= instr
->dest
.saturate
;
1190 case nir_op_fddy_fine
:
1191 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1192 inst
->saturate
= instr
->dest
.saturate
;
1194 case nir_op_fddy_coarse
:
1195 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1196 inst
->saturate
= instr
->dest
.saturate
;
1201 inst
= bld
.ADD(result
, op
[0], op
[1]);
1202 inst
->saturate
= instr
->dest
.saturate
;
1205 case nir_op_uadd_sat
:
1206 inst
= bld
.ADD(result
, op
[0], op
[1]);
1207 inst
->saturate
= true;
1211 for (unsigned i
= 0; i
< 2; i
++) {
1212 if (can_fuse_fmul_fsign(instr
, i
)) {
1213 emit_fsign(bld
, instr
, result
, op
, i
);
1218 inst
= bld
.MUL(result
, op
[0], op
[1]);
1219 inst
->saturate
= instr
->dest
.saturate
;
1222 case nir_op_imul_2x32_64
:
1223 case nir_op_umul_2x32_64
:
1224 bld
.MUL(result
, op
[0], op
[1]);
1228 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1229 bld
.MUL(result
, op
[0], op
[1]);
1232 case nir_op_imul_high
:
1233 case nir_op_umul_high
:
1234 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1235 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1240 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1241 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1244 case nir_op_uadd_carry
:
1245 unreachable("Should have been lowered by carry_to_arith().");
1247 case nir_op_usub_borrow
:
1248 unreachable("Should have been lowered by borrow_to_arith().");
1252 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1253 * appears that our hardware just does the right thing for signed
1256 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1257 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1261 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1262 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1264 /* Math instructions don't support conditional mod */
1265 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1266 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1268 /* Now, we need to determine if signs of the sources are different.
1269 * When we XOR the sources, the top bit is 0 if they are the same and 1
1270 * if they are different. We can then use a conditional modifier to
1271 * turn that into a predicate. This leads us to an XOR.l instruction.
1273 * Technically, according to the PRM, you're not allowed to use .l on a
1274 * XOR instruction. However, emperical experiments and Curro's reading
1275 * of the simulator source both indicate that it's safe.
1277 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1278 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1279 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1280 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1282 /* If the result of the initial remainder operation is non-zero and the
1283 * two sources have different signs, add in a copy of op[1] to get the
1284 * final integer modulus value.
1286 inst
= bld
.ADD(result
, result
, op
[1]);
1287 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1294 case nir_op_fne32
: {
1295 fs_reg dest
= result
;
1297 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1299 dest
= bld
.vgrf(op
[0].type
, 1);
1301 brw_conditional_mod cond
;
1302 switch (instr
->op
) {
1304 cond
= BRW_CONDITIONAL_L
;
1307 cond
= BRW_CONDITIONAL_GE
;
1310 cond
= BRW_CONDITIONAL_Z
;
1313 cond
= BRW_CONDITIONAL_NZ
;
1316 unreachable("bad opcode");
1319 bld
.CMP(dest
, op
[0], op
[1], cond
);
1321 if (bit_size
> 32) {
1322 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1323 } else if(bit_size
< 32) {
1324 /* When we convert the result to 32-bit we need to be careful and do
1325 * it as a signed conversion to get sign extension (for 32-bit true)
1327 const brw_reg_type src_type
=
1328 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1330 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1340 case nir_op_ine32
: {
1341 fs_reg dest
= result
;
1343 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1344 * type. So we convert both operands for the comparison.
1347 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1348 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1350 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1352 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1354 brw_conditional_mod cond
;
1355 switch (instr
->op
) {
1358 cond
= BRW_CONDITIONAL_L
;
1362 cond
= BRW_CONDITIONAL_GE
;
1365 cond
= BRW_CONDITIONAL_Z
;
1368 cond
= BRW_CONDITIONAL_NZ
;
1371 unreachable("bad opcode");
1373 bld
.CMP(dest
, temp_op
[0], temp_op
[1], cond
);
1375 if (bit_size
> 32) {
1376 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1377 } else if (bit_size
< 32) {
1378 /* When we convert the result to 32-bit we need to be careful and do
1379 * it as a signed conversion to get sign extension (for 32-bit true)
1381 const brw_reg_type src_type
=
1382 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1384 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1390 if (devinfo
->gen
>= 8) {
1391 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1393 if (inot_src_instr
!= NULL
&&
1394 (inot_src_instr
->op
== nir_op_ior
||
1395 inot_src_instr
->op
== nir_op_ixor
||
1396 inot_src_instr
->op
== nir_op_iand
) &&
1397 !inot_src_instr
->src
[0].abs
&&
1398 !inot_src_instr
->src
[0].negate
&&
1399 !inot_src_instr
->src
[1].abs
&&
1400 !inot_src_instr
->src
[1].negate
) {
1401 /* The sources of the source logical instruction are now the
1402 * sources of the instruction that will be generated.
1404 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1405 resolve_inot_sources(bld
, inot_src_instr
, op
);
1407 /* Smash all of the sources and destination to be signed. This
1408 * doesn't matter for the operation of the instruction, but cmod
1409 * propagation fails on unsigned sources with negation (due to
1410 * fs_inst::can_do_cmod returning false).
1413 brw_type_for_nir_type(devinfo
,
1414 (nir_alu_type
)(nir_type_int
|
1415 nir_dest_bit_size(instr
->dest
.dest
)));
1417 brw_type_for_nir_type(devinfo
,
1418 (nir_alu_type
)(nir_type_int
|
1419 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1421 brw_type_for_nir_type(devinfo
,
1422 (nir_alu_type
)(nir_type_int
|
1423 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1425 /* For XOR, only invert one of the sources. Arbitrarily choose
1428 op
[0].negate
= !op
[0].negate
;
1429 if (inot_src_instr
->op
!= nir_op_ixor
)
1430 op
[1].negate
= !op
[1].negate
;
1432 switch (inot_src_instr
->op
) {
1434 bld
.AND(result
, op
[0], op
[1]);
1438 bld
.OR(result
, op
[0], op
[1]);
1442 bld
.XOR(result
, op
[0], op
[1]);
1446 unreachable("impossible opcode");
1449 op
[0] = resolve_source_modifiers(op
[0]);
1451 bld
.NOT(result
, op
[0]);
1454 if (devinfo
->gen
>= 8) {
1455 resolve_inot_sources(bld
, instr
, op
);
1457 bld
.XOR(result
, op
[0], op
[1]);
1460 if (devinfo
->gen
>= 8) {
1461 resolve_inot_sources(bld
, instr
, op
);
1463 bld
.OR(result
, op
[0], op
[1]);
1466 if (devinfo
->gen
>= 8) {
1467 resolve_inot_sources(bld
, instr
, op
);
1469 bld
.AND(result
, op
[0], op
[1]);
1475 case nir_op_b32all_fequal2
:
1476 case nir_op_b32all_iequal2
:
1477 case nir_op_b32all_fequal3
:
1478 case nir_op_b32all_iequal3
:
1479 case nir_op_b32all_fequal4
:
1480 case nir_op_b32all_iequal4
:
1481 case nir_op_b32any_fnequal2
:
1482 case nir_op_b32any_inequal2
:
1483 case nir_op_b32any_fnequal3
:
1484 case nir_op_b32any_inequal3
:
1485 case nir_op_b32any_fnequal4
:
1486 case nir_op_b32any_inequal4
:
1487 unreachable("Lowered by nir_lower_alu_reductions");
1489 case nir_op_fnoise1_1
:
1490 case nir_op_fnoise1_2
:
1491 case nir_op_fnoise1_3
:
1492 case nir_op_fnoise1_4
:
1493 case nir_op_fnoise2_1
:
1494 case nir_op_fnoise2_2
:
1495 case nir_op_fnoise2_3
:
1496 case nir_op_fnoise2_4
:
1497 case nir_op_fnoise3_1
:
1498 case nir_op_fnoise3_2
:
1499 case nir_op_fnoise3_3
:
1500 case nir_op_fnoise3_4
:
1501 case nir_op_fnoise4_1
:
1502 case nir_op_fnoise4_2
:
1503 case nir_op_fnoise4_3
:
1504 case nir_op_fnoise4_4
:
1505 unreachable("not reached: should be handled by lower_noise");
1508 unreachable("not reached: should be handled by ldexp_to_arith()");
1511 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1512 inst
->saturate
= instr
->dest
.saturate
;
1516 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1517 inst
->saturate
= instr
->dest
.saturate
;
1521 case nir_op_f2b32
: {
1522 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1523 if (bit_size
== 64) {
1524 /* two-argument instructions can't take 64-bit immediates */
1528 if (instr
->op
== nir_op_f2b32
) {
1529 zero
= vgrf(glsl_type::double_type
);
1530 tmp
= vgrf(glsl_type::double_type
);
1531 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1533 zero
= vgrf(glsl_type::int64_t_type
);
1534 tmp
= vgrf(glsl_type::int64_t_type
);
1535 bld
.MOV(zero
, brw_imm_q(0));
1538 /* A SIMD16 execution needs to be split in two instructions, so use
1539 * a vgrf instead of the flag register as dst so instruction splitting
1542 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1543 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1546 if (bit_size
== 32) {
1547 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1549 assert(bit_size
== 16);
1550 zero
= instr
->op
== nir_op_f2b32
?
1551 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1553 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1559 inst
= bld
.RNDZ(result
, op
[0]);
1560 inst
->saturate
= instr
->dest
.saturate
;
1563 case nir_op_fceil
: {
1564 op
[0].negate
= !op
[0].negate
;
1565 fs_reg temp
= vgrf(glsl_type::float_type
);
1566 bld
.RNDD(temp
, op
[0]);
1568 inst
= bld
.MOV(result
, temp
);
1569 inst
->saturate
= instr
->dest
.saturate
;
1573 inst
= bld
.RNDD(result
, op
[0]);
1574 inst
->saturate
= instr
->dest
.saturate
;
1577 inst
= bld
.FRC(result
, op
[0]);
1578 inst
->saturate
= instr
->dest
.saturate
;
1580 case nir_op_fround_even
:
1581 inst
= bld
.RNDE(result
, op
[0]);
1582 inst
->saturate
= instr
->dest
.saturate
;
1585 case nir_op_fquantize2f16
: {
1586 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1587 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1588 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1590 /* The destination stride must be at least as big as the source stride. */
1591 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1594 /* Check for denormal */
1595 fs_reg abs_src0
= op
[0];
1596 abs_src0
.abs
= true;
1597 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1599 /* Get the appropriately signed zero */
1600 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1601 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1602 brw_imm_ud(0x80000000));
1603 /* Do the actual F32 -> F16 -> F32 conversion */
1604 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1605 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1606 /* Select that or zero based on normal status */
1607 inst
= bld
.SEL(result
, zero
, tmp32
);
1608 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1609 inst
->saturate
= instr
->dest
.saturate
;
1616 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1617 inst
->saturate
= instr
->dest
.saturate
;
1623 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1624 inst
->saturate
= instr
->dest
.saturate
;
1627 case nir_op_pack_snorm_2x16
:
1628 case nir_op_pack_snorm_4x8
:
1629 case nir_op_pack_unorm_2x16
:
1630 case nir_op_pack_unorm_4x8
:
1631 case nir_op_unpack_snorm_2x16
:
1632 case nir_op_unpack_snorm_4x8
:
1633 case nir_op_unpack_unorm_2x16
:
1634 case nir_op_unpack_unorm_4x8
:
1635 case nir_op_unpack_half_2x16
:
1636 case nir_op_pack_half_2x16
:
1637 unreachable("not reached: should be handled by lower_packing_builtins");
1639 case nir_op_unpack_half_2x16_split_x
:
1640 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1641 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1642 inst
->saturate
= instr
->dest
.saturate
;
1644 case nir_op_unpack_half_2x16_split_y
:
1645 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1646 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1647 inst
->saturate
= instr
->dest
.saturate
;
1650 case nir_op_pack_64_2x32_split
:
1651 case nir_op_pack_32_2x16_split
:
1652 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1655 case nir_op_unpack_64_2x32_split_x
:
1656 case nir_op_unpack_64_2x32_split_y
: {
1657 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1658 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1660 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1664 case nir_op_unpack_32_2x16_split_x
:
1665 case nir_op_unpack_32_2x16_split_y
: {
1666 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1667 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1669 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1674 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1675 inst
->saturate
= instr
->dest
.saturate
;
1678 case nir_op_bitfield_reverse
:
1679 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1680 bld
.BFREV(result
, op
[0]);
1683 case nir_op_bit_count
:
1684 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1685 bld
.CBIT(result
, op
[0]);
1688 case nir_op_ufind_msb
: {
1689 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1690 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1694 case nir_op_ifind_msb
: {
1695 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1697 if (devinfo
->gen
< 7) {
1698 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1700 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1702 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1703 * count from the LSB side. If FBH didn't return an error
1704 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1705 * count into an LSB count.
1707 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1709 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1710 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1711 inst
->src
[0].negate
= true;
1716 case nir_op_find_lsb
:
1717 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1719 if (devinfo
->gen
< 7) {
1720 fs_reg temp
= vgrf(glsl_type::int_type
);
1722 /* (x & -x) generates a value that consists of only the LSB of x.
1723 * For all powers of 2, findMSB(y) == findLSB(y).
1725 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1726 fs_reg negated_src
= src
;
1728 /* One must be negated, and the other must be non-negated. It
1729 * doesn't matter which is which.
1731 negated_src
.negate
= true;
1734 bld
.AND(temp
, src
, negated_src
);
1735 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1737 bld
.FBL(result
, op
[0]);
1741 case nir_op_ubitfield_extract
:
1742 case nir_op_ibitfield_extract
:
1743 unreachable("should have been lowered");
1746 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1747 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1750 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1751 bld
.BFI1(result
, op
[0], op
[1]);
1754 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1755 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1758 case nir_op_bitfield_insert
:
1759 unreachable("not reached: should have been lowered");
1762 bld
.SHL(result
, op
[0], op
[1]);
1765 bld
.ASR(result
, op
[0], op
[1]);
1768 bld
.SHR(result
, op
[0], op
[1]);
1771 case nir_op_pack_half_2x16_split
:
1772 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1776 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1777 inst
->saturate
= instr
->dest
.saturate
;
1781 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1782 inst
->saturate
= instr
->dest
.saturate
;
1785 case nir_op_b32csel
:
1786 if (optimize_frontfacing_ternary(instr
, result
))
1789 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1790 inst
= bld
.SEL(result
, op
[1], op
[2]);
1791 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1794 case nir_op_extract_u8
:
1795 case nir_op_extract_i8
: {
1796 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1801 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1802 * Use two instructions and a word or DWord intermediate integer type.
1804 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1805 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1807 if (instr
->op
== nir_op_extract_i8
) {
1808 /* If we need to sign extend, extract to a word first */
1809 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1810 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1811 bld
.MOV(result
, w_temp
);
1812 } else if (byte
& 1) {
1813 /* Extract the high byte from the word containing the desired byte
1817 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1820 /* Otherwise use an AND with 0xff and a word type */
1822 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1826 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1827 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1832 case nir_op_extract_u16
:
1833 case nir_op_extract_i16
: {
1834 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1835 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1836 bld
.MOV(result
, subscript(op
[0], type
, word
));
1841 unreachable("unhandled instruction");
1844 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1845 * to sign extend the low bit to 0/~0
1847 if (devinfo
->gen
<= 5 &&
1848 !result
.is_null() &&
1849 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1850 fs_reg masked
= vgrf(glsl_type::int_type
);
1851 bld
.AND(masked
, result
, brw_imm_d(1));
1852 masked
.negate
= true;
1853 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1858 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1859 nir_load_const_instr
*instr
)
1861 const brw_reg_type reg_type
=
1862 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1863 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1865 switch (instr
->def
.bit_size
) {
1867 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1868 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1872 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1873 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1877 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1878 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1882 assert(devinfo
->gen
>= 7);
1883 if (devinfo
->gen
== 7) {
1884 /* We don't get 64-bit integer types until gen8 */
1885 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1886 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1887 setup_imm_df(bld
, instr
->value
[i
].f64
));
1890 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1891 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1896 unreachable("Invalid bit size");
1899 nir_ssa_values
[instr
->def
.index
] = reg
;
1903 fs_visitor::get_nir_src(const nir_src
&src
)
1907 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1908 const brw_reg_type reg_type
=
1909 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1910 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1912 reg
= nir_ssa_values
[src
.ssa
->index
];
1915 /* We don't handle indirects on locals */
1916 assert(src
.reg
.indirect
== NULL
);
1917 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1918 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1921 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1922 /* The only 64-bit type available on gen7 is DF, so use that. */
1923 reg
.type
= BRW_REGISTER_TYPE_DF
;
1925 /* To avoid floating-point denorm flushing problems, set the type by
1926 * default to an integer type - instructions that need floating point
1927 * semantics will set this to F if they need to
1929 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1930 BRW_REGISTER_TYPE_D
);
1937 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1939 * This function should not be called on any value which may be 64 bits.
1940 * We could theoretically support 64-bit on gen8+ but we choose not to
1941 * because it wouldn't work in general (no gen7 support) and there are
1942 * enough restrictions in 64-bit immediates that you can't take the return
1943 * value and treat it the same as the result of get_nir_src().
1946 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1948 assert(nir_src_bit_size(src
) == 32);
1949 return nir_src_is_const(src
) ?
1950 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1954 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1957 const brw_reg_type reg_type
=
1958 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1959 dest
.ssa
.bit_size
== 8 ?
1960 BRW_REGISTER_TYPE_D
:
1961 BRW_REGISTER_TYPE_F
);
1962 nir_ssa_values
[dest
.ssa
.index
] =
1963 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1964 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
1965 return nir_ssa_values
[dest
.ssa
.index
];
1967 /* We don't handle indirects on locals */
1968 assert(dest
.reg
.indirect
== NULL
);
1969 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1970 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1975 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1978 for (unsigned i
= 0; i
< 4; i
++) {
1979 if (!((wr_mask
>> i
) & 1))
1982 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1983 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1984 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1985 if (new_inst
->src
[j
].file
== VGRF
)
1986 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1993 emit_pixel_interpolater_send(const fs_builder
&bld
,
1998 glsl_interp_mode interpolation
)
2000 struct brw_wm_prog_data
*wm_prog_data
=
2001 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2003 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2004 /* 2 floats per slot returned */
2005 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2006 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2008 wm_prog_data
->pulls_bary
= true;
2014 * Computes 1 << x, given a D/UD register containing some value x.
2017 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2019 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2021 fs_reg result
= bld
.vgrf(x
.type
, 1);
2022 fs_reg one
= bld
.vgrf(x
.type
, 1);
2024 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2025 bld
.SHL(result
, one
, x
);
2030 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2032 assert(stage
== MESA_SHADER_GEOMETRY
);
2034 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2036 if (gs_compile
->control_data_header_size_bits
== 0)
2039 /* We can only do EndPrimitive() functionality when the control data
2040 * consists of cut bits. Fortunately, the only time it isn't is when the
2041 * output type is points, in which case EndPrimitive() is a no-op.
2043 if (gs_prog_data
->control_data_format
!=
2044 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2048 /* Cut bits use one bit per vertex. */
2049 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2051 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2052 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2054 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2055 * vertex n, 0 otherwise. So all we need to do here is mark bit
2056 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2057 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2058 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2060 * Note that if EndPrimitive() is called before emitting any vertices, this
2061 * will cause us to set bit 31 of the control_data_bits register to 1.
2062 * That's fine because:
2064 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2065 * output, so the hardware will ignore cut bit 31.
2067 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2068 * last vertex, so setting cut bit 31 has no effect (since the primitive
2069 * is automatically ended when the GS terminates).
2071 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2072 * control_data_bits register to 0 when the first vertex is emitted.
2075 const fs_builder abld
= bld
.annotate("end primitive");
2077 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2078 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2079 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2080 fs_reg mask
= intexp2(abld
, prev_count
);
2081 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2082 * attention to the lower 5 bits of its second source argument, so on this
2083 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2084 * ((vertex_count - 1) % 32).
2086 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2090 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2092 assert(stage
== MESA_SHADER_GEOMETRY
);
2093 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2095 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2097 const fs_builder abld
= bld
.annotate("emit control data bits");
2098 const fs_builder fwa_bld
= bld
.exec_all();
2100 /* We use a single UD register to accumulate control data bits (32 bits
2101 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2104 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2105 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2106 * use the Channel Mask phase to enable/disable which DWord within that
2107 * group to write. (Remember, different SIMD8 channels may have emitted
2108 * different numbers of vertices, so we may need per-slot offsets.)
2110 * Channel masking presents an annoying problem: we may have to replicate
2111 * the data up to 4 times:
2113 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2115 * To avoid penalizing shaders that emit a small number of vertices, we
2116 * can avoid these sometimes: if the size of the control data header is
2117 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2118 * land in the same 128-bit group, so we can skip per-slot offsets.
2120 * Similarly, if the control data header is <= 32 bits, there is only one
2121 * DWord, so we can skip channel masks.
2123 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2125 fs_reg channel_mask
, per_slot_offset
;
2127 if (gs_compile
->control_data_header_size_bits
> 32) {
2128 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2129 channel_mask
= vgrf(glsl_type::uint_type
);
2132 if (gs_compile
->control_data_header_size_bits
> 128) {
2133 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2134 per_slot_offset
= vgrf(glsl_type::uint_type
);
2137 /* Figure out which DWord we're trying to write to using the formula:
2139 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2141 * Since bits_per_vertex is a power of two, and is known at compile
2142 * time, this can be optimized to:
2144 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2146 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2147 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2148 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2149 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2150 unsigned log2_bits_per_vertex
=
2151 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2152 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2154 if (per_slot_offset
.file
!= BAD_FILE
) {
2155 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2156 * the appropriate OWord within the control data header.
2158 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2161 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2162 * write to the appropriate DWORD within the OWORD.
2164 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2165 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2166 channel_mask
= intexp2(fwa_bld
, channel
);
2167 /* Then the channel masks need to be in bits 23:16. */
2168 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2171 /* Store the control data bits in the message payload and send it. */
2173 if (channel_mask
.file
!= BAD_FILE
)
2174 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2175 if (per_slot_offset
.file
!= BAD_FILE
)
2178 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2179 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2181 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2182 if (per_slot_offset
.file
!= BAD_FILE
)
2183 sources
[i
++] = per_slot_offset
;
2184 if (channel_mask
.file
!= BAD_FILE
)
2185 sources
[i
++] = channel_mask
;
2187 sources
[i
++] = this->control_data_bits
;
2190 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2191 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2193 /* We need to increment Global Offset by 256-bits to make room for
2194 * Broadwell's extra "Vertex Count" payload at the beginning of the
2195 * URB entry. Since this is an OWord message, Global Offset is counted
2196 * in 128-bit units, so we must set it to 2.
2198 if (gs_prog_data
->static_vertex_count
== -1)
2203 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2206 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2208 /* Note: we are calling this *before* increasing vertex_count, so
2209 * this->vertex_count == vertex_count - 1 in the formula above.
2212 /* Stream mode uses 2 bits per vertex */
2213 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2215 /* Must be a valid stream */
2216 assert(stream_id
< MAX_VERTEX_STREAMS
);
2218 /* Control data bits are initialized to 0 so we don't have to set any
2219 * bits when sending vertices to stream 0.
2224 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2226 /* reg::sid = stream_id */
2227 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2228 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2230 /* reg:shift_count = 2 * (vertex_count - 1) */
2231 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2232 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2234 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2235 * attention to the lower 5 bits of its second source argument, so on this
2236 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2237 * stream_id << ((2 * (vertex_count - 1)) % 32).
2239 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2240 abld
.SHL(mask
, sid
, shift_count
);
2241 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2245 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2248 assert(stage
== MESA_SHADER_GEOMETRY
);
2250 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2252 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2253 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2255 /* Haswell and later hardware ignores the "Render Stream Select" bits
2256 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2257 * and instead sends all primitives down the pipeline for rasterization.
2258 * If the SOL stage is enabled, "Render Stream Select" is honored and
2259 * primitives bound to non-zero streams are discarded after stream output.
2261 * Since the only purpose of primives sent to non-zero streams is to
2262 * be recorded by transform feedback, we can simply discard all geometry
2263 * bound to these streams when transform feedback is disabled.
2265 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2268 /* If we're outputting 32 control data bits or less, then we can wait
2269 * until the shader is over to output them all. Otherwise we need to
2270 * output them as we go. Now is the time to do it, since we're about to
2271 * output the vertex_count'th vertex, so it's guaranteed that the
2272 * control data bits associated with the (vertex_count - 1)th vertex are
2275 if (gs_compile
->control_data_header_size_bits
> 32) {
2276 const fs_builder abld
=
2277 bld
.annotate("emit vertex: emit control data bits");
2279 /* Only emit control data bits if we've finished accumulating a batch
2280 * of 32 bits. This is the case when:
2282 * (vertex_count * bits_per_vertex) % 32 == 0
2284 * (in other words, when the last 5 bits of vertex_count *
2285 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2286 * integer n (which is always the case, since bits_per_vertex is
2287 * always 1 or 2), this is equivalent to requiring that the last 5-n
2288 * bits of vertex_count are 0:
2290 * vertex_count & (2^(5-n) - 1) == 0
2292 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2295 * vertex_count & (32 / bits_per_vertex - 1) == 0
2297 * TODO: If vertex_count is an immediate, we could do some of this math
2298 * at compile time...
2301 abld
.AND(bld
.null_reg_d(), vertex_count
,
2302 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2303 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2305 abld
.IF(BRW_PREDICATE_NORMAL
);
2306 /* If vertex_count is 0, then no control data bits have been
2307 * accumulated yet, so we can skip emitting them.
2309 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2310 BRW_CONDITIONAL_NEQ
);
2311 abld
.IF(BRW_PREDICATE_NORMAL
);
2312 emit_gs_control_data_bits(vertex_count
);
2313 abld
.emit(BRW_OPCODE_ENDIF
);
2315 /* Reset control_data_bits to 0 so we can start accumulating a new
2318 * Note: in the case where vertex_count == 0, this neutralizes the
2319 * effect of any call to EndPrimitive() that the shader may have
2320 * made before outputting its first vertex.
2322 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2323 inst
->force_writemask_all
= true;
2324 abld
.emit(BRW_OPCODE_ENDIF
);
2327 emit_urb_writes(vertex_count
);
2329 /* In stream mode we have to set control data bits for all vertices
2330 * unless we have disabled control data bits completely (which we do
2331 * do for GL_POINTS outputs that don't use streams).
2333 if (gs_compile
->control_data_header_size_bits
> 0 &&
2334 gs_prog_data
->control_data_format
==
2335 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2336 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2341 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2342 const nir_src
&vertex_src
,
2343 unsigned base_offset
,
2344 const nir_src
&offset_src
,
2345 unsigned num_components
,
2346 unsigned first_component
)
2348 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2349 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2351 /* TODO: figure out push input layout for invocations == 1 */
2352 /* TODO: make this work with 64-bit inputs */
2353 if (gs_prog_data
->invocations
== 1 &&
2354 type_sz(dst
.type
) <= 4 &&
2355 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2356 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2357 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2358 nir_src_as_uint(vertex_src
) * push_reg_count
;
2359 for (unsigned i
= 0; i
< num_components
; i
++) {
2360 bld
.MOV(offset(dst
, bld
, i
),
2361 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2366 /* Resort to the pull model. Ensure the VUE handles are provided. */
2367 assert(gs_prog_data
->base
.include_vue_handles
);
2369 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2370 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2372 if (gs_prog_data
->invocations
== 1) {
2373 if (nir_src_is_const(vertex_src
)) {
2374 /* The vertex index is constant; just select the proper URB handle. */
2376 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2377 BRW_REGISTER_TYPE_UD
);
2379 /* The vertex index is non-constant. We need to use indirect
2380 * addressing to fetch the proper URB handle.
2382 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2383 * indicating that channel <n> should read the handle from
2384 * DWord <n>. We convert that to bytes by multiplying by 4.
2386 * Next, we convert the vertex index to bytes by multiplying
2387 * by 32 (shifting by 5), and add the two together. This is
2388 * the final indirect byte offset.
2390 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2391 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2392 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2393 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2395 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2396 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2397 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2398 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2399 /* Convert vertex_index to bytes (multiply by 32) */
2400 bld
.SHL(vertex_offset_bytes
,
2401 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2403 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2405 /* Use first_icp_handle as the base offset. There is one register
2406 * of URB handles per vertex, so inform the register allocator that
2407 * we might read up to nir->info.gs.vertices_in registers.
2409 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2410 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2411 fs_reg(icp_offset_bytes
),
2412 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2415 assert(gs_prog_data
->invocations
> 1);
2417 if (nir_src_is_const(vertex_src
)) {
2418 unsigned vertex
= nir_src_as_uint(vertex_src
);
2419 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2421 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2422 BRW_REGISTER_TYPE_UD
));
2424 /* The vertex index is non-constant. We need to use indirect
2425 * addressing to fetch the proper URB handle.
2428 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2430 /* Convert vertex_index to bytes (multiply by 4) */
2431 bld
.SHL(icp_offset_bytes
,
2432 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2435 /* Use first_icp_handle as the base offset. There is one DWord
2436 * of URB handles per vertex, so inform the register allocator that
2437 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2439 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2440 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2441 fs_reg(icp_offset_bytes
),
2442 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2449 fs_reg tmp_dst
= dst
;
2450 fs_reg indirect_offset
= get_nir_src(offset_src
);
2451 unsigned num_iterations
= 1;
2452 unsigned orig_num_components
= num_components
;
2454 if (type_sz(dst
.type
) == 8) {
2455 if (num_components
> 2) {
2459 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2461 first_component
= first_component
/ 2;
2464 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2465 if (nir_src_is_const(offset_src
)) {
2466 /* Constant indexing - use global offset. */
2467 if (first_component
!= 0) {
2468 unsigned read_components
= num_components
+ first_component
;
2469 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2470 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2471 inst
->size_written
= read_components
*
2472 tmp
.component_size(inst
->exec_size
);
2473 for (unsigned i
= 0; i
< num_components
; i
++) {
2474 bld
.MOV(offset(tmp_dst
, bld
, i
),
2475 offset(tmp
, bld
, i
+ first_component
));
2478 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2480 inst
->size_written
= num_components
*
2481 tmp_dst
.component_size(inst
->exec_size
);
2483 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2486 /* Indirect indexing - use per-slot offsets as well. */
2487 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2488 unsigned read_components
= num_components
+ first_component
;
2489 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2490 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2491 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2492 if (first_component
!= 0) {
2493 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2495 inst
->size_written
= read_components
*
2496 tmp
.component_size(inst
->exec_size
);
2497 for (unsigned i
= 0; i
< num_components
; i
++) {
2498 bld
.MOV(offset(tmp_dst
, bld
, i
),
2499 offset(tmp
, bld
, i
+ first_component
));
2502 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2504 inst
->size_written
= num_components
*
2505 tmp_dst
.component_size(inst
->exec_size
);
2507 inst
->offset
= base_offset
;
2511 if (type_sz(dst
.type
) == 8) {
2512 shuffle_from_32bit_read(bld
,
2513 offset(dst
, bld
, iter
* 2),
2514 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2519 if (num_iterations
> 1) {
2520 num_components
= orig_num_components
- 2;
2521 if(nir_src_is_const(offset_src
)) {
2524 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2525 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2526 indirect_offset
= new_indirect
;
2533 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2535 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2537 if (nir_src_is_const(*offset_src
)) {
2538 /* The only constant offset we should find is 0. brw_nir.c's
2539 * add_const_offset_to_base() will fold other constant offsets
2540 * into instr->const_index[0].
2542 assert(nir_src_as_uint(*offset_src
) == 0);
2546 return get_nir_src(*offset_src
);
2550 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2551 nir_intrinsic_instr
*instr
)
2553 assert(stage
== MESA_SHADER_VERTEX
);
2556 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2557 dest
= get_nir_dest(instr
->dest
);
2559 switch (instr
->intrinsic
) {
2560 case nir_intrinsic_load_vertex_id
:
2561 case nir_intrinsic_load_base_vertex
:
2562 unreachable("should be lowered by nir_lower_system_values()");
2564 case nir_intrinsic_load_input
: {
2565 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2566 unsigned first_component
= nir_intrinsic_component(instr
);
2567 unsigned num_components
= instr
->num_components
;
2569 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2571 if (type_sz(dest
.type
) == 8)
2572 first_component
/= 2;
2574 /* For 16-bit support maybe a temporary will be needed to copy from
2577 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2578 first_component
, num_components
);
2582 case nir_intrinsic_load_vertex_id_zero_base
:
2583 case nir_intrinsic_load_instance_id
:
2584 case nir_intrinsic_load_base_instance
:
2585 case nir_intrinsic_load_draw_id
:
2586 case nir_intrinsic_load_first_vertex
:
2587 case nir_intrinsic_load_is_indexed_draw
:
2588 unreachable("lowered by brw_nir_lower_vs_inputs");
2591 nir_emit_intrinsic(bld
, instr
);
2597 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2598 nir_intrinsic_instr
*instr
)
2600 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2601 const nir_src
&vertex_src
= instr
->src
[0];
2602 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2605 if (nir_src_is_const(vertex_src
)) {
2606 /* Emit a MOV to resolve <0,1,0> regioning. */
2607 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2608 unsigned vertex
= nir_src_as_uint(vertex_src
);
2610 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2611 BRW_REGISTER_TYPE_UD
));
2612 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2613 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2614 /* For the common case of only 1 instance, an array index of
2615 * gl_InvocationID means reading g1. Skip all the indirect work.
2617 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2619 /* The vertex index is non-constant. We need to use indirect
2620 * addressing to fetch the proper URB handle.
2622 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2624 /* Each ICP handle is a single DWord (4 bytes) */
2625 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2626 bld
.SHL(vertex_offset_bytes
,
2627 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2630 /* Start at g1. We might read up to 4 registers. */
2631 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2632 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2633 brw_imm_ud(4 * REG_SIZE
));
2640 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2641 nir_intrinsic_instr
*instr
)
2643 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2644 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2645 const nir_src
&vertex_src
= instr
->src
[0];
2647 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2649 if (nir_src_is_const(vertex_src
)) {
2650 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2651 nir_src_as_uint(vertex_src
), 0),
2652 BRW_REGISTER_TYPE_UD
));
2655 /* The vertex index is non-constant. We need to use indirect
2656 * addressing to fetch the proper URB handle.
2658 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2659 * indicating that channel <n> should read the handle from
2660 * DWord <n>. We convert that to bytes by multiplying by 4.
2662 * Next, we convert the vertex index to bytes by multiplying
2663 * by 32 (shifting by 5), and add the two together. This is
2664 * the final indirect byte offset.
2666 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2667 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2668 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2669 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2670 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2672 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2673 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2674 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2675 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2676 /* Convert vertex_index to bytes (multiply by 32) */
2677 bld
.SHL(vertex_offset_bytes
,
2678 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2680 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2682 /* Use first_icp_handle as the base offset. There is one register
2683 * of URB handles per vertex, so inform the register allocator that
2684 * we might read up to nir->info.gs.vertices_in registers.
2686 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2687 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2688 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2694 fs_visitor::get_tcs_output_urb_handle()
2696 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2698 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2699 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2701 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2702 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2707 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2708 nir_intrinsic_instr
*instr
)
2710 assert(stage
== MESA_SHADER_TESS_CTRL
);
2711 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2712 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2713 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2716 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2719 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2720 dst
= get_nir_dest(instr
->dest
);
2722 switch (instr
->intrinsic
) {
2723 case nir_intrinsic_load_primitive_id
:
2724 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2725 : brw_vec1_grf(0, 1)));
2727 case nir_intrinsic_load_invocation_id
:
2728 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2730 case nir_intrinsic_load_patch_vertices_in
:
2731 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2732 brw_imm_d(tcs_key
->input_vertices
));
2735 case nir_intrinsic_barrier
: {
2736 if (tcs_prog_data
->instances
== 1)
2739 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2740 fs_reg m0_2
= component(m0
, 2);
2742 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2744 /* Zero the message header */
2745 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2747 if (devinfo
->gen
< 11) {
2748 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2749 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2750 brw_imm_ud(INTEL_MASK(16, 13)));
2752 /* Shift it up to bits 27:24. */
2753 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2755 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2756 brw_imm_ud(INTEL_MASK(30, 24)));
2759 /* Set the Barrier Count and the enable bit */
2760 if (devinfo
->gen
< 11) {
2761 chanbld
.OR(m0_2
, m0_2
,
2762 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2764 chanbld
.OR(m0_2
, m0_2
,
2765 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2768 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2772 case nir_intrinsic_load_input
:
2773 unreachable("nir_lower_io should never give us these.");
2776 case nir_intrinsic_load_per_vertex_input
: {
2777 fs_reg indirect_offset
= get_indirect_offset(instr
);
2778 unsigned imm_offset
= instr
->const_index
[0];
2782 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2783 : get_tcs_single_patch_icp_handle(bld
, instr
);
2785 /* We can only read two double components with each URB read, so
2786 * we send two read messages in that case, each one loading up to
2787 * two double components.
2789 unsigned num_iterations
= 1;
2790 unsigned num_components
= instr
->num_components
;
2791 unsigned first_component
= nir_intrinsic_component(instr
);
2792 fs_reg orig_dst
= dst
;
2793 if (type_sz(dst
.type
) == 8) {
2794 first_component
= first_component
/ 2;
2795 if (instr
->num_components
> 2) {
2800 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2804 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2805 if (indirect_offset
.file
== BAD_FILE
) {
2806 /* Constant indexing - use global offset. */
2807 if (first_component
!= 0) {
2808 unsigned read_components
= num_components
+ first_component
;
2809 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2810 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2811 for (unsigned i
= 0; i
< num_components
; i
++) {
2812 bld
.MOV(offset(dst
, bld
, i
),
2813 offset(tmp
, bld
, i
+ first_component
));
2816 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2818 inst
->offset
= imm_offset
;
2821 /* Indirect indexing - use per-slot offsets as well. */
2822 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2823 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2824 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2825 if (first_component
!= 0) {
2826 unsigned read_components
= num_components
+ first_component
;
2827 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2828 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2830 for (unsigned i
= 0; i
< num_components
; i
++) {
2831 bld
.MOV(offset(dst
, bld
, i
),
2832 offset(tmp
, bld
, i
+ first_component
));
2835 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2838 inst
->offset
= imm_offset
;
2841 inst
->size_written
= (num_components
+ first_component
) *
2842 inst
->dst
.component_size(inst
->exec_size
);
2844 /* If we are reading 64-bit data using 32-bit read messages we need
2845 * build proper 64-bit data elements by shuffling the low and high
2846 * 32-bit components around like we do for other things like UBOs
2849 if (type_sz(dst
.type
) == 8) {
2850 shuffle_from_32bit_read(bld
,
2851 offset(orig_dst
, bld
, iter
* 2),
2852 retype(dst
, BRW_REGISTER_TYPE_D
),
2856 /* Copy the temporary to the destination to deal with writemasking.
2858 * Also attempt to deal with gl_PointSize being in the .w component.
2860 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2861 assert(type_sz(dst
.type
) < 8);
2862 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2863 inst
->size_written
= 4 * REG_SIZE
;
2864 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2867 /* If we are loading double data and we need a second read message
2868 * adjust the write offset
2870 if (num_iterations
> 1) {
2871 num_components
= instr
->num_components
- 2;
2878 case nir_intrinsic_load_output
:
2879 case nir_intrinsic_load_per_vertex_output
: {
2880 fs_reg indirect_offset
= get_indirect_offset(instr
);
2881 unsigned imm_offset
= instr
->const_index
[0];
2882 unsigned first_component
= nir_intrinsic_component(instr
);
2884 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2887 if (indirect_offset
.file
== BAD_FILE
) {
2888 /* This MOV replicates the output handle to all enabled channels
2889 * is SINGLE_PATCH mode.
2891 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2892 bld
.MOV(patch_handle
, output_handles
);
2895 if (first_component
!= 0) {
2896 unsigned read_components
=
2897 instr
->num_components
+ first_component
;
2898 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2899 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2901 inst
->size_written
= read_components
* REG_SIZE
;
2902 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2903 bld
.MOV(offset(dst
, bld
, i
),
2904 offset(tmp
, bld
, i
+ first_component
));
2907 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2909 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2911 inst
->offset
= imm_offset
;
2915 /* Indirect indexing - use per-slot offsets as well. */
2916 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2917 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2918 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2919 if (first_component
!= 0) {
2920 unsigned read_components
=
2921 instr
->num_components
+ first_component
;
2922 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2923 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2925 inst
->size_written
= read_components
* REG_SIZE
;
2926 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2927 bld
.MOV(offset(dst
, bld
, i
),
2928 offset(tmp
, bld
, i
+ first_component
));
2931 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2933 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2935 inst
->offset
= imm_offset
;
2941 case nir_intrinsic_store_output
:
2942 case nir_intrinsic_store_per_vertex_output
: {
2943 fs_reg value
= get_nir_src(instr
->src
[0]);
2944 bool is_64bit
= (instr
->src
[0].is_ssa
?
2945 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2946 fs_reg indirect_offset
= get_indirect_offset(instr
);
2947 unsigned imm_offset
= instr
->const_index
[0];
2948 unsigned mask
= instr
->const_index
[1];
2949 unsigned header_regs
= 0;
2950 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2953 srcs
[header_regs
++] = output_handles
;
2955 if (indirect_offset
.file
!= BAD_FILE
) {
2956 srcs
[header_regs
++] = indirect_offset
;
2962 unsigned num_components
= util_last_bit(mask
);
2965 /* We can only pack two 64-bit components in a single message, so send
2966 * 2 messages if we have more components
2968 unsigned num_iterations
= 1;
2969 unsigned iter_components
= num_components
;
2970 unsigned first_component
= nir_intrinsic_component(instr
);
2972 first_component
= first_component
/ 2;
2973 if (instr
->num_components
> 2) {
2975 iter_components
= 2;
2979 mask
= mask
<< first_component
;
2981 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2982 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2983 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2984 opcode
= indirect_offset
.file
!= BAD_FILE
?
2985 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2986 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2987 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2988 /* Expand the 64-bit mask to 32-bit channels. We only handle
2989 * two channels in each iteration, so we only care about X/Y.
2991 unsigned mask32
= 0;
2992 if (mask
& WRITEMASK_X
)
2993 mask32
|= WRITEMASK_XY
;
2994 if (mask
& WRITEMASK_Y
)
2995 mask32
|= WRITEMASK_ZW
;
2997 /* If the mask does not include any of the channels X or Y there
2998 * is nothing to do in this iteration. Move on to the next couple
2999 * of 64-bit channels.
3007 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
3008 opcode
= indirect_offset
.file
!= BAD_FILE
?
3009 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
3010 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
3012 opcode
= indirect_offset
.file
!= BAD_FILE
?
3013 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
3014 SHADER_OPCODE_URB_WRITE_SIMD8
;
3017 for (unsigned i
= 0; i
< iter_components
; i
++) {
3018 if (!(mask
& (1 << (i
+ first_component
))))
3022 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
3024 /* We need to shuffle the 64-bit data to match the layout
3025 * expected by our 32-bit URB write messages. We use a temporary
3028 unsigned channel
= iter
* 2 + i
;
3029 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
3031 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
3032 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
3033 offset(dest
, bld
, 1);
3038 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
3039 (is_64bit
? 2 * first_component
: first_component
);
3041 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
3042 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
3044 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
3045 inst
->offset
= imm_offset
;
3048 /* If this is a 64-bit attribute, select the next two 64-bit channels
3049 * to be handled in the next iteration.
3060 nir_emit_intrinsic(bld
, instr
);
3066 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
3067 nir_intrinsic_instr
*instr
)
3069 assert(stage
== MESA_SHADER_TESS_EVAL
);
3070 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
3073 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3074 dest
= get_nir_dest(instr
->dest
);
3076 switch (instr
->intrinsic
) {
3077 case nir_intrinsic_load_primitive_id
:
3078 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3080 case nir_intrinsic_load_tess_coord
:
3081 /* gl_TessCoord is part of the payload in g1-3 */
3082 for (unsigned i
= 0; i
< 3; i
++) {
3083 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3087 case nir_intrinsic_load_input
:
3088 case nir_intrinsic_load_per_vertex_input
: {
3089 fs_reg indirect_offset
= get_indirect_offset(instr
);
3090 unsigned imm_offset
= instr
->const_index
[0];
3091 unsigned first_component
= nir_intrinsic_component(instr
);
3093 if (type_sz(dest
.type
) == 8) {
3094 first_component
= first_component
/ 2;
3098 if (indirect_offset
.file
== BAD_FILE
) {
3099 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3100 * which is 16 registers (since each holds 2 vec4 slots).
3102 unsigned slot_count
= 1;
3103 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
3106 const unsigned max_push_slots
= 32;
3107 if (imm_offset
+ slot_count
<= max_push_slots
) {
3108 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3109 for (int i
= 0; i
< instr
->num_components
; i
++) {
3110 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
3111 i
+ first_component
;
3112 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3115 tes_prog_data
->base
.urb_read_length
=
3116 MAX2(tes_prog_data
->base
.urb_read_length
,
3117 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
3119 /* Replicate the patch handle to all enabled channels */
3120 const fs_reg srcs
[] = {
3121 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3123 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3124 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3126 if (first_component
!= 0) {
3127 unsigned read_components
=
3128 instr
->num_components
+ first_component
;
3129 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3130 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3132 inst
->size_written
= read_components
* REG_SIZE
;
3133 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3134 bld
.MOV(offset(dest
, bld
, i
),
3135 offset(tmp
, bld
, i
+ first_component
));
3138 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3140 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3143 inst
->offset
= imm_offset
;
3146 /* Indirect indexing - use per-slot offsets as well. */
3148 /* We can only read two double components with each URB read, so
3149 * we send two read messages in that case, each one loading up to
3150 * two double components.
3152 unsigned num_iterations
= 1;
3153 unsigned num_components
= instr
->num_components
;
3154 fs_reg orig_dest
= dest
;
3155 if (type_sz(dest
.type
) == 8) {
3156 if (instr
->num_components
> 2) {
3160 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3164 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3165 const fs_reg srcs
[] = {
3166 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3169 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3170 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3172 if (first_component
!= 0) {
3173 unsigned read_components
=
3174 num_components
+ first_component
;
3175 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3176 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3178 for (unsigned i
= 0; i
< num_components
; i
++) {
3179 bld
.MOV(offset(dest
, bld
, i
),
3180 offset(tmp
, bld
, i
+ first_component
));
3183 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3187 inst
->offset
= imm_offset
;
3188 inst
->size_written
= (num_components
+ first_component
) *
3189 inst
->dst
.component_size(inst
->exec_size
);
3191 /* If we are reading 64-bit data using 32-bit read messages we need
3192 * build proper 64-bit data elements by shuffling the low and high
3193 * 32-bit components around like we do for other things like UBOs
3196 if (type_sz(dest
.type
) == 8) {
3197 shuffle_from_32bit_read(bld
,
3198 offset(orig_dest
, bld
, iter
* 2),
3199 retype(dest
, BRW_REGISTER_TYPE_D
),
3203 /* If we are loading double data and we need a second read message
3206 if (num_iterations
> 1) {
3207 num_components
= instr
->num_components
- 2;
3215 nir_emit_intrinsic(bld
, instr
);
3221 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3222 nir_intrinsic_instr
*instr
)
3224 assert(stage
== MESA_SHADER_GEOMETRY
);
3225 fs_reg indirect_offset
;
3228 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3229 dest
= get_nir_dest(instr
->dest
);
3231 switch (instr
->intrinsic
) {
3232 case nir_intrinsic_load_primitive_id
:
3233 assert(stage
== MESA_SHADER_GEOMETRY
);
3234 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3235 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3236 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3239 case nir_intrinsic_load_input
:
3240 unreachable("load_input intrinsics are invalid for the GS stage");
3242 case nir_intrinsic_load_per_vertex_input
:
3243 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3244 instr
->src
[1], instr
->num_components
,
3245 nir_intrinsic_component(instr
));
3248 case nir_intrinsic_emit_vertex_with_counter
:
3249 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3252 case nir_intrinsic_end_primitive_with_counter
:
3253 emit_gs_end_primitive(instr
->src
[0]);
3256 case nir_intrinsic_set_vertex_count
:
3257 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3260 case nir_intrinsic_load_invocation_id
: {
3261 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3262 assert(val
.file
!= BAD_FILE
);
3263 dest
.type
= val
.type
;
3269 nir_emit_intrinsic(bld
, instr
);
3275 * Fetch the current render target layer index.
3278 fetch_render_target_array_index(const fs_builder
&bld
)
3280 if (bld
.shader
->devinfo
->gen
>= 6) {
3281 /* The render target array index is provided in the thread payload as
3282 * bits 26:16 of r0.0.
3284 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3285 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3289 /* Pre-SNB we only ever render into the first layer of the framebuffer
3290 * since layered rendering is not implemented.
3292 return brw_imm_ud(0);
3297 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3298 * framebuffer at the current fragment coordinates and sample index.
3301 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3304 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3306 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3307 const brw_wm_prog_key
*wm_key
=
3308 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3309 assert(!wm_key
->coherent_fb_fetch
);
3310 const struct brw_wm_prog_data
*wm_prog_data
=
3311 brw_wm_prog_data(stage_prog_data
);
3313 /* Calculate the surface index relative to the start of the texture binding
3314 * table block, since that's what the texturing messages expect.
3316 const unsigned surface
= target
+
3317 wm_prog_data
->binding_table
.render_target_read_start
-
3318 wm_prog_data
->base
.binding_table
.texture_start
;
3320 /* Calculate the fragment coordinates. */
3321 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3322 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3323 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3324 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3326 /* Calculate the sample index and MCS payload when multisampling. Luckily
3327 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3328 * shouldn't be necessary to recompile based on whether the framebuffer is
3331 if (wm_key
->multisample_fbo
&&
3332 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3333 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3335 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3336 const fs_reg mcs
= wm_key
->multisample_fbo
?
3337 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3339 /* Use either a normal or a CMS texel fetch message depending on whether
3340 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3341 * message just in case the framebuffer uses 16x multisampling, it should
3342 * be equivalent to the normal CMS fetch for lower multisampling modes.
3344 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3345 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3346 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3348 /* Emit the instruction. */
3349 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3350 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3351 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3352 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3353 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3354 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3355 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3356 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3357 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3359 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3360 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3366 * Actual coherent framebuffer read implemented using the native render target
3367 * read message. Requires SKL+.
3370 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3372 assert(bld
.shader
->devinfo
->gen
>= 9);
3373 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3374 inst
->target
= target
;
3375 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3381 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3383 if (n
&& regs
[0].file
!= BAD_FILE
) {
3387 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3389 for (unsigned i
= 0; i
< n
; i
++)
3397 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3399 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3400 const brw_wm_prog_key
*const key
=
3401 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3402 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3403 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3405 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3406 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3408 else if (l
== FRAG_RESULT_COLOR
)
3409 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3410 MAX2(key
->nr_color_regions
, 1));
3412 else if (l
== FRAG_RESULT_DEPTH
)
3413 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3415 else if (l
== FRAG_RESULT_STENCIL
)
3416 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3418 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3419 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3421 else if (l
>= FRAG_RESULT_DATA0
&&
3422 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3423 return alloc_temporary(v
->bld
, 4,
3424 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3427 unreachable("Invalid location");
3431 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3432 nir_intrinsic_instr
*instr
)
3434 assert(stage
== MESA_SHADER_FRAGMENT
);
3437 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3438 dest
= get_nir_dest(instr
->dest
);
3440 switch (instr
->intrinsic
) {
3441 case nir_intrinsic_load_front_face
:
3442 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3443 *emit_frontfacing_interpolation());
3446 case nir_intrinsic_load_sample_pos
: {
3447 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3448 assert(sample_pos
.file
!= BAD_FILE
);
3449 dest
.type
= sample_pos
.type
;
3450 bld
.MOV(dest
, sample_pos
);
3451 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3455 case nir_intrinsic_load_layer_id
:
3456 dest
.type
= BRW_REGISTER_TYPE_UD
;
3457 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3460 case nir_intrinsic_load_helper_invocation
:
3461 case nir_intrinsic_load_sample_mask_in
:
3462 case nir_intrinsic_load_sample_id
: {
3463 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3464 fs_reg val
= nir_system_values
[sv
];
3465 assert(val
.file
!= BAD_FILE
);
3466 dest
.type
= val
.type
;
3471 case nir_intrinsic_store_output
: {
3472 const fs_reg src
= get_nir_src(instr
->src
[0]);
3473 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3474 const unsigned location
= nir_intrinsic_base(instr
) +
3475 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3476 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3479 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3480 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3481 offset(src
, bld
, j
));
3486 case nir_intrinsic_load_output
: {
3487 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3488 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3489 assert(l
>= FRAG_RESULT_DATA0
);
3490 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3491 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3492 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3494 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3495 emit_coherent_fb_read(bld
, tmp
, target
);
3497 emit_non_coherent_fb_read(bld
, tmp
, target
);
3499 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3500 bld
.MOV(offset(dest
, bld
, j
),
3501 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3507 case nir_intrinsic_discard
:
3508 case nir_intrinsic_discard_if
: {
3509 /* We track our discarded pixels in f0.1. By predicating on it, we can
3510 * update just the flag bits that aren't yet discarded. If there's no
3511 * condition, we emit a CMP of g0 != g0, so all currently executing
3512 * channels will get turned off.
3514 fs_inst
*cmp
= NULL
;
3515 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3516 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3519 alu
->op
!= nir_op_bcsel
&&
3520 alu
->op
!= nir_op_inot
) {
3521 /* Re-emit the instruction that generated the Boolean value, but
3522 * do not store it. Since this instruction will be conditional,
3523 * other instructions that want to use the real Boolean value may
3524 * get garbage. This was a problem for piglit's fs-discard-exit-2
3527 * Ideally we'd detect that the instruction cannot have a
3528 * conditional modifier before emitting the instructions. Alas,
3529 * that is nigh impossible. Instead, we're going to assume the
3530 * instruction (or last instruction) generated can have a
3531 * conditional modifier. If it cannot, fallback to the old-style
3532 * compare, and hope dead code elimination will clean up the
3533 * extra instructions generated.
3535 nir_emit_alu(bld
, alu
, false);
3537 cmp
= (fs_inst
*) instructions
.get_tail();
3538 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3539 if (cmp
->can_do_cmod())
3540 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3544 /* The old sequence that would have been generated is,
3545 * basically, bool_result == false. This is equivalent to
3546 * !bool_result, so negate the old modifier.
3548 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3553 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3554 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3557 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3558 BRW_REGISTER_TYPE_UW
));
3559 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3562 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3563 cmp
->flag_subreg
= 1;
3565 if (devinfo
->gen
>= 6) {
3566 emit_discard_jump();
3569 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3573 case nir_intrinsic_load_input
: {
3574 /* load_input is only used for flat inputs */
3575 unsigned base
= nir_intrinsic_base(instr
);
3576 unsigned comp
= nir_intrinsic_component(instr
);
3577 unsigned num_components
= instr
->num_components
;
3578 fs_reg orig_dest
= dest
;
3579 enum brw_reg_type type
= dest
.type
;
3581 /* Special case fields in the VUE header */
3582 if (base
== VARYING_SLOT_LAYER
)
3584 else if (base
== VARYING_SLOT_VIEWPORT
)
3587 if (nir_dest_bit_size(instr
->dest
) == 64) {
3588 /* const_index is in 32-bit type size units that could not be aligned
3589 * with DF. We need to read the double vector as if it was a float
3590 * vector of twice the number of components to fetch the right data.
3592 type
= BRW_REGISTER_TYPE_F
;
3593 num_components
*= 2;
3594 dest
= bld
.vgrf(type
, num_components
);
3597 for (unsigned int i
= 0; i
< num_components
; i
++) {
3598 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3599 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3602 if (nir_dest_bit_size(instr
->dest
) == 64) {
3603 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3604 instr
->num_components
);
3609 case nir_intrinsic_load_barycentric_pixel
:
3610 case nir_intrinsic_load_barycentric_centroid
:
3611 case nir_intrinsic_load_barycentric_sample
:
3612 /* Do nothing - load_interpolated_input handling will handle it later. */
3615 case nir_intrinsic_load_barycentric_at_sample
: {
3616 const glsl_interp_mode interpolation
=
3617 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3619 if (nir_src_is_const(instr
->src
[0])) {
3620 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3622 emit_pixel_interpolater_send(bld
,
3623 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3626 brw_imm_ud(msg_data
),
3629 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3630 BRW_REGISTER_TYPE_UD
);
3632 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3633 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3634 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3635 bld
.exec_all().group(1, 0)
3636 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3637 emit_pixel_interpolater_send(bld
,
3638 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3644 /* Make a loop that sends a message to the pixel interpolater
3645 * for the sample number in each live channel. If there are
3646 * multiple channels with the same sample number then these
3647 * will be handled simultaneously with a single interation of
3650 bld
.emit(BRW_OPCODE_DO
);
3652 /* Get the next live sample number into sample_id_reg */
3653 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3655 /* Set the flag register so that we can perform the send
3656 * message on all channels that have the same sample number
3658 bld
.CMP(bld
.null_reg_ud(),
3659 sample_src
, sample_id
,
3660 BRW_CONDITIONAL_EQ
);
3661 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3662 bld
.exec_all().group(1, 0)
3663 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3665 emit_pixel_interpolater_send(bld
,
3666 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3669 component(msg_data
, 0),
3671 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3673 /* Continue the loop if there are any live channels left */
3674 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3676 bld
.emit(BRW_OPCODE_WHILE
));
3682 case nir_intrinsic_load_barycentric_at_offset
: {
3683 const glsl_interp_mode interpolation
=
3684 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3686 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3689 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3690 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3691 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3693 emit_pixel_interpolater_send(bld
,
3694 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3697 brw_imm_ud(off_x
| (off_y
<< 4)),
3700 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3701 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3702 BRW_REGISTER_TYPE_F
);
3703 for (int i
= 0; i
< 2; i
++) {
3704 fs_reg temp
= vgrf(glsl_type::float_type
);
3705 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3706 fs_reg itemp
= vgrf(glsl_type::int_type
);
3708 bld
.MOV(itemp
, temp
);
3710 /* Clamp the upper end of the range to +7/16.
3711 * ARB_gpu_shader5 requires that we support a maximum offset
3712 * of +0.5, which isn't representable in a S0.4 value -- if
3713 * we didn't clamp it, we'd end up with -8/16, which is the
3714 * opposite of what the shader author wanted.
3716 * This is legal due to ARB_gpu_shader5's quantization
3719 * "Not all values of <offset> may be supported; x and y
3720 * offsets may be rounded to fixed-point values with the
3721 * number of fraction bits given by the
3722 * implementation-dependent constant
3723 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3725 set_condmod(BRW_CONDITIONAL_L
,
3726 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3729 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3730 emit_pixel_interpolater_send(bld
,
3740 case nir_intrinsic_load_interpolated_input
: {
3741 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3742 emit_fragcoord_interpolation(dest
);
3746 assert(instr
->src
[0].ssa
&&
3747 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3748 nir_intrinsic_instr
*bary_intrinsic
=
3749 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3750 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3751 enum glsl_interp_mode interp_mode
=
3752 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3755 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3756 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3757 /* Use the result of the PI message */
3758 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3760 /* Use the delta_xy values computed from the payload */
3761 enum brw_barycentric_mode bary
=
3762 brw_barycentric_mode(interp_mode
, bary_intrin
);
3764 dst_xy
= this->delta_xy
[bary
];
3767 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3769 interp_reg(nir_intrinsic_base(instr
),
3770 nir_intrinsic_component(instr
) + i
);
3771 interp
.type
= BRW_REGISTER_TYPE_F
;
3772 dest
.type
= BRW_REGISTER_TYPE_F
;
3774 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3775 fs_reg tmp
= vgrf(glsl_type::float_type
);
3776 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3777 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3779 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3786 nir_emit_intrinsic(bld
, instr
);
3792 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3794 if (nir_src_is_const(instr
->src
[src
])) {
3795 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3798 else if (add_val
== -1)
3806 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3807 nir_intrinsic_instr
*instr
)
3809 assert(stage
== MESA_SHADER_COMPUTE
);
3810 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3813 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3814 dest
= get_nir_dest(instr
->dest
);
3816 switch (instr
->intrinsic
) {
3817 case nir_intrinsic_barrier
:
3819 cs_prog_data
->uses_barrier
= true;
3822 case nir_intrinsic_load_subgroup_id
:
3823 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3826 case nir_intrinsic_load_local_invocation_id
:
3827 case nir_intrinsic_load_work_group_id
: {
3828 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3829 fs_reg val
= nir_system_values
[sv
];
3830 assert(val
.file
!= BAD_FILE
);
3831 dest
.type
= val
.type
;
3832 for (unsigned i
= 0; i
< 3; i
++)
3833 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3837 case nir_intrinsic_load_num_work_groups
: {
3838 const unsigned surface
=
3839 cs_prog_data
->binding_table
.work_groups_start
;
3841 cs_prog_data
->uses_num_work_groups
= true;
3843 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3844 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3845 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3846 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3848 /* Read the 3 GLuint components of gl_NumWorkGroups */
3849 for (unsigned i
= 0; i
< 3; i
++) {
3850 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3851 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3852 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3857 case nir_intrinsic_shared_atomic_add
:
3858 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3860 case nir_intrinsic_shared_atomic_imin
:
3861 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3863 case nir_intrinsic_shared_atomic_umin
:
3864 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3866 case nir_intrinsic_shared_atomic_imax
:
3867 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3869 case nir_intrinsic_shared_atomic_umax
:
3870 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3872 case nir_intrinsic_shared_atomic_and
:
3873 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3875 case nir_intrinsic_shared_atomic_or
:
3876 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3878 case nir_intrinsic_shared_atomic_xor
:
3879 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3881 case nir_intrinsic_shared_atomic_exchange
:
3882 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3884 case nir_intrinsic_shared_atomic_comp_swap
:
3885 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3887 case nir_intrinsic_shared_atomic_fmin
:
3888 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3890 case nir_intrinsic_shared_atomic_fmax
:
3891 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3893 case nir_intrinsic_shared_atomic_fcomp_swap
:
3894 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3897 case nir_intrinsic_load_shared
: {
3898 assert(devinfo
->gen
>= 7);
3899 assert(stage
== MESA_SHADER_COMPUTE
);
3901 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3902 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3903 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3904 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3905 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3907 /* Make dest unsigned because that's what the temporary will be */
3908 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3910 /* Read the vector */
3911 if (nir_intrinsic_align(instr
) >= 4) {
3912 assert(nir_dest_bit_size(instr
->dest
) == 32);
3913 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3915 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3916 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3917 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3919 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3920 assert(nir_dest_num_components(instr
->dest
) == 1);
3921 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3923 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3924 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3925 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3926 bld
.MOV(dest
, read_result
);
3931 case nir_intrinsic_store_shared
: {
3932 assert(devinfo
->gen
>= 7);
3933 assert(stage
== MESA_SHADER_COMPUTE
);
3935 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3936 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3937 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3938 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3939 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3941 fs_reg data
= get_nir_src(instr
->src
[0]);
3942 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3944 assert(nir_intrinsic_write_mask(instr
) ==
3945 (1u << instr
->num_components
) - 1);
3946 if (nir_intrinsic_align(instr
) >= 4) {
3947 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3948 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3949 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3950 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3951 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3952 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3954 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3955 assert(nir_src_num_components(instr
->src
[0]) == 1);
3956 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3958 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3959 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3961 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3962 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3968 nir_emit_intrinsic(bld
, instr
);
3974 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3975 nir_op op
, brw_reg_type type
)
3977 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3978 switch (type_sz(type
)) {
3980 assert(type
!= BRW_REGISTER_TYPE_HF
);
3981 return retype(brw_imm_uw(value
.u16
), type
);
3983 return retype(brw_imm_ud(value
.u32
), type
);
3985 if (type
== BRW_REGISTER_TYPE_DF
)
3986 return setup_imm_df(bld
, value
.f64
);
3988 return retype(brw_imm_u64(value
.u64
), type
);
3990 unreachable("Invalid type size");
3995 brw_op_for_nir_reduction_op(nir_op op
)
3998 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3999 case nir_op_fadd
: return BRW_OPCODE_ADD
;
4000 case nir_op_imul
: return BRW_OPCODE_MUL
;
4001 case nir_op_fmul
: return BRW_OPCODE_MUL
;
4002 case nir_op_imin
: return BRW_OPCODE_SEL
;
4003 case nir_op_umin
: return BRW_OPCODE_SEL
;
4004 case nir_op_fmin
: return BRW_OPCODE_SEL
;
4005 case nir_op_imax
: return BRW_OPCODE_SEL
;
4006 case nir_op_umax
: return BRW_OPCODE_SEL
;
4007 case nir_op_fmax
: return BRW_OPCODE_SEL
;
4008 case nir_op_iand
: return BRW_OPCODE_AND
;
4009 case nir_op_ior
: return BRW_OPCODE_OR
;
4010 case nir_op_ixor
: return BRW_OPCODE_XOR
;
4012 unreachable("Invalid reduction operation");
4016 static brw_conditional_mod
4017 brw_cond_mod_for_nir_reduction_op(nir_op op
)
4020 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
4021 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
4022 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
4023 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
4024 case nir_op_imin
: return BRW_CONDITIONAL_L
;
4025 case nir_op_umin
: return BRW_CONDITIONAL_L
;
4026 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
4027 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
4028 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
4029 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
4030 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
4031 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
4032 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
4034 unreachable("Invalid reduction operation");
4039 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
4040 nir_intrinsic_instr
*instr
)
4042 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
4044 if (stage_prog_data
->binding_table
.image_start
> 0) {
4045 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
4046 image
.d
+= stage_prog_data
->binding_table
.image_start
;
4048 bld
.ADD(image
, image
,
4049 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
4053 return bld
.emit_uniformize(image
);
4057 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
4058 nir_intrinsic_instr
*instr
)
4060 /* SSBO stores are weird in that their index is in src[1] */
4061 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
4064 if (nir_src_is_const(instr
->src
[src
])) {
4065 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4066 nir_src_as_uint(instr
->src
[src
]);
4067 surf_index
= brw_imm_ud(index
);
4069 surf_index
= vgrf(glsl_type::uint_type
);
4070 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
4071 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4074 return bld
.emit_uniformize(surf_index
);
4078 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
4080 switch (nir_intrinsic_image_dim(instr
)) {
4081 case GLSL_SAMPLER_DIM_1D
:
4082 return 1 + nir_intrinsic_image_array(instr
);
4083 case GLSL_SAMPLER_DIM_2D
:
4084 case GLSL_SAMPLER_DIM_RECT
:
4085 return 2 + nir_intrinsic_image_array(instr
);
4086 case GLSL_SAMPLER_DIM_3D
:
4087 case GLSL_SAMPLER_DIM_CUBE
:
4089 case GLSL_SAMPLER_DIM_BUF
:
4091 case GLSL_SAMPLER_DIM_MS
:
4092 return 2 + nir_intrinsic_image_array(instr
);
4094 unreachable("Invalid image dimension");
4099 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4102 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4103 dest
= get_nir_dest(instr
->dest
);
4105 switch (instr
->intrinsic
) {
4106 case nir_intrinsic_image_load
:
4107 case nir_intrinsic_image_store
:
4108 case nir_intrinsic_image_atomic_add
:
4109 case nir_intrinsic_image_atomic_min
:
4110 case nir_intrinsic_image_atomic_max
:
4111 case nir_intrinsic_image_atomic_and
:
4112 case nir_intrinsic_image_atomic_or
:
4113 case nir_intrinsic_image_atomic_xor
:
4114 case nir_intrinsic_image_atomic_exchange
:
4115 case nir_intrinsic_image_atomic_comp_swap
:
4116 case nir_intrinsic_bindless_image_load
:
4117 case nir_intrinsic_bindless_image_store
:
4118 case nir_intrinsic_bindless_image_atomic_add
:
4119 case nir_intrinsic_bindless_image_atomic_min
:
4120 case nir_intrinsic_bindless_image_atomic_max
:
4121 case nir_intrinsic_bindless_image_atomic_and
:
4122 case nir_intrinsic_bindless_image_atomic_or
:
4123 case nir_intrinsic_bindless_image_atomic_xor
:
4124 case nir_intrinsic_bindless_image_atomic_exchange
:
4125 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4126 if (stage
== MESA_SHADER_FRAGMENT
&&
4127 instr
->intrinsic
!= nir_intrinsic_image_load
)
4128 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4130 /* Get some metadata from the image intrinsic. */
4131 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4132 const GLenum format
= nir_intrinsic_format(instr
);
4134 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4136 switch (instr
->intrinsic
) {
4137 case nir_intrinsic_image_load
:
4138 case nir_intrinsic_image_store
:
4139 case nir_intrinsic_image_atomic_add
:
4140 case nir_intrinsic_image_atomic_min
:
4141 case nir_intrinsic_image_atomic_max
:
4142 case nir_intrinsic_image_atomic_and
:
4143 case nir_intrinsic_image_atomic_or
:
4144 case nir_intrinsic_image_atomic_xor
:
4145 case nir_intrinsic_image_atomic_exchange
:
4146 case nir_intrinsic_image_atomic_comp_swap
:
4147 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4148 get_nir_image_intrinsic_image(bld
, instr
);
4153 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4154 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4158 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4159 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4160 brw_imm_ud(image_intrinsic_coord_components(instr
));
4162 /* Emit an image load, store or atomic op. */
4163 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4164 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4165 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4167 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4168 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4169 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4170 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4171 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4172 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4173 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4174 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4175 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4178 unsigned num_srcs
= info
->num_srcs
;
4180 switch (instr
->intrinsic
) {
4181 case nir_intrinsic_image_atomic_add
:
4182 case nir_intrinsic_bindless_image_atomic_add
:
4183 assert(num_srcs
== 4);
4185 op
= get_op_for_atomic_add(instr
, 3);
4187 if (op
!= BRW_AOP_ADD
)
4190 case nir_intrinsic_image_atomic_min
:
4191 case nir_intrinsic_bindless_image_atomic_min
:
4192 assert(format
== GL_R32UI
|| format
== GL_R32I
);
4193 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
4195 case nir_intrinsic_image_atomic_max
:
4196 case nir_intrinsic_bindless_image_atomic_max
:
4197 assert(format
== GL_R32UI
|| format
== GL_R32I
);
4198 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
4200 case nir_intrinsic_image_atomic_and
:
4201 case nir_intrinsic_bindless_image_atomic_and
:
4204 case nir_intrinsic_image_atomic_or
:
4205 case nir_intrinsic_bindless_image_atomic_or
:
4208 case nir_intrinsic_image_atomic_xor
:
4209 case nir_intrinsic_bindless_image_atomic_xor
:
4212 case nir_intrinsic_image_atomic_exchange
:
4213 case nir_intrinsic_bindless_image_atomic_exchange
:
4216 case nir_intrinsic_image_atomic_comp_swap
:
4217 case nir_intrinsic_bindless_image_atomic_comp_swap
:
4221 unreachable("Not reachable.");
4224 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4228 data
= get_nir_src(instr
->src
[3]);
4229 if (num_srcs
>= 5) {
4230 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4231 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4232 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4235 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4237 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4238 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4243 case nir_intrinsic_image_size
:
4244 case nir_intrinsic_bindless_image_size
: {
4245 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4246 * into will handle the binding table index for us in the geneerator.
4247 * Incidentally, this means that we can handle bindless with exactly the
4250 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4251 BRW_REGISTER_TYPE_UD
);
4252 image
= bld
.emit_uniformize(image
);
4254 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4255 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4256 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4258 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4259 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4260 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4261 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4263 /* Since the image size is always uniform, we can just emit a SIMD8
4264 * query instruction and splat the result out.
4266 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4268 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4269 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4270 tmp
, srcs
, ARRAY_SIZE(srcs
));
4271 inst
->size_written
= 4 * REG_SIZE
;
4273 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4274 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4275 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4276 offset(retype(dest
, tmp
.type
), bld
, c
),
4277 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4279 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4280 component(offset(tmp
, ubld
, c
), 0));
4286 case nir_intrinsic_image_load_raw_intel
: {
4287 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4288 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4289 get_nir_image_intrinsic_image(bld
, instr
);
4290 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4291 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4292 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4295 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4296 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4297 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4301 case nir_intrinsic_image_store_raw_intel
: {
4302 if (stage
== MESA_SHADER_FRAGMENT
)
4303 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4305 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4306 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4307 get_nir_image_intrinsic_image(bld
, instr
);
4308 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4309 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4310 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4311 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4313 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4314 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4318 case nir_intrinsic_group_memory_barrier
:
4319 case nir_intrinsic_memory_barrier_shared
:
4320 case nir_intrinsic_memory_barrier_atomic_counter
:
4321 case nir_intrinsic_memory_barrier_buffer
:
4322 case nir_intrinsic_memory_barrier_image
:
4323 case nir_intrinsic_memory_barrier
: {
4324 const fs_builder ubld
= bld
.group(8, 0);
4325 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4326 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4327 brw_vec8_grf(0, 0), brw_imm_ud(0))
4328 ->size_written
= 2 * REG_SIZE
;
4332 case nir_intrinsic_shader_clock
: {
4333 /* We cannot do anything if there is an event, so ignore it for now */
4334 const fs_reg shader_clock
= get_timestamp(bld
);
4335 const fs_reg srcs
[] = { component(shader_clock
, 0),
4336 component(shader_clock
, 1) };
4337 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4341 case nir_intrinsic_image_samples
:
4342 /* The driver does not support multi-sampled images. */
4343 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4346 case nir_intrinsic_load_uniform
: {
4347 /* Offsets are in bytes but they should always aligned to
4350 assert(instr
->const_index
[0] % 4 == 0 ||
4351 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4353 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4355 if (nir_src_is_const(instr
->src
[0])) {
4356 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4357 assert(load_offset
% type_sz(dest
.type
) == 0);
4358 /* For 16-bit types we add the module of the const_index[0]
4359 * offset to access to not 32-bit aligned element
4361 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4363 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4364 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4367 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4368 BRW_REGISTER_TYPE_UD
);
4370 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4371 * go past the end of the uniform. In order to keep the n'th
4372 * component from running past, we subtract off the size of all but
4373 * one component of the vector.
4375 assert(instr
->const_index
[1] >=
4376 instr
->num_components
* (int) type_sz(dest
.type
));
4377 unsigned read_size
= instr
->const_index
[1] -
4378 (instr
->num_components
- 1) * type_sz(dest
.type
);
4380 bool supports_64bit_indirects
=
4381 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4383 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4384 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4385 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4386 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4387 indirect
, brw_imm_ud(read_size
));
4390 const unsigned num_mov_indirects
=
4391 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4392 /* We read a little bit less per MOV INDIRECT, as they are now
4393 * 32-bits ones instead of 64-bit. Fix read_size then.
4395 const unsigned read_size_32bit
= read_size
-
4396 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4397 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4398 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4399 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4400 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4401 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4402 indirect
, brw_imm_ud(read_size_32bit
));
4410 case nir_intrinsic_load_ubo
: {
4412 if (nir_src_is_const(instr
->src
[0])) {
4413 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4414 nir_src_as_uint(instr
->src
[0]);
4415 surf_index
= brw_imm_ud(index
);
4417 /* The block index is not a constant. Evaluate the index expression
4418 * per-channel and add the base UBO index; we have to select a value
4419 * from any live channel.
4421 surf_index
= vgrf(glsl_type::uint_type
);
4422 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4423 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4424 surf_index
= bld
.emit_uniformize(surf_index
);
4427 if (!nir_src_is_const(instr
->src
[1])) {
4428 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4429 BRW_REGISTER_TYPE_UD
);
4431 for (int i
= 0; i
< instr
->num_components
; i
++)
4432 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4433 base_offset
, i
* type_sz(dest
.type
));
4435 /* Even if we are loading doubles, a pull constant load will load
4436 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4437 * need to load a full dvec4 we will have to emit 2 loads. This is
4438 * similar to demote_pull_constants(), except that in that case we
4439 * see individual accesses to each component of the vector and then
4440 * we let CSE deal with duplicate loads. Here we see a vector access
4441 * and we have to split it if necessary.
4443 const unsigned type_size
= type_sz(dest
.type
);
4444 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4446 /* See if we've selected this as a push constant candidate */
4447 if (nir_src_is_const(instr
->src
[0])) {
4448 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4449 const unsigned offset_256b
= load_offset
/ 32;
4452 for (int i
= 0; i
< 4; i
++) {
4453 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4454 if (range
->block
== ubo_block
&&
4455 offset_256b
>= range
->start
&&
4456 offset_256b
< range
->start
+ range
->length
) {
4458 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4459 push_reg
.offset
= load_offset
- 32 * range
->start
;
4464 if (push_reg
.file
!= BAD_FILE
) {
4465 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4466 bld
.MOV(offset(dest
, bld
, i
),
4467 byte_offset(push_reg
, i
* type_size
));
4473 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4474 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4475 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4477 for (unsigned c
= 0; c
< instr
->num_components
;) {
4478 const unsigned base
= load_offset
+ c
* type_size
;
4479 /* Number of usable components in the next block-aligned load. */
4480 const unsigned count
= MIN2(instr
->num_components
- c
,
4481 (block_sz
- base
% block_sz
) / type_size
);
4483 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4484 packed_consts
, surf_index
,
4485 brw_imm_ud(base
& ~(block_sz
- 1)));
4487 const fs_reg consts
=
4488 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4491 for (unsigned d
= 0; d
< count
; d
++)
4492 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4500 case nir_intrinsic_load_global
: {
4501 assert(devinfo
->gen
>= 8);
4503 if (nir_intrinsic_align(instr
) >= 4) {
4504 assert(nir_dest_bit_size(instr
->dest
) == 32);
4505 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4507 get_nir_src(instr
->src
[0]), /* Address */
4508 fs_reg(), /* No source data */
4509 brw_imm_ud(instr
->num_components
));
4510 inst
->size_written
= instr
->num_components
*
4511 inst
->dst
.component_size(inst
->exec_size
);
4513 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4514 assert(bit_size
<= 32);
4515 assert(nir_dest_num_components(instr
->dest
) == 1);
4516 brw_reg_type data_type
=
4517 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4518 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4519 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4521 get_nir_src(instr
->src
[0]), /* Address */
4522 fs_reg(), /* No source data */
4523 brw_imm_ud(bit_size
));
4524 bld
.MOV(retype(dest
, data_type
), tmp
);
4529 case nir_intrinsic_store_global
:
4530 assert(devinfo
->gen
>= 8);
4532 if (stage
== MESA_SHADER_FRAGMENT
)
4533 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4535 if (nir_intrinsic_align(instr
) >= 4) {
4536 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4537 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4539 get_nir_src(instr
->src
[1]), /* Address */
4540 get_nir_src(instr
->src
[0]), /* Data */
4541 brw_imm_ud(instr
->num_components
));
4543 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4544 assert(bit_size
<= 32);
4545 assert(nir_src_num_components(instr
->src
[0]) == 1);
4546 brw_reg_type data_type
=
4547 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4548 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4549 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4550 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4552 get_nir_src(instr
->src
[1]), /* Address */
4554 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4558 case nir_intrinsic_global_atomic_add
:
4559 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4561 case nir_intrinsic_global_atomic_imin
:
4562 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4564 case nir_intrinsic_global_atomic_umin
:
4565 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4567 case nir_intrinsic_global_atomic_imax
:
4568 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4570 case nir_intrinsic_global_atomic_umax
:
4571 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4573 case nir_intrinsic_global_atomic_and
:
4574 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4576 case nir_intrinsic_global_atomic_or
:
4577 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4579 case nir_intrinsic_global_atomic_xor
:
4580 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4582 case nir_intrinsic_global_atomic_exchange
:
4583 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4585 case nir_intrinsic_global_atomic_comp_swap
:
4586 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4588 case nir_intrinsic_global_atomic_fmin
:
4589 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4591 case nir_intrinsic_global_atomic_fmax
:
4592 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4594 case nir_intrinsic_global_atomic_fcomp_swap
:
4595 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4598 case nir_intrinsic_load_ssbo
: {
4599 assert(devinfo
->gen
>= 7);
4601 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4602 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4603 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4604 get_nir_ssbo_intrinsic_index(bld
, instr
);
4605 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4606 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4608 /* Make dest unsigned because that's what the temporary will be */
4609 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4611 /* Read the vector */
4612 if (nir_intrinsic_align(instr
) >= 4) {
4613 assert(nir_dest_bit_size(instr
->dest
) == 32);
4614 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4616 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4617 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4618 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4620 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4621 assert(nir_dest_num_components(instr
->dest
) == 1);
4622 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4624 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4625 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4626 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4627 bld
.MOV(dest
, read_result
);
4632 case nir_intrinsic_store_ssbo
: {
4633 assert(devinfo
->gen
>= 7);
4635 if (stage
== MESA_SHADER_FRAGMENT
)
4636 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4638 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4639 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4640 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4641 get_nir_ssbo_intrinsic_index(bld
, instr
);
4642 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4643 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4645 fs_reg data
= get_nir_src(instr
->src
[0]);
4646 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4648 assert(nir_intrinsic_write_mask(instr
) ==
4649 (1u << instr
->num_components
) - 1);
4650 if (nir_intrinsic_align(instr
) >= 4) {
4651 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4652 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4653 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4654 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4655 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4656 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4658 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4659 assert(nir_src_num_components(instr
->src
[0]) == 1);
4660 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4662 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4663 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4665 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4666 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4671 case nir_intrinsic_store_output
: {
4672 fs_reg src
= get_nir_src(instr
->src
[0]);
4674 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4675 unsigned num_components
= instr
->num_components
;
4676 unsigned first_component
= nir_intrinsic_component(instr
);
4677 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4678 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4679 num_components
*= 2;
4682 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4683 4 * store_offset
), src
.type
);
4684 for (unsigned j
= 0; j
< num_components
; j
++) {
4685 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4686 offset(src
, bld
, j
));
4691 case nir_intrinsic_ssbo_atomic_add
:
4692 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4694 case nir_intrinsic_ssbo_atomic_imin
:
4695 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4697 case nir_intrinsic_ssbo_atomic_umin
:
4698 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4700 case nir_intrinsic_ssbo_atomic_imax
:
4701 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4703 case nir_intrinsic_ssbo_atomic_umax
:
4704 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4706 case nir_intrinsic_ssbo_atomic_and
:
4707 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4709 case nir_intrinsic_ssbo_atomic_or
:
4710 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4712 case nir_intrinsic_ssbo_atomic_xor
:
4713 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4715 case nir_intrinsic_ssbo_atomic_exchange
:
4716 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4718 case nir_intrinsic_ssbo_atomic_comp_swap
:
4719 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4721 case nir_intrinsic_ssbo_atomic_fmin
:
4722 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4724 case nir_intrinsic_ssbo_atomic_fmax
:
4725 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4727 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4728 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4731 case nir_intrinsic_get_buffer_size
: {
4732 assert(nir_src_num_components(instr
->src
[0]) == 1);
4733 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4734 nir_src_as_uint(instr
->src
[0]) : 0;
4736 /* A resinfo's sampler message is used to get the buffer size. The
4737 * SIMD8's writeback message consists of four registers and SIMD16's
4738 * writeback message consists of 8 destination registers (two per each
4739 * component). Because we are only interested on the first channel of
4740 * the first returned component, where resinfo returns the buffer size
4741 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4742 * the dispatch width.
4744 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4745 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4746 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4749 ubld
.MOV(src_payload
, brw_imm_d(0));
4751 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4752 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4753 src_payload
, brw_imm_ud(index
));
4754 inst
->header_size
= 0;
4756 inst
->size_written
= 4 * REG_SIZE
;
4758 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4760 * "Out-of-bounds checking is always performed at a DWord granularity. If
4761 * any part of the DWord is out-of-bounds then the whole DWord is
4762 * considered out-of-bounds."
4764 * This implies that types with size smaller than 4-bytes need to be
4765 * padded if they don't complete the last dword of the buffer. But as we
4766 * need to maintain the original size we need to reverse the padding
4767 * calculation to return the correct size to know the number of elements
4768 * of an unsized array. As we stored in the last two bits of the surface
4769 * size the needed padding for the buffer, we calculate here the
4770 * original buffer_size reversing the surface_size calculation:
4772 * surface_size = isl_align(buffer_size, 4) +
4773 * (isl_align(buffer_size) - buffer_size)
4775 * buffer_size = surface_size & ~3 - surface_size & 3
4778 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4779 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4780 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4782 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4783 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4784 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4786 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4790 case nir_intrinsic_load_subgroup_invocation
:
4791 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4792 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4795 case nir_intrinsic_load_subgroup_eq_mask
:
4796 case nir_intrinsic_load_subgroup_ge_mask
:
4797 case nir_intrinsic_load_subgroup_gt_mask
:
4798 case nir_intrinsic_load_subgroup_le_mask
:
4799 case nir_intrinsic_load_subgroup_lt_mask
:
4800 unreachable("not reached");
4802 case nir_intrinsic_vote_any
: {
4803 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4805 /* The any/all predicates do not consider channel enables. To prevent
4806 * dead channels from affecting the result, we initialize the flag with
4807 * with the identity value for the logical operation.
4809 if (dispatch_width
== 32) {
4810 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4811 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4814 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4816 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4818 /* For some reason, the any/all predicates don't work properly with
4819 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4820 * doesn't read the correct subset of the flag register and you end up
4821 * getting garbage in the second half. Work around this by using a pair
4822 * of 1-wide MOVs and scattering the result.
4824 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4825 ubld
.MOV(res1
, brw_imm_d(0));
4826 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4827 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4828 BRW_PREDICATE_ALIGN1_ANY32H
,
4829 ubld
.MOV(res1
, brw_imm_d(-1)));
4831 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4834 case nir_intrinsic_vote_all
: {
4835 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4837 /* The any/all predicates do not consider channel enables. To prevent
4838 * dead channels from affecting the result, we initialize the flag with
4839 * with the identity value for the logical operation.
4841 if (dispatch_width
== 32) {
4842 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4843 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4844 brw_imm_ud(0xffffffff));
4846 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4848 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4850 /* For some reason, the any/all predicates don't work properly with
4851 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4852 * doesn't read the correct subset of the flag register and you end up
4853 * getting garbage in the second half. Work around this by using a pair
4854 * of 1-wide MOVs and scattering the result.
4856 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4857 ubld
.MOV(res1
, brw_imm_d(0));
4858 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4859 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4860 BRW_PREDICATE_ALIGN1_ALL32H
,
4861 ubld
.MOV(res1
, brw_imm_d(-1)));
4863 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4866 case nir_intrinsic_vote_feq
:
4867 case nir_intrinsic_vote_ieq
: {
4868 fs_reg value
= get_nir_src(instr
->src
[0]);
4869 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4870 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4871 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4872 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4875 fs_reg uniformized
= bld
.emit_uniformize(value
);
4876 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4878 /* The any/all predicates do not consider channel enables. To prevent
4879 * dead channels from affecting the result, we initialize the flag with
4880 * with the identity value for the logical operation.
4882 if (dispatch_width
== 32) {
4883 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4884 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4885 brw_imm_ud(0xffffffff));
4887 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4889 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4891 /* For some reason, the any/all predicates don't work properly with
4892 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4893 * doesn't read the correct subset of the flag register and you end up
4894 * getting garbage in the second half. Work around this by using a pair
4895 * of 1-wide MOVs and scattering the result.
4897 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4898 ubld
.MOV(res1
, brw_imm_d(0));
4899 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4900 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4901 BRW_PREDICATE_ALIGN1_ALL32H
,
4902 ubld
.MOV(res1
, brw_imm_d(-1)));
4904 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4908 case nir_intrinsic_ballot
: {
4909 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4910 BRW_REGISTER_TYPE_UD
);
4911 struct brw_reg flag
= brw_flag_reg(0, 0);
4912 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4913 * as f0.0. This is a problem for fragment programs as we currently use
4914 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4915 * programs yet so this isn't a problem. When we do, something will
4918 if (dispatch_width
== 32)
4919 flag
.type
= BRW_REGISTER_TYPE_UD
;
4921 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4922 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4924 if (instr
->dest
.ssa
.bit_size
> 32) {
4925 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4927 dest
.type
= BRW_REGISTER_TYPE_UD
;
4929 bld
.MOV(dest
, flag
);
4933 case nir_intrinsic_read_invocation
: {
4934 const fs_reg value
= get_nir_src(instr
->src
[0]);
4935 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4936 fs_reg tmp
= bld
.vgrf(value
.type
);
4938 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4939 bld
.emit_uniformize(invocation
));
4941 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4945 case nir_intrinsic_read_first_invocation
: {
4946 const fs_reg value
= get_nir_src(instr
->src
[0]);
4947 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4951 case nir_intrinsic_shuffle
: {
4952 const fs_reg value
= get_nir_src(instr
->src
[0]);
4953 const fs_reg index
= get_nir_src(instr
->src
[1]);
4955 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4959 case nir_intrinsic_first_invocation
: {
4960 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4961 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4962 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4963 fs_reg(component(tmp
, 0)));
4967 case nir_intrinsic_quad_broadcast
: {
4968 const fs_reg value
= get_nir_src(instr
->src
[0]);
4969 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4971 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4972 value
, brw_imm_ud(index
), brw_imm_ud(4));
4976 case nir_intrinsic_quad_swap_horizontal
: {
4977 const fs_reg value
= get_nir_src(instr
->src
[0]);
4978 const fs_reg tmp
= bld
.vgrf(value
.type
);
4979 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4981 const fs_reg src_left
= horiz_stride(value
, 2);
4982 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4983 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4984 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4986 ubld
.MOV(tmp_left
, src_right
);
4987 ubld
.MOV(tmp_right
, src_left
);
4989 bld
.MOV(retype(dest
, value
.type
), tmp
);
4993 case nir_intrinsic_quad_swap_vertical
: {
4994 const fs_reg value
= get_nir_src(instr
->src
[0]);
4995 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4996 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4997 const fs_reg tmp
= bld
.vgrf(value
.type
);
4998 const fs_builder ubld
= bld
.exec_all();
4999 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5000 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
5001 bld
.MOV(retype(dest
, value
.type
), tmp
);
5003 /* For larger data types, we have to either emit dispatch_width many
5004 * MOVs or else fall back to doing indirects.
5006 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5007 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5009 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5014 case nir_intrinsic_quad_swap_diagonal
: {
5015 const fs_reg value
= get_nir_src(instr
->src
[0]);
5016 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5017 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5018 const fs_reg tmp
= bld
.vgrf(value
.type
);
5019 const fs_builder ubld
= bld
.exec_all();
5020 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5021 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
5022 bld
.MOV(retype(dest
, value
.type
), tmp
);
5024 /* For larger data types, we have to either emit dispatch_width many
5025 * MOVs or else fall back to doing indirects.
5027 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5028 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5030 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5035 case nir_intrinsic_reduce
: {
5036 fs_reg src
= get_nir_src(instr
->src
[0]);
5037 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5038 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
5039 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
5040 cluster_size
= dispatch_width
;
5042 /* Figure out the source type */
5043 src
.type
= brw_type_for_nir_type(devinfo
,
5044 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5045 nir_src_bit_size(instr
->src
[0])));
5047 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5048 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5049 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5051 /* Set up a register for all of our scratching around and initialize it
5052 * to reduction operation's identity value.
5054 fs_reg scan
= bld
.vgrf(src
.type
);
5055 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5057 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
5059 dest
.type
= src
.type
;
5060 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
5061 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
5062 * the distance between clusters is at least 2 GRFs. In this case,
5063 * we don't need the weird striding of the CLUSTER_BROADCAST
5064 * instruction and can just do regular MOVs.
5066 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5067 const unsigned groups
=
5068 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5069 const unsigned group_size
= dispatch_width
/ groups
;
5070 for (unsigned i
= 0; i
< groups
; i
++) {
5071 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5072 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5073 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5074 component(scan
, comp
));
5077 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5078 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5083 case nir_intrinsic_inclusive_scan
:
5084 case nir_intrinsic_exclusive_scan
: {
5085 fs_reg src
= get_nir_src(instr
->src
[0]);
5086 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5088 /* Figure out the source type */
5089 src
.type
= brw_type_for_nir_type(devinfo
,
5090 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5091 nir_src_bit_size(instr
->src
[0])));
5093 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5094 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5095 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5097 /* Set up a register for all of our scratching around and initialize it
5098 * to reduction operation's identity value.
5100 fs_reg scan
= bld
.vgrf(src
.type
);
5101 const fs_builder allbld
= bld
.exec_all();
5102 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5104 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5105 /* Exclusive scan is a bit harder because we have to do an annoying
5106 * shift of the contents before we can begin. To make things worse,
5107 * we can't do this with a normal stride; we have to use indirects.
5109 fs_reg shifted
= bld
.vgrf(src
.type
);
5110 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5111 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5113 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5114 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5118 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5120 bld
.MOV(retype(dest
, src
.type
), scan
);
5124 case nir_intrinsic_begin_invocation_interlock
: {
5125 const fs_builder ubld
= bld
.group(8, 0);
5126 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5128 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
5129 ->size_written
= 2 * REG_SIZE
;
5133 case nir_intrinsic_end_invocation_interlock
: {
5134 /* For endInvocationInterlock(), we need to insert a memory fence which
5135 * stalls in the shader until the memory transactions prior to that
5136 * fence are complete. This ensures that the shader does not end before
5137 * any writes from its critical section have landed. Otherwise, you can
5138 * end up with a case where the next invocation on that pixel properly
5139 * stalls for previous FS invocation on its pixel to complete but
5140 * doesn't actually wait for the dataport memory transactions from that
5141 * thread to land before submitting its own.
5143 const fs_builder ubld
= bld
.group(8, 0);
5144 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5145 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
5146 brw_vec8_grf(0, 0), brw_imm_ud(1))
5147 ->size_written
= 2 * REG_SIZE
;
5152 unreachable("unknown intrinsic");
5157 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5158 int op
, nir_intrinsic_instr
*instr
)
5160 if (stage
== MESA_SHADER_FRAGMENT
)
5161 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5163 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5164 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5165 * appear to exist. However, if you look at Vol 2a, there are no message
5166 * descriptors provided for Qword atomic ops except for A64 messages.
5168 assert(nir_dest_bit_size(instr
->dest
) == 32);
5171 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5172 dest
= get_nir_dest(instr
->dest
);
5174 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5175 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5176 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5177 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5178 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5181 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5182 data
= get_nir_src(instr
->src
[2]);
5184 if (op
== BRW_AOP_CMPWR
) {
5185 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5186 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5187 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5190 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5192 /* Emit the actual atomic operation */
5194 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5195 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5199 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5200 int op
, nir_intrinsic_instr
*instr
)
5202 if (stage
== MESA_SHADER_FRAGMENT
)
5203 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5206 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5207 dest
= get_nir_dest(instr
->dest
);
5209 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5210 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5211 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5212 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5213 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5215 fs_reg data
= get_nir_src(instr
->src
[2]);
5216 if (op
== BRW_AOP_FCMPWR
) {
5217 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5218 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5219 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5222 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5224 /* Emit the actual atomic operation */
5226 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5227 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5231 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5232 int op
, nir_intrinsic_instr
*instr
)
5235 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5236 dest
= get_nir_dest(instr
->dest
);
5238 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5239 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5240 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5241 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5244 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5245 data
= get_nir_src(instr
->src
[1]);
5246 if (op
== BRW_AOP_CMPWR
) {
5247 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5248 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5249 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5252 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5254 /* Get the offset */
5255 if (nir_src_is_const(instr
->src
[0])) {
5256 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5257 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5259 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5260 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5261 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5262 brw_imm_ud(instr
->const_index
[0]));
5265 /* Emit the actual atomic operation operation */
5267 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5268 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5272 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5273 int op
, nir_intrinsic_instr
*instr
)
5276 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5277 dest
= get_nir_dest(instr
->dest
);
5279 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5280 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5281 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5282 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5284 fs_reg data
= get_nir_src(instr
->src
[1]);
5285 if (op
== BRW_AOP_FCMPWR
) {
5286 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5287 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5288 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5291 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5293 /* Get the offset */
5294 if (nir_src_is_const(instr
->src
[0])) {
5295 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5296 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5298 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5299 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5300 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5301 brw_imm_ud(instr
->const_index
[0]));
5304 /* Emit the actual atomic operation operation */
5306 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5307 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5311 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5312 int op
, nir_intrinsic_instr
*instr
)
5314 if (stage
== MESA_SHADER_FRAGMENT
)
5315 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5318 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5319 dest
= get_nir_dest(instr
->dest
);
5321 fs_reg addr
= get_nir_src(instr
->src
[0]);
5324 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5325 data
= get_nir_src(instr
->src
[1]);
5327 if (op
== BRW_AOP_CMPWR
) {
5328 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5329 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5330 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5334 if (nir_dest_bit_size(instr
->dest
) == 64) {
5335 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5336 dest
, addr
, data
, brw_imm_ud(op
));
5338 assert(nir_dest_bit_size(instr
->dest
) == 32);
5339 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5340 dest
, addr
, data
, brw_imm_ud(op
));
5345 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5346 int op
, nir_intrinsic_instr
*instr
)
5348 if (stage
== MESA_SHADER_FRAGMENT
)
5349 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5351 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5352 fs_reg dest
= get_nir_dest(instr
->dest
);
5354 fs_reg addr
= get_nir_src(instr
->src
[0]);
5356 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5357 fs_reg data
= get_nir_src(instr
->src
[1]);
5359 if (op
== BRW_AOP_FCMPWR
) {
5360 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5361 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5362 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5366 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5367 dest
, addr
, data
, brw_imm_ud(op
));
5371 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5373 unsigned texture
= instr
->texture_index
;
5374 unsigned sampler
= instr
->sampler_index
;
5376 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5378 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5379 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5381 int lod_components
= 0;
5383 /* The hardware requires a LOD for buffer textures */
5384 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5385 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5387 uint32_t header_bits
= 0;
5388 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5389 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5390 switch (instr
->src
[i
].src_type
) {
5391 case nir_tex_src_bias
:
5392 srcs
[TEX_LOGICAL_SRC_LOD
] =
5393 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5395 case nir_tex_src_comparator
:
5396 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5398 case nir_tex_src_coord
:
5399 switch (instr
->op
) {
5401 case nir_texop_txf_ms
:
5402 case nir_texop_txf_ms_mcs
:
5403 case nir_texop_samples_identical
:
5404 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5407 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5411 case nir_tex_src_ddx
:
5412 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5413 lod_components
= nir_tex_instr_src_size(instr
, i
);
5415 case nir_tex_src_ddy
:
5416 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5418 case nir_tex_src_lod
:
5419 switch (instr
->op
) {
5421 srcs
[TEX_LOGICAL_SRC_LOD
] =
5422 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5425 srcs
[TEX_LOGICAL_SRC_LOD
] =
5426 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5429 srcs
[TEX_LOGICAL_SRC_LOD
] =
5430 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5434 case nir_tex_src_min_lod
:
5435 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5436 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5438 case nir_tex_src_ms_index
:
5439 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5442 case nir_tex_src_offset
: {
5443 uint32_t offset_bits
= 0;
5444 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5445 header_bits
|= offset_bits
;
5447 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5448 retype(src
, BRW_REGISTER_TYPE_D
);
5453 case nir_tex_src_projector
:
5454 unreachable("should be lowered");
5456 case nir_tex_src_texture_offset
: {
5457 /* Emit code to evaluate the actual indexing expression */
5458 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5459 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5460 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5464 case nir_tex_src_sampler_offset
: {
5465 /* Emit code to evaluate the actual indexing expression */
5466 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5467 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5468 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5472 case nir_tex_src_texture_handle
:
5473 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5474 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5475 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5478 case nir_tex_src_sampler_handle
:
5479 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5480 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5481 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5484 case nir_tex_src_ms_mcs
:
5485 assert(instr
->op
== nir_texop_txf_ms
);
5486 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5489 case nir_tex_src_plane
: {
5490 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5491 const uint32_t texture_index
=
5492 instr
->texture_index
+
5493 stage_prog_data
->binding_table
.plane_start
[plane
] -
5494 stage_prog_data
->binding_table
.texture_start
;
5496 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5501 unreachable("unknown texture source");
5505 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5506 (instr
->op
== nir_texop_txf_ms
||
5507 instr
->op
== nir_texop_samples_identical
)) {
5508 if (devinfo
->gen
>= 7 &&
5509 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5510 srcs
[TEX_LOGICAL_SRC_MCS
] =
5511 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5512 instr
->coord_components
,
5513 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5514 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5516 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5520 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5521 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5524 switch (instr
->op
) {
5526 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5529 opcode
= FS_OPCODE_TXB_LOGICAL
;
5532 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5535 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5538 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5540 case nir_texop_txf_ms
:
5541 if ((key_tex
->msaa_16
& (1 << sampler
)))
5542 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5544 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5546 case nir_texop_txf_ms_mcs
:
5547 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5549 case nir_texop_query_levels
:
5551 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5554 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5557 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5558 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5560 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5562 case nir_texop_texture_samples
:
5563 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5565 case nir_texop_samples_identical
: {
5566 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5568 /* If mcs is an immediate value, it means there is no MCS. In that case
5569 * just return false.
5571 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5572 bld
.MOV(dst
, brw_imm_ud(0u));
5573 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5574 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5575 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5576 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5577 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5579 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5580 BRW_CONDITIONAL_EQ
);
5585 unreachable("unknown texture opcode");
5588 if (instr
->op
== nir_texop_tg4
) {
5589 if (instr
->component
== 1 &&
5590 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5591 /* gather4 sampler is broken for green channel on RG32F --
5592 * we must ask for blue instead.
5594 header_bits
|= 2 << 16;
5596 header_bits
|= instr
->component
<< 16;
5600 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5601 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5602 inst
->offset
= header_bits
;
5604 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5605 if (devinfo
->gen
>= 9 &&
5606 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5607 unsigned write_mask
= instr
->dest
.is_ssa
?
5608 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5609 (1 << dest_size
) - 1;
5610 assert(write_mask
!= 0); /* dead code should have been eliminated */
5611 inst
->size_written
= util_last_bit(write_mask
) *
5612 inst
->dst
.component_size(inst
->exec_size
);
5614 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5617 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5618 inst
->shadow_compare
= true;
5620 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5621 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5624 for (unsigned i
= 0; i
< dest_size
; i
++)
5625 nir_dest
[i
] = offset(dst
, bld
, i
);
5627 if (instr
->op
== nir_texop_query_levels
) {
5628 /* # levels is in .w */
5629 nir_dest
[0] = offset(dst
, bld
, 3);
5630 } else if (instr
->op
== nir_texop_txs
&&
5631 dest_size
>= 3 && devinfo
->gen
< 7) {
5632 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5633 fs_reg depth
= offset(dst
, bld
, 2);
5634 nir_dest
[2] = vgrf(glsl_type::int_type
);
5635 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5638 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5642 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5644 switch (instr
->type
) {
5645 case nir_jump_break
:
5646 bld
.emit(BRW_OPCODE_BREAK
);
5648 case nir_jump_continue
:
5649 bld
.emit(BRW_OPCODE_CONTINUE
);
5651 case nir_jump_return
:
5653 unreachable("unknown jump");
5658 * This helper takes a source register and un/shuffles it into the destination
5661 * If source type size is smaller than destination type size the operation
5662 * needed is a component shuffle. The opposite case would be an unshuffle. If
5663 * source/destination type size is equal a shuffle is done that would be
5664 * equivalent to a simple MOV.
5666 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5667 * components .xyz 16-bit vector on SIMD8 would be.
5669 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5670 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5672 * This helper will return the following 2 32-bit components with the 16-bit
5675 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5676 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5678 * For unshuffle, the example would be the opposite, a 64-bit type source
5679 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5682 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5683 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5684 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5685 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5687 * The returned result would be the following 4 32-bit components unshuffled:
5689 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5690 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5691 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5692 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5694 * - Source and destination register must not be overlapped.
5695 * - components units are measured in terms of the smaller type between
5696 * source and destination because we are un/shuffling the smaller
5697 * components from/into the bigger ones.
5698 * - first_component parameter allows skipping source components.
5701 shuffle_src_to_dst(const fs_builder
&bld
,
5704 uint32_t first_component
,
5705 uint32_t components
)
5707 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5708 assert(!regions_overlap(dst
,
5709 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5710 offset(src
, bld
, first_component
),
5711 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5712 for (unsigned i
= 0; i
< components
; i
++) {
5713 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5714 offset(src
, bld
, i
+ first_component
));
5716 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5717 /* Source is shuffled into destination */
5718 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5719 assert(!regions_overlap(dst
,
5720 type_sz(dst
.type
) * bld
.dispatch_width() *
5721 DIV_ROUND_UP(components
, size_ratio
),
5722 offset(src
, bld
, first_component
),
5723 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5725 brw_reg_type shuffle_type
=
5726 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5727 BRW_REGISTER_TYPE_D
);
5728 for (unsigned i
= 0; i
< components
; i
++) {
5729 fs_reg shuffle_component_i
=
5730 subscript(offset(dst
, bld
, i
/ size_ratio
),
5731 shuffle_type
, i
% size_ratio
);
5732 bld
.MOV(shuffle_component_i
,
5733 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5736 /* Source is unshuffled into destination */
5737 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5738 assert(!regions_overlap(dst
,
5739 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5740 offset(src
, bld
, first_component
/ size_ratio
),
5741 type_sz(src
.type
) * bld
.dispatch_width() *
5742 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5745 brw_reg_type shuffle_type
=
5746 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5747 BRW_REGISTER_TYPE_D
);
5748 for (unsigned i
= 0; i
< components
; i
++) {
5749 fs_reg shuffle_component_i
=
5750 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5751 shuffle_type
, (first_component
+ i
) % size_ratio
);
5752 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5753 shuffle_component_i
);
5759 shuffle_from_32bit_read(const fs_builder
&bld
,
5762 uint32_t first_component
,
5763 uint32_t components
)
5765 assert(type_sz(src
.type
) == 4);
5767 /* This function takes components in units of the destination type while
5768 * shuffle_src_to_dst takes components in units of the smallest type
5770 if (type_sz(dst
.type
) > 4) {
5771 assert(type_sz(dst
.type
) == 8);
5772 first_component
*= 2;
5776 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5780 shuffle_for_32bit_write(const fs_builder
&bld
,
5782 uint32_t first_component
,
5783 uint32_t components
)
5785 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5786 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5787 /* This function takes components in units of the source type while
5788 * shuffle_src_to_dst takes components in units of the smallest type
5790 if (type_sz(src
.type
) > 4) {
5791 assert(type_sz(src
.type
) == 8);
5792 first_component
*= 2;
5796 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5802 setup_imm_df(const fs_builder
&bld
, double v
)
5804 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5805 assert(devinfo
->gen
>= 7);
5807 if (devinfo
->gen
>= 8)
5808 return brw_imm_df(v
);
5810 /* gen7.5 does not support DF immediates straighforward but the DIM
5811 * instruction allows to set the 64-bit immediate value.
5813 if (devinfo
->is_haswell
) {
5814 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5815 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5816 ubld
.DIM(dst
, brw_imm_df(v
));
5817 return component(dst
, 0);
5820 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5821 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5822 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5824 * Alternatively, we could also produce a normal VGRF (without stride 0)
5825 * by writing to all the channels in the VGRF, however, that would hit the
5826 * gen7 bug where we have to split writes that span more than 1 register
5827 * into instructions with a width of 4 (otherwise the write to the second
5828 * register written runs into an execmask hardware bug) which isn't very
5841 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5842 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5843 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5844 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5846 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5850 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5852 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5853 bld
.MOV(tmp
, brw_imm_w(v
));
5858 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5860 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5861 bld
.MOV(tmp
, brw_imm_uw(v
));