2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "util/u_math.h"
29 #include "util/bitscan.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
48 fs_visitor::nir_setup_outputs()
50 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
53 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
55 /* Calculate the size of output registers in a separate pass, before
56 * allocating them. With ARB_enhanced_layouts, multiple output variables
57 * may occupy the same slot, but have different type sizes.
59 nir_foreach_variable(var
, &nir
->outputs
) {
60 const int loc
= var
->data
.driver_location
;
61 const unsigned var_vec4s
=
62 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
63 : type_size_vec4(var
->type
);
64 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
67 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
68 if (vec4s
[loc
] == 0) {
73 unsigned reg_size
= vec4s
[loc
];
75 /* Check if there are any ranges that start within this range and extend
76 * past it. If so, include them in this allocation.
78 for (unsigned i
= 1; i
< reg_size
; i
++)
79 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
81 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
82 for (unsigned i
= 0; i
< reg_size
; i
++)
83 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
90 fs_visitor::nir_setup_uniforms()
92 /* Only the first compile gets to set up uniforms. */
93 if (push_constant_loc
) {
94 assert(pull_constant_loc
);
98 uniforms
= nir
->num_uniforms
/ 4;
100 if (stage
== MESA_SHADER_COMPUTE
) {
101 /* Add a uniform for the thread local id. It must be the last uniform
104 assert(uniforms
== prog_data
->nr_params
);
105 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
106 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
107 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
112 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
116 nir_foreach_instr(instr
, block
) {
117 if (instr
->type
!= nir_instr_type_intrinsic
)
120 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
121 switch (intrin
->intrinsic
) {
122 case nir_intrinsic_load_vertex_id
:
123 case nir_intrinsic_load_base_vertex
:
124 unreachable("should be lowered by nir_lower_system_values().");
126 case nir_intrinsic_load_vertex_id_zero_base
:
127 case nir_intrinsic_load_is_indexed_draw
:
128 case nir_intrinsic_load_first_vertex
:
129 case nir_intrinsic_load_instance_id
:
130 case nir_intrinsic_load_base_instance
:
131 case nir_intrinsic_load_draw_id
:
132 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
134 case nir_intrinsic_load_invocation_id
:
135 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
137 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
138 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
139 if (reg
->file
== BAD_FILE
) {
140 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
141 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
142 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
143 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
148 case nir_intrinsic_load_sample_pos
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_samplepos_setup();
155 case nir_intrinsic_load_sample_id
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_sampleid_setup();
162 case nir_intrinsic_load_sample_mask_in
:
163 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
164 assert(v
->devinfo
->gen
>= 7);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplemaskin_setup();
170 case nir_intrinsic_load_work_group_id
:
171 assert(v
->stage
== MESA_SHADER_COMPUTE
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_cs_work_group_id_setup();
177 case nir_intrinsic_load_helper_invocation
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
180 if (reg
->file
== BAD_FILE
) {
181 const fs_builder abld
=
182 v
->bld
.annotate("gl_HelperInvocation", NULL
);
184 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
185 * pixel mask is in g1.7 of the thread payload.
187 * We move the per-channel pixel enable bit to the low bit of each
188 * channel by shifting the byte containing the pixel mask by the
189 * vector immediate 0x76543210UV.
191 * The region of <1,8,0> reads only 1 byte (the pixel masks for
192 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
193 * masks for 2 and 3) in SIMD16.
195 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
197 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
198 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
199 hbld
.SHR(offset(shifted
, hbld
, i
),
200 stride(retype(brw_vec1_grf(1 + i
, 7),
201 BRW_REGISTER_TYPE_UB
),
203 brw_imm_v(0x76543210));
206 /* A set bit in the pixel mask means the channel is enabled, but
207 * that is the opposite of gl_HelperInvocation so we need to invert
210 * The negate source-modifier bit of logical instructions on Gen8+
211 * performs 1's complement negation, so we can use that instead of
214 fs_reg inverted
= negate(shifted
);
215 if (v
->devinfo
->gen
< 8) {
216 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
217 abld
.NOT(inverted
, shifted
);
220 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
221 * with 1 and negating.
223 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
224 abld
.AND(anded
, inverted
, brw_imm_uw(1));
226 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
227 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
241 fs_visitor::nir_emit_system_values()
243 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
244 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
245 nir_system_values
[i
] = fs_reg();
248 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
249 * never end up using it.
252 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
253 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
254 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
256 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
257 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
258 if (dispatch_width
> 8)
259 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
260 if (dispatch_width
> 16) {
261 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
262 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
266 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
267 nir_foreach_block(block
, impl
)
268 emit_system_values_block(block
, this);
272 * Returns a type based on a reference_type (word, float, half-float) and a
275 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
277 * @FIXME: 64-bit return types are always DF on integer types to maintain
278 * compability with uses of DF previously to the introduction of int64
282 brw_reg_type_from_bit_size(const unsigned bit_size
,
283 const brw_reg_type reference_type
)
285 switch(reference_type
) {
286 case BRW_REGISTER_TYPE_HF
:
287 case BRW_REGISTER_TYPE_F
:
288 case BRW_REGISTER_TYPE_DF
:
291 return BRW_REGISTER_TYPE_HF
;
293 return BRW_REGISTER_TYPE_F
;
295 return BRW_REGISTER_TYPE_DF
;
297 unreachable("Invalid bit size");
299 case BRW_REGISTER_TYPE_B
:
300 case BRW_REGISTER_TYPE_W
:
301 case BRW_REGISTER_TYPE_D
:
302 case BRW_REGISTER_TYPE_Q
:
305 return BRW_REGISTER_TYPE_B
;
307 return BRW_REGISTER_TYPE_W
;
309 return BRW_REGISTER_TYPE_D
;
311 return BRW_REGISTER_TYPE_Q
;
313 unreachable("Invalid bit size");
315 case BRW_REGISTER_TYPE_UB
:
316 case BRW_REGISTER_TYPE_UW
:
317 case BRW_REGISTER_TYPE_UD
:
318 case BRW_REGISTER_TYPE_UQ
:
321 return BRW_REGISTER_TYPE_UB
;
323 return BRW_REGISTER_TYPE_UW
;
325 return BRW_REGISTER_TYPE_UD
;
327 return BRW_REGISTER_TYPE_UQ
;
329 unreachable("Invalid bit size");
332 unreachable("Unknown type");
337 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
339 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
340 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
341 nir_locals
[i
] = fs_reg();
344 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
345 unsigned array_elems
=
346 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
347 unsigned size
= array_elems
* reg
->num_components
;
348 const brw_reg_type reg_type
=
349 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
350 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
353 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
356 nir_emit_cf_list(&impl
->body
);
360 fs_visitor::nir_emit_cf_list(exec_list
*list
)
362 exec_list_validate(list
);
363 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
364 switch (node
->type
) {
366 nir_emit_if(nir_cf_node_as_if(node
));
369 case nir_cf_node_loop
:
370 nir_emit_loop(nir_cf_node_as_loop(node
));
373 case nir_cf_node_block
:
374 nir_emit_block(nir_cf_node_as_block(node
));
378 unreachable("Invalid CFG node block");
384 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
386 /* first, put the condition into f0 */
387 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
388 retype(get_nir_src(if_stmt
->condition
),
389 BRW_REGISTER_TYPE_D
));
390 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
392 bld
.IF(BRW_PREDICATE_NORMAL
);
394 nir_emit_cf_list(&if_stmt
->then_list
);
396 /* note: if the else is empty, dead CF elimination will remove it */
397 bld
.emit(BRW_OPCODE_ELSE
);
399 nir_emit_cf_list(&if_stmt
->else_list
);
401 bld
.emit(BRW_OPCODE_ENDIF
);
403 if (devinfo
->gen
< 7)
404 limit_dispatch_width(16, "Non-uniform control flow unsupported "
409 fs_visitor::nir_emit_loop(nir_loop
*loop
)
411 bld
.emit(BRW_OPCODE_DO
);
413 nir_emit_cf_list(&loop
->body
);
415 bld
.emit(BRW_OPCODE_WHILE
);
417 if (devinfo
->gen
< 7)
418 limit_dispatch_width(16, "Non-uniform control flow unsupported "
423 fs_visitor::nir_emit_block(nir_block
*block
)
425 nir_foreach_instr(instr
, block
) {
426 nir_emit_instr(instr
);
431 fs_visitor::nir_emit_instr(nir_instr
*instr
)
433 const fs_builder abld
= bld
.annotate(NULL
, instr
);
435 switch (instr
->type
) {
436 case nir_instr_type_alu
:
437 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
440 case nir_instr_type_deref
:
441 /* Derefs can exist for images but they do nothing */
444 case nir_instr_type_intrinsic
:
446 case MESA_SHADER_VERTEX
:
447 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
449 case MESA_SHADER_TESS_CTRL
:
450 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
452 case MESA_SHADER_TESS_EVAL
:
453 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
455 case MESA_SHADER_GEOMETRY
:
456 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
458 case MESA_SHADER_FRAGMENT
:
459 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
461 case MESA_SHADER_COMPUTE
:
462 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 unreachable("unsupported shader stage");
469 case nir_instr_type_tex
:
470 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
473 case nir_instr_type_load_const
:
474 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
477 case nir_instr_type_ssa_undef
:
478 /* We create a new VGRF for undefs on every use (by handling
479 * them in get_nir_src()), rather than for each definition.
480 * This helps register coalescing eliminate MOVs from undef.
484 case nir_instr_type_jump
:
485 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
489 unreachable("unknown instruction type");
494 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
498 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
499 const fs_reg
&result
)
501 if (!instr
->src
[0].src
.is_ssa
||
502 !instr
->src
[0].src
.ssa
->parent_instr
)
505 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
508 nir_alu_instr
*src0
=
509 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
511 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
512 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
515 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
517 /* Element type to extract.*/
518 const brw_reg_type type
= brw_int_type(
519 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
520 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
522 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
523 op0
.type
= brw_type_for_nir_type(devinfo
,
524 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
525 nir_src_bit_size(src0
->src
[0].src
)));
526 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
528 set_saturate(instr
->dest
.saturate
,
529 bld
.MOV(result
, subscript(op0
, type
, element
)));
534 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
535 const fs_reg
&result
)
537 if (!instr
->src
[0].src
.is_ssa
||
538 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
541 nir_intrinsic_instr
*src0
=
542 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
544 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
547 if (!nir_src_is_const(instr
->src
[1].src
) ||
548 !nir_src_is_const(instr
->src
[2].src
))
551 const float value1
= nir_src_as_float(instr
->src
[1].src
);
552 const float value2
= nir_src_as_float(instr
->src
[2].src
);
553 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
556 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
557 assert(value1
== -value2
);
559 fs_reg tmp
= vgrf(glsl_type::int_type
);
561 if (devinfo
->gen
>= 6) {
562 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
563 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
565 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
567 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
568 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
570 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
572 * This negation looks like it's safe in practice, because bits 0:4 will
573 * surely be TRIANGLES
576 if (value1
== -1.0f
) {
580 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
581 g0
, brw_imm_uw(0x3f80));
583 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
584 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
586 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
588 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
589 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
591 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
593 * This negation looks like it's safe in practice, because bits 0:4 will
594 * surely be TRIANGLES
597 if (value1
== -1.0f
) {
601 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
603 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
609 emit_find_msb_using_lzd(const fs_builder
&bld
,
610 const fs_reg
&result
,
618 /* LZD of an absolute value source almost always does the right
619 * thing. There are two problem values:
621 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
622 * 0. However, findMSB(int(0x80000000)) == 30.
624 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
625 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
627 * For a value of zero or negative one, -1 will be returned.
629 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
630 * findMSB(-(1<<x)) should return x-1.
632 * For all negative number cases, including 0x80000000 and
633 * 0xffffffff, the correct value is obtained from LZD if instead of
634 * negating the (already negative) value the logical-not is used. A
635 * conditonal logical-not can be achieved in two instructions.
637 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
639 bld
.ASR(temp
, src
, brw_imm_d(31));
640 bld
.XOR(temp
, temp
, src
);
643 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
644 retype(temp
, BRW_REGISTER_TYPE_UD
));
646 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
647 * from the LSB side. Subtract the result from 31 to convert the MSB
648 * count into an LSB count. If no bits are set, LZD will return 32.
649 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
651 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
652 inst
->src
[0].negate
= true;
656 brw_rnd_mode_from_nir_op (const nir_op op
) {
658 case nir_op_f2f16_rtz
:
659 return BRW_RND_MODE_RTZ
;
660 case nir_op_f2f16_rtne
:
661 return BRW_RND_MODE_RTNE
;
663 unreachable("Operation doesn't support rounding mode");
668 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
670 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
673 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
674 result
.type
= brw_type_for_nir_type(devinfo
,
675 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
676 nir_dest_bit_size(instr
->dest
.dest
)));
679 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
680 op
[i
] = get_nir_src(instr
->src
[i
].src
);
681 op
[i
].type
= brw_type_for_nir_type(devinfo
,
682 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
683 nir_src_bit_size(instr
->src
[i
].src
)));
684 op
[i
].abs
= instr
->src
[i
].abs
;
685 op
[i
].negate
= instr
->src
[i
].negate
;
688 /* We get a bunch of mov's out of the from_ssa pass and they may still
689 * be vectorized. We'll handle them as a special-case. We'll also
690 * handle vecN here because it's basically the same thing.
698 fs_reg temp
= result
;
699 bool need_extra_copy
= false;
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 if (!instr
->src
[i
].src
.is_ssa
&&
702 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
703 need_extra_copy
= true;
704 temp
= bld
.vgrf(result
.type
, 4);
709 for (unsigned i
= 0; i
< 4; i
++) {
710 if (!(instr
->dest
.write_mask
& (1 << i
)))
713 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
714 inst
= bld
.MOV(offset(temp
, bld
, i
),
715 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
717 inst
= bld
.MOV(offset(temp
, bld
, i
),
718 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
720 inst
->saturate
= instr
->dest
.saturate
;
723 /* In this case the source and destination registers were the same,
724 * so we need to insert an extra set of moves in order to deal with
727 if (need_extra_copy
) {
728 for (unsigned i
= 0; i
< 4; i
++) {
729 if (!(instr
->dest
.write_mask
& (1 << i
)))
732 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
741 /* At this point, we have dealt with any instruction that operates on
742 * more than a single channel. Therefore, we can just adjust the source
743 * and destination registers for that channel and emit the instruction.
745 unsigned channel
= 0;
746 if (nir_op_infos
[instr
->op
].output_size
== 0) {
747 /* Since NIR is doing the scalarizing for us, we should only ever see
748 * vectorized operations with a single channel.
750 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
751 channel
= ffs(instr
->dest
.write_mask
) - 1;
753 result
= offset(result
, bld
, channel
);
756 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
757 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
758 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
764 if (optimize_extract_to_float(instr
, result
))
766 inst
= bld
.MOV(result
, op
[0]);
767 inst
->saturate
= instr
->dest
.saturate
;
770 case nir_op_f2f16_rtne
:
771 case nir_op_f2f16_rtz
:
772 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
773 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
776 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
777 * on the HW gen, it is a special hw opcode or just a MOV, and
778 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
780 * But if we want to use that opcode, we need to provide support on
781 * different optimizations and lowerings. As right now HF support is
782 * only for gen8+, it will be better to use directly the MOV, and use
783 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
787 inst
= bld
.MOV(result
, op
[0]);
788 inst
->saturate
= instr
->dest
.saturate
;
798 op
[0].type
= BRW_REGISTER_TYPE_D
;
799 op
[0].negate
= !op
[0].negate
;
821 inst
= bld
.MOV(result
, op
[0]);
822 inst
->saturate
= instr
->dest
.saturate
;
826 assert(!instr
->dest
.saturate
);
828 /* Straightforward since the source can be assumed to be either
829 * strictly >= 0 or strictly <= 0 depending on the setting of the
832 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
834 inst
= (op
[0].negate
)
835 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
836 : bld
.MOV(result
, brw_imm_f(1.0f
));
838 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
839 } else if (type_sz(op
[0].type
) < 8) {
840 /* AND(val, 0x80000000) gives the sign bit.
842 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
845 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
847 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
848 op
[0].type
= BRW_REGISTER_TYPE_UD
;
849 result
.type
= BRW_REGISTER_TYPE_UD
;
850 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
852 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
853 inst
->predicate
= BRW_PREDICATE_NORMAL
;
855 /* For doubles we do the same but we need to consider:
857 * - 2-src instructions can't operate with 64-bit immediates
858 * - The sign is encoded in the high 32-bit of each DF
859 * - We need to produce a DF result.
862 fs_reg zero
= vgrf(glsl_type::double_type
);
863 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
864 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
866 bld
.MOV(result
, zero
);
868 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
869 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
870 brw_imm_ud(0x80000000u
));
872 set_predicate(BRW_PREDICATE_NORMAL
,
873 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
879 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
880 * -> non-negative val generates 0x00000000.
881 * Predicated OR sets 1 if val is positive.
883 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
884 assert(bit_size
== 32 || bit_size
== 16);
886 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
887 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
888 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
890 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
891 bld
.ASR(result
, op
[0], shift
);
892 inst
= bld
.OR(result
, result
, one
);
893 inst
->predicate
= BRW_PREDICATE_NORMAL
;
898 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
899 inst
->saturate
= instr
->dest
.saturate
;
903 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
904 inst
->saturate
= instr
->dest
.saturate
;
908 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
909 inst
->saturate
= instr
->dest
.saturate
;
913 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
914 inst
->saturate
= instr
->dest
.saturate
;
918 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
919 inst
->saturate
= instr
->dest
.saturate
;
923 if (fs_key
->high_quality_derivatives
) {
924 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
926 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
928 inst
->saturate
= instr
->dest
.saturate
;
930 case nir_op_fddx_fine
:
931 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
932 inst
->saturate
= instr
->dest
.saturate
;
934 case nir_op_fddx_coarse
:
935 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
936 inst
->saturate
= instr
->dest
.saturate
;
939 if (fs_key
->high_quality_derivatives
) {
940 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
942 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
944 inst
->saturate
= instr
->dest
.saturate
;
946 case nir_op_fddy_fine
:
947 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
948 inst
->saturate
= instr
->dest
.saturate
;
950 case nir_op_fddy_coarse
:
951 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
952 inst
->saturate
= instr
->dest
.saturate
;
957 inst
= bld
.ADD(result
, op
[0], op
[1]);
958 inst
->saturate
= instr
->dest
.saturate
;
961 case nir_op_uadd_sat
:
962 inst
= bld
.ADD(result
, op
[0], op
[1]);
963 inst
->saturate
= true;
967 inst
= bld
.MUL(result
, op
[0], op
[1]);
968 inst
->saturate
= instr
->dest
.saturate
;
972 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
973 bld
.MUL(result
, op
[0], op
[1]);
976 case nir_op_imul_high
:
977 case nir_op_umul_high
:
978 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
979 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
984 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
985 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
988 case nir_op_uadd_carry
:
989 unreachable("Should have been lowered by carry_to_arith().");
991 case nir_op_usub_borrow
:
992 unreachable("Should have been lowered by borrow_to_arith().");
996 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
997 * appears that our hardware just does the right thing for signed
1000 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1001 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1005 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1006 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1008 /* Math instructions don't support conditional mod */
1009 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1010 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1012 /* Now, we need to determine if signs of the sources are different.
1013 * When we XOR the sources, the top bit is 0 if they are the same and 1
1014 * if they are different. We can then use a conditional modifier to
1015 * turn that into a predicate. This leads us to an XOR.l instruction.
1017 * Technically, according to the PRM, you're not allowed to use .l on a
1018 * XOR instruction. However, emperical experiments and Curro's reading
1019 * of the simulator source both indicate that it's safe.
1021 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1022 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1023 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1024 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1026 /* If the result of the initial remainder operation is non-zero and the
1027 * two sources have different signs, add in a copy of op[1] to get the
1028 * final integer modulus value.
1030 inst
= bld
.ADD(result
, result
, op
[1]);
1031 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1038 case nir_op_fne32
: {
1039 fs_reg dest
= result
;
1041 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1043 dest
= bld
.vgrf(op
[0].type
, 1);
1045 brw_conditional_mod cond
;
1046 switch (instr
->op
) {
1048 cond
= BRW_CONDITIONAL_L
;
1051 cond
= BRW_CONDITIONAL_GE
;
1054 cond
= BRW_CONDITIONAL_Z
;
1057 cond
= BRW_CONDITIONAL_NZ
;
1060 unreachable("bad opcode");
1063 bld
.CMP(dest
, op
[0], op
[1], cond
);
1065 if (bit_size
> 32) {
1066 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1067 } else if(bit_size
< 32) {
1068 /* When we convert the result to 32-bit we need to be careful and do
1069 * it as a signed conversion to get sign extension (for 32-bit true)
1071 const brw_reg_type src_type
=
1072 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1074 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1084 case nir_op_ine32
: {
1085 fs_reg dest
= result
;
1087 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1089 dest
= bld
.vgrf(op
[0].type
, 1);
1091 brw_conditional_mod cond
;
1092 switch (instr
->op
) {
1095 cond
= BRW_CONDITIONAL_L
;
1099 cond
= BRW_CONDITIONAL_GE
;
1102 cond
= BRW_CONDITIONAL_Z
;
1105 cond
= BRW_CONDITIONAL_NZ
;
1108 unreachable("bad opcode");
1110 bld
.CMP(dest
, op
[0], op
[1], cond
);
1112 if (bit_size
> 32) {
1113 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1114 } else if (bit_size
< 32) {
1115 /* When we convert the result to 32-bit we need to be careful and do
1116 * it as a signed conversion to get sign extension (for 32-bit true)
1118 const brw_reg_type src_type
=
1119 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1121 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1127 if (devinfo
->gen
>= 8) {
1128 op
[0] = resolve_source_modifiers(op
[0]);
1130 bld
.NOT(result
, op
[0]);
1133 if (devinfo
->gen
>= 8) {
1134 op
[0] = resolve_source_modifiers(op
[0]);
1135 op
[1] = resolve_source_modifiers(op
[1]);
1137 bld
.XOR(result
, op
[0], op
[1]);
1140 if (devinfo
->gen
>= 8) {
1141 op
[0] = resolve_source_modifiers(op
[0]);
1142 op
[1] = resolve_source_modifiers(op
[1]);
1144 bld
.OR(result
, op
[0], op
[1]);
1147 if (devinfo
->gen
>= 8) {
1148 op
[0] = resolve_source_modifiers(op
[0]);
1149 op
[1] = resolve_source_modifiers(op
[1]);
1151 bld
.AND(result
, op
[0], op
[1]);
1157 case nir_op_b32all_fequal2
:
1158 case nir_op_b32all_iequal2
:
1159 case nir_op_b32all_fequal3
:
1160 case nir_op_b32all_iequal3
:
1161 case nir_op_b32all_fequal4
:
1162 case nir_op_b32all_iequal4
:
1163 case nir_op_b32any_fnequal2
:
1164 case nir_op_b32any_inequal2
:
1165 case nir_op_b32any_fnequal3
:
1166 case nir_op_b32any_inequal3
:
1167 case nir_op_b32any_fnequal4
:
1168 case nir_op_b32any_inequal4
:
1169 unreachable("Lowered by nir_lower_alu_reductions");
1171 case nir_op_fnoise1_1
:
1172 case nir_op_fnoise1_2
:
1173 case nir_op_fnoise1_3
:
1174 case nir_op_fnoise1_4
:
1175 case nir_op_fnoise2_1
:
1176 case nir_op_fnoise2_2
:
1177 case nir_op_fnoise2_3
:
1178 case nir_op_fnoise2_4
:
1179 case nir_op_fnoise3_1
:
1180 case nir_op_fnoise3_2
:
1181 case nir_op_fnoise3_3
:
1182 case nir_op_fnoise3_4
:
1183 case nir_op_fnoise4_1
:
1184 case nir_op_fnoise4_2
:
1185 case nir_op_fnoise4_3
:
1186 case nir_op_fnoise4_4
:
1187 unreachable("not reached: should be handled by lower_noise");
1190 unreachable("not reached: should be handled by ldexp_to_arith()");
1193 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1194 inst
->saturate
= instr
->dest
.saturate
;
1198 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1199 inst
->saturate
= instr
->dest
.saturate
;
1203 case nir_op_f2b32
: {
1204 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1205 if (bit_size
== 64) {
1206 /* two-argument instructions can't take 64-bit immediates */
1210 if (instr
->op
== nir_op_f2b32
) {
1211 zero
= vgrf(glsl_type::double_type
);
1212 tmp
= vgrf(glsl_type::double_type
);
1213 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1215 zero
= vgrf(glsl_type::int64_t_type
);
1216 tmp
= vgrf(glsl_type::int64_t_type
);
1217 bld
.MOV(zero
, brw_imm_q(0));
1220 /* A SIMD16 execution needs to be split in two instructions, so use
1221 * a vgrf instead of the flag register as dst so instruction splitting
1224 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1225 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1228 if (bit_size
== 32) {
1229 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1231 assert(bit_size
== 16);
1232 zero
= instr
->op
== nir_op_f2b32
?
1233 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1235 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1241 inst
= bld
.RNDZ(result
, op
[0]);
1242 inst
->saturate
= instr
->dest
.saturate
;
1245 case nir_op_fceil
: {
1246 op
[0].negate
= !op
[0].negate
;
1247 fs_reg temp
= vgrf(glsl_type::float_type
);
1248 bld
.RNDD(temp
, op
[0]);
1250 inst
= bld
.MOV(result
, temp
);
1251 inst
->saturate
= instr
->dest
.saturate
;
1255 inst
= bld
.RNDD(result
, op
[0]);
1256 inst
->saturate
= instr
->dest
.saturate
;
1259 inst
= bld
.FRC(result
, op
[0]);
1260 inst
->saturate
= instr
->dest
.saturate
;
1262 case nir_op_fround_even
:
1263 inst
= bld
.RNDE(result
, op
[0]);
1264 inst
->saturate
= instr
->dest
.saturate
;
1267 case nir_op_fquantize2f16
: {
1268 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1269 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1270 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1272 /* The destination stride must be at least as big as the source stride. */
1273 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1276 /* Check for denormal */
1277 fs_reg abs_src0
= op
[0];
1278 abs_src0
.abs
= true;
1279 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1281 /* Get the appropriately signed zero */
1282 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1283 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1284 brw_imm_ud(0x80000000));
1285 /* Do the actual F32 -> F16 -> F32 conversion */
1286 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1287 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1288 /* Select that or zero based on normal status */
1289 inst
= bld
.SEL(result
, zero
, tmp32
);
1290 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1291 inst
->saturate
= instr
->dest
.saturate
;
1298 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1299 inst
->saturate
= instr
->dest
.saturate
;
1305 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1306 inst
->saturate
= instr
->dest
.saturate
;
1309 case nir_op_pack_snorm_2x16
:
1310 case nir_op_pack_snorm_4x8
:
1311 case nir_op_pack_unorm_2x16
:
1312 case nir_op_pack_unorm_4x8
:
1313 case nir_op_unpack_snorm_2x16
:
1314 case nir_op_unpack_snorm_4x8
:
1315 case nir_op_unpack_unorm_2x16
:
1316 case nir_op_unpack_unorm_4x8
:
1317 case nir_op_unpack_half_2x16
:
1318 case nir_op_pack_half_2x16
:
1319 unreachable("not reached: should be handled by lower_packing_builtins");
1321 case nir_op_unpack_half_2x16_split_x
:
1322 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1323 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1324 inst
->saturate
= instr
->dest
.saturate
;
1326 case nir_op_unpack_half_2x16_split_y
:
1327 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1328 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1329 inst
->saturate
= instr
->dest
.saturate
;
1332 case nir_op_pack_64_2x32_split
:
1333 case nir_op_pack_32_2x16_split
:
1334 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1337 case nir_op_unpack_64_2x32_split_x
:
1338 case nir_op_unpack_64_2x32_split_y
: {
1339 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1340 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1342 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1346 case nir_op_unpack_32_2x16_split_x
:
1347 case nir_op_unpack_32_2x16_split_y
: {
1348 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1349 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1351 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1356 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1357 inst
->saturate
= instr
->dest
.saturate
;
1360 case nir_op_bitfield_reverse
:
1361 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1362 bld
.BFREV(result
, op
[0]);
1365 case nir_op_bit_count
:
1366 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1367 bld
.CBIT(result
, op
[0]);
1370 case nir_op_ufind_msb
: {
1371 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1372 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1376 case nir_op_ifind_msb
: {
1377 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1379 if (devinfo
->gen
< 7) {
1380 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1382 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1384 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1385 * count from the LSB side. If FBH didn't return an error
1386 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1387 * count into an LSB count.
1389 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1391 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1392 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1393 inst
->src
[0].negate
= true;
1398 case nir_op_find_lsb
:
1399 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1401 if (devinfo
->gen
< 7) {
1402 fs_reg temp
= vgrf(glsl_type::int_type
);
1404 /* (x & -x) generates a value that consists of only the LSB of x.
1405 * For all powers of 2, findMSB(y) == findLSB(y).
1407 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1408 fs_reg negated_src
= src
;
1410 /* One must be negated, and the other must be non-negated. It
1411 * doesn't matter which is which.
1413 negated_src
.negate
= true;
1416 bld
.AND(temp
, src
, negated_src
);
1417 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1419 bld
.FBL(result
, op
[0]);
1423 case nir_op_ubitfield_extract
:
1424 case nir_op_ibitfield_extract
:
1425 unreachable("should have been lowered");
1428 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1429 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1432 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1433 bld
.BFI1(result
, op
[0], op
[1]);
1436 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1437 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1440 case nir_op_bitfield_insert
:
1441 unreachable("not reached: should have been lowered");
1444 bld
.SHL(result
, op
[0], op
[1]);
1447 bld
.ASR(result
, op
[0], op
[1]);
1450 bld
.SHR(result
, op
[0], op
[1]);
1453 case nir_op_pack_half_2x16_split
:
1454 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1458 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1459 inst
->saturate
= instr
->dest
.saturate
;
1463 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1464 inst
->saturate
= instr
->dest
.saturate
;
1467 case nir_op_b32csel
:
1468 if (optimize_frontfacing_ternary(instr
, result
))
1471 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1472 inst
= bld
.SEL(result
, op
[1], op
[2]);
1473 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1476 case nir_op_extract_u8
:
1477 case nir_op_extract_i8
: {
1478 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1483 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1484 * Use two instructions and a word or DWord intermediate integer type.
1486 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1487 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1489 if (instr
->op
== nir_op_extract_i8
) {
1490 /* If we need to sign extend, extract to a word first */
1491 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1492 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1493 bld
.MOV(result
, w_temp
);
1495 /* Otherwise use an AND with 0xff and a word type */
1496 bld
.AND(result
, subscript(op
[0], type
, byte
/ 2), brw_imm_uw(0xff));
1499 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1500 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1505 case nir_op_extract_u16
:
1506 case nir_op_extract_i16
: {
1507 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1508 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1509 bld
.MOV(result
, subscript(op
[0], type
, word
));
1514 unreachable("unhandled instruction");
1517 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1518 * to sign extend the low bit to 0/~0
1520 if (devinfo
->gen
<= 5 &&
1521 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1522 fs_reg masked
= vgrf(glsl_type::int_type
);
1523 bld
.AND(masked
, result
, brw_imm_d(1));
1524 masked
.negate
= true;
1525 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1530 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1531 nir_load_const_instr
*instr
)
1533 const brw_reg_type reg_type
=
1534 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1535 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1537 switch (instr
->def
.bit_size
) {
1539 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1540 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1544 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1545 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1549 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1550 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1554 assert(devinfo
->gen
>= 7);
1555 if (devinfo
->gen
== 7) {
1556 /* We don't get 64-bit integer types until gen8 */
1557 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1558 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1559 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1562 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1563 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1568 unreachable("Invalid bit size");
1571 nir_ssa_values
[instr
->def
.index
] = reg
;
1575 fs_visitor::get_nir_src(const nir_src
&src
)
1579 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1580 const brw_reg_type reg_type
=
1581 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1582 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1584 reg
= nir_ssa_values
[src
.ssa
->index
];
1587 /* We don't handle indirects on locals */
1588 assert(src
.reg
.indirect
== NULL
);
1589 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1590 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1593 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1594 /* The only 64-bit type available on gen7 is DF, so use that. */
1595 reg
.type
= BRW_REGISTER_TYPE_DF
;
1597 /* To avoid floating-point denorm flushing problems, set the type by
1598 * default to an integer type - instructions that need floating point
1599 * semantics will set this to F if they need to
1601 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1602 BRW_REGISTER_TYPE_D
);
1609 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1611 * This function should not be called on any value which may be 64 bits.
1612 * We could theoretically support 64-bit on gen8+ but we choose not to
1613 * because it wouldn't work in general (no gen7 support) and there are
1614 * enough restrictions in 64-bit immediates that you can't take the return
1615 * value and treat it the same as the result of get_nir_src().
1618 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1620 assert(nir_src_bit_size(src
) == 32);
1621 return nir_src_is_const(src
) ?
1622 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1626 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1629 const brw_reg_type reg_type
=
1630 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1631 dest
.ssa
.bit_size
== 8 ?
1632 BRW_REGISTER_TYPE_D
:
1633 BRW_REGISTER_TYPE_F
);
1634 nir_ssa_values
[dest
.ssa
.index
] =
1635 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1636 return nir_ssa_values
[dest
.ssa
.index
];
1638 /* We don't handle indirects on locals */
1639 assert(dest
.reg
.indirect
== NULL
);
1640 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1641 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1646 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1649 for (unsigned i
= 0; i
< 4; i
++) {
1650 if (!((wr_mask
>> i
) & 1))
1653 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1654 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1655 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1656 if (new_inst
->src
[j
].file
== VGRF
)
1657 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1664 emit_pixel_interpolater_send(const fs_builder
&bld
,
1669 glsl_interp_mode interpolation
)
1671 struct brw_wm_prog_data
*wm_prog_data
=
1672 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1674 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1675 /* 2 floats per slot returned */
1676 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1677 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1679 wm_prog_data
->pulls_bary
= true;
1685 * Computes 1 << x, given a D/UD register containing some value x.
1688 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1690 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1692 fs_reg result
= bld
.vgrf(x
.type
, 1);
1693 fs_reg one
= bld
.vgrf(x
.type
, 1);
1695 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1696 bld
.SHL(result
, one
, x
);
1701 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1703 assert(stage
== MESA_SHADER_GEOMETRY
);
1705 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1707 if (gs_compile
->control_data_header_size_bits
== 0)
1710 /* We can only do EndPrimitive() functionality when the control data
1711 * consists of cut bits. Fortunately, the only time it isn't is when the
1712 * output type is points, in which case EndPrimitive() is a no-op.
1714 if (gs_prog_data
->control_data_format
!=
1715 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1719 /* Cut bits use one bit per vertex. */
1720 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1722 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1723 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1725 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1726 * vertex n, 0 otherwise. So all we need to do here is mark bit
1727 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1728 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1729 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1731 * Note that if EndPrimitive() is called before emitting any vertices, this
1732 * will cause us to set bit 31 of the control_data_bits register to 1.
1733 * That's fine because:
1735 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1736 * output, so the hardware will ignore cut bit 31.
1738 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1739 * last vertex, so setting cut bit 31 has no effect (since the primitive
1740 * is automatically ended when the GS terminates).
1742 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1743 * control_data_bits register to 0 when the first vertex is emitted.
1746 const fs_builder abld
= bld
.annotate("end primitive");
1748 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1749 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1750 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1751 fs_reg mask
= intexp2(abld
, prev_count
);
1752 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1753 * attention to the lower 5 bits of its second source argument, so on this
1754 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1755 * ((vertex_count - 1) % 32).
1757 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1761 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1763 assert(stage
== MESA_SHADER_GEOMETRY
);
1764 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1766 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1768 const fs_builder abld
= bld
.annotate("emit control data bits");
1769 const fs_builder fwa_bld
= bld
.exec_all();
1771 /* We use a single UD register to accumulate control data bits (32 bits
1772 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1775 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1776 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1777 * use the Channel Mask phase to enable/disable which DWord within that
1778 * group to write. (Remember, different SIMD8 channels may have emitted
1779 * different numbers of vertices, so we may need per-slot offsets.)
1781 * Channel masking presents an annoying problem: we may have to replicate
1782 * the data up to 4 times:
1784 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1786 * To avoid penalizing shaders that emit a small number of vertices, we
1787 * can avoid these sometimes: if the size of the control data header is
1788 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1789 * land in the same 128-bit group, so we can skip per-slot offsets.
1791 * Similarly, if the control data header is <= 32 bits, there is only one
1792 * DWord, so we can skip channel masks.
1794 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1796 fs_reg channel_mask
, per_slot_offset
;
1798 if (gs_compile
->control_data_header_size_bits
> 32) {
1799 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1800 channel_mask
= vgrf(glsl_type::uint_type
);
1803 if (gs_compile
->control_data_header_size_bits
> 128) {
1804 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1805 per_slot_offset
= vgrf(glsl_type::uint_type
);
1808 /* Figure out which DWord we're trying to write to using the formula:
1810 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1812 * Since bits_per_vertex is a power of two, and is known at compile
1813 * time, this can be optimized to:
1815 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1817 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1818 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1819 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1820 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1821 unsigned log2_bits_per_vertex
=
1822 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1823 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1825 if (per_slot_offset
.file
!= BAD_FILE
) {
1826 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1827 * the appropriate OWord within the control data header.
1829 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1832 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1833 * write to the appropriate DWORD within the OWORD.
1835 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1836 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1837 channel_mask
= intexp2(fwa_bld
, channel
);
1838 /* Then the channel masks need to be in bits 23:16. */
1839 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1842 /* Store the control data bits in the message payload and send it. */
1844 if (channel_mask
.file
!= BAD_FILE
)
1845 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1846 if (per_slot_offset
.file
!= BAD_FILE
)
1849 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1850 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1852 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1853 if (per_slot_offset
.file
!= BAD_FILE
)
1854 sources
[i
++] = per_slot_offset
;
1855 if (channel_mask
.file
!= BAD_FILE
)
1856 sources
[i
++] = channel_mask
;
1858 sources
[i
++] = this->control_data_bits
;
1861 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1862 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1864 /* We need to increment Global Offset by 256-bits to make room for
1865 * Broadwell's extra "Vertex Count" payload at the beginning of the
1866 * URB entry. Since this is an OWord message, Global Offset is counted
1867 * in 128-bit units, so we must set it to 2.
1869 if (gs_prog_data
->static_vertex_count
== -1)
1874 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1877 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1879 /* Note: we are calling this *before* increasing vertex_count, so
1880 * this->vertex_count == vertex_count - 1 in the formula above.
1883 /* Stream mode uses 2 bits per vertex */
1884 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1886 /* Must be a valid stream */
1887 assert(stream_id
< MAX_VERTEX_STREAMS
);
1889 /* Control data bits are initialized to 0 so we don't have to set any
1890 * bits when sending vertices to stream 0.
1895 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1897 /* reg::sid = stream_id */
1898 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1899 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1901 /* reg:shift_count = 2 * (vertex_count - 1) */
1902 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1903 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1905 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1906 * attention to the lower 5 bits of its second source argument, so on this
1907 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1908 * stream_id << ((2 * (vertex_count - 1)) % 32).
1910 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1911 abld
.SHL(mask
, sid
, shift_count
);
1912 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1916 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1919 assert(stage
== MESA_SHADER_GEOMETRY
);
1921 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1923 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1924 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1926 /* Haswell and later hardware ignores the "Render Stream Select" bits
1927 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1928 * and instead sends all primitives down the pipeline for rasterization.
1929 * If the SOL stage is enabled, "Render Stream Select" is honored and
1930 * primitives bound to non-zero streams are discarded after stream output.
1932 * Since the only purpose of primives sent to non-zero streams is to
1933 * be recorded by transform feedback, we can simply discard all geometry
1934 * bound to these streams when transform feedback is disabled.
1936 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1939 /* If we're outputting 32 control data bits or less, then we can wait
1940 * until the shader is over to output them all. Otherwise we need to
1941 * output them as we go. Now is the time to do it, since we're about to
1942 * output the vertex_count'th vertex, so it's guaranteed that the
1943 * control data bits associated with the (vertex_count - 1)th vertex are
1946 if (gs_compile
->control_data_header_size_bits
> 32) {
1947 const fs_builder abld
=
1948 bld
.annotate("emit vertex: emit control data bits");
1950 /* Only emit control data bits if we've finished accumulating a batch
1951 * of 32 bits. This is the case when:
1953 * (vertex_count * bits_per_vertex) % 32 == 0
1955 * (in other words, when the last 5 bits of vertex_count *
1956 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1957 * integer n (which is always the case, since bits_per_vertex is
1958 * always 1 or 2), this is equivalent to requiring that the last 5-n
1959 * bits of vertex_count are 0:
1961 * vertex_count & (2^(5-n) - 1) == 0
1963 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1966 * vertex_count & (32 / bits_per_vertex - 1) == 0
1968 * TODO: If vertex_count is an immediate, we could do some of this math
1969 * at compile time...
1972 abld
.AND(bld
.null_reg_d(), vertex_count
,
1973 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1974 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1976 abld
.IF(BRW_PREDICATE_NORMAL
);
1977 /* If vertex_count is 0, then no control data bits have been
1978 * accumulated yet, so we can skip emitting them.
1980 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1981 BRW_CONDITIONAL_NEQ
);
1982 abld
.IF(BRW_PREDICATE_NORMAL
);
1983 emit_gs_control_data_bits(vertex_count
);
1984 abld
.emit(BRW_OPCODE_ENDIF
);
1986 /* Reset control_data_bits to 0 so we can start accumulating a new
1989 * Note: in the case where vertex_count == 0, this neutralizes the
1990 * effect of any call to EndPrimitive() that the shader may have
1991 * made before outputting its first vertex.
1993 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1994 inst
->force_writemask_all
= true;
1995 abld
.emit(BRW_OPCODE_ENDIF
);
1998 emit_urb_writes(vertex_count
);
2000 /* In stream mode we have to set control data bits for all vertices
2001 * unless we have disabled control data bits completely (which we do
2002 * do for GL_POINTS outputs that don't use streams).
2004 if (gs_compile
->control_data_header_size_bits
> 0 &&
2005 gs_prog_data
->control_data_format
==
2006 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2007 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2012 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2013 const nir_src
&vertex_src
,
2014 unsigned base_offset
,
2015 const nir_src
&offset_src
,
2016 unsigned num_components
,
2017 unsigned first_component
)
2019 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2020 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2022 /* TODO: figure out push input layout for invocations == 1 */
2023 /* TODO: make this work with 64-bit inputs */
2024 if (gs_prog_data
->invocations
== 1 &&
2025 type_sz(dst
.type
) <= 4 &&
2026 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2027 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2028 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2029 nir_src_as_uint(vertex_src
) * push_reg_count
;
2030 for (unsigned i
= 0; i
< num_components
; i
++) {
2031 bld
.MOV(offset(dst
, bld
, i
),
2032 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2037 /* Resort to the pull model. Ensure the VUE handles are provided. */
2038 assert(gs_prog_data
->base
.include_vue_handles
);
2040 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2041 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2043 if (gs_prog_data
->invocations
== 1) {
2044 if (nir_src_is_const(vertex_src
)) {
2045 /* The vertex index is constant; just select the proper URB handle. */
2047 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2048 BRW_REGISTER_TYPE_UD
);
2050 /* The vertex index is non-constant. We need to use indirect
2051 * addressing to fetch the proper URB handle.
2053 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2054 * indicating that channel <n> should read the handle from
2055 * DWord <n>. We convert that to bytes by multiplying by 4.
2057 * Next, we convert the vertex index to bytes by multiplying
2058 * by 32 (shifting by 5), and add the two together. This is
2059 * the final indirect byte offset.
2061 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2062 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2063 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2064 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2066 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2067 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2068 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2069 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2070 /* Convert vertex_index to bytes (multiply by 32) */
2071 bld
.SHL(vertex_offset_bytes
,
2072 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2074 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2076 /* Use first_icp_handle as the base offset. There is one register
2077 * of URB handles per vertex, so inform the register allocator that
2078 * we might read up to nir->info.gs.vertices_in registers.
2080 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2081 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2082 fs_reg(icp_offset_bytes
),
2083 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2086 assert(gs_prog_data
->invocations
> 1);
2088 if (nir_src_is_const(vertex_src
)) {
2089 unsigned vertex
= nir_src_as_uint(vertex_src
);
2090 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2092 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2093 BRW_REGISTER_TYPE_UD
));
2095 /* The vertex index is non-constant. We need to use indirect
2096 * addressing to fetch the proper URB handle.
2099 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2101 /* Convert vertex_index to bytes (multiply by 4) */
2102 bld
.SHL(icp_offset_bytes
,
2103 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2106 /* Use first_icp_handle as the base offset. There is one DWord
2107 * of URB handles per vertex, so inform the register allocator that
2108 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2110 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2111 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2112 fs_reg(icp_offset_bytes
),
2113 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2120 fs_reg tmp_dst
= dst
;
2121 fs_reg indirect_offset
= get_nir_src(offset_src
);
2122 unsigned num_iterations
= 1;
2123 unsigned orig_num_components
= num_components
;
2125 if (type_sz(dst
.type
) == 8) {
2126 if (num_components
> 2) {
2130 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2132 first_component
= first_component
/ 2;
2135 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2136 if (nir_src_is_const(offset_src
)) {
2137 /* Constant indexing - use global offset. */
2138 if (first_component
!= 0) {
2139 unsigned read_components
= num_components
+ first_component
;
2140 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2141 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2142 inst
->size_written
= read_components
*
2143 tmp
.component_size(inst
->exec_size
);
2144 for (unsigned i
= 0; i
< num_components
; i
++) {
2145 bld
.MOV(offset(tmp_dst
, bld
, i
),
2146 offset(tmp
, bld
, i
+ first_component
));
2149 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2151 inst
->size_written
= num_components
*
2152 tmp_dst
.component_size(inst
->exec_size
);
2154 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2157 /* Indirect indexing - use per-slot offsets as well. */
2158 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2159 unsigned read_components
= num_components
+ first_component
;
2160 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2161 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2162 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2163 if (first_component
!= 0) {
2164 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2166 inst
->size_written
= read_components
*
2167 tmp
.component_size(inst
->exec_size
);
2168 for (unsigned i
= 0; i
< num_components
; i
++) {
2169 bld
.MOV(offset(tmp_dst
, bld
, i
),
2170 offset(tmp
, bld
, i
+ first_component
));
2173 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2175 inst
->size_written
= num_components
*
2176 tmp_dst
.component_size(inst
->exec_size
);
2178 inst
->offset
= base_offset
;
2182 if (type_sz(dst
.type
) == 8) {
2183 shuffle_from_32bit_read(bld
,
2184 offset(dst
, bld
, iter
* 2),
2185 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2190 if (num_iterations
> 1) {
2191 num_components
= orig_num_components
- 2;
2192 if(nir_src_is_const(offset_src
)) {
2195 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2196 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2197 indirect_offset
= new_indirect
;
2204 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2206 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2208 if (nir_src_is_const(*offset_src
)) {
2209 /* The only constant offset we should find is 0. brw_nir.c's
2210 * add_const_offset_to_base() will fold other constant offsets
2211 * into instr->const_index[0].
2213 assert(nir_src_as_uint(*offset_src
) == 0);
2217 return get_nir_src(*offset_src
);
2221 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2222 nir_intrinsic_instr
*instr
)
2224 assert(stage
== MESA_SHADER_VERTEX
);
2227 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2228 dest
= get_nir_dest(instr
->dest
);
2230 switch (instr
->intrinsic
) {
2231 case nir_intrinsic_load_vertex_id
:
2232 case nir_intrinsic_load_base_vertex
:
2233 unreachable("should be lowered by nir_lower_system_values()");
2235 case nir_intrinsic_load_input
: {
2236 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2237 unsigned first_component
= nir_intrinsic_component(instr
);
2238 unsigned num_components
= instr
->num_components
;
2240 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2242 if (type_sz(dest
.type
) == 8)
2243 first_component
/= 2;
2245 /* For 16-bit support maybe a temporary will be needed to copy from
2248 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2249 first_component
, num_components
);
2253 case nir_intrinsic_load_vertex_id_zero_base
:
2254 case nir_intrinsic_load_instance_id
:
2255 case nir_intrinsic_load_base_instance
:
2256 case nir_intrinsic_load_draw_id
:
2257 case nir_intrinsic_load_first_vertex
:
2258 case nir_intrinsic_load_is_indexed_draw
:
2259 unreachable("lowered by brw_nir_lower_vs_inputs");
2262 nir_emit_intrinsic(bld
, instr
);
2268 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2269 nir_intrinsic_instr
*instr
)
2271 assert(stage
== MESA_SHADER_TESS_CTRL
);
2272 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2273 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2276 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2277 dst
= get_nir_dest(instr
->dest
);
2279 switch (instr
->intrinsic
) {
2280 case nir_intrinsic_load_primitive_id
:
2281 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2283 case nir_intrinsic_load_invocation_id
:
2284 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2286 case nir_intrinsic_load_patch_vertices_in
:
2287 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2288 brw_imm_d(tcs_key
->input_vertices
));
2291 case nir_intrinsic_barrier
: {
2292 if (tcs_prog_data
->instances
== 1)
2295 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2296 fs_reg m0_2
= component(m0
, 2);
2298 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2300 /* Zero the message header */
2301 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2303 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2304 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2305 brw_imm_ud(INTEL_MASK(16, 13)));
2307 /* Shift it up to bits 27:24. */
2308 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2310 /* Set the Barrier Count and the enable bit */
2311 chanbld
.OR(m0_2
, m0_2
,
2312 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2314 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2318 case nir_intrinsic_load_input
:
2319 unreachable("nir_lower_io should never give us these.");
2322 case nir_intrinsic_load_per_vertex_input
: {
2323 fs_reg indirect_offset
= get_indirect_offset(instr
);
2324 unsigned imm_offset
= instr
->const_index
[0];
2326 const nir_src
&vertex_src
= instr
->src
[0];
2332 if (nir_src_is_const(vertex_src
)) {
2333 /* Emit a MOV to resolve <0,1,0> regioning. */
2334 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2335 unsigned vertex
= nir_src_as_uint(vertex_src
);
2337 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2338 BRW_REGISTER_TYPE_UD
));
2339 } else if (tcs_prog_data
->instances
== 1 &&
2340 vertex_src
.is_ssa
&&
2341 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2342 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2343 /* For the common case of only 1 instance, an array index of
2344 * gl_InvocationID means reading g1. Skip all the indirect work.
2346 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2348 /* The vertex index is non-constant. We need to use indirect
2349 * addressing to fetch the proper URB handle.
2351 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2353 /* Each ICP handle is a single DWord (4 bytes) */
2354 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2355 bld
.SHL(vertex_offset_bytes
,
2356 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2359 /* Start at g1. We might read up to 4 registers. */
2360 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2361 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2362 brw_imm_ud(4 * REG_SIZE
));
2365 /* We can only read two double components with each URB read, so
2366 * we send two read messages in that case, each one loading up to
2367 * two double components.
2369 unsigned num_iterations
= 1;
2370 unsigned num_components
= instr
->num_components
;
2371 unsigned first_component
= nir_intrinsic_component(instr
);
2372 fs_reg orig_dst
= dst
;
2373 if (type_sz(dst
.type
) == 8) {
2374 first_component
= first_component
/ 2;
2375 if (instr
->num_components
> 2) {
2380 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2384 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2385 if (indirect_offset
.file
== BAD_FILE
) {
2386 /* Constant indexing - use global offset. */
2387 if (first_component
!= 0) {
2388 unsigned read_components
= num_components
+ first_component
;
2389 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2390 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2391 for (unsigned i
= 0; i
< num_components
; i
++) {
2392 bld
.MOV(offset(dst
, bld
, i
),
2393 offset(tmp
, bld
, i
+ first_component
));
2396 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2398 inst
->offset
= imm_offset
;
2401 /* Indirect indexing - use per-slot offsets as well. */
2402 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2403 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2404 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2405 if (first_component
!= 0) {
2406 unsigned read_components
= num_components
+ first_component
;
2407 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2408 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2410 for (unsigned i
= 0; i
< num_components
; i
++) {
2411 bld
.MOV(offset(dst
, bld
, i
),
2412 offset(tmp
, bld
, i
+ first_component
));
2415 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2418 inst
->offset
= imm_offset
;
2421 inst
->size_written
= (num_components
+ first_component
) *
2422 inst
->dst
.component_size(inst
->exec_size
);
2424 /* If we are reading 64-bit data using 32-bit read messages we need
2425 * build proper 64-bit data elements by shuffling the low and high
2426 * 32-bit components around like we do for other things like UBOs
2429 if (type_sz(dst
.type
) == 8) {
2430 shuffle_from_32bit_read(bld
,
2431 offset(orig_dst
, bld
, iter
* 2),
2432 retype(dst
, BRW_REGISTER_TYPE_D
),
2436 /* Copy the temporary to the destination to deal with writemasking.
2438 * Also attempt to deal with gl_PointSize being in the .w component.
2440 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2441 assert(type_sz(dst
.type
) < 8);
2442 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2443 inst
->size_written
= 4 * REG_SIZE
;
2444 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2447 /* If we are loading double data and we need a second read message
2448 * adjust the write offset
2450 if (num_iterations
> 1) {
2451 num_components
= instr
->num_components
- 2;
2458 case nir_intrinsic_load_output
:
2459 case nir_intrinsic_load_per_vertex_output
: {
2460 fs_reg indirect_offset
= get_indirect_offset(instr
);
2461 unsigned imm_offset
= instr
->const_index
[0];
2462 unsigned first_component
= nir_intrinsic_component(instr
);
2465 if (indirect_offset
.file
== BAD_FILE
) {
2466 /* Replicate the patch handle to all enabled channels */
2467 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2468 bld
.MOV(patch_handle
,
2469 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2472 if (first_component
!= 0) {
2473 unsigned read_components
=
2474 instr
->num_components
+ first_component
;
2475 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2476 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2478 inst
->size_written
= read_components
* REG_SIZE
;
2479 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2480 bld
.MOV(offset(dst
, bld
, i
),
2481 offset(tmp
, bld
, i
+ first_component
));
2484 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2486 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2488 inst
->offset
= imm_offset
;
2492 /* Indirect indexing - use per-slot offsets as well. */
2493 const fs_reg srcs
[] = {
2494 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2497 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2498 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2499 if (first_component
!= 0) {
2500 unsigned read_components
=
2501 instr
->num_components
+ first_component
;
2502 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2503 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2505 inst
->size_written
= read_components
* REG_SIZE
;
2506 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2507 bld
.MOV(offset(dst
, bld
, i
),
2508 offset(tmp
, bld
, i
+ first_component
));
2511 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2513 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2515 inst
->offset
= imm_offset
;
2521 case nir_intrinsic_store_output
:
2522 case nir_intrinsic_store_per_vertex_output
: {
2523 fs_reg value
= get_nir_src(instr
->src
[0]);
2524 bool is_64bit
= (instr
->src
[0].is_ssa
?
2525 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2526 fs_reg indirect_offset
= get_indirect_offset(instr
);
2527 unsigned imm_offset
= instr
->const_index
[0];
2528 unsigned mask
= instr
->const_index
[1];
2529 unsigned header_regs
= 0;
2531 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2533 if (indirect_offset
.file
!= BAD_FILE
) {
2534 srcs
[header_regs
++] = indirect_offset
;
2540 unsigned num_components
= util_last_bit(mask
);
2543 /* We can only pack two 64-bit components in a single message, so send
2544 * 2 messages if we have more components
2546 unsigned num_iterations
= 1;
2547 unsigned iter_components
= num_components
;
2548 unsigned first_component
= nir_intrinsic_component(instr
);
2550 first_component
= first_component
/ 2;
2551 if (instr
->num_components
> 2) {
2553 iter_components
= 2;
2557 mask
= mask
<< first_component
;
2559 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2560 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2561 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2562 opcode
= indirect_offset
.file
!= BAD_FILE
?
2563 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2564 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2565 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2566 /* Expand the 64-bit mask to 32-bit channels. We only handle
2567 * two channels in each iteration, so we only care about X/Y.
2569 unsigned mask32
= 0;
2570 if (mask
& WRITEMASK_X
)
2571 mask32
|= WRITEMASK_XY
;
2572 if (mask
& WRITEMASK_Y
)
2573 mask32
|= WRITEMASK_ZW
;
2575 /* If the mask does not include any of the channels X or Y there
2576 * is nothing to do in this iteration. Move on to the next couple
2577 * of 64-bit channels.
2585 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2586 opcode
= indirect_offset
.file
!= BAD_FILE
?
2587 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2588 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2590 opcode
= indirect_offset
.file
!= BAD_FILE
?
2591 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2592 SHADER_OPCODE_URB_WRITE_SIMD8
;
2595 for (unsigned i
= 0; i
< iter_components
; i
++) {
2596 if (!(mask
& (1 << (i
+ first_component
))))
2600 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2602 /* We need to shuffle the 64-bit data to match the layout
2603 * expected by our 32-bit URB write messages. We use a temporary
2606 unsigned channel
= iter
* 2 + i
;
2607 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2609 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2610 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2611 offset(dest
, bld
, 1);
2616 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2617 (is_64bit
? 2 * first_component
: first_component
);
2619 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2620 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2622 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2623 inst
->offset
= imm_offset
;
2626 /* If this is a 64-bit attribute, select the next two 64-bit channels
2627 * to be handled in the next iteration.
2638 nir_emit_intrinsic(bld
, instr
);
2644 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2645 nir_intrinsic_instr
*instr
)
2647 assert(stage
== MESA_SHADER_TESS_EVAL
);
2648 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2651 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2652 dest
= get_nir_dest(instr
->dest
);
2654 switch (instr
->intrinsic
) {
2655 case nir_intrinsic_load_primitive_id
:
2656 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2658 case nir_intrinsic_load_tess_coord
:
2659 /* gl_TessCoord is part of the payload in g1-3 */
2660 for (unsigned i
= 0; i
< 3; i
++) {
2661 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2665 case nir_intrinsic_load_input
:
2666 case nir_intrinsic_load_per_vertex_input
: {
2667 fs_reg indirect_offset
= get_indirect_offset(instr
);
2668 unsigned imm_offset
= instr
->const_index
[0];
2669 unsigned first_component
= nir_intrinsic_component(instr
);
2671 if (type_sz(dest
.type
) == 8) {
2672 first_component
= first_component
/ 2;
2676 if (indirect_offset
.file
== BAD_FILE
) {
2677 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2678 * which is 16 registers (since each holds 2 vec4 slots).
2680 unsigned slot_count
= 1;
2681 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2684 const unsigned max_push_slots
= 32;
2685 if (imm_offset
+ slot_count
<= max_push_slots
) {
2686 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2687 for (int i
= 0; i
< instr
->num_components
; i
++) {
2688 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2689 i
+ first_component
;
2690 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2693 tes_prog_data
->base
.urb_read_length
=
2694 MAX2(tes_prog_data
->base
.urb_read_length
,
2695 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2697 /* Replicate the patch handle to all enabled channels */
2698 const fs_reg srcs
[] = {
2699 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2701 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2702 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2704 if (first_component
!= 0) {
2705 unsigned read_components
=
2706 instr
->num_components
+ first_component
;
2707 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2708 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2710 inst
->size_written
= read_components
* REG_SIZE
;
2711 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2712 bld
.MOV(offset(dest
, bld
, i
),
2713 offset(tmp
, bld
, i
+ first_component
));
2716 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2718 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2721 inst
->offset
= imm_offset
;
2724 /* Indirect indexing - use per-slot offsets as well. */
2726 /* We can only read two double components with each URB read, so
2727 * we send two read messages in that case, each one loading up to
2728 * two double components.
2730 unsigned num_iterations
= 1;
2731 unsigned num_components
= instr
->num_components
;
2732 fs_reg orig_dest
= dest
;
2733 if (type_sz(dest
.type
) == 8) {
2734 if (instr
->num_components
> 2) {
2738 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2742 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2743 const fs_reg srcs
[] = {
2744 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2747 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2748 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2750 if (first_component
!= 0) {
2751 unsigned read_components
=
2752 num_components
+ first_component
;
2753 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2754 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2756 for (unsigned i
= 0; i
< num_components
; i
++) {
2757 bld
.MOV(offset(dest
, bld
, i
),
2758 offset(tmp
, bld
, i
+ first_component
));
2761 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2765 inst
->offset
= imm_offset
;
2766 inst
->size_written
= (num_components
+ first_component
) *
2767 inst
->dst
.component_size(inst
->exec_size
);
2769 /* If we are reading 64-bit data using 32-bit read messages we need
2770 * build proper 64-bit data elements by shuffling the low and high
2771 * 32-bit components around like we do for other things like UBOs
2774 if (type_sz(dest
.type
) == 8) {
2775 shuffle_from_32bit_read(bld
,
2776 offset(orig_dest
, bld
, iter
* 2),
2777 retype(dest
, BRW_REGISTER_TYPE_D
),
2781 /* If we are loading double data and we need a second read message
2784 if (num_iterations
> 1) {
2785 num_components
= instr
->num_components
- 2;
2793 nir_emit_intrinsic(bld
, instr
);
2799 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2800 nir_intrinsic_instr
*instr
)
2802 assert(stage
== MESA_SHADER_GEOMETRY
);
2803 fs_reg indirect_offset
;
2806 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2807 dest
= get_nir_dest(instr
->dest
);
2809 switch (instr
->intrinsic
) {
2810 case nir_intrinsic_load_primitive_id
:
2811 assert(stage
== MESA_SHADER_GEOMETRY
);
2812 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2813 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2814 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2817 case nir_intrinsic_load_input
:
2818 unreachable("load_input intrinsics are invalid for the GS stage");
2820 case nir_intrinsic_load_per_vertex_input
:
2821 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2822 instr
->src
[1], instr
->num_components
,
2823 nir_intrinsic_component(instr
));
2826 case nir_intrinsic_emit_vertex_with_counter
:
2827 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2830 case nir_intrinsic_end_primitive_with_counter
:
2831 emit_gs_end_primitive(instr
->src
[0]);
2834 case nir_intrinsic_set_vertex_count
:
2835 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2838 case nir_intrinsic_load_invocation_id
: {
2839 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2840 assert(val
.file
!= BAD_FILE
);
2841 dest
.type
= val
.type
;
2847 nir_emit_intrinsic(bld
, instr
);
2853 * Fetch the current render target layer index.
2856 fetch_render_target_array_index(const fs_builder
&bld
)
2858 if (bld
.shader
->devinfo
->gen
>= 6) {
2859 /* The render target array index is provided in the thread payload as
2860 * bits 26:16 of r0.0.
2862 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2863 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2867 /* Pre-SNB we only ever render into the first layer of the framebuffer
2868 * since layered rendering is not implemented.
2870 return brw_imm_ud(0);
2875 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2876 * framebuffer at the current fragment coordinates and sample index.
2879 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2882 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2884 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2885 const brw_wm_prog_key
*wm_key
=
2886 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2887 assert(!wm_key
->coherent_fb_fetch
);
2888 const struct brw_wm_prog_data
*wm_prog_data
=
2889 brw_wm_prog_data(stage_prog_data
);
2891 /* Calculate the surface index relative to the start of the texture binding
2892 * table block, since that's what the texturing messages expect.
2894 const unsigned surface
= target
+
2895 wm_prog_data
->binding_table
.render_target_read_start
-
2896 wm_prog_data
->base
.binding_table
.texture_start
;
2898 brw_mark_surface_used(
2899 bld
.shader
->stage_prog_data
,
2900 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2902 /* Calculate the fragment coordinates. */
2903 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2904 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2905 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2906 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2908 /* Calculate the sample index and MCS payload when multisampling. Luckily
2909 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2910 * shouldn't be necessary to recompile based on whether the framebuffer is
2913 if (wm_key
->multisample_fbo
&&
2914 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2915 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2917 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2918 const fs_reg mcs
= wm_key
->multisample_fbo
?
2919 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2921 /* Use either a normal or a CMS texel fetch message depending on whether
2922 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2923 * message just in case the framebuffer uses 16x multisampling, it should
2924 * be equivalent to the normal CMS fetch for lower multisampling modes.
2926 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2927 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2928 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2930 /* Emit the instruction. */
2931 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
2932 fs_reg(), sample
, mcs
,
2933 brw_imm_ud(surface
), brw_imm_ud(0),
2934 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
2935 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
2937 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
2938 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2944 * Actual coherent framebuffer read implemented using the native render target
2945 * read message. Requires SKL+.
2948 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
2950 assert(bld
.shader
->devinfo
->gen
>= 9);
2951 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
2952 inst
->target
= target
;
2953 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2959 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
2961 if (n
&& regs
[0].file
!= BAD_FILE
) {
2965 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
2967 for (unsigned i
= 0; i
< n
; i
++)
2975 alloc_frag_output(fs_visitor
*v
, unsigned location
)
2977 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
2978 const brw_wm_prog_key
*const key
=
2979 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
2980 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
2981 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
2983 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
2984 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
2986 else if (l
== FRAG_RESULT_COLOR
)
2987 return alloc_temporary(v
->bld
, 4, v
->outputs
,
2988 MAX2(key
->nr_color_regions
, 1));
2990 else if (l
== FRAG_RESULT_DEPTH
)
2991 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
2993 else if (l
== FRAG_RESULT_STENCIL
)
2994 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
2996 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
2997 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
2999 else if (l
>= FRAG_RESULT_DATA0
&&
3000 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3001 return alloc_temporary(v
->bld
, 4,
3002 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3005 unreachable("Invalid location");
3009 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3010 nir_intrinsic_instr
*instr
)
3012 assert(stage
== MESA_SHADER_FRAGMENT
);
3015 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3016 dest
= get_nir_dest(instr
->dest
);
3018 switch (instr
->intrinsic
) {
3019 case nir_intrinsic_load_front_face
:
3020 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3021 *emit_frontfacing_interpolation());
3024 case nir_intrinsic_load_sample_pos
: {
3025 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3026 assert(sample_pos
.file
!= BAD_FILE
);
3027 dest
.type
= sample_pos
.type
;
3028 bld
.MOV(dest
, sample_pos
);
3029 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3033 case nir_intrinsic_load_layer_id
:
3034 dest
.type
= BRW_REGISTER_TYPE_UD
;
3035 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3038 case nir_intrinsic_load_helper_invocation
:
3039 case nir_intrinsic_load_sample_mask_in
:
3040 case nir_intrinsic_load_sample_id
: {
3041 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3042 fs_reg val
= nir_system_values
[sv
];
3043 assert(val
.file
!= BAD_FILE
);
3044 dest
.type
= val
.type
;
3049 case nir_intrinsic_store_output
: {
3050 const fs_reg src
= get_nir_src(instr
->src
[0]);
3051 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3052 const unsigned location
= nir_intrinsic_base(instr
) +
3053 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3054 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3057 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3058 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3059 offset(src
, bld
, j
));
3064 case nir_intrinsic_load_output
: {
3065 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3066 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3067 assert(l
>= FRAG_RESULT_DATA0
);
3068 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3069 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3070 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3072 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3073 emit_coherent_fb_read(bld
, tmp
, target
);
3075 emit_non_coherent_fb_read(bld
, tmp
, target
);
3077 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3078 bld
.MOV(offset(dest
, bld
, j
),
3079 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3085 case nir_intrinsic_discard
:
3086 case nir_intrinsic_discard_if
: {
3087 /* We track our discarded pixels in f0.1. By predicating on it, we can
3088 * update just the flag bits that aren't yet discarded. If there's no
3089 * condition, we emit a CMP of g0 != g0, so all currently executing
3090 * channels will get turned off.
3093 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3094 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3095 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3097 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3098 BRW_REGISTER_TYPE_UW
));
3099 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3101 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3102 cmp
->flag_subreg
= 1;
3104 if (devinfo
->gen
>= 6) {
3105 emit_discard_jump();
3108 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3112 case nir_intrinsic_load_input
: {
3113 /* load_input is only used for flat inputs */
3114 unsigned base
= nir_intrinsic_base(instr
);
3115 unsigned comp
= nir_intrinsic_component(instr
);
3116 unsigned num_components
= instr
->num_components
;
3117 fs_reg orig_dest
= dest
;
3118 enum brw_reg_type type
= dest
.type
;
3120 /* Special case fields in the VUE header */
3121 if (base
== VARYING_SLOT_LAYER
)
3123 else if (base
== VARYING_SLOT_VIEWPORT
)
3126 if (nir_dest_bit_size(instr
->dest
) == 64) {
3127 /* const_index is in 32-bit type size units that could not be aligned
3128 * with DF. We need to read the double vector as if it was a float
3129 * vector of twice the number of components to fetch the right data.
3131 type
= BRW_REGISTER_TYPE_F
;
3132 num_components
*= 2;
3133 dest
= bld
.vgrf(type
, num_components
);
3136 for (unsigned int i
= 0; i
< num_components
; i
++) {
3137 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3138 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3141 if (nir_dest_bit_size(instr
->dest
) == 64) {
3142 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3143 instr
->num_components
);
3148 case nir_intrinsic_load_barycentric_pixel
:
3149 case nir_intrinsic_load_barycentric_centroid
:
3150 case nir_intrinsic_load_barycentric_sample
:
3151 /* Do nothing - load_interpolated_input handling will handle it later. */
3154 case nir_intrinsic_load_barycentric_at_sample
: {
3155 const glsl_interp_mode interpolation
=
3156 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3158 if (nir_src_is_const(instr
->src
[0])) {
3159 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3161 emit_pixel_interpolater_send(bld
,
3162 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3165 brw_imm_ud(msg_data
),
3168 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3169 BRW_REGISTER_TYPE_UD
);
3171 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3172 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3173 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3174 bld
.exec_all().group(1, 0)
3175 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3176 emit_pixel_interpolater_send(bld
,
3177 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3183 /* Make a loop that sends a message to the pixel interpolater
3184 * for the sample number in each live channel. If there are
3185 * multiple channels with the same sample number then these
3186 * will be handled simultaneously with a single interation of
3189 bld
.emit(BRW_OPCODE_DO
);
3191 /* Get the next live sample number into sample_id_reg */
3192 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3194 /* Set the flag register so that we can perform the send
3195 * message on all channels that have the same sample number
3197 bld
.CMP(bld
.null_reg_ud(),
3198 sample_src
, sample_id
,
3199 BRW_CONDITIONAL_EQ
);
3200 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3201 bld
.exec_all().group(1, 0)
3202 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3204 emit_pixel_interpolater_send(bld
,
3205 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3208 component(msg_data
, 0),
3210 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3212 /* Continue the loop if there are any live channels left */
3213 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3215 bld
.emit(BRW_OPCODE_WHILE
));
3221 case nir_intrinsic_load_barycentric_at_offset
: {
3222 const glsl_interp_mode interpolation
=
3223 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3225 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3228 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3229 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3230 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3232 emit_pixel_interpolater_send(bld
,
3233 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3236 brw_imm_ud(off_x
| (off_y
<< 4)),
3239 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3240 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3241 BRW_REGISTER_TYPE_F
);
3242 for (int i
= 0; i
< 2; i
++) {
3243 fs_reg temp
= vgrf(glsl_type::float_type
);
3244 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3245 fs_reg itemp
= vgrf(glsl_type::int_type
);
3247 bld
.MOV(itemp
, temp
);
3249 /* Clamp the upper end of the range to +7/16.
3250 * ARB_gpu_shader5 requires that we support a maximum offset
3251 * of +0.5, which isn't representable in a S0.4 value -- if
3252 * we didn't clamp it, we'd end up with -8/16, which is the
3253 * opposite of what the shader author wanted.
3255 * This is legal due to ARB_gpu_shader5's quantization
3258 * "Not all values of <offset> may be supported; x and y
3259 * offsets may be rounded to fixed-point values with the
3260 * number of fraction bits given by the
3261 * implementation-dependent constant
3262 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3264 set_condmod(BRW_CONDITIONAL_L
,
3265 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3268 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3269 emit_pixel_interpolater_send(bld
,
3279 case nir_intrinsic_load_interpolated_input
: {
3280 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3281 emit_fragcoord_interpolation(dest
);
3285 assert(instr
->src
[0].ssa
&&
3286 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3287 nir_intrinsic_instr
*bary_intrinsic
=
3288 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3289 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3290 enum glsl_interp_mode interp_mode
=
3291 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3294 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3295 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3296 /* Use the result of the PI message */
3297 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3299 /* Use the delta_xy values computed from the payload */
3300 enum brw_barycentric_mode bary
=
3301 brw_barycentric_mode(interp_mode
, bary_intrin
);
3303 dst_xy
= this->delta_xy
[bary
];
3306 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3308 component(interp_reg(nir_intrinsic_base(instr
),
3309 nir_intrinsic_component(instr
) + i
), 0);
3310 interp
.type
= BRW_REGISTER_TYPE_F
;
3311 dest
.type
= BRW_REGISTER_TYPE_F
;
3313 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3314 fs_reg tmp
= vgrf(glsl_type::float_type
);
3315 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3316 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3318 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3325 nir_emit_intrinsic(bld
, instr
);
3331 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3333 if (nir_src_is_const(instr
->src
[src
])) {
3334 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3337 else if (add_val
== -1)
3345 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3346 nir_intrinsic_instr
*instr
)
3348 assert(stage
== MESA_SHADER_COMPUTE
);
3349 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3352 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3353 dest
= get_nir_dest(instr
->dest
);
3355 switch (instr
->intrinsic
) {
3356 case nir_intrinsic_barrier
:
3358 cs_prog_data
->uses_barrier
= true;
3361 case nir_intrinsic_load_subgroup_id
:
3362 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3365 case nir_intrinsic_load_local_invocation_id
:
3366 case nir_intrinsic_load_work_group_id
: {
3367 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3368 fs_reg val
= nir_system_values
[sv
];
3369 assert(val
.file
!= BAD_FILE
);
3370 dest
.type
= val
.type
;
3371 for (unsigned i
= 0; i
< 3; i
++)
3372 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3376 case nir_intrinsic_load_num_work_groups
: {
3377 const unsigned surface
=
3378 cs_prog_data
->binding_table
.work_groups_start
;
3380 cs_prog_data
->uses_num_work_groups
= true;
3382 fs_reg surf_index
= brw_imm_ud(surface
);
3383 brw_mark_surface_used(prog_data
, surface
);
3385 /* Read the 3 GLuint components of gl_NumWorkGroups */
3386 for (unsigned i
= 0; i
< 3; i
++) {
3387 fs_reg read_result
=
3388 emit_untyped_read(bld
, surf_index
,
3390 1 /* dims */, 1 /* size */,
3391 BRW_PREDICATE_NONE
);
3392 read_result
.type
= dest
.type
;
3393 bld
.MOV(dest
, read_result
);
3394 dest
= offset(dest
, bld
, 1);
3399 case nir_intrinsic_shared_atomic_add
:
3400 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3402 case nir_intrinsic_shared_atomic_imin
:
3403 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3405 case nir_intrinsic_shared_atomic_umin
:
3406 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3408 case nir_intrinsic_shared_atomic_imax
:
3409 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3411 case nir_intrinsic_shared_atomic_umax
:
3412 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3414 case nir_intrinsic_shared_atomic_and
:
3415 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3417 case nir_intrinsic_shared_atomic_or
:
3418 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3420 case nir_intrinsic_shared_atomic_xor
:
3421 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3423 case nir_intrinsic_shared_atomic_exchange
:
3424 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3426 case nir_intrinsic_shared_atomic_comp_swap
:
3427 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3429 case nir_intrinsic_shared_atomic_fmin
:
3430 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3432 case nir_intrinsic_shared_atomic_fmax
:
3433 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3435 case nir_intrinsic_shared_atomic_fcomp_swap
:
3436 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3439 case nir_intrinsic_load_shared
: {
3440 assert(devinfo
->gen
>= 7);
3441 assert(stage
== MESA_SHADER_COMPUTE
);
3443 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3444 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[0]),
3445 BRW_REGISTER_TYPE_UD
);
3447 /* Make dest unsigned because that's what the temporary will be */
3448 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3450 /* Read the vector */
3451 if (nir_intrinsic_align(instr
) >= 4) {
3452 assert(nir_dest_bit_size(instr
->dest
) == 32);
3453 fs_reg read_result
= emit_untyped_read(bld
, brw_imm_ud(GEN7_BTI_SLM
),
3454 offset_reg
, 1 /* dims */,
3455 instr
->num_components
,
3456 BRW_PREDICATE_NONE
);
3457 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
3458 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
3460 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3461 assert(nir_dest_num_components(instr
->dest
) == 1);
3462 fs_reg read_result
=
3463 emit_byte_scattered_read(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
,
3464 1 /* dims */, 1, bit_size
,
3465 BRW_PREDICATE_NONE
);
3466 bld
.MOV(dest
, read_result
);
3471 case nir_intrinsic_store_shared
: {
3472 assert(devinfo
->gen
>= 7);
3473 assert(stage
== MESA_SHADER_COMPUTE
);
3475 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3476 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3477 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[1]),
3478 BRW_REGISTER_TYPE_UD
);
3480 val_reg
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3482 assert(nir_intrinsic_write_mask(instr
) ==
3483 (1u << instr
->num_components
) - 1);
3484 if (nir_intrinsic_align(instr
) >= 4) {
3485 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3486 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3487 emit_untyped_write(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
, val_reg
,
3488 1 /* dims */, instr
->num_components
,
3489 BRW_PREDICATE_NONE
);
3491 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3492 assert(nir_src_num_components(instr
->src
[0]) == 1);
3493 fs_reg write_src
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3494 bld
.MOV(write_src
, val_reg
);
3495 emit_byte_scattered_write(bld
, brw_imm_ud(GEN7_BTI_SLM
), offset_reg
,
3496 write_src
, 1 /* dims */, bit_size
,
3497 BRW_PREDICATE_NONE
);
3503 nir_emit_intrinsic(bld
, instr
);
3509 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3510 nir_op op
, brw_reg_type type
)
3512 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3513 switch (type_sz(type
)) {
3515 assert(type
!= BRW_REGISTER_TYPE_HF
);
3516 return retype(brw_imm_uw(value
.u16
[0]), type
);
3518 return retype(brw_imm_ud(value
.u32
[0]), type
);
3520 if (type
== BRW_REGISTER_TYPE_DF
)
3521 return setup_imm_df(bld
, value
.f64
[0]);
3523 return retype(brw_imm_u64(value
.u64
[0]), type
);
3525 unreachable("Invalid type size");
3530 brw_op_for_nir_reduction_op(nir_op op
)
3533 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3534 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3535 case nir_op_imul
: return BRW_OPCODE_MUL
;
3536 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3537 case nir_op_imin
: return BRW_OPCODE_SEL
;
3538 case nir_op_umin
: return BRW_OPCODE_SEL
;
3539 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3540 case nir_op_imax
: return BRW_OPCODE_SEL
;
3541 case nir_op_umax
: return BRW_OPCODE_SEL
;
3542 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3543 case nir_op_iand
: return BRW_OPCODE_AND
;
3544 case nir_op_ior
: return BRW_OPCODE_OR
;
3545 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3547 unreachable("Invalid reduction operation");
3551 static brw_conditional_mod
3552 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3555 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3556 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3557 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3558 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3559 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3560 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3561 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3562 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3563 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3564 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3565 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3566 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3567 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3569 unreachable("Invalid reduction operation");
3574 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3575 nir_intrinsic_instr
*instr
)
3577 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3579 if (stage_prog_data
->binding_table
.image_start
> 0) {
3580 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3581 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3583 bld
.ADD(image
, image
,
3584 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3588 return bld
.emit_uniformize(image
);
3592 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3593 nir_intrinsic_instr
*instr
)
3595 /* SSBO stores are weird in that their index is in src[1] */
3596 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3599 if (nir_src_is_const(instr
->src
[src
])) {
3600 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3601 nir_src_as_uint(instr
->src
[src
]);
3602 surf_index
= brw_imm_ud(index
);
3603 brw_mark_surface_used(prog_data
, index
);
3605 surf_index
= vgrf(glsl_type::uint_type
);
3606 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3607 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3609 /* Assume this may touch any UBO. It would be nice to provide
3610 * a tighter bound, but the array information is already lowered away.
3612 brw_mark_surface_used(prog_data
,
3613 stage_prog_data
->binding_table
.ssbo_start
+
3614 nir
->info
.num_ssbos
- 1);
3621 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3623 switch (nir_intrinsic_image_dim(instr
)) {
3624 case GLSL_SAMPLER_DIM_1D
:
3625 return 1 + nir_intrinsic_image_array(instr
);
3626 case GLSL_SAMPLER_DIM_2D
:
3627 case GLSL_SAMPLER_DIM_RECT
:
3628 return 2 + nir_intrinsic_image_array(instr
);
3629 case GLSL_SAMPLER_DIM_3D
:
3630 case GLSL_SAMPLER_DIM_CUBE
:
3632 case GLSL_SAMPLER_DIM_BUF
:
3634 case GLSL_SAMPLER_DIM_MS
:
3635 return 2 + nir_intrinsic_image_array(instr
);
3637 unreachable("Invalid image dimension");
3642 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3645 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3646 dest
= get_nir_dest(instr
->dest
);
3648 switch (instr
->intrinsic
) {
3649 case nir_intrinsic_image_load
:
3650 case nir_intrinsic_image_store
:
3651 case nir_intrinsic_image_atomic_add
:
3652 case nir_intrinsic_image_atomic_min
:
3653 case nir_intrinsic_image_atomic_max
:
3654 case nir_intrinsic_image_atomic_and
:
3655 case nir_intrinsic_image_atomic_or
:
3656 case nir_intrinsic_image_atomic_xor
:
3657 case nir_intrinsic_image_atomic_exchange
:
3658 case nir_intrinsic_image_atomic_comp_swap
: {
3659 if (stage
== MESA_SHADER_FRAGMENT
&&
3660 instr
->intrinsic
!= nir_intrinsic_image_load
)
3661 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3663 /* Get some metadata from the image intrinsic. */
3664 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3665 const unsigned dims
= image_intrinsic_coord_components(instr
);
3666 const GLenum format
= nir_intrinsic_format(instr
);
3667 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3669 /* Get the arguments of the image intrinsic. */
3670 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3671 const fs_reg coords
= retype(get_nir_src(instr
->src
[1]),
3672 BRW_REGISTER_TYPE_UD
);
3675 /* Emit an image load, store or atomic op. */
3676 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3677 tmp
= emit_typed_read(bld
, image
, coords
, dims
,
3678 instr
->num_components
);
3679 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3680 const fs_reg src0
= get_nir_src(instr
->src
[3]);
3681 emit_typed_write(bld
, image
, coords
, src0
, dims
,
3682 instr
->num_components
);
3685 unsigned num_srcs
= info
->num_srcs
;
3687 switch (instr
->intrinsic
) {
3688 case nir_intrinsic_image_atomic_add
:
3689 assert(num_srcs
== 4);
3691 op
= get_op_for_atomic_add(instr
, 3);
3693 if (op
!= BRW_AOP_ADD
)
3696 case nir_intrinsic_image_atomic_min
:
3697 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3698 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3700 case nir_intrinsic_image_atomic_max
:
3701 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3702 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3704 case nir_intrinsic_image_atomic_and
:
3707 case nir_intrinsic_image_atomic_or
:
3710 case nir_intrinsic_image_atomic_xor
:
3713 case nir_intrinsic_image_atomic_exchange
:
3716 case nir_intrinsic_image_atomic_comp_swap
:
3720 unreachable("Not reachable.");
3723 const fs_reg src0
= (num_srcs
>= 4 ?
3724 get_nir_src(instr
->src
[3]) : fs_reg());
3725 const fs_reg src1
= (num_srcs
>= 5 ?
3726 get_nir_src(instr
->src
[4]) : fs_reg());
3728 tmp
= emit_typed_atomic(bld
, image
, coords
, src0
, src1
, dims
, 1, op
);
3731 /* Assign the result. */
3732 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3733 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3734 offset(tmp
, bld
, c
));
3739 case nir_intrinsic_image_size
: {
3740 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3741 * into will handle the binding table index for us in the geneerator.
3743 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3744 BRW_REGISTER_TYPE_UD
);
3745 image
= bld
.emit_uniformize(image
);
3747 /* Since the image size is always uniform, we can just emit a SIMD8
3748 * query instruction and splat the result out.
3750 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3752 /* The LOD also serves as the message payload */
3753 fs_reg lod
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3754 ubld
.MOV(lod
, brw_imm_ud(0));
3756 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3757 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE
, tmp
, lod
, image
);
3759 inst
->size_written
= 4 * REG_SIZE
;
3761 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3762 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3763 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3764 offset(retype(dest
, tmp
.type
), bld
, c
),
3765 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3767 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3768 component(offset(tmp
, ubld
, c
), 0));
3774 case nir_intrinsic_image_load_raw_intel
: {
3775 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3776 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3777 BRW_REGISTER_TYPE_UD
);
3779 fs_reg tmp
= emit_untyped_read(bld
, image
, addr
, 1,
3780 instr
->num_components
);
3782 for (unsigned c
= 0; c
< instr
->num_components
; ++c
) {
3783 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3784 offset(tmp
, bld
, c
));
3789 case nir_intrinsic_image_store_raw_intel
: {
3790 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3791 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3792 BRW_REGISTER_TYPE_UD
);
3793 const fs_reg data
= retype(get_nir_src(instr
->src
[2]),
3794 BRW_REGISTER_TYPE_UD
);
3796 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3798 emit_untyped_write(bld
, image
, addr
, data
, 1,
3799 instr
->num_components
);
3803 case nir_intrinsic_group_memory_barrier
:
3804 case nir_intrinsic_memory_barrier_shared
:
3805 case nir_intrinsic_memory_barrier_atomic_counter
:
3806 case nir_intrinsic_memory_barrier_buffer
:
3807 case nir_intrinsic_memory_barrier_image
:
3808 case nir_intrinsic_memory_barrier
: {
3809 const fs_builder ubld
= bld
.group(8, 0);
3810 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3811 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3812 ->size_written
= 2 * REG_SIZE
;
3816 case nir_intrinsic_shader_clock
: {
3817 /* We cannot do anything if there is an event, so ignore it for now */
3818 const fs_reg shader_clock
= get_timestamp(bld
);
3819 const fs_reg srcs
[] = { component(shader_clock
, 0),
3820 component(shader_clock
, 1) };
3821 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3825 case nir_intrinsic_image_samples
:
3826 /* The driver does not support multi-sampled images. */
3827 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3830 case nir_intrinsic_load_uniform
: {
3831 /* Offsets are in bytes but they should always aligned to
3834 assert(instr
->const_index
[0] % 4 == 0 ||
3835 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3837 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3839 if (nir_src_is_const(instr
->src
[0])) {
3840 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3841 assert(load_offset
% type_sz(dest
.type
) == 0);
3842 /* For 16-bit types we add the module of the const_index[0]
3843 * offset to access to not 32-bit aligned element
3845 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
3847 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3848 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3851 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3852 BRW_REGISTER_TYPE_UD
);
3854 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3855 * go past the end of the uniform. In order to keep the n'th
3856 * component from running past, we subtract off the size of all but
3857 * one component of the vector.
3859 assert(instr
->const_index
[1] >=
3860 instr
->num_components
* (int) type_sz(dest
.type
));
3861 unsigned read_size
= instr
->const_index
[1] -
3862 (instr
->num_components
- 1) * type_sz(dest
.type
);
3864 bool supports_64bit_indirects
=
3865 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3867 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3868 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3869 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3870 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3871 indirect
, brw_imm_ud(read_size
));
3874 const unsigned num_mov_indirects
=
3875 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3876 /* We read a little bit less per MOV INDIRECT, as they are now
3877 * 32-bits ones instead of 64-bit. Fix read_size then.
3879 const unsigned read_size_32bit
= read_size
-
3880 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3881 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3882 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3883 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3884 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3885 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3886 indirect
, brw_imm_ud(read_size_32bit
));
3894 case nir_intrinsic_load_ubo
: {
3896 if (nir_src_is_const(instr
->src
[0])) {
3897 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3898 nir_src_as_uint(instr
->src
[0]);
3899 surf_index
= brw_imm_ud(index
);
3900 brw_mark_surface_used(prog_data
, index
);
3902 /* The block index is not a constant. Evaluate the index expression
3903 * per-channel and add the base UBO index; we have to select a value
3904 * from any live channel.
3906 surf_index
= vgrf(glsl_type::uint_type
);
3907 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3908 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3909 surf_index
= bld
.emit_uniformize(surf_index
);
3911 /* Assume this may touch any UBO. It would be nice to provide
3912 * a tighter bound, but the array information is already lowered away.
3914 brw_mark_surface_used(prog_data
,
3915 stage_prog_data
->binding_table
.ubo_start
+
3916 nir
->info
.num_ubos
- 1);
3919 if (!nir_src_is_const(instr
->src
[1])) {
3920 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3921 BRW_REGISTER_TYPE_UD
);
3923 for (int i
= 0; i
< instr
->num_components
; i
++)
3924 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3925 base_offset
, i
* type_sz(dest
.type
));
3927 /* Even if we are loading doubles, a pull constant load will load
3928 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3929 * need to load a full dvec4 we will have to emit 2 loads. This is
3930 * similar to demote_pull_constants(), except that in that case we
3931 * see individual accesses to each component of the vector and then
3932 * we let CSE deal with duplicate loads. Here we see a vector access
3933 * and we have to split it if necessary.
3935 const unsigned type_size
= type_sz(dest
.type
);
3936 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
3938 /* See if we've selected this as a push constant candidate */
3939 if (nir_src_is_const(instr
->src
[0])) {
3940 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
3941 const unsigned offset_256b
= load_offset
/ 32;
3944 for (int i
= 0; i
< 4; i
++) {
3945 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3946 if (range
->block
== ubo_block
&&
3947 offset_256b
>= range
->start
&&
3948 offset_256b
< range
->start
+ range
->length
) {
3950 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3951 push_reg
.offset
= load_offset
- 32 * range
->start
;
3956 if (push_reg
.file
!= BAD_FILE
) {
3957 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3958 bld
.MOV(offset(dest
, bld
, i
),
3959 byte_offset(push_reg
, i
* type_size
));
3965 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3966 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3967 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3969 for (unsigned c
= 0; c
< instr
->num_components
;) {
3970 const unsigned base
= load_offset
+ c
* type_size
;
3971 /* Number of usable components in the next block-aligned load. */
3972 const unsigned count
= MIN2(instr
->num_components
- c
,
3973 (block_sz
- base
% block_sz
) / type_size
);
3975 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3976 packed_consts
, surf_index
,
3977 brw_imm_ud(base
& ~(block_sz
- 1)));
3979 const fs_reg consts
=
3980 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3983 for (unsigned d
= 0; d
< count
; d
++)
3984 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3992 case nir_intrinsic_load_ssbo
: {
3993 assert(devinfo
->gen
>= 7);
3995 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3996 fs_reg surf_index
= get_nir_ssbo_intrinsic_index(bld
, instr
);
3997 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[1]),
3998 BRW_REGISTER_TYPE_UD
);
4000 /* Make dest unsigned because that's what the temporary will be */
4001 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4003 /* Read the vector */
4004 if (nir_intrinsic_align(instr
) >= 4) {
4005 assert(nir_dest_bit_size(instr
->dest
) == 32);
4006 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
4008 instr
->num_components
,
4009 BRW_PREDICATE_NONE
);
4010 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
4011 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
4013 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4014 assert(nir_dest_num_components(instr
->dest
) == 1);
4015 fs_reg read_result
=
4016 emit_byte_scattered_read(bld
, surf_index
, offset_reg
,
4017 1 /* dims */, 1, bit_size
,
4018 BRW_PREDICATE_NONE
);
4019 bld
.MOV(dest
, read_result
);
4024 case nir_intrinsic_store_ssbo
: {
4025 assert(devinfo
->gen
>= 7);
4027 if (stage
== MESA_SHADER_FRAGMENT
)
4028 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4030 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4031 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4032 fs_reg surf_index
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4033 fs_reg offset_reg
= retype(get_nir_src(instr
->src
[2]),
4034 BRW_REGISTER_TYPE_UD
);
4036 val_reg
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4038 assert(nir_intrinsic_write_mask(instr
) ==
4039 (1u << instr
->num_components
) - 1);
4040 if (nir_intrinsic_align(instr
) >= 4) {
4041 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4042 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4043 emit_untyped_write(bld
, surf_index
, offset_reg
, val_reg
,
4044 1 /* dims */, instr
->num_components
,
4045 BRW_PREDICATE_NONE
);
4047 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4048 assert(nir_src_num_components(instr
->src
[0]) == 1);
4049 fs_reg write_src
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4050 bld
.MOV(write_src
, val_reg
);
4051 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4052 write_src
, 1 /* dims */, bit_size
,
4053 BRW_PREDICATE_NONE
);
4058 case nir_intrinsic_store_output
: {
4059 fs_reg src
= get_nir_src(instr
->src
[0]);
4061 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4062 unsigned num_components
= instr
->num_components
;
4063 unsigned first_component
= nir_intrinsic_component(instr
);
4064 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4065 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4066 num_components
*= 2;
4069 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4070 4 * store_offset
), src
.type
);
4071 for (unsigned j
= 0; j
< num_components
; j
++) {
4072 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4073 offset(src
, bld
, j
));
4078 case nir_intrinsic_ssbo_atomic_add
:
4079 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4081 case nir_intrinsic_ssbo_atomic_imin
:
4082 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4084 case nir_intrinsic_ssbo_atomic_umin
:
4085 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4087 case nir_intrinsic_ssbo_atomic_imax
:
4088 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4090 case nir_intrinsic_ssbo_atomic_umax
:
4091 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4093 case nir_intrinsic_ssbo_atomic_and
:
4094 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4096 case nir_intrinsic_ssbo_atomic_or
:
4097 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4099 case nir_intrinsic_ssbo_atomic_xor
:
4100 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4102 case nir_intrinsic_ssbo_atomic_exchange
:
4103 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4105 case nir_intrinsic_ssbo_atomic_comp_swap
:
4106 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4108 case nir_intrinsic_ssbo_atomic_fmin
:
4109 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4111 case nir_intrinsic_ssbo_atomic_fmax
:
4112 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4114 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4115 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4118 case nir_intrinsic_get_buffer_size
: {
4119 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4120 nir_src_as_uint(instr
->src
[0]) : 0;
4122 /* A resinfo's sampler message is used to get the buffer size. The
4123 * SIMD8's writeback message consists of four registers and SIMD16's
4124 * writeback message consists of 8 destination registers (two per each
4125 * component). Because we are only interested on the first channel of
4126 * the first returned component, where resinfo returns the buffer size
4127 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4128 * the dispatch width.
4130 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4131 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4132 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4135 ubld
.MOV(src_payload
, brw_imm_d(0));
4137 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4138 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4139 src_payload
, brw_imm_ud(index
));
4140 inst
->header_size
= 0;
4142 inst
->size_written
= 4 * REG_SIZE
;
4144 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4146 * "Out-of-bounds checking is always performed at a DWord granularity. If
4147 * any part of the DWord is out-of-bounds then the whole DWord is
4148 * considered out-of-bounds."
4150 * This implies that types with size smaller than 4-bytes need to be
4151 * padded if they don't complete the last dword of the buffer. But as we
4152 * need to maintain the original size we need to reverse the padding
4153 * calculation to return the correct size to know the number of elements
4154 * of an unsized array. As we stored in the last two bits of the surface
4155 * size the needed padding for the buffer, we calculate here the
4156 * original buffer_size reversing the surface_size calculation:
4158 * surface_size = isl_align(buffer_size, 4) +
4159 * (isl_align(buffer_size) - buffer_size)
4161 * buffer_size = surface_size & ~3 - surface_size & 3
4164 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4165 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4166 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4168 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4169 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4170 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4172 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4174 brw_mark_surface_used(prog_data
, index
);
4178 case nir_intrinsic_load_subgroup_invocation
:
4179 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4180 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4183 case nir_intrinsic_load_subgroup_eq_mask
:
4184 case nir_intrinsic_load_subgroup_ge_mask
:
4185 case nir_intrinsic_load_subgroup_gt_mask
:
4186 case nir_intrinsic_load_subgroup_le_mask
:
4187 case nir_intrinsic_load_subgroup_lt_mask
:
4188 unreachable("not reached");
4190 case nir_intrinsic_vote_any
: {
4191 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4193 /* The any/all predicates do not consider channel enables. To prevent
4194 * dead channels from affecting the result, we initialize the flag with
4195 * with the identity value for the logical operation.
4197 if (dispatch_width
== 32) {
4198 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4199 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4202 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4204 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4206 /* For some reason, the any/all predicates don't work properly with
4207 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4208 * doesn't read the correct subset of the flag register and you end up
4209 * getting garbage in the second half. Work around this by using a pair
4210 * of 1-wide MOVs and scattering the result.
4212 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4213 ubld
.MOV(res1
, brw_imm_d(0));
4214 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4215 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4216 BRW_PREDICATE_ALIGN1_ANY32H
,
4217 ubld
.MOV(res1
, brw_imm_d(-1)));
4219 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4222 case nir_intrinsic_vote_all
: {
4223 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4225 /* The any/all predicates do not consider channel enables. To prevent
4226 * dead channels from affecting the result, we initialize the flag with
4227 * with the identity value for the logical operation.
4229 if (dispatch_width
== 32) {
4230 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4231 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4232 brw_imm_ud(0xffffffff));
4234 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4236 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4238 /* For some reason, the any/all predicates don't work properly with
4239 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4240 * doesn't read the correct subset of the flag register and you end up
4241 * getting garbage in the second half. Work around this by using a pair
4242 * of 1-wide MOVs and scattering the result.
4244 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4245 ubld
.MOV(res1
, brw_imm_d(0));
4246 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4247 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4248 BRW_PREDICATE_ALIGN1_ALL32H
,
4249 ubld
.MOV(res1
, brw_imm_d(-1)));
4251 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4254 case nir_intrinsic_vote_feq
:
4255 case nir_intrinsic_vote_ieq
: {
4256 fs_reg value
= get_nir_src(instr
->src
[0]);
4257 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4258 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4259 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4262 fs_reg uniformized
= bld
.emit_uniformize(value
);
4263 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4265 /* The any/all predicates do not consider channel enables. To prevent
4266 * dead channels from affecting the result, we initialize the flag with
4267 * with the identity value for the logical operation.
4269 if (dispatch_width
== 32) {
4270 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4271 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4272 brw_imm_ud(0xffffffff));
4274 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4276 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4278 /* For some reason, the any/all predicates don't work properly with
4279 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4280 * doesn't read the correct subset of the flag register and you end up
4281 * getting garbage in the second half. Work around this by using a pair
4282 * of 1-wide MOVs and scattering the result.
4284 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4285 ubld
.MOV(res1
, brw_imm_d(0));
4286 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4287 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4288 BRW_PREDICATE_ALIGN1_ALL32H
,
4289 ubld
.MOV(res1
, brw_imm_d(-1)));
4291 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4295 case nir_intrinsic_ballot
: {
4296 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4297 BRW_REGISTER_TYPE_UD
);
4298 struct brw_reg flag
= brw_flag_reg(0, 0);
4299 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4300 * as f0.0. This is a problem for fragment programs as we currently use
4301 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4302 * programs yet so this isn't a problem. When we do, something will
4305 if (dispatch_width
== 32)
4306 flag
.type
= BRW_REGISTER_TYPE_UD
;
4308 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4309 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4311 if (instr
->dest
.ssa
.bit_size
> 32) {
4312 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4314 dest
.type
= BRW_REGISTER_TYPE_UD
;
4316 bld
.MOV(dest
, flag
);
4320 case nir_intrinsic_read_invocation
: {
4321 const fs_reg value
= get_nir_src(instr
->src
[0]);
4322 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4323 fs_reg tmp
= bld
.vgrf(value
.type
);
4325 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4326 bld
.emit_uniformize(invocation
));
4328 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4332 case nir_intrinsic_read_first_invocation
: {
4333 const fs_reg value
= get_nir_src(instr
->src
[0]);
4334 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4338 case nir_intrinsic_shuffle
: {
4339 const fs_reg value
= get_nir_src(instr
->src
[0]);
4340 const fs_reg index
= get_nir_src(instr
->src
[1]);
4342 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4346 case nir_intrinsic_first_invocation
: {
4347 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4348 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4349 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4350 fs_reg(component(tmp
, 0)));
4354 case nir_intrinsic_quad_broadcast
: {
4355 const fs_reg value
= get_nir_src(instr
->src
[0]);
4356 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4358 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4359 value
, brw_imm_ud(index
), brw_imm_ud(4));
4363 case nir_intrinsic_quad_swap_horizontal
: {
4364 const fs_reg value
= get_nir_src(instr
->src
[0]);
4365 const fs_reg tmp
= bld
.vgrf(value
.type
);
4366 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4368 const fs_reg src_left
= horiz_stride(value
, 2);
4369 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4370 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4371 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4373 ubld
.MOV(tmp_left
, src_right
);
4374 ubld
.MOV(tmp_right
, src_left
);
4376 bld
.MOV(retype(dest
, value
.type
), tmp
);
4380 case nir_intrinsic_quad_swap_vertical
: {
4381 const fs_reg value
= get_nir_src(instr
->src
[0]);
4382 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4383 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4384 const fs_reg tmp
= bld
.vgrf(value
.type
);
4385 const fs_builder ubld
= bld
.exec_all();
4386 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4387 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4388 bld
.MOV(retype(dest
, value
.type
), tmp
);
4390 /* For larger data types, we have to either emit dispatch_width many
4391 * MOVs or else fall back to doing indirects.
4393 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4394 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4396 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4401 case nir_intrinsic_quad_swap_diagonal
: {
4402 const fs_reg value
= get_nir_src(instr
->src
[0]);
4403 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4404 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4405 const fs_reg tmp
= bld
.vgrf(value
.type
);
4406 const fs_builder ubld
= bld
.exec_all();
4407 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4408 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4409 bld
.MOV(retype(dest
, value
.type
), tmp
);
4411 /* For larger data types, we have to either emit dispatch_width many
4412 * MOVs or else fall back to doing indirects.
4414 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4415 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4417 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4422 case nir_intrinsic_reduce
: {
4423 fs_reg src
= get_nir_src(instr
->src
[0]);
4424 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4425 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4426 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4427 cluster_size
= dispatch_width
;
4429 /* Figure out the source type */
4430 src
.type
= brw_type_for_nir_type(devinfo
,
4431 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4432 nir_src_bit_size(instr
->src
[0])));
4434 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4435 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4436 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4438 /* Set up a register for all of our scratching around and initialize it
4439 * to reduction operation's identity value.
4441 fs_reg scan
= bld
.vgrf(src
.type
);
4442 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4444 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4446 dest
.type
= src
.type
;
4447 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4448 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4449 * the distance between clusters is at least 2 GRFs. In this case,
4450 * we don't need the weird striding of the CLUSTER_BROADCAST
4451 * instruction and can just do regular MOVs.
4453 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4454 const unsigned groups
=
4455 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4456 const unsigned group_size
= dispatch_width
/ groups
;
4457 for (unsigned i
= 0; i
< groups
; i
++) {
4458 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4459 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4460 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4461 component(scan
, comp
));
4464 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4465 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4470 case nir_intrinsic_inclusive_scan
:
4471 case nir_intrinsic_exclusive_scan
: {
4472 fs_reg src
= get_nir_src(instr
->src
[0]);
4473 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4475 /* Figure out the source type */
4476 src
.type
= brw_type_for_nir_type(devinfo
,
4477 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4478 nir_src_bit_size(instr
->src
[0])));
4480 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4481 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4482 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4484 /* Set up a register for all of our scratching around and initialize it
4485 * to reduction operation's identity value.
4487 fs_reg scan
= bld
.vgrf(src
.type
);
4488 const fs_builder allbld
= bld
.exec_all();
4489 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4491 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4492 /* Exclusive scan is a bit harder because we have to do an annoying
4493 * shift of the contents before we can begin. To make things worse,
4494 * we can't do this with a normal stride; we have to use indirects.
4496 fs_reg shifted
= bld
.vgrf(src
.type
);
4497 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4498 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4500 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4501 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4505 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4507 bld
.MOV(retype(dest
, src
.type
), scan
);
4511 case nir_intrinsic_begin_invocation_interlock
: {
4512 const fs_builder ubld
= bld
.group(8, 0);
4513 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4515 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4521 case nir_intrinsic_end_invocation_interlock
: {
4522 /* We don't need to do anything here */
4527 unreachable("unknown intrinsic");
4532 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4533 int op
, nir_intrinsic_instr
*instr
)
4535 if (stage
== MESA_SHADER_FRAGMENT
)
4536 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4539 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4540 dest
= get_nir_dest(instr
->dest
);
4542 fs_reg surface
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4543 fs_reg offset
= get_nir_src(instr
->src
[1]);
4545 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4546 data1
= get_nir_src(instr
->src
[2]);
4548 if (op
== BRW_AOP_CMPWR
)
4549 data2
= get_nir_src(instr
->src
[3]);
4551 /* Emit the actual atomic operation */
4553 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4555 1 /* dims */, 1 /* rsize */,
4557 BRW_PREDICATE_NONE
);
4558 dest
.type
= atomic_result
.type
;
4559 bld
.MOV(dest
, atomic_result
);
4563 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4564 int op
, nir_intrinsic_instr
*instr
)
4566 if (stage
== MESA_SHADER_FRAGMENT
)
4567 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4570 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4571 dest
= get_nir_dest(instr
->dest
);
4573 fs_reg surface
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4574 fs_reg offset
= get_nir_src(instr
->src
[1]);
4575 fs_reg data1
= get_nir_src(instr
->src
[2]);
4577 if (op
== BRW_AOP_FCMPWR
)
4578 data2
= get_nir_src(instr
->src
[3]);
4580 /* Emit the actual atomic operation */
4582 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4584 1 /* dims */, 1 /* rsize */,
4586 BRW_PREDICATE_NONE
);
4587 dest
.type
= atomic_result
.type
;
4588 bld
.MOV(dest
, atomic_result
);
4592 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4593 int op
, nir_intrinsic_instr
*instr
)
4596 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4597 dest
= get_nir_dest(instr
->dest
);
4599 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4602 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4603 data1
= get_nir_src(instr
->src
[1]);
4605 if (op
== BRW_AOP_CMPWR
)
4606 data2
= get_nir_src(instr
->src
[2]);
4608 /* Get the offset */
4609 if (nir_src_is_const(instr
->src
[0])) {
4610 offset
= brw_imm_ud(instr
->const_index
[0] +
4611 nir_src_as_uint(instr
->src
[0]));
4613 offset
= vgrf(glsl_type::uint_type
);
4615 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4616 brw_imm_ud(instr
->const_index
[0]));
4619 /* Emit the actual atomic operation operation */
4621 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4623 1 /* dims */, 1 /* rsize */,
4625 BRW_PREDICATE_NONE
);
4626 dest
.type
= atomic_result
.type
;
4627 bld
.MOV(dest
, atomic_result
);
4631 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4632 int op
, nir_intrinsic_instr
*instr
)
4635 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4636 dest
= get_nir_dest(instr
->dest
);
4638 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4640 fs_reg data1
= get_nir_src(instr
->src
[1]);
4642 if (op
== BRW_AOP_FCMPWR
)
4643 data2
= get_nir_src(instr
->src
[2]);
4645 /* Get the offset */
4646 if (nir_src_is_const(instr
->src
[0])) {
4647 offset
= brw_imm_ud(instr
->const_index
[0] +
4648 nir_src_as_uint(instr
->src
[0]));
4650 offset
= vgrf(glsl_type::uint_type
);
4652 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4653 brw_imm_ud(instr
->const_index
[0]));
4656 /* Emit the actual atomic operation operation */
4658 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4660 1 /* dims */, 1 /* rsize */,
4662 BRW_PREDICATE_NONE
);
4663 dest
.type
= atomic_result
.type
;
4664 bld
.MOV(dest
, atomic_result
);
4668 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4670 unsigned texture
= instr
->texture_index
;
4671 unsigned sampler
= instr
->sampler_index
;
4673 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4675 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4676 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4678 int lod_components
= 0;
4680 /* The hardware requires a LOD for buffer textures */
4681 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4682 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4684 uint32_t header_bits
= 0;
4685 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4686 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4687 switch (instr
->src
[i
].src_type
) {
4688 case nir_tex_src_bias
:
4689 srcs
[TEX_LOGICAL_SRC_LOD
] =
4690 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4692 case nir_tex_src_comparator
:
4693 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4695 case nir_tex_src_coord
:
4696 switch (instr
->op
) {
4698 case nir_texop_txf_ms
:
4699 case nir_texop_txf_ms_mcs
:
4700 case nir_texop_samples_identical
:
4701 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4704 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4708 case nir_tex_src_ddx
:
4709 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4710 lod_components
= nir_tex_instr_src_size(instr
, i
);
4712 case nir_tex_src_ddy
:
4713 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4715 case nir_tex_src_lod
:
4716 switch (instr
->op
) {
4718 srcs
[TEX_LOGICAL_SRC_LOD
] =
4719 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4722 srcs
[TEX_LOGICAL_SRC_LOD
] =
4723 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4726 srcs
[TEX_LOGICAL_SRC_LOD
] =
4727 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4731 case nir_tex_src_min_lod
:
4732 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
4733 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4735 case nir_tex_src_ms_index
:
4736 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4739 case nir_tex_src_offset
: {
4740 nir_const_value
*const_offset
=
4741 nir_src_as_const_value(instr
->src
[i
].src
);
4742 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
4743 unsigned offset_bits
= 0;
4745 brw_texture_offset(const_offset
->i32
,
4746 nir_tex_instr_src_size(instr
, i
),
4748 header_bits
|= offset_bits
;
4750 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4751 retype(src
, BRW_REGISTER_TYPE_D
);
4756 case nir_tex_src_projector
:
4757 unreachable("should be lowered");
4759 case nir_tex_src_texture_offset
: {
4760 /* Figure out the highest possible texture index and mark it as used */
4761 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4762 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4763 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4765 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4767 brw_mark_surface_used(prog_data
, max_used
);
4769 /* Emit code to evaluate the actual indexing expression */
4770 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4771 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4772 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4776 case nir_tex_src_sampler_offset
: {
4777 /* Emit code to evaluate the actual indexing expression */
4778 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4779 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4780 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4784 case nir_tex_src_ms_mcs
:
4785 assert(instr
->op
== nir_texop_txf_ms
);
4786 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4789 case nir_tex_src_plane
: {
4790 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
4791 const uint32_t texture_index
=
4792 instr
->texture_index
+
4793 stage_prog_data
->binding_table
.plane_start
[plane
] -
4794 stage_prog_data
->binding_table
.texture_start
;
4796 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4801 unreachable("unknown texture source");
4805 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4806 (instr
->op
== nir_texop_txf_ms
||
4807 instr
->op
== nir_texop_samples_identical
)) {
4808 if (devinfo
->gen
>= 7 &&
4809 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4810 srcs
[TEX_LOGICAL_SRC_MCS
] =
4811 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4812 instr
->coord_components
,
4813 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4815 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4819 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4820 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4823 switch (instr
->op
) {
4825 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4826 SHADER_OPCODE_TXL_LOGICAL
);
4829 opcode
= FS_OPCODE_TXB_LOGICAL
;
4832 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4835 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4838 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4840 case nir_texop_txf_ms
:
4841 if ((key_tex
->msaa_16
& (1 << sampler
)))
4842 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4844 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4846 case nir_texop_txf_ms_mcs
:
4847 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4849 case nir_texop_query_levels
:
4851 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4854 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4857 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4858 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4860 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4862 case nir_texop_texture_samples
:
4863 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4865 case nir_texop_samples_identical
: {
4866 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4868 /* If mcs is an immediate value, it means there is no MCS. In that case
4869 * just return false.
4871 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4872 bld
.MOV(dst
, brw_imm_ud(0u));
4873 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4874 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4875 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4876 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4877 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4879 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4880 BRW_CONDITIONAL_EQ
);
4885 unreachable("unknown texture opcode");
4888 if (instr
->op
== nir_texop_tg4
) {
4889 if (instr
->component
== 1 &&
4890 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4891 /* gather4 sampler is broken for green channel on RG32F --
4892 * we must ask for blue instead.
4894 header_bits
|= 2 << 16;
4896 header_bits
|= instr
->component
<< 16;
4900 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4901 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4902 inst
->offset
= header_bits
;
4904 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4905 if (devinfo
->gen
>= 9 &&
4906 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4907 unsigned write_mask
= instr
->dest
.is_ssa
?
4908 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4909 (1 << dest_size
) - 1;
4910 assert(write_mask
!= 0); /* dead code should have been eliminated */
4911 inst
->size_written
= util_last_bit(write_mask
) *
4912 inst
->dst
.component_size(inst
->exec_size
);
4914 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4917 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4918 inst
->shadow_compare
= true;
4920 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4921 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4924 for (unsigned i
= 0; i
< dest_size
; i
++)
4925 nir_dest
[i
] = offset(dst
, bld
, i
);
4927 if (instr
->op
== nir_texop_query_levels
) {
4928 /* # levels is in .w */
4929 nir_dest
[0] = offset(dst
, bld
, 3);
4930 } else if (instr
->op
== nir_texop_txs
&&
4931 dest_size
>= 3 && devinfo
->gen
< 7) {
4932 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4933 fs_reg depth
= offset(dst
, bld
, 2);
4934 nir_dest
[2] = vgrf(glsl_type::int_type
);
4935 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4938 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4942 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4944 switch (instr
->type
) {
4945 case nir_jump_break
:
4946 bld
.emit(BRW_OPCODE_BREAK
);
4948 case nir_jump_continue
:
4949 bld
.emit(BRW_OPCODE_CONTINUE
);
4951 case nir_jump_return
:
4953 unreachable("unknown jump");
4958 * This helper takes a source register and un/shuffles it into the destination
4961 * If source type size is smaller than destination type size the operation
4962 * needed is a component shuffle. The opposite case would be an unshuffle. If
4963 * source/destination type size is equal a shuffle is done that would be
4964 * equivalent to a simple MOV.
4966 * For example, if source is a 16-bit type and destination is 32-bit. A 3
4967 * components .xyz 16-bit vector on SIMD8 would be.
4969 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
4970 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
4972 * This helper will return the following 2 32-bit components with the 16-bit
4975 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
4976 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
4978 * For unshuffle, the example would be the opposite, a 64-bit type source
4979 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
4982 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
4983 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
4984 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
4985 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
4987 * The returned result would be the following 4 32-bit components unshuffled:
4989 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
4990 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
4991 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
4992 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
4994 * - Source and destination register must not be overlapped.
4995 * - components units are measured in terms of the smaller type between
4996 * source and destination because we are un/shuffling the smaller
4997 * components from/into the bigger ones.
4998 * - first_component parameter allows skipping source components.
5001 shuffle_src_to_dst(const fs_builder
&bld
,
5004 uint32_t first_component
,
5005 uint32_t components
)
5007 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5008 assert(!regions_overlap(dst
,
5009 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5010 offset(src
, bld
, first_component
),
5011 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5012 for (unsigned i
= 0; i
< components
; i
++) {
5013 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5014 offset(src
, bld
, i
+ first_component
));
5016 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5017 /* Source is shuffled into destination */
5018 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5019 assert(!regions_overlap(dst
,
5020 type_sz(dst
.type
) * bld
.dispatch_width() *
5021 DIV_ROUND_UP(components
, size_ratio
),
5022 offset(src
, bld
, first_component
),
5023 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5025 brw_reg_type shuffle_type
=
5026 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5027 BRW_REGISTER_TYPE_D
);
5028 for (unsigned i
= 0; i
< components
; i
++) {
5029 fs_reg shuffle_component_i
=
5030 subscript(offset(dst
, bld
, i
/ size_ratio
),
5031 shuffle_type
, i
% size_ratio
);
5032 bld
.MOV(shuffle_component_i
,
5033 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5036 /* Source is unshuffled into destination */
5037 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5038 assert(!regions_overlap(dst
,
5039 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5040 offset(src
, bld
, first_component
/ size_ratio
),
5041 type_sz(src
.type
) * bld
.dispatch_width() *
5042 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5045 brw_reg_type shuffle_type
=
5046 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5047 BRW_REGISTER_TYPE_D
);
5048 for (unsigned i
= 0; i
< components
; i
++) {
5049 fs_reg shuffle_component_i
=
5050 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5051 shuffle_type
, (first_component
+ i
) % size_ratio
);
5052 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5053 shuffle_component_i
);
5059 shuffle_from_32bit_read(const fs_builder
&bld
,
5062 uint32_t first_component
,
5063 uint32_t components
)
5065 assert(type_sz(src
.type
) == 4);
5067 /* This function takes components in units of the destination type while
5068 * shuffle_src_to_dst takes components in units of the smallest type
5070 if (type_sz(dst
.type
) > 4) {
5071 assert(type_sz(dst
.type
) == 8);
5072 first_component
*= 2;
5076 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5080 shuffle_for_32bit_write(const fs_builder
&bld
,
5082 uint32_t first_component
,
5083 uint32_t components
)
5085 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5086 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5087 /* This function takes components in units of the source type while
5088 * shuffle_src_to_dst takes components in units of the smallest type
5090 if (type_sz(src
.type
) > 4) {
5091 assert(type_sz(src
.type
) == 8);
5092 first_component
*= 2;
5096 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5102 setup_imm_df(const fs_builder
&bld
, double v
)
5104 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5105 assert(devinfo
->gen
>= 7);
5107 if (devinfo
->gen
>= 8)
5108 return brw_imm_df(v
);
5110 /* gen7.5 does not support DF immediates straighforward but the DIM
5111 * instruction allows to set the 64-bit immediate value.
5113 if (devinfo
->is_haswell
) {
5114 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5115 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5116 ubld
.DIM(dst
, brw_imm_df(v
));
5117 return component(dst
, 0);
5120 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5121 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5122 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5124 * Alternatively, we could also produce a normal VGRF (without stride 0)
5125 * by writing to all the channels in the VGRF, however, that would hit the
5126 * gen7 bug where we have to split writes that span more than 1 register
5127 * into instructions with a width of 4 (otherwise the write to the second
5128 * register written runs into an execmask hardware bug) which isn't very
5141 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5142 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5143 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5144 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5146 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5150 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5152 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5153 bld
.MOV(tmp
, brw_imm_w(v
));
5158 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5160 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5161 bld
.MOV(tmp
, brw_imm_uw(v
));