2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "util/u_math.h"
28 #include "util/bitscan.h"
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
46 fs_visitor::nir_setup_outputs()
48 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
51 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
53 /* Calculate the size of output registers in a separate pass, before
54 * allocating them. With ARB_enhanced_layouts, multiple output variables
55 * may occupy the same slot, but have different type sizes.
57 nir_foreach_variable(var
, &nir
->outputs
) {
58 const int loc
= var
->data
.driver_location
;
59 const unsigned var_vec4s
=
60 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
61 : type_size_vec4(var
->type
, true);
62 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
65 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
66 if (vec4s
[loc
] == 0) {
71 unsigned reg_size
= vec4s
[loc
];
73 /* Check if there are any ranges that start within this range and extend
74 * past it. If so, include them in this allocation.
76 for (unsigned i
= 1; i
< reg_size
; i
++)
77 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
79 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
80 for (unsigned i
= 0; i
< reg_size
; i
++)
81 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
88 fs_visitor::nir_setup_uniforms()
90 /* Only the first compile gets to set up uniforms. */
91 if (push_constant_loc
) {
92 assert(pull_constant_loc
);
96 uniforms
= nir
->num_uniforms
/ 4;
98 if (stage
== MESA_SHADER_COMPUTE
) {
99 /* Add a uniform for the thread local id. It must be the last uniform
102 assert(uniforms
== prog_data
->nr_params
);
103 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
104 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
105 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
110 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
114 nir_foreach_instr(instr
, block
) {
115 if (instr
->type
!= nir_instr_type_intrinsic
)
118 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
119 switch (intrin
->intrinsic
) {
120 case nir_intrinsic_load_vertex_id
:
121 case nir_intrinsic_load_base_vertex
:
122 unreachable("should be lowered by nir_lower_system_values().");
124 case nir_intrinsic_load_vertex_id_zero_base
:
125 case nir_intrinsic_load_is_indexed_draw
:
126 case nir_intrinsic_load_first_vertex
:
127 case nir_intrinsic_load_instance_id
:
128 case nir_intrinsic_load_base_instance
:
129 case nir_intrinsic_load_draw_id
:
130 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
132 case nir_intrinsic_load_invocation_id
:
133 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
135 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
136 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
137 if (reg
->file
== BAD_FILE
) {
138 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
139 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
140 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
141 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
146 case nir_intrinsic_load_sample_pos
:
147 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
148 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
149 if (reg
->file
== BAD_FILE
)
150 *reg
= *v
->emit_samplepos_setup();
153 case nir_intrinsic_load_sample_id
:
154 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_sampleid_setup();
160 case nir_intrinsic_load_sample_mask_in
:
161 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
162 assert(v
->devinfo
->gen
>= 7);
163 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
164 if (reg
->file
== BAD_FILE
)
165 *reg
= *v
->emit_samplemaskin_setup();
168 case nir_intrinsic_load_work_group_id
:
169 assert(v
->stage
== MESA_SHADER_COMPUTE
);
170 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
171 if (reg
->file
== BAD_FILE
)
172 *reg
= *v
->emit_cs_work_group_id_setup();
175 case nir_intrinsic_load_helper_invocation
:
176 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
177 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
178 if (reg
->file
== BAD_FILE
) {
179 const fs_builder abld
=
180 v
->bld
.annotate("gl_HelperInvocation", NULL
);
182 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
183 * pixel mask is in g1.7 of the thread payload.
185 * We move the per-channel pixel enable bit to the low bit of each
186 * channel by shifting the byte containing the pixel mask by the
187 * vector immediate 0x76543210UV.
189 * The region of <1,8,0> reads only 1 byte (the pixel masks for
190 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
191 * masks for 2 and 3) in SIMD16.
193 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
195 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
196 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
197 hbld
.SHR(offset(shifted
, hbld
, i
),
198 stride(retype(brw_vec1_grf(1 + i
, 7),
199 BRW_REGISTER_TYPE_UB
),
201 brw_imm_v(0x76543210));
204 /* A set bit in the pixel mask means the channel is enabled, but
205 * that is the opposite of gl_HelperInvocation so we need to invert
208 * The negate source-modifier bit of logical instructions on Gen8+
209 * performs 1's complement negation, so we can use that instead of
212 fs_reg inverted
= negate(shifted
);
213 if (v
->devinfo
->gen
< 8) {
214 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
215 abld
.NOT(inverted
, shifted
);
218 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
219 * with 1 and negating.
221 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
222 abld
.AND(anded
, inverted
, brw_imm_uw(1));
224 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
225 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
239 fs_visitor::nir_emit_system_values()
241 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
242 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
243 nir_system_values
[i
] = fs_reg();
246 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
247 * never end up using it.
250 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
251 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
252 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
254 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
255 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
256 if (dispatch_width
> 8)
257 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
258 if (dispatch_width
> 16) {
259 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
260 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
264 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
265 nir_foreach_block(block
, impl
)
266 emit_system_values_block(block
, this);
270 * Returns a type based on a reference_type (word, float, half-float) and a
273 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
275 * @FIXME: 64-bit return types are always DF on integer types to maintain
276 * compability with uses of DF previously to the introduction of int64
280 brw_reg_type_from_bit_size(const unsigned bit_size
,
281 const brw_reg_type reference_type
)
283 switch(reference_type
) {
284 case BRW_REGISTER_TYPE_HF
:
285 case BRW_REGISTER_TYPE_F
:
286 case BRW_REGISTER_TYPE_DF
:
289 return BRW_REGISTER_TYPE_HF
;
291 return BRW_REGISTER_TYPE_F
;
293 return BRW_REGISTER_TYPE_DF
;
295 unreachable("Invalid bit size");
297 case BRW_REGISTER_TYPE_B
:
298 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_D
:
300 case BRW_REGISTER_TYPE_Q
:
303 return BRW_REGISTER_TYPE_B
;
305 return BRW_REGISTER_TYPE_W
;
307 return BRW_REGISTER_TYPE_D
;
309 return BRW_REGISTER_TYPE_Q
;
311 unreachable("Invalid bit size");
313 case BRW_REGISTER_TYPE_UB
:
314 case BRW_REGISTER_TYPE_UW
:
315 case BRW_REGISTER_TYPE_UD
:
316 case BRW_REGISTER_TYPE_UQ
:
319 return BRW_REGISTER_TYPE_UB
;
321 return BRW_REGISTER_TYPE_UW
;
323 return BRW_REGISTER_TYPE_UD
;
325 return BRW_REGISTER_TYPE_UQ
;
327 unreachable("Invalid bit size");
330 unreachable("Unknown type");
335 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
337 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
338 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
339 nir_locals
[i
] = fs_reg();
342 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
343 unsigned array_elems
=
344 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
345 unsigned size
= array_elems
* reg
->num_components
;
346 const brw_reg_type reg_type
=
347 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
348 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
351 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
354 nir_emit_cf_list(&impl
->body
);
358 fs_visitor::nir_emit_cf_list(exec_list
*list
)
360 exec_list_validate(list
);
361 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
362 switch (node
->type
) {
364 nir_emit_if(nir_cf_node_as_if(node
));
367 case nir_cf_node_loop
:
368 nir_emit_loop(nir_cf_node_as_loop(node
));
371 case nir_cf_node_block
:
372 nir_emit_block(nir_cf_node_as_block(node
));
376 unreachable("Invalid CFG node block");
382 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
387 /* If the condition has the form !other_condition, use other_condition as
388 * the source, but invert the predicate on the if instruction.
390 nir_alu_instr
*const cond
= nir_src_as_alu_instr(&if_stmt
->condition
);
391 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
392 assert(!cond
->src
[0].negate
);
393 assert(!cond
->src
[0].abs
);
396 cond_reg
= get_nir_src(cond
->src
[0].src
);
399 cond_reg
= get_nir_src(if_stmt
->condition
);
402 /* first, put the condition into f0 */
403 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
404 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
405 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
407 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
409 nir_emit_cf_list(&if_stmt
->then_list
);
411 /* note: if the else is empty, dead CF elimination will remove it */
412 bld
.emit(BRW_OPCODE_ELSE
);
414 nir_emit_cf_list(&if_stmt
->else_list
);
416 bld
.emit(BRW_OPCODE_ENDIF
);
418 if (devinfo
->gen
< 7)
419 limit_dispatch_width(16, "Non-uniform control flow unsupported "
424 fs_visitor::nir_emit_loop(nir_loop
*loop
)
426 bld
.emit(BRW_OPCODE_DO
);
428 nir_emit_cf_list(&loop
->body
);
430 bld
.emit(BRW_OPCODE_WHILE
);
432 if (devinfo
->gen
< 7)
433 limit_dispatch_width(16, "Non-uniform control flow unsupported "
438 fs_visitor::nir_emit_block(nir_block
*block
)
440 nir_foreach_instr(instr
, block
) {
441 nir_emit_instr(instr
);
446 fs_visitor::nir_emit_instr(nir_instr
*instr
)
448 const fs_builder abld
= bld
.annotate(NULL
, instr
);
450 switch (instr
->type
) {
451 case nir_instr_type_alu
:
452 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
455 case nir_instr_type_deref
:
456 /* Derefs can exist for images but they do nothing */
459 case nir_instr_type_intrinsic
:
461 case MESA_SHADER_VERTEX
:
462 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
464 case MESA_SHADER_TESS_CTRL
:
465 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
467 case MESA_SHADER_TESS_EVAL
:
468 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
470 case MESA_SHADER_GEOMETRY
:
471 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
473 case MESA_SHADER_FRAGMENT
:
474 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
476 case MESA_SHADER_COMPUTE
:
477 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
480 unreachable("unsupported shader stage");
484 case nir_instr_type_tex
:
485 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
488 case nir_instr_type_load_const
:
489 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
492 case nir_instr_type_ssa_undef
:
493 /* We create a new VGRF for undefs on every use (by handling
494 * them in get_nir_src()), rather than for each definition.
495 * This helps register coalescing eliminate MOVs from undef.
499 case nir_instr_type_jump
:
500 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
504 unreachable("unknown instruction type");
509 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
513 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
514 const fs_reg
&result
)
516 if (!instr
->src
[0].src
.is_ssa
||
517 !instr
->src
[0].src
.ssa
->parent_instr
)
520 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
523 nir_alu_instr
*src0
=
524 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
526 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
527 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
530 /* If either opcode has source modifiers, bail.
532 * TODO: We can potentially handle source modifiers if both of the opcodes
533 * we're combining are signed integers.
535 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
536 src0
->src
[0].abs
|| src0
->src
[0].negate
)
539 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
541 /* Element type to extract.*/
542 const brw_reg_type type
= brw_int_type(
543 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
544 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
546 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
547 op0
.type
= brw_type_for_nir_type(devinfo
,
548 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
549 nir_src_bit_size(src0
->src
[0].src
)));
550 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
552 set_saturate(instr
->dest
.saturate
,
553 bld
.MOV(result
, subscript(op0
, type
, element
)));
558 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
559 const fs_reg
&result
)
561 if (!instr
->src
[0].src
.is_ssa
||
562 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
565 nir_intrinsic_instr
*src0
=
566 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
568 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
571 if (!nir_src_is_const(instr
->src
[1].src
) ||
572 !nir_src_is_const(instr
->src
[2].src
))
575 const float value1
= nir_src_as_float(instr
->src
[1].src
);
576 const float value2
= nir_src_as_float(instr
->src
[2].src
);
577 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
580 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
581 assert(value1
== -value2
);
583 fs_reg tmp
= vgrf(glsl_type::int_type
);
585 if (devinfo
->gen
>= 6) {
586 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
587 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
589 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
591 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
592 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
594 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
596 * This negation looks like it's safe in practice, because bits 0:4 will
597 * surely be TRIANGLES
600 if (value1
== -1.0f
) {
604 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
605 g0
, brw_imm_uw(0x3f80));
607 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
608 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
610 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
612 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
613 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
615 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
617 * This negation looks like it's safe in practice, because bits 0:4 will
618 * surely be TRIANGLES
621 if (value1
== -1.0f
) {
625 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
627 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
633 emit_find_msb_using_lzd(const fs_builder
&bld
,
634 const fs_reg
&result
,
642 /* LZD of an absolute value source almost always does the right
643 * thing. There are two problem values:
645 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
646 * 0. However, findMSB(int(0x80000000)) == 30.
648 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
649 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
651 * For a value of zero or negative one, -1 will be returned.
653 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
654 * findMSB(-(1<<x)) should return x-1.
656 * For all negative number cases, including 0x80000000 and
657 * 0xffffffff, the correct value is obtained from LZD if instead of
658 * negating the (already negative) value the logical-not is used. A
659 * conditonal logical-not can be achieved in two instructions.
661 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
663 bld
.ASR(temp
, src
, brw_imm_d(31));
664 bld
.XOR(temp
, temp
, src
);
667 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
668 retype(temp
, BRW_REGISTER_TYPE_UD
));
670 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
671 * from the LSB side. Subtract the result from 31 to convert the MSB
672 * count into an LSB count. If no bits are set, LZD will return 32.
673 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
675 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
676 inst
->src
[0].negate
= true;
680 brw_rnd_mode_from_nir_op (const nir_op op
) {
682 case nir_op_f2f16_rtz
:
683 return BRW_RND_MODE_RTZ
;
684 case nir_op_f2f16_rtne
:
685 return BRW_RND_MODE_RTNE
;
687 unreachable("Operation doesn't support rounding mode");
692 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
693 nir_alu_instr
*instr
,
698 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
700 result
.type
= brw_type_for_nir_type(devinfo
,
701 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
702 nir_dest_bit_size(instr
->dest
.dest
)));
704 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
705 op
[i
] = get_nir_src(instr
->src
[i
].src
);
706 op
[i
].type
= brw_type_for_nir_type(devinfo
,
707 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
708 nir_src_bit_size(instr
->src
[i
].src
)));
709 op
[i
].abs
= instr
->src
[i
].abs
;
710 op
[i
].negate
= instr
->src
[i
].negate
;
713 /* Move and vecN instrutions may still be vectored. Return the raw,
714 * vectored source and destination so that fs_visitor::nir_emit_alu can
715 * handle it. Other callers should not have to handle these kinds of
729 /* At this point, we have dealt with any instruction that operates on
730 * more than a single channel. Therefore, we can just adjust the source
731 * and destination registers for that channel and emit the instruction.
733 unsigned channel
= 0;
734 if (nir_op_infos
[instr
->op
].output_size
== 0) {
735 /* Since NIR is doing the scalarizing for us, we should only ever see
736 * vectorized operations with a single channel.
738 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
739 channel
= ffs(instr
->dest
.write_mask
) - 1;
741 result
= offset(result
, bld
, channel
);
744 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
745 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
746 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
753 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
756 for (unsigned i
= 0; i
< 2; i
++) {
757 nir_alu_instr
*const inot_instr
=
758 nir_src_as_alu_instr(&instr
->src
[i
].src
);
760 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
761 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
762 /* The source of the inot is now the source of instr. */
763 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
765 assert(!op
[i
].negate
);
768 op
[i
] = resolve_source_modifiers(op
[i
]);
774 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
776 nir_alu_instr
*instr
)
778 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
781 nir_alu_instr
*const inot_instr
= nir_src_as_alu_instr(&instr
->src
[0].src
);
783 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
786 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
787 * of valid size-changing combinations is a bit more complex.
789 * The source restriction is just because I was lazy about generating the
792 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
793 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
796 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
797 * this is float(1 + a).
801 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
803 /* Ignore the saturate modifier, if there is one. The result of the
804 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
806 bld
.ADD(result
, op
, brw_imm_d(1));
812 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
814 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
818 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, true);
826 fs_reg temp
= result
;
827 bool need_extra_copy
= false;
828 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
829 if (!instr
->src
[i
].src
.is_ssa
&&
830 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
831 need_extra_copy
= true;
832 temp
= bld
.vgrf(result
.type
, 4);
837 for (unsigned i
= 0; i
< 4; i
++) {
838 if (!(instr
->dest
.write_mask
& (1 << i
)))
841 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
842 inst
= bld
.MOV(offset(temp
, bld
, i
),
843 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
845 inst
= bld
.MOV(offset(temp
, bld
, i
),
846 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
848 inst
->saturate
= instr
->dest
.saturate
;
851 /* In this case the source and destination registers were the same,
852 * so we need to insert an extra set of moves in order to deal with
855 if (need_extra_copy
) {
856 for (unsigned i
= 0; i
< 4; i
++) {
857 if (!(instr
->dest
.write_mask
& (1 << i
)))
860 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
868 if (optimize_extract_to_float(instr
, result
))
870 inst
= bld
.MOV(result
, op
[0]);
871 inst
->saturate
= instr
->dest
.saturate
;
874 case nir_op_f2f16_rtne
:
875 case nir_op_f2f16_rtz
:
876 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
877 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
880 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
881 * on the HW gen, it is a special hw opcode or just a MOV, and
882 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
884 * But if we want to use that opcode, we need to provide support on
885 * different optimizations and lowerings. As right now HF support is
886 * only for gen8+, it will be better to use directly the MOV, and use
887 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
893 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
894 inst
= bld
.MOV(result
, op
[0]);
895 inst
->saturate
= instr
->dest
.saturate
;
901 assert(type_sz(op
[0].type
) > 2); /* brw_nir_lower_conversions */
902 inst
= bld
.MOV(result
, op
[0]);
903 inst
->saturate
= instr
->dest
.saturate
;
913 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
915 op
[0].type
= BRW_REGISTER_TYPE_D
;
916 op
[0].negate
= !op
[0].negate
;
922 assert(type_sz(op
[0].type
) > 1); /* brw_nir_lower_conversions */
935 inst
= bld
.MOV(result
, op
[0]);
936 inst
->saturate
= instr
->dest
.saturate
;
940 assert(!instr
->dest
.saturate
);
942 /* Straightforward since the source can be assumed to be either
943 * strictly >= 0 or strictly <= 0 depending on the setting of the
946 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
948 inst
= (op
[0].negate
)
949 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
950 : bld
.MOV(result
, brw_imm_f(1.0f
));
952 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
953 } else if (type_sz(op
[0].type
) < 8) {
954 /* AND(val, 0x80000000) gives the sign bit.
956 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
959 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
961 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
962 op
[0].type
= BRW_REGISTER_TYPE_UD
;
963 result
.type
= BRW_REGISTER_TYPE_UD
;
964 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
966 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
967 inst
->predicate
= BRW_PREDICATE_NORMAL
;
969 /* For doubles we do the same but we need to consider:
971 * - 2-src instructions can't operate with 64-bit immediates
972 * - The sign is encoded in the high 32-bit of each DF
973 * - We need to produce a DF result.
976 fs_reg zero
= vgrf(glsl_type::double_type
);
977 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
978 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
980 bld
.MOV(result
, zero
);
982 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
983 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
984 brw_imm_ud(0x80000000u
));
986 set_predicate(BRW_PREDICATE_NORMAL
,
987 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
993 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
994 inst
->saturate
= instr
->dest
.saturate
;
998 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
999 inst
->saturate
= instr
->dest
.saturate
;
1003 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1004 inst
->saturate
= instr
->dest
.saturate
;
1008 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1009 inst
->saturate
= instr
->dest
.saturate
;
1013 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1014 inst
->saturate
= instr
->dest
.saturate
;
1018 if (fs_key
->high_quality_derivatives
) {
1019 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1021 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1023 inst
->saturate
= instr
->dest
.saturate
;
1025 case nir_op_fddx_fine
:
1026 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1027 inst
->saturate
= instr
->dest
.saturate
;
1029 case nir_op_fddx_coarse
:
1030 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1031 inst
->saturate
= instr
->dest
.saturate
;
1034 if (fs_key
->high_quality_derivatives
) {
1035 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1037 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1039 inst
->saturate
= instr
->dest
.saturate
;
1041 case nir_op_fddy_fine
:
1042 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1043 inst
->saturate
= instr
->dest
.saturate
;
1045 case nir_op_fddy_coarse
:
1046 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1047 inst
->saturate
= instr
->dest
.saturate
;
1052 inst
= bld
.ADD(result
, op
[0], op
[1]);
1053 inst
->saturate
= instr
->dest
.saturate
;
1056 case nir_op_uadd_sat
:
1057 inst
= bld
.ADD(result
, op
[0], op
[1]);
1058 inst
->saturate
= true;
1062 inst
= bld
.MUL(result
, op
[0], op
[1]);
1063 inst
->saturate
= instr
->dest
.saturate
;
1066 case nir_op_imul_2x32_64
:
1067 case nir_op_umul_2x32_64
:
1068 bld
.MUL(result
, op
[0], op
[1]);
1072 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1073 bld
.MUL(result
, op
[0], op
[1]);
1076 case nir_op_imul_high
:
1077 case nir_op_umul_high
:
1078 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1079 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1084 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1085 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1088 case nir_op_uadd_carry
:
1089 unreachable("Should have been lowered by carry_to_arith().");
1091 case nir_op_usub_borrow
:
1092 unreachable("Should have been lowered by borrow_to_arith().");
1096 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1097 * appears that our hardware just does the right thing for signed
1100 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1101 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1105 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1106 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1108 /* Math instructions don't support conditional mod */
1109 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1110 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1112 /* Now, we need to determine if signs of the sources are different.
1113 * When we XOR the sources, the top bit is 0 if they are the same and 1
1114 * if they are different. We can then use a conditional modifier to
1115 * turn that into a predicate. This leads us to an XOR.l instruction.
1117 * Technically, according to the PRM, you're not allowed to use .l on a
1118 * XOR instruction. However, emperical experiments and Curro's reading
1119 * of the simulator source both indicate that it's safe.
1121 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1122 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1123 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1124 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1126 /* If the result of the initial remainder operation is non-zero and the
1127 * two sources have different signs, add in a copy of op[1] to get the
1128 * final integer modulus value.
1130 inst
= bld
.ADD(result
, result
, op
[1]);
1131 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1138 case nir_op_fne32
: {
1139 fs_reg dest
= result
;
1141 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1143 dest
= bld
.vgrf(op
[0].type
, 1);
1145 brw_conditional_mod cond
;
1146 switch (instr
->op
) {
1148 cond
= BRW_CONDITIONAL_L
;
1151 cond
= BRW_CONDITIONAL_GE
;
1154 cond
= BRW_CONDITIONAL_Z
;
1157 cond
= BRW_CONDITIONAL_NZ
;
1160 unreachable("bad opcode");
1163 bld
.CMP(dest
, op
[0], op
[1], cond
);
1165 if (bit_size
> 32) {
1166 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1167 } else if(bit_size
< 32) {
1168 /* When we convert the result to 32-bit we need to be careful and do
1169 * it as a signed conversion to get sign extension (for 32-bit true)
1171 const brw_reg_type src_type
=
1172 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1174 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1184 case nir_op_ine32
: {
1185 fs_reg dest
= result
;
1187 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1189 dest
= bld
.vgrf(op
[0].type
, 1);
1191 brw_conditional_mod cond
;
1192 switch (instr
->op
) {
1195 cond
= BRW_CONDITIONAL_L
;
1199 cond
= BRW_CONDITIONAL_GE
;
1202 cond
= BRW_CONDITIONAL_Z
;
1205 cond
= BRW_CONDITIONAL_NZ
;
1208 unreachable("bad opcode");
1210 bld
.CMP(dest
, op
[0], op
[1], cond
);
1212 if (bit_size
> 32) {
1213 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1214 } else if (bit_size
< 32) {
1215 /* When we convert the result to 32-bit we need to be careful and do
1216 * it as a signed conversion to get sign extension (for 32-bit true)
1218 const brw_reg_type src_type
=
1219 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1221 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1227 if (devinfo
->gen
>= 8) {
1228 nir_alu_instr
*const inot_src_instr
=
1229 nir_src_as_alu_instr(&instr
->src
[0].src
);
1231 if (inot_src_instr
!= NULL
&&
1232 (inot_src_instr
->op
== nir_op_ior
||
1233 inot_src_instr
->op
== nir_op_ixor
||
1234 inot_src_instr
->op
== nir_op_iand
) &&
1235 !inot_src_instr
->src
[0].abs
&&
1236 !inot_src_instr
->src
[0].negate
&&
1237 !inot_src_instr
->src
[1].abs
&&
1238 !inot_src_instr
->src
[1].negate
) {
1239 /* The sources of the source logical instruction are now the
1240 * sources of the instruction that will be generated.
1242 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1243 resolve_inot_sources(bld
, inot_src_instr
, op
);
1245 /* Smash all of the sources and destination to be signed. This
1246 * doesn't matter for the operation of the instruction, but cmod
1247 * propagation fails on unsigned sources with negation (due to
1248 * fs_inst::can_do_cmod returning false).
1251 brw_type_for_nir_type(devinfo
,
1252 (nir_alu_type
)(nir_type_int
|
1253 nir_dest_bit_size(instr
->dest
.dest
)));
1255 brw_type_for_nir_type(devinfo
,
1256 (nir_alu_type
)(nir_type_int
|
1257 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1259 brw_type_for_nir_type(devinfo
,
1260 (nir_alu_type
)(nir_type_int
|
1261 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1263 /* For XOR, only invert one of the sources. Arbitrarily choose
1266 op
[0].negate
= !op
[0].negate
;
1267 if (inot_src_instr
->op
!= nir_op_ixor
)
1268 op
[1].negate
= !op
[1].negate
;
1270 switch (inot_src_instr
->op
) {
1272 bld
.AND(result
, op
[0], op
[1]);
1276 bld
.OR(result
, op
[0], op
[1]);
1280 bld
.XOR(result
, op
[0], op
[1]);
1284 unreachable("impossible opcode");
1287 op
[0] = resolve_source_modifiers(op
[0]);
1289 bld
.NOT(result
, op
[0]);
1292 if (devinfo
->gen
>= 8) {
1293 resolve_inot_sources(bld
, instr
, op
);
1295 bld
.XOR(result
, op
[0], op
[1]);
1298 if (devinfo
->gen
>= 8) {
1299 resolve_inot_sources(bld
, instr
, op
);
1301 bld
.OR(result
, op
[0], op
[1]);
1304 if (devinfo
->gen
>= 8) {
1305 resolve_inot_sources(bld
, instr
, op
);
1307 bld
.AND(result
, op
[0], op
[1]);
1313 case nir_op_b32all_fequal2
:
1314 case nir_op_b32all_iequal2
:
1315 case nir_op_b32all_fequal3
:
1316 case nir_op_b32all_iequal3
:
1317 case nir_op_b32all_fequal4
:
1318 case nir_op_b32all_iequal4
:
1319 case nir_op_b32any_fnequal2
:
1320 case nir_op_b32any_inequal2
:
1321 case nir_op_b32any_fnequal3
:
1322 case nir_op_b32any_inequal3
:
1323 case nir_op_b32any_fnequal4
:
1324 case nir_op_b32any_inequal4
:
1325 unreachable("Lowered by nir_lower_alu_reductions");
1327 case nir_op_fnoise1_1
:
1328 case nir_op_fnoise1_2
:
1329 case nir_op_fnoise1_3
:
1330 case nir_op_fnoise1_4
:
1331 case nir_op_fnoise2_1
:
1332 case nir_op_fnoise2_2
:
1333 case nir_op_fnoise2_3
:
1334 case nir_op_fnoise2_4
:
1335 case nir_op_fnoise3_1
:
1336 case nir_op_fnoise3_2
:
1337 case nir_op_fnoise3_3
:
1338 case nir_op_fnoise3_4
:
1339 case nir_op_fnoise4_1
:
1340 case nir_op_fnoise4_2
:
1341 case nir_op_fnoise4_3
:
1342 case nir_op_fnoise4_4
:
1343 unreachable("not reached: should be handled by lower_noise");
1346 unreachable("not reached: should be handled by ldexp_to_arith()");
1349 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1350 inst
->saturate
= instr
->dest
.saturate
;
1354 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1355 inst
->saturate
= instr
->dest
.saturate
;
1359 case nir_op_f2b32
: {
1360 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1361 if (bit_size
== 64) {
1362 /* two-argument instructions can't take 64-bit immediates */
1366 if (instr
->op
== nir_op_f2b32
) {
1367 zero
= vgrf(glsl_type::double_type
);
1368 tmp
= vgrf(glsl_type::double_type
);
1369 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1371 zero
= vgrf(glsl_type::int64_t_type
);
1372 tmp
= vgrf(glsl_type::int64_t_type
);
1373 bld
.MOV(zero
, brw_imm_q(0));
1376 /* A SIMD16 execution needs to be split in two instructions, so use
1377 * a vgrf instead of the flag register as dst so instruction splitting
1380 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1381 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1384 if (bit_size
== 32) {
1385 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1387 assert(bit_size
== 16);
1388 zero
= instr
->op
== nir_op_f2b32
?
1389 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1391 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1397 inst
= bld
.RNDZ(result
, op
[0]);
1398 inst
->saturate
= instr
->dest
.saturate
;
1401 case nir_op_fceil
: {
1402 op
[0].negate
= !op
[0].negate
;
1403 fs_reg temp
= vgrf(glsl_type::float_type
);
1404 bld
.RNDD(temp
, op
[0]);
1406 inst
= bld
.MOV(result
, temp
);
1407 inst
->saturate
= instr
->dest
.saturate
;
1411 inst
= bld
.RNDD(result
, op
[0]);
1412 inst
->saturate
= instr
->dest
.saturate
;
1415 inst
= bld
.FRC(result
, op
[0]);
1416 inst
->saturate
= instr
->dest
.saturate
;
1418 case nir_op_fround_even
:
1419 inst
= bld
.RNDE(result
, op
[0]);
1420 inst
->saturate
= instr
->dest
.saturate
;
1423 case nir_op_fquantize2f16
: {
1424 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1425 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1426 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1428 /* The destination stride must be at least as big as the source stride. */
1429 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1432 /* Check for denormal */
1433 fs_reg abs_src0
= op
[0];
1434 abs_src0
.abs
= true;
1435 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1437 /* Get the appropriately signed zero */
1438 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1439 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1440 brw_imm_ud(0x80000000));
1441 /* Do the actual F32 -> F16 -> F32 conversion */
1442 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1443 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1444 /* Select that or zero based on normal status */
1445 inst
= bld
.SEL(result
, zero
, tmp32
);
1446 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1447 inst
->saturate
= instr
->dest
.saturate
;
1454 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1455 inst
->saturate
= instr
->dest
.saturate
;
1461 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1462 inst
->saturate
= instr
->dest
.saturate
;
1465 case nir_op_pack_snorm_2x16
:
1466 case nir_op_pack_snorm_4x8
:
1467 case nir_op_pack_unorm_2x16
:
1468 case nir_op_pack_unorm_4x8
:
1469 case nir_op_unpack_snorm_2x16
:
1470 case nir_op_unpack_snorm_4x8
:
1471 case nir_op_unpack_unorm_2x16
:
1472 case nir_op_unpack_unorm_4x8
:
1473 case nir_op_unpack_half_2x16
:
1474 case nir_op_pack_half_2x16
:
1475 unreachable("not reached: should be handled by lower_packing_builtins");
1477 case nir_op_unpack_half_2x16_split_x
:
1478 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1479 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1480 inst
->saturate
= instr
->dest
.saturate
;
1482 case nir_op_unpack_half_2x16_split_y
:
1483 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1484 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1485 inst
->saturate
= instr
->dest
.saturate
;
1488 case nir_op_pack_64_2x32_split
:
1489 case nir_op_pack_32_2x16_split
:
1490 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1493 case nir_op_unpack_64_2x32_split_x
:
1494 case nir_op_unpack_64_2x32_split_y
: {
1495 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1496 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1498 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1502 case nir_op_unpack_32_2x16_split_x
:
1503 case nir_op_unpack_32_2x16_split_y
: {
1504 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1505 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1507 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1512 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1513 inst
->saturate
= instr
->dest
.saturate
;
1516 case nir_op_bitfield_reverse
:
1517 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1518 bld
.BFREV(result
, op
[0]);
1521 case nir_op_bit_count
:
1522 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1523 bld
.CBIT(result
, op
[0]);
1526 case nir_op_ufind_msb
: {
1527 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1528 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1532 case nir_op_ifind_msb
: {
1533 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1535 if (devinfo
->gen
< 7) {
1536 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1538 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1540 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1541 * count from the LSB side. If FBH didn't return an error
1542 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1543 * count into an LSB count.
1545 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1547 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1548 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1549 inst
->src
[0].negate
= true;
1554 case nir_op_find_lsb
:
1555 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1557 if (devinfo
->gen
< 7) {
1558 fs_reg temp
= vgrf(glsl_type::int_type
);
1560 /* (x & -x) generates a value that consists of only the LSB of x.
1561 * For all powers of 2, findMSB(y) == findLSB(y).
1563 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1564 fs_reg negated_src
= src
;
1566 /* One must be negated, and the other must be non-negated. It
1567 * doesn't matter which is which.
1569 negated_src
.negate
= true;
1572 bld
.AND(temp
, src
, negated_src
);
1573 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1575 bld
.FBL(result
, op
[0]);
1579 case nir_op_ubitfield_extract
:
1580 case nir_op_ibitfield_extract
:
1581 unreachable("should have been lowered");
1584 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1585 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1588 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1589 bld
.BFI1(result
, op
[0], op
[1]);
1592 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1593 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1596 case nir_op_bitfield_insert
:
1597 unreachable("not reached: should have been lowered");
1600 bld
.SHL(result
, op
[0], op
[1]);
1603 bld
.ASR(result
, op
[0], op
[1]);
1606 bld
.SHR(result
, op
[0], op
[1]);
1609 case nir_op_pack_half_2x16_split
:
1610 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1614 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1615 inst
->saturate
= instr
->dest
.saturate
;
1619 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1620 inst
->saturate
= instr
->dest
.saturate
;
1623 case nir_op_b32csel
:
1624 if (optimize_frontfacing_ternary(instr
, result
))
1627 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1628 inst
= bld
.SEL(result
, op
[1], op
[2]);
1629 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1632 case nir_op_extract_u8
:
1633 case nir_op_extract_i8
: {
1634 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1639 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1640 * Use two instructions and a word or DWord intermediate integer type.
1642 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1643 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1645 if (instr
->op
== nir_op_extract_i8
) {
1646 /* If we need to sign extend, extract to a word first */
1647 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1648 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1649 bld
.MOV(result
, w_temp
);
1650 } else if (byte
& 1) {
1651 /* Extract the high byte from the word containing the desired byte
1655 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1658 /* Otherwise use an AND with 0xff and a word type */
1660 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1664 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1665 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1670 case nir_op_extract_u16
:
1671 case nir_op_extract_i16
: {
1672 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1673 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1674 bld
.MOV(result
, subscript(op
[0], type
, word
));
1679 unreachable("unhandled instruction");
1682 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1683 * to sign extend the low bit to 0/~0
1685 if (devinfo
->gen
<= 5 &&
1686 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1687 fs_reg masked
= vgrf(glsl_type::int_type
);
1688 bld
.AND(masked
, result
, brw_imm_d(1));
1689 masked
.negate
= true;
1690 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1695 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1696 nir_load_const_instr
*instr
)
1698 const brw_reg_type reg_type
=
1699 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1700 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1702 switch (instr
->def
.bit_size
) {
1704 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1705 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1709 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1710 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1714 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1715 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1719 assert(devinfo
->gen
>= 7);
1720 if (devinfo
->gen
== 7) {
1721 /* We don't get 64-bit integer types until gen8 */
1722 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1723 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1724 setup_imm_df(bld
, instr
->value
[i
].f64
));
1727 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1728 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1733 unreachable("Invalid bit size");
1736 nir_ssa_values
[instr
->def
.index
] = reg
;
1740 fs_visitor::get_nir_src(const nir_src
&src
)
1744 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1745 const brw_reg_type reg_type
=
1746 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1747 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1749 reg
= nir_ssa_values
[src
.ssa
->index
];
1752 /* We don't handle indirects on locals */
1753 assert(src
.reg
.indirect
== NULL
);
1754 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1755 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1758 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1759 /* The only 64-bit type available on gen7 is DF, so use that. */
1760 reg
.type
= BRW_REGISTER_TYPE_DF
;
1762 /* To avoid floating-point denorm flushing problems, set the type by
1763 * default to an integer type - instructions that need floating point
1764 * semantics will set this to F if they need to
1766 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1767 BRW_REGISTER_TYPE_D
);
1774 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1776 * This function should not be called on any value which may be 64 bits.
1777 * We could theoretically support 64-bit on gen8+ but we choose not to
1778 * because it wouldn't work in general (no gen7 support) and there are
1779 * enough restrictions in 64-bit immediates that you can't take the return
1780 * value and treat it the same as the result of get_nir_src().
1783 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1785 assert(nir_src_bit_size(src
) == 32);
1786 return nir_src_is_const(src
) ?
1787 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1791 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1794 const brw_reg_type reg_type
=
1795 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1796 dest
.ssa
.bit_size
== 8 ?
1797 BRW_REGISTER_TYPE_D
:
1798 BRW_REGISTER_TYPE_F
);
1799 nir_ssa_values
[dest
.ssa
.index
] =
1800 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1801 return nir_ssa_values
[dest
.ssa
.index
];
1803 /* We don't handle indirects on locals */
1804 assert(dest
.reg
.indirect
== NULL
);
1805 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1806 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1811 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1814 for (unsigned i
= 0; i
< 4; i
++) {
1815 if (!((wr_mask
>> i
) & 1))
1818 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1819 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1820 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1821 if (new_inst
->src
[j
].file
== VGRF
)
1822 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1829 emit_pixel_interpolater_send(const fs_builder
&bld
,
1834 glsl_interp_mode interpolation
)
1836 struct brw_wm_prog_data
*wm_prog_data
=
1837 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1839 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1840 /* 2 floats per slot returned */
1841 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1842 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1844 wm_prog_data
->pulls_bary
= true;
1850 * Computes 1 << x, given a D/UD register containing some value x.
1853 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1855 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1857 fs_reg result
= bld
.vgrf(x
.type
, 1);
1858 fs_reg one
= bld
.vgrf(x
.type
, 1);
1860 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1861 bld
.SHL(result
, one
, x
);
1866 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1868 assert(stage
== MESA_SHADER_GEOMETRY
);
1870 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1872 if (gs_compile
->control_data_header_size_bits
== 0)
1875 /* We can only do EndPrimitive() functionality when the control data
1876 * consists of cut bits. Fortunately, the only time it isn't is when the
1877 * output type is points, in which case EndPrimitive() is a no-op.
1879 if (gs_prog_data
->control_data_format
!=
1880 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1884 /* Cut bits use one bit per vertex. */
1885 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1887 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1888 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1890 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1891 * vertex n, 0 otherwise. So all we need to do here is mark bit
1892 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1893 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1894 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1896 * Note that if EndPrimitive() is called before emitting any vertices, this
1897 * will cause us to set bit 31 of the control_data_bits register to 1.
1898 * That's fine because:
1900 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1901 * output, so the hardware will ignore cut bit 31.
1903 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1904 * last vertex, so setting cut bit 31 has no effect (since the primitive
1905 * is automatically ended when the GS terminates).
1907 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1908 * control_data_bits register to 0 when the first vertex is emitted.
1911 const fs_builder abld
= bld
.annotate("end primitive");
1913 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1914 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1915 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1916 fs_reg mask
= intexp2(abld
, prev_count
);
1917 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1918 * attention to the lower 5 bits of its second source argument, so on this
1919 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1920 * ((vertex_count - 1) % 32).
1922 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1926 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1928 assert(stage
== MESA_SHADER_GEOMETRY
);
1929 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1931 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1933 const fs_builder abld
= bld
.annotate("emit control data bits");
1934 const fs_builder fwa_bld
= bld
.exec_all();
1936 /* We use a single UD register to accumulate control data bits (32 bits
1937 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1940 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1941 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1942 * use the Channel Mask phase to enable/disable which DWord within that
1943 * group to write. (Remember, different SIMD8 channels may have emitted
1944 * different numbers of vertices, so we may need per-slot offsets.)
1946 * Channel masking presents an annoying problem: we may have to replicate
1947 * the data up to 4 times:
1949 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1951 * To avoid penalizing shaders that emit a small number of vertices, we
1952 * can avoid these sometimes: if the size of the control data header is
1953 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1954 * land in the same 128-bit group, so we can skip per-slot offsets.
1956 * Similarly, if the control data header is <= 32 bits, there is only one
1957 * DWord, so we can skip channel masks.
1959 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1961 fs_reg channel_mask
, per_slot_offset
;
1963 if (gs_compile
->control_data_header_size_bits
> 32) {
1964 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1965 channel_mask
= vgrf(glsl_type::uint_type
);
1968 if (gs_compile
->control_data_header_size_bits
> 128) {
1969 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1970 per_slot_offset
= vgrf(glsl_type::uint_type
);
1973 /* Figure out which DWord we're trying to write to using the formula:
1975 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1977 * Since bits_per_vertex is a power of two, and is known at compile
1978 * time, this can be optimized to:
1980 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1982 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1983 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1984 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1985 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1986 unsigned log2_bits_per_vertex
=
1987 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1988 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1990 if (per_slot_offset
.file
!= BAD_FILE
) {
1991 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1992 * the appropriate OWord within the control data header.
1994 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1997 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1998 * write to the appropriate DWORD within the OWORD.
2000 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2001 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2002 channel_mask
= intexp2(fwa_bld
, channel
);
2003 /* Then the channel masks need to be in bits 23:16. */
2004 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2007 /* Store the control data bits in the message payload and send it. */
2009 if (channel_mask
.file
!= BAD_FILE
)
2010 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2011 if (per_slot_offset
.file
!= BAD_FILE
)
2014 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2015 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2017 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2018 if (per_slot_offset
.file
!= BAD_FILE
)
2019 sources
[i
++] = per_slot_offset
;
2020 if (channel_mask
.file
!= BAD_FILE
)
2021 sources
[i
++] = channel_mask
;
2023 sources
[i
++] = this->control_data_bits
;
2026 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2027 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2029 /* We need to increment Global Offset by 256-bits to make room for
2030 * Broadwell's extra "Vertex Count" payload at the beginning of the
2031 * URB entry. Since this is an OWord message, Global Offset is counted
2032 * in 128-bit units, so we must set it to 2.
2034 if (gs_prog_data
->static_vertex_count
== -1)
2039 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2042 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2044 /* Note: we are calling this *before* increasing vertex_count, so
2045 * this->vertex_count == vertex_count - 1 in the formula above.
2048 /* Stream mode uses 2 bits per vertex */
2049 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2051 /* Must be a valid stream */
2052 assert(stream_id
< MAX_VERTEX_STREAMS
);
2054 /* Control data bits are initialized to 0 so we don't have to set any
2055 * bits when sending vertices to stream 0.
2060 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2062 /* reg::sid = stream_id */
2063 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2064 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2066 /* reg:shift_count = 2 * (vertex_count - 1) */
2067 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2068 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2070 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2071 * attention to the lower 5 bits of its second source argument, so on this
2072 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2073 * stream_id << ((2 * (vertex_count - 1)) % 32).
2075 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2076 abld
.SHL(mask
, sid
, shift_count
);
2077 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2081 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2084 assert(stage
== MESA_SHADER_GEOMETRY
);
2086 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2088 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2089 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2091 /* Haswell and later hardware ignores the "Render Stream Select" bits
2092 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2093 * and instead sends all primitives down the pipeline for rasterization.
2094 * If the SOL stage is enabled, "Render Stream Select" is honored and
2095 * primitives bound to non-zero streams are discarded after stream output.
2097 * Since the only purpose of primives sent to non-zero streams is to
2098 * be recorded by transform feedback, we can simply discard all geometry
2099 * bound to these streams when transform feedback is disabled.
2101 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2104 /* If we're outputting 32 control data bits or less, then we can wait
2105 * until the shader is over to output them all. Otherwise we need to
2106 * output them as we go. Now is the time to do it, since we're about to
2107 * output the vertex_count'th vertex, so it's guaranteed that the
2108 * control data bits associated with the (vertex_count - 1)th vertex are
2111 if (gs_compile
->control_data_header_size_bits
> 32) {
2112 const fs_builder abld
=
2113 bld
.annotate("emit vertex: emit control data bits");
2115 /* Only emit control data bits if we've finished accumulating a batch
2116 * of 32 bits. This is the case when:
2118 * (vertex_count * bits_per_vertex) % 32 == 0
2120 * (in other words, when the last 5 bits of vertex_count *
2121 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2122 * integer n (which is always the case, since bits_per_vertex is
2123 * always 1 or 2), this is equivalent to requiring that the last 5-n
2124 * bits of vertex_count are 0:
2126 * vertex_count & (2^(5-n) - 1) == 0
2128 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2131 * vertex_count & (32 / bits_per_vertex - 1) == 0
2133 * TODO: If vertex_count is an immediate, we could do some of this math
2134 * at compile time...
2137 abld
.AND(bld
.null_reg_d(), vertex_count
,
2138 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2139 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2141 abld
.IF(BRW_PREDICATE_NORMAL
);
2142 /* If vertex_count is 0, then no control data bits have been
2143 * accumulated yet, so we can skip emitting them.
2145 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2146 BRW_CONDITIONAL_NEQ
);
2147 abld
.IF(BRW_PREDICATE_NORMAL
);
2148 emit_gs_control_data_bits(vertex_count
);
2149 abld
.emit(BRW_OPCODE_ENDIF
);
2151 /* Reset control_data_bits to 0 so we can start accumulating a new
2154 * Note: in the case where vertex_count == 0, this neutralizes the
2155 * effect of any call to EndPrimitive() that the shader may have
2156 * made before outputting its first vertex.
2158 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2159 inst
->force_writemask_all
= true;
2160 abld
.emit(BRW_OPCODE_ENDIF
);
2163 emit_urb_writes(vertex_count
);
2165 /* In stream mode we have to set control data bits for all vertices
2166 * unless we have disabled control data bits completely (which we do
2167 * do for GL_POINTS outputs that don't use streams).
2169 if (gs_compile
->control_data_header_size_bits
> 0 &&
2170 gs_prog_data
->control_data_format
==
2171 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2172 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2177 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2178 const nir_src
&vertex_src
,
2179 unsigned base_offset
,
2180 const nir_src
&offset_src
,
2181 unsigned num_components
,
2182 unsigned first_component
)
2184 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2185 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2187 /* TODO: figure out push input layout for invocations == 1 */
2188 /* TODO: make this work with 64-bit inputs */
2189 if (gs_prog_data
->invocations
== 1 &&
2190 type_sz(dst
.type
) <= 4 &&
2191 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2192 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2193 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2194 nir_src_as_uint(vertex_src
) * push_reg_count
;
2195 for (unsigned i
= 0; i
< num_components
; i
++) {
2196 bld
.MOV(offset(dst
, bld
, i
),
2197 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2202 /* Resort to the pull model. Ensure the VUE handles are provided. */
2203 assert(gs_prog_data
->base
.include_vue_handles
);
2205 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2206 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2208 if (gs_prog_data
->invocations
== 1) {
2209 if (nir_src_is_const(vertex_src
)) {
2210 /* The vertex index is constant; just select the proper URB handle. */
2212 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2213 BRW_REGISTER_TYPE_UD
);
2215 /* The vertex index is non-constant. We need to use indirect
2216 * addressing to fetch the proper URB handle.
2218 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2219 * indicating that channel <n> should read the handle from
2220 * DWord <n>. We convert that to bytes by multiplying by 4.
2222 * Next, we convert the vertex index to bytes by multiplying
2223 * by 32 (shifting by 5), and add the two together. This is
2224 * the final indirect byte offset.
2226 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2227 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2228 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2229 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2231 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2232 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2233 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2234 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2235 /* Convert vertex_index to bytes (multiply by 32) */
2236 bld
.SHL(vertex_offset_bytes
,
2237 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2239 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2241 /* Use first_icp_handle as the base offset. There is one register
2242 * of URB handles per vertex, so inform the register allocator that
2243 * we might read up to nir->info.gs.vertices_in registers.
2245 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2246 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2247 fs_reg(icp_offset_bytes
),
2248 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2251 assert(gs_prog_data
->invocations
> 1);
2253 if (nir_src_is_const(vertex_src
)) {
2254 unsigned vertex
= nir_src_as_uint(vertex_src
);
2255 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2257 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2258 BRW_REGISTER_TYPE_UD
));
2260 /* The vertex index is non-constant. We need to use indirect
2261 * addressing to fetch the proper URB handle.
2264 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2266 /* Convert vertex_index to bytes (multiply by 4) */
2267 bld
.SHL(icp_offset_bytes
,
2268 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2271 /* Use first_icp_handle as the base offset. There is one DWord
2272 * of URB handles per vertex, so inform the register allocator that
2273 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2275 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2276 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2277 fs_reg(icp_offset_bytes
),
2278 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2285 fs_reg tmp_dst
= dst
;
2286 fs_reg indirect_offset
= get_nir_src(offset_src
);
2287 unsigned num_iterations
= 1;
2288 unsigned orig_num_components
= num_components
;
2290 if (type_sz(dst
.type
) == 8) {
2291 if (num_components
> 2) {
2295 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2297 first_component
= first_component
/ 2;
2300 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2301 if (nir_src_is_const(offset_src
)) {
2302 /* Constant indexing - use global offset. */
2303 if (first_component
!= 0) {
2304 unsigned read_components
= num_components
+ first_component
;
2305 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2306 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2307 inst
->size_written
= read_components
*
2308 tmp
.component_size(inst
->exec_size
);
2309 for (unsigned i
= 0; i
< num_components
; i
++) {
2310 bld
.MOV(offset(tmp_dst
, bld
, i
),
2311 offset(tmp
, bld
, i
+ first_component
));
2314 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2316 inst
->size_written
= num_components
*
2317 tmp_dst
.component_size(inst
->exec_size
);
2319 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2322 /* Indirect indexing - use per-slot offsets as well. */
2323 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2324 unsigned read_components
= num_components
+ first_component
;
2325 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2326 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2327 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2328 if (first_component
!= 0) {
2329 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2331 inst
->size_written
= read_components
*
2332 tmp
.component_size(inst
->exec_size
);
2333 for (unsigned i
= 0; i
< num_components
; i
++) {
2334 bld
.MOV(offset(tmp_dst
, bld
, i
),
2335 offset(tmp
, bld
, i
+ first_component
));
2338 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2340 inst
->size_written
= num_components
*
2341 tmp_dst
.component_size(inst
->exec_size
);
2343 inst
->offset
= base_offset
;
2347 if (type_sz(dst
.type
) == 8) {
2348 shuffle_from_32bit_read(bld
,
2349 offset(dst
, bld
, iter
* 2),
2350 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2355 if (num_iterations
> 1) {
2356 num_components
= orig_num_components
- 2;
2357 if(nir_src_is_const(offset_src
)) {
2360 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2361 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2362 indirect_offset
= new_indirect
;
2369 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2371 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2373 if (nir_src_is_const(*offset_src
)) {
2374 /* The only constant offset we should find is 0. brw_nir.c's
2375 * add_const_offset_to_base() will fold other constant offsets
2376 * into instr->const_index[0].
2378 assert(nir_src_as_uint(*offset_src
) == 0);
2382 return get_nir_src(*offset_src
);
2386 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2387 nir_intrinsic_instr
*instr
)
2389 assert(stage
== MESA_SHADER_VERTEX
);
2392 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2393 dest
= get_nir_dest(instr
->dest
);
2395 switch (instr
->intrinsic
) {
2396 case nir_intrinsic_load_vertex_id
:
2397 case nir_intrinsic_load_base_vertex
:
2398 unreachable("should be lowered by nir_lower_system_values()");
2400 case nir_intrinsic_load_input
: {
2401 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2402 unsigned first_component
= nir_intrinsic_component(instr
);
2403 unsigned num_components
= instr
->num_components
;
2405 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2407 if (type_sz(dest
.type
) == 8)
2408 first_component
/= 2;
2410 /* For 16-bit support maybe a temporary will be needed to copy from
2413 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2414 first_component
, num_components
);
2418 case nir_intrinsic_load_vertex_id_zero_base
:
2419 case nir_intrinsic_load_instance_id
:
2420 case nir_intrinsic_load_base_instance
:
2421 case nir_intrinsic_load_draw_id
:
2422 case nir_intrinsic_load_first_vertex
:
2423 case nir_intrinsic_load_is_indexed_draw
:
2424 unreachable("lowered by brw_nir_lower_vs_inputs");
2427 nir_emit_intrinsic(bld
, instr
);
2433 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2434 nir_intrinsic_instr
*instr
)
2436 assert(stage
== MESA_SHADER_TESS_CTRL
);
2437 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2438 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2441 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2442 dst
= get_nir_dest(instr
->dest
);
2444 switch (instr
->intrinsic
) {
2445 case nir_intrinsic_load_primitive_id
:
2446 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2448 case nir_intrinsic_load_invocation_id
:
2449 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2451 case nir_intrinsic_load_patch_vertices_in
:
2452 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2453 brw_imm_d(tcs_key
->input_vertices
));
2456 case nir_intrinsic_barrier
: {
2457 if (tcs_prog_data
->instances
== 1)
2460 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2461 fs_reg m0_2
= component(m0
, 2);
2463 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2465 /* Zero the message header */
2466 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2468 if (devinfo
->gen
< 11) {
2469 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2470 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2471 brw_imm_ud(INTEL_MASK(16, 13)));
2473 /* Shift it up to bits 27:24. */
2474 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2476 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2477 brw_imm_ud(INTEL_MASK(30, 24)));
2480 /* Set the Barrier Count and the enable bit */
2481 if (devinfo
->gen
< 11) {
2482 chanbld
.OR(m0_2
, m0_2
,
2483 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2485 chanbld
.OR(m0_2
, m0_2
,
2486 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2489 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2493 case nir_intrinsic_load_input
:
2494 unreachable("nir_lower_io should never give us these.");
2497 case nir_intrinsic_load_per_vertex_input
: {
2498 fs_reg indirect_offset
= get_indirect_offset(instr
);
2499 unsigned imm_offset
= instr
->const_index
[0];
2501 const nir_src
&vertex_src
= instr
->src
[0];
2507 if (nir_src_is_const(vertex_src
)) {
2508 /* Emit a MOV to resolve <0,1,0> regioning. */
2509 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2510 unsigned vertex
= nir_src_as_uint(vertex_src
);
2512 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2513 BRW_REGISTER_TYPE_UD
));
2514 } else if (tcs_prog_data
->instances
== 1 &&
2515 vertex_src
.is_ssa
&&
2516 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2517 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2518 /* For the common case of only 1 instance, an array index of
2519 * gl_InvocationID means reading g1. Skip all the indirect work.
2521 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2523 /* The vertex index is non-constant. We need to use indirect
2524 * addressing to fetch the proper URB handle.
2526 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2528 /* Each ICP handle is a single DWord (4 bytes) */
2529 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2530 bld
.SHL(vertex_offset_bytes
,
2531 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2534 /* Start at g1. We might read up to 4 registers. */
2535 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2536 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2537 brw_imm_ud(4 * REG_SIZE
));
2540 /* We can only read two double components with each URB read, so
2541 * we send two read messages in that case, each one loading up to
2542 * two double components.
2544 unsigned num_iterations
= 1;
2545 unsigned num_components
= instr
->num_components
;
2546 unsigned first_component
= nir_intrinsic_component(instr
);
2547 fs_reg orig_dst
= dst
;
2548 if (type_sz(dst
.type
) == 8) {
2549 first_component
= first_component
/ 2;
2550 if (instr
->num_components
> 2) {
2555 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2559 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2560 if (indirect_offset
.file
== BAD_FILE
) {
2561 /* Constant indexing - use global offset. */
2562 if (first_component
!= 0) {
2563 unsigned read_components
= num_components
+ first_component
;
2564 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2565 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2566 for (unsigned i
= 0; i
< num_components
; i
++) {
2567 bld
.MOV(offset(dst
, bld
, i
),
2568 offset(tmp
, bld
, i
+ first_component
));
2571 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2573 inst
->offset
= imm_offset
;
2576 /* Indirect indexing - use per-slot offsets as well. */
2577 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2578 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2579 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2580 if (first_component
!= 0) {
2581 unsigned read_components
= num_components
+ first_component
;
2582 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2583 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2585 for (unsigned i
= 0; i
< num_components
; i
++) {
2586 bld
.MOV(offset(dst
, bld
, i
),
2587 offset(tmp
, bld
, i
+ first_component
));
2590 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2593 inst
->offset
= imm_offset
;
2596 inst
->size_written
= (num_components
+ first_component
) *
2597 inst
->dst
.component_size(inst
->exec_size
);
2599 /* If we are reading 64-bit data using 32-bit read messages we need
2600 * build proper 64-bit data elements by shuffling the low and high
2601 * 32-bit components around like we do for other things like UBOs
2604 if (type_sz(dst
.type
) == 8) {
2605 shuffle_from_32bit_read(bld
,
2606 offset(orig_dst
, bld
, iter
* 2),
2607 retype(dst
, BRW_REGISTER_TYPE_D
),
2611 /* Copy the temporary to the destination to deal with writemasking.
2613 * Also attempt to deal with gl_PointSize being in the .w component.
2615 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2616 assert(type_sz(dst
.type
) < 8);
2617 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2618 inst
->size_written
= 4 * REG_SIZE
;
2619 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2622 /* If we are loading double data and we need a second read message
2623 * adjust the write offset
2625 if (num_iterations
> 1) {
2626 num_components
= instr
->num_components
- 2;
2633 case nir_intrinsic_load_output
:
2634 case nir_intrinsic_load_per_vertex_output
: {
2635 fs_reg indirect_offset
= get_indirect_offset(instr
);
2636 unsigned imm_offset
= instr
->const_index
[0];
2637 unsigned first_component
= nir_intrinsic_component(instr
);
2640 if (indirect_offset
.file
== BAD_FILE
) {
2641 /* Replicate the patch handle to all enabled channels */
2642 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2643 bld
.MOV(patch_handle
,
2644 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2647 if (first_component
!= 0) {
2648 unsigned read_components
=
2649 instr
->num_components
+ first_component
;
2650 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2651 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2653 inst
->size_written
= read_components
* REG_SIZE
;
2654 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2655 bld
.MOV(offset(dst
, bld
, i
),
2656 offset(tmp
, bld
, i
+ first_component
));
2659 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2661 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2663 inst
->offset
= imm_offset
;
2667 /* Indirect indexing - use per-slot offsets as well. */
2668 const fs_reg srcs
[] = {
2669 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2672 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2673 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2674 if (first_component
!= 0) {
2675 unsigned read_components
=
2676 instr
->num_components
+ first_component
;
2677 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2678 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2680 inst
->size_written
= read_components
* REG_SIZE
;
2681 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2682 bld
.MOV(offset(dst
, bld
, i
),
2683 offset(tmp
, bld
, i
+ first_component
));
2686 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2688 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2690 inst
->offset
= imm_offset
;
2696 case nir_intrinsic_store_output
:
2697 case nir_intrinsic_store_per_vertex_output
: {
2698 fs_reg value
= get_nir_src(instr
->src
[0]);
2699 bool is_64bit
= (instr
->src
[0].is_ssa
?
2700 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2701 fs_reg indirect_offset
= get_indirect_offset(instr
);
2702 unsigned imm_offset
= instr
->const_index
[0];
2703 unsigned mask
= instr
->const_index
[1];
2704 unsigned header_regs
= 0;
2706 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2708 if (indirect_offset
.file
!= BAD_FILE
) {
2709 srcs
[header_regs
++] = indirect_offset
;
2715 unsigned num_components
= util_last_bit(mask
);
2718 /* We can only pack two 64-bit components in a single message, so send
2719 * 2 messages if we have more components
2721 unsigned num_iterations
= 1;
2722 unsigned iter_components
= num_components
;
2723 unsigned first_component
= nir_intrinsic_component(instr
);
2725 first_component
= first_component
/ 2;
2726 if (instr
->num_components
> 2) {
2728 iter_components
= 2;
2732 mask
= mask
<< first_component
;
2734 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2735 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2736 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2737 opcode
= indirect_offset
.file
!= BAD_FILE
?
2738 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2739 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2740 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2741 /* Expand the 64-bit mask to 32-bit channels. We only handle
2742 * two channels in each iteration, so we only care about X/Y.
2744 unsigned mask32
= 0;
2745 if (mask
& WRITEMASK_X
)
2746 mask32
|= WRITEMASK_XY
;
2747 if (mask
& WRITEMASK_Y
)
2748 mask32
|= WRITEMASK_ZW
;
2750 /* If the mask does not include any of the channels X or Y there
2751 * is nothing to do in this iteration. Move on to the next couple
2752 * of 64-bit channels.
2760 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2761 opcode
= indirect_offset
.file
!= BAD_FILE
?
2762 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2763 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2765 opcode
= indirect_offset
.file
!= BAD_FILE
?
2766 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2767 SHADER_OPCODE_URB_WRITE_SIMD8
;
2770 for (unsigned i
= 0; i
< iter_components
; i
++) {
2771 if (!(mask
& (1 << (i
+ first_component
))))
2775 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2777 /* We need to shuffle the 64-bit data to match the layout
2778 * expected by our 32-bit URB write messages. We use a temporary
2781 unsigned channel
= iter
* 2 + i
;
2782 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2784 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2785 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2786 offset(dest
, bld
, 1);
2791 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2792 (is_64bit
? 2 * first_component
: first_component
);
2794 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2795 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2797 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2798 inst
->offset
= imm_offset
;
2801 /* If this is a 64-bit attribute, select the next two 64-bit channels
2802 * to be handled in the next iteration.
2813 nir_emit_intrinsic(bld
, instr
);
2819 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2820 nir_intrinsic_instr
*instr
)
2822 assert(stage
== MESA_SHADER_TESS_EVAL
);
2823 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2826 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2827 dest
= get_nir_dest(instr
->dest
);
2829 switch (instr
->intrinsic
) {
2830 case nir_intrinsic_load_primitive_id
:
2831 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2833 case nir_intrinsic_load_tess_coord
:
2834 /* gl_TessCoord is part of the payload in g1-3 */
2835 for (unsigned i
= 0; i
< 3; i
++) {
2836 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2840 case nir_intrinsic_load_input
:
2841 case nir_intrinsic_load_per_vertex_input
: {
2842 fs_reg indirect_offset
= get_indirect_offset(instr
);
2843 unsigned imm_offset
= instr
->const_index
[0];
2844 unsigned first_component
= nir_intrinsic_component(instr
);
2846 if (type_sz(dest
.type
) == 8) {
2847 first_component
= first_component
/ 2;
2851 if (indirect_offset
.file
== BAD_FILE
) {
2852 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2853 * which is 16 registers (since each holds 2 vec4 slots).
2855 unsigned slot_count
= 1;
2856 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2859 const unsigned max_push_slots
= 32;
2860 if (imm_offset
+ slot_count
<= max_push_slots
) {
2861 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2862 for (int i
= 0; i
< instr
->num_components
; i
++) {
2863 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2864 i
+ first_component
;
2865 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2868 tes_prog_data
->base
.urb_read_length
=
2869 MAX2(tes_prog_data
->base
.urb_read_length
,
2870 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2872 /* Replicate the patch handle to all enabled channels */
2873 const fs_reg srcs
[] = {
2874 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2876 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2877 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2879 if (first_component
!= 0) {
2880 unsigned read_components
=
2881 instr
->num_components
+ first_component
;
2882 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2883 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2885 inst
->size_written
= read_components
* REG_SIZE
;
2886 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2887 bld
.MOV(offset(dest
, bld
, i
),
2888 offset(tmp
, bld
, i
+ first_component
));
2891 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2893 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2896 inst
->offset
= imm_offset
;
2899 /* Indirect indexing - use per-slot offsets as well. */
2901 /* We can only read two double components with each URB read, so
2902 * we send two read messages in that case, each one loading up to
2903 * two double components.
2905 unsigned num_iterations
= 1;
2906 unsigned num_components
= instr
->num_components
;
2907 fs_reg orig_dest
= dest
;
2908 if (type_sz(dest
.type
) == 8) {
2909 if (instr
->num_components
> 2) {
2913 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2917 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2918 const fs_reg srcs
[] = {
2919 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2922 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2923 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2925 if (first_component
!= 0) {
2926 unsigned read_components
=
2927 num_components
+ first_component
;
2928 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2929 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2931 for (unsigned i
= 0; i
< num_components
; i
++) {
2932 bld
.MOV(offset(dest
, bld
, i
),
2933 offset(tmp
, bld
, i
+ first_component
));
2936 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2940 inst
->offset
= imm_offset
;
2941 inst
->size_written
= (num_components
+ first_component
) *
2942 inst
->dst
.component_size(inst
->exec_size
);
2944 /* If we are reading 64-bit data using 32-bit read messages we need
2945 * build proper 64-bit data elements by shuffling the low and high
2946 * 32-bit components around like we do for other things like UBOs
2949 if (type_sz(dest
.type
) == 8) {
2950 shuffle_from_32bit_read(bld
,
2951 offset(orig_dest
, bld
, iter
* 2),
2952 retype(dest
, BRW_REGISTER_TYPE_D
),
2956 /* If we are loading double data and we need a second read message
2959 if (num_iterations
> 1) {
2960 num_components
= instr
->num_components
- 2;
2968 nir_emit_intrinsic(bld
, instr
);
2974 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2975 nir_intrinsic_instr
*instr
)
2977 assert(stage
== MESA_SHADER_GEOMETRY
);
2978 fs_reg indirect_offset
;
2981 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2982 dest
= get_nir_dest(instr
->dest
);
2984 switch (instr
->intrinsic
) {
2985 case nir_intrinsic_load_primitive_id
:
2986 assert(stage
== MESA_SHADER_GEOMETRY
);
2987 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2988 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2989 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2992 case nir_intrinsic_load_input
:
2993 unreachable("load_input intrinsics are invalid for the GS stage");
2995 case nir_intrinsic_load_per_vertex_input
:
2996 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2997 instr
->src
[1], instr
->num_components
,
2998 nir_intrinsic_component(instr
));
3001 case nir_intrinsic_emit_vertex_with_counter
:
3002 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3005 case nir_intrinsic_end_primitive_with_counter
:
3006 emit_gs_end_primitive(instr
->src
[0]);
3009 case nir_intrinsic_set_vertex_count
:
3010 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3013 case nir_intrinsic_load_invocation_id
: {
3014 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3015 assert(val
.file
!= BAD_FILE
);
3016 dest
.type
= val
.type
;
3022 nir_emit_intrinsic(bld
, instr
);
3028 * Fetch the current render target layer index.
3031 fetch_render_target_array_index(const fs_builder
&bld
)
3033 if (bld
.shader
->devinfo
->gen
>= 6) {
3034 /* The render target array index is provided in the thread payload as
3035 * bits 26:16 of r0.0.
3037 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3038 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3042 /* Pre-SNB we only ever render into the first layer of the framebuffer
3043 * since layered rendering is not implemented.
3045 return brw_imm_ud(0);
3050 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3051 * framebuffer at the current fragment coordinates and sample index.
3054 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3057 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3059 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3060 const brw_wm_prog_key
*wm_key
=
3061 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3062 assert(!wm_key
->coherent_fb_fetch
);
3063 const struct brw_wm_prog_data
*wm_prog_data
=
3064 brw_wm_prog_data(stage_prog_data
);
3066 /* Calculate the surface index relative to the start of the texture binding
3067 * table block, since that's what the texturing messages expect.
3069 const unsigned surface
= target
+
3070 wm_prog_data
->binding_table
.render_target_read_start
-
3071 wm_prog_data
->base
.binding_table
.texture_start
;
3073 /* Calculate the fragment coordinates. */
3074 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3075 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3076 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3077 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3079 /* Calculate the sample index and MCS payload when multisampling. Luckily
3080 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3081 * shouldn't be necessary to recompile based on whether the framebuffer is
3084 if (wm_key
->multisample_fbo
&&
3085 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3086 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3088 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3089 const fs_reg mcs
= wm_key
->multisample_fbo
?
3090 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3092 /* Use either a normal or a CMS texel fetch message depending on whether
3093 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3094 * message just in case the framebuffer uses 16x multisampling, it should
3095 * be equivalent to the normal CMS fetch for lower multisampling modes.
3097 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3098 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3099 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3101 /* Emit the instruction. */
3102 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3103 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3104 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3105 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3106 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3107 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3108 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3109 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3110 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3112 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3113 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3119 * Actual coherent framebuffer read implemented using the native render target
3120 * read message. Requires SKL+.
3123 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3125 assert(bld
.shader
->devinfo
->gen
>= 9);
3126 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3127 inst
->target
= target
;
3128 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3134 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3136 if (n
&& regs
[0].file
!= BAD_FILE
) {
3140 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3142 for (unsigned i
= 0; i
< n
; i
++)
3150 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3152 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3153 const brw_wm_prog_key
*const key
=
3154 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3155 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3156 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3158 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3159 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3161 else if (l
== FRAG_RESULT_COLOR
)
3162 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3163 MAX2(key
->nr_color_regions
, 1));
3165 else if (l
== FRAG_RESULT_DEPTH
)
3166 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3168 else if (l
== FRAG_RESULT_STENCIL
)
3169 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3171 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3172 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3174 else if (l
>= FRAG_RESULT_DATA0
&&
3175 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3176 return alloc_temporary(v
->bld
, 4,
3177 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3180 unreachable("Invalid location");
3184 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3185 nir_intrinsic_instr
*instr
)
3187 assert(stage
== MESA_SHADER_FRAGMENT
);
3190 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3191 dest
= get_nir_dest(instr
->dest
);
3193 switch (instr
->intrinsic
) {
3194 case nir_intrinsic_load_front_face
:
3195 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3196 *emit_frontfacing_interpolation());
3199 case nir_intrinsic_load_sample_pos
: {
3200 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3201 assert(sample_pos
.file
!= BAD_FILE
);
3202 dest
.type
= sample_pos
.type
;
3203 bld
.MOV(dest
, sample_pos
);
3204 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3208 case nir_intrinsic_load_layer_id
:
3209 dest
.type
= BRW_REGISTER_TYPE_UD
;
3210 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3213 case nir_intrinsic_load_helper_invocation
:
3214 case nir_intrinsic_load_sample_mask_in
:
3215 case nir_intrinsic_load_sample_id
: {
3216 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3217 fs_reg val
= nir_system_values
[sv
];
3218 assert(val
.file
!= BAD_FILE
);
3219 dest
.type
= val
.type
;
3224 case nir_intrinsic_store_output
: {
3225 const fs_reg src
= get_nir_src(instr
->src
[0]);
3226 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3227 const unsigned location
= nir_intrinsic_base(instr
) +
3228 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3229 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3232 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3233 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3234 offset(src
, bld
, j
));
3239 case nir_intrinsic_load_output
: {
3240 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3241 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3242 assert(l
>= FRAG_RESULT_DATA0
);
3243 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3244 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3245 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3247 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3248 emit_coherent_fb_read(bld
, tmp
, target
);
3250 emit_non_coherent_fb_read(bld
, tmp
, target
);
3252 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3253 bld
.MOV(offset(dest
, bld
, j
),
3254 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3260 case nir_intrinsic_discard
:
3261 case nir_intrinsic_discard_if
: {
3262 /* We track our discarded pixels in f0.1. By predicating on it, we can
3263 * update just the flag bits that aren't yet discarded. If there's no
3264 * condition, we emit a CMP of g0 != g0, so all currently executing
3265 * channels will get turned off.
3268 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3269 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3270 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3272 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3273 BRW_REGISTER_TYPE_UW
));
3274 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3276 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3277 cmp
->flag_subreg
= 1;
3279 if (devinfo
->gen
>= 6) {
3280 emit_discard_jump();
3283 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3287 case nir_intrinsic_load_input
: {
3288 /* load_input is only used for flat inputs */
3289 unsigned base
= nir_intrinsic_base(instr
);
3290 unsigned comp
= nir_intrinsic_component(instr
);
3291 unsigned num_components
= instr
->num_components
;
3292 fs_reg orig_dest
= dest
;
3293 enum brw_reg_type type
= dest
.type
;
3295 /* Special case fields in the VUE header */
3296 if (base
== VARYING_SLOT_LAYER
)
3298 else if (base
== VARYING_SLOT_VIEWPORT
)
3301 if (nir_dest_bit_size(instr
->dest
) == 64) {
3302 /* const_index is in 32-bit type size units that could not be aligned
3303 * with DF. We need to read the double vector as if it was a float
3304 * vector of twice the number of components to fetch the right data.
3306 type
= BRW_REGISTER_TYPE_F
;
3307 num_components
*= 2;
3308 dest
= bld
.vgrf(type
, num_components
);
3311 for (unsigned int i
= 0; i
< num_components
; i
++) {
3312 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3313 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3316 if (nir_dest_bit_size(instr
->dest
) == 64) {
3317 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3318 instr
->num_components
);
3323 case nir_intrinsic_load_barycentric_pixel
:
3324 case nir_intrinsic_load_barycentric_centroid
:
3325 case nir_intrinsic_load_barycentric_sample
:
3326 /* Do nothing - load_interpolated_input handling will handle it later. */
3329 case nir_intrinsic_load_barycentric_at_sample
: {
3330 const glsl_interp_mode interpolation
=
3331 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3333 if (nir_src_is_const(instr
->src
[0])) {
3334 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3336 emit_pixel_interpolater_send(bld
,
3337 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3340 brw_imm_ud(msg_data
),
3343 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3344 BRW_REGISTER_TYPE_UD
);
3346 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3347 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3348 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3349 bld
.exec_all().group(1, 0)
3350 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3351 emit_pixel_interpolater_send(bld
,
3352 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3358 /* Make a loop that sends a message to the pixel interpolater
3359 * for the sample number in each live channel. If there are
3360 * multiple channels with the same sample number then these
3361 * will be handled simultaneously with a single interation of
3364 bld
.emit(BRW_OPCODE_DO
);
3366 /* Get the next live sample number into sample_id_reg */
3367 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3369 /* Set the flag register so that we can perform the send
3370 * message on all channels that have the same sample number
3372 bld
.CMP(bld
.null_reg_ud(),
3373 sample_src
, sample_id
,
3374 BRW_CONDITIONAL_EQ
);
3375 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3376 bld
.exec_all().group(1, 0)
3377 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3379 emit_pixel_interpolater_send(bld
,
3380 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3383 component(msg_data
, 0),
3385 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3387 /* Continue the loop if there are any live channels left */
3388 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3390 bld
.emit(BRW_OPCODE_WHILE
));
3396 case nir_intrinsic_load_barycentric_at_offset
: {
3397 const glsl_interp_mode interpolation
=
3398 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3400 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3403 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3404 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3405 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3407 emit_pixel_interpolater_send(bld
,
3408 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3411 brw_imm_ud(off_x
| (off_y
<< 4)),
3414 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3415 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3416 BRW_REGISTER_TYPE_F
);
3417 for (int i
= 0; i
< 2; i
++) {
3418 fs_reg temp
= vgrf(glsl_type::float_type
);
3419 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3420 fs_reg itemp
= vgrf(glsl_type::int_type
);
3422 bld
.MOV(itemp
, temp
);
3424 /* Clamp the upper end of the range to +7/16.
3425 * ARB_gpu_shader5 requires that we support a maximum offset
3426 * of +0.5, which isn't representable in a S0.4 value -- if
3427 * we didn't clamp it, we'd end up with -8/16, which is the
3428 * opposite of what the shader author wanted.
3430 * This is legal due to ARB_gpu_shader5's quantization
3433 * "Not all values of <offset> may be supported; x and y
3434 * offsets may be rounded to fixed-point values with the
3435 * number of fraction bits given by the
3436 * implementation-dependent constant
3437 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3439 set_condmod(BRW_CONDITIONAL_L
,
3440 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3443 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3444 emit_pixel_interpolater_send(bld
,
3454 case nir_intrinsic_load_interpolated_input
: {
3455 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3456 emit_fragcoord_interpolation(dest
);
3460 assert(instr
->src
[0].ssa
&&
3461 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3462 nir_intrinsic_instr
*bary_intrinsic
=
3463 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3464 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3465 enum glsl_interp_mode interp_mode
=
3466 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3469 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3470 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3471 /* Use the result of the PI message */
3472 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3474 /* Use the delta_xy values computed from the payload */
3475 enum brw_barycentric_mode bary
=
3476 brw_barycentric_mode(interp_mode
, bary_intrin
);
3478 dst_xy
= this->delta_xy
[bary
];
3481 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3483 component(interp_reg(nir_intrinsic_base(instr
),
3484 nir_intrinsic_component(instr
) + i
), 0);
3485 interp
.type
= BRW_REGISTER_TYPE_F
;
3486 dest
.type
= BRW_REGISTER_TYPE_F
;
3488 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3489 fs_reg tmp
= vgrf(glsl_type::float_type
);
3490 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3491 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3493 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3500 nir_emit_intrinsic(bld
, instr
);
3506 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3508 if (nir_src_is_const(instr
->src
[src
])) {
3509 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3512 else if (add_val
== -1)
3520 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3521 nir_intrinsic_instr
*instr
)
3523 assert(stage
== MESA_SHADER_COMPUTE
);
3524 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3527 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3528 dest
= get_nir_dest(instr
->dest
);
3530 switch (instr
->intrinsic
) {
3531 case nir_intrinsic_barrier
:
3533 cs_prog_data
->uses_barrier
= true;
3536 case nir_intrinsic_load_subgroup_id
:
3537 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3540 case nir_intrinsic_load_local_invocation_id
:
3541 case nir_intrinsic_load_work_group_id
: {
3542 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3543 fs_reg val
= nir_system_values
[sv
];
3544 assert(val
.file
!= BAD_FILE
);
3545 dest
.type
= val
.type
;
3546 for (unsigned i
= 0; i
< 3; i
++)
3547 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3551 case nir_intrinsic_load_num_work_groups
: {
3552 const unsigned surface
=
3553 cs_prog_data
->binding_table
.work_groups_start
;
3555 cs_prog_data
->uses_num_work_groups
= true;
3557 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3558 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3559 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3560 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3562 /* Read the 3 GLuint components of gl_NumWorkGroups */
3563 for (unsigned i
= 0; i
< 3; i
++) {
3564 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3565 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3566 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3571 case nir_intrinsic_shared_atomic_add
:
3572 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3574 case nir_intrinsic_shared_atomic_imin
:
3575 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3577 case nir_intrinsic_shared_atomic_umin
:
3578 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3580 case nir_intrinsic_shared_atomic_imax
:
3581 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3583 case nir_intrinsic_shared_atomic_umax
:
3584 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3586 case nir_intrinsic_shared_atomic_and
:
3587 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3589 case nir_intrinsic_shared_atomic_or
:
3590 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3592 case nir_intrinsic_shared_atomic_xor
:
3593 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3595 case nir_intrinsic_shared_atomic_exchange
:
3596 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3598 case nir_intrinsic_shared_atomic_comp_swap
:
3599 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3601 case nir_intrinsic_shared_atomic_fmin
:
3602 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3604 case nir_intrinsic_shared_atomic_fmax
:
3605 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3607 case nir_intrinsic_shared_atomic_fcomp_swap
:
3608 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3611 case nir_intrinsic_load_shared
: {
3612 assert(devinfo
->gen
>= 7);
3613 assert(stage
== MESA_SHADER_COMPUTE
);
3615 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3616 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3617 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3618 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3619 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3621 /* Make dest unsigned because that's what the temporary will be */
3622 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3624 /* Read the vector */
3625 if (nir_intrinsic_align(instr
) >= 4) {
3626 assert(nir_dest_bit_size(instr
->dest
) == 32);
3627 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3629 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3630 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3631 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3633 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3634 assert(nir_dest_num_components(instr
->dest
) == 1);
3635 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3637 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3638 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3639 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3640 bld
.MOV(dest
, read_result
);
3645 case nir_intrinsic_store_shared
: {
3646 assert(devinfo
->gen
>= 7);
3647 assert(stage
== MESA_SHADER_COMPUTE
);
3649 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3650 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3651 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3652 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3653 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3655 fs_reg data
= get_nir_src(instr
->src
[0]);
3656 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3658 assert(nir_intrinsic_write_mask(instr
) ==
3659 (1u << instr
->num_components
) - 1);
3660 if (nir_intrinsic_align(instr
) >= 4) {
3661 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3662 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3663 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3664 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3665 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3666 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3668 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3669 assert(nir_src_num_components(instr
->src
[0]) == 1);
3670 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3672 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3673 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3675 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3676 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3682 nir_emit_intrinsic(bld
, instr
);
3688 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3689 nir_op op
, brw_reg_type type
)
3691 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3692 switch (type_sz(type
)) {
3694 assert(type
!= BRW_REGISTER_TYPE_HF
);
3695 return retype(brw_imm_uw(value
.u16
), type
);
3697 return retype(brw_imm_ud(value
.u32
), type
);
3699 if (type
== BRW_REGISTER_TYPE_DF
)
3700 return setup_imm_df(bld
, value
.f64
);
3702 return retype(brw_imm_u64(value
.u64
), type
);
3704 unreachable("Invalid type size");
3709 brw_op_for_nir_reduction_op(nir_op op
)
3712 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3713 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3714 case nir_op_imul
: return BRW_OPCODE_MUL
;
3715 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3716 case nir_op_imin
: return BRW_OPCODE_SEL
;
3717 case nir_op_umin
: return BRW_OPCODE_SEL
;
3718 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3719 case nir_op_imax
: return BRW_OPCODE_SEL
;
3720 case nir_op_umax
: return BRW_OPCODE_SEL
;
3721 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3722 case nir_op_iand
: return BRW_OPCODE_AND
;
3723 case nir_op_ior
: return BRW_OPCODE_OR
;
3724 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3726 unreachable("Invalid reduction operation");
3730 static brw_conditional_mod
3731 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3734 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3735 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3736 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3737 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3738 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3739 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3740 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3741 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3742 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3743 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3744 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3745 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3746 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3748 unreachable("Invalid reduction operation");
3753 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3754 nir_intrinsic_instr
*instr
)
3756 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3758 if (stage_prog_data
->binding_table
.image_start
> 0) {
3759 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3760 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3762 bld
.ADD(image
, image
,
3763 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3767 return bld
.emit_uniformize(image
);
3771 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3772 nir_intrinsic_instr
*instr
)
3774 /* SSBO stores are weird in that their index is in src[1] */
3775 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3778 if (nir_src_is_const(instr
->src
[src
])) {
3779 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3780 nir_src_as_uint(instr
->src
[src
]);
3781 surf_index
= brw_imm_ud(index
);
3783 surf_index
= vgrf(glsl_type::uint_type
);
3784 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3785 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3788 return bld
.emit_uniformize(surf_index
);
3792 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3794 switch (nir_intrinsic_image_dim(instr
)) {
3795 case GLSL_SAMPLER_DIM_1D
:
3796 return 1 + nir_intrinsic_image_array(instr
);
3797 case GLSL_SAMPLER_DIM_2D
:
3798 case GLSL_SAMPLER_DIM_RECT
:
3799 return 2 + nir_intrinsic_image_array(instr
);
3800 case GLSL_SAMPLER_DIM_3D
:
3801 case GLSL_SAMPLER_DIM_CUBE
:
3803 case GLSL_SAMPLER_DIM_BUF
:
3805 case GLSL_SAMPLER_DIM_MS
:
3806 return 2 + nir_intrinsic_image_array(instr
);
3808 unreachable("Invalid image dimension");
3813 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3816 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3817 dest
= get_nir_dest(instr
->dest
);
3819 switch (instr
->intrinsic
) {
3820 case nir_intrinsic_image_load
:
3821 case nir_intrinsic_image_store
:
3822 case nir_intrinsic_image_atomic_add
:
3823 case nir_intrinsic_image_atomic_min
:
3824 case nir_intrinsic_image_atomic_max
:
3825 case nir_intrinsic_image_atomic_and
:
3826 case nir_intrinsic_image_atomic_or
:
3827 case nir_intrinsic_image_atomic_xor
:
3828 case nir_intrinsic_image_atomic_exchange
:
3829 case nir_intrinsic_image_atomic_comp_swap
: {
3830 if (stage
== MESA_SHADER_FRAGMENT
&&
3831 instr
->intrinsic
!= nir_intrinsic_image_load
)
3832 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3834 /* Get some metadata from the image intrinsic. */
3835 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3836 const GLenum format
= nir_intrinsic_format(instr
);
3838 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3839 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3840 get_nir_image_intrinsic_image(bld
, instr
);
3841 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3842 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
3843 brw_imm_ud(image_intrinsic_coord_components(instr
));
3845 /* Emit an image load, store or atomic op. */
3846 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3847 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3849 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
3850 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3851 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3852 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3853 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3854 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
3855 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
3856 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3859 unsigned num_srcs
= info
->num_srcs
;
3861 switch (instr
->intrinsic
) {
3862 case nir_intrinsic_image_atomic_add
:
3863 assert(num_srcs
== 4);
3865 op
= get_op_for_atomic_add(instr
, 3);
3867 if (op
!= BRW_AOP_ADD
)
3870 case nir_intrinsic_image_atomic_min
:
3871 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3872 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3874 case nir_intrinsic_image_atomic_max
:
3875 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3876 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3878 case nir_intrinsic_image_atomic_and
:
3881 case nir_intrinsic_image_atomic_or
:
3884 case nir_intrinsic_image_atomic_xor
:
3887 case nir_intrinsic_image_atomic_exchange
:
3890 case nir_intrinsic_image_atomic_comp_swap
:
3894 unreachable("Not reachable.");
3897 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
3901 data
= get_nir_src(instr
->src
[3]);
3902 if (num_srcs
>= 5) {
3903 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
3904 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
3905 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
3908 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3910 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
3911 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3916 case nir_intrinsic_image_size
: {
3917 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3918 * into will handle the binding table index for us in the geneerator.
3920 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3921 BRW_REGISTER_TYPE_UD
);
3922 image
= bld
.emit_uniformize(image
);
3924 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3925 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
3926 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
3927 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
3928 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
3930 /* Since the image size is always uniform, we can just emit a SIMD8
3931 * query instruction and splat the result out.
3933 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3935 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3936 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
3937 tmp
, srcs
, ARRAY_SIZE(srcs
));
3938 inst
->size_written
= 4 * REG_SIZE
;
3940 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3941 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3942 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3943 offset(retype(dest
, tmp
.type
), bld
, c
),
3944 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3946 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3947 component(offset(tmp
, ubld
, c
), 0));
3953 case nir_intrinsic_image_load_raw_intel
: {
3954 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3955 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3956 get_nir_image_intrinsic_image(bld
, instr
);
3957 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3958 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3959 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3962 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3963 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3964 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3968 case nir_intrinsic_image_store_raw_intel
: {
3969 if (stage
== MESA_SHADER_FRAGMENT
)
3970 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3972 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3973 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3974 get_nir_image_intrinsic_image(bld
, instr
);
3975 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3976 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
3977 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3978 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3980 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3981 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3985 case nir_intrinsic_group_memory_barrier
:
3986 case nir_intrinsic_memory_barrier_shared
:
3987 case nir_intrinsic_memory_barrier_atomic_counter
:
3988 case nir_intrinsic_memory_barrier_buffer
:
3989 case nir_intrinsic_memory_barrier_image
:
3990 case nir_intrinsic_memory_barrier
: {
3991 const fs_builder ubld
= bld
.group(8, 0);
3992 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3993 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3994 ->size_written
= 2 * REG_SIZE
;
3998 case nir_intrinsic_shader_clock
: {
3999 /* We cannot do anything if there is an event, so ignore it for now */
4000 const fs_reg shader_clock
= get_timestamp(bld
);
4001 const fs_reg srcs
[] = { component(shader_clock
, 0),
4002 component(shader_clock
, 1) };
4003 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4007 case nir_intrinsic_image_samples
:
4008 /* The driver does not support multi-sampled images. */
4009 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4012 case nir_intrinsic_load_uniform
: {
4013 /* Offsets are in bytes but they should always aligned to
4016 assert(instr
->const_index
[0] % 4 == 0 ||
4017 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4019 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4021 if (nir_src_is_const(instr
->src
[0])) {
4022 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4023 assert(load_offset
% type_sz(dest
.type
) == 0);
4024 /* For 16-bit types we add the module of the const_index[0]
4025 * offset to access to not 32-bit aligned element
4027 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4029 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4030 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4033 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4034 BRW_REGISTER_TYPE_UD
);
4036 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4037 * go past the end of the uniform. In order to keep the n'th
4038 * component from running past, we subtract off the size of all but
4039 * one component of the vector.
4041 assert(instr
->const_index
[1] >=
4042 instr
->num_components
* (int) type_sz(dest
.type
));
4043 unsigned read_size
= instr
->const_index
[1] -
4044 (instr
->num_components
- 1) * type_sz(dest
.type
);
4046 bool supports_64bit_indirects
=
4047 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4049 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4050 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4051 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4052 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4053 indirect
, brw_imm_ud(read_size
));
4056 const unsigned num_mov_indirects
=
4057 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4058 /* We read a little bit less per MOV INDIRECT, as they are now
4059 * 32-bits ones instead of 64-bit. Fix read_size then.
4061 const unsigned read_size_32bit
= read_size
-
4062 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4063 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4064 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4065 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4066 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4067 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4068 indirect
, brw_imm_ud(read_size_32bit
));
4076 case nir_intrinsic_load_ubo
: {
4078 if (nir_src_is_const(instr
->src
[0])) {
4079 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4080 nir_src_as_uint(instr
->src
[0]);
4081 surf_index
= brw_imm_ud(index
);
4083 /* The block index is not a constant. Evaluate the index expression
4084 * per-channel and add the base UBO index; we have to select a value
4085 * from any live channel.
4087 surf_index
= vgrf(glsl_type::uint_type
);
4088 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4089 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4090 surf_index
= bld
.emit_uniformize(surf_index
);
4093 if (!nir_src_is_const(instr
->src
[1])) {
4094 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4095 BRW_REGISTER_TYPE_UD
);
4097 for (int i
= 0; i
< instr
->num_components
; i
++)
4098 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4099 base_offset
, i
* type_sz(dest
.type
));
4101 /* Even if we are loading doubles, a pull constant load will load
4102 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4103 * need to load a full dvec4 we will have to emit 2 loads. This is
4104 * similar to demote_pull_constants(), except that in that case we
4105 * see individual accesses to each component of the vector and then
4106 * we let CSE deal with duplicate loads. Here we see a vector access
4107 * and we have to split it if necessary.
4109 const unsigned type_size
= type_sz(dest
.type
);
4110 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4112 /* See if we've selected this as a push constant candidate */
4113 if (nir_src_is_const(instr
->src
[0])) {
4114 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4115 const unsigned offset_256b
= load_offset
/ 32;
4118 for (int i
= 0; i
< 4; i
++) {
4119 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4120 if (range
->block
== ubo_block
&&
4121 offset_256b
>= range
->start
&&
4122 offset_256b
< range
->start
+ range
->length
) {
4124 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4125 push_reg
.offset
= load_offset
- 32 * range
->start
;
4130 if (push_reg
.file
!= BAD_FILE
) {
4131 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4132 bld
.MOV(offset(dest
, bld
, i
),
4133 byte_offset(push_reg
, i
* type_size
));
4139 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4140 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4141 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4143 for (unsigned c
= 0; c
< instr
->num_components
;) {
4144 const unsigned base
= load_offset
+ c
* type_size
;
4145 /* Number of usable components in the next block-aligned load. */
4146 const unsigned count
= MIN2(instr
->num_components
- c
,
4147 (block_sz
- base
% block_sz
) / type_size
);
4149 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4150 packed_consts
, surf_index
,
4151 brw_imm_ud(base
& ~(block_sz
- 1)));
4153 const fs_reg consts
=
4154 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4157 for (unsigned d
= 0; d
< count
; d
++)
4158 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4166 case nir_intrinsic_load_global
: {
4167 assert(devinfo
->gen
>= 8);
4169 if (nir_intrinsic_align(instr
) >= 4) {
4170 assert(nir_dest_bit_size(instr
->dest
) == 32);
4171 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4173 get_nir_src(instr
->src
[0]), /* Address */
4174 fs_reg(), /* No source data */
4175 brw_imm_ud(instr
->num_components
));
4176 inst
->size_written
= instr
->num_components
*
4177 inst
->dst
.component_size(inst
->exec_size
);
4179 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4180 assert(bit_size
<= 32);
4181 assert(nir_dest_num_components(instr
->dest
) == 1);
4182 brw_reg_type data_type
=
4183 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4184 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4185 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4187 get_nir_src(instr
->src
[0]), /* Address */
4188 fs_reg(), /* No source data */
4189 brw_imm_ud(bit_size
));
4190 bld
.MOV(retype(dest
, data_type
), tmp
);
4195 case nir_intrinsic_store_global
:
4196 assert(devinfo
->gen
>= 8);
4198 if (stage
== MESA_SHADER_FRAGMENT
)
4199 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4201 if (nir_intrinsic_align(instr
) >= 4) {
4202 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4203 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4205 get_nir_src(instr
->src
[1]), /* Address */
4206 get_nir_src(instr
->src
[0]), /* Data */
4207 brw_imm_ud(instr
->num_components
));
4209 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4210 assert(bit_size
<= 32);
4211 assert(nir_src_num_components(instr
->src
[0]) == 1);
4212 brw_reg_type data_type
=
4213 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4214 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4215 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4216 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4218 get_nir_src(instr
->src
[1]), /* Address */
4220 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4224 case nir_intrinsic_global_atomic_add
:
4225 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4227 case nir_intrinsic_global_atomic_imin
:
4228 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4230 case nir_intrinsic_global_atomic_umin
:
4231 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4233 case nir_intrinsic_global_atomic_imax
:
4234 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4236 case nir_intrinsic_global_atomic_umax
:
4237 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4239 case nir_intrinsic_global_atomic_and
:
4240 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4242 case nir_intrinsic_global_atomic_or
:
4243 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4245 case nir_intrinsic_global_atomic_xor
:
4246 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4248 case nir_intrinsic_global_atomic_exchange
:
4249 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4251 case nir_intrinsic_global_atomic_comp_swap
:
4252 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4254 case nir_intrinsic_global_atomic_fmin
:
4255 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4257 case nir_intrinsic_global_atomic_fmax
:
4258 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4260 case nir_intrinsic_global_atomic_fcomp_swap
:
4261 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4264 case nir_intrinsic_load_ssbo
: {
4265 assert(devinfo
->gen
>= 7);
4267 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4268 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4269 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4270 get_nir_ssbo_intrinsic_index(bld
, instr
);
4271 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4272 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4274 /* Make dest unsigned because that's what the temporary will be */
4275 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4277 /* Read the vector */
4278 if (nir_intrinsic_align(instr
) >= 4) {
4279 assert(nir_dest_bit_size(instr
->dest
) == 32);
4280 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4282 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4283 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4284 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4286 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4287 assert(nir_dest_num_components(instr
->dest
) == 1);
4288 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4290 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4291 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4292 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4293 bld
.MOV(dest
, read_result
);
4298 case nir_intrinsic_store_ssbo
: {
4299 assert(devinfo
->gen
>= 7);
4301 if (stage
== MESA_SHADER_FRAGMENT
)
4302 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4304 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4305 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4306 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4307 get_nir_ssbo_intrinsic_index(bld
, instr
);
4308 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4309 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4311 fs_reg data
= get_nir_src(instr
->src
[0]);
4312 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4314 assert(nir_intrinsic_write_mask(instr
) ==
4315 (1u << instr
->num_components
) - 1);
4316 if (nir_intrinsic_align(instr
) >= 4) {
4317 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4318 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4319 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4320 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4321 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4322 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4324 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4325 assert(nir_src_num_components(instr
->src
[0]) == 1);
4326 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4328 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4329 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4331 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4332 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4337 case nir_intrinsic_store_output
: {
4338 fs_reg src
= get_nir_src(instr
->src
[0]);
4340 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4341 unsigned num_components
= instr
->num_components
;
4342 unsigned first_component
= nir_intrinsic_component(instr
);
4343 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4344 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4345 num_components
*= 2;
4348 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4349 4 * store_offset
), src
.type
);
4350 for (unsigned j
= 0; j
< num_components
; j
++) {
4351 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4352 offset(src
, bld
, j
));
4357 case nir_intrinsic_ssbo_atomic_add
:
4358 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4360 case nir_intrinsic_ssbo_atomic_imin
:
4361 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4363 case nir_intrinsic_ssbo_atomic_umin
:
4364 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4366 case nir_intrinsic_ssbo_atomic_imax
:
4367 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4369 case nir_intrinsic_ssbo_atomic_umax
:
4370 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4372 case nir_intrinsic_ssbo_atomic_and
:
4373 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4375 case nir_intrinsic_ssbo_atomic_or
:
4376 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4378 case nir_intrinsic_ssbo_atomic_xor
:
4379 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4381 case nir_intrinsic_ssbo_atomic_exchange
:
4382 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4384 case nir_intrinsic_ssbo_atomic_comp_swap
:
4385 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4387 case nir_intrinsic_ssbo_atomic_fmin
:
4388 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4390 case nir_intrinsic_ssbo_atomic_fmax
:
4391 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4393 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4394 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4397 case nir_intrinsic_get_buffer_size
: {
4398 assert(nir_src_num_components(instr
->src
[0]) == 1);
4399 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4400 nir_src_as_uint(instr
->src
[0]) : 0;
4402 /* A resinfo's sampler message is used to get the buffer size. The
4403 * SIMD8's writeback message consists of four registers and SIMD16's
4404 * writeback message consists of 8 destination registers (two per each
4405 * component). Because we are only interested on the first channel of
4406 * the first returned component, where resinfo returns the buffer size
4407 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4408 * the dispatch width.
4410 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4411 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4412 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4415 ubld
.MOV(src_payload
, brw_imm_d(0));
4417 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4418 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4419 src_payload
, brw_imm_ud(index
));
4420 inst
->header_size
= 0;
4422 inst
->size_written
= 4 * REG_SIZE
;
4424 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4426 * "Out-of-bounds checking is always performed at a DWord granularity. If
4427 * any part of the DWord is out-of-bounds then the whole DWord is
4428 * considered out-of-bounds."
4430 * This implies that types with size smaller than 4-bytes need to be
4431 * padded if they don't complete the last dword of the buffer. But as we
4432 * need to maintain the original size we need to reverse the padding
4433 * calculation to return the correct size to know the number of elements
4434 * of an unsized array. As we stored in the last two bits of the surface
4435 * size the needed padding for the buffer, we calculate here the
4436 * original buffer_size reversing the surface_size calculation:
4438 * surface_size = isl_align(buffer_size, 4) +
4439 * (isl_align(buffer_size) - buffer_size)
4441 * buffer_size = surface_size & ~3 - surface_size & 3
4444 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4445 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4446 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4448 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4449 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4450 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4452 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4456 case nir_intrinsic_load_subgroup_invocation
:
4457 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4458 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4461 case nir_intrinsic_load_subgroup_eq_mask
:
4462 case nir_intrinsic_load_subgroup_ge_mask
:
4463 case nir_intrinsic_load_subgroup_gt_mask
:
4464 case nir_intrinsic_load_subgroup_le_mask
:
4465 case nir_intrinsic_load_subgroup_lt_mask
:
4466 unreachable("not reached");
4468 case nir_intrinsic_vote_any
: {
4469 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4471 /* The any/all predicates do not consider channel enables. To prevent
4472 * dead channels from affecting the result, we initialize the flag with
4473 * with the identity value for the logical operation.
4475 if (dispatch_width
== 32) {
4476 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4477 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4480 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4482 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4484 /* For some reason, the any/all predicates don't work properly with
4485 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4486 * doesn't read the correct subset of the flag register and you end up
4487 * getting garbage in the second half. Work around this by using a pair
4488 * of 1-wide MOVs and scattering the result.
4490 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4491 ubld
.MOV(res1
, brw_imm_d(0));
4492 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4493 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4494 BRW_PREDICATE_ALIGN1_ANY32H
,
4495 ubld
.MOV(res1
, brw_imm_d(-1)));
4497 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4500 case nir_intrinsic_vote_all
: {
4501 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4503 /* The any/all predicates do not consider channel enables. To prevent
4504 * dead channels from affecting the result, we initialize the flag with
4505 * with the identity value for the logical operation.
4507 if (dispatch_width
== 32) {
4508 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4509 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4510 brw_imm_ud(0xffffffff));
4512 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4514 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4516 /* For some reason, the any/all predicates don't work properly with
4517 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4518 * doesn't read the correct subset of the flag register and you end up
4519 * getting garbage in the second half. Work around this by using a pair
4520 * of 1-wide MOVs and scattering the result.
4522 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4523 ubld
.MOV(res1
, brw_imm_d(0));
4524 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4525 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4526 BRW_PREDICATE_ALIGN1_ALL32H
,
4527 ubld
.MOV(res1
, brw_imm_d(-1)));
4529 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4532 case nir_intrinsic_vote_feq
:
4533 case nir_intrinsic_vote_ieq
: {
4534 fs_reg value
= get_nir_src(instr
->src
[0]);
4535 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4536 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4537 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4540 fs_reg uniformized
= bld
.emit_uniformize(value
);
4541 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4543 /* The any/all predicates do not consider channel enables. To prevent
4544 * dead channels from affecting the result, we initialize the flag with
4545 * with the identity value for the logical operation.
4547 if (dispatch_width
== 32) {
4548 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4549 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4550 brw_imm_ud(0xffffffff));
4552 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4554 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4556 /* For some reason, the any/all predicates don't work properly with
4557 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4558 * doesn't read the correct subset of the flag register and you end up
4559 * getting garbage in the second half. Work around this by using a pair
4560 * of 1-wide MOVs and scattering the result.
4562 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4563 ubld
.MOV(res1
, brw_imm_d(0));
4564 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4565 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4566 BRW_PREDICATE_ALIGN1_ALL32H
,
4567 ubld
.MOV(res1
, brw_imm_d(-1)));
4569 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4573 case nir_intrinsic_ballot
: {
4574 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4575 BRW_REGISTER_TYPE_UD
);
4576 struct brw_reg flag
= brw_flag_reg(0, 0);
4577 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4578 * as f0.0. This is a problem for fragment programs as we currently use
4579 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4580 * programs yet so this isn't a problem. When we do, something will
4583 if (dispatch_width
== 32)
4584 flag
.type
= BRW_REGISTER_TYPE_UD
;
4586 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4587 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4589 if (instr
->dest
.ssa
.bit_size
> 32) {
4590 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4592 dest
.type
= BRW_REGISTER_TYPE_UD
;
4594 bld
.MOV(dest
, flag
);
4598 case nir_intrinsic_read_invocation
: {
4599 const fs_reg value
= get_nir_src(instr
->src
[0]);
4600 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4601 fs_reg tmp
= bld
.vgrf(value
.type
);
4603 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4604 bld
.emit_uniformize(invocation
));
4606 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4610 case nir_intrinsic_read_first_invocation
: {
4611 const fs_reg value
= get_nir_src(instr
->src
[0]);
4612 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4616 case nir_intrinsic_shuffle
: {
4617 const fs_reg value
= get_nir_src(instr
->src
[0]);
4618 const fs_reg index
= get_nir_src(instr
->src
[1]);
4620 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4624 case nir_intrinsic_first_invocation
: {
4625 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4626 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4627 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4628 fs_reg(component(tmp
, 0)));
4632 case nir_intrinsic_quad_broadcast
: {
4633 const fs_reg value
= get_nir_src(instr
->src
[0]);
4634 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4636 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4637 value
, brw_imm_ud(index
), brw_imm_ud(4));
4641 case nir_intrinsic_quad_swap_horizontal
: {
4642 const fs_reg value
= get_nir_src(instr
->src
[0]);
4643 const fs_reg tmp
= bld
.vgrf(value
.type
);
4644 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4646 const fs_reg src_left
= horiz_stride(value
, 2);
4647 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4648 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4649 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4651 ubld
.MOV(tmp_left
, src_right
);
4652 ubld
.MOV(tmp_right
, src_left
);
4654 bld
.MOV(retype(dest
, value
.type
), tmp
);
4658 case nir_intrinsic_quad_swap_vertical
: {
4659 const fs_reg value
= get_nir_src(instr
->src
[0]);
4660 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4661 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4662 const fs_reg tmp
= bld
.vgrf(value
.type
);
4663 const fs_builder ubld
= bld
.exec_all();
4664 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4665 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4666 bld
.MOV(retype(dest
, value
.type
), tmp
);
4668 /* For larger data types, we have to either emit dispatch_width many
4669 * MOVs or else fall back to doing indirects.
4671 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4672 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4674 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4679 case nir_intrinsic_quad_swap_diagonal
: {
4680 const fs_reg value
= get_nir_src(instr
->src
[0]);
4681 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4682 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4683 const fs_reg tmp
= bld
.vgrf(value
.type
);
4684 const fs_builder ubld
= bld
.exec_all();
4685 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4686 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4687 bld
.MOV(retype(dest
, value
.type
), tmp
);
4689 /* For larger data types, we have to either emit dispatch_width many
4690 * MOVs or else fall back to doing indirects.
4692 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4693 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4695 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4700 case nir_intrinsic_reduce
: {
4701 fs_reg src
= get_nir_src(instr
->src
[0]);
4702 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4703 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4704 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4705 cluster_size
= dispatch_width
;
4707 /* Figure out the source type */
4708 src
.type
= brw_type_for_nir_type(devinfo
,
4709 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4710 nir_src_bit_size(instr
->src
[0])));
4712 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4713 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4714 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4716 /* Set up a register for all of our scratching around and initialize it
4717 * to reduction operation's identity value.
4719 fs_reg scan
= bld
.vgrf(src
.type
);
4720 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4722 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4724 dest
.type
= src
.type
;
4725 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4726 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4727 * the distance between clusters is at least 2 GRFs. In this case,
4728 * we don't need the weird striding of the CLUSTER_BROADCAST
4729 * instruction and can just do regular MOVs.
4731 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4732 const unsigned groups
=
4733 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4734 const unsigned group_size
= dispatch_width
/ groups
;
4735 for (unsigned i
= 0; i
< groups
; i
++) {
4736 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4737 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4738 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4739 component(scan
, comp
));
4742 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4743 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4748 case nir_intrinsic_inclusive_scan
:
4749 case nir_intrinsic_exclusive_scan
: {
4750 fs_reg src
= get_nir_src(instr
->src
[0]);
4751 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4753 /* Figure out the source type */
4754 src
.type
= brw_type_for_nir_type(devinfo
,
4755 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4756 nir_src_bit_size(instr
->src
[0])));
4758 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4759 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4760 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4762 /* Set up a register for all of our scratching around and initialize it
4763 * to reduction operation's identity value.
4765 fs_reg scan
= bld
.vgrf(src
.type
);
4766 const fs_builder allbld
= bld
.exec_all();
4767 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4769 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4770 /* Exclusive scan is a bit harder because we have to do an annoying
4771 * shift of the contents before we can begin. To make things worse,
4772 * we can't do this with a normal stride; we have to use indirects.
4774 fs_reg shifted
= bld
.vgrf(src
.type
);
4775 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4776 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4778 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4779 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4783 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4785 bld
.MOV(retype(dest
, src
.type
), scan
);
4789 case nir_intrinsic_begin_invocation_interlock
: {
4790 const fs_builder ubld
= bld
.group(8, 0);
4791 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4793 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4799 case nir_intrinsic_end_invocation_interlock
: {
4800 /* We don't need to do anything here */
4805 unreachable("unknown intrinsic");
4810 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4811 int op
, nir_intrinsic_instr
*instr
)
4813 if (stage
== MESA_SHADER_FRAGMENT
)
4814 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4817 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4818 dest
= get_nir_dest(instr
->dest
);
4820 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4821 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4822 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4823 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4824 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4827 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4828 data
= get_nir_src(instr
->src
[2]);
4830 if (op
== BRW_AOP_CMPWR
) {
4831 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4832 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4833 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4836 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4838 /* Emit the actual atomic operation */
4840 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4841 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4845 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4846 int op
, nir_intrinsic_instr
*instr
)
4848 if (stage
== MESA_SHADER_FRAGMENT
)
4849 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4852 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4853 dest
= get_nir_dest(instr
->dest
);
4855 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4856 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4857 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4858 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4859 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4861 fs_reg data
= get_nir_src(instr
->src
[2]);
4862 if (op
== BRW_AOP_FCMPWR
) {
4863 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4864 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4865 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4868 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4870 /* Emit the actual atomic operation */
4872 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4873 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4877 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4878 int op
, nir_intrinsic_instr
*instr
)
4881 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4882 dest
= get_nir_dest(instr
->dest
);
4884 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4885 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4886 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4887 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4890 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4891 data
= get_nir_src(instr
->src
[1]);
4892 if (op
== BRW_AOP_CMPWR
) {
4893 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4894 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4895 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4898 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4900 /* Get the offset */
4901 if (nir_src_is_const(instr
->src
[0])) {
4902 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4903 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4905 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4906 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4907 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4908 brw_imm_ud(instr
->const_index
[0]));
4911 /* Emit the actual atomic operation operation */
4913 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4914 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4918 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4919 int op
, nir_intrinsic_instr
*instr
)
4922 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4923 dest
= get_nir_dest(instr
->dest
);
4925 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4926 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4927 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4928 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4930 fs_reg data
= get_nir_src(instr
->src
[1]);
4931 if (op
== BRW_AOP_FCMPWR
) {
4932 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4933 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4934 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4937 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4939 /* Get the offset */
4940 if (nir_src_is_const(instr
->src
[0])) {
4941 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4942 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4944 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4945 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4946 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4947 brw_imm_ud(instr
->const_index
[0]));
4950 /* Emit the actual atomic operation operation */
4952 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4953 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4957 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
4958 int op
, nir_intrinsic_instr
*instr
)
4960 if (stage
== MESA_SHADER_FRAGMENT
)
4961 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4964 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4965 dest
= get_nir_dest(instr
->dest
);
4967 fs_reg addr
= get_nir_src(instr
->src
[0]);
4970 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4971 data
= get_nir_src(instr
->src
[1]);
4973 if (op
== BRW_AOP_CMPWR
) {
4974 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4975 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4976 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4980 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4981 dest
, addr
, data
, brw_imm_ud(op
));
4985 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
4986 int op
, nir_intrinsic_instr
*instr
)
4988 if (stage
== MESA_SHADER_FRAGMENT
)
4989 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4991 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
4992 fs_reg dest
= get_nir_dest(instr
->dest
);
4994 fs_reg addr
= get_nir_src(instr
->src
[0]);
4996 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
4997 fs_reg data
= get_nir_src(instr
->src
[1]);
4999 if (op
== BRW_AOP_FCMPWR
) {
5000 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5001 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5002 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5006 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5007 dest
, addr
, data
, brw_imm_ud(op
));
5011 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5013 unsigned texture
= instr
->texture_index
;
5014 unsigned sampler
= instr
->sampler_index
;
5016 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5018 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5019 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5021 int lod_components
= 0;
5023 /* The hardware requires a LOD for buffer textures */
5024 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5025 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5027 uint32_t header_bits
= 0;
5028 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5029 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5030 switch (instr
->src
[i
].src_type
) {
5031 case nir_tex_src_bias
:
5032 srcs
[TEX_LOGICAL_SRC_LOD
] =
5033 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5035 case nir_tex_src_comparator
:
5036 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5038 case nir_tex_src_coord
:
5039 switch (instr
->op
) {
5041 case nir_texop_txf_ms
:
5042 case nir_texop_txf_ms_mcs
:
5043 case nir_texop_samples_identical
:
5044 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5047 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5051 case nir_tex_src_ddx
:
5052 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5053 lod_components
= nir_tex_instr_src_size(instr
, i
);
5055 case nir_tex_src_ddy
:
5056 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5058 case nir_tex_src_lod
:
5059 switch (instr
->op
) {
5061 srcs
[TEX_LOGICAL_SRC_LOD
] =
5062 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5065 srcs
[TEX_LOGICAL_SRC_LOD
] =
5066 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5069 srcs
[TEX_LOGICAL_SRC_LOD
] =
5070 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5074 case nir_tex_src_min_lod
:
5075 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5076 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5078 case nir_tex_src_ms_index
:
5079 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5082 case nir_tex_src_offset
: {
5083 uint32_t offset_bits
= 0;
5084 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5085 header_bits
|= offset_bits
;
5087 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5088 retype(src
, BRW_REGISTER_TYPE_D
);
5093 case nir_tex_src_projector
:
5094 unreachable("should be lowered");
5096 case nir_tex_src_texture_offset
: {
5097 /* Emit code to evaluate the actual indexing expression */
5098 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5099 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5100 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5104 case nir_tex_src_sampler_offset
: {
5105 /* Emit code to evaluate the actual indexing expression */
5106 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5107 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5108 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5112 case nir_tex_src_ms_mcs
:
5113 assert(instr
->op
== nir_texop_txf_ms
);
5114 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5117 case nir_tex_src_plane
: {
5118 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5119 const uint32_t texture_index
=
5120 instr
->texture_index
+
5121 stage_prog_data
->binding_table
.plane_start
[plane
] -
5122 stage_prog_data
->binding_table
.texture_start
;
5124 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5129 unreachable("unknown texture source");
5133 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5134 (instr
->op
== nir_texop_txf_ms
||
5135 instr
->op
== nir_texop_samples_identical
)) {
5136 if (devinfo
->gen
>= 7 &&
5137 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5138 srcs
[TEX_LOGICAL_SRC_MCS
] =
5139 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5140 instr
->coord_components
,
5141 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5143 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5147 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5148 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5150 bool shader_supports_implicit_lod
= stage
== MESA_SHADER_FRAGMENT
||
5151 (stage
== MESA_SHADER_COMPUTE
&&
5152 nir
->info
.cs
.derivative_group
!= DERIVATIVE_GROUP_NONE
);
5155 switch (instr
->op
) {
5157 opcode
= shader_supports_implicit_lod
?
5158 SHADER_OPCODE_TEX_LOGICAL
: SHADER_OPCODE_TXL_LOGICAL
;
5161 opcode
= FS_OPCODE_TXB_LOGICAL
;
5164 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5167 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5170 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5172 case nir_texop_txf_ms
:
5173 if ((key_tex
->msaa_16
& (1 << sampler
)))
5174 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5176 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5178 case nir_texop_txf_ms_mcs
:
5179 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5181 case nir_texop_query_levels
:
5183 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5186 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5189 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5190 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5192 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5194 case nir_texop_texture_samples
:
5195 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5197 case nir_texop_samples_identical
: {
5198 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5200 /* If mcs is an immediate value, it means there is no MCS. In that case
5201 * just return false.
5203 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5204 bld
.MOV(dst
, brw_imm_ud(0u));
5205 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5206 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5207 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5208 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5209 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5211 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5212 BRW_CONDITIONAL_EQ
);
5217 unreachable("unknown texture opcode");
5220 if (instr
->op
== nir_texop_tg4
) {
5221 if (instr
->component
== 1 &&
5222 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5223 /* gather4 sampler is broken for green channel on RG32F --
5224 * we must ask for blue instead.
5226 header_bits
|= 2 << 16;
5228 header_bits
|= instr
->component
<< 16;
5232 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5233 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5234 inst
->offset
= header_bits
;
5236 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5237 if (devinfo
->gen
>= 9 &&
5238 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5239 unsigned write_mask
= instr
->dest
.is_ssa
?
5240 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5241 (1 << dest_size
) - 1;
5242 assert(write_mask
!= 0); /* dead code should have been eliminated */
5243 inst
->size_written
= util_last_bit(write_mask
) *
5244 inst
->dst
.component_size(inst
->exec_size
);
5246 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5249 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5250 inst
->shadow_compare
= true;
5252 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5253 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5256 for (unsigned i
= 0; i
< dest_size
; i
++)
5257 nir_dest
[i
] = offset(dst
, bld
, i
);
5259 if (instr
->op
== nir_texop_query_levels
) {
5260 /* # levels is in .w */
5261 nir_dest
[0] = offset(dst
, bld
, 3);
5262 } else if (instr
->op
== nir_texop_txs
&&
5263 dest_size
>= 3 && devinfo
->gen
< 7) {
5264 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5265 fs_reg depth
= offset(dst
, bld
, 2);
5266 nir_dest
[2] = vgrf(glsl_type::int_type
);
5267 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5270 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5274 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5276 switch (instr
->type
) {
5277 case nir_jump_break
:
5278 bld
.emit(BRW_OPCODE_BREAK
);
5280 case nir_jump_continue
:
5281 bld
.emit(BRW_OPCODE_CONTINUE
);
5283 case nir_jump_return
:
5285 unreachable("unknown jump");
5290 * This helper takes a source register and un/shuffles it into the destination
5293 * If source type size is smaller than destination type size the operation
5294 * needed is a component shuffle. The opposite case would be an unshuffle. If
5295 * source/destination type size is equal a shuffle is done that would be
5296 * equivalent to a simple MOV.
5298 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5299 * components .xyz 16-bit vector on SIMD8 would be.
5301 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5302 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5304 * This helper will return the following 2 32-bit components with the 16-bit
5307 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5308 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5310 * For unshuffle, the example would be the opposite, a 64-bit type source
5311 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5314 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5315 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5316 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5317 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5319 * The returned result would be the following 4 32-bit components unshuffled:
5321 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5322 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5323 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5324 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5326 * - Source and destination register must not be overlapped.
5327 * - components units are measured in terms of the smaller type between
5328 * source and destination because we are un/shuffling the smaller
5329 * components from/into the bigger ones.
5330 * - first_component parameter allows skipping source components.
5333 shuffle_src_to_dst(const fs_builder
&bld
,
5336 uint32_t first_component
,
5337 uint32_t components
)
5339 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5340 assert(!regions_overlap(dst
,
5341 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5342 offset(src
, bld
, first_component
),
5343 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5344 for (unsigned i
= 0; i
< components
; i
++) {
5345 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5346 offset(src
, bld
, i
+ first_component
));
5348 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5349 /* Source is shuffled into destination */
5350 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5351 assert(!regions_overlap(dst
,
5352 type_sz(dst
.type
) * bld
.dispatch_width() *
5353 DIV_ROUND_UP(components
, size_ratio
),
5354 offset(src
, bld
, first_component
),
5355 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5357 brw_reg_type shuffle_type
=
5358 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5359 BRW_REGISTER_TYPE_D
);
5360 for (unsigned i
= 0; i
< components
; i
++) {
5361 fs_reg shuffle_component_i
=
5362 subscript(offset(dst
, bld
, i
/ size_ratio
),
5363 shuffle_type
, i
% size_ratio
);
5364 bld
.MOV(shuffle_component_i
,
5365 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5368 /* Source is unshuffled into destination */
5369 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5370 assert(!regions_overlap(dst
,
5371 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5372 offset(src
, bld
, first_component
/ size_ratio
),
5373 type_sz(src
.type
) * bld
.dispatch_width() *
5374 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5377 brw_reg_type shuffle_type
=
5378 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5379 BRW_REGISTER_TYPE_D
);
5380 for (unsigned i
= 0; i
< components
; i
++) {
5381 fs_reg shuffle_component_i
=
5382 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5383 shuffle_type
, (first_component
+ i
) % size_ratio
);
5384 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5385 shuffle_component_i
);
5391 shuffle_from_32bit_read(const fs_builder
&bld
,
5394 uint32_t first_component
,
5395 uint32_t components
)
5397 assert(type_sz(src
.type
) == 4);
5399 /* This function takes components in units of the destination type while
5400 * shuffle_src_to_dst takes components in units of the smallest type
5402 if (type_sz(dst
.type
) > 4) {
5403 assert(type_sz(dst
.type
) == 8);
5404 first_component
*= 2;
5408 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5412 shuffle_for_32bit_write(const fs_builder
&bld
,
5414 uint32_t first_component
,
5415 uint32_t components
)
5417 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5418 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5419 /* This function takes components in units of the source type while
5420 * shuffle_src_to_dst takes components in units of the smallest type
5422 if (type_sz(src
.type
) > 4) {
5423 assert(type_sz(src
.type
) == 8);
5424 first_component
*= 2;
5428 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5434 setup_imm_df(const fs_builder
&bld
, double v
)
5436 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5437 assert(devinfo
->gen
>= 7);
5439 if (devinfo
->gen
>= 8)
5440 return brw_imm_df(v
);
5442 /* gen7.5 does not support DF immediates straighforward but the DIM
5443 * instruction allows to set the 64-bit immediate value.
5445 if (devinfo
->is_haswell
) {
5446 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5447 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5448 ubld
.DIM(dst
, brw_imm_df(v
));
5449 return component(dst
, 0);
5452 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5453 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5454 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5456 * Alternatively, we could also produce a normal VGRF (without stride 0)
5457 * by writing to all the channels in the VGRF, however, that would hit the
5458 * gen7 bug where we have to split writes that span more than 1 register
5459 * into instructions with a width of 4 (otherwise the write to the second
5460 * register written runs into an execmask hardware bug) which isn't very
5473 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5474 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5475 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5476 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5478 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5482 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5484 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5485 bld
.MOV(tmp
, brw_imm_w(v
));
5490 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5492 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5493 bld
.MOV(tmp
, brw_imm_uw(v
));