2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
45 last_scratch
= ALIGN(nir
->scratch_size
, 4) * dispatch_width
;
47 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
, true);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
) {
104 /* Add uniforms for builtins after regular NIR uniforms. */
105 assert(uniforms
== prog_data
->nr_params
);
108 if (nir
->info
.cs
.local_size_variable
) {
109 param
= brw_stage_prog_data_add_params(prog_data
, 3);
110 for (unsigned i
= 0; i
< 3; i
++) {
111 param
[i
] = (BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
+ i
);
112 group_size
[i
] = fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
116 /* Subgroup ID must be the last uniform on the list. This will make
117 * easier later to split between cross thread and per thread
120 param
= brw_stage_prog_data_add_params(prog_data
, 1);
121 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
122 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
127 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
131 nir_foreach_instr(instr
, block
) {
132 if (instr
->type
!= nir_instr_type_intrinsic
)
135 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
136 switch (intrin
->intrinsic
) {
137 case nir_intrinsic_load_vertex_id
:
138 case nir_intrinsic_load_base_vertex
:
139 unreachable("should be lowered by nir_lower_system_values().");
141 case nir_intrinsic_load_vertex_id_zero_base
:
142 case nir_intrinsic_load_is_indexed_draw
:
143 case nir_intrinsic_load_first_vertex
:
144 case nir_intrinsic_load_instance_id
:
145 case nir_intrinsic_load_base_instance
:
146 case nir_intrinsic_load_draw_id
:
147 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
149 case nir_intrinsic_load_invocation_id
:
150 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
152 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
153 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
154 if (reg
->file
== BAD_FILE
) {
155 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
156 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
157 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
158 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
163 case nir_intrinsic_load_sample_pos
:
164 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplepos_setup();
170 case nir_intrinsic_load_sample_id
:
171 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_sampleid_setup();
177 case nir_intrinsic_load_sample_mask_in
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 assert(v
->devinfo
->gen
>= 7);
180 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
181 if (reg
->file
== BAD_FILE
)
182 *reg
= *v
->emit_samplemaskin_setup();
185 case nir_intrinsic_load_work_group_id
:
186 assert(v
->stage
== MESA_SHADER_COMPUTE
);
187 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
188 if (reg
->file
== BAD_FILE
)
189 *reg
= *v
->emit_cs_work_group_id_setup();
192 case nir_intrinsic_load_helper_invocation
:
193 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
194 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
195 if (reg
->file
== BAD_FILE
) {
196 const fs_builder abld
=
197 v
->bld
.annotate("gl_HelperInvocation", NULL
);
199 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
200 * pixel mask is in g1.7 of the thread payload.
202 * We move the per-channel pixel enable bit to the low bit of each
203 * channel by shifting the byte containing the pixel mask by the
204 * vector immediate 0x76543210UV.
206 * The region of <1,8,0> reads only 1 byte (the pixel masks for
207 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
208 * masks for 2 and 3) in SIMD16.
210 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
212 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
213 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
214 hbld
.SHR(offset(shifted
, hbld
, i
),
215 stride(retype(brw_vec1_grf(1 + i
, 7),
216 BRW_REGISTER_TYPE_UB
),
218 brw_imm_v(0x76543210));
221 /* A set bit in the pixel mask means the channel is enabled, but
222 * that is the opposite of gl_HelperInvocation so we need to invert
225 * The negate source-modifier bit of logical instructions on Gen8+
226 * performs 1's complement negation, so we can use that instead of
229 fs_reg inverted
= negate(shifted
);
230 if (v
->devinfo
->gen
< 8) {
231 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
232 abld
.NOT(inverted
, shifted
);
235 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
236 * with 1 and negating.
238 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
239 abld
.AND(anded
, inverted
, brw_imm_uw(1));
241 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
242 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
256 fs_visitor::nir_emit_system_values()
258 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
259 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
260 nir_system_values
[i
] = fs_reg();
263 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
264 * never end up using it.
267 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
268 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
269 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
271 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
272 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
273 if (dispatch_width
> 8)
274 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
275 if (dispatch_width
> 16) {
276 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
277 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
281 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
282 nir_foreach_block(block
, impl
)
283 emit_system_values_block(block
, this);
287 * Returns a type based on a reference_type (word, float, half-float) and a
290 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
292 * @FIXME: 64-bit return types are always DF on integer types to maintain
293 * compability with uses of DF previously to the introduction of int64
297 brw_reg_type_from_bit_size(const unsigned bit_size
,
298 const brw_reg_type reference_type
)
300 switch(reference_type
) {
301 case BRW_REGISTER_TYPE_HF
:
302 case BRW_REGISTER_TYPE_F
:
303 case BRW_REGISTER_TYPE_DF
:
306 return BRW_REGISTER_TYPE_HF
;
308 return BRW_REGISTER_TYPE_F
;
310 return BRW_REGISTER_TYPE_DF
;
312 unreachable("Invalid bit size");
314 case BRW_REGISTER_TYPE_B
:
315 case BRW_REGISTER_TYPE_W
:
316 case BRW_REGISTER_TYPE_D
:
317 case BRW_REGISTER_TYPE_Q
:
320 return BRW_REGISTER_TYPE_B
;
322 return BRW_REGISTER_TYPE_W
;
324 return BRW_REGISTER_TYPE_D
;
326 return BRW_REGISTER_TYPE_Q
;
328 unreachable("Invalid bit size");
330 case BRW_REGISTER_TYPE_UB
:
331 case BRW_REGISTER_TYPE_UW
:
332 case BRW_REGISTER_TYPE_UD
:
333 case BRW_REGISTER_TYPE_UQ
:
336 return BRW_REGISTER_TYPE_UB
;
338 return BRW_REGISTER_TYPE_UW
;
340 return BRW_REGISTER_TYPE_UD
;
342 return BRW_REGISTER_TYPE_UQ
;
344 unreachable("Invalid bit size");
347 unreachable("Unknown type");
352 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
354 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
355 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
356 nir_locals
[i
] = fs_reg();
359 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
360 unsigned array_elems
=
361 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
362 unsigned size
= array_elems
* reg
->num_components
;
363 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
364 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
365 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
368 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
371 nir_emit_cf_list(&impl
->body
);
375 fs_visitor::nir_emit_cf_list(exec_list
*list
)
377 exec_list_validate(list
);
378 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
379 switch (node
->type
) {
381 nir_emit_if(nir_cf_node_as_if(node
));
384 case nir_cf_node_loop
:
385 nir_emit_loop(nir_cf_node_as_loop(node
));
388 case nir_cf_node_block
:
389 nir_emit_block(nir_cf_node_as_block(node
));
393 unreachable("Invalid CFG node block");
399 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
404 /* If the condition has the form !other_condition, use other_condition as
405 * the source, but invert the predicate on the if instruction.
407 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
408 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
410 cond_reg
= get_nir_src(cond
->src
[0].src
);
413 cond_reg
= get_nir_src(if_stmt
->condition
);
416 /* first, put the condition into f0 */
417 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
418 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
419 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
421 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
423 nir_emit_cf_list(&if_stmt
->then_list
);
425 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
426 bld
.emit(BRW_OPCODE_ELSE
);
427 nir_emit_cf_list(&if_stmt
->else_list
);
430 bld
.emit(BRW_OPCODE_ENDIF
);
432 if (devinfo
->gen
< 7)
433 limit_dispatch_width(16, "Non-uniform control flow unsupported "
438 fs_visitor::nir_emit_loop(nir_loop
*loop
)
440 bld
.emit(BRW_OPCODE_DO
);
442 nir_emit_cf_list(&loop
->body
);
444 bld
.emit(BRW_OPCODE_WHILE
);
446 if (devinfo
->gen
< 7)
447 limit_dispatch_width(16, "Non-uniform control flow unsupported "
452 fs_visitor::nir_emit_block(nir_block
*block
)
454 nir_foreach_instr(instr
, block
) {
455 nir_emit_instr(instr
);
460 fs_visitor::nir_emit_instr(nir_instr
*instr
)
462 const fs_builder abld
= bld
.annotate(NULL
, instr
);
464 switch (instr
->type
) {
465 case nir_instr_type_alu
:
466 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
469 case nir_instr_type_deref
:
470 unreachable("All derefs should've been lowered");
473 case nir_instr_type_intrinsic
:
475 case MESA_SHADER_VERTEX
:
476 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 case MESA_SHADER_TESS_CTRL
:
479 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
481 case MESA_SHADER_TESS_EVAL
:
482 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
484 case MESA_SHADER_GEOMETRY
:
485 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
487 case MESA_SHADER_FRAGMENT
:
488 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
490 case MESA_SHADER_COMPUTE
:
491 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
494 unreachable("unsupported shader stage");
498 case nir_instr_type_tex
:
499 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
502 case nir_instr_type_load_const
:
503 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
506 case nir_instr_type_ssa_undef
:
507 /* We create a new VGRF for undefs on every use (by handling
508 * them in get_nir_src()), rather than for each definition.
509 * This helps register coalescing eliminate MOVs from undef.
513 case nir_instr_type_jump
:
514 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
518 unreachable("unknown instruction type");
523 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
527 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
528 const fs_reg
&result
)
530 if (!instr
->src
[0].src
.is_ssa
||
531 !instr
->src
[0].src
.ssa
->parent_instr
)
534 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
537 nir_alu_instr
*src0
=
538 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
540 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
541 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
544 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
546 /* Element type to extract.*/
547 const brw_reg_type type
= brw_int_type(
548 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
549 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
551 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
552 op0
.type
= brw_type_for_nir_type(devinfo
,
553 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
554 nir_src_bit_size(src0
->src
[0].src
)));
555 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
557 bld
.MOV(result
, subscript(op0
, type
, element
));
562 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
563 const fs_reg
&result
)
565 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
566 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
569 if (!nir_src_is_const(instr
->src
[1].src
) ||
570 !nir_src_is_const(instr
->src
[2].src
))
573 const float value1
= nir_src_as_float(instr
->src
[1].src
);
574 const float value2
= nir_src_as_float(instr
->src
[2].src
);
575 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
578 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
579 assert(value1
== -value2
);
581 fs_reg tmp
= vgrf(glsl_type::int_type
);
583 if (devinfo
->gen
>= 12) {
584 /* Bit 15 of g1.1 is 0 if the polygon is front facing. */
585 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
587 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
589 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
590 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
592 * and negate the result for (gl_FrontFacing ? -1.0 : 1.0).
594 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
595 g1
, brw_imm_uw(0x3f80));
598 bld
.MOV(tmp
, negate(tmp
));
600 } else if (devinfo
->gen
>= 6) {
601 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
602 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
604 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
606 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
607 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
609 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
611 * This negation looks like it's safe in practice, because bits 0:4 will
612 * surely be TRIANGLES
615 if (value1
== -1.0f
) {
619 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
620 g0
, brw_imm_uw(0x3f80));
622 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
623 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
625 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
627 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
628 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
630 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
632 * This negation looks like it's safe in practice, because bits 0:4 will
633 * surely be TRIANGLES
636 if (value1
== -1.0f
) {
640 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
642 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
648 emit_find_msb_using_lzd(const fs_builder
&bld
,
649 const fs_reg
&result
,
657 /* LZD of an absolute value source almost always does the right
658 * thing. There are two problem values:
660 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
661 * 0. However, findMSB(int(0x80000000)) == 30.
663 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
664 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
666 * For a value of zero or negative one, -1 will be returned.
668 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
669 * findMSB(-(1<<x)) should return x-1.
671 * For all negative number cases, including 0x80000000 and
672 * 0xffffffff, the correct value is obtained from LZD if instead of
673 * negating the (already negative) value the logical-not is used. A
674 * conditonal logical-not can be achieved in two instructions.
676 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
678 bld
.ASR(temp
, src
, brw_imm_d(31));
679 bld
.XOR(temp
, temp
, src
);
682 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
683 retype(temp
, BRW_REGISTER_TYPE_UD
));
685 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
686 * from the LSB side. Subtract the result from 31 to convert the MSB
687 * count into an LSB count. If no bits are set, LZD will return 32.
688 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
690 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
691 inst
->src
[0].negate
= true;
695 brw_rnd_mode_from_nir_op (const nir_op op
) {
697 case nir_op_f2f16_rtz
:
698 return BRW_RND_MODE_RTZ
;
699 case nir_op_f2f16_rtne
:
700 return BRW_RND_MODE_RTNE
;
702 unreachable("Operation doesn't support rounding mode");
707 brw_rnd_mode_from_execution_mode(unsigned execution_mode
)
709 if (nir_has_any_rounding_mode_rtne(execution_mode
))
710 return BRW_RND_MODE_RTNE
;
711 if (nir_has_any_rounding_mode_rtz(execution_mode
))
712 return BRW_RND_MODE_RTZ
;
713 return BRW_RND_MODE_UNSPECIFIED
;
717 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
718 nir_alu_instr
*instr
,
723 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
725 result
.type
= brw_type_for_nir_type(devinfo
,
726 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
727 nir_dest_bit_size(instr
->dest
.dest
)));
729 assert(!instr
->dest
.saturate
);
731 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
732 /* We don't lower to source modifiers so they should not exist. */
733 assert(!instr
->src
[i
].abs
);
734 assert(!instr
->src
[i
].negate
);
736 op
[i
] = get_nir_src(instr
->src
[i
].src
);
737 op
[i
].type
= brw_type_for_nir_type(devinfo
,
738 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
739 nir_src_bit_size(instr
->src
[i
].src
)));
742 /* Move and vecN instrutions may still be vectored. Return the raw,
743 * vectored source and destination so that fs_visitor::nir_emit_alu can
744 * handle it. Other callers should not have to handle these kinds of
757 /* At this point, we have dealt with any instruction that operates on
758 * more than a single channel. Therefore, we can just adjust the source
759 * and destination registers for that channel and emit the instruction.
761 unsigned channel
= 0;
762 if (nir_op_infos
[instr
->op
].output_size
== 0) {
763 /* Since NIR is doing the scalarizing for us, we should only ever see
764 * vectorized operations with a single channel.
766 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
767 channel
= ffs(instr
->dest
.write_mask
) - 1;
769 result
= offset(result
, bld
, channel
);
772 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
773 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
774 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
781 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
784 for (unsigned i
= 0; i
< 2; i
++) {
785 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
787 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
) {
788 /* The source of the inot is now the source of instr. */
789 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
791 assert(!op
[i
].negate
);
794 op
[i
] = resolve_source_modifiers(op
[i
]);
800 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
802 nir_alu_instr
*instr
)
804 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
807 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
809 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
812 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
813 * of valid size-changing combinations is a bit more complex.
815 * The source restriction is just because I was lazy about generating the
818 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
819 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
822 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
823 * this is float(1 + a).
827 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
829 /* Ignore the saturate modifier, if there is one. The result of the
830 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
832 bld
.ADD(result
, op
, brw_imm_d(1));
838 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
840 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
841 * the source of \c instr that is a \c nir_op_fsign.
844 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
845 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
849 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
850 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
852 if (instr
->op
!= nir_op_fsign
) {
853 const nir_alu_instr
*const fsign_instr
=
854 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
856 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
857 * fsign_src] has the other multiply source. This must be rearranged so
858 * that op[0] is the source of the fsign op[1] is the other multiply
864 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
866 const nir_alu_type t
=
867 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
868 nir_src_bit_size(fsign_instr
->src
[0].src
));
870 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
872 unsigned channel
= 0;
873 if (nir_op_infos
[instr
->op
].output_size
== 0) {
874 /* Since NIR is doing the scalarizing for us, we should only ever see
875 * vectorized operations with a single channel.
877 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
878 channel
= ffs(instr
->dest
.write_mask
) - 1;
881 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
884 if (type_sz(op
[0].type
) == 2) {
885 /* AND(val, 0x8000) gives the sign bit.
887 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
889 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
890 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
892 op
[0].type
= BRW_REGISTER_TYPE_UW
;
893 result
.type
= BRW_REGISTER_TYPE_UW
;
894 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
896 if (instr
->op
== nir_op_fsign
)
897 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
899 /* Use XOR here to get the result sign correct. */
900 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
903 inst
->predicate
= BRW_PREDICATE_NORMAL
;
904 } else if (type_sz(op
[0].type
) == 4) {
905 /* AND(val, 0x80000000) gives the sign bit.
907 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
910 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
912 op
[0].type
= BRW_REGISTER_TYPE_UD
;
913 result
.type
= BRW_REGISTER_TYPE_UD
;
914 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
916 if (instr
->op
== nir_op_fsign
)
917 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
919 /* Use XOR here to get the result sign correct. */
920 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
923 inst
->predicate
= BRW_PREDICATE_NORMAL
;
925 /* For doubles we do the same but we need to consider:
927 * - 2-src instructions can't operate with 64-bit immediates
928 * - The sign is encoded in the high 32-bit of each DF
929 * - We need to produce a DF result.
932 fs_reg zero
= vgrf(glsl_type::double_type
);
933 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
934 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
936 bld
.MOV(result
, zero
);
938 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
939 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
940 brw_imm_ud(0x80000000u
));
942 if (instr
->op
== nir_op_fsign
) {
943 set_predicate(BRW_PREDICATE_NORMAL
,
944 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
946 /* This could be done better in some cases. If the scale is an
947 * immediate with the low 32-bits all 0, emitting a separate XOR and
948 * OR would allow an algebraic optimization to remove the OR. There
949 * are currently zero instances of fsign(double(x))*IMM in shader-db
950 * or any test suite, so it is hard to care at this time.
952 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
953 inst
= bld
.XOR(result_int64
, result_int64
,
954 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
960 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
962 * Checks the operands of a \c nir_op_fmul to determine whether or not
963 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
965 * \param instr The multiplication instruction
967 * \param fsign_src The source of \c instr that may or may not be a
971 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
973 assert(instr
->op
== nir_op_fmul
);
975 nir_alu_instr
*const fsign_instr
=
976 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
980 * 1. instr->src[fsign_src] must be a nir_op_fsign.
981 * 2. The nir_op_fsign can only be used by this multiplication.
982 * 3. The source that is the nir_op_fsign does not have source modifiers.
983 * \c emit_fsign only examines the source modifiers of the source of the
986 * The nir_op_fsign must also not have the saturate modifier, but steps
987 * have already been taken (in nir_opt_algebraic) to ensure that.
989 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
990 is_used_once(fsign_instr
);
994 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
997 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
999 unsigned execution_mode
=
1000 bld
.shader
->nir
->info
.float_controls_execution_mode
;
1003 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1005 switch (instr
->op
) {
1010 fs_reg temp
= result
;
1011 bool need_extra_copy
= false;
1012 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1013 if (!instr
->src
[i
].src
.is_ssa
&&
1014 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1015 need_extra_copy
= true;
1016 temp
= bld
.vgrf(result
.type
, 4);
1021 for (unsigned i
= 0; i
< 4; i
++) {
1022 if (!(instr
->dest
.write_mask
& (1 << i
)))
1025 if (instr
->op
== nir_op_mov
) {
1026 inst
= bld
.MOV(offset(temp
, bld
, i
),
1027 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1029 inst
= bld
.MOV(offset(temp
, bld
, i
),
1030 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1034 /* In this case the source and destination registers were the same,
1035 * so we need to insert an extra set of moves in order to deal with
1038 if (need_extra_copy
) {
1039 for (unsigned i
= 0; i
< 4; i
++) {
1040 if (!(instr
->dest
.write_mask
& (1 << i
)))
1043 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1051 if (optimize_extract_to_float(instr
, result
))
1053 inst
= bld
.MOV(result
, op
[0]);
1056 case nir_op_f2f16_rtne
:
1057 case nir_op_f2f16_rtz
:
1058 case nir_op_f2f16
: {
1059 brw_rnd_mode rnd
= BRW_RND_MODE_UNSPECIFIED
;
1061 if (nir_op_f2f16
== instr
->op
)
1062 rnd
= brw_rnd_mode_from_execution_mode(execution_mode
);
1064 rnd
= brw_rnd_mode_from_nir_op(instr
->op
);
1066 if (BRW_RND_MODE_UNSPECIFIED
!= rnd
)
1067 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(), brw_imm_d(rnd
));
1069 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1070 * on the HW gen, it is a special hw opcode or just a MOV, and
1071 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1073 * But if we want to use that opcode, we need to provide support on
1074 * different optimizations and lowerings. As right now HF support is
1075 * only for gen8+, it will be better to use directly the MOV, and use
1076 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1078 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1079 inst
= bld
.MOV(result
, op
[0]);
1090 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1092 op
[0].type
= BRW_REGISTER_TYPE_D
;
1093 op
[0].negate
= !op
[0].negate
;
1116 if (result
.type
== BRW_REGISTER_TYPE_B
||
1117 result
.type
== BRW_REGISTER_TYPE_UB
||
1118 result
.type
== BRW_REGISTER_TYPE_HF
)
1119 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1121 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1122 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1123 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1124 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1126 inst
= bld
.MOV(result
, op
[0]);
1130 inst
= bld
.MOV(result
, op
[0]);
1131 inst
->saturate
= true;
1136 op
[0].negate
= true;
1137 inst
= bld
.MOV(result
, op
[0]);
1142 op
[0].negate
= false;
1144 inst
= bld
.MOV(result
, op
[0]);
1148 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1150 brw_rnd_mode_from_execution_mode(execution_mode
);
1151 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1155 if (op
[0].type
== BRW_REGISTER_TYPE_HF
)
1156 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1158 inst
= bld
.MOV(result
, op
[0]);
1162 emit_fsign(bld
, instr
, result
, op
, 0);
1166 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1170 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1174 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1178 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1182 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1186 if (fs_key
->high_quality_derivatives
) {
1187 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1189 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1192 case nir_op_fddx_fine
:
1193 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1195 case nir_op_fddx_coarse
:
1196 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1199 if (fs_key
->high_quality_derivatives
) {
1200 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1202 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1205 case nir_op_fddy_fine
:
1206 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1208 case nir_op_fddy_coarse
:
1209 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1213 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1215 brw_rnd_mode_from_execution_mode(execution_mode
);
1216 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1221 inst
= bld
.ADD(result
, op
[0], op
[1]);
1224 case nir_op_iadd_sat
:
1225 case nir_op_uadd_sat
:
1226 inst
= bld
.ADD(result
, op
[0], op
[1]);
1227 inst
->saturate
= true;
1230 case nir_op_isub_sat
:
1231 bld
.emit(SHADER_OPCODE_ISUB_SAT
, result
, op
[0], op
[1]);
1234 case nir_op_usub_sat
:
1235 bld
.emit(SHADER_OPCODE_USUB_SAT
, result
, op
[0], op
[1]);
1240 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1241 inst
= bld
.AVG(result
, op
[0], op
[1]);
1245 case nir_op_uhadd
: {
1246 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1247 fs_reg tmp
= bld
.vgrf(result
.type
);
1249 if (devinfo
->gen
>= 8) {
1250 op
[0] = resolve_source_modifiers(op
[0]);
1251 op
[1] = resolve_source_modifiers(op
[1]);
1254 /* AVG(x, y) - ((x ^ y) & 1) */
1255 bld
.XOR(tmp
, op
[0], op
[1]);
1256 bld
.AND(tmp
, tmp
, retype(brw_imm_ud(1), result
.type
));
1257 bld
.AVG(result
, op
[0], op
[1]);
1258 inst
= bld
.ADD(result
, result
, tmp
);
1259 inst
->src
[1].negate
= true;
1264 for (unsigned i
= 0; i
< 2; i
++) {
1265 if (can_fuse_fmul_fsign(instr
, i
)) {
1266 emit_fsign(bld
, instr
, result
, op
, i
);
1271 /* We emit the rounding mode after the previous fsign optimization since
1272 * it won't result in a MUL, but will try to negate the value by other
1275 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1277 brw_rnd_mode_from_execution_mode(execution_mode
);
1278 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1282 inst
= bld
.MUL(result
, op
[0], op
[1]);
1285 case nir_op_imul_2x32_64
:
1286 case nir_op_umul_2x32_64
:
1287 bld
.MUL(result
, op
[0], op
[1]);
1290 case nir_op_imul_32x16
:
1291 case nir_op_umul_32x16
: {
1292 const bool ud
= instr
->op
== nir_op_umul_32x16
;
1294 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1296 /* Before Gen7, the order of the 32-bit source and the 16-bit source was
1297 * swapped. The extension isn't enabled on those platforms, so don't
1298 * pretend to support the differences.
1300 assert(devinfo
->gen
>= 7);
1302 if (op
[1].file
== IMM
)
1303 op
[1] = ud
? brw_imm_uw(op
[1].ud
) : brw_imm_w(op
[1].d
);
1305 const enum brw_reg_type word_type
=
1306 ud
? BRW_REGISTER_TYPE_UW
: BRW_REGISTER_TYPE_W
;
1308 op
[1] = subscript(op
[1], word_type
, 0);
1311 const enum brw_reg_type dword_type
=
1312 ud
? BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_D
;
1314 bld
.MUL(result
, retype(op
[0], dword_type
), op
[1]);
1319 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1320 bld
.MUL(result
, op
[0], op
[1]);
1323 case nir_op_imul_high
:
1324 case nir_op_umul_high
:
1325 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1326 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1331 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1332 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1335 case nir_op_uadd_carry
:
1336 unreachable("Should have been lowered by carry_to_arith().");
1338 case nir_op_usub_borrow
:
1339 unreachable("Should have been lowered by borrow_to_arith().");
1343 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1344 * appears that our hardware just does the right thing for signed
1347 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1348 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1352 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1353 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1355 /* Math instructions don't support conditional mod */
1356 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1357 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1359 /* Now, we need to determine if signs of the sources are different.
1360 * When we XOR the sources, the top bit is 0 if they are the same and 1
1361 * if they are different. We can then use a conditional modifier to
1362 * turn that into a predicate. This leads us to an XOR.l instruction.
1364 * Technically, according to the PRM, you're not allowed to use .l on a
1365 * XOR instruction. However, emperical experiments and Curro's reading
1366 * of the simulator source both indicate that it's safe.
1368 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1369 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1370 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1371 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1373 /* If the result of the initial remainder operation is non-zero and the
1374 * two sources have different signs, add in a copy of op[1] to get the
1375 * final integer modulus value.
1377 inst
= bld
.ADD(result
, result
, op
[1]);
1378 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1385 case nir_op_fne32
: {
1386 fs_reg dest
= result
;
1388 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1390 dest
= bld
.vgrf(op
[0].type
, 1);
1392 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1394 if (bit_size
> 32) {
1395 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1396 } else if(bit_size
< 32) {
1397 /* When we convert the result to 32-bit we need to be careful and do
1398 * it as a signed conversion to get sign extension (for 32-bit true)
1400 const brw_reg_type src_type
=
1401 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1403 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1413 case nir_op_ine32
: {
1414 fs_reg dest
= result
;
1416 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1417 * type. So we convert both operands for the comparison.
1420 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1421 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1423 const uint32_t bit_size
= type_sz(temp_op
[0].type
) * 8;
1425 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1427 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1428 brw_cmod_for_nir_comparison(instr
->op
));
1430 if (bit_size
> 32) {
1431 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1432 } else if (bit_size
< 32) {
1433 /* When we convert the result to 32-bit we need to be careful and do
1434 * it as a signed conversion to get sign extension (for 32-bit true)
1436 const brw_reg_type src_type
=
1437 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1439 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1445 if (devinfo
->gen
>= 8) {
1446 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1448 if (inot_src_instr
!= NULL
&&
1449 (inot_src_instr
->op
== nir_op_ior
||
1450 inot_src_instr
->op
== nir_op_ixor
||
1451 inot_src_instr
->op
== nir_op_iand
)) {
1452 /* The sources of the source logical instruction are now the
1453 * sources of the instruction that will be generated.
1455 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1456 resolve_inot_sources(bld
, inot_src_instr
, op
);
1458 /* Smash all of the sources and destination to be signed. This
1459 * doesn't matter for the operation of the instruction, but cmod
1460 * propagation fails on unsigned sources with negation (due to
1461 * fs_inst::can_do_cmod returning false).
1464 brw_type_for_nir_type(devinfo
,
1465 (nir_alu_type
)(nir_type_int
|
1466 nir_dest_bit_size(instr
->dest
.dest
)));
1468 brw_type_for_nir_type(devinfo
,
1469 (nir_alu_type
)(nir_type_int
|
1470 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1472 brw_type_for_nir_type(devinfo
,
1473 (nir_alu_type
)(nir_type_int
|
1474 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1476 /* For XOR, only invert one of the sources. Arbitrarily choose
1479 op
[0].negate
= !op
[0].negate
;
1480 if (inot_src_instr
->op
!= nir_op_ixor
)
1481 op
[1].negate
= !op
[1].negate
;
1483 switch (inot_src_instr
->op
) {
1485 bld
.AND(result
, op
[0], op
[1]);
1489 bld
.OR(result
, op
[0], op
[1]);
1493 bld
.XOR(result
, op
[0], op
[1]);
1497 unreachable("impossible opcode");
1500 op
[0] = resolve_source_modifiers(op
[0]);
1502 bld
.NOT(result
, op
[0]);
1505 if (devinfo
->gen
>= 8) {
1506 resolve_inot_sources(bld
, instr
, op
);
1508 bld
.XOR(result
, op
[0], op
[1]);
1511 if (devinfo
->gen
>= 8) {
1512 resolve_inot_sources(bld
, instr
, op
);
1514 bld
.OR(result
, op
[0], op
[1]);
1517 if (devinfo
->gen
>= 8) {
1518 resolve_inot_sources(bld
, instr
, op
);
1520 bld
.AND(result
, op
[0], op
[1]);
1526 case nir_op_b32all_fequal2
:
1527 case nir_op_b32all_iequal2
:
1528 case nir_op_b32all_fequal3
:
1529 case nir_op_b32all_iequal3
:
1530 case nir_op_b32all_fequal4
:
1531 case nir_op_b32all_iequal4
:
1532 case nir_op_b32any_fnequal2
:
1533 case nir_op_b32any_inequal2
:
1534 case nir_op_b32any_fnequal3
:
1535 case nir_op_b32any_inequal3
:
1536 case nir_op_b32any_fnequal4
:
1537 case nir_op_b32any_inequal4
:
1538 unreachable("Lowered by nir_lower_alu_reductions");
1541 unreachable("not reached: should be handled by ldexp_to_arith()");
1544 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1548 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1552 case nir_op_f2b32
: {
1553 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1554 if (bit_size
== 64) {
1555 /* two-argument instructions can't take 64-bit immediates */
1559 if (instr
->op
== nir_op_f2b32
) {
1560 zero
= vgrf(glsl_type::double_type
);
1561 tmp
= vgrf(glsl_type::double_type
);
1562 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1564 zero
= vgrf(glsl_type::int64_t_type
);
1565 tmp
= vgrf(glsl_type::int64_t_type
);
1566 bld
.MOV(zero
, brw_imm_q(0));
1569 /* A SIMD16 execution needs to be split in two instructions, so use
1570 * a vgrf instead of the flag register as dst so instruction splitting
1573 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1574 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1577 if (bit_size
== 32) {
1578 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1580 assert(bit_size
== 16);
1581 zero
= instr
->op
== nir_op_f2b32
?
1582 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1584 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1590 inst
= bld
.RNDZ(result
, op
[0]);
1591 if (devinfo
->gen
< 6) {
1592 set_condmod(BRW_CONDITIONAL_R
, inst
);
1593 set_predicate(BRW_PREDICATE_NORMAL
,
1594 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1595 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1599 case nir_op_fceil
: {
1600 op
[0].negate
= !op
[0].negate
;
1601 fs_reg temp
= vgrf(glsl_type::float_type
);
1602 bld
.RNDD(temp
, op
[0]);
1604 inst
= bld
.MOV(result
, temp
);
1608 inst
= bld
.RNDD(result
, op
[0]);
1611 inst
= bld
.FRC(result
, op
[0]);
1613 case nir_op_fround_even
:
1614 inst
= bld
.RNDE(result
, op
[0]);
1615 if (devinfo
->gen
< 6) {
1616 set_condmod(BRW_CONDITIONAL_R
, inst
);
1617 set_predicate(BRW_PREDICATE_NORMAL
,
1618 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1619 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1623 case nir_op_fquantize2f16
: {
1624 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1625 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1626 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1628 /* The destination stride must be at least as big as the source stride. */
1629 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1632 /* Check for denormal */
1633 fs_reg abs_src0
= op
[0];
1634 abs_src0
.abs
= true;
1635 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1637 /* Get the appropriately signed zero */
1638 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1639 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1640 brw_imm_ud(0x80000000));
1641 /* Do the actual F32 -> F16 -> F32 conversion */
1642 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1643 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1644 /* Select that or zero based on normal status */
1645 inst
= bld
.SEL(result
, zero
, tmp32
);
1646 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1653 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1659 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1662 case nir_op_pack_snorm_2x16
:
1663 case nir_op_pack_snorm_4x8
:
1664 case nir_op_pack_unorm_2x16
:
1665 case nir_op_pack_unorm_4x8
:
1666 case nir_op_unpack_snorm_2x16
:
1667 case nir_op_unpack_snorm_4x8
:
1668 case nir_op_unpack_unorm_2x16
:
1669 case nir_op_unpack_unorm_4x8
:
1670 case nir_op_unpack_half_2x16
:
1671 case nir_op_pack_half_2x16
:
1672 unreachable("not reached: should be handled by lower_packing_builtins");
1674 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1675 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1677 case nir_op_unpack_half_2x16_split_x
:
1678 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1679 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1682 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1683 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1685 case nir_op_unpack_half_2x16_split_y
:
1686 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1687 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1690 case nir_op_pack_64_2x32_split
:
1691 case nir_op_pack_32_2x16_split
:
1692 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1695 case nir_op_unpack_64_2x32_split_x
:
1696 case nir_op_unpack_64_2x32_split_y
: {
1697 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1698 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1700 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1704 case nir_op_unpack_32_2x16_split_x
:
1705 case nir_op_unpack_32_2x16_split_y
: {
1706 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1707 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1709 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1714 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1717 case nir_op_bitfield_reverse
:
1718 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1719 bld
.BFREV(result
, op
[0]);
1722 case nir_op_bit_count
:
1723 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1724 bld
.CBIT(result
, op
[0]);
1727 case nir_op_ufind_msb
: {
1728 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1729 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1734 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1735 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1738 case nir_op_ifind_msb
: {
1739 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1741 if (devinfo
->gen
< 7) {
1742 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1744 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1746 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1747 * count from the LSB side. If FBH didn't return an error
1748 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1749 * count into an LSB count.
1751 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1753 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1754 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1755 inst
->src
[0].negate
= true;
1760 case nir_op_find_lsb
:
1761 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1763 if (devinfo
->gen
< 7) {
1764 fs_reg temp
= vgrf(glsl_type::int_type
);
1766 /* (x & -x) generates a value that consists of only the LSB of x.
1767 * For all powers of 2, findMSB(y) == findLSB(y).
1769 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1770 fs_reg negated_src
= src
;
1772 /* One must be negated, and the other must be non-negated. It
1773 * doesn't matter which is which.
1775 negated_src
.negate
= true;
1778 bld
.AND(temp
, src
, negated_src
);
1779 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1781 bld
.FBL(result
, op
[0]);
1785 case nir_op_ubitfield_extract
:
1786 case nir_op_ibitfield_extract
:
1787 unreachable("should have been lowered");
1790 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1791 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1794 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1795 bld
.BFI1(result
, op
[0], op
[1]);
1798 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1799 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1802 case nir_op_bitfield_insert
:
1803 unreachable("not reached: should have been lowered");
1806 bld
.SHL(result
, op
[0], op
[1]);
1809 bld
.ASR(result
, op
[0], op
[1]);
1812 bld
.SHR(result
, op
[0], op
[1]);
1816 bld
.ROL(result
, op
[0], op
[1]);
1819 bld
.ROR(result
, op
[0], op
[1]);
1822 case nir_op_pack_half_2x16_split
:
1823 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1827 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1829 brw_rnd_mode_from_execution_mode(execution_mode
);
1830 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1834 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1838 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1840 brw_rnd_mode_from_execution_mode(execution_mode
);
1841 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1845 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1848 case nir_op_b32csel
:
1849 if (optimize_frontfacing_ternary(instr
, result
))
1852 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1853 inst
= bld
.SEL(result
, op
[1], op
[2]);
1854 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1857 case nir_op_extract_u8
:
1858 case nir_op_extract_i8
: {
1859 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1864 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1865 * Use two instructions and a word or DWord intermediate integer type.
1867 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1868 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1870 if (instr
->op
== nir_op_extract_i8
) {
1871 /* If we need to sign extend, extract to a word first */
1872 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1873 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1874 bld
.MOV(result
, w_temp
);
1875 } else if (byte
& 1) {
1876 /* Extract the high byte from the word containing the desired byte
1880 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1883 /* Otherwise use an AND with 0xff and a word type */
1885 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1889 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1890 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1895 case nir_op_extract_u16
:
1896 case nir_op_extract_i16
: {
1897 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1898 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1899 bld
.MOV(result
, subscript(op
[0], type
, word
));
1904 unreachable("unhandled instruction");
1907 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1908 * to sign extend the low bit to 0/~0
1910 if (devinfo
->gen
<= 5 &&
1911 !result
.is_null() &&
1912 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1913 fs_reg masked
= vgrf(glsl_type::int_type
);
1914 bld
.AND(masked
, result
, brw_imm_d(1));
1915 masked
.negate
= true;
1916 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1921 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1922 nir_load_const_instr
*instr
)
1924 const brw_reg_type reg_type
=
1925 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1926 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1928 switch (instr
->def
.bit_size
) {
1930 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1931 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1935 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1936 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1940 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1941 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1945 assert(devinfo
->gen
>= 7);
1946 if (devinfo
->gen
== 7) {
1947 /* We don't get 64-bit integer types until gen8 */
1948 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1949 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1950 setup_imm_df(bld
, instr
->value
[i
].f64
));
1953 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1954 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1959 unreachable("Invalid bit size");
1962 nir_ssa_values
[instr
->def
.index
] = reg
;
1966 fs_visitor::get_nir_src(const nir_src
&src
)
1970 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1971 const brw_reg_type reg_type
=
1972 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1973 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1975 reg
= nir_ssa_values
[src
.ssa
->index
];
1978 /* We don't handle indirects on locals */
1979 assert(src
.reg
.indirect
== NULL
);
1980 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1981 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1984 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1985 /* The only 64-bit type available on gen7 is DF, so use that. */
1986 reg
.type
= BRW_REGISTER_TYPE_DF
;
1988 /* To avoid floating-point denorm flushing problems, set the type by
1989 * default to an integer type - instructions that need floating point
1990 * semantics will set this to F if they need to
1992 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1993 BRW_REGISTER_TYPE_D
);
2000 * Return an IMM for constants; otherwise call get_nir_src() as normal.
2002 * This function should not be called on any value which may be 64 bits.
2003 * We could theoretically support 64-bit on gen8+ but we choose not to
2004 * because it wouldn't work in general (no gen7 support) and there are
2005 * enough restrictions in 64-bit immediates that you can't take the return
2006 * value and treat it the same as the result of get_nir_src().
2009 fs_visitor::get_nir_src_imm(const nir_src
&src
)
2011 assert(nir_src_bit_size(src
) == 32);
2012 return nir_src_is_const(src
) ?
2013 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
2017 fs_visitor::get_nir_dest(const nir_dest
&dest
)
2020 const brw_reg_type reg_type
=
2021 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
2022 dest
.ssa
.bit_size
== 8 ?
2023 BRW_REGISTER_TYPE_D
:
2024 BRW_REGISTER_TYPE_F
);
2025 nir_ssa_values
[dest
.ssa
.index
] =
2026 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
2027 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
2028 return nir_ssa_values
[dest
.ssa
.index
];
2030 /* We don't handle indirects on locals */
2031 assert(dest
.reg
.indirect
== NULL
);
2032 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
2033 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
2038 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
2041 for (unsigned i
= 0; i
< 4; i
++) {
2042 if (!((wr_mask
>> i
) & 1))
2045 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
2046 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
2047 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
2048 if (new_inst
->src
[j
].file
== VGRF
)
2049 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2056 emit_pixel_interpolater_send(const fs_builder
&bld
,
2061 glsl_interp_mode interpolation
)
2063 struct brw_wm_prog_data
*wm_prog_data
=
2064 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2066 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2067 /* 2 floats per slot returned */
2068 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2069 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2071 wm_prog_data
->pulls_bary
= true;
2077 * Computes 1 << x, given a D/UD register containing some value x.
2080 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2082 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2084 fs_reg result
= bld
.vgrf(x
.type
, 1);
2085 fs_reg one
= bld
.vgrf(x
.type
, 1);
2087 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2088 bld
.SHL(result
, one
, x
);
2093 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2095 assert(stage
== MESA_SHADER_GEOMETRY
);
2097 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2099 if (gs_compile
->control_data_header_size_bits
== 0)
2102 /* We can only do EndPrimitive() functionality when the control data
2103 * consists of cut bits. Fortunately, the only time it isn't is when the
2104 * output type is points, in which case EndPrimitive() is a no-op.
2106 if (gs_prog_data
->control_data_format
!=
2107 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2111 /* Cut bits use one bit per vertex. */
2112 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2114 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2115 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2117 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2118 * vertex n, 0 otherwise. So all we need to do here is mark bit
2119 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2120 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2121 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2123 * Note that if EndPrimitive() is called before emitting any vertices, this
2124 * will cause us to set bit 31 of the control_data_bits register to 1.
2125 * That's fine because:
2127 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2128 * output, so the hardware will ignore cut bit 31.
2130 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2131 * last vertex, so setting cut bit 31 has no effect (since the primitive
2132 * is automatically ended when the GS terminates).
2134 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2135 * control_data_bits register to 0 when the first vertex is emitted.
2138 const fs_builder abld
= bld
.annotate("end primitive");
2140 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2141 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2142 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2143 fs_reg mask
= intexp2(abld
, prev_count
);
2144 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2145 * attention to the lower 5 bits of its second source argument, so on this
2146 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2147 * ((vertex_count - 1) % 32).
2149 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2153 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2155 assert(stage
== MESA_SHADER_GEOMETRY
);
2156 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2158 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2160 const fs_builder abld
= bld
.annotate("emit control data bits");
2161 const fs_builder fwa_bld
= bld
.exec_all();
2163 /* We use a single UD register to accumulate control data bits (32 bits
2164 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2167 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2168 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2169 * use the Channel Mask phase to enable/disable which DWord within that
2170 * group to write. (Remember, different SIMD8 channels may have emitted
2171 * different numbers of vertices, so we may need per-slot offsets.)
2173 * Channel masking presents an annoying problem: we may have to replicate
2174 * the data up to 4 times:
2176 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2178 * To avoid penalizing shaders that emit a small number of vertices, we
2179 * can avoid these sometimes: if the size of the control data header is
2180 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2181 * land in the same 128-bit group, so we can skip per-slot offsets.
2183 * Similarly, if the control data header is <= 32 bits, there is only one
2184 * DWord, so we can skip channel masks.
2186 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2188 fs_reg channel_mask
, per_slot_offset
;
2190 if (gs_compile
->control_data_header_size_bits
> 32) {
2191 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2192 channel_mask
= vgrf(glsl_type::uint_type
);
2195 if (gs_compile
->control_data_header_size_bits
> 128) {
2196 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2197 per_slot_offset
= vgrf(glsl_type::uint_type
);
2200 /* Figure out which DWord we're trying to write to using the formula:
2202 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2204 * Since bits_per_vertex is a power of two, and is known at compile
2205 * time, this can be optimized to:
2207 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2209 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2210 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2211 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2212 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2213 unsigned log2_bits_per_vertex
=
2214 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2215 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2217 if (per_slot_offset
.file
!= BAD_FILE
) {
2218 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2219 * the appropriate OWord within the control data header.
2221 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2224 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2225 * write to the appropriate DWORD within the OWORD.
2227 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2228 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2229 channel_mask
= intexp2(fwa_bld
, channel
);
2230 /* Then the channel masks need to be in bits 23:16. */
2231 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2234 /* Store the control data bits in the message payload and send it. */
2236 if (channel_mask
.file
!= BAD_FILE
)
2237 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2238 if (per_slot_offset
.file
!= BAD_FILE
)
2241 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2242 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2244 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2245 if (per_slot_offset
.file
!= BAD_FILE
)
2246 sources
[i
++] = per_slot_offset
;
2247 if (channel_mask
.file
!= BAD_FILE
)
2248 sources
[i
++] = channel_mask
;
2250 sources
[i
++] = this->control_data_bits
;
2253 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2254 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2256 /* We need to increment Global Offset by 256-bits to make room for
2257 * Broadwell's extra "Vertex Count" payload at the beginning of the
2258 * URB entry. Since this is an OWord message, Global Offset is counted
2259 * in 128-bit units, so we must set it to 2.
2261 if (gs_prog_data
->static_vertex_count
== -1)
2266 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2269 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2271 /* Note: we are calling this *before* increasing vertex_count, so
2272 * this->vertex_count == vertex_count - 1 in the formula above.
2275 /* Stream mode uses 2 bits per vertex */
2276 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2278 /* Must be a valid stream */
2279 assert(stream_id
< MAX_VERTEX_STREAMS
);
2281 /* Control data bits are initialized to 0 so we don't have to set any
2282 * bits when sending vertices to stream 0.
2287 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2289 /* reg::sid = stream_id */
2290 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2291 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2293 /* reg:shift_count = 2 * (vertex_count - 1) */
2294 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2295 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2297 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2298 * attention to the lower 5 bits of its second source argument, so on this
2299 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2300 * stream_id << ((2 * (vertex_count - 1)) % 32).
2302 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2303 abld
.SHL(mask
, sid
, shift_count
);
2304 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2308 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2311 assert(stage
== MESA_SHADER_GEOMETRY
);
2313 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2315 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2316 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2318 /* Haswell and later hardware ignores the "Render Stream Select" bits
2319 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2320 * and instead sends all primitives down the pipeline for rasterization.
2321 * If the SOL stage is enabled, "Render Stream Select" is honored and
2322 * primitives bound to non-zero streams are discarded after stream output.
2324 * Since the only purpose of primives sent to non-zero streams is to
2325 * be recorded by transform feedback, we can simply discard all geometry
2326 * bound to these streams when transform feedback is disabled.
2328 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2331 /* If we're outputting 32 control data bits or less, then we can wait
2332 * until the shader is over to output them all. Otherwise we need to
2333 * output them as we go. Now is the time to do it, since we're about to
2334 * output the vertex_count'th vertex, so it's guaranteed that the
2335 * control data bits associated with the (vertex_count - 1)th vertex are
2338 if (gs_compile
->control_data_header_size_bits
> 32) {
2339 const fs_builder abld
=
2340 bld
.annotate("emit vertex: emit control data bits");
2342 /* Only emit control data bits if we've finished accumulating a batch
2343 * of 32 bits. This is the case when:
2345 * (vertex_count * bits_per_vertex) % 32 == 0
2347 * (in other words, when the last 5 bits of vertex_count *
2348 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2349 * integer n (which is always the case, since bits_per_vertex is
2350 * always 1 or 2), this is equivalent to requiring that the last 5-n
2351 * bits of vertex_count are 0:
2353 * vertex_count & (2^(5-n) - 1) == 0
2355 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2358 * vertex_count & (32 / bits_per_vertex - 1) == 0
2360 * TODO: If vertex_count is an immediate, we could do some of this math
2361 * at compile time...
2364 abld
.AND(bld
.null_reg_d(), vertex_count
,
2365 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2366 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2368 abld
.IF(BRW_PREDICATE_NORMAL
);
2369 /* If vertex_count is 0, then no control data bits have been
2370 * accumulated yet, so we can skip emitting them.
2372 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2373 BRW_CONDITIONAL_NEQ
);
2374 abld
.IF(BRW_PREDICATE_NORMAL
);
2375 emit_gs_control_data_bits(vertex_count
);
2376 abld
.emit(BRW_OPCODE_ENDIF
);
2378 /* Reset control_data_bits to 0 so we can start accumulating a new
2381 * Note: in the case where vertex_count == 0, this neutralizes the
2382 * effect of any call to EndPrimitive() that the shader may have
2383 * made before outputting its first vertex.
2385 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2386 inst
->force_writemask_all
= true;
2387 abld
.emit(BRW_OPCODE_ENDIF
);
2390 emit_urb_writes(vertex_count
);
2392 /* In stream mode we have to set control data bits for all vertices
2393 * unless we have disabled control data bits completely (which we do
2394 * do for GL_POINTS outputs that don't use streams).
2396 if (gs_compile
->control_data_header_size_bits
> 0 &&
2397 gs_prog_data
->control_data_format
==
2398 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2399 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2404 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2405 const nir_src
&vertex_src
,
2406 unsigned base_offset
,
2407 const nir_src
&offset_src
,
2408 unsigned num_components
,
2409 unsigned first_component
)
2411 assert(type_sz(dst
.type
) == 4);
2412 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2413 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2415 /* TODO: figure out push input layout for invocations == 1 */
2416 if (gs_prog_data
->invocations
== 1 &&
2417 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2418 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2419 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2420 nir_src_as_uint(vertex_src
) * push_reg_count
;
2421 for (unsigned i
= 0; i
< num_components
; i
++) {
2422 bld
.MOV(offset(dst
, bld
, i
),
2423 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2428 /* Resort to the pull model. Ensure the VUE handles are provided. */
2429 assert(gs_prog_data
->base
.include_vue_handles
);
2431 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2432 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2434 if (gs_prog_data
->invocations
== 1) {
2435 if (nir_src_is_const(vertex_src
)) {
2436 /* The vertex index is constant; just select the proper URB handle. */
2438 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2439 BRW_REGISTER_TYPE_UD
);
2441 /* The vertex index is non-constant. We need to use indirect
2442 * addressing to fetch the proper URB handle.
2444 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2445 * indicating that channel <n> should read the handle from
2446 * DWord <n>. We convert that to bytes by multiplying by 4.
2448 * Next, we convert the vertex index to bytes by multiplying
2449 * by 32 (shifting by 5), and add the two together. This is
2450 * the final indirect byte offset.
2452 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2453 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2454 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2455 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2457 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2458 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2459 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2460 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2461 /* Convert vertex_index to bytes (multiply by 32) */
2462 bld
.SHL(vertex_offset_bytes
,
2463 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2465 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2467 /* Use first_icp_handle as the base offset. There is one register
2468 * of URB handles per vertex, so inform the register allocator that
2469 * we might read up to nir->info.gs.vertices_in registers.
2471 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2472 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2473 fs_reg(icp_offset_bytes
),
2474 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2477 assert(gs_prog_data
->invocations
> 1);
2479 if (nir_src_is_const(vertex_src
)) {
2480 unsigned vertex
= nir_src_as_uint(vertex_src
);
2481 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2483 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2484 BRW_REGISTER_TYPE_UD
));
2486 /* The vertex index is non-constant. We need to use indirect
2487 * addressing to fetch the proper URB handle.
2490 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2492 /* Convert vertex_index to bytes (multiply by 4) */
2493 bld
.SHL(icp_offset_bytes
,
2494 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2497 /* Use first_icp_handle as the base offset. There is one DWord
2498 * of URB handles per vertex, so inform the register allocator that
2499 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2501 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2502 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2503 fs_reg(icp_offset_bytes
),
2504 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2510 fs_reg indirect_offset
= get_nir_src(offset_src
);
2512 if (nir_src_is_const(offset_src
)) {
2513 /* Constant indexing - use global offset. */
2514 if (first_component
!= 0) {
2515 unsigned read_components
= num_components
+ first_component
;
2516 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2517 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2518 inst
->size_written
= read_components
*
2519 tmp
.component_size(inst
->exec_size
);
2520 for (unsigned i
= 0; i
< num_components
; i
++) {
2521 bld
.MOV(offset(dst
, bld
, i
),
2522 offset(tmp
, bld
, i
+ first_component
));
2525 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2526 inst
->size_written
= num_components
*
2527 dst
.component_size(inst
->exec_size
);
2529 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2532 /* Indirect indexing - use per-slot offsets as well. */
2533 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2534 unsigned read_components
= num_components
+ first_component
;
2535 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2536 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2537 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2538 if (first_component
!= 0) {
2539 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2541 inst
->size_written
= read_components
*
2542 tmp
.component_size(inst
->exec_size
);
2543 for (unsigned i
= 0; i
< num_components
; i
++) {
2544 bld
.MOV(offset(dst
, bld
, i
),
2545 offset(tmp
, bld
, i
+ first_component
));
2548 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2549 inst
->size_written
= num_components
*
2550 dst
.component_size(inst
->exec_size
);
2552 inst
->offset
= base_offset
;
2558 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2560 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2562 if (nir_src_is_const(*offset_src
)) {
2563 /* The only constant offset we should find is 0. brw_nir.c's
2564 * add_const_offset_to_base() will fold other constant offsets
2565 * into instr->const_index[0].
2567 assert(nir_src_as_uint(*offset_src
) == 0);
2571 return get_nir_src(*offset_src
);
2575 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2576 nir_intrinsic_instr
*instr
)
2578 assert(stage
== MESA_SHADER_VERTEX
);
2581 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2582 dest
= get_nir_dest(instr
->dest
);
2584 switch (instr
->intrinsic
) {
2585 case nir_intrinsic_load_vertex_id
:
2586 case nir_intrinsic_load_base_vertex
:
2587 unreachable("should be lowered by nir_lower_system_values()");
2589 case nir_intrinsic_load_input
: {
2590 assert(nir_dest_bit_size(instr
->dest
) == 32);
2591 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2592 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2593 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2595 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2596 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2600 case nir_intrinsic_load_vertex_id_zero_base
:
2601 case nir_intrinsic_load_instance_id
:
2602 case nir_intrinsic_load_base_instance
:
2603 case nir_intrinsic_load_draw_id
:
2604 case nir_intrinsic_load_first_vertex
:
2605 case nir_intrinsic_load_is_indexed_draw
:
2606 unreachable("lowered by brw_nir_lower_vs_inputs");
2609 nir_emit_intrinsic(bld
, instr
);
2615 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2616 nir_intrinsic_instr
*instr
)
2618 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2619 const nir_src
&vertex_src
= instr
->src
[0];
2620 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2623 if (nir_src_is_const(vertex_src
)) {
2624 /* Emit a MOV to resolve <0,1,0> regioning. */
2625 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2626 unsigned vertex
= nir_src_as_uint(vertex_src
);
2628 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2629 BRW_REGISTER_TYPE_UD
));
2630 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2631 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2632 /* For the common case of only 1 instance, an array index of
2633 * gl_InvocationID means reading g1. Skip all the indirect work.
2635 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2637 /* The vertex index is non-constant. We need to use indirect
2638 * addressing to fetch the proper URB handle.
2640 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2642 /* Each ICP handle is a single DWord (4 bytes) */
2643 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2644 bld
.SHL(vertex_offset_bytes
,
2645 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2648 /* Start at g1. We might read up to 4 registers. */
2649 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2650 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2651 brw_imm_ud(4 * REG_SIZE
));
2658 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2659 nir_intrinsic_instr
*instr
)
2661 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2662 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2663 const nir_src
&vertex_src
= instr
->src
[0];
2665 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2667 if (nir_src_is_const(vertex_src
)) {
2668 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2669 nir_src_as_uint(vertex_src
), 0),
2670 BRW_REGISTER_TYPE_UD
));
2673 /* The vertex index is non-constant. We need to use indirect
2674 * addressing to fetch the proper URB handle.
2676 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2677 * indicating that channel <n> should read the handle from
2678 * DWord <n>. We convert that to bytes by multiplying by 4.
2680 * Next, we convert the vertex index to bytes by multiplying
2681 * by 32 (shifting by 5), and add the two together. This is
2682 * the final indirect byte offset.
2684 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2685 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2686 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2687 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2688 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2690 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2691 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2692 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2693 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2694 /* Convert vertex_index to bytes (multiply by 32) */
2695 bld
.SHL(vertex_offset_bytes
,
2696 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2698 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2700 /* Use first_icp_handle as the base offset. There is one register
2701 * of URB handles per vertex, so inform the register allocator that
2702 * we might read up to nir->info.gs.vertices_in registers.
2704 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2705 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2706 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2712 fs_visitor::get_tcs_output_urb_handle()
2714 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2716 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2717 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2719 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2720 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2725 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2726 nir_intrinsic_instr
*instr
)
2728 assert(stage
== MESA_SHADER_TESS_CTRL
);
2729 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2730 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2731 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2734 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2737 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2738 dst
= get_nir_dest(instr
->dest
);
2740 switch (instr
->intrinsic
) {
2741 case nir_intrinsic_load_primitive_id
:
2742 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2743 : brw_vec1_grf(0, 1)));
2745 case nir_intrinsic_load_invocation_id
:
2746 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2748 case nir_intrinsic_load_patch_vertices_in
:
2749 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2750 brw_imm_d(tcs_key
->input_vertices
));
2753 case nir_intrinsic_control_barrier
: {
2754 if (tcs_prog_data
->instances
== 1)
2757 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2758 fs_reg m0_2
= component(m0
, 2);
2760 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2762 /* Zero the message header */
2763 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2765 if (devinfo
->gen
< 11) {
2766 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2767 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2768 brw_imm_ud(INTEL_MASK(16, 13)));
2770 /* Shift it up to bits 27:24. */
2771 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2773 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2774 brw_imm_ud(INTEL_MASK(30, 24)));
2777 /* Set the Barrier Count and the enable bit */
2778 if (devinfo
->gen
< 11) {
2779 chanbld
.OR(m0_2
, m0_2
,
2780 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2782 chanbld
.OR(m0_2
, m0_2
,
2783 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2786 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2790 case nir_intrinsic_load_input
:
2791 unreachable("nir_lower_io should never give us these.");
2794 case nir_intrinsic_load_per_vertex_input
: {
2795 assert(nir_dest_bit_size(instr
->dest
) == 32);
2796 fs_reg indirect_offset
= get_indirect_offset(instr
);
2797 unsigned imm_offset
= instr
->const_index
[0];
2801 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2802 : get_tcs_single_patch_icp_handle(bld
, instr
);
2804 /* We can only read two double components with each URB read, so
2805 * we send two read messages in that case, each one loading up to
2806 * two double components.
2808 unsigned num_components
= instr
->num_components
;
2809 unsigned first_component
= nir_intrinsic_component(instr
);
2811 if (indirect_offset
.file
== BAD_FILE
) {
2812 /* Constant indexing - use global offset. */
2813 if (first_component
!= 0) {
2814 unsigned read_components
= num_components
+ first_component
;
2815 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2816 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2817 for (unsigned i
= 0; i
< num_components
; i
++) {
2818 bld
.MOV(offset(dst
, bld
, i
),
2819 offset(tmp
, bld
, i
+ first_component
));
2822 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2824 inst
->offset
= imm_offset
;
2827 /* Indirect indexing - use per-slot offsets as well. */
2828 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2829 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2830 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2831 if (first_component
!= 0) {
2832 unsigned read_components
= num_components
+ first_component
;
2833 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2834 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2836 for (unsigned i
= 0; i
< num_components
; i
++) {
2837 bld
.MOV(offset(dst
, bld
, i
),
2838 offset(tmp
, bld
, i
+ first_component
));
2841 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2844 inst
->offset
= imm_offset
;
2847 inst
->size_written
= (num_components
+ first_component
) *
2848 inst
->dst
.component_size(inst
->exec_size
);
2850 /* Copy the temporary to the destination to deal with writemasking.
2852 * Also attempt to deal with gl_PointSize being in the .w component.
2854 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2855 assert(type_sz(dst
.type
) == 4);
2856 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2857 inst
->size_written
= 4 * REG_SIZE
;
2858 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2863 case nir_intrinsic_load_output
:
2864 case nir_intrinsic_load_per_vertex_output
: {
2865 assert(nir_dest_bit_size(instr
->dest
) == 32);
2866 fs_reg indirect_offset
= get_indirect_offset(instr
);
2867 unsigned imm_offset
= instr
->const_index
[0];
2868 unsigned first_component
= nir_intrinsic_component(instr
);
2870 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2873 if (indirect_offset
.file
== BAD_FILE
) {
2874 /* This MOV replicates the output handle to all enabled channels
2875 * is SINGLE_PATCH mode.
2877 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2878 bld
.MOV(patch_handle
, output_handles
);
2881 if (first_component
!= 0) {
2882 unsigned read_components
=
2883 instr
->num_components
+ first_component
;
2884 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2885 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2887 inst
->size_written
= read_components
* REG_SIZE
;
2888 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2889 bld
.MOV(offset(dst
, bld
, i
),
2890 offset(tmp
, bld
, i
+ first_component
));
2893 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2895 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2897 inst
->offset
= imm_offset
;
2901 /* Indirect indexing - use per-slot offsets as well. */
2902 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2903 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2904 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2905 if (first_component
!= 0) {
2906 unsigned read_components
=
2907 instr
->num_components
+ first_component
;
2908 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2909 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2911 inst
->size_written
= read_components
* REG_SIZE
;
2912 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2913 bld
.MOV(offset(dst
, bld
, i
),
2914 offset(tmp
, bld
, i
+ first_component
));
2917 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2919 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2921 inst
->offset
= imm_offset
;
2927 case nir_intrinsic_store_output
:
2928 case nir_intrinsic_store_per_vertex_output
: {
2929 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2930 fs_reg value
= get_nir_src(instr
->src
[0]);
2931 fs_reg indirect_offset
= get_indirect_offset(instr
);
2932 unsigned imm_offset
= instr
->const_index
[0];
2933 unsigned mask
= instr
->const_index
[1];
2934 unsigned header_regs
= 0;
2935 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2938 srcs
[header_regs
++] = output_handles
;
2940 if (indirect_offset
.file
!= BAD_FILE
) {
2941 srcs
[header_regs
++] = indirect_offset
;
2947 unsigned num_components
= util_last_bit(mask
);
2950 /* We can only pack two 64-bit components in a single message, so send
2951 * 2 messages if we have more components
2953 unsigned first_component
= nir_intrinsic_component(instr
);
2954 mask
= mask
<< first_component
;
2956 if (mask
!= WRITEMASK_XYZW
) {
2957 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2958 opcode
= indirect_offset
.file
!= BAD_FILE
?
2959 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2960 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2962 opcode
= indirect_offset
.file
!= BAD_FILE
?
2963 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2964 SHADER_OPCODE_URB_WRITE_SIMD8
;
2967 for (unsigned i
= 0; i
< num_components
; i
++) {
2968 if (!(mask
& (1 << (i
+ first_component
))))
2971 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2974 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2976 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2977 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2979 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2980 inst
->offset
= imm_offset
;
2986 nir_emit_intrinsic(bld
, instr
);
2992 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2993 nir_intrinsic_instr
*instr
)
2995 assert(stage
== MESA_SHADER_TESS_EVAL
);
2996 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2999 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3000 dest
= get_nir_dest(instr
->dest
);
3002 switch (instr
->intrinsic
) {
3003 case nir_intrinsic_load_primitive_id
:
3004 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3006 case nir_intrinsic_load_tess_coord
:
3007 /* gl_TessCoord is part of the payload in g1-3 */
3008 for (unsigned i
= 0; i
< 3; i
++) {
3009 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3013 case nir_intrinsic_load_input
:
3014 case nir_intrinsic_load_per_vertex_input
: {
3015 assert(nir_dest_bit_size(instr
->dest
) == 32);
3016 fs_reg indirect_offset
= get_indirect_offset(instr
);
3017 unsigned imm_offset
= instr
->const_index
[0];
3018 unsigned first_component
= nir_intrinsic_component(instr
);
3021 if (indirect_offset
.file
== BAD_FILE
) {
3022 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3023 * which is 16 registers (since each holds 2 vec4 slots).
3025 const unsigned max_push_slots
= 32;
3026 if (imm_offset
< max_push_slots
) {
3027 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3028 for (int i
= 0; i
< instr
->num_components
; i
++) {
3029 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
3030 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3033 tes_prog_data
->base
.urb_read_length
=
3034 MAX2(tes_prog_data
->base
.urb_read_length
,
3035 (imm_offset
/ 2) + 1);
3037 /* Replicate the patch handle to all enabled channels */
3038 const fs_reg srcs
[] = {
3039 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3041 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3042 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3044 if (first_component
!= 0) {
3045 unsigned read_components
=
3046 instr
->num_components
+ first_component
;
3047 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3048 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3050 inst
->size_written
= read_components
* REG_SIZE
;
3051 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3052 bld
.MOV(offset(dest
, bld
, i
),
3053 offset(tmp
, bld
, i
+ first_component
));
3056 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3058 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3061 inst
->offset
= imm_offset
;
3064 /* Indirect indexing - use per-slot offsets as well. */
3066 /* We can only read two double components with each URB read, so
3067 * we send two read messages in that case, each one loading up to
3068 * two double components.
3070 unsigned num_components
= instr
->num_components
;
3071 const fs_reg srcs
[] = {
3072 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3075 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3076 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3078 if (first_component
!= 0) {
3079 unsigned read_components
=
3080 num_components
+ first_component
;
3081 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3082 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3084 for (unsigned i
= 0; i
< num_components
; i
++) {
3085 bld
.MOV(offset(dest
, bld
, i
),
3086 offset(tmp
, bld
, i
+ first_component
));
3089 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3093 inst
->offset
= imm_offset
;
3094 inst
->size_written
= (num_components
+ first_component
) *
3095 inst
->dst
.component_size(inst
->exec_size
);
3100 nir_emit_intrinsic(bld
, instr
);
3106 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3107 nir_intrinsic_instr
*instr
)
3109 assert(stage
== MESA_SHADER_GEOMETRY
);
3110 fs_reg indirect_offset
;
3113 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3114 dest
= get_nir_dest(instr
->dest
);
3116 switch (instr
->intrinsic
) {
3117 case nir_intrinsic_load_primitive_id
:
3118 assert(stage
== MESA_SHADER_GEOMETRY
);
3119 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3120 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3121 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3124 case nir_intrinsic_load_input
:
3125 unreachable("load_input intrinsics are invalid for the GS stage");
3127 case nir_intrinsic_load_per_vertex_input
:
3128 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3129 instr
->src
[1], instr
->num_components
,
3130 nir_intrinsic_component(instr
));
3133 case nir_intrinsic_emit_vertex_with_counter
:
3134 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3137 case nir_intrinsic_end_primitive_with_counter
:
3138 emit_gs_end_primitive(instr
->src
[0]);
3141 case nir_intrinsic_set_vertex_count
:
3142 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3145 case nir_intrinsic_load_invocation_id
: {
3146 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3147 assert(val
.file
!= BAD_FILE
);
3148 dest
.type
= val
.type
;
3154 nir_emit_intrinsic(bld
, instr
);
3160 * Fetch the current render target layer index.
3163 fetch_render_target_array_index(const fs_builder
&bld
)
3165 if (bld
.shader
->devinfo
->gen
>= 12) {
3166 /* The render target array index is provided in the thread payload as
3167 * bits 26:16 of r1.1.
3169 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3170 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 1, 3),
3173 } else if (bld
.shader
->devinfo
->gen
>= 6) {
3174 /* The render target array index is provided in the thread payload as
3175 * bits 26:16 of r0.0.
3177 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3178 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3182 /* Pre-SNB we only ever render into the first layer of the framebuffer
3183 * since layered rendering is not implemented.
3185 return brw_imm_ud(0);
3190 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3191 * framebuffer at the current fragment coordinates and sample index.
3194 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3197 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3199 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3200 const brw_wm_prog_key
*wm_key
=
3201 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3202 assert(!wm_key
->coherent_fb_fetch
);
3203 const struct brw_wm_prog_data
*wm_prog_data
=
3204 brw_wm_prog_data(stage_prog_data
);
3206 /* Calculate the surface index relative to the start of the texture binding
3207 * table block, since that's what the texturing messages expect.
3209 const unsigned surface
= target
+
3210 wm_prog_data
->binding_table
.render_target_read_start
-
3211 wm_prog_data
->base
.binding_table
.texture_start
;
3213 /* Calculate the fragment coordinates. */
3214 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3215 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3216 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3217 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3219 /* Calculate the sample index and MCS payload when multisampling. Luckily
3220 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3221 * shouldn't be necessary to recompile based on whether the framebuffer is
3224 if (wm_key
->multisample_fbo
&&
3225 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3226 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3228 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3229 const fs_reg mcs
= wm_key
->multisample_fbo
?
3230 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3232 /* Use either a normal or a CMS texel fetch message depending on whether
3233 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3234 * message just in case the framebuffer uses 16x multisampling, it should
3235 * be equivalent to the normal CMS fetch for lower multisampling modes.
3237 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3238 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3239 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3241 /* Emit the instruction. */
3242 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3243 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3244 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3245 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3246 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3247 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3248 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3249 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3250 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3252 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3253 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3259 * Actual coherent framebuffer read implemented using the native render target
3260 * read message. Requires SKL+.
3263 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3265 assert(bld
.shader
->devinfo
->gen
>= 9);
3266 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3267 inst
->target
= target
;
3268 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3274 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3276 if (n
&& regs
[0].file
!= BAD_FILE
) {
3280 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3282 for (unsigned i
= 0; i
< n
; i
++)
3290 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3292 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3293 const brw_wm_prog_key
*const key
=
3294 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3295 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3296 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3298 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3299 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3301 else if (l
== FRAG_RESULT_COLOR
)
3302 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3303 MAX2(key
->nr_color_regions
, 1));
3305 else if (l
== FRAG_RESULT_DEPTH
)
3306 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3308 else if (l
== FRAG_RESULT_STENCIL
)
3309 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3311 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3312 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3314 else if (l
>= FRAG_RESULT_DATA0
&&
3315 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3316 return alloc_temporary(v
->bld
, 4,
3317 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3320 unreachable("Invalid location");
3324 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3325 nir_intrinsic_instr
*instr
)
3327 assert(stage
== MESA_SHADER_FRAGMENT
);
3330 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3331 dest
= get_nir_dest(instr
->dest
);
3333 switch (instr
->intrinsic
) {
3334 case nir_intrinsic_load_front_face
:
3335 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3336 *emit_frontfacing_interpolation());
3339 case nir_intrinsic_load_sample_pos
: {
3340 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3341 assert(sample_pos
.file
!= BAD_FILE
);
3342 dest
.type
= sample_pos
.type
;
3343 bld
.MOV(dest
, sample_pos
);
3344 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3348 case nir_intrinsic_load_layer_id
:
3349 dest
.type
= BRW_REGISTER_TYPE_UD
;
3350 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3353 case nir_intrinsic_is_helper_invocation
: {
3354 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3355 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3356 * consideration demoted invocations. That information is stored in
3359 dest
.type
= BRW_REGISTER_TYPE_UD
;
3361 bld
.MOV(dest
, brw_imm_ud(0));
3363 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3364 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3365 mov
->predicate_inverse
= true;
3366 mov
->flag_subreg
= sample_mask_flag_subreg(this);
3370 case nir_intrinsic_load_helper_invocation
:
3371 case nir_intrinsic_load_sample_mask_in
:
3372 case nir_intrinsic_load_sample_id
: {
3373 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3374 fs_reg val
= nir_system_values
[sv
];
3375 assert(val
.file
!= BAD_FILE
);
3376 dest
.type
= val
.type
;
3381 case nir_intrinsic_store_output
: {
3382 const fs_reg src
= get_nir_src(instr
->src
[0]);
3383 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3384 const unsigned location
= nir_intrinsic_base(instr
) +
3385 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3386 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3389 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3390 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3391 offset(src
, bld
, j
));
3396 case nir_intrinsic_load_output
: {
3397 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3398 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3399 assert(l
>= FRAG_RESULT_DATA0
);
3400 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3401 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3402 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3404 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3405 emit_coherent_fb_read(bld
, tmp
, target
);
3407 emit_non_coherent_fb_read(bld
, tmp
, target
);
3409 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3410 bld
.MOV(offset(dest
, bld
, j
),
3411 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3417 case nir_intrinsic_demote
:
3418 case nir_intrinsic_discard
:
3419 case nir_intrinsic_demote_if
:
3420 case nir_intrinsic_discard_if
: {
3421 /* We track our discarded pixels in f0.1/f1.0. By predicating on it, we
3422 * can update just the flag bits that aren't yet discarded. If there's
3423 * no condition, we emit a CMP of g0 != g0, so all currently executing
3424 * channels will get turned off.
3426 fs_inst
*cmp
= NULL
;
3427 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3428 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3429 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3432 alu
->op
!= nir_op_bcsel
&&
3433 (devinfo
->gen
> 5 ||
3434 (alu
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE
||
3435 alu
->op
== nir_op_fne32
|| alu
->op
== nir_op_feq32
||
3436 alu
->op
== nir_op_flt32
|| alu
->op
== nir_op_fge32
||
3437 alu
->op
== nir_op_ine32
|| alu
->op
== nir_op_ieq32
||
3438 alu
->op
== nir_op_ilt32
|| alu
->op
== nir_op_ige32
||
3439 alu
->op
== nir_op_ult32
|| alu
->op
== nir_op_uge32
)) {
3440 /* Re-emit the instruction that generated the Boolean value, but
3441 * do not store it. Since this instruction will be conditional,
3442 * other instructions that want to use the real Boolean value may
3443 * get garbage. This was a problem for piglit's fs-discard-exit-2
3446 * Ideally we'd detect that the instruction cannot have a
3447 * conditional modifier before emitting the instructions. Alas,
3448 * that is nigh impossible. Instead, we're going to assume the
3449 * instruction (or last instruction) generated can have a
3450 * conditional modifier. If it cannot, fallback to the old-style
3451 * compare, and hope dead code elimination will clean up the
3452 * extra instructions generated.
3454 nir_emit_alu(bld
, alu
, false);
3456 cmp
= (fs_inst
*) instructions
.get_tail();
3457 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3458 if (cmp
->can_do_cmod())
3459 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3463 /* The old sequence that would have been generated is,
3464 * basically, bool_result == false. This is equivalent to
3465 * !bool_result, so negate the old modifier.
3467 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3472 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3473 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3476 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3477 BRW_REGISTER_TYPE_UW
));
3478 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3481 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3482 cmp
->flag_subreg
= sample_mask_flag_subreg(this);
3484 if (devinfo
->gen
>= 6) {
3485 /* Due to the way we implement discard, the jump will only happen
3486 * when the whole quad is discarded. So we can do this even for
3487 * demote as it won't break its uniformity promises.
3489 emit_discard_jump();
3492 if (devinfo
->gen
< 7)
3493 limit_dispatch_width(
3494 16, "Fragment discard/demote not implemented in SIMD32 mode.\n");
3498 case nir_intrinsic_load_input
: {
3499 /* load_input is only used for flat inputs */
3500 assert(nir_dest_bit_size(instr
->dest
) == 32);
3501 unsigned base
= nir_intrinsic_base(instr
);
3502 unsigned comp
= nir_intrinsic_component(instr
);
3503 unsigned num_components
= instr
->num_components
;
3505 /* Special case fields in the VUE header */
3506 if (base
== VARYING_SLOT_LAYER
)
3508 else if (base
== VARYING_SLOT_VIEWPORT
)
3511 for (unsigned int i
= 0; i
< num_components
; i
++) {
3512 bld
.MOV(offset(dest
, bld
, i
),
3513 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3518 case nir_intrinsic_load_fs_input_interp_deltas
: {
3519 assert(stage
== MESA_SHADER_FRAGMENT
);
3520 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3521 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3522 nir_intrinsic_component(instr
));
3523 dest
.type
= BRW_REGISTER_TYPE_F
;
3524 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3525 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3526 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3530 case nir_intrinsic_load_barycentric_pixel
:
3531 case nir_intrinsic_load_barycentric_centroid
:
3532 case nir_intrinsic_load_barycentric_sample
: {
3533 /* Use the delta_xy values computed from the payload */
3534 const glsl_interp_mode interp_mode
=
3535 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3536 enum brw_barycentric_mode bary
=
3537 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3538 const fs_reg srcs
[] = { offset(this->delta_xy
[bary
], bld
, 0),
3539 offset(this->delta_xy
[bary
], bld
, 1) };
3540 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3544 case nir_intrinsic_load_barycentric_at_sample
: {
3545 const glsl_interp_mode interpolation
=
3546 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3548 if (nir_src_is_const(instr
->src
[0])) {
3549 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3551 emit_pixel_interpolater_send(bld
,
3552 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3555 brw_imm_ud(msg_data
),
3558 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3559 BRW_REGISTER_TYPE_UD
);
3561 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3562 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3563 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3564 bld
.exec_all().group(1, 0)
3565 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3566 emit_pixel_interpolater_send(bld
,
3567 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3570 component(msg_data
, 0),
3573 /* Make a loop that sends a message to the pixel interpolater
3574 * for the sample number in each live channel. If there are
3575 * multiple channels with the same sample number then these
3576 * will be handled simultaneously with a single interation of
3579 bld
.emit(BRW_OPCODE_DO
);
3581 /* Get the next live sample number into sample_id_reg */
3582 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3584 /* Set the flag register so that we can perform the send
3585 * message on all channels that have the same sample number
3587 bld
.CMP(bld
.null_reg_ud(),
3588 sample_src
, sample_id
,
3589 BRW_CONDITIONAL_EQ
);
3590 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3591 bld
.exec_all().group(1, 0)
3592 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3594 emit_pixel_interpolater_send(bld
,
3595 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3598 component(msg_data
, 0),
3600 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3602 /* Continue the loop if there are any live channels left */
3603 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3605 bld
.emit(BRW_OPCODE_WHILE
));
3611 case nir_intrinsic_load_barycentric_at_offset
: {
3612 const glsl_interp_mode interpolation
=
3613 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3615 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3618 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3619 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3620 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3622 emit_pixel_interpolater_send(bld
,
3623 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3626 brw_imm_ud(off_x
| (off_y
<< 4)),
3629 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3630 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3631 BRW_REGISTER_TYPE_F
);
3632 for (int i
= 0; i
< 2; i
++) {
3633 fs_reg temp
= vgrf(glsl_type::float_type
);
3634 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3635 fs_reg itemp
= vgrf(glsl_type::int_type
);
3637 bld
.MOV(itemp
, temp
);
3639 /* Clamp the upper end of the range to +7/16.
3640 * ARB_gpu_shader5 requires that we support a maximum offset
3641 * of +0.5, which isn't representable in a S0.4 value -- if
3642 * we didn't clamp it, we'd end up with -8/16, which is the
3643 * opposite of what the shader author wanted.
3645 * This is legal due to ARB_gpu_shader5's quantization
3648 * "Not all values of <offset> may be supported; x and y
3649 * offsets may be rounded to fixed-point values with the
3650 * number of fraction bits given by the
3651 * implementation-dependent constant
3652 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3654 set_condmod(BRW_CONDITIONAL_L
,
3655 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3658 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3659 emit_pixel_interpolater_send(bld
,
3669 case nir_intrinsic_load_frag_coord
:
3670 emit_fragcoord_interpolation(dest
);
3673 case nir_intrinsic_load_interpolated_input
: {
3674 assert(instr
->src
[0].ssa
&&
3675 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3676 nir_intrinsic_instr
*bary_intrinsic
=
3677 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3678 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3679 enum glsl_interp_mode interp_mode
=
3680 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3683 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3684 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3685 /* Use the result of the PI message. */
3686 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3688 /* Use the delta_xy values computed from the payload */
3689 enum brw_barycentric_mode bary
=
3690 brw_barycentric_mode(interp_mode
, bary_intrin
);
3691 dst_xy
= this->delta_xy
[bary
];
3694 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3696 component(interp_reg(nir_intrinsic_base(instr
),
3697 nir_intrinsic_component(instr
) + i
), 0);
3698 interp
.type
= BRW_REGISTER_TYPE_F
;
3699 dest
.type
= BRW_REGISTER_TYPE_F
;
3701 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3702 fs_reg tmp
= vgrf(glsl_type::float_type
);
3703 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3704 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3706 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3713 nir_emit_intrinsic(bld
, instr
);
3719 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3720 nir_intrinsic_instr
*instr
)
3722 assert(stage
== MESA_SHADER_COMPUTE
);
3723 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3726 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3727 dest
= get_nir_dest(instr
->dest
);
3729 switch (instr
->intrinsic
) {
3730 case nir_intrinsic_control_barrier
:
3731 /* The whole workgroup fits in a single HW thread, so all the
3732 * invocations are already executed lock-step. Instead of an actual
3733 * barrier just emit a scheduling fence, that will generate no code.
3735 if (!nir
->info
.cs
.local_size_variable
&&
3736 workgroup_size() <= dispatch_width
) {
3737 bld
.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE
);
3742 cs_prog_data
->uses_barrier
= true;
3745 case nir_intrinsic_load_subgroup_id
:
3746 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3749 case nir_intrinsic_load_local_invocation_id
:
3750 case nir_intrinsic_load_work_group_id
: {
3751 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3752 fs_reg val
= nir_system_values
[sv
];
3753 assert(val
.file
!= BAD_FILE
);
3754 dest
.type
= val
.type
;
3755 for (unsigned i
= 0; i
< 3; i
++)
3756 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3760 case nir_intrinsic_load_num_work_groups
: {
3761 const unsigned surface
=
3762 cs_prog_data
->binding_table
.work_groups_start
;
3764 cs_prog_data
->uses_num_work_groups
= true;
3766 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3767 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3768 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3769 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3771 /* Read the 3 GLuint components of gl_NumWorkGroups */
3772 for (unsigned i
= 0; i
< 3; i
++) {
3773 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3774 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3775 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3780 case nir_intrinsic_shared_atomic_add
:
3781 case nir_intrinsic_shared_atomic_imin
:
3782 case nir_intrinsic_shared_atomic_umin
:
3783 case nir_intrinsic_shared_atomic_imax
:
3784 case nir_intrinsic_shared_atomic_umax
:
3785 case nir_intrinsic_shared_atomic_and
:
3786 case nir_intrinsic_shared_atomic_or
:
3787 case nir_intrinsic_shared_atomic_xor
:
3788 case nir_intrinsic_shared_atomic_exchange
:
3789 case nir_intrinsic_shared_atomic_comp_swap
:
3790 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3792 case nir_intrinsic_shared_atomic_fmin
:
3793 case nir_intrinsic_shared_atomic_fmax
:
3794 case nir_intrinsic_shared_atomic_fcomp_swap
:
3795 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3798 case nir_intrinsic_load_shared
: {
3799 assert(devinfo
->gen
>= 7);
3800 assert(stage
== MESA_SHADER_COMPUTE
);
3802 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3803 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3804 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3805 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3806 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3808 /* Make dest unsigned because that's what the temporary will be */
3809 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3811 /* Read the vector */
3812 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3813 assert(nir_intrinsic_align(instr
) > 0);
3814 if (nir_dest_bit_size(instr
->dest
) == 32 &&
3815 nir_intrinsic_align(instr
) >= 4) {
3816 assert(nir_dest_num_components(instr
->dest
) <= 4);
3817 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3819 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3820 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3821 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3823 assert(nir_dest_num_components(instr
->dest
) == 1);
3824 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3826 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3827 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3828 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3829 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3834 case nir_intrinsic_store_shared
: {
3835 assert(devinfo
->gen
>= 7);
3836 assert(stage
== MESA_SHADER_COMPUTE
);
3838 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3839 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3840 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3841 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3842 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3844 fs_reg data
= get_nir_src(instr
->src
[0]);
3845 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3847 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3848 assert(nir_intrinsic_write_mask(instr
) ==
3849 (1u << instr
->num_components
) - 1);
3850 assert(nir_intrinsic_align(instr
) > 0);
3851 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
3852 nir_intrinsic_align(instr
) >= 4) {
3853 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3854 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3855 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3856 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3857 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3859 assert(nir_src_num_components(instr
->src
[0]) == 1);
3860 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3862 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3863 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3865 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3866 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3871 case nir_intrinsic_load_local_group_size
: {
3872 for (unsigned i
= 0; i
< 3; i
++) {
3873 bld
.MOV(retype(offset(dest
, bld
, i
), BRW_REGISTER_TYPE_UD
),
3880 nir_emit_intrinsic(bld
, instr
);
3886 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3887 nir_op op
, brw_reg_type type
)
3889 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3890 switch (type_sz(type
)) {
3892 if (type
== BRW_REGISTER_TYPE_UB
) {
3893 return brw_imm_uw(value
.u8
);
3895 assert(type
== BRW_REGISTER_TYPE_B
);
3896 return brw_imm_w(value
.i8
);
3899 return retype(brw_imm_uw(value
.u16
), type
);
3901 return retype(brw_imm_ud(value
.u32
), type
);
3903 if (type
== BRW_REGISTER_TYPE_DF
)
3904 return setup_imm_df(bld
, value
.f64
);
3906 return retype(brw_imm_u64(value
.u64
), type
);
3908 unreachable("Invalid type size");
3913 brw_op_for_nir_reduction_op(nir_op op
)
3916 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3917 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3918 case nir_op_imul
: return BRW_OPCODE_MUL
;
3919 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3920 case nir_op_imin
: return BRW_OPCODE_SEL
;
3921 case nir_op_umin
: return BRW_OPCODE_SEL
;
3922 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3923 case nir_op_imax
: return BRW_OPCODE_SEL
;
3924 case nir_op_umax
: return BRW_OPCODE_SEL
;
3925 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3926 case nir_op_iand
: return BRW_OPCODE_AND
;
3927 case nir_op_ior
: return BRW_OPCODE_OR
;
3928 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3930 unreachable("Invalid reduction operation");
3934 static brw_conditional_mod
3935 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3938 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3939 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3940 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3941 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3942 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3943 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3944 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3945 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3946 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3947 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3948 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3949 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3950 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3952 unreachable("Invalid reduction operation");
3957 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3958 nir_intrinsic_instr
*instr
)
3960 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3961 fs_reg surf_index
= image
;
3963 if (stage_prog_data
->binding_table
.image_start
> 0) {
3964 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3966 brw_imm_ud(image
.d
+ stage_prog_data
->binding_table
.image_start
);
3968 surf_index
= vgrf(glsl_type::uint_type
);
3969 bld
.ADD(surf_index
, image
,
3970 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3974 return bld
.emit_uniformize(surf_index
);
3978 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3979 nir_intrinsic_instr
*instr
)
3981 /* SSBO stores are weird in that their index is in src[1] */
3982 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3985 if (nir_src_is_const(instr
->src
[src
])) {
3986 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3987 nir_src_as_uint(instr
->src
[src
]);
3988 surf_index
= brw_imm_ud(index
);
3990 surf_index
= vgrf(glsl_type::uint_type
);
3991 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3992 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3995 return bld
.emit_uniformize(surf_index
);
3999 * The offsets we get from NIR act as if each SIMD channel has it's own blob
4000 * of contiguous space. However, if we actually place each SIMD channel in
4001 * it's own space, we end up with terrible cache performance because each SIMD
4002 * channel accesses a different cache line even when they're all accessing the
4003 * same byte offset. To deal with this problem, we swizzle the address using
4004 * a simple algorithm which ensures that any time a SIMD message reads or
4005 * writes the same address, it's all in the same cache line. We have to keep
4006 * the bottom two bits fixed so that we can read/write up to a dword at a time
4007 * and the individual element is contiguous. We do this by splitting the
4008 * address as follows:
4011 * +-------------------------------+------------+----------+
4012 * | Hi address bits | chan index | addr low |
4013 * +-------------------------------+------------+----------+
4015 * In other words, the bottom two address bits stay, and the top 30 get
4016 * shifted up so that we can stick the SIMD channel index in the middle. This
4017 * way, we can access 8, 16, or 32-bit elements and, when accessing a 32-bit
4018 * at the same logical offset, the scratch read/write instruction acts on
4019 * continuous elements and we get good cache locality.
4022 fs_visitor::swizzle_nir_scratch_addr(const brw::fs_builder
&bld
,
4023 const fs_reg
&nir_addr
,
4026 const fs_reg
&chan_index
=
4027 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
4028 const unsigned chan_index_bits
= ffs(dispatch_width
) - 1;
4030 fs_reg addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4032 /* In this case, we know the address is aligned to a DWORD and we want
4033 * the final address in DWORDs.
4035 bld
.SHL(addr
, nir_addr
, brw_imm_ud(chan_index_bits
- 2));
4036 bld
.OR(addr
, addr
, chan_index
);
4038 /* This case substantially more annoying because we have to pay
4039 * attention to those pesky two bottom bits.
4041 fs_reg addr_hi
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4042 bld
.AND(addr_hi
, nir_addr
, brw_imm_ud(~0x3u
));
4043 bld
.SHL(addr_hi
, addr_hi
, brw_imm_ud(chan_index_bits
));
4044 fs_reg chan_addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4045 bld
.SHL(chan_addr
, chan_index
, brw_imm_ud(2));
4046 bld
.AND(addr
, nir_addr
, brw_imm_ud(0x3u
));
4047 bld
.OR(addr
, addr
, addr_hi
);
4048 bld
.OR(addr
, addr
, chan_addr
);
4054 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4057 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4058 dest
= get_nir_dest(instr
->dest
);
4060 switch (instr
->intrinsic
) {
4061 case nir_intrinsic_image_load
:
4062 case nir_intrinsic_image_store
:
4063 case nir_intrinsic_image_atomic_add
:
4064 case nir_intrinsic_image_atomic_imin
:
4065 case nir_intrinsic_image_atomic_umin
:
4066 case nir_intrinsic_image_atomic_imax
:
4067 case nir_intrinsic_image_atomic_umax
:
4068 case nir_intrinsic_image_atomic_and
:
4069 case nir_intrinsic_image_atomic_or
:
4070 case nir_intrinsic_image_atomic_xor
:
4071 case nir_intrinsic_image_atomic_exchange
:
4072 case nir_intrinsic_image_atomic_comp_swap
:
4073 case nir_intrinsic_bindless_image_load
:
4074 case nir_intrinsic_bindless_image_store
:
4075 case nir_intrinsic_bindless_image_atomic_add
:
4076 case nir_intrinsic_bindless_image_atomic_imin
:
4077 case nir_intrinsic_bindless_image_atomic_umin
:
4078 case nir_intrinsic_bindless_image_atomic_imax
:
4079 case nir_intrinsic_bindless_image_atomic_umax
:
4080 case nir_intrinsic_bindless_image_atomic_and
:
4081 case nir_intrinsic_bindless_image_atomic_or
:
4082 case nir_intrinsic_bindless_image_atomic_xor
:
4083 case nir_intrinsic_bindless_image_atomic_exchange
:
4084 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4085 if (stage
== MESA_SHADER_FRAGMENT
&&
4086 instr
->intrinsic
!= nir_intrinsic_image_load
)
4087 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4089 /* Get some metadata from the image intrinsic. */
4090 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4092 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4094 switch (instr
->intrinsic
) {
4095 case nir_intrinsic_image_load
:
4096 case nir_intrinsic_image_store
:
4097 case nir_intrinsic_image_atomic_add
:
4098 case nir_intrinsic_image_atomic_imin
:
4099 case nir_intrinsic_image_atomic_umin
:
4100 case nir_intrinsic_image_atomic_imax
:
4101 case nir_intrinsic_image_atomic_umax
:
4102 case nir_intrinsic_image_atomic_and
:
4103 case nir_intrinsic_image_atomic_or
:
4104 case nir_intrinsic_image_atomic_xor
:
4105 case nir_intrinsic_image_atomic_exchange
:
4106 case nir_intrinsic_image_atomic_comp_swap
:
4107 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4108 get_nir_image_intrinsic_image(bld
, instr
);
4113 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4114 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4118 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4119 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4120 brw_imm_ud(nir_image_intrinsic_coord_components(instr
));
4122 /* Emit an image load, store or atomic op. */
4123 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4124 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4125 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4127 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4128 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4129 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4130 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4131 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4132 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4133 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4134 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4135 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4137 unsigned num_srcs
= info
->num_srcs
;
4138 int op
= brw_aop_for_nir_intrinsic(instr
);
4139 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4140 assert(num_srcs
== 4);
4144 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4148 data
= get_nir_src(instr
->src
[3]);
4149 if (num_srcs
>= 5) {
4150 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4151 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4152 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4155 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4157 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4158 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4163 case nir_intrinsic_image_size
:
4164 case nir_intrinsic_bindless_image_size
: {
4165 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4166 * into will handle the binding table index for us in the geneerator.
4167 * Incidentally, this means that we can handle bindless with exactly the
4170 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4171 BRW_REGISTER_TYPE_UD
);
4172 image
= bld
.emit_uniformize(image
);
4174 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4175 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4176 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4178 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4179 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4180 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4181 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4183 /* Since the image size is always uniform, we can just emit a SIMD8
4184 * query instruction and splat the result out.
4186 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4188 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4189 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4190 tmp
, srcs
, ARRAY_SIZE(srcs
));
4191 inst
->size_written
= 4 * REG_SIZE
;
4193 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4194 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4195 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4196 offset(retype(dest
, tmp
.type
), bld
, c
),
4197 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4199 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4200 component(offset(tmp
, ubld
, c
), 0));
4206 case nir_intrinsic_image_load_raw_intel
: {
4207 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4208 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4209 get_nir_image_intrinsic_image(bld
, instr
);
4210 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4211 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4212 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4215 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4216 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4217 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4221 case nir_intrinsic_image_store_raw_intel
: {
4222 if (stage
== MESA_SHADER_FRAGMENT
)
4223 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4225 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4226 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4227 get_nir_image_intrinsic_image(bld
, instr
);
4228 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4229 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4230 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4231 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4233 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4234 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4238 case nir_intrinsic_scoped_memory_barrier
:
4239 case nir_intrinsic_group_memory_barrier
:
4240 case nir_intrinsic_memory_barrier_shared
:
4241 case nir_intrinsic_memory_barrier_buffer
:
4242 case nir_intrinsic_memory_barrier_image
:
4243 case nir_intrinsic_memory_barrier
:
4244 case nir_intrinsic_begin_invocation_interlock
:
4245 case nir_intrinsic_end_invocation_interlock
: {
4246 bool l3_fence
, slm_fence
;
4247 const enum opcode opcode
=
4248 instr
->intrinsic
== nir_intrinsic_begin_invocation_interlock
?
4249 SHADER_OPCODE_INTERLOCK
: SHADER_OPCODE_MEMORY_FENCE
;
4251 switch (instr
->intrinsic
) {
4252 case nir_intrinsic_scoped_memory_barrier
: {
4253 nir_variable_mode modes
= nir_intrinsic_memory_modes(instr
);
4254 l3_fence
= modes
& (nir_var_shader_out
|
4256 nir_var_mem_global
);
4257 slm_fence
= modes
& nir_var_mem_shared
;
4261 case nir_intrinsic_begin_invocation_interlock
:
4262 case nir_intrinsic_end_invocation_interlock
:
4263 /* For beginInvocationInterlockARB(), we will generate a memory fence
4264 * but with a different opcode so that generator can pick SENDC
4267 * For endInvocationInterlockARB(), we need to insert a memory fence which
4268 * stalls in the shader until the memory transactions prior to that
4269 * fence are complete. This ensures that the shader does not end before
4270 * any writes from its critical section have landed. Otherwise, you can
4271 * end up with a case where the next invocation on that pixel properly
4272 * stalls for previous FS invocation on its pixel to complete but
4273 * doesn't actually wait for the dataport memory transactions from that
4274 * thread to land before submitting its own.
4276 * Handling them here will allow the logic for IVB render cache (see
4277 * below) to be reused.
4284 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4285 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4286 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4287 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4291 if (stage
!= MESA_SHADER_COMPUTE
)
4294 /* If the workgroup fits in a single HW thread, the messages for SLM are
4295 * processed in-order and the shader itself is already synchronized so
4296 * the memory fence is not necessary.
4298 * TODO: Check if applies for many HW threads sharing same Data Port.
4300 if (!nir
->info
.cs
.local_size_variable
&&
4301 slm_fence
&& workgroup_size() <= dispatch_width
)
4304 /* Prior to Gen11, there's only L3 fence, so emit that instead. */
4305 if (slm_fence
&& devinfo
->gen
< 11) {
4310 /* IVB does typed surface access through the render cache, so we need
4313 const bool needs_render_fence
=
4314 devinfo
->gen
== 7 && !devinfo
->is_haswell
;
4316 /* Be conservative in Gen11+ and always stall in a fence. Since there
4317 * are two different fences, and shader might want to synchronize
4320 * TODO: Use scope and visibility information for the barriers from NIR
4321 * to make a better decision on whether we need to stall.
4323 const bool stall
= devinfo
->gen
>= 11 || needs_render_fence
||
4324 instr
->intrinsic
== nir_intrinsic_end_invocation_interlock
;
4326 const bool commit_enable
= stall
||
4327 devinfo
->gen
>= 10; /* HSD ES # 1404612949 */
4329 unsigned fence_regs_count
= 0;
4330 fs_reg fence_regs
[2] = {};
4332 const fs_builder ubld
= bld
.group(8, 0);
4337 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4339 brw_imm_ud(commit_enable
),
4340 brw_imm_ud(/* bti */ 0));
4341 fence
->sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
4343 fence_regs
[fence_regs_count
++] = fence
->dst
;
4345 if (needs_render_fence
) {
4346 fs_inst
*render_fence
=
4348 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4350 brw_imm_ud(commit_enable
),
4351 brw_imm_ud(/* bti */ 0));
4352 render_fence
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4354 fence_regs
[fence_regs_count
++] = render_fence
->dst
;
4359 assert(opcode
== SHADER_OPCODE_MEMORY_FENCE
);
4362 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4364 brw_imm_ud(commit_enable
),
4365 brw_imm_ud(GEN7_BTI_SLM
));
4366 fence
->sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
4368 fence_regs
[fence_regs_count
++] = fence
->dst
;
4371 assert(fence_regs_count
<= 2);
4373 if (stall
|| fence_regs_count
== 0) {
4374 ubld
.exec_all().group(1, 0).emit(
4375 FS_OPCODE_SCHEDULING_FENCE
, ubld
.null_reg_ud(),
4376 fence_regs
, fence_regs_count
);
4382 case nir_intrinsic_memory_barrier_tcs_patch
:
4385 case nir_intrinsic_shader_clock
: {
4386 /* We cannot do anything if there is an event, so ignore it for now */
4387 const fs_reg shader_clock
= get_timestamp(bld
);
4388 const fs_reg srcs
[] = { component(shader_clock
, 0),
4389 component(shader_clock
, 1) };
4390 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4394 case nir_intrinsic_image_samples
:
4395 /* The driver does not support multi-sampled images. */
4396 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4399 case nir_intrinsic_load_uniform
: {
4400 /* Offsets are in bytes but they should always aligned to
4403 assert(instr
->const_index
[0] % 4 == 0 ||
4404 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4406 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4408 if (nir_src_is_const(instr
->src
[0])) {
4409 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4410 assert(load_offset
% type_sz(dest
.type
) == 0);
4411 /* For 16-bit types we add the module of the const_index[0]
4412 * offset to access to not 32-bit aligned element
4414 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4416 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4417 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4420 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4421 BRW_REGISTER_TYPE_UD
);
4423 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4424 * go past the end of the uniform. In order to keep the n'th
4425 * component from running past, we subtract off the size of all but
4426 * one component of the vector.
4428 assert(instr
->const_index
[1] >=
4429 instr
->num_components
* (int) type_sz(dest
.type
));
4430 unsigned read_size
= instr
->const_index
[1] -
4431 (instr
->num_components
- 1) * type_sz(dest
.type
);
4433 bool supports_64bit_indirects
=
4434 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4436 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4437 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4438 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4439 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4440 indirect
, brw_imm_ud(read_size
));
4443 const unsigned num_mov_indirects
=
4444 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4445 /* We read a little bit less per MOV INDIRECT, as they are now
4446 * 32-bits ones instead of 64-bit. Fix read_size then.
4448 const unsigned read_size_32bit
= read_size
-
4449 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4450 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4451 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4452 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4453 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4454 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4455 indirect
, brw_imm_ud(read_size_32bit
));
4463 case nir_intrinsic_load_ubo
: {
4465 if (nir_src_is_const(instr
->src
[0])) {
4466 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4467 nir_src_as_uint(instr
->src
[0]);
4468 surf_index
= brw_imm_ud(index
);
4470 /* The block index is not a constant. Evaluate the index expression
4471 * per-channel and add the base UBO index; we have to select a value
4472 * from any live channel.
4474 surf_index
= vgrf(glsl_type::uint_type
);
4475 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4476 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4477 surf_index
= bld
.emit_uniformize(surf_index
);
4480 if (!nir_src_is_const(instr
->src
[1])) {
4481 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4482 BRW_REGISTER_TYPE_UD
);
4484 for (int i
= 0; i
< instr
->num_components
; i
++)
4485 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4486 base_offset
, i
* type_sz(dest
.type
));
4488 prog_data
->has_ubo_pull
= true;
4490 /* Even if we are loading doubles, a pull constant load will load
4491 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4492 * need to load a full dvec4 we will have to emit 2 loads. This is
4493 * similar to demote_pull_constants(), except that in that case we
4494 * see individual accesses to each component of the vector and then
4495 * we let CSE deal with duplicate loads. Here we see a vector access
4496 * and we have to split it if necessary.
4498 const unsigned type_size
= type_sz(dest
.type
);
4499 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4501 /* See if we've selected this as a push constant candidate */
4502 if (nir_src_is_const(instr
->src
[0])) {
4503 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4504 const unsigned offset_256b
= load_offset
/ 32;
4507 for (int i
= 0; i
< 4; i
++) {
4508 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4509 if (range
->block
== ubo_block
&&
4510 offset_256b
>= range
->start
&&
4511 offset_256b
< range
->start
+ range
->length
) {
4513 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4514 push_reg
.offset
= load_offset
- 32 * range
->start
;
4519 if (push_reg
.file
!= BAD_FILE
) {
4520 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4521 bld
.MOV(offset(dest
, bld
, i
),
4522 byte_offset(push_reg
, i
* type_size
));
4528 prog_data
->has_ubo_pull
= true;
4530 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4531 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4532 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4534 for (unsigned c
= 0; c
< instr
->num_components
;) {
4535 const unsigned base
= load_offset
+ c
* type_size
;
4536 /* Number of usable components in the next block-aligned load. */
4537 const unsigned count
= MIN2(instr
->num_components
- c
,
4538 (block_sz
- base
% block_sz
) / type_size
);
4540 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4541 packed_consts
, surf_index
,
4542 brw_imm_ud(base
& ~(block_sz
- 1)));
4544 const fs_reg consts
=
4545 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4548 for (unsigned d
= 0; d
< count
; d
++)
4549 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4557 case nir_intrinsic_load_global
: {
4558 assert(devinfo
->gen
>= 8);
4560 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4561 assert(nir_intrinsic_align(instr
) > 0);
4562 if (nir_dest_bit_size(instr
->dest
) == 32 &&
4563 nir_intrinsic_align(instr
) >= 4) {
4564 assert(nir_dest_num_components(instr
->dest
) <= 4);
4565 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4567 get_nir_src(instr
->src
[0]), /* Address */
4568 fs_reg(), /* No source data */
4569 brw_imm_ud(instr
->num_components
));
4570 inst
->size_written
= instr
->num_components
*
4571 inst
->dst
.component_size(inst
->exec_size
);
4573 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4574 assert(nir_dest_num_components(instr
->dest
) == 1);
4575 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4576 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4578 get_nir_src(instr
->src
[0]), /* Address */
4579 fs_reg(), /* No source data */
4580 brw_imm_ud(bit_size
));
4581 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4586 case nir_intrinsic_store_global
:
4587 assert(devinfo
->gen
>= 8);
4589 if (stage
== MESA_SHADER_FRAGMENT
)
4590 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4592 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4593 assert(nir_intrinsic_write_mask(instr
) ==
4594 (1u << instr
->num_components
) - 1);
4595 assert(nir_intrinsic_align(instr
) > 0);
4596 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4597 nir_intrinsic_align(instr
) >= 4) {
4598 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4599 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4601 get_nir_src(instr
->src
[1]), /* Address */
4602 get_nir_src(instr
->src
[0]), /* Data */
4603 brw_imm_ud(instr
->num_components
));
4605 assert(nir_src_num_components(instr
->src
[0]) == 1);
4606 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4607 brw_reg_type data_type
=
4608 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4609 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4610 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4611 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4613 get_nir_src(instr
->src
[1]), /* Address */
4615 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4619 case nir_intrinsic_global_atomic_add
:
4620 case nir_intrinsic_global_atomic_imin
:
4621 case nir_intrinsic_global_atomic_umin
:
4622 case nir_intrinsic_global_atomic_imax
:
4623 case nir_intrinsic_global_atomic_umax
:
4624 case nir_intrinsic_global_atomic_and
:
4625 case nir_intrinsic_global_atomic_or
:
4626 case nir_intrinsic_global_atomic_xor
:
4627 case nir_intrinsic_global_atomic_exchange
:
4628 case nir_intrinsic_global_atomic_comp_swap
:
4629 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4631 case nir_intrinsic_global_atomic_fmin
:
4632 case nir_intrinsic_global_atomic_fmax
:
4633 case nir_intrinsic_global_atomic_fcomp_swap
:
4634 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4637 case nir_intrinsic_load_ssbo
: {
4638 assert(devinfo
->gen
>= 7);
4640 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4641 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4642 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4643 get_nir_ssbo_intrinsic_index(bld
, instr
);
4644 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4645 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4647 /* Make dest unsigned because that's what the temporary will be */
4648 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4650 /* Read the vector */
4651 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4652 assert(nir_intrinsic_align(instr
) > 0);
4653 if (nir_dest_bit_size(instr
->dest
) == 32 &&
4654 nir_intrinsic_align(instr
) >= 4) {
4655 assert(nir_dest_num_components(instr
->dest
) <= 4);
4656 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4658 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4659 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4660 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4662 assert(nir_dest_num_components(instr
->dest
) == 1);
4663 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4665 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4666 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4667 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4668 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4673 case nir_intrinsic_store_ssbo
: {
4674 assert(devinfo
->gen
>= 7);
4676 if (stage
== MESA_SHADER_FRAGMENT
)
4677 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4679 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4680 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4681 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4682 get_nir_ssbo_intrinsic_index(bld
, instr
);
4683 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4684 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4686 fs_reg data
= get_nir_src(instr
->src
[0]);
4687 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4689 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4690 assert(nir_intrinsic_write_mask(instr
) ==
4691 (1u << instr
->num_components
) - 1);
4692 assert(nir_intrinsic_align(instr
) > 0);
4693 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4694 nir_intrinsic_align(instr
) >= 4) {
4695 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4696 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4697 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4698 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4699 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4701 assert(nir_src_num_components(instr
->src
[0]) == 1);
4702 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4704 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4705 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4707 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4708 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4713 case nir_intrinsic_store_output
: {
4714 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4715 fs_reg src
= get_nir_src(instr
->src
[0]);
4717 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4718 unsigned num_components
= instr
->num_components
;
4719 unsigned first_component
= nir_intrinsic_component(instr
);
4721 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4722 4 * store_offset
), src
.type
);
4723 for (unsigned j
= 0; j
< num_components
; j
++) {
4724 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4725 offset(src
, bld
, j
));
4730 case nir_intrinsic_ssbo_atomic_add
:
4731 case nir_intrinsic_ssbo_atomic_imin
:
4732 case nir_intrinsic_ssbo_atomic_umin
:
4733 case nir_intrinsic_ssbo_atomic_imax
:
4734 case nir_intrinsic_ssbo_atomic_umax
:
4735 case nir_intrinsic_ssbo_atomic_and
:
4736 case nir_intrinsic_ssbo_atomic_or
:
4737 case nir_intrinsic_ssbo_atomic_xor
:
4738 case nir_intrinsic_ssbo_atomic_exchange
:
4739 case nir_intrinsic_ssbo_atomic_comp_swap
:
4740 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4742 case nir_intrinsic_ssbo_atomic_fmin
:
4743 case nir_intrinsic_ssbo_atomic_fmax
:
4744 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4745 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4748 case nir_intrinsic_get_buffer_size
: {
4749 assert(nir_src_num_components(instr
->src
[0]) == 1);
4750 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4751 nir_src_as_uint(instr
->src
[0]) : 0;
4753 /* A resinfo's sampler message is used to get the buffer size. The
4754 * SIMD8's writeback message consists of four registers and SIMD16's
4755 * writeback message consists of 8 destination registers (two per each
4756 * component). Because we are only interested on the first channel of
4757 * the first returned component, where resinfo returns the buffer size
4758 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4759 * the dispatch width.
4761 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4762 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4763 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4766 ubld
.MOV(src_payload
, brw_imm_d(0));
4768 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4769 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4770 src_payload
, brw_imm_ud(index
));
4771 inst
->header_size
= 0;
4773 inst
->size_written
= 4 * REG_SIZE
;
4775 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4777 * "Out-of-bounds checking is always performed at a DWord granularity. If
4778 * any part of the DWord is out-of-bounds then the whole DWord is
4779 * considered out-of-bounds."
4781 * This implies that types with size smaller than 4-bytes need to be
4782 * padded if they don't complete the last dword of the buffer. But as we
4783 * need to maintain the original size we need to reverse the padding
4784 * calculation to return the correct size to know the number of elements
4785 * of an unsized array. As we stored in the last two bits of the surface
4786 * size the needed padding for the buffer, we calculate here the
4787 * original buffer_size reversing the surface_size calculation:
4789 * surface_size = isl_align(buffer_size, 4) +
4790 * (isl_align(buffer_size) - buffer_size)
4792 * buffer_size = surface_size & ~3 - surface_size & 3
4795 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4796 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4797 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4799 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4800 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4801 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4803 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4807 case nir_intrinsic_load_scratch
: {
4808 assert(devinfo
->gen
>= 7);
4810 assert(nir_dest_num_components(instr
->dest
) == 1);
4811 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4812 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4814 if (devinfo
->gen
>= 8) {
4815 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4816 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4818 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4821 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4822 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4823 const fs_reg nir_addr
= get_nir_src(instr
->src
[0]);
4825 /* Make dest unsigned because that's what the temporary will be */
4826 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4828 /* Read the vector */
4829 assert(nir_dest_num_components(instr
->dest
) == 1);
4830 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4831 assert(nir_intrinsic_align(instr
) > 1);
4832 if (nir_dest_bit_size(instr
->dest
) >= 4 &&
4833 nir_intrinsic_align(instr
) >= 4) {
4834 /* The offset for a DWORD scattered message is in dwords. */
4835 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4836 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4838 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
,
4839 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4841 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4842 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4844 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4845 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4846 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4847 bld
.MOV(dest
, read_result
);
4852 case nir_intrinsic_store_scratch
: {
4853 assert(devinfo
->gen
>= 7);
4855 assert(nir_src_num_components(instr
->src
[0]) == 1);
4856 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4857 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4859 if (devinfo
->gen
>= 8) {
4860 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4861 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4863 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4866 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4867 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4868 const fs_reg nir_addr
= get_nir_src(instr
->src
[1]);
4870 fs_reg data
= get_nir_src(instr
->src
[0]);
4871 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4873 assert(nir_src_num_components(instr
->src
[0]) == 1);
4874 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4875 assert(nir_intrinsic_write_mask(instr
) == 1);
4876 assert(nir_intrinsic_align(instr
) > 1);
4877 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4878 nir_intrinsic_align(instr
) >= 4) {
4879 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4881 /* The offset for a DWORD scattered message is in dwords. */
4882 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4883 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4885 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
,
4886 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4888 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4889 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4891 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4892 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4894 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4895 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4900 case nir_intrinsic_load_subgroup_size
:
4901 /* This should only happen for fragment shaders because every other case
4902 * is lowered in NIR so we can optimize on it.
4904 assert(stage
== MESA_SHADER_FRAGMENT
);
4905 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4908 case nir_intrinsic_load_subgroup_invocation
:
4909 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4910 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4913 case nir_intrinsic_load_subgroup_eq_mask
:
4914 case nir_intrinsic_load_subgroup_ge_mask
:
4915 case nir_intrinsic_load_subgroup_gt_mask
:
4916 case nir_intrinsic_load_subgroup_le_mask
:
4917 case nir_intrinsic_load_subgroup_lt_mask
:
4918 unreachable("not reached");
4920 case nir_intrinsic_vote_any
: {
4921 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4923 /* The any/all predicates do not consider channel enables. To prevent
4924 * dead channels from affecting the result, we initialize the flag with
4925 * with the identity value for the logical operation.
4927 if (dispatch_width
== 32) {
4928 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4929 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4932 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4934 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4936 /* For some reason, the any/all predicates don't work properly with
4937 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4938 * doesn't read the correct subset of the flag register and you end up
4939 * getting garbage in the second half. Work around this by using a pair
4940 * of 1-wide MOVs and scattering the result.
4942 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4943 ubld
.MOV(res1
, brw_imm_d(0));
4944 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4945 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4946 BRW_PREDICATE_ALIGN1_ANY32H
,
4947 ubld
.MOV(res1
, brw_imm_d(-1)));
4949 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4952 case nir_intrinsic_vote_all
: {
4953 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4955 /* The any/all predicates do not consider channel enables. To prevent
4956 * dead channels from affecting the result, we initialize the flag with
4957 * with the identity value for the logical operation.
4959 if (dispatch_width
== 32) {
4960 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4961 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4962 brw_imm_ud(0xffffffff));
4964 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4966 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4968 /* For some reason, the any/all predicates don't work properly with
4969 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4970 * doesn't read the correct subset of the flag register and you end up
4971 * getting garbage in the second half. Work around this by using a pair
4972 * of 1-wide MOVs and scattering the result.
4974 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4975 ubld
.MOV(res1
, brw_imm_d(0));
4976 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4977 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4978 BRW_PREDICATE_ALIGN1_ALL32H
,
4979 ubld
.MOV(res1
, brw_imm_d(-1)));
4981 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4984 case nir_intrinsic_vote_feq
:
4985 case nir_intrinsic_vote_ieq
: {
4986 fs_reg value
= get_nir_src(instr
->src
[0]);
4987 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4988 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4989 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4990 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4993 fs_reg uniformized
= bld
.emit_uniformize(value
);
4994 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4996 /* The any/all predicates do not consider channel enables. To prevent
4997 * dead channels from affecting the result, we initialize the flag with
4998 * with the identity value for the logical operation.
5000 if (dispatch_width
== 32) {
5001 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
5002 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
5003 brw_imm_ud(0xffffffff));
5005 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
5007 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
5009 /* For some reason, the any/all predicates don't work properly with
5010 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
5011 * doesn't read the correct subset of the flag register and you end up
5012 * getting garbage in the second half. Work around this by using a pair
5013 * of 1-wide MOVs and scattering the result.
5015 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
5016 ubld
.MOV(res1
, brw_imm_d(0));
5017 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
5018 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
5019 BRW_PREDICATE_ALIGN1_ALL32H
,
5020 ubld
.MOV(res1
, brw_imm_d(-1)));
5022 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
5026 case nir_intrinsic_ballot
: {
5027 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
5028 BRW_REGISTER_TYPE_UD
);
5029 struct brw_reg flag
= brw_flag_reg(0, 0);
5030 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
5031 * as f0.0. This is a problem for fragment programs as we currently use
5032 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
5033 * programs yet so this isn't a problem. When we do, something will
5036 if (dispatch_width
== 32)
5037 flag
.type
= BRW_REGISTER_TYPE_UD
;
5039 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
5040 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
5042 if (instr
->dest
.ssa
.bit_size
> 32) {
5043 dest
.type
= BRW_REGISTER_TYPE_UQ
;
5045 dest
.type
= BRW_REGISTER_TYPE_UD
;
5047 bld
.MOV(dest
, flag
);
5051 case nir_intrinsic_read_invocation
: {
5052 const fs_reg value
= get_nir_src(instr
->src
[0]);
5053 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
5054 fs_reg tmp
= bld
.vgrf(value
.type
);
5056 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
5057 bld
.emit_uniformize(invocation
));
5059 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
5063 case nir_intrinsic_read_first_invocation
: {
5064 const fs_reg value
= get_nir_src(instr
->src
[0]);
5065 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
5069 case nir_intrinsic_shuffle
: {
5070 const fs_reg value
= get_nir_src(instr
->src
[0]);
5071 const fs_reg index
= get_nir_src(instr
->src
[1]);
5073 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
5077 case nir_intrinsic_first_invocation
: {
5078 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5079 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
5080 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
5081 fs_reg(component(tmp
, 0)));
5085 case nir_intrinsic_quad_broadcast
: {
5086 const fs_reg value
= get_nir_src(instr
->src
[0]);
5087 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
5089 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
5090 value
, brw_imm_ud(index
), brw_imm_ud(4));
5094 case nir_intrinsic_quad_swap_horizontal
: {
5095 const fs_reg value
= get_nir_src(instr
->src
[0]);
5096 const fs_reg tmp
= bld
.vgrf(value
.type
);
5097 if (devinfo
->gen
<= 7) {
5098 /* The hardware doesn't seem to support these crazy regions with
5099 * compressed instructions on gen7 and earlier so we fall back to
5100 * using quad swizzles. Fortunately, we don't support 64-bit
5101 * anything in Vulkan on gen7.
5103 assert(nir_src_bit_size(instr
->src
[0]) == 32);
5104 const fs_builder ubld
= bld
.exec_all();
5105 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5106 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
5107 bld
.MOV(retype(dest
, value
.type
), tmp
);
5109 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
5111 const fs_reg src_left
= horiz_stride(value
, 2);
5112 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
5113 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
5114 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
5116 ubld
.MOV(tmp_left
, src_right
);
5117 ubld
.MOV(tmp_right
, src_left
);
5120 bld
.MOV(retype(dest
, value
.type
), tmp
);
5124 case nir_intrinsic_quad_swap_vertical
: {
5125 const fs_reg value
= get_nir_src(instr
->src
[0]);
5126 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5127 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5128 const fs_reg tmp
= bld
.vgrf(value
.type
);
5129 const fs_builder ubld
= bld
.exec_all();
5130 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5131 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
5132 bld
.MOV(retype(dest
, value
.type
), tmp
);
5134 /* For larger data types, we have to either emit dispatch_width many
5135 * MOVs or else fall back to doing indirects.
5137 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5138 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5140 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5145 case nir_intrinsic_quad_swap_diagonal
: {
5146 const fs_reg value
= get_nir_src(instr
->src
[0]);
5147 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5148 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5149 const fs_reg tmp
= bld
.vgrf(value
.type
);
5150 const fs_builder ubld
= bld
.exec_all();
5151 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5152 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
5153 bld
.MOV(retype(dest
, value
.type
), tmp
);
5155 /* For larger data types, we have to either emit dispatch_width many
5156 * MOVs or else fall back to doing indirects.
5158 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5159 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5161 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5166 case nir_intrinsic_reduce
: {
5167 fs_reg src
= get_nir_src(instr
->src
[0]);
5168 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5169 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
5170 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
5171 cluster_size
= dispatch_width
;
5173 /* Figure out the source type */
5174 src
.type
= brw_type_for_nir_type(devinfo
,
5175 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5176 nir_src_bit_size(instr
->src
[0])));
5178 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5179 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5180 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5182 /* There are a couple of register region issues that make things
5183 * complicated for 8-bit types:
5185 * 1. Only raw moves are allowed to write to a packed 8-bit
5187 * 2. If we use a strided destination, the efficient way to do scan
5188 * operations ends up using strides that are too big to encode in
5191 * To get around these issues, we just do all 8-bit scan operations in
5192 * 16 bits. It's actually fewer instructions than what we'd have to do
5193 * if we were trying to do it in native 8-bit types and the results are
5194 * the same once we truncate to 8 bits at the end.
5196 brw_reg_type scan_type
= src
.type
;
5197 if (type_sz(scan_type
) == 1)
5198 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5200 /* Set up a register for all of our scratching around and initialize it
5201 * to reduction operation's identity value.
5203 fs_reg scan
= bld
.vgrf(scan_type
);
5204 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5206 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
5208 dest
.type
= src
.type
;
5209 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
5210 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
5211 * the distance between clusters is at least 2 GRFs. In this case,
5212 * we don't need the weird striding of the CLUSTER_BROADCAST
5213 * instruction and can just do regular MOVs.
5215 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5216 const unsigned groups
=
5217 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5218 const unsigned group_size
= dispatch_width
/ groups
;
5219 for (unsigned i
= 0; i
< groups
; i
++) {
5220 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5221 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5222 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5223 component(scan
, comp
));
5226 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5227 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5232 case nir_intrinsic_inclusive_scan
:
5233 case nir_intrinsic_exclusive_scan
: {
5234 fs_reg src
= get_nir_src(instr
->src
[0]);
5235 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5237 /* Figure out the source type */
5238 src
.type
= brw_type_for_nir_type(devinfo
,
5239 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5240 nir_src_bit_size(instr
->src
[0])));
5242 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5243 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5244 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5246 /* There are a couple of register region issues that make things
5247 * complicated for 8-bit types:
5249 * 1. Only raw moves are allowed to write to a packed 8-bit
5251 * 2. If we use a strided destination, the efficient way to do scan
5252 * operations ends up using strides that are too big to encode in
5255 * To get around these issues, we just do all 8-bit scan operations in
5256 * 16 bits. It's actually fewer instructions than what we'd have to do
5257 * if we were trying to do it in native 8-bit types and the results are
5258 * the same once we truncate to 8 bits at the end.
5260 brw_reg_type scan_type
= src
.type
;
5261 if (type_sz(scan_type
) == 1)
5262 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5264 /* Set up a register for all of our scratching around and initialize it
5265 * to reduction operation's identity value.
5267 fs_reg scan
= bld
.vgrf(scan_type
);
5268 const fs_builder allbld
= bld
.exec_all();
5269 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5271 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5272 /* Exclusive scan is a bit harder because we have to do an annoying
5273 * shift of the contents before we can begin. To make things worse,
5274 * we can't do this with a normal stride; we have to use indirects.
5276 fs_reg shifted
= bld
.vgrf(scan_type
);
5277 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5278 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5280 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5281 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5285 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5287 bld
.MOV(retype(dest
, src
.type
), scan
);
5292 unreachable("unknown intrinsic");
5297 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5298 int op
, nir_intrinsic_instr
*instr
)
5300 if (stage
== MESA_SHADER_FRAGMENT
)
5301 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5303 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5304 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5305 * appear to exist. However, if you look at Vol 2a, there are no message
5306 * descriptors provided for Qword atomic ops except for A64 messages.
5308 assert(nir_dest_bit_size(instr
->dest
) == 32);
5311 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5312 dest
= get_nir_dest(instr
->dest
);
5314 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5315 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5316 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5317 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5318 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5321 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5322 data
= get_nir_src(instr
->src
[2]);
5324 if (op
== BRW_AOP_CMPWR
) {
5325 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5326 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5327 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5330 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5332 /* Emit the actual atomic operation */
5334 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5335 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5339 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5340 int op
, nir_intrinsic_instr
*instr
)
5342 if (stage
== MESA_SHADER_FRAGMENT
)
5343 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5346 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5347 dest
= get_nir_dest(instr
->dest
);
5349 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5350 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5351 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5352 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5353 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5355 fs_reg data
= get_nir_src(instr
->src
[2]);
5356 if (op
== BRW_AOP_FCMPWR
) {
5357 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5358 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5359 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5362 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5364 /* Emit the actual atomic operation */
5366 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5367 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5371 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5372 int op
, nir_intrinsic_instr
*instr
)
5375 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5376 dest
= get_nir_dest(instr
->dest
);
5378 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5379 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5380 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5381 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5384 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5385 data
= get_nir_src(instr
->src
[1]);
5386 if (op
== BRW_AOP_CMPWR
) {
5387 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5388 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5389 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5392 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5394 /* Get the offset */
5395 if (nir_src_is_const(instr
->src
[0])) {
5396 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5397 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5399 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5400 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5401 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5402 brw_imm_ud(instr
->const_index
[0]));
5405 /* Emit the actual atomic operation operation */
5407 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5408 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5412 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5413 int op
, nir_intrinsic_instr
*instr
)
5416 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5417 dest
= get_nir_dest(instr
->dest
);
5419 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5420 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5421 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5422 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5424 fs_reg data
= get_nir_src(instr
->src
[1]);
5425 if (op
== BRW_AOP_FCMPWR
) {
5426 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5427 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5428 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5431 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5433 /* Get the offset */
5434 if (nir_src_is_const(instr
->src
[0])) {
5435 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5436 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5438 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5439 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5440 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5441 brw_imm_ud(instr
->const_index
[0]));
5444 /* Emit the actual atomic operation operation */
5446 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5447 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5451 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5452 int op
, nir_intrinsic_instr
*instr
)
5454 if (stage
== MESA_SHADER_FRAGMENT
)
5455 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5458 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5459 dest
= get_nir_dest(instr
->dest
);
5461 fs_reg addr
= get_nir_src(instr
->src
[0]);
5464 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5465 data
= get_nir_src(instr
->src
[1]);
5467 if (op
== BRW_AOP_CMPWR
) {
5468 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5469 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5470 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5474 if (nir_dest_bit_size(instr
->dest
) == 64) {
5475 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5476 dest
, addr
, data
, brw_imm_ud(op
));
5478 assert(nir_dest_bit_size(instr
->dest
) == 32);
5479 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5480 dest
, addr
, data
, brw_imm_ud(op
));
5485 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5486 int op
, nir_intrinsic_instr
*instr
)
5488 if (stage
== MESA_SHADER_FRAGMENT
)
5489 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5491 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5492 fs_reg dest
= get_nir_dest(instr
->dest
);
5494 fs_reg addr
= get_nir_src(instr
->src
[0]);
5496 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5497 fs_reg data
= get_nir_src(instr
->src
[1]);
5499 if (op
== BRW_AOP_FCMPWR
) {
5500 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5501 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5502 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5506 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5507 dest
, addr
, data
, brw_imm_ud(op
));
5511 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5513 unsigned texture
= instr
->texture_index
;
5514 unsigned sampler
= instr
->sampler_index
;
5516 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5518 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5519 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5521 int lod_components
= 0;
5523 /* The hardware requires a LOD for buffer textures */
5524 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5525 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5527 uint32_t header_bits
= 0;
5528 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5529 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5530 switch (instr
->src
[i
].src_type
) {
5531 case nir_tex_src_bias
:
5532 srcs
[TEX_LOGICAL_SRC_LOD
] =
5533 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5535 case nir_tex_src_comparator
:
5536 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5538 case nir_tex_src_coord
:
5539 switch (instr
->op
) {
5541 case nir_texop_txf_ms
:
5542 case nir_texop_txf_ms_mcs
:
5543 case nir_texop_samples_identical
:
5544 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5547 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5551 case nir_tex_src_ddx
:
5552 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5553 lod_components
= nir_tex_instr_src_size(instr
, i
);
5555 case nir_tex_src_ddy
:
5556 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5558 case nir_tex_src_lod
:
5559 switch (instr
->op
) {
5561 srcs
[TEX_LOGICAL_SRC_LOD
] =
5562 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5565 srcs
[TEX_LOGICAL_SRC_LOD
] =
5566 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5569 srcs
[TEX_LOGICAL_SRC_LOD
] =
5570 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5574 case nir_tex_src_min_lod
:
5575 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5576 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5578 case nir_tex_src_ms_index
:
5579 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5582 case nir_tex_src_offset
: {
5583 uint32_t offset_bits
= 0;
5584 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5585 header_bits
|= offset_bits
;
5587 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5588 retype(src
, BRW_REGISTER_TYPE_D
);
5593 case nir_tex_src_projector
:
5594 unreachable("should be lowered");
5596 case nir_tex_src_texture_offset
: {
5597 /* Emit code to evaluate the actual indexing expression */
5598 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5599 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5600 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5604 case nir_tex_src_sampler_offset
: {
5605 /* Emit code to evaluate the actual indexing expression */
5606 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5607 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5608 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5612 case nir_tex_src_texture_handle
:
5613 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5614 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5615 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5618 case nir_tex_src_sampler_handle
:
5619 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5620 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5621 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5624 case nir_tex_src_ms_mcs
:
5625 assert(instr
->op
== nir_texop_txf_ms
);
5626 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5629 case nir_tex_src_plane
: {
5630 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5631 const uint32_t texture_index
=
5632 instr
->texture_index
+
5633 stage_prog_data
->binding_table
.plane_start
[plane
] -
5634 stage_prog_data
->binding_table
.texture_start
;
5636 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5641 unreachable("unknown texture source");
5645 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5646 (instr
->op
== nir_texop_txf_ms
||
5647 instr
->op
== nir_texop_samples_identical
)) {
5648 if (devinfo
->gen
>= 7 &&
5649 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5650 srcs
[TEX_LOGICAL_SRC_MCS
] =
5651 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5652 instr
->coord_components
,
5653 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5654 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5656 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5660 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5661 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5664 switch (instr
->op
) {
5666 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5669 opcode
= FS_OPCODE_TXB_LOGICAL
;
5672 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5675 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5678 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5680 case nir_texop_txf_ms
:
5681 if ((key_tex
->msaa_16
& (1 << sampler
)))
5682 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5684 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5686 case nir_texop_txf_ms_mcs
:
5687 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5689 case nir_texop_query_levels
:
5691 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5694 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5697 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5698 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5700 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5702 case nir_texop_texture_samples
:
5703 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5705 case nir_texop_samples_identical
: {
5706 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5708 /* If mcs is an immediate value, it means there is no MCS. In that case
5709 * just return false.
5711 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5712 bld
.MOV(dst
, brw_imm_ud(0u));
5713 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5714 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5715 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5716 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5717 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5719 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5720 BRW_CONDITIONAL_EQ
);
5725 unreachable("unknown texture opcode");
5728 if (instr
->op
== nir_texop_tg4
) {
5729 if (instr
->component
== 1 &&
5730 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5731 /* gather4 sampler is broken for green channel on RG32F --
5732 * we must ask for blue instead.
5734 header_bits
|= 2 << 16;
5736 header_bits
|= instr
->component
<< 16;
5740 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5741 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5742 inst
->offset
= header_bits
;
5744 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5745 if (devinfo
->gen
>= 9 &&
5746 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5747 unsigned write_mask
= instr
->dest
.is_ssa
?
5748 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5749 (1 << dest_size
) - 1;
5750 assert(write_mask
!= 0); /* dead code should have been eliminated */
5751 inst
->size_written
= util_last_bit(write_mask
) *
5752 inst
->dst
.component_size(inst
->exec_size
);
5754 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5757 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5758 inst
->shadow_compare
= true;
5760 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5761 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5764 for (unsigned i
= 0; i
< dest_size
; i
++)
5765 nir_dest
[i
] = offset(dst
, bld
, i
);
5767 if (instr
->op
== nir_texop_query_levels
) {
5768 /* # levels is in .w */
5769 nir_dest
[0] = offset(dst
, bld
, 3);
5770 } else if (instr
->op
== nir_texop_txs
&&
5771 dest_size
>= 3 && devinfo
->gen
< 7) {
5772 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5773 fs_reg depth
= offset(dst
, bld
, 2);
5774 nir_dest
[2] = vgrf(glsl_type::int_type
);
5775 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5778 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5782 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5784 switch (instr
->type
) {
5785 case nir_jump_break
:
5786 bld
.emit(BRW_OPCODE_BREAK
);
5788 case nir_jump_continue
:
5789 bld
.emit(BRW_OPCODE_CONTINUE
);
5791 case nir_jump_return
:
5793 unreachable("unknown jump");
5798 * This helper takes a source register and un/shuffles it into the destination
5801 * If source type size is smaller than destination type size the operation
5802 * needed is a component shuffle. The opposite case would be an unshuffle. If
5803 * source/destination type size is equal a shuffle is done that would be
5804 * equivalent to a simple MOV.
5806 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5807 * components .xyz 16-bit vector on SIMD8 would be.
5809 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5810 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5812 * This helper will return the following 2 32-bit components with the 16-bit
5815 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5816 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5818 * For unshuffle, the example would be the opposite, a 64-bit type source
5819 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5822 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5823 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5824 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5825 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5827 * The returned result would be the following 4 32-bit components unshuffled:
5829 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5830 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5831 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5832 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5834 * - Source and destination register must not be overlapped.
5835 * - components units are measured in terms of the smaller type between
5836 * source and destination because we are un/shuffling the smaller
5837 * components from/into the bigger ones.
5838 * - first_component parameter allows skipping source components.
5841 shuffle_src_to_dst(const fs_builder
&bld
,
5844 uint32_t first_component
,
5845 uint32_t components
)
5847 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5848 assert(!regions_overlap(dst
,
5849 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5850 offset(src
, bld
, first_component
),
5851 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5852 for (unsigned i
= 0; i
< components
; i
++) {
5853 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5854 offset(src
, bld
, i
+ first_component
));
5856 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5857 /* Source is shuffled into destination */
5858 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5859 assert(!regions_overlap(dst
,
5860 type_sz(dst
.type
) * bld
.dispatch_width() *
5861 DIV_ROUND_UP(components
, size_ratio
),
5862 offset(src
, bld
, first_component
),
5863 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5865 brw_reg_type shuffle_type
=
5866 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5867 BRW_REGISTER_TYPE_D
);
5868 for (unsigned i
= 0; i
< components
; i
++) {
5869 fs_reg shuffle_component_i
=
5870 subscript(offset(dst
, bld
, i
/ size_ratio
),
5871 shuffle_type
, i
% size_ratio
);
5872 bld
.MOV(shuffle_component_i
,
5873 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5876 /* Source is unshuffled into destination */
5877 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5878 assert(!regions_overlap(dst
,
5879 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5880 offset(src
, bld
, first_component
/ size_ratio
),
5881 type_sz(src
.type
) * bld
.dispatch_width() *
5882 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5885 brw_reg_type shuffle_type
=
5886 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5887 BRW_REGISTER_TYPE_D
);
5888 for (unsigned i
= 0; i
< components
; i
++) {
5889 fs_reg shuffle_component_i
=
5890 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5891 shuffle_type
, (first_component
+ i
) % size_ratio
);
5892 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5893 shuffle_component_i
);
5899 shuffle_from_32bit_read(const fs_builder
&bld
,
5902 uint32_t first_component
,
5903 uint32_t components
)
5905 assert(type_sz(src
.type
) == 4);
5907 /* This function takes components in units of the destination type while
5908 * shuffle_src_to_dst takes components in units of the smallest type
5910 if (type_sz(dst
.type
) > 4) {
5911 assert(type_sz(dst
.type
) == 8);
5912 first_component
*= 2;
5916 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5920 setup_imm_df(const fs_builder
&bld
, double v
)
5922 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5923 assert(devinfo
->gen
>= 7);
5925 if (devinfo
->gen
>= 8)
5926 return brw_imm_df(v
);
5928 /* gen7.5 does not support DF immediates straighforward but the DIM
5929 * instruction allows to set the 64-bit immediate value.
5931 if (devinfo
->is_haswell
) {
5932 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5933 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5934 ubld
.DIM(dst
, brw_imm_df(v
));
5935 return component(dst
, 0);
5938 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5939 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5940 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5942 * Alternatively, we could also produce a normal VGRF (without stride 0)
5943 * by writing to all the channels in the VGRF, however, that would hit the
5944 * gen7 bug where we have to split writes that span more than 1 register
5945 * into instructions with a width of 4 (otherwise the write to the second
5946 * register written runs into an execmask hardware bug) which isn't very
5959 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5960 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5961 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5962 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5964 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5968 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5970 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5971 bld
.MOV(tmp
, brw_imm_w(v
));
5976 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5978 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5979 bld
.MOV(tmp
, brw_imm_uw(v
));