2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
45 last_scratch
= ALIGN(nir
->scratch_size
, 4) * dispatch_width
;
47 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
, true);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
) {
104 /* Add uniforms for builtins after regular NIR uniforms. */
105 assert(uniforms
== prog_data
->nr_params
);
108 if (nir
->info
.cs
.local_size_variable
&&
109 compiler
->lower_variable_group_size
) {
110 param
= brw_stage_prog_data_add_params(prog_data
, 3);
111 for (unsigned i
= 0; i
< 3; i
++) {
112 param
[i
] = (BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X
+ i
);
113 group_size
[i
] = fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
117 /* Subgroup ID must be the last uniform on the list. This will make
118 * easier later to split between cross thread and per thread
121 param
= brw_stage_prog_data_add_params(prog_data
, 1);
122 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
123 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
128 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
132 nir_foreach_instr(instr
, block
) {
133 if (instr
->type
!= nir_instr_type_intrinsic
)
136 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
137 switch (intrin
->intrinsic
) {
138 case nir_intrinsic_load_vertex_id
:
139 case nir_intrinsic_load_base_vertex
:
140 unreachable("should be lowered by nir_lower_system_values().");
142 case nir_intrinsic_load_vertex_id_zero_base
:
143 case nir_intrinsic_load_is_indexed_draw
:
144 case nir_intrinsic_load_first_vertex
:
145 case nir_intrinsic_load_instance_id
:
146 case nir_intrinsic_load_base_instance
:
147 case nir_intrinsic_load_draw_id
:
148 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
150 case nir_intrinsic_load_invocation_id
:
151 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
153 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
154 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
155 if (reg
->file
== BAD_FILE
) {
156 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
157 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
158 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
159 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
164 case nir_intrinsic_load_sample_pos
:
165 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
166 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
167 if (reg
->file
== BAD_FILE
)
168 *reg
= *v
->emit_samplepos_setup();
171 case nir_intrinsic_load_sample_id
:
172 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
173 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
174 if (reg
->file
== BAD_FILE
)
175 *reg
= *v
->emit_sampleid_setup();
178 case nir_intrinsic_load_sample_mask_in
:
179 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
180 assert(v
->devinfo
->gen
>= 7);
181 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
182 if (reg
->file
== BAD_FILE
)
183 *reg
= *v
->emit_samplemaskin_setup();
186 case nir_intrinsic_load_work_group_id
:
187 assert(v
->stage
== MESA_SHADER_COMPUTE
);
188 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
189 if (reg
->file
== BAD_FILE
)
190 *reg
= *v
->emit_cs_work_group_id_setup();
193 case nir_intrinsic_load_helper_invocation
:
194 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
195 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
196 if (reg
->file
== BAD_FILE
) {
197 const fs_builder abld
=
198 v
->bld
.annotate("gl_HelperInvocation", NULL
);
200 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
201 * pixel mask is in g1.7 of the thread payload.
203 * We move the per-channel pixel enable bit to the low bit of each
204 * channel by shifting the byte containing the pixel mask by the
205 * vector immediate 0x76543210UV.
207 * The region of <1,8,0> reads only 1 byte (the pixel masks for
208 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
209 * masks for 2 and 3) in SIMD16.
211 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
213 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
214 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
215 hbld
.SHR(offset(shifted
, hbld
, i
),
216 stride(retype(brw_vec1_grf(1 + i
, 7),
217 BRW_REGISTER_TYPE_UB
),
219 brw_imm_v(0x76543210));
222 /* A set bit in the pixel mask means the channel is enabled, but
223 * that is the opposite of gl_HelperInvocation so we need to invert
226 * The negate source-modifier bit of logical instructions on Gen8+
227 * performs 1's complement negation, so we can use that instead of
230 fs_reg inverted
= negate(shifted
);
231 if (v
->devinfo
->gen
< 8) {
232 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
233 abld
.NOT(inverted
, shifted
);
236 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
237 * with 1 and negating.
239 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
240 abld
.AND(anded
, inverted
, brw_imm_uw(1));
242 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
243 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
257 fs_visitor::nir_emit_system_values()
259 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
260 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
261 nir_system_values
[i
] = fs_reg();
264 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
265 * never end up using it.
268 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
269 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
270 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
272 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
273 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
274 if (dispatch_width
> 8)
275 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
276 if (dispatch_width
> 16) {
277 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
278 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
282 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
283 nir_foreach_block(block
, impl
)
284 emit_system_values_block(block
, this);
288 * Returns a type based on a reference_type (word, float, half-float) and a
291 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
293 * @FIXME: 64-bit return types are always DF on integer types to maintain
294 * compability with uses of DF previously to the introduction of int64
298 brw_reg_type_from_bit_size(const unsigned bit_size
,
299 const brw_reg_type reference_type
)
301 switch(reference_type
) {
302 case BRW_REGISTER_TYPE_HF
:
303 case BRW_REGISTER_TYPE_F
:
304 case BRW_REGISTER_TYPE_DF
:
307 return BRW_REGISTER_TYPE_HF
;
309 return BRW_REGISTER_TYPE_F
;
311 return BRW_REGISTER_TYPE_DF
;
313 unreachable("Invalid bit size");
315 case BRW_REGISTER_TYPE_B
:
316 case BRW_REGISTER_TYPE_W
:
317 case BRW_REGISTER_TYPE_D
:
318 case BRW_REGISTER_TYPE_Q
:
321 return BRW_REGISTER_TYPE_B
;
323 return BRW_REGISTER_TYPE_W
;
325 return BRW_REGISTER_TYPE_D
;
327 return BRW_REGISTER_TYPE_Q
;
329 unreachable("Invalid bit size");
331 case BRW_REGISTER_TYPE_UB
:
332 case BRW_REGISTER_TYPE_UW
:
333 case BRW_REGISTER_TYPE_UD
:
334 case BRW_REGISTER_TYPE_UQ
:
337 return BRW_REGISTER_TYPE_UB
;
339 return BRW_REGISTER_TYPE_UW
;
341 return BRW_REGISTER_TYPE_UD
;
343 return BRW_REGISTER_TYPE_UQ
;
345 unreachable("Invalid bit size");
348 unreachable("Unknown type");
353 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
355 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
356 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
357 nir_locals
[i
] = fs_reg();
360 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
361 unsigned array_elems
=
362 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
363 unsigned size
= array_elems
* reg
->num_components
;
364 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
365 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
366 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
369 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
372 nir_emit_cf_list(&impl
->body
);
376 fs_visitor::nir_emit_cf_list(exec_list
*list
)
378 exec_list_validate(list
);
379 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
380 switch (node
->type
) {
382 nir_emit_if(nir_cf_node_as_if(node
));
385 case nir_cf_node_loop
:
386 nir_emit_loop(nir_cf_node_as_loop(node
));
389 case nir_cf_node_block
:
390 nir_emit_block(nir_cf_node_as_block(node
));
394 unreachable("Invalid CFG node block");
400 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
405 /* If the condition has the form !other_condition, use other_condition as
406 * the source, but invert the predicate on the if instruction.
408 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
409 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
411 cond_reg
= get_nir_src(cond
->src
[0].src
);
414 cond_reg
= get_nir_src(if_stmt
->condition
);
417 /* first, put the condition into f0 */
418 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
419 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
420 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
422 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
424 nir_emit_cf_list(&if_stmt
->then_list
);
426 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
427 bld
.emit(BRW_OPCODE_ELSE
);
428 nir_emit_cf_list(&if_stmt
->else_list
);
431 bld
.emit(BRW_OPCODE_ENDIF
);
433 if (devinfo
->gen
< 7)
434 limit_dispatch_width(16, "Non-uniform control flow unsupported "
439 fs_visitor::nir_emit_loop(nir_loop
*loop
)
441 bld
.emit(BRW_OPCODE_DO
);
443 nir_emit_cf_list(&loop
->body
);
445 bld
.emit(BRW_OPCODE_WHILE
);
447 if (devinfo
->gen
< 7)
448 limit_dispatch_width(16, "Non-uniform control flow unsupported "
453 fs_visitor::nir_emit_block(nir_block
*block
)
455 nir_foreach_instr(instr
, block
) {
456 nir_emit_instr(instr
);
461 fs_visitor::nir_emit_instr(nir_instr
*instr
)
463 const fs_builder abld
= bld
.annotate(NULL
, instr
);
465 switch (instr
->type
) {
466 case nir_instr_type_alu
:
467 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
470 case nir_instr_type_deref
:
471 unreachable("All derefs should've been lowered");
474 case nir_instr_type_intrinsic
:
476 case MESA_SHADER_VERTEX
:
477 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
479 case MESA_SHADER_TESS_CTRL
:
480 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
482 case MESA_SHADER_TESS_EVAL
:
483 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
485 case MESA_SHADER_GEOMETRY
:
486 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
488 case MESA_SHADER_FRAGMENT
:
489 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
491 case MESA_SHADER_COMPUTE
:
492 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
495 unreachable("unsupported shader stage");
499 case nir_instr_type_tex
:
500 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
503 case nir_instr_type_load_const
:
504 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
507 case nir_instr_type_ssa_undef
:
508 /* We create a new VGRF for undefs on every use (by handling
509 * them in get_nir_src()), rather than for each definition.
510 * This helps register coalescing eliminate MOVs from undef.
514 case nir_instr_type_jump
:
515 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
519 unreachable("unknown instruction type");
524 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
528 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
529 const fs_reg
&result
)
531 if (!instr
->src
[0].src
.is_ssa
||
532 !instr
->src
[0].src
.ssa
->parent_instr
)
535 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
538 nir_alu_instr
*src0
=
539 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
541 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
542 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
545 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
547 /* Element type to extract.*/
548 const brw_reg_type type
= brw_int_type(
549 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
550 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
552 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
553 op0
.type
= brw_type_for_nir_type(devinfo
,
554 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
555 nir_src_bit_size(src0
->src
[0].src
)));
556 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
558 bld
.MOV(result
, subscript(op0
, type
, element
));
563 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
564 const fs_reg
&result
)
566 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
567 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
570 if (!nir_src_is_const(instr
->src
[1].src
) ||
571 !nir_src_is_const(instr
->src
[2].src
))
574 const float value1
= nir_src_as_float(instr
->src
[1].src
);
575 const float value2
= nir_src_as_float(instr
->src
[2].src
);
576 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
579 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
580 assert(value1
== -value2
);
582 fs_reg tmp
= vgrf(glsl_type::int_type
);
584 if (devinfo
->gen
>= 12) {
585 /* Bit 15 of g1.1 is 0 if the polygon is front facing. */
586 fs_reg g1
= fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W
));
588 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
590 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
591 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
593 * and negate the result for (gl_FrontFacing ? -1.0 : 1.0).
595 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
596 g1
, brw_imm_uw(0x3f80));
599 bld
.MOV(tmp
, negate(tmp
));
601 } else if (devinfo
->gen
>= 6) {
602 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
603 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
605 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
607 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
608 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
610 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
612 * This negation looks like it's safe in practice, because bits 0:4 will
613 * surely be TRIANGLES
616 if (value1
== -1.0f
) {
620 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
621 g0
, brw_imm_uw(0x3f80));
623 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
624 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
626 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
628 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
629 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
631 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
633 * This negation looks like it's safe in practice, because bits 0:4 will
634 * surely be TRIANGLES
637 if (value1
== -1.0f
) {
641 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
643 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
649 emit_find_msb_using_lzd(const fs_builder
&bld
,
650 const fs_reg
&result
,
658 /* LZD of an absolute value source almost always does the right
659 * thing. There are two problem values:
661 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
662 * 0. However, findMSB(int(0x80000000)) == 30.
664 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
665 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
667 * For a value of zero or negative one, -1 will be returned.
669 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
670 * findMSB(-(1<<x)) should return x-1.
672 * For all negative number cases, including 0x80000000 and
673 * 0xffffffff, the correct value is obtained from LZD if instead of
674 * negating the (already negative) value the logical-not is used. A
675 * conditonal logical-not can be achieved in two instructions.
677 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
679 bld
.ASR(temp
, src
, brw_imm_d(31));
680 bld
.XOR(temp
, temp
, src
);
683 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
684 retype(temp
, BRW_REGISTER_TYPE_UD
));
686 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
687 * from the LSB side. Subtract the result from 31 to convert the MSB
688 * count into an LSB count. If no bits are set, LZD will return 32.
689 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
691 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
692 inst
->src
[0].negate
= true;
696 brw_rnd_mode_from_nir_op (const nir_op op
) {
698 case nir_op_f2f16_rtz
:
699 return BRW_RND_MODE_RTZ
;
700 case nir_op_f2f16_rtne
:
701 return BRW_RND_MODE_RTNE
;
703 unreachable("Operation doesn't support rounding mode");
708 brw_rnd_mode_from_execution_mode(unsigned execution_mode
)
710 if (nir_has_any_rounding_mode_rtne(execution_mode
))
711 return BRW_RND_MODE_RTNE
;
712 if (nir_has_any_rounding_mode_rtz(execution_mode
))
713 return BRW_RND_MODE_RTZ
;
714 return BRW_RND_MODE_UNSPECIFIED
;
718 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
719 nir_alu_instr
*instr
,
724 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
726 result
.type
= brw_type_for_nir_type(devinfo
,
727 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
728 nir_dest_bit_size(instr
->dest
.dest
)));
730 assert(!instr
->dest
.saturate
);
732 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
733 /* We don't lower to source modifiers so they should not exist. */
734 assert(!instr
->src
[i
].abs
);
735 assert(!instr
->src
[i
].negate
);
737 op
[i
] = get_nir_src(instr
->src
[i
].src
);
738 op
[i
].type
= brw_type_for_nir_type(devinfo
,
739 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
740 nir_src_bit_size(instr
->src
[i
].src
)));
743 /* Move and vecN instrutions may still be vectored. Return the raw,
744 * vectored source and destination so that fs_visitor::nir_emit_alu can
745 * handle it. Other callers should not have to handle these kinds of
758 /* At this point, we have dealt with any instruction that operates on
759 * more than a single channel. Therefore, we can just adjust the source
760 * and destination registers for that channel and emit the instruction.
762 unsigned channel
= 0;
763 if (nir_op_infos
[instr
->op
].output_size
== 0) {
764 /* Since NIR is doing the scalarizing for us, we should only ever see
765 * vectorized operations with a single channel.
767 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
768 channel
= ffs(instr
->dest
.write_mask
) - 1;
770 result
= offset(result
, bld
, channel
);
773 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
774 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
775 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
782 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
785 for (unsigned i
= 0; i
< 2; i
++) {
786 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
788 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
) {
789 /* The source of the inot is now the source of instr. */
790 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
792 assert(!op
[i
].negate
);
795 op
[i
] = resolve_source_modifiers(op
[i
]);
801 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
803 nir_alu_instr
*instr
)
805 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
808 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
810 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
813 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
814 * of valid size-changing combinations is a bit more complex.
816 * The source restriction is just because I was lazy about generating the
819 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
820 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
823 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
824 * this is float(1 + a).
828 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
830 /* Ignore the saturate modifier, if there is one. The result of the
831 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
833 bld
.ADD(result
, op
, brw_imm_d(1));
839 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
841 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
842 * the source of \c instr that is a \c nir_op_fsign.
845 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
846 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
850 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
851 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
853 if (instr
->op
!= nir_op_fsign
) {
854 const nir_alu_instr
*const fsign_instr
=
855 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
857 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
858 * fsign_src] has the other multiply source. This must be rearranged so
859 * that op[0] is the source of the fsign op[1] is the other multiply
865 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
867 const nir_alu_type t
=
868 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
869 nir_src_bit_size(fsign_instr
->src
[0].src
));
871 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
873 unsigned channel
= 0;
874 if (nir_op_infos
[instr
->op
].output_size
== 0) {
875 /* Since NIR is doing the scalarizing for us, we should only ever see
876 * vectorized operations with a single channel.
878 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
879 channel
= ffs(instr
->dest
.write_mask
) - 1;
882 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
885 if (type_sz(op
[0].type
) == 2) {
886 /* AND(val, 0x8000) gives the sign bit.
888 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
890 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
891 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
893 op
[0].type
= BRW_REGISTER_TYPE_UW
;
894 result
.type
= BRW_REGISTER_TYPE_UW
;
895 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
897 if (instr
->op
== nir_op_fsign
)
898 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
900 /* Use XOR here to get the result sign correct. */
901 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
904 inst
->predicate
= BRW_PREDICATE_NORMAL
;
905 } else if (type_sz(op
[0].type
) == 4) {
906 /* AND(val, 0x80000000) gives the sign bit.
908 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
911 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
913 op
[0].type
= BRW_REGISTER_TYPE_UD
;
914 result
.type
= BRW_REGISTER_TYPE_UD
;
915 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
917 if (instr
->op
== nir_op_fsign
)
918 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
920 /* Use XOR here to get the result sign correct. */
921 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
924 inst
->predicate
= BRW_PREDICATE_NORMAL
;
926 /* For doubles we do the same but we need to consider:
928 * - 2-src instructions can't operate with 64-bit immediates
929 * - The sign is encoded in the high 32-bit of each DF
930 * - We need to produce a DF result.
933 fs_reg zero
= vgrf(glsl_type::double_type
);
934 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
935 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
937 bld
.MOV(result
, zero
);
939 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
940 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
941 brw_imm_ud(0x80000000u
));
943 if (instr
->op
== nir_op_fsign
) {
944 set_predicate(BRW_PREDICATE_NORMAL
,
945 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
947 /* This could be done better in some cases. If the scale is an
948 * immediate with the low 32-bits all 0, emitting a separate XOR and
949 * OR would allow an algebraic optimization to remove the OR. There
950 * are currently zero instances of fsign(double(x))*IMM in shader-db
951 * or any test suite, so it is hard to care at this time.
953 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
954 inst
= bld
.XOR(result_int64
, result_int64
,
955 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
961 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
963 * Checks the operands of a \c nir_op_fmul to determine whether or not
964 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
966 * \param instr The multiplication instruction
968 * \param fsign_src The source of \c instr that may or may not be a
972 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
974 assert(instr
->op
== nir_op_fmul
);
976 nir_alu_instr
*const fsign_instr
=
977 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
981 * 1. instr->src[fsign_src] must be a nir_op_fsign.
982 * 2. The nir_op_fsign can only be used by this multiplication.
983 * 3. The source that is the nir_op_fsign does not have source modifiers.
984 * \c emit_fsign only examines the source modifiers of the source of the
987 * The nir_op_fsign must also not have the saturate modifier, but steps
988 * have already been taken (in nir_opt_algebraic) to ensure that.
990 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
991 is_used_once(fsign_instr
);
995 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
998 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
1000 unsigned execution_mode
=
1001 bld
.shader
->nir
->info
.float_controls_execution_mode
;
1004 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1006 switch (instr
->op
) {
1011 fs_reg temp
= result
;
1012 bool need_extra_copy
= false;
1013 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1014 if (!instr
->src
[i
].src
.is_ssa
&&
1015 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1016 need_extra_copy
= true;
1017 temp
= bld
.vgrf(result
.type
, 4);
1022 for (unsigned i
= 0; i
< 4; i
++) {
1023 if (!(instr
->dest
.write_mask
& (1 << i
)))
1026 if (instr
->op
== nir_op_mov
) {
1027 inst
= bld
.MOV(offset(temp
, bld
, i
),
1028 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1030 inst
= bld
.MOV(offset(temp
, bld
, i
),
1031 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1035 /* In this case the source and destination registers were the same,
1036 * so we need to insert an extra set of moves in order to deal with
1039 if (need_extra_copy
) {
1040 for (unsigned i
= 0; i
< 4; i
++) {
1041 if (!(instr
->dest
.write_mask
& (1 << i
)))
1044 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1052 if (optimize_extract_to_float(instr
, result
))
1054 inst
= bld
.MOV(result
, op
[0]);
1057 case nir_op_f2f16_rtne
:
1058 case nir_op_f2f16_rtz
:
1059 case nir_op_f2f16
: {
1060 brw_rnd_mode rnd
= BRW_RND_MODE_UNSPECIFIED
;
1062 if (nir_op_f2f16
== instr
->op
)
1063 rnd
= brw_rnd_mode_from_execution_mode(execution_mode
);
1065 rnd
= brw_rnd_mode_from_nir_op(instr
->op
);
1067 if (BRW_RND_MODE_UNSPECIFIED
!= rnd
)
1068 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(), brw_imm_d(rnd
));
1070 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1071 * on the HW gen, it is a special hw opcode or just a MOV, and
1072 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1074 * But if we want to use that opcode, we need to provide support on
1075 * different optimizations and lowerings. As right now HF support is
1076 * only for gen8+, it will be better to use directly the MOV, and use
1077 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1079 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1080 inst
= bld
.MOV(result
, op
[0]);
1091 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1093 op
[0].type
= BRW_REGISTER_TYPE_D
;
1094 op
[0].negate
= !op
[0].negate
;
1117 if (result
.type
== BRW_REGISTER_TYPE_B
||
1118 result
.type
== BRW_REGISTER_TYPE_UB
||
1119 result
.type
== BRW_REGISTER_TYPE_HF
)
1120 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1122 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1123 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1124 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1125 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1127 inst
= bld
.MOV(result
, op
[0]);
1131 inst
= bld
.MOV(result
, op
[0]);
1132 inst
->saturate
= true;
1137 op
[0].negate
= true;
1138 inst
= bld
.MOV(result
, op
[0]);
1143 op
[0].negate
= false;
1145 inst
= bld
.MOV(result
, op
[0]);
1149 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1151 brw_rnd_mode_from_execution_mode(execution_mode
);
1152 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1156 if (op
[0].type
== BRW_REGISTER_TYPE_HF
)
1157 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1159 inst
= bld
.MOV(result
, op
[0]);
1163 emit_fsign(bld
, instr
, result
, op
, 0);
1167 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1171 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1175 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1179 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1183 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1187 if (fs_key
->high_quality_derivatives
) {
1188 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1190 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1193 case nir_op_fddx_fine
:
1194 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1196 case nir_op_fddx_coarse
:
1197 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1200 if (fs_key
->high_quality_derivatives
) {
1201 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1203 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1206 case nir_op_fddy_fine
:
1207 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1209 case nir_op_fddy_coarse
:
1210 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1214 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1216 brw_rnd_mode_from_execution_mode(execution_mode
);
1217 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1222 inst
= bld
.ADD(result
, op
[0], op
[1]);
1225 case nir_op_iadd_sat
:
1226 case nir_op_uadd_sat
:
1227 inst
= bld
.ADD(result
, op
[0], op
[1]);
1228 inst
->saturate
= true;
1231 case nir_op_isub_sat
:
1232 bld
.emit(SHADER_OPCODE_ISUB_SAT
, result
, op
[0], op
[1]);
1235 case nir_op_usub_sat
:
1236 bld
.emit(SHADER_OPCODE_USUB_SAT
, result
, op
[0], op
[1]);
1241 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1242 inst
= bld
.AVG(result
, op
[0], op
[1]);
1246 case nir_op_uhadd
: {
1247 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1248 fs_reg tmp
= bld
.vgrf(result
.type
);
1250 if (devinfo
->gen
>= 8) {
1251 op
[0] = resolve_source_modifiers(op
[0]);
1252 op
[1] = resolve_source_modifiers(op
[1]);
1255 /* AVG(x, y) - ((x ^ y) & 1) */
1256 bld
.XOR(tmp
, op
[0], op
[1]);
1257 bld
.AND(tmp
, tmp
, retype(brw_imm_ud(1), result
.type
));
1258 bld
.AVG(result
, op
[0], op
[1]);
1259 inst
= bld
.ADD(result
, result
, tmp
);
1260 inst
->src
[1].negate
= true;
1265 for (unsigned i
= 0; i
< 2; i
++) {
1266 if (can_fuse_fmul_fsign(instr
, i
)) {
1267 emit_fsign(bld
, instr
, result
, op
, i
);
1272 /* We emit the rounding mode after the previous fsign optimization since
1273 * it won't result in a MUL, but will try to negate the value by other
1276 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1278 brw_rnd_mode_from_execution_mode(execution_mode
);
1279 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1283 inst
= bld
.MUL(result
, op
[0], op
[1]);
1286 case nir_op_imul_2x32_64
:
1287 case nir_op_umul_2x32_64
:
1288 bld
.MUL(result
, op
[0], op
[1]);
1291 case nir_op_imul_32x16
:
1292 case nir_op_umul_32x16
: {
1293 const bool ud
= instr
->op
== nir_op_umul_32x16
;
1295 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1297 /* Before Gen7, the order of the 32-bit source and the 16-bit source was
1298 * swapped. The extension isn't enabled on those platforms, so don't
1299 * pretend to support the differences.
1301 assert(devinfo
->gen
>= 7);
1303 if (op
[1].file
== IMM
)
1304 op
[1] = ud
? brw_imm_uw(op
[1].ud
) : brw_imm_w(op
[1].d
);
1306 const enum brw_reg_type word_type
=
1307 ud
? BRW_REGISTER_TYPE_UW
: BRW_REGISTER_TYPE_W
;
1309 op
[1] = subscript(op
[1], word_type
, 0);
1312 const enum brw_reg_type dword_type
=
1313 ud
? BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_D
;
1315 bld
.MUL(result
, retype(op
[0], dword_type
), op
[1]);
1320 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1321 bld
.MUL(result
, op
[0], op
[1]);
1324 case nir_op_imul_high
:
1325 case nir_op_umul_high
:
1326 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1327 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1332 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1333 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1336 case nir_op_uadd_carry
:
1337 unreachable("Should have been lowered by carry_to_arith().");
1339 case nir_op_usub_borrow
:
1340 unreachable("Should have been lowered by borrow_to_arith().");
1344 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1345 * appears that our hardware just does the right thing for signed
1348 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1349 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1353 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1354 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1356 /* Math instructions don't support conditional mod */
1357 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1358 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1360 /* Now, we need to determine if signs of the sources are different.
1361 * When we XOR the sources, the top bit is 0 if they are the same and 1
1362 * if they are different. We can then use a conditional modifier to
1363 * turn that into a predicate. This leads us to an XOR.l instruction.
1365 * Technically, according to the PRM, you're not allowed to use .l on a
1366 * XOR instruction. However, emperical experiments and Curro's reading
1367 * of the simulator source both indicate that it's safe.
1369 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1370 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1371 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1372 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1374 /* If the result of the initial remainder operation is non-zero and the
1375 * two sources have different signs, add in a copy of op[1] to get the
1376 * final integer modulus value.
1378 inst
= bld
.ADD(result
, result
, op
[1]);
1379 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1386 case nir_op_fne32
: {
1387 fs_reg dest
= result
;
1389 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1391 dest
= bld
.vgrf(op
[0].type
, 1);
1393 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1395 if (bit_size
> 32) {
1396 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1397 } else if(bit_size
< 32) {
1398 /* When we convert the result to 32-bit we need to be careful and do
1399 * it as a signed conversion to get sign extension (for 32-bit true)
1401 const brw_reg_type src_type
=
1402 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1404 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1414 case nir_op_ine32
: {
1415 fs_reg dest
= result
;
1417 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1418 * type. So we convert both operands for the comparison.
1421 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1422 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1424 const uint32_t bit_size
= type_sz(temp_op
[0].type
) * 8;
1426 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1428 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1429 brw_cmod_for_nir_comparison(instr
->op
));
1431 if (bit_size
> 32) {
1432 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1433 } else if (bit_size
< 32) {
1434 /* When we convert the result to 32-bit we need to be careful and do
1435 * it as a signed conversion to get sign extension (for 32-bit true)
1437 const brw_reg_type src_type
=
1438 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1440 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1446 if (devinfo
->gen
>= 8) {
1447 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1449 if (inot_src_instr
!= NULL
&&
1450 (inot_src_instr
->op
== nir_op_ior
||
1451 inot_src_instr
->op
== nir_op_ixor
||
1452 inot_src_instr
->op
== nir_op_iand
)) {
1453 /* The sources of the source logical instruction are now the
1454 * sources of the instruction that will be generated.
1456 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1457 resolve_inot_sources(bld
, inot_src_instr
, op
);
1459 /* Smash all of the sources and destination to be signed. This
1460 * doesn't matter for the operation of the instruction, but cmod
1461 * propagation fails on unsigned sources with negation (due to
1462 * fs_inst::can_do_cmod returning false).
1465 brw_type_for_nir_type(devinfo
,
1466 (nir_alu_type
)(nir_type_int
|
1467 nir_dest_bit_size(instr
->dest
.dest
)));
1469 brw_type_for_nir_type(devinfo
,
1470 (nir_alu_type
)(nir_type_int
|
1471 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1473 brw_type_for_nir_type(devinfo
,
1474 (nir_alu_type
)(nir_type_int
|
1475 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1477 /* For XOR, only invert one of the sources. Arbitrarily choose
1480 op
[0].negate
= !op
[0].negate
;
1481 if (inot_src_instr
->op
!= nir_op_ixor
)
1482 op
[1].negate
= !op
[1].negate
;
1484 switch (inot_src_instr
->op
) {
1486 bld
.AND(result
, op
[0], op
[1]);
1490 bld
.OR(result
, op
[0], op
[1]);
1494 bld
.XOR(result
, op
[0], op
[1]);
1498 unreachable("impossible opcode");
1501 op
[0] = resolve_source_modifiers(op
[0]);
1503 bld
.NOT(result
, op
[0]);
1506 if (devinfo
->gen
>= 8) {
1507 resolve_inot_sources(bld
, instr
, op
);
1509 bld
.XOR(result
, op
[0], op
[1]);
1512 if (devinfo
->gen
>= 8) {
1513 resolve_inot_sources(bld
, instr
, op
);
1515 bld
.OR(result
, op
[0], op
[1]);
1518 if (devinfo
->gen
>= 8) {
1519 resolve_inot_sources(bld
, instr
, op
);
1521 bld
.AND(result
, op
[0], op
[1]);
1527 case nir_op_b32all_fequal2
:
1528 case nir_op_b32all_iequal2
:
1529 case nir_op_b32all_fequal3
:
1530 case nir_op_b32all_iequal3
:
1531 case nir_op_b32all_fequal4
:
1532 case nir_op_b32all_iequal4
:
1533 case nir_op_b32any_fnequal2
:
1534 case nir_op_b32any_inequal2
:
1535 case nir_op_b32any_fnequal3
:
1536 case nir_op_b32any_inequal3
:
1537 case nir_op_b32any_fnequal4
:
1538 case nir_op_b32any_inequal4
:
1539 unreachable("Lowered by nir_lower_alu_reductions");
1542 unreachable("not reached: should be handled by ldexp_to_arith()");
1545 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1549 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1553 case nir_op_f2b32
: {
1554 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1555 if (bit_size
== 64) {
1556 /* two-argument instructions can't take 64-bit immediates */
1560 if (instr
->op
== nir_op_f2b32
) {
1561 zero
= vgrf(glsl_type::double_type
);
1562 tmp
= vgrf(glsl_type::double_type
);
1563 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1565 zero
= vgrf(glsl_type::int64_t_type
);
1566 tmp
= vgrf(glsl_type::int64_t_type
);
1567 bld
.MOV(zero
, brw_imm_q(0));
1570 /* A SIMD16 execution needs to be split in two instructions, so use
1571 * a vgrf instead of the flag register as dst so instruction splitting
1574 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1575 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1578 if (bit_size
== 32) {
1579 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1581 assert(bit_size
== 16);
1582 zero
= instr
->op
== nir_op_f2b32
?
1583 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1585 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1591 inst
= bld
.RNDZ(result
, op
[0]);
1592 if (devinfo
->gen
< 6) {
1593 set_condmod(BRW_CONDITIONAL_R
, inst
);
1594 set_predicate(BRW_PREDICATE_NORMAL
,
1595 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1596 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1600 case nir_op_fceil
: {
1601 op
[0].negate
= !op
[0].negate
;
1602 fs_reg temp
= vgrf(glsl_type::float_type
);
1603 bld
.RNDD(temp
, op
[0]);
1605 inst
= bld
.MOV(result
, temp
);
1609 inst
= bld
.RNDD(result
, op
[0]);
1612 inst
= bld
.FRC(result
, op
[0]);
1614 case nir_op_fround_even
:
1615 inst
= bld
.RNDE(result
, op
[0]);
1616 if (devinfo
->gen
< 6) {
1617 set_condmod(BRW_CONDITIONAL_R
, inst
);
1618 set_predicate(BRW_PREDICATE_NORMAL
,
1619 bld
.ADD(result
, result
, brw_imm_f(1.0f
)));
1620 inst
= bld
.MOV(result
, result
); /* for potential saturation */
1624 case nir_op_fquantize2f16
: {
1625 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1626 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1627 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1629 /* The destination stride must be at least as big as the source stride. */
1630 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1633 /* Check for denormal */
1634 fs_reg abs_src0
= op
[0];
1635 abs_src0
.abs
= true;
1636 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1638 /* Get the appropriately signed zero */
1639 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1640 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1641 brw_imm_ud(0x80000000));
1642 /* Do the actual F32 -> F16 -> F32 conversion */
1643 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1644 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1645 /* Select that or zero based on normal status */
1646 inst
= bld
.SEL(result
, zero
, tmp32
);
1647 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1654 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1660 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1663 case nir_op_pack_snorm_2x16
:
1664 case nir_op_pack_snorm_4x8
:
1665 case nir_op_pack_unorm_2x16
:
1666 case nir_op_pack_unorm_4x8
:
1667 case nir_op_unpack_snorm_2x16
:
1668 case nir_op_unpack_snorm_4x8
:
1669 case nir_op_unpack_unorm_2x16
:
1670 case nir_op_unpack_unorm_4x8
:
1671 case nir_op_unpack_half_2x16
:
1672 case nir_op_pack_half_2x16
:
1673 unreachable("not reached: should be handled by lower_packing_builtins");
1675 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1676 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1678 case nir_op_unpack_half_2x16_split_x
:
1679 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1680 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1683 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1684 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1686 case nir_op_unpack_half_2x16_split_y
:
1687 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1688 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1691 case nir_op_pack_64_2x32_split
:
1692 case nir_op_pack_32_2x16_split
:
1693 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1696 case nir_op_unpack_64_2x32_split_x
:
1697 case nir_op_unpack_64_2x32_split_y
: {
1698 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1699 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1701 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1705 case nir_op_unpack_32_2x16_split_x
:
1706 case nir_op_unpack_32_2x16_split_y
: {
1707 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1708 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1710 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1715 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1718 case nir_op_bitfield_reverse
:
1719 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1720 bld
.BFREV(result
, op
[0]);
1723 case nir_op_bit_count
:
1724 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1725 bld
.CBIT(result
, op
[0]);
1728 case nir_op_ufind_msb
: {
1729 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1730 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1735 assert(nir_dest_bit_size(instr
->dest
.dest
) == 32);
1736 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1739 case nir_op_ifind_msb
: {
1740 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1742 if (devinfo
->gen
< 7) {
1743 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1745 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1747 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1748 * count from the LSB side. If FBH didn't return an error
1749 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1750 * count into an LSB count.
1752 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1754 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1755 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1756 inst
->src
[0].negate
= true;
1761 case nir_op_find_lsb
:
1762 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1764 if (devinfo
->gen
< 7) {
1765 fs_reg temp
= vgrf(glsl_type::int_type
);
1767 /* (x & -x) generates a value that consists of only the LSB of x.
1768 * For all powers of 2, findMSB(y) == findLSB(y).
1770 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1771 fs_reg negated_src
= src
;
1773 /* One must be negated, and the other must be non-negated. It
1774 * doesn't matter which is which.
1776 negated_src
.negate
= true;
1779 bld
.AND(temp
, src
, negated_src
);
1780 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1782 bld
.FBL(result
, op
[0]);
1786 case nir_op_ubitfield_extract
:
1787 case nir_op_ibitfield_extract
:
1788 unreachable("should have been lowered");
1791 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1792 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1795 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1796 bld
.BFI1(result
, op
[0], op
[1]);
1799 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1800 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1803 case nir_op_bitfield_insert
:
1804 unreachable("not reached: should have been lowered");
1807 bld
.SHL(result
, op
[0], op
[1]);
1810 bld
.ASR(result
, op
[0], op
[1]);
1813 bld
.SHR(result
, op
[0], op
[1]);
1817 bld
.ROL(result
, op
[0], op
[1]);
1820 bld
.ROR(result
, op
[0], op
[1]);
1823 case nir_op_pack_half_2x16_split
:
1824 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1828 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1830 brw_rnd_mode_from_execution_mode(execution_mode
);
1831 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1835 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1839 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1841 brw_rnd_mode_from_execution_mode(execution_mode
);
1842 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1846 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1849 case nir_op_b32csel
:
1850 if (optimize_frontfacing_ternary(instr
, result
))
1853 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1854 inst
= bld
.SEL(result
, op
[1], op
[2]);
1855 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1858 case nir_op_extract_u8
:
1859 case nir_op_extract_i8
: {
1860 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1865 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1866 * Use two instructions and a word or DWord intermediate integer type.
1868 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1869 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1871 if (instr
->op
== nir_op_extract_i8
) {
1872 /* If we need to sign extend, extract to a word first */
1873 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1874 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1875 bld
.MOV(result
, w_temp
);
1876 } else if (byte
& 1) {
1877 /* Extract the high byte from the word containing the desired byte
1881 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1884 /* Otherwise use an AND with 0xff and a word type */
1886 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1890 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1891 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1896 case nir_op_extract_u16
:
1897 case nir_op_extract_i16
: {
1898 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1899 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1900 bld
.MOV(result
, subscript(op
[0], type
, word
));
1905 unreachable("unhandled instruction");
1908 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1909 * to sign extend the low bit to 0/~0
1911 if (devinfo
->gen
<= 5 &&
1912 !result
.is_null() &&
1913 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1914 fs_reg masked
= vgrf(glsl_type::int_type
);
1915 bld
.AND(masked
, result
, brw_imm_d(1));
1916 masked
.negate
= true;
1917 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1922 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1923 nir_load_const_instr
*instr
)
1925 const brw_reg_type reg_type
=
1926 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1927 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1929 switch (instr
->def
.bit_size
) {
1931 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1932 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1936 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1937 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1941 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1942 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1946 assert(devinfo
->gen
>= 7);
1947 if (devinfo
->gen
== 7) {
1948 /* We don't get 64-bit integer types until gen8 */
1949 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1950 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1951 setup_imm_df(bld
, instr
->value
[i
].f64
));
1954 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1955 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1960 unreachable("Invalid bit size");
1963 nir_ssa_values
[instr
->def
.index
] = reg
;
1967 fs_visitor::get_nir_src(const nir_src
&src
)
1971 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1972 const brw_reg_type reg_type
=
1973 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1974 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1976 reg
= nir_ssa_values
[src
.ssa
->index
];
1979 /* We don't handle indirects on locals */
1980 assert(src
.reg
.indirect
== NULL
);
1981 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1982 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1985 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1986 /* The only 64-bit type available on gen7 is DF, so use that. */
1987 reg
.type
= BRW_REGISTER_TYPE_DF
;
1989 /* To avoid floating-point denorm flushing problems, set the type by
1990 * default to an integer type - instructions that need floating point
1991 * semantics will set this to F if they need to
1993 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1994 BRW_REGISTER_TYPE_D
);
2001 * Return an IMM for constants; otherwise call get_nir_src() as normal.
2003 * This function should not be called on any value which may be 64 bits.
2004 * We could theoretically support 64-bit on gen8+ but we choose not to
2005 * because it wouldn't work in general (no gen7 support) and there are
2006 * enough restrictions in 64-bit immediates that you can't take the return
2007 * value and treat it the same as the result of get_nir_src().
2010 fs_visitor::get_nir_src_imm(const nir_src
&src
)
2012 assert(nir_src_bit_size(src
) == 32);
2013 return nir_src_is_const(src
) ?
2014 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
2018 fs_visitor::get_nir_dest(const nir_dest
&dest
)
2021 const brw_reg_type reg_type
=
2022 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
2023 dest
.ssa
.bit_size
== 8 ?
2024 BRW_REGISTER_TYPE_D
:
2025 BRW_REGISTER_TYPE_F
);
2026 nir_ssa_values
[dest
.ssa
.index
] =
2027 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
2028 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
2029 return nir_ssa_values
[dest
.ssa
.index
];
2031 /* We don't handle indirects on locals */
2032 assert(dest
.reg
.indirect
== NULL
);
2033 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
2034 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
2039 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
2042 for (unsigned i
= 0; i
< 4; i
++) {
2043 if (!((wr_mask
>> i
) & 1))
2046 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
2047 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
2048 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
2049 if (new_inst
->src
[j
].file
== VGRF
)
2050 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2057 emit_pixel_interpolater_send(const fs_builder
&bld
,
2062 glsl_interp_mode interpolation
)
2064 struct brw_wm_prog_data
*wm_prog_data
=
2065 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2067 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2068 /* 2 floats per slot returned */
2069 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2070 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2072 wm_prog_data
->pulls_bary
= true;
2078 * Computes 1 << x, given a D/UD register containing some value x.
2081 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2083 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2085 fs_reg result
= bld
.vgrf(x
.type
, 1);
2086 fs_reg one
= bld
.vgrf(x
.type
, 1);
2088 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2089 bld
.SHL(result
, one
, x
);
2094 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2096 assert(stage
== MESA_SHADER_GEOMETRY
);
2098 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2100 if (gs_compile
->control_data_header_size_bits
== 0)
2103 /* We can only do EndPrimitive() functionality when the control data
2104 * consists of cut bits. Fortunately, the only time it isn't is when the
2105 * output type is points, in which case EndPrimitive() is a no-op.
2107 if (gs_prog_data
->control_data_format
!=
2108 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2112 /* Cut bits use one bit per vertex. */
2113 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2115 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2116 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2118 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2119 * vertex n, 0 otherwise. So all we need to do here is mark bit
2120 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2121 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2122 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2124 * Note that if EndPrimitive() is called before emitting any vertices, this
2125 * will cause us to set bit 31 of the control_data_bits register to 1.
2126 * That's fine because:
2128 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2129 * output, so the hardware will ignore cut bit 31.
2131 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2132 * last vertex, so setting cut bit 31 has no effect (since the primitive
2133 * is automatically ended when the GS terminates).
2135 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2136 * control_data_bits register to 0 when the first vertex is emitted.
2139 const fs_builder abld
= bld
.annotate("end primitive");
2141 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2142 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2143 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2144 fs_reg mask
= intexp2(abld
, prev_count
);
2145 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2146 * attention to the lower 5 bits of its second source argument, so on this
2147 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2148 * ((vertex_count - 1) % 32).
2150 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2154 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2156 assert(stage
== MESA_SHADER_GEOMETRY
);
2157 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2159 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2161 const fs_builder abld
= bld
.annotate("emit control data bits");
2162 const fs_builder fwa_bld
= bld
.exec_all();
2164 /* We use a single UD register to accumulate control data bits (32 bits
2165 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2168 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2169 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2170 * use the Channel Mask phase to enable/disable which DWord within that
2171 * group to write. (Remember, different SIMD8 channels may have emitted
2172 * different numbers of vertices, so we may need per-slot offsets.)
2174 * Channel masking presents an annoying problem: we may have to replicate
2175 * the data up to 4 times:
2177 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2179 * To avoid penalizing shaders that emit a small number of vertices, we
2180 * can avoid these sometimes: if the size of the control data header is
2181 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2182 * land in the same 128-bit group, so we can skip per-slot offsets.
2184 * Similarly, if the control data header is <= 32 bits, there is only one
2185 * DWord, so we can skip channel masks.
2187 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2189 fs_reg channel_mask
, per_slot_offset
;
2191 if (gs_compile
->control_data_header_size_bits
> 32) {
2192 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2193 channel_mask
= vgrf(glsl_type::uint_type
);
2196 if (gs_compile
->control_data_header_size_bits
> 128) {
2197 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2198 per_slot_offset
= vgrf(glsl_type::uint_type
);
2201 /* Figure out which DWord we're trying to write to using the formula:
2203 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2205 * Since bits_per_vertex is a power of two, and is known at compile
2206 * time, this can be optimized to:
2208 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2210 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2211 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2212 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2213 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2214 unsigned log2_bits_per_vertex
=
2215 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2216 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2218 if (per_slot_offset
.file
!= BAD_FILE
) {
2219 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2220 * the appropriate OWord within the control data header.
2222 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2225 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2226 * write to the appropriate DWORD within the OWORD.
2228 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2229 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2230 channel_mask
= intexp2(fwa_bld
, channel
);
2231 /* Then the channel masks need to be in bits 23:16. */
2232 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2235 /* Store the control data bits in the message payload and send it. */
2237 if (channel_mask
.file
!= BAD_FILE
)
2238 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2239 if (per_slot_offset
.file
!= BAD_FILE
)
2242 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2243 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2245 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2246 if (per_slot_offset
.file
!= BAD_FILE
)
2247 sources
[i
++] = per_slot_offset
;
2248 if (channel_mask
.file
!= BAD_FILE
)
2249 sources
[i
++] = channel_mask
;
2251 sources
[i
++] = this->control_data_bits
;
2254 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2255 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2257 /* We need to increment Global Offset by 256-bits to make room for
2258 * Broadwell's extra "Vertex Count" payload at the beginning of the
2259 * URB entry. Since this is an OWord message, Global Offset is counted
2260 * in 128-bit units, so we must set it to 2.
2262 if (gs_prog_data
->static_vertex_count
== -1)
2267 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2270 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2272 /* Note: we are calling this *before* increasing vertex_count, so
2273 * this->vertex_count == vertex_count - 1 in the formula above.
2276 /* Stream mode uses 2 bits per vertex */
2277 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2279 /* Must be a valid stream */
2280 assert(stream_id
< MAX_VERTEX_STREAMS
);
2282 /* Control data bits are initialized to 0 so we don't have to set any
2283 * bits when sending vertices to stream 0.
2288 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2290 /* reg::sid = stream_id */
2291 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2292 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2294 /* reg:shift_count = 2 * (vertex_count - 1) */
2295 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2296 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2298 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2299 * attention to the lower 5 bits of its second source argument, so on this
2300 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2301 * stream_id << ((2 * (vertex_count - 1)) % 32).
2303 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2304 abld
.SHL(mask
, sid
, shift_count
);
2305 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2309 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2312 assert(stage
== MESA_SHADER_GEOMETRY
);
2314 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2316 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2317 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2319 /* Haswell and later hardware ignores the "Render Stream Select" bits
2320 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2321 * and instead sends all primitives down the pipeline for rasterization.
2322 * If the SOL stage is enabled, "Render Stream Select" is honored and
2323 * primitives bound to non-zero streams are discarded after stream output.
2325 * Since the only purpose of primives sent to non-zero streams is to
2326 * be recorded by transform feedback, we can simply discard all geometry
2327 * bound to these streams when transform feedback is disabled.
2329 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2332 /* If we're outputting 32 control data bits or less, then we can wait
2333 * until the shader is over to output them all. Otherwise we need to
2334 * output them as we go. Now is the time to do it, since we're about to
2335 * output the vertex_count'th vertex, so it's guaranteed that the
2336 * control data bits associated with the (vertex_count - 1)th vertex are
2339 if (gs_compile
->control_data_header_size_bits
> 32) {
2340 const fs_builder abld
=
2341 bld
.annotate("emit vertex: emit control data bits");
2343 /* Only emit control data bits if we've finished accumulating a batch
2344 * of 32 bits. This is the case when:
2346 * (vertex_count * bits_per_vertex) % 32 == 0
2348 * (in other words, when the last 5 bits of vertex_count *
2349 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2350 * integer n (which is always the case, since bits_per_vertex is
2351 * always 1 or 2), this is equivalent to requiring that the last 5-n
2352 * bits of vertex_count are 0:
2354 * vertex_count & (2^(5-n) - 1) == 0
2356 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2359 * vertex_count & (32 / bits_per_vertex - 1) == 0
2361 * TODO: If vertex_count is an immediate, we could do some of this math
2362 * at compile time...
2365 abld
.AND(bld
.null_reg_d(), vertex_count
,
2366 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2367 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2369 abld
.IF(BRW_PREDICATE_NORMAL
);
2370 /* If vertex_count is 0, then no control data bits have been
2371 * accumulated yet, so we can skip emitting them.
2373 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2374 BRW_CONDITIONAL_NEQ
);
2375 abld
.IF(BRW_PREDICATE_NORMAL
);
2376 emit_gs_control_data_bits(vertex_count
);
2377 abld
.emit(BRW_OPCODE_ENDIF
);
2379 /* Reset control_data_bits to 0 so we can start accumulating a new
2382 * Note: in the case where vertex_count == 0, this neutralizes the
2383 * effect of any call to EndPrimitive() that the shader may have
2384 * made before outputting its first vertex.
2386 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2387 inst
->force_writemask_all
= true;
2388 abld
.emit(BRW_OPCODE_ENDIF
);
2391 emit_urb_writes(vertex_count
);
2393 /* In stream mode we have to set control data bits for all vertices
2394 * unless we have disabled control data bits completely (which we do
2395 * do for GL_POINTS outputs that don't use streams).
2397 if (gs_compile
->control_data_header_size_bits
> 0 &&
2398 gs_prog_data
->control_data_format
==
2399 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2400 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2405 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2406 const nir_src
&vertex_src
,
2407 unsigned base_offset
,
2408 const nir_src
&offset_src
,
2409 unsigned num_components
,
2410 unsigned first_component
)
2412 assert(type_sz(dst
.type
) == 4);
2413 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2414 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2416 /* TODO: figure out push input layout for invocations == 1 */
2417 if (gs_prog_data
->invocations
== 1 &&
2418 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2419 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2420 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2421 nir_src_as_uint(vertex_src
) * push_reg_count
;
2422 for (unsigned i
= 0; i
< num_components
; i
++) {
2423 bld
.MOV(offset(dst
, bld
, i
),
2424 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2429 /* Resort to the pull model. Ensure the VUE handles are provided. */
2430 assert(gs_prog_data
->base
.include_vue_handles
);
2432 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2433 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2435 if (gs_prog_data
->invocations
== 1) {
2436 if (nir_src_is_const(vertex_src
)) {
2437 /* The vertex index is constant; just select the proper URB handle. */
2439 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2440 BRW_REGISTER_TYPE_UD
);
2442 /* The vertex index is non-constant. We need to use indirect
2443 * addressing to fetch the proper URB handle.
2445 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2446 * indicating that channel <n> should read the handle from
2447 * DWord <n>. We convert that to bytes by multiplying by 4.
2449 * Next, we convert the vertex index to bytes by multiplying
2450 * by 32 (shifting by 5), and add the two together. This is
2451 * the final indirect byte offset.
2453 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2454 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2455 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2456 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2458 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2459 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2460 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2461 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2462 /* Convert vertex_index to bytes (multiply by 32) */
2463 bld
.SHL(vertex_offset_bytes
,
2464 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2466 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2468 /* Use first_icp_handle as the base offset. There is one register
2469 * of URB handles per vertex, so inform the register allocator that
2470 * we might read up to nir->info.gs.vertices_in registers.
2472 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2473 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2474 fs_reg(icp_offset_bytes
),
2475 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2478 assert(gs_prog_data
->invocations
> 1);
2480 if (nir_src_is_const(vertex_src
)) {
2481 unsigned vertex
= nir_src_as_uint(vertex_src
);
2482 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2484 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2485 BRW_REGISTER_TYPE_UD
));
2487 /* The vertex index is non-constant. We need to use indirect
2488 * addressing to fetch the proper URB handle.
2491 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2493 /* Convert vertex_index to bytes (multiply by 4) */
2494 bld
.SHL(icp_offset_bytes
,
2495 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2498 /* Use first_icp_handle as the base offset. There is one DWord
2499 * of URB handles per vertex, so inform the register allocator that
2500 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2502 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2503 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2504 fs_reg(icp_offset_bytes
),
2505 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2511 fs_reg indirect_offset
= get_nir_src(offset_src
);
2513 if (nir_src_is_const(offset_src
)) {
2514 /* Constant indexing - use global offset. */
2515 if (first_component
!= 0) {
2516 unsigned read_components
= num_components
+ first_component
;
2517 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2518 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2519 inst
->size_written
= read_components
*
2520 tmp
.component_size(inst
->exec_size
);
2521 for (unsigned i
= 0; i
< num_components
; i
++) {
2522 bld
.MOV(offset(dst
, bld
, i
),
2523 offset(tmp
, bld
, i
+ first_component
));
2526 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2527 inst
->size_written
= num_components
*
2528 dst
.component_size(inst
->exec_size
);
2530 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2533 /* Indirect indexing - use per-slot offsets as well. */
2534 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2535 unsigned read_components
= num_components
+ first_component
;
2536 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2537 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2538 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2539 if (first_component
!= 0) {
2540 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2542 inst
->size_written
= read_components
*
2543 tmp
.component_size(inst
->exec_size
);
2544 for (unsigned i
= 0; i
< num_components
; i
++) {
2545 bld
.MOV(offset(dst
, bld
, i
),
2546 offset(tmp
, bld
, i
+ first_component
));
2549 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2550 inst
->size_written
= num_components
*
2551 dst
.component_size(inst
->exec_size
);
2553 inst
->offset
= base_offset
;
2559 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2561 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2563 if (nir_src_is_const(*offset_src
)) {
2564 /* The only constant offset we should find is 0. brw_nir.c's
2565 * add_const_offset_to_base() will fold other constant offsets
2566 * into instr->const_index[0].
2568 assert(nir_src_as_uint(*offset_src
) == 0);
2572 return get_nir_src(*offset_src
);
2576 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2577 nir_intrinsic_instr
*instr
)
2579 assert(stage
== MESA_SHADER_VERTEX
);
2582 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2583 dest
= get_nir_dest(instr
->dest
);
2585 switch (instr
->intrinsic
) {
2586 case nir_intrinsic_load_vertex_id
:
2587 case nir_intrinsic_load_base_vertex
:
2588 unreachable("should be lowered by nir_lower_system_values()");
2590 case nir_intrinsic_load_input
: {
2591 assert(nir_dest_bit_size(instr
->dest
) == 32);
2592 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2593 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2594 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2596 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2597 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2601 case nir_intrinsic_load_vertex_id_zero_base
:
2602 case nir_intrinsic_load_instance_id
:
2603 case nir_intrinsic_load_base_instance
:
2604 case nir_intrinsic_load_draw_id
:
2605 case nir_intrinsic_load_first_vertex
:
2606 case nir_intrinsic_load_is_indexed_draw
:
2607 unreachable("lowered by brw_nir_lower_vs_inputs");
2610 nir_emit_intrinsic(bld
, instr
);
2616 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2617 nir_intrinsic_instr
*instr
)
2619 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2620 const nir_src
&vertex_src
= instr
->src
[0];
2621 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2624 if (nir_src_is_const(vertex_src
)) {
2625 /* Emit a MOV to resolve <0,1,0> regioning. */
2626 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2627 unsigned vertex
= nir_src_as_uint(vertex_src
);
2629 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2630 BRW_REGISTER_TYPE_UD
));
2631 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2632 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2633 /* For the common case of only 1 instance, an array index of
2634 * gl_InvocationID means reading g1. Skip all the indirect work.
2636 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2638 /* The vertex index is non-constant. We need to use indirect
2639 * addressing to fetch the proper URB handle.
2641 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2643 /* Each ICP handle is a single DWord (4 bytes) */
2644 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2645 bld
.SHL(vertex_offset_bytes
,
2646 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2649 /* Start at g1. We might read up to 4 registers. */
2650 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2651 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2652 brw_imm_ud(4 * REG_SIZE
));
2659 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2660 nir_intrinsic_instr
*instr
)
2662 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2663 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2664 const nir_src
&vertex_src
= instr
->src
[0];
2666 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2668 if (nir_src_is_const(vertex_src
)) {
2669 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2670 nir_src_as_uint(vertex_src
), 0),
2671 BRW_REGISTER_TYPE_UD
));
2674 /* The vertex index is non-constant. We need to use indirect
2675 * addressing to fetch the proper URB handle.
2677 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2678 * indicating that channel <n> should read the handle from
2679 * DWord <n>. We convert that to bytes by multiplying by 4.
2681 * Next, we convert the vertex index to bytes by multiplying
2682 * by 32 (shifting by 5), and add the two together. This is
2683 * the final indirect byte offset.
2685 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2686 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2687 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2688 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2689 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2691 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2692 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2693 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2694 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2695 /* Convert vertex_index to bytes (multiply by 32) */
2696 bld
.SHL(vertex_offset_bytes
,
2697 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2699 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2701 /* Use first_icp_handle as the base offset. There is one register
2702 * of URB handles per vertex, so inform the register allocator that
2703 * we might read up to nir->info.gs.vertices_in registers.
2705 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2706 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2707 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2713 fs_visitor::get_tcs_output_urb_handle()
2715 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2717 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2718 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2720 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2721 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2726 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2727 nir_intrinsic_instr
*instr
)
2729 assert(stage
== MESA_SHADER_TESS_CTRL
);
2730 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2731 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2732 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2735 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2738 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2739 dst
= get_nir_dest(instr
->dest
);
2741 switch (instr
->intrinsic
) {
2742 case nir_intrinsic_load_primitive_id
:
2743 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2744 : brw_vec1_grf(0, 1)));
2746 case nir_intrinsic_load_invocation_id
:
2747 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2749 case nir_intrinsic_load_patch_vertices_in
:
2750 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2751 brw_imm_d(tcs_key
->input_vertices
));
2754 case nir_intrinsic_control_barrier
: {
2755 if (tcs_prog_data
->instances
== 1)
2758 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2759 fs_reg m0_2
= component(m0
, 2);
2761 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2763 /* Zero the message header */
2764 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2766 if (devinfo
->gen
< 11) {
2767 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2768 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2769 brw_imm_ud(INTEL_MASK(16, 13)));
2771 /* Shift it up to bits 27:24. */
2772 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2774 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2775 brw_imm_ud(INTEL_MASK(30, 24)));
2778 /* Set the Barrier Count and the enable bit */
2779 if (devinfo
->gen
< 11) {
2780 chanbld
.OR(m0_2
, m0_2
,
2781 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2783 chanbld
.OR(m0_2
, m0_2
,
2784 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2787 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2791 case nir_intrinsic_load_input
:
2792 unreachable("nir_lower_io should never give us these.");
2795 case nir_intrinsic_load_per_vertex_input
: {
2796 assert(nir_dest_bit_size(instr
->dest
) == 32);
2797 fs_reg indirect_offset
= get_indirect_offset(instr
);
2798 unsigned imm_offset
= instr
->const_index
[0];
2802 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2803 : get_tcs_single_patch_icp_handle(bld
, instr
);
2805 /* We can only read two double components with each URB read, so
2806 * we send two read messages in that case, each one loading up to
2807 * two double components.
2809 unsigned num_components
= instr
->num_components
;
2810 unsigned first_component
= nir_intrinsic_component(instr
);
2812 if (indirect_offset
.file
== BAD_FILE
) {
2813 /* Constant indexing - use global offset. */
2814 if (first_component
!= 0) {
2815 unsigned read_components
= num_components
+ first_component
;
2816 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2817 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2818 for (unsigned i
= 0; i
< num_components
; i
++) {
2819 bld
.MOV(offset(dst
, bld
, i
),
2820 offset(tmp
, bld
, i
+ first_component
));
2823 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2825 inst
->offset
= imm_offset
;
2828 /* Indirect indexing - use per-slot offsets as well. */
2829 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2830 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2831 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2832 if (first_component
!= 0) {
2833 unsigned read_components
= num_components
+ first_component
;
2834 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2835 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2837 for (unsigned i
= 0; i
< num_components
; i
++) {
2838 bld
.MOV(offset(dst
, bld
, i
),
2839 offset(tmp
, bld
, i
+ first_component
));
2842 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2845 inst
->offset
= imm_offset
;
2848 inst
->size_written
= (num_components
+ first_component
) *
2849 inst
->dst
.component_size(inst
->exec_size
);
2851 /* Copy the temporary to the destination to deal with writemasking.
2853 * Also attempt to deal with gl_PointSize being in the .w component.
2855 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2856 assert(type_sz(dst
.type
) == 4);
2857 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2858 inst
->size_written
= 4 * REG_SIZE
;
2859 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2864 case nir_intrinsic_load_output
:
2865 case nir_intrinsic_load_per_vertex_output
: {
2866 assert(nir_dest_bit_size(instr
->dest
) == 32);
2867 fs_reg indirect_offset
= get_indirect_offset(instr
);
2868 unsigned imm_offset
= instr
->const_index
[0];
2869 unsigned first_component
= nir_intrinsic_component(instr
);
2871 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2874 if (indirect_offset
.file
== BAD_FILE
) {
2875 /* This MOV replicates the output handle to all enabled channels
2876 * is SINGLE_PATCH mode.
2878 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2879 bld
.MOV(patch_handle
, output_handles
);
2882 if (first_component
!= 0) {
2883 unsigned read_components
=
2884 instr
->num_components
+ first_component
;
2885 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2886 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2888 inst
->size_written
= read_components
* REG_SIZE
;
2889 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2890 bld
.MOV(offset(dst
, bld
, i
),
2891 offset(tmp
, bld
, i
+ first_component
));
2894 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2896 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2898 inst
->offset
= imm_offset
;
2902 /* Indirect indexing - use per-slot offsets as well. */
2903 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2904 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2905 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2906 if (first_component
!= 0) {
2907 unsigned read_components
=
2908 instr
->num_components
+ first_component
;
2909 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2910 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2912 inst
->size_written
= read_components
* REG_SIZE
;
2913 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2914 bld
.MOV(offset(dst
, bld
, i
),
2915 offset(tmp
, bld
, i
+ first_component
));
2918 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2920 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2922 inst
->offset
= imm_offset
;
2928 case nir_intrinsic_store_output
:
2929 case nir_intrinsic_store_per_vertex_output
: {
2930 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2931 fs_reg value
= get_nir_src(instr
->src
[0]);
2932 fs_reg indirect_offset
= get_indirect_offset(instr
);
2933 unsigned imm_offset
= instr
->const_index
[0];
2934 unsigned mask
= instr
->const_index
[1];
2935 unsigned header_regs
= 0;
2936 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2939 srcs
[header_regs
++] = output_handles
;
2941 if (indirect_offset
.file
!= BAD_FILE
) {
2942 srcs
[header_regs
++] = indirect_offset
;
2948 unsigned num_components
= util_last_bit(mask
);
2951 /* We can only pack two 64-bit components in a single message, so send
2952 * 2 messages if we have more components
2954 unsigned first_component
= nir_intrinsic_component(instr
);
2955 mask
= mask
<< first_component
;
2957 if (mask
!= WRITEMASK_XYZW
) {
2958 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2959 opcode
= indirect_offset
.file
!= BAD_FILE
?
2960 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2961 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2963 opcode
= indirect_offset
.file
!= BAD_FILE
?
2964 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2965 SHADER_OPCODE_URB_WRITE_SIMD8
;
2968 for (unsigned i
= 0; i
< num_components
; i
++) {
2969 if (!(mask
& (1 << (i
+ first_component
))))
2972 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2975 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2977 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2978 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2980 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2981 inst
->offset
= imm_offset
;
2987 nir_emit_intrinsic(bld
, instr
);
2993 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2994 nir_intrinsic_instr
*instr
)
2996 assert(stage
== MESA_SHADER_TESS_EVAL
);
2997 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
3000 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3001 dest
= get_nir_dest(instr
->dest
);
3003 switch (instr
->intrinsic
) {
3004 case nir_intrinsic_load_primitive_id
:
3005 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3007 case nir_intrinsic_load_tess_coord
:
3008 /* gl_TessCoord is part of the payload in g1-3 */
3009 for (unsigned i
= 0; i
< 3; i
++) {
3010 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3014 case nir_intrinsic_load_input
:
3015 case nir_intrinsic_load_per_vertex_input
: {
3016 assert(nir_dest_bit_size(instr
->dest
) == 32);
3017 fs_reg indirect_offset
= get_indirect_offset(instr
);
3018 unsigned imm_offset
= instr
->const_index
[0];
3019 unsigned first_component
= nir_intrinsic_component(instr
);
3022 if (indirect_offset
.file
== BAD_FILE
) {
3023 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3024 * which is 16 registers (since each holds 2 vec4 slots).
3026 const unsigned max_push_slots
= 32;
3027 if (imm_offset
< max_push_slots
) {
3028 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3029 for (int i
= 0; i
< instr
->num_components
; i
++) {
3030 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
3031 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3034 tes_prog_data
->base
.urb_read_length
=
3035 MAX2(tes_prog_data
->base
.urb_read_length
,
3036 (imm_offset
/ 2) + 1);
3038 /* Replicate the patch handle to all enabled channels */
3039 const fs_reg srcs
[] = {
3040 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3042 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3043 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3045 if (first_component
!= 0) {
3046 unsigned read_components
=
3047 instr
->num_components
+ first_component
;
3048 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3049 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3051 inst
->size_written
= read_components
* REG_SIZE
;
3052 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3053 bld
.MOV(offset(dest
, bld
, i
),
3054 offset(tmp
, bld
, i
+ first_component
));
3057 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3059 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3062 inst
->offset
= imm_offset
;
3065 /* Indirect indexing - use per-slot offsets as well. */
3067 /* We can only read two double components with each URB read, so
3068 * we send two read messages in that case, each one loading up to
3069 * two double components.
3071 unsigned num_components
= instr
->num_components
;
3072 const fs_reg srcs
[] = {
3073 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3076 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3077 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3079 if (first_component
!= 0) {
3080 unsigned read_components
=
3081 num_components
+ first_component
;
3082 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3083 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3085 for (unsigned i
= 0; i
< num_components
; i
++) {
3086 bld
.MOV(offset(dest
, bld
, i
),
3087 offset(tmp
, bld
, i
+ first_component
));
3090 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3094 inst
->offset
= imm_offset
;
3095 inst
->size_written
= (num_components
+ first_component
) *
3096 inst
->dst
.component_size(inst
->exec_size
);
3101 nir_emit_intrinsic(bld
, instr
);
3107 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3108 nir_intrinsic_instr
*instr
)
3110 assert(stage
== MESA_SHADER_GEOMETRY
);
3111 fs_reg indirect_offset
;
3114 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3115 dest
= get_nir_dest(instr
->dest
);
3117 switch (instr
->intrinsic
) {
3118 case nir_intrinsic_load_primitive_id
:
3119 assert(stage
== MESA_SHADER_GEOMETRY
);
3120 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3121 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3122 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3125 case nir_intrinsic_load_input
:
3126 unreachable("load_input intrinsics are invalid for the GS stage");
3128 case nir_intrinsic_load_per_vertex_input
:
3129 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3130 instr
->src
[1], instr
->num_components
,
3131 nir_intrinsic_component(instr
));
3134 case nir_intrinsic_emit_vertex_with_counter
:
3135 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3138 case nir_intrinsic_end_primitive_with_counter
:
3139 emit_gs_end_primitive(instr
->src
[0]);
3142 case nir_intrinsic_set_vertex_count
:
3143 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3146 case nir_intrinsic_load_invocation_id
: {
3147 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3148 assert(val
.file
!= BAD_FILE
);
3149 dest
.type
= val
.type
;
3155 nir_emit_intrinsic(bld
, instr
);
3161 * Fetch the current render target layer index.
3164 fetch_render_target_array_index(const fs_builder
&bld
)
3166 if (bld
.shader
->devinfo
->gen
>= 12) {
3167 /* The render target array index is provided in the thread payload as
3168 * bits 26:16 of r1.1.
3170 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3171 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 1, 3),
3174 } else if (bld
.shader
->devinfo
->gen
>= 6) {
3175 /* The render target array index is provided in the thread payload as
3176 * bits 26:16 of r0.0.
3178 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3179 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3183 /* Pre-SNB we only ever render into the first layer of the framebuffer
3184 * since layered rendering is not implemented.
3186 return brw_imm_ud(0);
3191 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3192 * framebuffer at the current fragment coordinates and sample index.
3195 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3198 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3200 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3201 const brw_wm_prog_key
*wm_key
=
3202 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3203 assert(!wm_key
->coherent_fb_fetch
);
3204 const struct brw_wm_prog_data
*wm_prog_data
=
3205 brw_wm_prog_data(stage_prog_data
);
3207 /* Calculate the surface index relative to the start of the texture binding
3208 * table block, since that's what the texturing messages expect.
3210 const unsigned surface
= target
+
3211 wm_prog_data
->binding_table
.render_target_read_start
-
3212 wm_prog_data
->base
.binding_table
.texture_start
;
3214 /* Calculate the fragment coordinates. */
3215 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3216 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3217 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3218 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3220 /* Calculate the sample index and MCS payload when multisampling. Luckily
3221 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3222 * shouldn't be necessary to recompile based on whether the framebuffer is
3225 if (wm_key
->multisample_fbo
&&
3226 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3227 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3229 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3230 const fs_reg mcs
= wm_key
->multisample_fbo
?
3231 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3233 /* Use either a normal or a CMS texel fetch message depending on whether
3234 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3235 * message just in case the framebuffer uses 16x multisampling, it should
3236 * be equivalent to the normal CMS fetch for lower multisampling modes.
3238 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3239 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3240 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3242 /* Emit the instruction. */
3243 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3244 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3245 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3246 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3247 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3248 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3249 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3250 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3251 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3253 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3254 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3260 * Actual coherent framebuffer read implemented using the native render target
3261 * read message. Requires SKL+.
3264 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3266 assert(bld
.shader
->devinfo
->gen
>= 9);
3267 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3268 inst
->target
= target
;
3269 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3275 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3277 if (n
&& regs
[0].file
!= BAD_FILE
) {
3281 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3283 for (unsigned i
= 0; i
< n
; i
++)
3291 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3293 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3294 const brw_wm_prog_key
*const key
=
3295 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3296 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3297 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3299 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3300 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3302 else if (l
== FRAG_RESULT_COLOR
)
3303 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3304 MAX2(key
->nr_color_regions
, 1));
3306 else if (l
== FRAG_RESULT_DEPTH
)
3307 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3309 else if (l
== FRAG_RESULT_STENCIL
)
3310 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3312 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3313 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3315 else if (l
>= FRAG_RESULT_DATA0
&&
3316 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3317 return alloc_temporary(v
->bld
, 4,
3318 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3321 unreachable("Invalid location");
3325 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3326 nir_intrinsic_instr
*instr
)
3328 assert(stage
== MESA_SHADER_FRAGMENT
);
3331 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3332 dest
= get_nir_dest(instr
->dest
);
3334 switch (instr
->intrinsic
) {
3335 case nir_intrinsic_load_front_face
:
3336 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3337 *emit_frontfacing_interpolation());
3340 case nir_intrinsic_load_sample_pos
: {
3341 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3342 assert(sample_pos
.file
!= BAD_FILE
);
3343 dest
.type
= sample_pos
.type
;
3344 bld
.MOV(dest
, sample_pos
);
3345 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3349 case nir_intrinsic_load_layer_id
:
3350 dest
.type
= BRW_REGISTER_TYPE_UD
;
3351 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3354 case nir_intrinsic_is_helper_invocation
: {
3355 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3356 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3357 * consideration demoted invocations. That information is stored in
3360 dest
.type
= BRW_REGISTER_TYPE_UD
;
3362 bld
.MOV(dest
, brw_imm_ud(0));
3364 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3365 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3366 mov
->predicate_inverse
= true;
3367 mov
->flag_subreg
= sample_mask_flag_subreg(this);
3371 case nir_intrinsic_load_helper_invocation
:
3372 case nir_intrinsic_load_sample_mask_in
:
3373 case nir_intrinsic_load_sample_id
: {
3374 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3375 fs_reg val
= nir_system_values
[sv
];
3376 assert(val
.file
!= BAD_FILE
);
3377 dest
.type
= val
.type
;
3382 case nir_intrinsic_store_output
: {
3383 const fs_reg src
= get_nir_src(instr
->src
[0]);
3384 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3385 const unsigned location
= nir_intrinsic_base(instr
) +
3386 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3387 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3390 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3391 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3392 offset(src
, bld
, j
));
3397 case nir_intrinsic_load_output
: {
3398 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3399 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3400 assert(l
>= FRAG_RESULT_DATA0
);
3401 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3402 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3403 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3405 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3406 emit_coherent_fb_read(bld
, tmp
, target
);
3408 emit_non_coherent_fb_read(bld
, tmp
, target
);
3410 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3411 bld
.MOV(offset(dest
, bld
, j
),
3412 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3418 case nir_intrinsic_demote
:
3419 case nir_intrinsic_discard
:
3420 case nir_intrinsic_demote_if
:
3421 case nir_intrinsic_discard_if
: {
3422 /* We track our discarded pixels in f0.1/f1.0. By predicating on it, we
3423 * can update just the flag bits that aren't yet discarded. If there's
3424 * no condition, we emit a CMP of g0 != g0, so all currently executing
3425 * channels will get turned off.
3427 fs_inst
*cmp
= NULL
;
3428 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3429 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3430 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3433 alu
->op
!= nir_op_bcsel
&&
3434 (devinfo
->gen
> 5 ||
3435 (alu
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE
||
3436 alu
->op
== nir_op_fne32
|| alu
->op
== nir_op_feq32
||
3437 alu
->op
== nir_op_flt32
|| alu
->op
== nir_op_fge32
||
3438 alu
->op
== nir_op_ine32
|| alu
->op
== nir_op_ieq32
||
3439 alu
->op
== nir_op_ilt32
|| alu
->op
== nir_op_ige32
||
3440 alu
->op
== nir_op_ult32
|| alu
->op
== nir_op_uge32
)) {
3441 /* Re-emit the instruction that generated the Boolean value, but
3442 * do not store it. Since this instruction will be conditional,
3443 * other instructions that want to use the real Boolean value may
3444 * get garbage. This was a problem for piglit's fs-discard-exit-2
3447 * Ideally we'd detect that the instruction cannot have a
3448 * conditional modifier before emitting the instructions. Alas,
3449 * that is nigh impossible. Instead, we're going to assume the
3450 * instruction (or last instruction) generated can have a
3451 * conditional modifier. If it cannot, fallback to the old-style
3452 * compare, and hope dead code elimination will clean up the
3453 * extra instructions generated.
3455 nir_emit_alu(bld
, alu
, false);
3457 cmp
= (fs_inst
*) instructions
.get_tail();
3458 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3459 if (cmp
->can_do_cmod())
3460 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3464 /* The old sequence that would have been generated is,
3465 * basically, bool_result == false. This is equivalent to
3466 * !bool_result, so negate the old modifier.
3468 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3473 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3474 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3477 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3478 BRW_REGISTER_TYPE_UW
));
3479 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3482 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3483 cmp
->flag_subreg
= sample_mask_flag_subreg(this);
3485 emit_discard_jump();
3487 if (devinfo
->gen
< 7)
3488 limit_dispatch_width(
3489 16, "Fragment discard/demote not implemented in SIMD32 mode.\n");
3493 case nir_intrinsic_load_input
: {
3494 /* load_input is only used for flat inputs */
3495 assert(nir_dest_bit_size(instr
->dest
) == 32);
3496 unsigned base
= nir_intrinsic_base(instr
);
3497 unsigned comp
= nir_intrinsic_component(instr
);
3498 unsigned num_components
= instr
->num_components
;
3500 /* Special case fields in the VUE header */
3501 if (base
== VARYING_SLOT_LAYER
)
3503 else if (base
== VARYING_SLOT_VIEWPORT
)
3506 for (unsigned int i
= 0; i
< num_components
; i
++) {
3507 bld
.MOV(offset(dest
, bld
, i
),
3508 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3513 case nir_intrinsic_load_fs_input_interp_deltas
: {
3514 assert(stage
== MESA_SHADER_FRAGMENT
);
3515 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3516 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3517 nir_intrinsic_component(instr
));
3518 dest
.type
= BRW_REGISTER_TYPE_F
;
3519 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3520 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3521 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3525 case nir_intrinsic_load_barycentric_pixel
:
3526 case nir_intrinsic_load_barycentric_centroid
:
3527 case nir_intrinsic_load_barycentric_sample
: {
3528 /* Use the delta_xy values computed from the payload */
3529 const glsl_interp_mode interp_mode
=
3530 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3531 enum brw_barycentric_mode bary
=
3532 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3533 const fs_reg srcs
[] = { offset(this->delta_xy
[bary
], bld
, 0),
3534 offset(this->delta_xy
[bary
], bld
, 1) };
3535 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3539 case nir_intrinsic_load_barycentric_at_sample
: {
3540 const glsl_interp_mode interpolation
=
3541 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3543 if (nir_src_is_const(instr
->src
[0])) {
3544 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3546 emit_pixel_interpolater_send(bld
,
3547 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3550 brw_imm_ud(msg_data
),
3553 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3554 BRW_REGISTER_TYPE_UD
);
3556 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3557 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3558 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3559 bld
.exec_all().group(1, 0)
3560 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3561 emit_pixel_interpolater_send(bld
,
3562 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3565 component(msg_data
, 0),
3568 /* Make a loop that sends a message to the pixel interpolater
3569 * for the sample number in each live channel. If there are
3570 * multiple channels with the same sample number then these
3571 * will be handled simultaneously with a single interation of
3574 bld
.emit(BRW_OPCODE_DO
);
3576 /* Get the next live sample number into sample_id_reg */
3577 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3579 /* Set the flag register so that we can perform the send
3580 * message on all channels that have the same sample number
3582 bld
.CMP(bld
.null_reg_ud(),
3583 sample_src
, sample_id
,
3584 BRW_CONDITIONAL_EQ
);
3585 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3586 bld
.exec_all().group(1, 0)
3587 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3589 emit_pixel_interpolater_send(bld
,
3590 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3593 component(msg_data
, 0),
3595 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3597 /* Continue the loop if there are any live channels left */
3598 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3600 bld
.emit(BRW_OPCODE_WHILE
));
3606 case nir_intrinsic_load_barycentric_at_offset
: {
3607 const glsl_interp_mode interpolation
=
3608 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3610 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3613 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3614 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3615 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3617 emit_pixel_interpolater_send(bld
,
3618 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3621 brw_imm_ud(off_x
| (off_y
<< 4)),
3624 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3625 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3626 BRW_REGISTER_TYPE_F
);
3627 for (int i
= 0; i
< 2; i
++) {
3628 fs_reg temp
= vgrf(glsl_type::float_type
);
3629 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3630 fs_reg itemp
= vgrf(glsl_type::int_type
);
3632 bld
.MOV(itemp
, temp
);
3634 /* Clamp the upper end of the range to +7/16.
3635 * ARB_gpu_shader5 requires that we support a maximum offset
3636 * of +0.5, which isn't representable in a S0.4 value -- if
3637 * we didn't clamp it, we'd end up with -8/16, which is the
3638 * opposite of what the shader author wanted.
3640 * This is legal due to ARB_gpu_shader5's quantization
3643 * "Not all values of <offset> may be supported; x and y
3644 * offsets may be rounded to fixed-point values with the
3645 * number of fraction bits given by the
3646 * implementation-dependent constant
3647 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3649 set_condmod(BRW_CONDITIONAL_L
,
3650 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3653 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3654 emit_pixel_interpolater_send(bld
,
3664 case nir_intrinsic_load_frag_coord
:
3665 emit_fragcoord_interpolation(dest
);
3668 case nir_intrinsic_load_interpolated_input
: {
3669 assert(instr
->src
[0].ssa
&&
3670 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3671 nir_intrinsic_instr
*bary_intrinsic
=
3672 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3673 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3674 enum glsl_interp_mode interp_mode
=
3675 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3678 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3679 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3680 /* Use the result of the PI message. */
3681 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3683 /* Use the delta_xy values computed from the payload */
3684 enum brw_barycentric_mode bary
=
3685 brw_barycentric_mode(interp_mode
, bary_intrin
);
3686 dst_xy
= this->delta_xy
[bary
];
3689 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3691 component(interp_reg(nir_intrinsic_base(instr
),
3692 nir_intrinsic_component(instr
) + i
), 0);
3693 interp
.type
= BRW_REGISTER_TYPE_F
;
3694 dest
.type
= BRW_REGISTER_TYPE_F
;
3696 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3697 fs_reg tmp
= vgrf(glsl_type::float_type
);
3698 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3699 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3701 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3708 nir_emit_intrinsic(bld
, instr
);
3714 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3715 nir_intrinsic_instr
*instr
)
3717 assert(stage
== MESA_SHADER_COMPUTE
);
3718 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3721 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3722 dest
= get_nir_dest(instr
->dest
);
3724 switch (instr
->intrinsic
) {
3725 case nir_intrinsic_control_barrier
:
3726 /* The whole workgroup fits in a single HW thread, so all the
3727 * invocations are already executed lock-step. Instead of an actual
3728 * barrier just emit a scheduling fence, that will generate no code.
3730 if (!nir
->info
.cs
.local_size_variable
&&
3731 workgroup_size() <= dispatch_width
) {
3732 bld
.exec_all().group(1, 0).emit(FS_OPCODE_SCHEDULING_FENCE
);
3737 cs_prog_data
->uses_barrier
= true;
3740 case nir_intrinsic_load_subgroup_id
:
3741 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3744 case nir_intrinsic_load_local_invocation_id
:
3745 case nir_intrinsic_load_work_group_id
: {
3746 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3747 fs_reg val
= nir_system_values
[sv
];
3748 assert(val
.file
!= BAD_FILE
);
3749 dest
.type
= val
.type
;
3750 for (unsigned i
= 0; i
< 3; i
++)
3751 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3755 case nir_intrinsic_load_num_work_groups
: {
3756 const unsigned surface
=
3757 cs_prog_data
->binding_table
.work_groups_start
;
3759 cs_prog_data
->uses_num_work_groups
= true;
3761 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3762 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3763 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3764 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3766 /* Read the 3 GLuint components of gl_NumWorkGroups */
3767 for (unsigned i
= 0; i
< 3; i
++) {
3768 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3769 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3770 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3775 case nir_intrinsic_shared_atomic_add
:
3776 case nir_intrinsic_shared_atomic_imin
:
3777 case nir_intrinsic_shared_atomic_umin
:
3778 case nir_intrinsic_shared_atomic_imax
:
3779 case nir_intrinsic_shared_atomic_umax
:
3780 case nir_intrinsic_shared_atomic_and
:
3781 case nir_intrinsic_shared_atomic_or
:
3782 case nir_intrinsic_shared_atomic_xor
:
3783 case nir_intrinsic_shared_atomic_exchange
:
3784 case nir_intrinsic_shared_atomic_comp_swap
:
3785 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3787 case nir_intrinsic_shared_atomic_fmin
:
3788 case nir_intrinsic_shared_atomic_fmax
:
3789 case nir_intrinsic_shared_atomic_fcomp_swap
:
3790 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3793 case nir_intrinsic_load_shared
: {
3794 assert(devinfo
->gen
>= 7);
3795 assert(stage
== MESA_SHADER_COMPUTE
);
3797 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3798 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3799 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3800 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3801 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3803 /* Make dest unsigned because that's what the temporary will be */
3804 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3806 /* Read the vector */
3807 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3808 assert(nir_intrinsic_align(instr
) > 0);
3809 if (nir_dest_bit_size(instr
->dest
) == 32 &&
3810 nir_intrinsic_align(instr
) >= 4) {
3811 assert(nir_dest_num_components(instr
->dest
) <= 4);
3812 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3814 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3815 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3816 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3818 assert(nir_dest_num_components(instr
->dest
) == 1);
3819 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3821 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3822 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3823 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3824 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3829 case nir_intrinsic_store_shared
: {
3830 assert(devinfo
->gen
>= 7);
3831 assert(stage
== MESA_SHADER_COMPUTE
);
3833 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3834 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3835 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3836 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3837 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3839 fs_reg data
= get_nir_src(instr
->src
[0]);
3840 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3842 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3843 assert(nir_intrinsic_write_mask(instr
) ==
3844 (1u << instr
->num_components
) - 1);
3845 assert(nir_intrinsic_align(instr
) > 0);
3846 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
3847 nir_intrinsic_align(instr
) >= 4) {
3848 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3849 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3850 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3851 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3852 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3854 assert(nir_src_num_components(instr
->src
[0]) == 1);
3855 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3857 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3858 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3860 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3861 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3866 case nir_intrinsic_load_local_group_size
: {
3867 assert(compiler
->lower_variable_group_size
);
3868 assert(nir
->info
.cs
.local_size_variable
);
3869 for (unsigned i
= 0; i
< 3; i
++) {
3870 bld
.MOV(retype(offset(dest
, bld
, i
), BRW_REGISTER_TYPE_UD
),
3877 nir_emit_intrinsic(bld
, instr
);
3883 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3884 nir_op op
, brw_reg_type type
)
3886 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3887 switch (type_sz(type
)) {
3889 if (type
== BRW_REGISTER_TYPE_UB
) {
3890 return brw_imm_uw(value
.u8
);
3892 assert(type
== BRW_REGISTER_TYPE_B
);
3893 return brw_imm_w(value
.i8
);
3896 return retype(brw_imm_uw(value
.u16
), type
);
3898 return retype(brw_imm_ud(value
.u32
), type
);
3900 if (type
== BRW_REGISTER_TYPE_DF
)
3901 return setup_imm_df(bld
, value
.f64
);
3903 return retype(brw_imm_u64(value
.u64
), type
);
3905 unreachable("Invalid type size");
3910 brw_op_for_nir_reduction_op(nir_op op
)
3913 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3914 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3915 case nir_op_imul
: return BRW_OPCODE_MUL
;
3916 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3917 case nir_op_imin
: return BRW_OPCODE_SEL
;
3918 case nir_op_umin
: return BRW_OPCODE_SEL
;
3919 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3920 case nir_op_imax
: return BRW_OPCODE_SEL
;
3921 case nir_op_umax
: return BRW_OPCODE_SEL
;
3922 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3923 case nir_op_iand
: return BRW_OPCODE_AND
;
3924 case nir_op_ior
: return BRW_OPCODE_OR
;
3925 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3927 unreachable("Invalid reduction operation");
3931 static brw_conditional_mod
3932 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3935 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3936 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3937 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3938 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3939 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3940 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3941 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3942 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3943 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3944 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3945 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3946 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3947 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3949 unreachable("Invalid reduction operation");
3954 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3955 nir_intrinsic_instr
*instr
)
3957 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3958 fs_reg surf_index
= image
;
3960 if (stage_prog_data
->binding_table
.image_start
> 0) {
3961 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3963 brw_imm_ud(image
.d
+ stage_prog_data
->binding_table
.image_start
);
3965 surf_index
= vgrf(glsl_type::uint_type
);
3966 bld
.ADD(surf_index
, image
,
3967 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3971 return bld
.emit_uniformize(surf_index
);
3975 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3976 nir_intrinsic_instr
*instr
)
3978 /* SSBO stores are weird in that their index is in src[1] */
3979 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3982 if (nir_src_is_const(instr
->src
[src
])) {
3983 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3984 nir_src_as_uint(instr
->src
[src
]);
3985 surf_index
= brw_imm_ud(index
);
3987 surf_index
= vgrf(glsl_type::uint_type
);
3988 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3989 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3992 return bld
.emit_uniformize(surf_index
);
3996 * The offsets we get from NIR act as if each SIMD channel has it's own blob
3997 * of contiguous space. However, if we actually place each SIMD channel in
3998 * it's own space, we end up with terrible cache performance because each SIMD
3999 * channel accesses a different cache line even when they're all accessing the
4000 * same byte offset. To deal with this problem, we swizzle the address using
4001 * a simple algorithm which ensures that any time a SIMD message reads or
4002 * writes the same address, it's all in the same cache line. We have to keep
4003 * the bottom two bits fixed so that we can read/write up to a dword at a time
4004 * and the individual element is contiguous. We do this by splitting the
4005 * address as follows:
4008 * +-------------------------------+------------+----------+
4009 * | Hi address bits | chan index | addr low |
4010 * +-------------------------------+------------+----------+
4012 * In other words, the bottom two address bits stay, and the top 30 get
4013 * shifted up so that we can stick the SIMD channel index in the middle. This
4014 * way, we can access 8, 16, or 32-bit elements and, when accessing a 32-bit
4015 * at the same logical offset, the scratch read/write instruction acts on
4016 * continuous elements and we get good cache locality.
4019 fs_visitor::swizzle_nir_scratch_addr(const brw::fs_builder
&bld
,
4020 const fs_reg
&nir_addr
,
4023 const fs_reg
&chan_index
=
4024 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
4025 const unsigned chan_index_bits
= ffs(dispatch_width
) - 1;
4027 fs_reg addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4029 /* In this case, we know the address is aligned to a DWORD and we want
4030 * the final address in DWORDs.
4032 bld
.SHL(addr
, nir_addr
, brw_imm_ud(chan_index_bits
- 2));
4033 bld
.OR(addr
, addr
, chan_index
);
4035 /* This case substantially more annoying because we have to pay
4036 * attention to those pesky two bottom bits.
4038 fs_reg addr_hi
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4039 bld
.AND(addr_hi
, nir_addr
, brw_imm_ud(~0x3u
));
4040 bld
.SHL(addr_hi
, addr_hi
, brw_imm_ud(chan_index_bits
));
4041 fs_reg chan_addr
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4042 bld
.SHL(chan_addr
, chan_index
, brw_imm_ud(2));
4043 bld
.AND(addr
, nir_addr
, brw_imm_ud(0x3u
));
4044 bld
.OR(addr
, addr
, addr_hi
);
4045 bld
.OR(addr
, addr
, chan_addr
);
4051 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4054 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4055 dest
= get_nir_dest(instr
->dest
);
4057 switch (instr
->intrinsic
) {
4058 case nir_intrinsic_image_load
:
4059 case nir_intrinsic_image_store
:
4060 case nir_intrinsic_image_atomic_add
:
4061 case nir_intrinsic_image_atomic_imin
:
4062 case nir_intrinsic_image_atomic_umin
:
4063 case nir_intrinsic_image_atomic_imax
:
4064 case nir_intrinsic_image_atomic_umax
:
4065 case nir_intrinsic_image_atomic_and
:
4066 case nir_intrinsic_image_atomic_or
:
4067 case nir_intrinsic_image_atomic_xor
:
4068 case nir_intrinsic_image_atomic_exchange
:
4069 case nir_intrinsic_image_atomic_comp_swap
:
4070 case nir_intrinsic_bindless_image_load
:
4071 case nir_intrinsic_bindless_image_store
:
4072 case nir_intrinsic_bindless_image_atomic_add
:
4073 case nir_intrinsic_bindless_image_atomic_imin
:
4074 case nir_intrinsic_bindless_image_atomic_umin
:
4075 case nir_intrinsic_bindless_image_atomic_imax
:
4076 case nir_intrinsic_bindless_image_atomic_umax
:
4077 case nir_intrinsic_bindless_image_atomic_and
:
4078 case nir_intrinsic_bindless_image_atomic_or
:
4079 case nir_intrinsic_bindless_image_atomic_xor
:
4080 case nir_intrinsic_bindless_image_atomic_exchange
:
4081 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4082 /* Get some metadata from the image intrinsic. */
4083 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4085 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4087 switch (instr
->intrinsic
) {
4088 case nir_intrinsic_image_load
:
4089 case nir_intrinsic_image_store
:
4090 case nir_intrinsic_image_atomic_add
:
4091 case nir_intrinsic_image_atomic_imin
:
4092 case nir_intrinsic_image_atomic_umin
:
4093 case nir_intrinsic_image_atomic_imax
:
4094 case nir_intrinsic_image_atomic_umax
:
4095 case nir_intrinsic_image_atomic_and
:
4096 case nir_intrinsic_image_atomic_or
:
4097 case nir_intrinsic_image_atomic_xor
:
4098 case nir_intrinsic_image_atomic_exchange
:
4099 case nir_intrinsic_image_atomic_comp_swap
:
4100 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4101 get_nir_image_intrinsic_image(bld
, instr
);
4106 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4107 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4111 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4112 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4113 brw_imm_ud(nir_image_intrinsic_coord_components(instr
));
4115 /* Emit an image load, store or atomic op. */
4116 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4117 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4118 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4120 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4121 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4122 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4123 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4124 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4125 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4126 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4127 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4128 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4130 unsigned num_srcs
= info
->num_srcs
;
4131 int op
= brw_aop_for_nir_intrinsic(instr
);
4132 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4133 assert(num_srcs
== 4);
4137 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4141 data
= get_nir_src(instr
->src
[3]);
4142 if (num_srcs
>= 5) {
4143 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4144 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4145 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4148 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4150 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4151 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4156 case nir_intrinsic_image_size
:
4157 case nir_intrinsic_bindless_image_size
: {
4158 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4159 * into will handle the binding table index for us in the geneerator.
4160 * Incidentally, this means that we can handle bindless with exactly the
4163 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4164 BRW_REGISTER_TYPE_UD
);
4165 image
= bld
.emit_uniformize(image
);
4167 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4168 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4169 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4171 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4172 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4173 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4174 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4176 /* Since the image size is always uniform, we can just emit a SIMD8
4177 * query instruction and splat the result out.
4179 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4181 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4182 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4183 tmp
, srcs
, ARRAY_SIZE(srcs
));
4184 inst
->size_written
= 4 * REG_SIZE
;
4186 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4187 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4188 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4189 offset(retype(dest
, tmp
.type
), bld
, c
),
4190 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4192 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4193 component(offset(tmp
, ubld
, c
), 0));
4199 case nir_intrinsic_image_load_raw_intel
: {
4200 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4201 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4202 get_nir_image_intrinsic_image(bld
, instr
);
4203 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4204 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4205 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4208 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4209 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4210 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4214 case nir_intrinsic_image_store_raw_intel
: {
4215 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4216 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4217 get_nir_image_intrinsic_image(bld
, instr
);
4218 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4219 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4220 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4221 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4223 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4224 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4228 case nir_intrinsic_scoped_barrier
:
4229 assert(nir_intrinsic_execution_scope(instr
) == NIR_SCOPE_NONE
);
4231 case nir_intrinsic_group_memory_barrier
:
4232 case nir_intrinsic_memory_barrier_shared
:
4233 case nir_intrinsic_memory_barrier_buffer
:
4234 case nir_intrinsic_memory_barrier_image
:
4235 case nir_intrinsic_memory_barrier
:
4236 case nir_intrinsic_begin_invocation_interlock
:
4237 case nir_intrinsic_end_invocation_interlock
: {
4238 bool l3_fence
, slm_fence
;
4239 const enum opcode opcode
=
4240 instr
->intrinsic
== nir_intrinsic_begin_invocation_interlock
?
4241 SHADER_OPCODE_INTERLOCK
: SHADER_OPCODE_MEMORY_FENCE
;
4243 switch (instr
->intrinsic
) {
4244 case nir_intrinsic_scoped_barrier
: {
4245 nir_variable_mode modes
= nir_intrinsic_memory_modes(instr
);
4246 l3_fence
= modes
& (nir_var_shader_out
|
4248 nir_var_mem_global
);
4249 slm_fence
= modes
& nir_var_mem_shared
;
4253 case nir_intrinsic_begin_invocation_interlock
:
4254 case nir_intrinsic_end_invocation_interlock
:
4255 /* For beginInvocationInterlockARB(), we will generate a memory fence
4256 * but with a different opcode so that generator can pick SENDC
4259 * For endInvocationInterlockARB(), we need to insert a memory fence which
4260 * stalls in the shader until the memory transactions prior to that
4261 * fence are complete. This ensures that the shader does not end before
4262 * any writes from its critical section have landed. Otherwise, you can
4263 * end up with a case where the next invocation on that pixel properly
4264 * stalls for previous FS invocation on its pixel to complete but
4265 * doesn't actually wait for the dataport memory transactions from that
4266 * thread to land before submitting its own.
4268 * Handling them here will allow the logic for IVB render cache (see
4269 * below) to be reused.
4276 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4277 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4278 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4279 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4283 if (stage
!= MESA_SHADER_COMPUTE
)
4286 /* If the workgroup fits in a single HW thread, the messages for SLM are
4287 * processed in-order and the shader itself is already synchronized so
4288 * the memory fence is not necessary.
4290 * TODO: Check if applies for many HW threads sharing same Data Port.
4292 if (!nir
->info
.cs
.local_size_variable
&&
4293 slm_fence
&& workgroup_size() <= dispatch_width
)
4296 /* Prior to Gen11, there's only L3 fence, so emit that instead. */
4297 if (slm_fence
&& devinfo
->gen
< 11) {
4302 /* IVB does typed surface access through the render cache, so we need
4305 const bool needs_render_fence
=
4306 devinfo
->gen
== 7 && !devinfo
->is_haswell
;
4308 /* Be conservative in Gen11+ and always stall in a fence. Since there
4309 * are two different fences, and shader might want to synchronize
4312 * TODO: Use scope and visibility information for the barriers from NIR
4313 * to make a better decision on whether we need to stall.
4315 const bool stall
= devinfo
->gen
>= 11 || needs_render_fence
||
4316 instr
->intrinsic
== nir_intrinsic_end_invocation_interlock
;
4318 const bool commit_enable
= stall
||
4319 devinfo
->gen
>= 10; /* HSD ES # 1404612949 */
4321 unsigned fence_regs_count
= 0;
4322 fs_reg fence_regs
[2] = {};
4324 const fs_builder ubld
= bld
.group(8, 0);
4329 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4331 brw_imm_ud(commit_enable
),
4332 brw_imm_ud(/* bti */ 0));
4333 fence
->sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
4335 fence_regs
[fence_regs_count
++] = fence
->dst
;
4337 if (needs_render_fence
) {
4338 fs_inst
*render_fence
=
4340 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4342 brw_imm_ud(commit_enable
),
4343 brw_imm_ud(/* bti */ 0));
4344 render_fence
->sfid
= GEN6_SFID_DATAPORT_RENDER_CACHE
;
4346 fence_regs
[fence_regs_count
++] = render_fence
->dst
;
4351 assert(opcode
== SHADER_OPCODE_MEMORY_FENCE
);
4354 ubld
.vgrf(BRW_REGISTER_TYPE_UD
),
4356 brw_imm_ud(commit_enable
),
4357 brw_imm_ud(GEN7_BTI_SLM
));
4358 fence
->sfid
= GEN7_SFID_DATAPORT_DATA_CACHE
;
4360 fence_regs
[fence_regs_count
++] = fence
->dst
;
4363 assert(fence_regs_count
<= 2);
4365 if (stall
|| fence_regs_count
== 0) {
4366 ubld
.exec_all().group(1, 0).emit(
4367 FS_OPCODE_SCHEDULING_FENCE
, ubld
.null_reg_ud(),
4368 fence_regs
, fence_regs_count
);
4374 case nir_intrinsic_memory_barrier_tcs_patch
:
4377 case nir_intrinsic_shader_clock
: {
4378 /* We cannot do anything if there is an event, so ignore it for now */
4379 const fs_reg shader_clock
= get_timestamp(bld
);
4380 const fs_reg srcs
[] = { component(shader_clock
, 0),
4381 component(shader_clock
, 1) };
4382 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4386 case nir_intrinsic_image_samples
:
4387 /* The driver does not support multi-sampled images. */
4388 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4391 case nir_intrinsic_load_uniform
: {
4392 /* Offsets are in bytes but they should always aligned to
4395 assert(instr
->const_index
[0] % 4 == 0 ||
4396 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4398 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4400 if (nir_src_is_const(instr
->src
[0])) {
4401 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4402 assert(load_offset
% type_sz(dest
.type
) == 0);
4403 /* For 16-bit types we add the module of the const_index[0]
4404 * offset to access to not 32-bit aligned element
4406 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4408 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4409 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4412 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4413 BRW_REGISTER_TYPE_UD
);
4415 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4416 * go past the end of the uniform. In order to keep the n'th
4417 * component from running past, we subtract off the size of all but
4418 * one component of the vector.
4420 assert(instr
->const_index
[1] >=
4421 instr
->num_components
* (int) type_sz(dest
.type
));
4422 unsigned read_size
= instr
->const_index
[1] -
4423 (instr
->num_components
- 1) * type_sz(dest
.type
);
4425 bool supports_64bit_indirects
=
4426 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4428 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4429 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4430 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4431 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4432 indirect
, brw_imm_ud(read_size
));
4435 const unsigned num_mov_indirects
=
4436 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4437 /* We read a little bit less per MOV INDIRECT, as they are now
4438 * 32-bits ones instead of 64-bit. Fix read_size then.
4440 const unsigned read_size_32bit
= read_size
-
4441 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4442 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4443 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4444 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4445 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4446 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4447 indirect
, brw_imm_ud(read_size_32bit
));
4455 case nir_intrinsic_load_ubo
: {
4457 if (nir_src_is_const(instr
->src
[0])) {
4458 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4459 nir_src_as_uint(instr
->src
[0]);
4460 surf_index
= brw_imm_ud(index
);
4462 /* The block index is not a constant. Evaluate the index expression
4463 * per-channel and add the base UBO index; we have to select a value
4464 * from any live channel.
4466 surf_index
= vgrf(glsl_type::uint_type
);
4467 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4468 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4469 surf_index
= bld
.emit_uniformize(surf_index
);
4472 if (!nir_src_is_const(instr
->src
[1])) {
4473 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4474 BRW_REGISTER_TYPE_UD
);
4476 for (int i
= 0; i
< instr
->num_components
; i
++)
4477 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4478 base_offset
, i
* type_sz(dest
.type
));
4480 prog_data
->has_ubo_pull
= true;
4482 /* Even if we are loading doubles, a pull constant load will load
4483 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4484 * need to load a full dvec4 we will have to emit 2 loads. This is
4485 * similar to demote_pull_constants(), except that in that case we
4486 * see individual accesses to each component of the vector and then
4487 * we let CSE deal with duplicate loads. Here we see a vector access
4488 * and we have to split it if necessary.
4490 const unsigned type_size
= type_sz(dest
.type
);
4491 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4493 /* See if we've selected this as a push constant candidate */
4494 if (nir_src_is_const(instr
->src
[0])) {
4495 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4496 const unsigned offset_256b
= load_offset
/ 32;
4499 for (int i
= 0; i
< 4; i
++) {
4500 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4501 if (range
->block
== ubo_block
&&
4502 offset_256b
>= range
->start
&&
4503 offset_256b
< range
->start
+ range
->length
) {
4505 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4506 push_reg
.offset
= load_offset
- 32 * range
->start
;
4511 if (push_reg
.file
!= BAD_FILE
) {
4512 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4513 bld
.MOV(offset(dest
, bld
, i
),
4514 byte_offset(push_reg
, i
* type_size
));
4520 prog_data
->has_ubo_pull
= true;
4522 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4523 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4524 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4526 for (unsigned c
= 0; c
< instr
->num_components
;) {
4527 const unsigned base
= load_offset
+ c
* type_size
;
4528 /* Number of usable components in the next block-aligned load. */
4529 const unsigned count
= MIN2(instr
->num_components
- c
,
4530 (block_sz
- base
% block_sz
) / type_size
);
4532 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4533 packed_consts
, surf_index
,
4534 brw_imm_ud(base
& ~(block_sz
- 1)));
4536 const fs_reg consts
=
4537 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4540 for (unsigned d
= 0; d
< count
; d
++)
4541 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4549 case nir_intrinsic_load_global
: {
4550 assert(devinfo
->gen
>= 8);
4552 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4553 assert(nir_intrinsic_align(instr
) > 0);
4554 if (nir_dest_bit_size(instr
->dest
) == 32 &&
4555 nir_intrinsic_align(instr
) >= 4) {
4556 assert(nir_dest_num_components(instr
->dest
) <= 4);
4557 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4559 get_nir_src(instr
->src
[0]), /* Address */
4560 fs_reg(), /* No source data */
4561 brw_imm_ud(instr
->num_components
));
4562 inst
->size_written
= instr
->num_components
*
4563 inst
->dst
.component_size(inst
->exec_size
);
4565 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4566 assert(nir_dest_num_components(instr
->dest
) == 1);
4567 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4568 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4570 get_nir_src(instr
->src
[0]), /* Address */
4571 fs_reg(), /* No source data */
4572 brw_imm_ud(bit_size
));
4573 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4578 case nir_intrinsic_store_global
:
4579 assert(devinfo
->gen
>= 8);
4581 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4582 assert(nir_intrinsic_write_mask(instr
) ==
4583 (1u << instr
->num_components
) - 1);
4584 assert(nir_intrinsic_align(instr
) > 0);
4585 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4586 nir_intrinsic_align(instr
) >= 4) {
4587 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4588 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4590 get_nir_src(instr
->src
[1]), /* Address */
4591 get_nir_src(instr
->src
[0]), /* Data */
4592 brw_imm_ud(instr
->num_components
));
4594 assert(nir_src_num_components(instr
->src
[0]) == 1);
4595 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4596 brw_reg_type data_type
=
4597 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4598 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4599 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4600 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4602 get_nir_src(instr
->src
[1]), /* Address */
4604 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4608 case nir_intrinsic_global_atomic_add
:
4609 case nir_intrinsic_global_atomic_imin
:
4610 case nir_intrinsic_global_atomic_umin
:
4611 case nir_intrinsic_global_atomic_imax
:
4612 case nir_intrinsic_global_atomic_umax
:
4613 case nir_intrinsic_global_atomic_and
:
4614 case nir_intrinsic_global_atomic_or
:
4615 case nir_intrinsic_global_atomic_xor
:
4616 case nir_intrinsic_global_atomic_exchange
:
4617 case nir_intrinsic_global_atomic_comp_swap
:
4618 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4620 case nir_intrinsic_global_atomic_fmin
:
4621 case nir_intrinsic_global_atomic_fmax
:
4622 case nir_intrinsic_global_atomic_fcomp_swap
:
4623 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4626 case nir_intrinsic_load_ssbo
: {
4627 assert(devinfo
->gen
>= 7);
4629 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4630 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4631 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4632 get_nir_ssbo_intrinsic_index(bld
, instr
);
4633 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4634 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4636 /* Make dest unsigned because that's what the temporary will be */
4637 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4639 /* Read the vector */
4640 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4641 assert(nir_intrinsic_align(instr
) > 0);
4642 if (nir_dest_bit_size(instr
->dest
) == 32 &&
4643 nir_intrinsic_align(instr
) >= 4) {
4644 assert(nir_dest_num_components(instr
->dest
) <= 4);
4645 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4647 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4648 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4649 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4651 assert(nir_dest_num_components(instr
->dest
) == 1);
4652 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4654 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4655 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4656 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4657 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4662 case nir_intrinsic_store_ssbo
: {
4663 assert(devinfo
->gen
>= 7);
4665 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4666 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4667 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4668 get_nir_ssbo_intrinsic_index(bld
, instr
);
4669 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4670 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4672 fs_reg data
= get_nir_src(instr
->src
[0]);
4673 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4675 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4676 assert(nir_intrinsic_write_mask(instr
) ==
4677 (1u << instr
->num_components
) - 1);
4678 assert(nir_intrinsic_align(instr
) > 0);
4679 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4680 nir_intrinsic_align(instr
) >= 4) {
4681 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4682 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4683 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4684 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4685 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4687 assert(nir_src_num_components(instr
->src
[0]) == 1);
4688 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4690 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4691 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4693 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4694 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4699 case nir_intrinsic_store_output
: {
4700 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4701 fs_reg src
= get_nir_src(instr
->src
[0]);
4703 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4704 unsigned num_components
= instr
->num_components
;
4705 unsigned first_component
= nir_intrinsic_component(instr
);
4707 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4708 4 * store_offset
), src
.type
);
4709 for (unsigned j
= 0; j
< num_components
; j
++) {
4710 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4711 offset(src
, bld
, j
));
4716 case nir_intrinsic_ssbo_atomic_add
:
4717 case nir_intrinsic_ssbo_atomic_imin
:
4718 case nir_intrinsic_ssbo_atomic_umin
:
4719 case nir_intrinsic_ssbo_atomic_imax
:
4720 case nir_intrinsic_ssbo_atomic_umax
:
4721 case nir_intrinsic_ssbo_atomic_and
:
4722 case nir_intrinsic_ssbo_atomic_or
:
4723 case nir_intrinsic_ssbo_atomic_xor
:
4724 case nir_intrinsic_ssbo_atomic_exchange
:
4725 case nir_intrinsic_ssbo_atomic_comp_swap
:
4726 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4728 case nir_intrinsic_ssbo_atomic_fmin
:
4729 case nir_intrinsic_ssbo_atomic_fmax
:
4730 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4731 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4734 case nir_intrinsic_get_buffer_size
: {
4735 assert(nir_src_num_components(instr
->src
[0]) == 1);
4736 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4737 nir_src_as_uint(instr
->src
[0]) : 0;
4739 /* A resinfo's sampler message is used to get the buffer size. The
4740 * SIMD8's writeback message consists of four registers and SIMD16's
4741 * writeback message consists of 8 destination registers (two per each
4742 * component). Because we are only interested on the first channel of
4743 * the first returned component, where resinfo returns the buffer size
4744 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4745 * the dispatch width.
4747 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4748 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4749 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4752 ubld
.MOV(src_payload
, brw_imm_d(0));
4754 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4755 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4756 src_payload
, brw_imm_ud(index
));
4757 inst
->header_size
= 0;
4759 inst
->size_written
= 4 * REG_SIZE
;
4761 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4763 * "Out-of-bounds checking is always performed at a DWord granularity. If
4764 * any part of the DWord is out-of-bounds then the whole DWord is
4765 * considered out-of-bounds."
4767 * This implies that types with size smaller than 4-bytes need to be
4768 * padded if they don't complete the last dword of the buffer. But as we
4769 * need to maintain the original size we need to reverse the padding
4770 * calculation to return the correct size to know the number of elements
4771 * of an unsized array. As we stored in the last two bits of the surface
4772 * size the needed padding for the buffer, we calculate here the
4773 * original buffer_size reversing the surface_size calculation:
4775 * surface_size = isl_align(buffer_size, 4) +
4776 * (isl_align(buffer_size) - buffer_size)
4778 * buffer_size = surface_size & ~3 - surface_size & 3
4781 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4782 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4783 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4785 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4786 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4787 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4789 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4793 case nir_intrinsic_load_scratch
: {
4794 assert(devinfo
->gen
>= 7);
4796 assert(nir_dest_num_components(instr
->dest
) == 1);
4797 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4798 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4800 if (devinfo
->gen
>= 8) {
4801 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4802 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4804 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4807 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4808 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4809 const fs_reg nir_addr
= get_nir_src(instr
->src
[0]);
4811 /* Make dest unsigned because that's what the temporary will be */
4812 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4814 /* Read the vector */
4815 assert(nir_dest_num_components(instr
->dest
) == 1);
4816 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4817 assert(nir_intrinsic_align(instr
) > 1);
4818 if (nir_dest_bit_size(instr
->dest
) >= 4 &&
4819 nir_intrinsic_align(instr
) >= 4) {
4820 /* The offset for a DWORD scattered message is in dwords. */
4821 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4822 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4824 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL
,
4825 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4827 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4828 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4830 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4831 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4832 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4833 bld
.MOV(dest
, read_result
);
4838 case nir_intrinsic_store_scratch
: {
4839 assert(devinfo
->gen
>= 7);
4841 assert(nir_src_num_components(instr
->src
[0]) == 1);
4842 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4843 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4845 if (devinfo
->gen
>= 8) {
4846 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4847 brw_imm_ud(GEN8_BTI_STATELESS_NON_COHERENT
);
4849 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(BRW_BTI_STATELESS
);
4852 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4853 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4854 const fs_reg nir_addr
= get_nir_src(instr
->src
[1]);
4856 fs_reg data
= get_nir_src(instr
->src
[0]);
4857 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4859 assert(nir_src_num_components(instr
->src
[0]) == 1);
4860 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4861 assert(nir_intrinsic_write_mask(instr
) == 1);
4862 assert(nir_intrinsic_align(instr
) > 0);
4863 if (nir_src_bit_size(instr
->src
[0]) == 32 &&
4864 nir_intrinsic_align(instr
) >= 4) {
4865 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4867 /* The offset for a DWORD scattered message is in dwords. */
4868 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4869 swizzle_nir_scratch_addr(bld
, nir_addr
, true);
4871 bld
.emit(SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL
,
4872 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4874 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4875 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4877 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4878 swizzle_nir_scratch_addr(bld
, nir_addr
, false);
4880 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4881 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4886 case nir_intrinsic_load_subgroup_size
:
4887 /* This should only happen for fragment shaders because every other case
4888 * is lowered in NIR so we can optimize on it.
4890 assert(stage
== MESA_SHADER_FRAGMENT
);
4891 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4894 case nir_intrinsic_load_subgroup_invocation
:
4895 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4896 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4899 case nir_intrinsic_load_subgroup_eq_mask
:
4900 case nir_intrinsic_load_subgroup_ge_mask
:
4901 case nir_intrinsic_load_subgroup_gt_mask
:
4902 case nir_intrinsic_load_subgroup_le_mask
:
4903 case nir_intrinsic_load_subgroup_lt_mask
:
4904 unreachable("not reached");
4906 case nir_intrinsic_vote_any
: {
4907 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4909 /* The any/all predicates do not consider channel enables. To prevent
4910 * dead channels from affecting the result, we initialize the flag with
4911 * with the identity value for the logical operation.
4913 if (dispatch_width
== 32) {
4914 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4915 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4918 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4920 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4922 /* For some reason, the any/all predicates don't work properly with
4923 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4924 * doesn't read the correct subset of the flag register and you end up
4925 * getting garbage in the second half. Work around this by using a pair
4926 * of 1-wide MOVs and scattering the result.
4928 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4929 ubld
.MOV(res1
, brw_imm_d(0));
4930 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4931 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4932 BRW_PREDICATE_ALIGN1_ANY32H
,
4933 ubld
.MOV(res1
, brw_imm_d(-1)));
4935 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4938 case nir_intrinsic_vote_all
: {
4939 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4941 /* The any/all predicates do not consider channel enables. To prevent
4942 * dead channels from affecting the result, we initialize the flag with
4943 * with the identity value for the logical operation.
4945 if (dispatch_width
== 32) {
4946 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4947 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4948 brw_imm_ud(0xffffffff));
4950 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4952 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4954 /* For some reason, the any/all predicates don't work properly with
4955 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4956 * doesn't read the correct subset of the flag register and you end up
4957 * getting garbage in the second half. Work around this by using a pair
4958 * of 1-wide MOVs and scattering the result.
4960 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4961 ubld
.MOV(res1
, brw_imm_d(0));
4962 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4963 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4964 BRW_PREDICATE_ALIGN1_ALL32H
,
4965 ubld
.MOV(res1
, brw_imm_d(-1)));
4967 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4970 case nir_intrinsic_vote_feq
:
4971 case nir_intrinsic_vote_ieq
: {
4972 fs_reg value
= get_nir_src(instr
->src
[0]);
4973 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4974 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4975 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4976 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4979 fs_reg uniformized
= bld
.emit_uniformize(value
);
4980 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4982 /* The any/all predicates do not consider channel enables. To prevent
4983 * dead channels from affecting the result, we initialize the flag with
4984 * with the identity value for the logical operation.
4986 if (dispatch_width
== 32) {
4987 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4988 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4989 brw_imm_ud(0xffffffff));
4991 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4993 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4995 /* For some reason, the any/all predicates don't work properly with
4996 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4997 * doesn't read the correct subset of the flag register and you end up
4998 * getting garbage in the second half. Work around this by using a pair
4999 * of 1-wide MOVs and scattering the result.
5001 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
5002 ubld
.MOV(res1
, brw_imm_d(0));
5003 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
5004 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
5005 BRW_PREDICATE_ALIGN1_ALL32H
,
5006 ubld
.MOV(res1
, brw_imm_d(-1)));
5008 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
5012 case nir_intrinsic_ballot
: {
5013 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
5014 BRW_REGISTER_TYPE_UD
);
5015 struct brw_reg flag
= brw_flag_reg(0, 0);
5016 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
5017 * as f0.0. This is a problem for fragment programs as we currently use
5018 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
5019 * programs yet so this isn't a problem. When we do, something will
5022 if (dispatch_width
== 32)
5023 flag
.type
= BRW_REGISTER_TYPE_UD
;
5025 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
5026 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
5028 if (instr
->dest
.ssa
.bit_size
> 32) {
5029 dest
.type
= BRW_REGISTER_TYPE_UQ
;
5031 dest
.type
= BRW_REGISTER_TYPE_UD
;
5033 bld
.MOV(dest
, flag
);
5037 case nir_intrinsic_read_invocation
: {
5038 const fs_reg value
= get_nir_src(instr
->src
[0]);
5039 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
5040 fs_reg tmp
= bld
.vgrf(value
.type
);
5042 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
5043 bld
.emit_uniformize(invocation
));
5045 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
5049 case nir_intrinsic_read_first_invocation
: {
5050 const fs_reg value
= get_nir_src(instr
->src
[0]);
5051 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
5055 case nir_intrinsic_shuffle
: {
5056 const fs_reg value
= get_nir_src(instr
->src
[0]);
5057 const fs_reg index
= get_nir_src(instr
->src
[1]);
5059 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
5063 case nir_intrinsic_first_invocation
: {
5064 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
5065 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
5066 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
5067 fs_reg(component(tmp
, 0)));
5071 case nir_intrinsic_quad_broadcast
: {
5072 const fs_reg value
= get_nir_src(instr
->src
[0]);
5073 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
5075 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
5076 value
, brw_imm_ud(index
), brw_imm_ud(4));
5080 case nir_intrinsic_quad_swap_horizontal
: {
5081 const fs_reg value
= get_nir_src(instr
->src
[0]);
5082 const fs_reg tmp
= bld
.vgrf(value
.type
);
5083 if (devinfo
->gen
<= 7) {
5084 /* The hardware doesn't seem to support these crazy regions with
5085 * compressed instructions on gen7 and earlier so we fall back to
5086 * using quad swizzles. Fortunately, we don't support 64-bit
5087 * anything in Vulkan on gen7.
5089 assert(nir_src_bit_size(instr
->src
[0]) == 32);
5090 const fs_builder ubld
= bld
.exec_all();
5091 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5092 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
5093 bld
.MOV(retype(dest
, value
.type
), tmp
);
5095 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
5097 const fs_reg src_left
= horiz_stride(value
, 2);
5098 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
5099 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
5100 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
5102 ubld
.MOV(tmp_left
, src_right
);
5103 ubld
.MOV(tmp_right
, src_left
);
5106 bld
.MOV(retype(dest
, value
.type
), tmp
);
5110 case nir_intrinsic_quad_swap_vertical
: {
5111 const fs_reg value
= get_nir_src(instr
->src
[0]);
5112 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5113 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5114 const fs_reg tmp
= bld
.vgrf(value
.type
);
5115 const fs_builder ubld
= bld
.exec_all();
5116 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5117 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
5118 bld
.MOV(retype(dest
, value
.type
), tmp
);
5120 /* For larger data types, we have to either emit dispatch_width many
5121 * MOVs or else fall back to doing indirects.
5123 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5124 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5126 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5131 case nir_intrinsic_quad_swap_diagonal
: {
5132 const fs_reg value
= get_nir_src(instr
->src
[0]);
5133 if (nir_src_bit_size(instr
->src
[0]) == 32) {
5134 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
5135 const fs_reg tmp
= bld
.vgrf(value
.type
);
5136 const fs_builder ubld
= bld
.exec_all();
5137 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
5138 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
5139 bld
.MOV(retype(dest
, value
.type
), tmp
);
5141 /* For larger data types, we have to either emit dispatch_width many
5142 * MOVs or else fall back to doing indirects.
5144 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5145 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5147 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
5152 case nir_intrinsic_reduce
: {
5153 fs_reg src
= get_nir_src(instr
->src
[0]);
5154 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5155 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
5156 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
5157 cluster_size
= dispatch_width
;
5159 /* Figure out the source type */
5160 src
.type
= brw_type_for_nir_type(devinfo
,
5161 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5162 nir_src_bit_size(instr
->src
[0])));
5164 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5165 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5166 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5168 /* There are a couple of register region issues that make things
5169 * complicated for 8-bit types:
5171 * 1. Only raw moves are allowed to write to a packed 8-bit
5173 * 2. If we use a strided destination, the efficient way to do scan
5174 * operations ends up using strides that are too big to encode in
5177 * To get around these issues, we just do all 8-bit scan operations in
5178 * 16 bits. It's actually fewer instructions than what we'd have to do
5179 * if we were trying to do it in native 8-bit types and the results are
5180 * the same once we truncate to 8 bits at the end.
5182 brw_reg_type scan_type
= src
.type
;
5183 if (type_sz(scan_type
) == 1)
5184 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5186 /* Set up a register for all of our scratching around and initialize it
5187 * to reduction operation's identity value.
5189 fs_reg scan
= bld
.vgrf(scan_type
);
5190 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5192 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
5194 dest
.type
= src
.type
;
5195 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
5196 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
5197 * the distance between clusters is at least 2 GRFs. In this case,
5198 * we don't need the weird striding of the CLUSTER_BROADCAST
5199 * instruction and can just do regular MOVs.
5201 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5202 const unsigned groups
=
5203 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5204 const unsigned group_size
= dispatch_width
/ groups
;
5205 for (unsigned i
= 0; i
< groups
; i
++) {
5206 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5207 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5208 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5209 component(scan
, comp
));
5212 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5213 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5218 case nir_intrinsic_inclusive_scan
:
5219 case nir_intrinsic_exclusive_scan
: {
5220 fs_reg src
= get_nir_src(instr
->src
[0]);
5221 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5223 /* Figure out the source type */
5224 src
.type
= brw_type_for_nir_type(devinfo
,
5225 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5226 nir_src_bit_size(instr
->src
[0])));
5228 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5229 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5230 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5232 /* There are a couple of register region issues that make things
5233 * complicated for 8-bit types:
5235 * 1. Only raw moves are allowed to write to a packed 8-bit
5237 * 2. If we use a strided destination, the efficient way to do scan
5238 * operations ends up using strides that are too big to encode in
5241 * To get around these issues, we just do all 8-bit scan operations in
5242 * 16 bits. It's actually fewer instructions than what we'd have to do
5243 * if we were trying to do it in native 8-bit types and the results are
5244 * the same once we truncate to 8 bits at the end.
5246 brw_reg_type scan_type
= src
.type
;
5247 if (type_sz(scan_type
) == 1)
5248 scan_type
= brw_reg_type_from_bit_size(16, src
.type
);
5250 /* Set up a register for all of our scratching around and initialize it
5251 * to reduction operation's identity value.
5253 fs_reg scan
= bld
.vgrf(scan_type
);
5254 const fs_builder allbld
= bld
.exec_all();
5255 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5257 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5258 /* Exclusive scan is a bit harder because we have to do an annoying
5259 * shift of the contents before we can begin. To make things worse,
5260 * we can't do this with a normal stride; we have to use indirects.
5262 fs_reg shifted
= bld
.vgrf(scan_type
);
5263 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5264 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5266 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5267 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5271 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5273 bld
.MOV(retype(dest
, src
.type
), scan
);
5278 unreachable("unknown intrinsic");
5283 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5284 int op
, nir_intrinsic_instr
*instr
)
5286 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5287 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5288 * appear to exist. However, if you look at Vol 2a, there are no message
5289 * descriptors provided for Qword atomic ops except for A64 messages.
5291 assert(nir_dest_bit_size(instr
->dest
) == 32);
5294 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5295 dest
= get_nir_dest(instr
->dest
);
5297 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5298 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5299 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5300 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5301 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5304 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5305 data
= get_nir_src(instr
->src
[2]);
5307 if (op
== BRW_AOP_CMPWR
) {
5308 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5309 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5310 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5313 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5315 /* Emit the actual atomic operation */
5317 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5318 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5322 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5323 int op
, nir_intrinsic_instr
*instr
)
5326 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5327 dest
= get_nir_dest(instr
->dest
);
5329 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5330 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5331 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5332 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5333 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5335 fs_reg data
= get_nir_src(instr
->src
[2]);
5336 if (op
== BRW_AOP_FCMPWR
) {
5337 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5338 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5339 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5342 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5344 /* Emit the actual atomic operation */
5346 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5347 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5351 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5352 int op
, nir_intrinsic_instr
*instr
)
5355 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5356 dest
= get_nir_dest(instr
->dest
);
5358 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5359 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5360 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5361 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5364 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5365 data
= get_nir_src(instr
->src
[1]);
5366 if (op
== BRW_AOP_CMPWR
) {
5367 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5368 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5369 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5372 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5374 /* Get the offset */
5375 if (nir_src_is_const(instr
->src
[0])) {
5376 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5377 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5379 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5380 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5381 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5382 brw_imm_ud(instr
->const_index
[0]));
5385 /* Emit the actual atomic operation operation */
5387 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5388 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5392 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5393 int op
, nir_intrinsic_instr
*instr
)
5396 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5397 dest
= get_nir_dest(instr
->dest
);
5399 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5400 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5401 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5402 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5404 fs_reg data
= get_nir_src(instr
->src
[1]);
5405 if (op
== BRW_AOP_FCMPWR
) {
5406 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5407 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5408 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5411 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5413 /* Get the offset */
5414 if (nir_src_is_const(instr
->src
[0])) {
5415 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5416 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5418 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5419 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5420 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5421 brw_imm_ud(instr
->const_index
[0]));
5424 /* Emit the actual atomic operation operation */
5426 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5427 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5431 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5432 int op
, nir_intrinsic_instr
*instr
)
5435 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5436 dest
= get_nir_dest(instr
->dest
);
5438 fs_reg addr
= get_nir_src(instr
->src
[0]);
5441 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5442 data
= get_nir_src(instr
->src
[1]);
5444 if (op
== BRW_AOP_CMPWR
) {
5445 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5446 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5447 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5451 if (nir_dest_bit_size(instr
->dest
) == 64) {
5452 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5453 dest
, addr
, data
, brw_imm_ud(op
));
5455 assert(nir_dest_bit_size(instr
->dest
) == 32);
5456 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5457 dest
, addr
, data
, brw_imm_ud(op
));
5462 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5463 int op
, nir_intrinsic_instr
*instr
)
5465 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5466 fs_reg dest
= get_nir_dest(instr
->dest
);
5468 fs_reg addr
= get_nir_src(instr
->src
[0]);
5470 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5471 fs_reg data
= get_nir_src(instr
->src
[1]);
5473 if (op
== BRW_AOP_FCMPWR
) {
5474 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5475 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5476 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5480 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5481 dest
, addr
, data
, brw_imm_ud(op
));
5485 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5487 unsigned texture
= instr
->texture_index
;
5488 unsigned sampler
= instr
->sampler_index
;
5490 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5492 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5493 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5495 int lod_components
= 0;
5497 /* The hardware requires a LOD for buffer textures */
5498 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5499 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5501 uint32_t header_bits
= 0;
5502 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5503 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5504 switch (instr
->src
[i
].src_type
) {
5505 case nir_tex_src_bias
:
5506 srcs
[TEX_LOGICAL_SRC_LOD
] =
5507 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5509 case nir_tex_src_comparator
:
5510 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5512 case nir_tex_src_coord
:
5513 switch (instr
->op
) {
5515 case nir_texop_txf_ms
:
5516 case nir_texop_txf_ms_mcs
:
5517 case nir_texop_samples_identical
:
5518 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5521 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5525 case nir_tex_src_ddx
:
5526 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5527 lod_components
= nir_tex_instr_src_size(instr
, i
);
5529 case nir_tex_src_ddy
:
5530 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5532 case nir_tex_src_lod
:
5533 switch (instr
->op
) {
5535 srcs
[TEX_LOGICAL_SRC_LOD
] =
5536 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5539 srcs
[TEX_LOGICAL_SRC_LOD
] =
5540 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5543 srcs
[TEX_LOGICAL_SRC_LOD
] =
5544 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5548 case nir_tex_src_min_lod
:
5549 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5550 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5552 case nir_tex_src_ms_index
:
5553 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5556 case nir_tex_src_offset
: {
5557 uint32_t offset_bits
= 0;
5558 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5559 header_bits
|= offset_bits
;
5561 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5562 retype(src
, BRW_REGISTER_TYPE_D
);
5567 case nir_tex_src_projector
:
5568 unreachable("should be lowered");
5570 case nir_tex_src_texture_offset
: {
5571 /* Emit code to evaluate the actual indexing expression */
5572 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5573 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5574 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5578 case nir_tex_src_sampler_offset
: {
5579 /* Emit code to evaluate the actual indexing expression */
5580 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5581 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5582 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5586 case nir_tex_src_texture_handle
:
5587 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5588 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5589 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5592 case nir_tex_src_sampler_handle
:
5593 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5594 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5595 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5598 case nir_tex_src_ms_mcs
:
5599 assert(instr
->op
== nir_texop_txf_ms
);
5600 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5603 case nir_tex_src_plane
: {
5604 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5605 const uint32_t texture_index
=
5606 instr
->texture_index
+
5607 stage_prog_data
->binding_table
.plane_start
[plane
] -
5608 stage_prog_data
->binding_table
.texture_start
;
5610 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5615 unreachable("unknown texture source");
5619 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5620 (instr
->op
== nir_texop_txf_ms
||
5621 instr
->op
== nir_texop_samples_identical
)) {
5622 if (devinfo
->gen
>= 7 &&
5623 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5624 srcs
[TEX_LOGICAL_SRC_MCS
] =
5625 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5626 instr
->coord_components
,
5627 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5628 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5630 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5634 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5635 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5638 switch (instr
->op
) {
5640 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5643 opcode
= FS_OPCODE_TXB_LOGICAL
;
5646 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5649 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5652 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5654 case nir_texop_txf_ms
:
5655 if ((key_tex
->msaa_16
& (1 << sampler
)))
5656 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5658 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5660 case nir_texop_txf_ms_mcs
:
5661 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5663 case nir_texop_query_levels
:
5665 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5668 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5671 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5672 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5674 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5676 case nir_texop_texture_samples
:
5677 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5679 case nir_texop_samples_identical
: {
5680 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5682 /* If mcs is an immediate value, it means there is no MCS. In that case
5683 * just return false.
5685 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5686 bld
.MOV(dst
, brw_imm_ud(0u));
5687 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5688 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5689 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5690 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5691 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5693 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5694 BRW_CONDITIONAL_EQ
);
5699 unreachable("unknown texture opcode");
5702 if (instr
->op
== nir_texop_tg4
) {
5703 if (instr
->component
== 1 &&
5704 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5705 /* gather4 sampler is broken for green channel on RG32F --
5706 * we must ask for blue instead.
5708 header_bits
|= 2 << 16;
5710 header_bits
|= instr
->component
<< 16;
5714 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5715 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5716 inst
->offset
= header_bits
;
5718 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5719 if (devinfo
->gen
>= 9 &&
5720 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5721 unsigned write_mask
= instr
->dest
.is_ssa
?
5722 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5723 (1 << dest_size
) - 1;
5724 assert(write_mask
!= 0); /* dead code should have been eliminated */
5725 inst
->size_written
= util_last_bit(write_mask
) *
5726 inst
->dst
.component_size(inst
->exec_size
);
5728 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5731 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5732 inst
->shadow_compare
= true;
5734 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5735 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5738 for (unsigned i
= 0; i
< dest_size
; i
++)
5739 nir_dest
[i
] = offset(dst
, bld
, i
);
5741 if (instr
->op
== nir_texop_query_levels
) {
5742 /* # levels is in .w */
5743 nir_dest
[0] = offset(dst
, bld
, 3);
5744 } else if (instr
->op
== nir_texop_txs
&&
5745 dest_size
>= 3 && devinfo
->gen
< 7) {
5746 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5747 fs_reg depth
= offset(dst
, bld
, 2);
5748 nir_dest
[2] = vgrf(glsl_type::int_type
);
5749 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5752 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5756 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5758 switch (instr
->type
) {
5759 case nir_jump_break
:
5760 bld
.emit(BRW_OPCODE_BREAK
);
5762 case nir_jump_continue
:
5763 bld
.emit(BRW_OPCODE_CONTINUE
);
5765 case nir_jump_return
:
5767 unreachable("unknown jump");
5772 * This helper takes a source register and un/shuffles it into the destination
5775 * If source type size is smaller than destination type size the operation
5776 * needed is a component shuffle. The opposite case would be an unshuffle. If
5777 * source/destination type size is equal a shuffle is done that would be
5778 * equivalent to a simple MOV.
5780 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5781 * components .xyz 16-bit vector on SIMD8 would be.
5783 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5784 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5786 * This helper will return the following 2 32-bit components with the 16-bit
5789 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5790 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5792 * For unshuffle, the example would be the opposite, a 64-bit type source
5793 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5796 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5797 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5798 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5799 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5801 * The returned result would be the following 4 32-bit components unshuffled:
5803 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5804 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5805 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5806 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5808 * - Source and destination register must not be overlapped.
5809 * - components units are measured in terms of the smaller type between
5810 * source and destination because we are un/shuffling the smaller
5811 * components from/into the bigger ones.
5812 * - first_component parameter allows skipping source components.
5815 shuffle_src_to_dst(const fs_builder
&bld
,
5818 uint32_t first_component
,
5819 uint32_t components
)
5821 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5822 assert(!regions_overlap(dst
,
5823 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5824 offset(src
, bld
, first_component
),
5825 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5826 for (unsigned i
= 0; i
< components
; i
++) {
5827 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5828 offset(src
, bld
, i
+ first_component
));
5830 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5831 /* Source is shuffled into destination */
5832 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5833 assert(!regions_overlap(dst
,
5834 type_sz(dst
.type
) * bld
.dispatch_width() *
5835 DIV_ROUND_UP(components
, size_ratio
),
5836 offset(src
, bld
, first_component
),
5837 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5839 brw_reg_type shuffle_type
=
5840 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5841 BRW_REGISTER_TYPE_D
);
5842 for (unsigned i
= 0; i
< components
; i
++) {
5843 fs_reg shuffle_component_i
=
5844 subscript(offset(dst
, bld
, i
/ size_ratio
),
5845 shuffle_type
, i
% size_ratio
);
5846 bld
.MOV(shuffle_component_i
,
5847 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5850 /* Source is unshuffled into destination */
5851 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5852 assert(!regions_overlap(dst
,
5853 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5854 offset(src
, bld
, first_component
/ size_ratio
),
5855 type_sz(src
.type
) * bld
.dispatch_width() *
5856 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5859 brw_reg_type shuffle_type
=
5860 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5861 BRW_REGISTER_TYPE_D
);
5862 for (unsigned i
= 0; i
< components
; i
++) {
5863 fs_reg shuffle_component_i
=
5864 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5865 shuffle_type
, (first_component
+ i
) % size_ratio
);
5866 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5867 shuffle_component_i
);
5873 shuffle_from_32bit_read(const fs_builder
&bld
,
5876 uint32_t first_component
,
5877 uint32_t components
)
5879 assert(type_sz(src
.type
) == 4);
5881 /* This function takes components in units of the destination type while
5882 * shuffle_src_to_dst takes components in units of the smallest type
5884 if (type_sz(dst
.type
) > 4) {
5885 assert(type_sz(dst
.type
) == 8);
5886 first_component
*= 2;
5890 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5894 setup_imm_df(const fs_builder
&bld
, double v
)
5896 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5897 assert(devinfo
->gen
>= 7);
5899 if (devinfo
->gen
>= 8)
5900 return brw_imm_df(v
);
5902 /* gen7.5 does not support DF immediates straighforward but the DIM
5903 * instruction allows to set the 64-bit immediate value.
5905 if (devinfo
->is_haswell
) {
5906 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5907 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5908 ubld
.DIM(dst
, brw_imm_df(v
));
5909 return component(dst
, 0);
5912 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5913 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5914 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5916 * Alternatively, we could also produce a normal VGRF (without stride 0)
5917 * by writing to all the channels in the VGRF, however, that would hit the
5918 * gen7 bug where we have to split writes that span more than 1 register
5919 * into instructions with a width of 4 (otherwise the write to the second
5920 * register written runs into an execmask hardware bug) which isn't very
5933 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5934 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5935 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5936 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5938 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5942 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5944 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5945 bld
.MOV(tmp
, brw_imm_w(v
));
5950 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5952 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5953 bld
.MOV(tmp
, brw_imm_uw(v
));