2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "util/u_math.h"
28 #include "util/bitscan.h"
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
46 fs_visitor::nir_setup_outputs()
48 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
51 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
53 /* Calculate the size of output registers in a separate pass, before
54 * allocating them. With ARB_enhanced_layouts, multiple output variables
55 * may occupy the same slot, but have different type sizes.
57 nir_foreach_variable(var
, &nir
->outputs
) {
58 const int loc
= var
->data
.driver_location
;
59 const unsigned var_vec4s
=
60 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
61 : type_size_vec4(var
->type
, true);
62 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
65 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
66 if (vec4s
[loc
] == 0) {
71 unsigned reg_size
= vec4s
[loc
];
73 /* Check if there are any ranges that start within this range and extend
74 * past it. If so, include them in this allocation.
76 for (unsigned i
= 1; i
< reg_size
; i
++)
77 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
79 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
80 for (unsigned i
= 0; i
< reg_size
; i
++)
81 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
88 fs_visitor::nir_setup_uniforms()
90 /* Only the first compile gets to set up uniforms. */
91 if (push_constant_loc
) {
92 assert(pull_constant_loc
);
96 uniforms
= nir
->num_uniforms
/ 4;
98 if (stage
== MESA_SHADER_COMPUTE
) {
99 /* Add a uniform for the thread local id. It must be the last uniform
102 assert(uniforms
== prog_data
->nr_params
);
103 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
104 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
105 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
110 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
114 nir_foreach_instr(instr
, block
) {
115 if (instr
->type
!= nir_instr_type_intrinsic
)
118 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
119 switch (intrin
->intrinsic
) {
120 case nir_intrinsic_load_vertex_id
:
121 case nir_intrinsic_load_base_vertex
:
122 unreachable("should be lowered by nir_lower_system_values().");
124 case nir_intrinsic_load_vertex_id_zero_base
:
125 case nir_intrinsic_load_is_indexed_draw
:
126 case nir_intrinsic_load_first_vertex
:
127 case nir_intrinsic_load_instance_id
:
128 case nir_intrinsic_load_base_instance
:
129 case nir_intrinsic_load_draw_id
:
130 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
132 case nir_intrinsic_load_invocation_id
:
133 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
135 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
136 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
137 if (reg
->file
== BAD_FILE
) {
138 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
139 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
140 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
141 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
146 case nir_intrinsic_load_sample_pos
:
147 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
148 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
149 if (reg
->file
== BAD_FILE
)
150 *reg
= *v
->emit_samplepos_setup();
153 case nir_intrinsic_load_sample_id
:
154 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_sampleid_setup();
160 case nir_intrinsic_load_sample_mask_in
:
161 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
162 assert(v
->devinfo
->gen
>= 7);
163 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
164 if (reg
->file
== BAD_FILE
)
165 *reg
= *v
->emit_samplemaskin_setup();
168 case nir_intrinsic_load_work_group_id
:
169 assert(v
->stage
== MESA_SHADER_COMPUTE
);
170 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
171 if (reg
->file
== BAD_FILE
)
172 *reg
= *v
->emit_cs_work_group_id_setup();
175 case nir_intrinsic_load_helper_invocation
:
176 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
177 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
178 if (reg
->file
== BAD_FILE
) {
179 const fs_builder abld
=
180 v
->bld
.annotate("gl_HelperInvocation", NULL
);
182 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
183 * pixel mask is in g1.7 of the thread payload.
185 * We move the per-channel pixel enable bit to the low bit of each
186 * channel by shifting the byte containing the pixel mask by the
187 * vector immediate 0x76543210UV.
189 * The region of <1,8,0> reads only 1 byte (the pixel masks for
190 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
191 * masks for 2 and 3) in SIMD16.
193 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
195 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
196 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
197 hbld
.SHR(offset(shifted
, hbld
, i
),
198 stride(retype(brw_vec1_grf(1 + i
, 7),
199 BRW_REGISTER_TYPE_UB
),
201 brw_imm_v(0x76543210));
204 /* A set bit in the pixel mask means the channel is enabled, but
205 * that is the opposite of gl_HelperInvocation so we need to invert
208 * The negate source-modifier bit of logical instructions on Gen8+
209 * performs 1's complement negation, so we can use that instead of
212 fs_reg inverted
= negate(shifted
);
213 if (v
->devinfo
->gen
< 8) {
214 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
215 abld
.NOT(inverted
, shifted
);
218 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
219 * with 1 and negating.
221 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
222 abld
.AND(anded
, inverted
, brw_imm_uw(1));
224 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
225 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
239 fs_visitor::nir_emit_system_values()
241 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
242 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
243 nir_system_values
[i
] = fs_reg();
246 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
247 * never end up using it.
250 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
251 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
252 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
254 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
255 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
256 if (dispatch_width
> 8)
257 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
258 if (dispatch_width
> 16) {
259 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
260 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
264 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
265 nir_foreach_block(block
, impl
)
266 emit_system_values_block(block
, this);
270 * Returns a type based on a reference_type (word, float, half-float) and a
273 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
275 * @FIXME: 64-bit return types are always DF on integer types to maintain
276 * compability with uses of DF previously to the introduction of int64
280 brw_reg_type_from_bit_size(const unsigned bit_size
,
281 const brw_reg_type reference_type
)
283 switch(reference_type
) {
284 case BRW_REGISTER_TYPE_HF
:
285 case BRW_REGISTER_TYPE_F
:
286 case BRW_REGISTER_TYPE_DF
:
289 return BRW_REGISTER_TYPE_HF
;
291 return BRW_REGISTER_TYPE_F
;
293 return BRW_REGISTER_TYPE_DF
;
295 unreachable("Invalid bit size");
297 case BRW_REGISTER_TYPE_B
:
298 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_D
:
300 case BRW_REGISTER_TYPE_Q
:
303 return BRW_REGISTER_TYPE_B
;
305 return BRW_REGISTER_TYPE_W
;
307 return BRW_REGISTER_TYPE_D
;
309 return BRW_REGISTER_TYPE_Q
;
311 unreachable("Invalid bit size");
313 case BRW_REGISTER_TYPE_UB
:
314 case BRW_REGISTER_TYPE_UW
:
315 case BRW_REGISTER_TYPE_UD
:
316 case BRW_REGISTER_TYPE_UQ
:
319 return BRW_REGISTER_TYPE_UB
;
321 return BRW_REGISTER_TYPE_UW
;
323 return BRW_REGISTER_TYPE_UD
;
325 return BRW_REGISTER_TYPE_UQ
;
327 unreachable("Invalid bit size");
330 unreachable("Unknown type");
335 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
337 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
338 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
339 nir_locals
[i
] = fs_reg();
342 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
343 unsigned array_elems
=
344 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
345 unsigned size
= array_elems
* reg
->num_components
;
346 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
347 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
348 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
351 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
354 nir_emit_cf_list(&impl
->body
);
358 fs_visitor::nir_emit_cf_list(exec_list
*list
)
360 exec_list_validate(list
);
361 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
362 switch (node
->type
) {
364 nir_emit_if(nir_cf_node_as_if(node
));
367 case nir_cf_node_loop
:
368 nir_emit_loop(nir_cf_node_as_loop(node
));
371 case nir_cf_node_block
:
372 nir_emit_block(nir_cf_node_as_block(node
));
376 unreachable("Invalid CFG node block");
382 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
387 /* If the condition has the form !other_condition, use other_condition as
388 * the source, but invert the predicate on the if instruction.
390 nir_alu_instr
*const cond
= nir_src_as_alu_instr(&if_stmt
->condition
);
391 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
392 assert(!cond
->src
[0].negate
);
393 assert(!cond
->src
[0].abs
);
396 cond_reg
= get_nir_src(cond
->src
[0].src
);
399 cond_reg
= get_nir_src(if_stmt
->condition
);
402 /* first, put the condition into f0 */
403 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
404 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
405 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
407 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
409 nir_emit_cf_list(&if_stmt
->then_list
);
411 /* note: if the else is empty, dead CF elimination will remove it */
412 bld
.emit(BRW_OPCODE_ELSE
);
414 nir_emit_cf_list(&if_stmt
->else_list
);
416 bld
.emit(BRW_OPCODE_ENDIF
);
418 if (devinfo
->gen
< 7)
419 limit_dispatch_width(16, "Non-uniform control flow unsupported "
424 fs_visitor::nir_emit_loop(nir_loop
*loop
)
426 bld
.emit(BRW_OPCODE_DO
);
428 nir_emit_cf_list(&loop
->body
);
430 bld
.emit(BRW_OPCODE_WHILE
);
432 if (devinfo
->gen
< 7)
433 limit_dispatch_width(16, "Non-uniform control flow unsupported "
438 fs_visitor::nir_emit_block(nir_block
*block
)
440 nir_foreach_instr(instr
, block
) {
441 nir_emit_instr(instr
);
446 fs_visitor::nir_emit_instr(nir_instr
*instr
)
448 const fs_builder abld
= bld
.annotate(NULL
, instr
);
450 switch (instr
->type
) {
451 case nir_instr_type_alu
:
452 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
455 case nir_instr_type_deref
:
456 /* Derefs can exist for images but they do nothing */
459 case nir_instr_type_intrinsic
:
461 case MESA_SHADER_VERTEX
:
462 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
464 case MESA_SHADER_TESS_CTRL
:
465 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
467 case MESA_SHADER_TESS_EVAL
:
468 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
470 case MESA_SHADER_GEOMETRY
:
471 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
473 case MESA_SHADER_FRAGMENT
:
474 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
476 case MESA_SHADER_COMPUTE
:
477 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
480 unreachable("unsupported shader stage");
484 case nir_instr_type_tex
:
485 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
488 case nir_instr_type_load_const
:
489 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
492 case nir_instr_type_ssa_undef
:
493 /* We create a new VGRF for undefs on every use (by handling
494 * them in get_nir_src()), rather than for each definition.
495 * This helps register coalescing eliminate MOVs from undef.
499 case nir_instr_type_jump
:
500 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
504 unreachable("unknown instruction type");
509 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
513 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
514 const fs_reg
&result
)
516 if (!instr
->src
[0].src
.is_ssa
||
517 !instr
->src
[0].src
.ssa
->parent_instr
)
520 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
523 nir_alu_instr
*src0
=
524 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
526 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
527 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
530 /* If either opcode has source modifiers, bail.
532 * TODO: We can potentially handle source modifiers if both of the opcodes
533 * we're combining are signed integers.
535 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
536 src0
->src
[0].abs
|| src0
->src
[0].negate
)
539 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
541 /* Element type to extract.*/
542 const brw_reg_type type
= brw_int_type(
543 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
544 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
546 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
547 op0
.type
= brw_type_for_nir_type(devinfo
,
548 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
549 nir_src_bit_size(src0
->src
[0].src
)));
550 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
552 set_saturate(instr
->dest
.saturate
,
553 bld
.MOV(result
, subscript(op0
, type
, element
)));
558 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
559 const fs_reg
&result
)
561 if (!instr
->src
[0].src
.is_ssa
||
562 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
565 nir_intrinsic_instr
*src0
=
566 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
568 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
571 if (!nir_src_is_const(instr
->src
[1].src
) ||
572 !nir_src_is_const(instr
->src
[2].src
))
575 const float value1
= nir_src_as_float(instr
->src
[1].src
);
576 const float value2
= nir_src_as_float(instr
->src
[2].src
);
577 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
580 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
581 assert(value1
== -value2
);
583 fs_reg tmp
= vgrf(glsl_type::int_type
);
585 if (devinfo
->gen
>= 6) {
586 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
587 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
589 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
591 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
592 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
594 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
596 * This negation looks like it's safe in practice, because bits 0:4 will
597 * surely be TRIANGLES
600 if (value1
== -1.0f
) {
604 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
605 g0
, brw_imm_uw(0x3f80));
607 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
608 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
610 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
612 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
613 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
615 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
617 * This negation looks like it's safe in practice, because bits 0:4 will
618 * surely be TRIANGLES
621 if (value1
== -1.0f
) {
625 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
627 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
633 emit_find_msb_using_lzd(const fs_builder
&bld
,
634 const fs_reg
&result
,
642 /* LZD of an absolute value source almost always does the right
643 * thing. There are two problem values:
645 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
646 * 0. However, findMSB(int(0x80000000)) == 30.
648 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
649 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
651 * For a value of zero or negative one, -1 will be returned.
653 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
654 * findMSB(-(1<<x)) should return x-1.
656 * For all negative number cases, including 0x80000000 and
657 * 0xffffffff, the correct value is obtained from LZD if instead of
658 * negating the (already negative) value the logical-not is used. A
659 * conditonal logical-not can be achieved in two instructions.
661 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
663 bld
.ASR(temp
, src
, brw_imm_d(31));
664 bld
.XOR(temp
, temp
, src
);
667 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
668 retype(temp
, BRW_REGISTER_TYPE_UD
));
670 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
671 * from the LSB side. Subtract the result from 31 to convert the MSB
672 * count into an LSB count. If no bits are set, LZD will return 32.
673 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
675 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
676 inst
->src
[0].negate
= true;
680 brw_rnd_mode_from_nir_op (const nir_op op
) {
682 case nir_op_f2f16_rtz
:
683 return BRW_RND_MODE_RTZ
;
684 case nir_op_f2f16_rtne
:
685 return BRW_RND_MODE_RTNE
;
687 unreachable("Operation doesn't support rounding mode");
692 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
693 nir_alu_instr
*instr
,
698 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
700 result
.type
= brw_type_for_nir_type(devinfo
,
701 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
702 nir_dest_bit_size(instr
->dest
.dest
)));
704 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
705 op
[i
] = get_nir_src(instr
->src
[i
].src
);
706 op
[i
].type
= brw_type_for_nir_type(devinfo
,
707 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
708 nir_src_bit_size(instr
->src
[i
].src
)));
709 op
[i
].abs
= instr
->src
[i
].abs
;
710 op
[i
].negate
= instr
->src
[i
].negate
;
713 /* Move and vecN instrutions may still be vectored. Return the raw,
714 * vectored source and destination so that fs_visitor::nir_emit_alu can
715 * handle it. Other callers should not have to handle these kinds of
729 /* At this point, we have dealt with any instruction that operates on
730 * more than a single channel. Therefore, we can just adjust the source
731 * and destination registers for that channel and emit the instruction.
733 unsigned channel
= 0;
734 if (nir_op_infos
[instr
->op
].output_size
== 0) {
735 /* Since NIR is doing the scalarizing for us, we should only ever see
736 * vectorized operations with a single channel.
738 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
739 channel
= ffs(instr
->dest
.write_mask
) - 1;
741 result
= offset(result
, bld
, channel
);
744 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
745 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
746 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
753 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
756 for (unsigned i
= 0; i
< 2; i
++) {
757 nir_alu_instr
*const inot_instr
=
758 nir_src_as_alu_instr(&instr
->src
[i
].src
);
760 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
761 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
762 /* The source of the inot is now the source of instr. */
763 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
765 assert(!op
[i
].negate
);
768 op
[i
] = resolve_source_modifiers(op
[i
]);
774 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
776 nir_alu_instr
*instr
)
778 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
781 nir_alu_instr
*const inot_instr
= nir_src_as_alu_instr(&instr
->src
[0].src
);
783 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
786 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
787 * of valid size-changing combinations is a bit more complex.
789 * The source restriction is just because I was lazy about generating the
792 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
793 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
796 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
797 * this is float(1 + a).
801 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
803 /* Ignore the saturate modifier, if there is one. The result of the
804 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
806 bld
.ADD(result
, op
, brw_imm_d(1));
812 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
814 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
818 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, true);
826 fs_reg temp
= result
;
827 bool need_extra_copy
= false;
828 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
829 if (!instr
->src
[i
].src
.is_ssa
&&
830 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
831 need_extra_copy
= true;
832 temp
= bld
.vgrf(result
.type
, 4);
837 for (unsigned i
= 0; i
< 4; i
++) {
838 if (!(instr
->dest
.write_mask
& (1 << i
)))
841 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
842 inst
= bld
.MOV(offset(temp
, bld
, i
),
843 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
845 inst
= bld
.MOV(offset(temp
, bld
, i
),
846 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
848 inst
->saturate
= instr
->dest
.saturate
;
851 /* In this case the source and destination registers were the same,
852 * so we need to insert an extra set of moves in order to deal with
855 if (need_extra_copy
) {
856 for (unsigned i
= 0; i
< 4; i
++) {
857 if (!(instr
->dest
.write_mask
& (1 << i
)))
860 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
868 if (optimize_extract_to_float(instr
, result
))
870 inst
= bld
.MOV(result
, op
[0]);
871 inst
->saturate
= instr
->dest
.saturate
;
874 case nir_op_f2f16_rtne
:
875 case nir_op_f2f16_rtz
:
876 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
877 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
880 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
881 * on the HW gen, it is a special hw opcode or just a MOV, and
882 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
884 * But if we want to use that opcode, we need to provide support on
885 * different optimizations and lowerings. As right now HF support is
886 * only for gen8+, it will be better to use directly the MOV, and use
887 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
889 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
890 inst
= bld
.MOV(result
, op
[0]);
891 inst
->saturate
= instr
->dest
.saturate
;
901 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
903 op
[0].type
= BRW_REGISTER_TYPE_D
;
904 op
[0].negate
= !op
[0].negate
;
928 if (result
.type
== BRW_REGISTER_TYPE_B
||
929 result
.type
== BRW_REGISTER_TYPE_UB
||
930 result
.type
== BRW_REGISTER_TYPE_HF
)
931 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
933 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
934 op
[0].type
== BRW_REGISTER_TYPE_UB
||
935 op
[0].type
== BRW_REGISTER_TYPE_HF
)
936 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
938 inst
= bld
.MOV(result
, op
[0]);
939 inst
->saturate
= instr
->dest
.saturate
;
943 assert(!instr
->dest
.saturate
);
945 /* Straightforward since the source can be assumed to be either
946 * strictly >= 0 or strictly <= 0 depending on the setting of the
949 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
951 inst
= (op
[0].negate
)
952 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
953 : bld
.MOV(result
, brw_imm_f(1.0f
));
955 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
956 } else if (type_sz(op
[0].type
) == 2) {
957 /* AND(val, 0x8000) gives the sign bit.
959 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
961 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
962 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
964 op
[0].type
= BRW_REGISTER_TYPE_UW
;
965 result
.type
= BRW_REGISTER_TYPE_UW
;
966 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
968 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
969 inst
->predicate
= BRW_PREDICATE_NORMAL
;
970 } else if (type_sz(op
[0].type
) == 4) {
971 /* AND(val, 0x80000000) gives the sign bit.
973 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
976 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
978 op
[0].type
= BRW_REGISTER_TYPE_UD
;
979 result
.type
= BRW_REGISTER_TYPE_UD
;
980 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
982 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
983 inst
->predicate
= BRW_PREDICATE_NORMAL
;
985 /* For doubles we do the same but we need to consider:
987 * - 2-src instructions can't operate with 64-bit immediates
988 * - The sign is encoded in the high 32-bit of each DF
989 * - We need to produce a DF result.
991 assert(type_sz(op
[0].type
) == 8);
993 fs_reg zero
= vgrf(glsl_type::double_type
);
994 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
995 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
997 bld
.MOV(result
, zero
);
999 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
1000 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
1001 brw_imm_ud(0x80000000u
));
1003 set_predicate(BRW_PREDICATE_NORMAL
,
1004 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
1010 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1011 inst
->saturate
= instr
->dest
.saturate
;
1015 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1016 inst
->saturate
= instr
->dest
.saturate
;
1020 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1021 inst
->saturate
= instr
->dest
.saturate
;
1025 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1026 inst
->saturate
= instr
->dest
.saturate
;
1030 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1031 inst
->saturate
= instr
->dest
.saturate
;
1035 if (fs_key
->high_quality_derivatives
) {
1036 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1038 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1040 inst
->saturate
= instr
->dest
.saturate
;
1042 case nir_op_fddx_fine
:
1043 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1044 inst
->saturate
= instr
->dest
.saturate
;
1046 case nir_op_fddx_coarse
:
1047 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1048 inst
->saturate
= instr
->dest
.saturate
;
1051 if (fs_key
->high_quality_derivatives
) {
1052 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1054 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1056 inst
->saturate
= instr
->dest
.saturate
;
1058 case nir_op_fddy_fine
:
1059 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1060 inst
->saturate
= instr
->dest
.saturate
;
1062 case nir_op_fddy_coarse
:
1063 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1064 inst
->saturate
= instr
->dest
.saturate
;
1069 inst
= bld
.ADD(result
, op
[0], op
[1]);
1070 inst
->saturate
= instr
->dest
.saturate
;
1073 case nir_op_uadd_sat
:
1074 inst
= bld
.ADD(result
, op
[0], op
[1]);
1075 inst
->saturate
= true;
1079 inst
= bld
.MUL(result
, op
[0], op
[1]);
1080 inst
->saturate
= instr
->dest
.saturate
;
1083 case nir_op_imul_2x32_64
:
1084 case nir_op_umul_2x32_64
:
1085 bld
.MUL(result
, op
[0], op
[1]);
1089 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1090 bld
.MUL(result
, op
[0], op
[1]);
1093 case nir_op_imul_high
:
1094 case nir_op_umul_high
:
1095 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1096 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1101 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1102 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1105 case nir_op_uadd_carry
:
1106 unreachable("Should have been lowered by carry_to_arith().");
1108 case nir_op_usub_borrow
:
1109 unreachable("Should have been lowered by borrow_to_arith().");
1113 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1114 * appears that our hardware just does the right thing for signed
1117 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1118 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1122 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1123 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1125 /* Math instructions don't support conditional mod */
1126 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1127 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1129 /* Now, we need to determine if signs of the sources are different.
1130 * When we XOR the sources, the top bit is 0 if they are the same and 1
1131 * if they are different. We can then use a conditional modifier to
1132 * turn that into a predicate. This leads us to an XOR.l instruction.
1134 * Technically, according to the PRM, you're not allowed to use .l on a
1135 * XOR instruction. However, emperical experiments and Curro's reading
1136 * of the simulator source both indicate that it's safe.
1138 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1139 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1140 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1141 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1143 /* If the result of the initial remainder operation is non-zero and the
1144 * two sources have different signs, add in a copy of op[1] to get the
1145 * final integer modulus value.
1147 inst
= bld
.ADD(result
, result
, op
[1]);
1148 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1155 case nir_op_fne32
: {
1156 fs_reg dest
= result
;
1158 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1160 dest
= bld
.vgrf(op
[0].type
, 1);
1162 brw_conditional_mod cond
;
1163 switch (instr
->op
) {
1165 cond
= BRW_CONDITIONAL_L
;
1168 cond
= BRW_CONDITIONAL_GE
;
1171 cond
= BRW_CONDITIONAL_Z
;
1174 cond
= BRW_CONDITIONAL_NZ
;
1177 unreachable("bad opcode");
1180 bld
.CMP(dest
, op
[0], op
[1], cond
);
1182 if (bit_size
> 32) {
1183 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1184 } else if(bit_size
< 32) {
1185 /* When we convert the result to 32-bit we need to be careful and do
1186 * it as a signed conversion to get sign extension (for 32-bit true)
1188 const brw_reg_type src_type
=
1189 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1191 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1201 case nir_op_ine32
: {
1202 fs_reg dest
= result
;
1204 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1206 dest
= bld
.vgrf(op
[0].type
, 1);
1208 brw_conditional_mod cond
;
1209 switch (instr
->op
) {
1212 cond
= BRW_CONDITIONAL_L
;
1216 cond
= BRW_CONDITIONAL_GE
;
1219 cond
= BRW_CONDITIONAL_Z
;
1222 cond
= BRW_CONDITIONAL_NZ
;
1225 unreachable("bad opcode");
1227 bld
.CMP(dest
, op
[0], op
[1], cond
);
1229 if (bit_size
> 32) {
1230 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1231 } else if (bit_size
< 32) {
1232 /* When we convert the result to 32-bit we need to be careful and do
1233 * it as a signed conversion to get sign extension (for 32-bit true)
1235 const brw_reg_type src_type
=
1236 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1238 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1244 if (devinfo
->gen
>= 8) {
1245 nir_alu_instr
*const inot_src_instr
=
1246 nir_src_as_alu_instr(&instr
->src
[0].src
);
1248 if (inot_src_instr
!= NULL
&&
1249 (inot_src_instr
->op
== nir_op_ior
||
1250 inot_src_instr
->op
== nir_op_ixor
||
1251 inot_src_instr
->op
== nir_op_iand
) &&
1252 !inot_src_instr
->src
[0].abs
&&
1253 !inot_src_instr
->src
[0].negate
&&
1254 !inot_src_instr
->src
[1].abs
&&
1255 !inot_src_instr
->src
[1].negate
) {
1256 /* The sources of the source logical instruction are now the
1257 * sources of the instruction that will be generated.
1259 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1260 resolve_inot_sources(bld
, inot_src_instr
, op
);
1262 /* Smash all of the sources and destination to be signed. This
1263 * doesn't matter for the operation of the instruction, but cmod
1264 * propagation fails on unsigned sources with negation (due to
1265 * fs_inst::can_do_cmod returning false).
1268 brw_type_for_nir_type(devinfo
,
1269 (nir_alu_type
)(nir_type_int
|
1270 nir_dest_bit_size(instr
->dest
.dest
)));
1272 brw_type_for_nir_type(devinfo
,
1273 (nir_alu_type
)(nir_type_int
|
1274 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1276 brw_type_for_nir_type(devinfo
,
1277 (nir_alu_type
)(nir_type_int
|
1278 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1280 /* For XOR, only invert one of the sources. Arbitrarily choose
1283 op
[0].negate
= !op
[0].negate
;
1284 if (inot_src_instr
->op
!= nir_op_ixor
)
1285 op
[1].negate
= !op
[1].negate
;
1287 switch (inot_src_instr
->op
) {
1289 bld
.AND(result
, op
[0], op
[1]);
1293 bld
.OR(result
, op
[0], op
[1]);
1297 bld
.XOR(result
, op
[0], op
[1]);
1301 unreachable("impossible opcode");
1304 op
[0] = resolve_source_modifiers(op
[0]);
1306 bld
.NOT(result
, op
[0]);
1309 if (devinfo
->gen
>= 8) {
1310 resolve_inot_sources(bld
, instr
, op
);
1312 bld
.XOR(result
, op
[0], op
[1]);
1315 if (devinfo
->gen
>= 8) {
1316 resolve_inot_sources(bld
, instr
, op
);
1318 bld
.OR(result
, op
[0], op
[1]);
1321 if (devinfo
->gen
>= 8) {
1322 resolve_inot_sources(bld
, instr
, op
);
1324 bld
.AND(result
, op
[0], op
[1]);
1330 case nir_op_b32all_fequal2
:
1331 case nir_op_b32all_iequal2
:
1332 case nir_op_b32all_fequal3
:
1333 case nir_op_b32all_iequal3
:
1334 case nir_op_b32all_fequal4
:
1335 case nir_op_b32all_iequal4
:
1336 case nir_op_b32any_fnequal2
:
1337 case nir_op_b32any_inequal2
:
1338 case nir_op_b32any_fnequal3
:
1339 case nir_op_b32any_inequal3
:
1340 case nir_op_b32any_fnequal4
:
1341 case nir_op_b32any_inequal4
:
1342 unreachable("Lowered by nir_lower_alu_reductions");
1344 case nir_op_fnoise1_1
:
1345 case nir_op_fnoise1_2
:
1346 case nir_op_fnoise1_3
:
1347 case nir_op_fnoise1_4
:
1348 case nir_op_fnoise2_1
:
1349 case nir_op_fnoise2_2
:
1350 case nir_op_fnoise2_3
:
1351 case nir_op_fnoise2_4
:
1352 case nir_op_fnoise3_1
:
1353 case nir_op_fnoise3_2
:
1354 case nir_op_fnoise3_3
:
1355 case nir_op_fnoise3_4
:
1356 case nir_op_fnoise4_1
:
1357 case nir_op_fnoise4_2
:
1358 case nir_op_fnoise4_3
:
1359 case nir_op_fnoise4_4
:
1360 unreachable("not reached: should be handled by lower_noise");
1363 unreachable("not reached: should be handled by ldexp_to_arith()");
1366 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1367 inst
->saturate
= instr
->dest
.saturate
;
1371 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1372 inst
->saturate
= instr
->dest
.saturate
;
1376 case nir_op_f2b32
: {
1377 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1378 if (bit_size
== 64) {
1379 /* two-argument instructions can't take 64-bit immediates */
1383 if (instr
->op
== nir_op_f2b32
) {
1384 zero
= vgrf(glsl_type::double_type
);
1385 tmp
= vgrf(glsl_type::double_type
);
1386 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1388 zero
= vgrf(glsl_type::int64_t_type
);
1389 tmp
= vgrf(glsl_type::int64_t_type
);
1390 bld
.MOV(zero
, brw_imm_q(0));
1393 /* A SIMD16 execution needs to be split in two instructions, so use
1394 * a vgrf instead of the flag register as dst so instruction splitting
1397 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1398 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1401 if (bit_size
== 32) {
1402 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1404 assert(bit_size
== 16);
1405 zero
= instr
->op
== nir_op_f2b32
?
1406 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1408 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1414 inst
= bld
.RNDZ(result
, op
[0]);
1415 inst
->saturate
= instr
->dest
.saturate
;
1418 case nir_op_fceil
: {
1419 op
[0].negate
= !op
[0].negate
;
1420 fs_reg temp
= vgrf(glsl_type::float_type
);
1421 bld
.RNDD(temp
, op
[0]);
1423 inst
= bld
.MOV(result
, temp
);
1424 inst
->saturate
= instr
->dest
.saturate
;
1428 inst
= bld
.RNDD(result
, op
[0]);
1429 inst
->saturate
= instr
->dest
.saturate
;
1432 inst
= bld
.FRC(result
, op
[0]);
1433 inst
->saturate
= instr
->dest
.saturate
;
1435 case nir_op_fround_even
:
1436 inst
= bld
.RNDE(result
, op
[0]);
1437 inst
->saturate
= instr
->dest
.saturate
;
1440 case nir_op_fquantize2f16
: {
1441 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1442 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1443 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1445 /* The destination stride must be at least as big as the source stride. */
1446 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1449 /* Check for denormal */
1450 fs_reg abs_src0
= op
[0];
1451 abs_src0
.abs
= true;
1452 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1454 /* Get the appropriately signed zero */
1455 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1456 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1457 brw_imm_ud(0x80000000));
1458 /* Do the actual F32 -> F16 -> F32 conversion */
1459 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1460 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1461 /* Select that or zero based on normal status */
1462 inst
= bld
.SEL(result
, zero
, tmp32
);
1463 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1464 inst
->saturate
= instr
->dest
.saturate
;
1471 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1472 inst
->saturate
= instr
->dest
.saturate
;
1478 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1479 inst
->saturate
= instr
->dest
.saturate
;
1482 case nir_op_pack_snorm_2x16
:
1483 case nir_op_pack_snorm_4x8
:
1484 case nir_op_pack_unorm_2x16
:
1485 case nir_op_pack_unorm_4x8
:
1486 case nir_op_unpack_snorm_2x16
:
1487 case nir_op_unpack_snorm_4x8
:
1488 case nir_op_unpack_unorm_2x16
:
1489 case nir_op_unpack_unorm_4x8
:
1490 case nir_op_unpack_half_2x16
:
1491 case nir_op_pack_half_2x16
:
1492 unreachable("not reached: should be handled by lower_packing_builtins");
1494 case nir_op_unpack_half_2x16_split_x
:
1495 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1496 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1497 inst
->saturate
= instr
->dest
.saturate
;
1499 case nir_op_unpack_half_2x16_split_y
:
1500 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1501 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1502 inst
->saturate
= instr
->dest
.saturate
;
1505 case nir_op_pack_64_2x32_split
:
1506 case nir_op_pack_32_2x16_split
:
1507 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1510 case nir_op_unpack_64_2x32_split_x
:
1511 case nir_op_unpack_64_2x32_split_y
: {
1512 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1513 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1515 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1519 case nir_op_unpack_32_2x16_split_x
:
1520 case nir_op_unpack_32_2x16_split_y
: {
1521 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1522 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1524 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1529 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1530 inst
->saturate
= instr
->dest
.saturate
;
1533 case nir_op_bitfield_reverse
:
1534 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1535 bld
.BFREV(result
, op
[0]);
1538 case nir_op_bit_count
:
1539 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1540 bld
.CBIT(result
, op
[0]);
1543 case nir_op_ufind_msb
: {
1544 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1545 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1549 case nir_op_ifind_msb
: {
1550 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1552 if (devinfo
->gen
< 7) {
1553 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1555 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1557 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1558 * count from the LSB side. If FBH didn't return an error
1559 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1560 * count into an LSB count.
1562 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1564 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1565 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1566 inst
->src
[0].negate
= true;
1571 case nir_op_find_lsb
:
1572 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1574 if (devinfo
->gen
< 7) {
1575 fs_reg temp
= vgrf(glsl_type::int_type
);
1577 /* (x & -x) generates a value that consists of only the LSB of x.
1578 * For all powers of 2, findMSB(y) == findLSB(y).
1580 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1581 fs_reg negated_src
= src
;
1583 /* One must be negated, and the other must be non-negated. It
1584 * doesn't matter which is which.
1586 negated_src
.negate
= true;
1589 bld
.AND(temp
, src
, negated_src
);
1590 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1592 bld
.FBL(result
, op
[0]);
1596 case nir_op_ubitfield_extract
:
1597 case nir_op_ibitfield_extract
:
1598 unreachable("should have been lowered");
1601 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1602 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1605 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1606 bld
.BFI1(result
, op
[0], op
[1]);
1609 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1610 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1613 case nir_op_bitfield_insert
:
1614 unreachable("not reached: should have been lowered");
1617 bld
.SHL(result
, op
[0], op
[1]);
1620 bld
.ASR(result
, op
[0], op
[1]);
1623 bld
.SHR(result
, op
[0], op
[1]);
1626 case nir_op_pack_half_2x16_split
:
1627 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1631 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1632 inst
->saturate
= instr
->dest
.saturate
;
1636 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1637 inst
->saturate
= instr
->dest
.saturate
;
1640 case nir_op_b32csel
:
1641 if (optimize_frontfacing_ternary(instr
, result
))
1644 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1645 inst
= bld
.SEL(result
, op
[1], op
[2]);
1646 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1649 case nir_op_extract_u8
:
1650 case nir_op_extract_i8
: {
1651 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1656 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1657 * Use two instructions and a word or DWord intermediate integer type.
1659 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1660 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1662 if (instr
->op
== nir_op_extract_i8
) {
1663 /* If we need to sign extend, extract to a word first */
1664 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1665 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1666 bld
.MOV(result
, w_temp
);
1667 } else if (byte
& 1) {
1668 /* Extract the high byte from the word containing the desired byte
1672 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1675 /* Otherwise use an AND with 0xff and a word type */
1677 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1681 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1682 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1687 case nir_op_extract_u16
:
1688 case nir_op_extract_i16
: {
1689 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1690 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1691 bld
.MOV(result
, subscript(op
[0], type
, word
));
1696 unreachable("unhandled instruction");
1699 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1700 * to sign extend the low bit to 0/~0
1702 if (devinfo
->gen
<= 5 &&
1703 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1704 fs_reg masked
= vgrf(glsl_type::int_type
);
1705 bld
.AND(masked
, result
, brw_imm_d(1));
1706 masked
.negate
= true;
1707 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1712 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1713 nir_load_const_instr
*instr
)
1715 const brw_reg_type reg_type
=
1716 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1717 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1719 switch (instr
->def
.bit_size
) {
1721 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1722 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1726 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1727 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1731 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1732 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1736 assert(devinfo
->gen
>= 7);
1737 if (devinfo
->gen
== 7) {
1738 /* We don't get 64-bit integer types until gen8 */
1739 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1740 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1741 setup_imm_df(bld
, instr
->value
[i
].f64
));
1744 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1745 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1750 unreachable("Invalid bit size");
1753 nir_ssa_values
[instr
->def
.index
] = reg
;
1757 fs_visitor::get_nir_src(const nir_src
&src
)
1761 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1762 const brw_reg_type reg_type
=
1763 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1764 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1766 reg
= nir_ssa_values
[src
.ssa
->index
];
1769 /* We don't handle indirects on locals */
1770 assert(src
.reg
.indirect
== NULL
);
1771 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1772 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1775 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1776 /* The only 64-bit type available on gen7 is DF, so use that. */
1777 reg
.type
= BRW_REGISTER_TYPE_DF
;
1779 /* To avoid floating-point denorm flushing problems, set the type by
1780 * default to an integer type - instructions that need floating point
1781 * semantics will set this to F if they need to
1783 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1784 BRW_REGISTER_TYPE_D
);
1791 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1793 * This function should not be called on any value which may be 64 bits.
1794 * We could theoretically support 64-bit on gen8+ but we choose not to
1795 * because it wouldn't work in general (no gen7 support) and there are
1796 * enough restrictions in 64-bit immediates that you can't take the return
1797 * value and treat it the same as the result of get_nir_src().
1800 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1802 assert(nir_src_bit_size(src
) == 32);
1803 return nir_src_is_const(src
) ?
1804 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1808 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1811 const brw_reg_type reg_type
=
1812 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1813 dest
.ssa
.bit_size
== 8 ?
1814 BRW_REGISTER_TYPE_D
:
1815 BRW_REGISTER_TYPE_F
);
1816 nir_ssa_values
[dest
.ssa
.index
] =
1817 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1818 return nir_ssa_values
[dest
.ssa
.index
];
1820 /* We don't handle indirects on locals */
1821 assert(dest
.reg
.indirect
== NULL
);
1822 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1823 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1828 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1831 for (unsigned i
= 0; i
< 4; i
++) {
1832 if (!((wr_mask
>> i
) & 1))
1835 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1836 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1837 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1838 if (new_inst
->src
[j
].file
== VGRF
)
1839 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1846 emit_pixel_interpolater_send(const fs_builder
&bld
,
1851 glsl_interp_mode interpolation
)
1853 struct brw_wm_prog_data
*wm_prog_data
=
1854 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1856 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1857 /* 2 floats per slot returned */
1858 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1859 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1861 wm_prog_data
->pulls_bary
= true;
1867 * Computes 1 << x, given a D/UD register containing some value x.
1870 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1872 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1874 fs_reg result
= bld
.vgrf(x
.type
, 1);
1875 fs_reg one
= bld
.vgrf(x
.type
, 1);
1877 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1878 bld
.SHL(result
, one
, x
);
1883 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1885 assert(stage
== MESA_SHADER_GEOMETRY
);
1887 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1889 if (gs_compile
->control_data_header_size_bits
== 0)
1892 /* We can only do EndPrimitive() functionality when the control data
1893 * consists of cut bits. Fortunately, the only time it isn't is when the
1894 * output type is points, in which case EndPrimitive() is a no-op.
1896 if (gs_prog_data
->control_data_format
!=
1897 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1901 /* Cut bits use one bit per vertex. */
1902 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1904 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1905 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1907 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1908 * vertex n, 0 otherwise. So all we need to do here is mark bit
1909 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1910 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1911 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1913 * Note that if EndPrimitive() is called before emitting any vertices, this
1914 * will cause us to set bit 31 of the control_data_bits register to 1.
1915 * That's fine because:
1917 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1918 * output, so the hardware will ignore cut bit 31.
1920 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1921 * last vertex, so setting cut bit 31 has no effect (since the primitive
1922 * is automatically ended when the GS terminates).
1924 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1925 * control_data_bits register to 0 when the first vertex is emitted.
1928 const fs_builder abld
= bld
.annotate("end primitive");
1930 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1931 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1932 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1933 fs_reg mask
= intexp2(abld
, prev_count
);
1934 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1935 * attention to the lower 5 bits of its second source argument, so on this
1936 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1937 * ((vertex_count - 1) % 32).
1939 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1943 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1945 assert(stage
== MESA_SHADER_GEOMETRY
);
1946 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1948 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1950 const fs_builder abld
= bld
.annotate("emit control data bits");
1951 const fs_builder fwa_bld
= bld
.exec_all();
1953 /* We use a single UD register to accumulate control data bits (32 bits
1954 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1957 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1958 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1959 * use the Channel Mask phase to enable/disable which DWord within that
1960 * group to write. (Remember, different SIMD8 channels may have emitted
1961 * different numbers of vertices, so we may need per-slot offsets.)
1963 * Channel masking presents an annoying problem: we may have to replicate
1964 * the data up to 4 times:
1966 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1968 * To avoid penalizing shaders that emit a small number of vertices, we
1969 * can avoid these sometimes: if the size of the control data header is
1970 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1971 * land in the same 128-bit group, so we can skip per-slot offsets.
1973 * Similarly, if the control data header is <= 32 bits, there is only one
1974 * DWord, so we can skip channel masks.
1976 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1978 fs_reg channel_mask
, per_slot_offset
;
1980 if (gs_compile
->control_data_header_size_bits
> 32) {
1981 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1982 channel_mask
= vgrf(glsl_type::uint_type
);
1985 if (gs_compile
->control_data_header_size_bits
> 128) {
1986 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1987 per_slot_offset
= vgrf(glsl_type::uint_type
);
1990 /* Figure out which DWord we're trying to write to using the formula:
1992 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1994 * Since bits_per_vertex is a power of two, and is known at compile
1995 * time, this can be optimized to:
1997 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1999 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2000 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2001 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2002 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2003 unsigned log2_bits_per_vertex
=
2004 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2005 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2007 if (per_slot_offset
.file
!= BAD_FILE
) {
2008 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2009 * the appropriate OWord within the control data header.
2011 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2014 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2015 * write to the appropriate DWORD within the OWORD.
2017 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2018 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2019 channel_mask
= intexp2(fwa_bld
, channel
);
2020 /* Then the channel masks need to be in bits 23:16. */
2021 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2024 /* Store the control data bits in the message payload and send it. */
2026 if (channel_mask
.file
!= BAD_FILE
)
2027 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2028 if (per_slot_offset
.file
!= BAD_FILE
)
2031 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2032 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2034 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2035 if (per_slot_offset
.file
!= BAD_FILE
)
2036 sources
[i
++] = per_slot_offset
;
2037 if (channel_mask
.file
!= BAD_FILE
)
2038 sources
[i
++] = channel_mask
;
2040 sources
[i
++] = this->control_data_bits
;
2043 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2044 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2046 /* We need to increment Global Offset by 256-bits to make room for
2047 * Broadwell's extra "Vertex Count" payload at the beginning of the
2048 * URB entry. Since this is an OWord message, Global Offset is counted
2049 * in 128-bit units, so we must set it to 2.
2051 if (gs_prog_data
->static_vertex_count
== -1)
2056 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2059 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2061 /* Note: we are calling this *before* increasing vertex_count, so
2062 * this->vertex_count == vertex_count - 1 in the formula above.
2065 /* Stream mode uses 2 bits per vertex */
2066 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2068 /* Must be a valid stream */
2069 assert(stream_id
< MAX_VERTEX_STREAMS
);
2071 /* Control data bits are initialized to 0 so we don't have to set any
2072 * bits when sending vertices to stream 0.
2077 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2079 /* reg::sid = stream_id */
2080 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2081 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2083 /* reg:shift_count = 2 * (vertex_count - 1) */
2084 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2085 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2087 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2088 * attention to the lower 5 bits of its second source argument, so on this
2089 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2090 * stream_id << ((2 * (vertex_count - 1)) % 32).
2092 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2093 abld
.SHL(mask
, sid
, shift_count
);
2094 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2098 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2101 assert(stage
== MESA_SHADER_GEOMETRY
);
2103 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2105 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2106 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2108 /* Haswell and later hardware ignores the "Render Stream Select" bits
2109 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2110 * and instead sends all primitives down the pipeline for rasterization.
2111 * If the SOL stage is enabled, "Render Stream Select" is honored and
2112 * primitives bound to non-zero streams are discarded after stream output.
2114 * Since the only purpose of primives sent to non-zero streams is to
2115 * be recorded by transform feedback, we can simply discard all geometry
2116 * bound to these streams when transform feedback is disabled.
2118 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2121 /* If we're outputting 32 control data bits or less, then we can wait
2122 * until the shader is over to output them all. Otherwise we need to
2123 * output them as we go. Now is the time to do it, since we're about to
2124 * output the vertex_count'th vertex, so it's guaranteed that the
2125 * control data bits associated with the (vertex_count - 1)th vertex are
2128 if (gs_compile
->control_data_header_size_bits
> 32) {
2129 const fs_builder abld
=
2130 bld
.annotate("emit vertex: emit control data bits");
2132 /* Only emit control data bits if we've finished accumulating a batch
2133 * of 32 bits. This is the case when:
2135 * (vertex_count * bits_per_vertex) % 32 == 0
2137 * (in other words, when the last 5 bits of vertex_count *
2138 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2139 * integer n (which is always the case, since bits_per_vertex is
2140 * always 1 or 2), this is equivalent to requiring that the last 5-n
2141 * bits of vertex_count are 0:
2143 * vertex_count & (2^(5-n) - 1) == 0
2145 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2148 * vertex_count & (32 / bits_per_vertex - 1) == 0
2150 * TODO: If vertex_count is an immediate, we could do some of this math
2151 * at compile time...
2154 abld
.AND(bld
.null_reg_d(), vertex_count
,
2155 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2156 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2158 abld
.IF(BRW_PREDICATE_NORMAL
);
2159 /* If vertex_count is 0, then no control data bits have been
2160 * accumulated yet, so we can skip emitting them.
2162 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2163 BRW_CONDITIONAL_NEQ
);
2164 abld
.IF(BRW_PREDICATE_NORMAL
);
2165 emit_gs_control_data_bits(vertex_count
);
2166 abld
.emit(BRW_OPCODE_ENDIF
);
2168 /* Reset control_data_bits to 0 so we can start accumulating a new
2171 * Note: in the case where vertex_count == 0, this neutralizes the
2172 * effect of any call to EndPrimitive() that the shader may have
2173 * made before outputting its first vertex.
2175 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2176 inst
->force_writemask_all
= true;
2177 abld
.emit(BRW_OPCODE_ENDIF
);
2180 emit_urb_writes(vertex_count
);
2182 /* In stream mode we have to set control data bits for all vertices
2183 * unless we have disabled control data bits completely (which we do
2184 * do for GL_POINTS outputs that don't use streams).
2186 if (gs_compile
->control_data_header_size_bits
> 0 &&
2187 gs_prog_data
->control_data_format
==
2188 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2189 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2194 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2195 const nir_src
&vertex_src
,
2196 unsigned base_offset
,
2197 const nir_src
&offset_src
,
2198 unsigned num_components
,
2199 unsigned first_component
)
2201 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2202 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2204 /* TODO: figure out push input layout for invocations == 1 */
2205 /* TODO: make this work with 64-bit inputs */
2206 if (gs_prog_data
->invocations
== 1 &&
2207 type_sz(dst
.type
) <= 4 &&
2208 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2209 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2210 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2211 nir_src_as_uint(vertex_src
) * push_reg_count
;
2212 for (unsigned i
= 0; i
< num_components
; i
++) {
2213 bld
.MOV(offset(dst
, bld
, i
),
2214 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2219 /* Resort to the pull model. Ensure the VUE handles are provided. */
2220 assert(gs_prog_data
->base
.include_vue_handles
);
2222 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2223 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2225 if (gs_prog_data
->invocations
== 1) {
2226 if (nir_src_is_const(vertex_src
)) {
2227 /* The vertex index is constant; just select the proper URB handle. */
2229 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2230 BRW_REGISTER_TYPE_UD
);
2232 /* The vertex index is non-constant. We need to use indirect
2233 * addressing to fetch the proper URB handle.
2235 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2236 * indicating that channel <n> should read the handle from
2237 * DWord <n>. We convert that to bytes by multiplying by 4.
2239 * Next, we convert the vertex index to bytes by multiplying
2240 * by 32 (shifting by 5), and add the two together. This is
2241 * the final indirect byte offset.
2243 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2244 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2245 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2246 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2248 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2249 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2250 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2251 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2252 /* Convert vertex_index to bytes (multiply by 32) */
2253 bld
.SHL(vertex_offset_bytes
,
2254 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2256 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2258 /* Use first_icp_handle as the base offset. There is one register
2259 * of URB handles per vertex, so inform the register allocator that
2260 * we might read up to nir->info.gs.vertices_in registers.
2262 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2263 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2264 fs_reg(icp_offset_bytes
),
2265 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2268 assert(gs_prog_data
->invocations
> 1);
2270 if (nir_src_is_const(vertex_src
)) {
2271 unsigned vertex
= nir_src_as_uint(vertex_src
);
2272 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2274 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2275 BRW_REGISTER_TYPE_UD
));
2277 /* The vertex index is non-constant. We need to use indirect
2278 * addressing to fetch the proper URB handle.
2281 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2283 /* Convert vertex_index to bytes (multiply by 4) */
2284 bld
.SHL(icp_offset_bytes
,
2285 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2288 /* Use first_icp_handle as the base offset. There is one DWord
2289 * of URB handles per vertex, so inform the register allocator that
2290 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2292 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2293 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2294 fs_reg(icp_offset_bytes
),
2295 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2302 fs_reg tmp_dst
= dst
;
2303 fs_reg indirect_offset
= get_nir_src(offset_src
);
2304 unsigned num_iterations
= 1;
2305 unsigned orig_num_components
= num_components
;
2307 if (type_sz(dst
.type
) == 8) {
2308 if (num_components
> 2) {
2312 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2314 first_component
= first_component
/ 2;
2317 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2318 if (nir_src_is_const(offset_src
)) {
2319 /* Constant indexing - use global offset. */
2320 if (first_component
!= 0) {
2321 unsigned read_components
= num_components
+ first_component
;
2322 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2323 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2324 inst
->size_written
= read_components
*
2325 tmp
.component_size(inst
->exec_size
);
2326 for (unsigned i
= 0; i
< num_components
; i
++) {
2327 bld
.MOV(offset(tmp_dst
, bld
, i
),
2328 offset(tmp
, bld
, i
+ first_component
));
2331 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2333 inst
->size_written
= num_components
*
2334 tmp_dst
.component_size(inst
->exec_size
);
2336 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2339 /* Indirect indexing - use per-slot offsets as well. */
2340 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2341 unsigned read_components
= num_components
+ first_component
;
2342 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2343 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2344 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2345 if (first_component
!= 0) {
2346 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2348 inst
->size_written
= read_components
*
2349 tmp
.component_size(inst
->exec_size
);
2350 for (unsigned i
= 0; i
< num_components
; i
++) {
2351 bld
.MOV(offset(tmp_dst
, bld
, i
),
2352 offset(tmp
, bld
, i
+ first_component
));
2355 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2357 inst
->size_written
= num_components
*
2358 tmp_dst
.component_size(inst
->exec_size
);
2360 inst
->offset
= base_offset
;
2364 if (type_sz(dst
.type
) == 8) {
2365 shuffle_from_32bit_read(bld
,
2366 offset(dst
, bld
, iter
* 2),
2367 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2372 if (num_iterations
> 1) {
2373 num_components
= orig_num_components
- 2;
2374 if(nir_src_is_const(offset_src
)) {
2377 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2378 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2379 indirect_offset
= new_indirect
;
2386 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2388 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2390 if (nir_src_is_const(*offset_src
)) {
2391 /* The only constant offset we should find is 0. brw_nir.c's
2392 * add_const_offset_to_base() will fold other constant offsets
2393 * into instr->const_index[0].
2395 assert(nir_src_as_uint(*offset_src
) == 0);
2399 return get_nir_src(*offset_src
);
2403 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2404 nir_intrinsic_instr
*instr
)
2406 assert(stage
== MESA_SHADER_VERTEX
);
2409 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2410 dest
= get_nir_dest(instr
->dest
);
2412 switch (instr
->intrinsic
) {
2413 case nir_intrinsic_load_vertex_id
:
2414 case nir_intrinsic_load_base_vertex
:
2415 unreachable("should be lowered by nir_lower_system_values()");
2417 case nir_intrinsic_load_input
: {
2418 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2419 unsigned first_component
= nir_intrinsic_component(instr
);
2420 unsigned num_components
= instr
->num_components
;
2422 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2424 if (type_sz(dest
.type
) == 8)
2425 first_component
/= 2;
2427 /* For 16-bit support maybe a temporary will be needed to copy from
2430 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2431 first_component
, num_components
);
2435 case nir_intrinsic_load_vertex_id_zero_base
:
2436 case nir_intrinsic_load_instance_id
:
2437 case nir_intrinsic_load_base_instance
:
2438 case nir_intrinsic_load_draw_id
:
2439 case nir_intrinsic_load_first_vertex
:
2440 case nir_intrinsic_load_is_indexed_draw
:
2441 unreachable("lowered by brw_nir_lower_vs_inputs");
2444 nir_emit_intrinsic(bld
, instr
);
2450 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2451 nir_intrinsic_instr
*instr
)
2453 assert(stage
== MESA_SHADER_TESS_CTRL
);
2454 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2455 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2458 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2459 dst
= get_nir_dest(instr
->dest
);
2461 switch (instr
->intrinsic
) {
2462 case nir_intrinsic_load_primitive_id
:
2463 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2465 case nir_intrinsic_load_invocation_id
:
2466 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2468 case nir_intrinsic_load_patch_vertices_in
:
2469 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2470 brw_imm_d(tcs_key
->input_vertices
));
2473 case nir_intrinsic_barrier
: {
2474 if (tcs_prog_data
->instances
== 1)
2477 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2478 fs_reg m0_2
= component(m0
, 2);
2480 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2482 /* Zero the message header */
2483 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2485 if (devinfo
->gen
< 11) {
2486 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2487 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2488 brw_imm_ud(INTEL_MASK(16, 13)));
2490 /* Shift it up to bits 27:24. */
2491 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2493 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2494 brw_imm_ud(INTEL_MASK(30, 24)));
2497 /* Set the Barrier Count and the enable bit */
2498 if (devinfo
->gen
< 11) {
2499 chanbld
.OR(m0_2
, m0_2
,
2500 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2502 chanbld
.OR(m0_2
, m0_2
,
2503 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2506 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2510 case nir_intrinsic_load_input
:
2511 unreachable("nir_lower_io should never give us these.");
2514 case nir_intrinsic_load_per_vertex_input
: {
2515 fs_reg indirect_offset
= get_indirect_offset(instr
);
2516 unsigned imm_offset
= instr
->const_index
[0];
2518 const nir_src
&vertex_src
= instr
->src
[0];
2524 if (nir_src_is_const(vertex_src
)) {
2525 /* Emit a MOV to resolve <0,1,0> regioning. */
2526 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2527 unsigned vertex
= nir_src_as_uint(vertex_src
);
2529 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2530 BRW_REGISTER_TYPE_UD
));
2531 } else if (tcs_prog_data
->instances
== 1 &&
2532 vertex_src
.is_ssa
&&
2533 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2534 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2535 /* For the common case of only 1 instance, an array index of
2536 * gl_InvocationID means reading g1. Skip all the indirect work.
2538 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2540 /* The vertex index is non-constant. We need to use indirect
2541 * addressing to fetch the proper URB handle.
2543 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2545 /* Each ICP handle is a single DWord (4 bytes) */
2546 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2547 bld
.SHL(vertex_offset_bytes
,
2548 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2551 /* Start at g1. We might read up to 4 registers. */
2552 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2553 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2554 brw_imm_ud(4 * REG_SIZE
));
2557 /* We can only read two double components with each URB read, so
2558 * we send two read messages in that case, each one loading up to
2559 * two double components.
2561 unsigned num_iterations
= 1;
2562 unsigned num_components
= instr
->num_components
;
2563 unsigned first_component
= nir_intrinsic_component(instr
);
2564 fs_reg orig_dst
= dst
;
2565 if (type_sz(dst
.type
) == 8) {
2566 first_component
= first_component
/ 2;
2567 if (instr
->num_components
> 2) {
2572 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2576 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2577 if (indirect_offset
.file
== BAD_FILE
) {
2578 /* Constant indexing - use global offset. */
2579 if (first_component
!= 0) {
2580 unsigned read_components
= num_components
+ first_component
;
2581 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2582 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2583 for (unsigned i
= 0; i
< num_components
; i
++) {
2584 bld
.MOV(offset(dst
, bld
, i
),
2585 offset(tmp
, bld
, i
+ first_component
));
2588 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2590 inst
->offset
= imm_offset
;
2593 /* Indirect indexing - use per-slot offsets as well. */
2594 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2595 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2596 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2597 if (first_component
!= 0) {
2598 unsigned read_components
= num_components
+ first_component
;
2599 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2600 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2602 for (unsigned i
= 0; i
< num_components
; i
++) {
2603 bld
.MOV(offset(dst
, bld
, i
),
2604 offset(tmp
, bld
, i
+ first_component
));
2607 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2610 inst
->offset
= imm_offset
;
2613 inst
->size_written
= (num_components
+ first_component
) *
2614 inst
->dst
.component_size(inst
->exec_size
);
2616 /* If we are reading 64-bit data using 32-bit read messages we need
2617 * build proper 64-bit data elements by shuffling the low and high
2618 * 32-bit components around like we do for other things like UBOs
2621 if (type_sz(dst
.type
) == 8) {
2622 shuffle_from_32bit_read(bld
,
2623 offset(orig_dst
, bld
, iter
* 2),
2624 retype(dst
, BRW_REGISTER_TYPE_D
),
2628 /* Copy the temporary to the destination to deal with writemasking.
2630 * Also attempt to deal with gl_PointSize being in the .w component.
2632 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2633 assert(type_sz(dst
.type
) < 8);
2634 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2635 inst
->size_written
= 4 * REG_SIZE
;
2636 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2639 /* If we are loading double data and we need a second read message
2640 * adjust the write offset
2642 if (num_iterations
> 1) {
2643 num_components
= instr
->num_components
- 2;
2650 case nir_intrinsic_load_output
:
2651 case nir_intrinsic_load_per_vertex_output
: {
2652 fs_reg indirect_offset
= get_indirect_offset(instr
);
2653 unsigned imm_offset
= instr
->const_index
[0];
2654 unsigned first_component
= nir_intrinsic_component(instr
);
2657 if (indirect_offset
.file
== BAD_FILE
) {
2658 /* Replicate the patch handle to all enabled channels */
2659 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2660 bld
.MOV(patch_handle
,
2661 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2664 if (first_component
!= 0) {
2665 unsigned read_components
=
2666 instr
->num_components
+ first_component
;
2667 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2668 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2670 inst
->size_written
= read_components
* REG_SIZE
;
2671 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2672 bld
.MOV(offset(dst
, bld
, i
),
2673 offset(tmp
, bld
, i
+ first_component
));
2676 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2678 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2680 inst
->offset
= imm_offset
;
2684 /* Indirect indexing - use per-slot offsets as well. */
2685 const fs_reg srcs
[] = {
2686 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2689 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2690 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2691 if (first_component
!= 0) {
2692 unsigned read_components
=
2693 instr
->num_components
+ first_component
;
2694 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2695 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2697 inst
->size_written
= read_components
* REG_SIZE
;
2698 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2699 bld
.MOV(offset(dst
, bld
, i
),
2700 offset(tmp
, bld
, i
+ first_component
));
2703 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2705 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2707 inst
->offset
= imm_offset
;
2713 case nir_intrinsic_store_output
:
2714 case nir_intrinsic_store_per_vertex_output
: {
2715 fs_reg value
= get_nir_src(instr
->src
[0]);
2716 bool is_64bit
= (instr
->src
[0].is_ssa
?
2717 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2718 fs_reg indirect_offset
= get_indirect_offset(instr
);
2719 unsigned imm_offset
= instr
->const_index
[0];
2720 unsigned mask
= instr
->const_index
[1];
2721 unsigned header_regs
= 0;
2723 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2725 if (indirect_offset
.file
!= BAD_FILE
) {
2726 srcs
[header_regs
++] = indirect_offset
;
2732 unsigned num_components
= util_last_bit(mask
);
2735 /* We can only pack two 64-bit components in a single message, so send
2736 * 2 messages if we have more components
2738 unsigned num_iterations
= 1;
2739 unsigned iter_components
= num_components
;
2740 unsigned first_component
= nir_intrinsic_component(instr
);
2742 first_component
= first_component
/ 2;
2743 if (instr
->num_components
> 2) {
2745 iter_components
= 2;
2749 mask
= mask
<< first_component
;
2751 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2752 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2753 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2754 opcode
= indirect_offset
.file
!= BAD_FILE
?
2755 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2756 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2757 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2758 /* Expand the 64-bit mask to 32-bit channels. We only handle
2759 * two channels in each iteration, so we only care about X/Y.
2761 unsigned mask32
= 0;
2762 if (mask
& WRITEMASK_X
)
2763 mask32
|= WRITEMASK_XY
;
2764 if (mask
& WRITEMASK_Y
)
2765 mask32
|= WRITEMASK_ZW
;
2767 /* If the mask does not include any of the channels X or Y there
2768 * is nothing to do in this iteration. Move on to the next couple
2769 * of 64-bit channels.
2777 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2778 opcode
= indirect_offset
.file
!= BAD_FILE
?
2779 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2780 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2782 opcode
= indirect_offset
.file
!= BAD_FILE
?
2783 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2784 SHADER_OPCODE_URB_WRITE_SIMD8
;
2787 for (unsigned i
= 0; i
< iter_components
; i
++) {
2788 if (!(mask
& (1 << (i
+ first_component
))))
2792 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2794 /* We need to shuffle the 64-bit data to match the layout
2795 * expected by our 32-bit URB write messages. We use a temporary
2798 unsigned channel
= iter
* 2 + i
;
2799 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2801 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2802 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2803 offset(dest
, bld
, 1);
2808 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2809 (is_64bit
? 2 * first_component
: first_component
);
2811 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2812 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2814 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2815 inst
->offset
= imm_offset
;
2818 /* If this is a 64-bit attribute, select the next two 64-bit channels
2819 * to be handled in the next iteration.
2830 nir_emit_intrinsic(bld
, instr
);
2836 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2837 nir_intrinsic_instr
*instr
)
2839 assert(stage
== MESA_SHADER_TESS_EVAL
);
2840 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2843 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2844 dest
= get_nir_dest(instr
->dest
);
2846 switch (instr
->intrinsic
) {
2847 case nir_intrinsic_load_primitive_id
:
2848 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2850 case nir_intrinsic_load_tess_coord
:
2851 /* gl_TessCoord is part of the payload in g1-3 */
2852 for (unsigned i
= 0; i
< 3; i
++) {
2853 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2857 case nir_intrinsic_load_input
:
2858 case nir_intrinsic_load_per_vertex_input
: {
2859 fs_reg indirect_offset
= get_indirect_offset(instr
);
2860 unsigned imm_offset
= instr
->const_index
[0];
2861 unsigned first_component
= nir_intrinsic_component(instr
);
2863 if (type_sz(dest
.type
) == 8) {
2864 first_component
= first_component
/ 2;
2868 if (indirect_offset
.file
== BAD_FILE
) {
2869 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2870 * which is 16 registers (since each holds 2 vec4 slots).
2872 unsigned slot_count
= 1;
2873 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2876 const unsigned max_push_slots
= 32;
2877 if (imm_offset
+ slot_count
<= max_push_slots
) {
2878 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2879 for (int i
= 0; i
< instr
->num_components
; i
++) {
2880 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2881 i
+ first_component
;
2882 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2885 tes_prog_data
->base
.urb_read_length
=
2886 MAX2(tes_prog_data
->base
.urb_read_length
,
2887 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2889 /* Replicate the patch handle to all enabled channels */
2890 const fs_reg srcs
[] = {
2891 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2893 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2894 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2896 if (first_component
!= 0) {
2897 unsigned read_components
=
2898 instr
->num_components
+ first_component
;
2899 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2900 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2902 inst
->size_written
= read_components
* REG_SIZE
;
2903 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2904 bld
.MOV(offset(dest
, bld
, i
),
2905 offset(tmp
, bld
, i
+ first_component
));
2908 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2910 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2913 inst
->offset
= imm_offset
;
2916 /* Indirect indexing - use per-slot offsets as well. */
2918 /* We can only read two double components with each URB read, so
2919 * we send two read messages in that case, each one loading up to
2920 * two double components.
2922 unsigned num_iterations
= 1;
2923 unsigned num_components
= instr
->num_components
;
2924 fs_reg orig_dest
= dest
;
2925 if (type_sz(dest
.type
) == 8) {
2926 if (instr
->num_components
> 2) {
2930 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2934 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2935 const fs_reg srcs
[] = {
2936 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2939 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2940 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2942 if (first_component
!= 0) {
2943 unsigned read_components
=
2944 num_components
+ first_component
;
2945 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2946 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2948 for (unsigned i
= 0; i
< num_components
; i
++) {
2949 bld
.MOV(offset(dest
, bld
, i
),
2950 offset(tmp
, bld
, i
+ first_component
));
2953 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2957 inst
->offset
= imm_offset
;
2958 inst
->size_written
= (num_components
+ first_component
) *
2959 inst
->dst
.component_size(inst
->exec_size
);
2961 /* If we are reading 64-bit data using 32-bit read messages we need
2962 * build proper 64-bit data elements by shuffling the low and high
2963 * 32-bit components around like we do for other things like UBOs
2966 if (type_sz(dest
.type
) == 8) {
2967 shuffle_from_32bit_read(bld
,
2968 offset(orig_dest
, bld
, iter
* 2),
2969 retype(dest
, BRW_REGISTER_TYPE_D
),
2973 /* If we are loading double data and we need a second read message
2976 if (num_iterations
> 1) {
2977 num_components
= instr
->num_components
- 2;
2985 nir_emit_intrinsic(bld
, instr
);
2991 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2992 nir_intrinsic_instr
*instr
)
2994 assert(stage
== MESA_SHADER_GEOMETRY
);
2995 fs_reg indirect_offset
;
2998 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2999 dest
= get_nir_dest(instr
->dest
);
3001 switch (instr
->intrinsic
) {
3002 case nir_intrinsic_load_primitive_id
:
3003 assert(stage
== MESA_SHADER_GEOMETRY
);
3004 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3005 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3006 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3009 case nir_intrinsic_load_input
:
3010 unreachable("load_input intrinsics are invalid for the GS stage");
3012 case nir_intrinsic_load_per_vertex_input
:
3013 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3014 instr
->src
[1], instr
->num_components
,
3015 nir_intrinsic_component(instr
));
3018 case nir_intrinsic_emit_vertex_with_counter
:
3019 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3022 case nir_intrinsic_end_primitive_with_counter
:
3023 emit_gs_end_primitive(instr
->src
[0]);
3026 case nir_intrinsic_set_vertex_count
:
3027 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3030 case nir_intrinsic_load_invocation_id
: {
3031 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3032 assert(val
.file
!= BAD_FILE
);
3033 dest
.type
= val
.type
;
3039 nir_emit_intrinsic(bld
, instr
);
3045 * Fetch the current render target layer index.
3048 fetch_render_target_array_index(const fs_builder
&bld
)
3050 if (bld
.shader
->devinfo
->gen
>= 6) {
3051 /* The render target array index is provided in the thread payload as
3052 * bits 26:16 of r0.0.
3054 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3055 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3059 /* Pre-SNB we only ever render into the first layer of the framebuffer
3060 * since layered rendering is not implemented.
3062 return brw_imm_ud(0);
3067 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3068 * framebuffer at the current fragment coordinates and sample index.
3071 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3074 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3076 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3077 const brw_wm_prog_key
*wm_key
=
3078 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3079 assert(!wm_key
->coherent_fb_fetch
);
3080 const struct brw_wm_prog_data
*wm_prog_data
=
3081 brw_wm_prog_data(stage_prog_data
);
3083 /* Calculate the surface index relative to the start of the texture binding
3084 * table block, since that's what the texturing messages expect.
3086 const unsigned surface
= target
+
3087 wm_prog_data
->binding_table
.render_target_read_start
-
3088 wm_prog_data
->base
.binding_table
.texture_start
;
3090 /* Calculate the fragment coordinates. */
3091 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3092 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3093 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3094 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3096 /* Calculate the sample index and MCS payload when multisampling. Luckily
3097 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3098 * shouldn't be necessary to recompile based on whether the framebuffer is
3101 if (wm_key
->multisample_fbo
&&
3102 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3103 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3105 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3106 const fs_reg mcs
= wm_key
->multisample_fbo
?
3107 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3109 /* Use either a normal or a CMS texel fetch message depending on whether
3110 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3111 * message just in case the framebuffer uses 16x multisampling, it should
3112 * be equivalent to the normal CMS fetch for lower multisampling modes.
3114 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3115 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3116 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3118 /* Emit the instruction. */
3119 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3120 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3121 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3122 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3123 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3124 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3125 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3126 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3127 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3129 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3130 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3136 * Actual coherent framebuffer read implemented using the native render target
3137 * read message. Requires SKL+.
3140 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3142 assert(bld
.shader
->devinfo
->gen
>= 9);
3143 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3144 inst
->target
= target
;
3145 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3151 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3153 if (n
&& regs
[0].file
!= BAD_FILE
) {
3157 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3159 for (unsigned i
= 0; i
< n
; i
++)
3167 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3169 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3170 const brw_wm_prog_key
*const key
=
3171 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3172 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3173 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3175 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3176 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3178 else if (l
== FRAG_RESULT_COLOR
)
3179 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3180 MAX2(key
->nr_color_regions
, 1));
3182 else if (l
== FRAG_RESULT_DEPTH
)
3183 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3185 else if (l
== FRAG_RESULT_STENCIL
)
3186 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3188 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3189 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3191 else if (l
>= FRAG_RESULT_DATA0
&&
3192 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3193 return alloc_temporary(v
->bld
, 4,
3194 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3197 unreachable("Invalid location");
3201 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3202 nir_intrinsic_instr
*instr
)
3204 assert(stage
== MESA_SHADER_FRAGMENT
);
3207 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3208 dest
= get_nir_dest(instr
->dest
);
3210 switch (instr
->intrinsic
) {
3211 case nir_intrinsic_load_front_face
:
3212 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3213 *emit_frontfacing_interpolation());
3216 case nir_intrinsic_load_sample_pos
: {
3217 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3218 assert(sample_pos
.file
!= BAD_FILE
);
3219 dest
.type
= sample_pos
.type
;
3220 bld
.MOV(dest
, sample_pos
);
3221 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3225 case nir_intrinsic_load_layer_id
:
3226 dest
.type
= BRW_REGISTER_TYPE_UD
;
3227 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3230 case nir_intrinsic_load_helper_invocation
:
3231 case nir_intrinsic_load_sample_mask_in
:
3232 case nir_intrinsic_load_sample_id
: {
3233 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3234 fs_reg val
= nir_system_values
[sv
];
3235 assert(val
.file
!= BAD_FILE
);
3236 dest
.type
= val
.type
;
3241 case nir_intrinsic_store_output
: {
3242 const fs_reg src
= get_nir_src(instr
->src
[0]);
3243 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3244 const unsigned location
= nir_intrinsic_base(instr
) +
3245 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3246 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3249 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3250 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3251 offset(src
, bld
, j
));
3256 case nir_intrinsic_load_output
: {
3257 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3258 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3259 assert(l
>= FRAG_RESULT_DATA0
);
3260 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3261 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3262 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3264 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3265 emit_coherent_fb_read(bld
, tmp
, target
);
3267 emit_non_coherent_fb_read(bld
, tmp
, target
);
3269 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3270 bld
.MOV(offset(dest
, bld
, j
),
3271 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3277 case nir_intrinsic_discard
:
3278 case nir_intrinsic_discard_if
: {
3279 /* We track our discarded pixels in f0.1. By predicating on it, we can
3280 * update just the flag bits that aren't yet discarded. If there's no
3281 * condition, we emit a CMP of g0 != g0, so all currently executing
3282 * channels will get turned off.
3285 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3286 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3287 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3289 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3290 BRW_REGISTER_TYPE_UW
));
3291 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3293 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3294 cmp
->flag_subreg
= 1;
3296 if (devinfo
->gen
>= 6) {
3297 emit_discard_jump();
3300 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3304 case nir_intrinsic_load_input
: {
3305 /* load_input is only used for flat inputs */
3306 unsigned base
= nir_intrinsic_base(instr
);
3307 unsigned comp
= nir_intrinsic_component(instr
);
3308 unsigned num_components
= instr
->num_components
;
3309 fs_reg orig_dest
= dest
;
3310 enum brw_reg_type type
= dest
.type
;
3312 /* Special case fields in the VUE header */
3313 if (base
== VARYING_SLOT_LAYER
)
3315 else if (base
== VARYING_SLOT_VIEWPORT
)
3318 if (nir_dest_bit_size(instr
->dest
) == 64) {
3319 /* const_index is in 32-bit type size units that could not be aligned
3320 * with DF. We need to read the double vector as if it was a float
3321 * vector of twice the number of components to fetch the right data.
3323 type
= BRW_REGISTER_TYPE_F
;
3324 num_components
*= 2;
3325 dest
= bld
.vgrf(type
, num_components
);
3328 for (unsigned int i
= 0; i
< num_components
; i
++) {
3329 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3330 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3333 if (nir_dest_bit_size(instr
->dest
) == 64) {
3334 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3335 instr
->num_components
);
3340 case nir_intrinsic_load_barycentric_pixel
:
3341 case nir_intrinsic_load_barycentric_centroid
:
3342 case nir_intrinsic_load_barycentric_sample
:
3343 /* Do nothing - load_interpolated_input handling will handle it later. */
3346 case nir_intrinsic_load_barycentric_at_sample
: {
3347 const glsl_interp_mode interpolation
=
3348 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3350 if (nir_src_is_const(instr
->src
[0])) {
3351 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3353 emit_pixel_interpolater_send(bld
,
3354 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3357 brw_imm_ud(msg_data
),
3360 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3361 BRW_REGISTER_TYPE_UD
);
3363 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3364 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3365 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3366 bld
.exec_all().group(1, 0)
3367 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3368 emit_pixel_interpolater_send(bld
,
3369 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3375 /* Make a loop that sends a message to the pixel interpolater
3376 * for the sample number in each live channel. If there are
3377 * multiple channels with the same sample number then these
3378 * will be handled simultaneously with a single interation of
3381 bld
.emit(BRW_OPCODE_DO
);
3383 /* Get the next live sample number into sample_id_reg */
3384 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3386 /* Set the flag register so that we can perform the send
3387 * message on all channels that have the same sample number
3389 bld
.CMP(bld
.null_reg_ud(),
3390 sample_src
, sample_id
,
3391 BRW_CONDITIONAL_EQ
);
3392 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3393 bld
.exec_all().group(1, 0)
3394 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3396 emit_pixel_interpolater_send(bld
,
3397 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3400 component(msg_data
, 0),
3402 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3404 /* Continue the loop if there are any live channels left */
3405 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3407 bld
.emit(BRW_OPCODE_WHILE
));
3413 case nir_intrinsic_load_barycentric_at_offset
: {
3414 const glsl_interp_mode interpolation
=
3415 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3417 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3420 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3421 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3422 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3424 emit_pixel_interpolater_send(bld
,
3425 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3428 brw_imm_ud(off_x
| (off_y
<< 4)),
3431 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3432 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3433 BRW_REGISTER_TYPE_F
);
3434 for (int i
= 0; i
< 2; i
++) {
3435 fs_reg temp
= vgrf(glsl_type::float_type
);
3436 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3437 fs_reg itemp
= vgrf(glsl_type::int_type
);
3439 bld
.MOV(itemp
, temp
);
3441 /* Clamp the upper end of the range to +7/16.
3442 * ARB_gpu_shader5 requires that we support a maximum offset
3443 * of +0.5, which isn't representable in a S0.4 value -- if
3444 * we didn't clamp it, we'd end up with -8/16, which is the
3445 * opposite of what the shader author wanted.
3447 * This is legal due to ARB_gpu_shader5's quantization
3450 * "Not all values of <offset> may be supported; x and y
3451 * offsets may be rounded to fixed-point values with the
3452 * number of fraction bits given by the
3453 * implementation-dependent constant
3454 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3456 set_condmod(BRW_CONDITIONAL_L
,
3457 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3460 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3461 emit_pixel_interpolater_send(bld
,
3471 case nir_intrinsic_load_interpolated_input
: {
3472 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3473 emit_fragcoord_interpolation(dest
);
3477 assert(instr
->src
[0].ssa
&&
3478 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3479 nir_intrinsic_instr
*bary_intrinsic
=
3480 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3481 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3482 enum glsl_interp_mode interp_mode
=
3483 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3486 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3487 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3488 /* Use the result of the PI message */
3489 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3491 /* Use the delta_xy values computed from the payload */
3492 enum brw_barycentric_mode bary
=
3493 brw_barycentric_mode(interp_mode
, bary_intrin
);
3495 dst_xy
= this->delta_xy
[bary
];
3498 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3500 component(interp_reg(nir_intrinsic_base(instr
),
3501 nir_intrinsic_component(instr
) + i
), 0);
3502 interp
.type
= BRW_REGISTER_TYPE_F
;
3503 dest
.type
= BRW_REGISTER_TYPE_F
;
3505 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3506 fs_reg tmp
= vgrf(glsl_type::float_type
);
3507 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3508 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3510 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3517 nir_emit_intrinsic(bld
, instr
);
3523 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3525 if (nir_src_is_const(instr
->src
[src
])) {
3526 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3529 else if (add_val
== -1)
3537 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3538 nir_intrinsic_instr
*instr
)
3540 assert(stage
== MESA_SHADER_COMPUTE
);
3541 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3544 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3545 dest
= get_nir_dest(instr
->dest
);
3547 switch (instr
->intrinsic
) {
3548 case nir_intrinsic_barrier
:
3550 cs_prog_data
->uses_barrier
= true;
3553 case nir_intrinsic_load_subgroup_id
:
3554 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3557 case nir_intrinsic_load_local_invocation_id
:
3558 case nir_intrinsic_load_work_group_id
: {
3559 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3560 fs_reg val
= nir_system_values
[sv
];
3561 assert(val
.file
!= BAD_FILE
);
3562 dest
.type
= val
.type
;
3563 for (unsigned i
= 0; i
< 3; i
++)
3564 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3568 case nir_intrinsic_load_num_work_groups
: {
3569 const unsigned surface
=
3570 cs_prog_data
->binding_table
.work_groups_start
;
3572 cs_prog_data
->uses_num_work_groups
= true;
3574 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3575 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3576 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3577 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3579 /* Read the 3 GLuint components of gl_NumWorkGroups */
3580 for (unsigned i
= 0; i
< 3; i
++) {
3581 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3582 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3583 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3588 case nir_intrinsic_shared_atomic_add
:
3589 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3591 case nir_intrinsic_shared_atomic_imin
:
3592 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3594 case nir_intrinsic_shared_atomic_umin
:
3595 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3597 case nir_intrinsic_shared_atomic_imax
:
3598 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3600 case nir_intrinsic_shared_atomic_umax
:
3601 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3603 case nir_intrinsic_shared_atomic_and
:
3604 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3606 case nir_intrinsic_shared_atomic_or
:
3607 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3609 case nir_intrinsic_shared_atomic_xor
:
3610 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3612 case nir_intrinsic_shared_atomic_exchange
:
3613 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3615 case nir_intrinsic_shared_atomic_comp_swap
:
3616 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3618 case nir_intrinsic_shared_atomic_fmin
:
3619 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3621 case nir_intrinsic_shared_atomic_fmax
:
3622 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3624 case nir_intrinsic_shared_atomic_fcomp_swap
:
3625 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3628 case nir_intrinsic_load_shared
: {
3629 assert(devinfo
->gen
>= 7);
3630 assert(stage
== MESA_SHADER_COMPUTE
);
3632 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3633 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3634 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3635 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3636 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3638 /* Make dest unsigned because that's what the temporary will be */
3639 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3641 /* Read the vector */
3642 if (nir_intrinsic_align(instr
) >= 4) {
3643 assert(nir_dest_bit_size(instr
->dest
) == 32);
3644 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3646 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3647 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3648 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3650 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3651 assert(nir_dest_num_components(instr
->dest
) == 1);
3652 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3654 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3655 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3656 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3657 bld
.MOV(dest
, read_result
);
3662 case nir_intrinsic_store_shared
: {
3663 assert(devinfo
->gen
>= 7);
3664 assert(stage
== MESA_SHADER_COMPUTE
);
3666 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3667 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3668 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3669 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3670 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3672 fs_reg data
= get_nir_src(instr
->src
[0]);
3673 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3675 assert(nir_intrinsic_write_mask(instr
) ==
3676 (1u << instr
->num_components
) - 1);
3677 if (nir_intrinsic_align(instr
) >= 4) {
3678 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3679 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3680 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3681 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3682 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3683 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3685 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3686 assert(nir_src_num_components(instr
->src
[0]) == 1);
3687 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3689 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3690 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3692 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3693 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3699 nir_emit_intrinsic(bld
, instr
);
3705 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3706 nir_op op
, brw_reg_type type
)
3708 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3709 switch (type_sz(type
)) {
3711 assert(type
!= BRW_REGISTER_TYPE_HF
);
3712 return retype(brw_imm_uw(value
.u16
), type
);
3714 return retype(brw_imm_ud(value
.u32
), type
);
3716 if (type
== BRW_REGISTER_TYPE_DF
)
3717 return setup_imm_df(bld
, value
.f64
);
3719 return retype(brw_imm_u64(value
.u64
), type
);
3721 unreachable("Invalid type size");
3726 brw_op_for_nir_reduction_op(nir_op op
)
3729 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3730 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3731 case nir_op_imul
: return BRW_OPCODE_MUL
;
3732 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3733 case nir_op_imin
: return BRW_OPCODE_SEL
;
3734 case nir_op_umin
: return BRW_OPCODE_SEL
;
3735 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3736 case nir_op_imax
: return BRW_OPCODE_SEL
;
3737 case nir_op_umax
: return BRW_OPCODE_SEL
;
3738 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3739 case nir_op_iand
: return BRW_OPCODE_AND
;
3740 case nir_op_ior
: return BRW_OPCODE_OR
;
3741 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3743 unreachable("Invalid reduction operation");
3747 static brw_conditional_mod
3748 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3751 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3752 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3753 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3754 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3755 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3756 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3757 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3758 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3759 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3760 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3761 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3762 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3763 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3765 unreachable("Invalid reduction operation");
3770 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3771 nir_intrinsic_instr
*instr
)
3773 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3775 if (stage_prog_data
->binding_table
.image_start
> 0) {
3776 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3777 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3779 bld
.ADD(image
, image
,
3780 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3784 return bld
.emit_uniformize(image
);
3788 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3789 nir_intrinsic_instr
*instr
)
3791 /* SSBO stores are weird in that their index is in src[1] */
3792 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3795 if (nir_src_is_const(instr
->src
[src
])) {
3796 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3797 nir_src_as_uint(instr
->src
[src
]);
3798 surf_index
= brw_imm_ud(index
);
3800 surf_index
= vgrf(glsl_type::uint_type
);
3801 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3802 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3805 return bld
.emit_uniformize(surf_index
);
3809 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3811 switch (nir_intrinsic_image_dim(instr
)) {
3812 case GLSL_SAMPLER_DIM_1D
:
3813 return 1 + nir_intrinsic_image_array(instr
);
3814 case GLSL_SAMPLER_DIM_2D
:
3815 case GLSL_SAMPLER_DIM_RECT
:
3816 return 2 + nir_intrinsic_image_array(instr
);
3817 case GLSL_SAMPLER_DIM_3D
:
3818 case GLSL_SAMPLER_DIM_CUBE
:
3820 case GLSL_SAMPLER_DIM_BUF
:
3822 case GLSL_SAMPLER_DIM_MS
:
3823 return 2 + nir_intrinsic_image_array(instr
);
3825 unreachable("Invalid image dimension");
3830 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3833 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3834 dest
= get_nir_dest(instr
->dest
);
3836 switch (instr
->intrinsic
) {
3837 case nir_intrinsic_image_load
:
3838 case nir_intrinsic_image_store
:
3839 case nir_intrinsic_image_atomic_add
:
3840 case nir_intrinsic_image_atomic_min
:
3841 case nir_intrinsic_image_atomic_max
:
3842 case nir_intrinsic_image_atomic_and
:
3843 case nir_intrinsic_image_atomic_or
:
3844 case nir_intrinsic_image_atomic_xor
:
3845 case nir_intrinsic_image_atomic_exchange
:
3846 case nir_intrinsic_image_atomic_comp_swap
: {
3847 if (stage
== MESA_SHADER_FRAGMENT
&&
3848 instr
->intrinsic
!= nir_intrinsic_image_load
)
3849 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3851 /* Get some metadata from the image intrinsic. */
3852 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3853 const GLenum format
= nir_intrinsic_format(instr
);
3855 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3856 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3857 get_nir_image_intrinsic_image(bld
, instr
);
3858 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3859 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
3860 brw_imm_ud(image_intrinsic_coord_components(instr
));
3862 /* Emit an image load, store or atomic op. */
3863 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3864 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3866 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
3867 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3868 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3869 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3870 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3871 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
3872 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
3873 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3876 unsigned num_srcs
= info
->num_srcs
;
3878 switch (instr
->intrinsic
) {
3879 case nir_intrinsic_image_atomic_add
:
3880 assert(num_srcs
== 4);
3882 op
= get_op_for_atomic_add(instr
, 3);
3884 if (op
!= BRW_AOP_ADD
)
3887 case nir_intrinsic_image_atomic_min
:
3888 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3889 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3891 case nir_intrinsic_image_atomic_max
:
3892 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3893 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3895 case nir_intrinsic_image_atomic_and
:
3898 case nir_intrinsic_image_atomic_or
:
3901 case nir_intrinsic_image_atomic_xor
:
3904 case nir_intrinsic_image_atomic_exchange
:
3907 case nir_intrinsic_image_atomic_comp_swap
:
3911 unreachable("Not reachable.");
3914 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
3918 data
= get_nir_src(instr
->src
[3]);
3919 if (num_srcs
>= 5) {
3920 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
3921 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
3922 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
3925 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3927 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
3928 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3933 case nir_intrinsic_image_size
: {
3934 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3935 * into will handle the binding table index for us in the geneerator.
3937 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3938 BRW_REGISTER_TYPE_UD
);
3939 image
= bld
.emit_uniformize(image
);
3941 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3942 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
3943 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
3944 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
3945 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
3947 /* Since the image size is always uniform, we can just emit a SIMD8
3948 * query instruction and splat the result out.
3950 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3952 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3953 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
3954 tmp
, srcs
, ARRAY_SIZE(srcs
));
3955 inst
->size_written
= 4 * REG_SIZE
;
3957 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3958 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3959 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3960 offset(retype(dest
, tmp
.type
), bld
, c
),
3961 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3963 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3964 component(offset(tmp
, ubld
, c
), 0));
3970 case nir_intrinsic_image_load_raw_intel
: {
3971 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3972 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3973 get_nir_image_intrinsic_image(bld
, instr
);
3974 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3975 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3976 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3979 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3980 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3981 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3985 case nir_intrinsic_image_store_raw_intel
: {
3986 if (stage
== MESA_SHADER_FRAGMENT
)
3987 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3989 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3990 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3991 get_nir_image_intrinsic_image(bld
, instr
);
3992 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3993 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
3994 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3995 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3997 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3998 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4002 case nir_intrinsic_group_memory_barrier
:
4003 case nir_intrinsic_memory_barrier_shared
:
4004 case nir_intrinsic_memory_barrier_atomic_counter
:
4005 case nir_intrinsic_memory_barrier_buffer
:
4006 case nir_intrinsic_memory_barrier_image
:
4007 case nir_intrinsic_memory_barrier
: {
4008 const fs_builder ubld
= bld
.group(8, 0);
4009 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4010 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
4011 ->size_written
= 2 * REG_SIZE
;
4015 case nir_intrinsic_shader_clock
: {
4016 /* We cannot do anything if there is an event, so ignore it for now */
4017 const fs_reg shader_clock
= get_timestamp(bld
);
4018 const fs_reg srcs
[] = { component(shader_clock
, 0),
4019 component(shader_clock
, 1) };
4020 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4024 case nir_intrinsic_image_samples
:
4025 /* The driver does not support multi-sampled images. */
4026 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4029 case nir_intrinsic_load_uniform
: {
4030 /* Offsets are in bytes but they should always aligned to
4033 assert(instr
->const_index
[0] % 4 == 0 ||
4034 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4036 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4038 if (nir_src_is_const(instr
->src
[0])) {
4039 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4040 assert(load_offset
% type_sz(dest
.type
) == 0);
4041 /* For 16-bit types we add the module of the const_index[0]
4042 * offset to access to not 32-bit aligned element
4044 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4046 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4047 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4050 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4051 BRW_REGISTER_TYPE_UD
);
4053 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4054 * go past the end of the uniform. In order to keep the n'th
4055 * component from running past, we subtract off the size of all but
4056 * one component of the vector.
4058 assert(instr
->const_index
[1] >=
4059 instr
->num_components
* (int) type_sz(dest
.type
));
4060 unsigned read_size
= instr
->const_index
[1] -
4061 (instr
->num_components
- 1) * type_sz(dest
.type
);
4063 bool supports_64bit_indirects
=
4064 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4066 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4067 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4068 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4069 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4070 indirect
, brw_imm_ud(read_size
));
4073 const unsigned num_mov_indirects
=
4074 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4075 /* We read a little bit less per MOV INDIRECT, as they are now
4076 * 32-bits ones instead of 64-bit. Fix read_size then.
4078 const unsigned read_size_32bit
= read_size
-
4079 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4080 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4081 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4082 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4083 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4084 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4085 indirect
, brw_imm_ud(read_size_32bit
));
4093 case nir_intrinsic_load_ubo
: {
4095 if (nir_src_is_const(instr
->src
[0])) {
4096 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4097 nir_src_as_uint(instr
->src
[0]);
4098 surf_index
= brw_imm_ud(index
);
4100 /* The block index is not a constant. Evaluate the index expression
4101 * per-channel and add the base UBO index; we have to select a value
4102 * from any live channel.
4104 surf_index
= vgrf(glsl_type::uint_type
);
4105 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4106 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4107 surf_index
= bld
.emit_uniformize(surf_index
);
4110 if (!nir_src_is_const(instr
->src
[1])) {
4111 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4112 BRW_REGISTER_TYPE_UD
);
4114 for (int i
= 0; i
< instr
->num_components
; i
++)
4115 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4116 base_offset
, i
* type_sz(dest
.type
));
4118 /* Even if we are loading doubles, a pull constant load will load
4119 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4120 * need to load a full dvec4 we will have to emit 2 loads. This is
4121 * similar to demote_pull_constants(), except that in that case we
4122 * see individual accesses to each component of the vector and then
4123 * we let CSE deal with duplicate loads. Here we see a vector access
4124 * and we have to split it if necessary.
4126 const unsigned type_size
= type_sz(dest
.type
);
4127 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4129 /* See if we've selected this as a push constant candidate */
4130 if (nir_src_is_const(instr
->src
[0])) {
4131 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4132 const unsigned offset_256b
= load_offset
/ 32;
4135 for (int i
= 0; i
< 4; i
++) {
4136 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4137 if (range
->block
== ubo_block
&&
4138 offset_256b
>= range
->start
&&
4139 offset_256b
< range
->start
+ range
->length
) {
4141 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4142 push_reg
.offset
= load_offset
- 32 * range
->start
;
4147 if (push_reg
.file
!= BAD_FILE
) {
4148 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4149 bld
.MOV(offset(dest
, bld
, i
),
4150 byte_offset(push_reg
, i
* type_size
));
4156 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4157 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4158 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4160 for (unsigned c
= 0; c
< instr
->num_components
;) {
4161 const unsigned base
= load_offset
+ c
* type_size
;
4162 /* Number of usable components in the next block-aligned load. */
4163 const unsigned count
= MIN2(instr
->num_components
- c
,
4164 (block_sz
- base
% block_sz
) / type_size
);
4166 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4167 packed_consts
, surf_index
,
4168 brw_imm_ud(base
& ~(block_sz
- 1)));
4170 const fs_reg consts
=
4171 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4174 for (unsigned d
= 0; d
< count
; d
++)
4175 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4183 case nir_intrinsic_load_global
: {
4184 assert(devinfo
->gen
>= 8);
4186 if (nir_intrinsic_align(instr
) >= 4) {
4187 assert(nir_dest_bit_size(instr
->dest
) == 32);
4188 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4190 get_nir_src(instr
->src
[0]), /* Address */
4191 fs_reg(), /* No source data */
4192 brw_imm_ud(instr
->num_components
));
4193 inst
->size_written
= instr
->num_components
*
4194 inst
->dst
.component_size(inst
->exec_size
);
4196 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4197 assert(bit_size
<= 32);
4198 assert(nir_dest_num_components(instr
->dest
) == 1);
4199 brw_reg_type data_type
=
4200 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4201 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4202 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4204 get_nir_src(instr
->src
[0]), /* Address */
4205 fs_reg(), /* No source data */
4206 brw_imm_ud(bit_size
));
4207 bld
.MOV(retype(dest
, data_type
), tmp
);
4212 case nir_intrinsic_store_global
:
4213 assert(devinfo
->gen
>= 8);
4215 if (stage
== MESA_SHADER_FRAGMENT
)
4216 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4218 if (nir_intrinsic_align(instr
) >= 4) {
4219 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4220 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4222 get_nir_src(instr
->src
[1]), /* Address */
4223 get_nir_src(instr
->src
[0]), /* Data */
4224 brw_imm_ud(instr
->num_components
));
4226 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4227 assert(bit_size
<= 32);
4228 assert(nir_src_num_components(instr
->src
[0]) == 1);
4229 brw_reg_type data_type
=
4230 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4231 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4232 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4233 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4235 get_nir_src(instr
->src
[1]), /* Address */
4237 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4241 case nir_intrinsic_global_atomic_add
:
4242 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4244 case nir_intrinsic_global_atomic_imin
:
4245 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4247 case nir_intrinsic_global_atomic_umin
:
4248 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4250 case nir_intrinsic_global_atomic_imax
:
4251 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4253 case nir_intrinsic_global_atomic_umax
:
4254 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4256 case nir_intrinsic_global_atomic_and
:
4257 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4259 case nir_intrinsic_global_atomic_or
:
4260 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4262 case nir_intrinsic_global_atomic_xor
:
4263 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4265 case nir_intrinsic_global_atomic_exchange
:
4266 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4268 case nir_intrinsic_global_atomic_comp_swap
:
4269 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4271 case nir_intrinsic_global_atomic_fmin
:
4272 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4274 case nir_intrinsic_global_atomic_fmax
:
4275 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4277 case nir_intrinsic_global_atomic_fcomp_swap
:
4278 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4281 case nir_intrinsic_load_ssbo
: {
4282 assert(devinfo
->gen
>= 7);
4284 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4285 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4286 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4287 get_nir_ssbo_intrinsic_index(bld
, instr
);
4288 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4289 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4291 /* Make dest unsigned because that's what the temporary will be */
4292 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4294 /* Read the vector */
4295 if (nir_intrinsic_align(instr
) >= 4) {
4296 assert(nir_dest_bit_size(instr
->dest
) == 32);
4297 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4299 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4300 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4301 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4303 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4304 assert(nir_dest_num_components(instr
->dest
) == 1);
4305 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4307 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4308 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4309 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4310 bld
.MOV(dest
, read_result
);
4315 case nir_intrinsic_store_ssbo
: {
4316 assert(devinfo
->gen
>= 7);
4318 if (stage
== MESA_SHADER_FRAGMENT
)
4319 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4321 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4322 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4323 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4324 get_nir_ssbo_intrinsic_index(bld
, instr
);
4325 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4326 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4328 fs_reg data
= get_nir_src(instr
->src
[0]);
4329 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4331 assert(nir_intrinsic_write_mask(instr
) ==
4332 (1u << instr
->num_components
) - 1);
4333 if (nir_intrinsic_align(instr
) >= 4) {
4334 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4335 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4336 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4337 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4338 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4339 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4341 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4342 assert(nir_src_num_components(instr
->src
[0]) == 1);
4343 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4345 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4346 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4348 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4349 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4354 case nir_intrinsic_store_output
: {
4355 fs_reg src
= get_nir_src(instr
->src
[0]);
4357 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4358 unsigned num_components
= instr
->num_components
;
4359 unsigned first_component
= nir_intrinsic_component(instr
);
4360 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4361 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4362 num_components
*= 2;
4365 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4366 4 * store_offset
), src
.type
);
4367 for (unsigned j
= 0; j
< num_components
; j
++) {
4368 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4369 offset(src
, bld
, j
));
4374 case nir_intrinsic_ssbo_atomic_add
:
4375 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4377 case nir_intrinsic_ssbo_atomic_imin
:
4378 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4380 case nir_intrinsic_ssbo_atomic_umin
:
4381 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4383 case nir_intrinsic_ssbo_atomic_imax
:
4384 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4386 case nir_intrinsic_ssbo_atomic_umax
:
4387 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4389 case nir_intrinsic_ssbo_atomic_and
:
4390 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4392 case nir_intrinsic_ssbo_atomic_or
:
4393 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4395 case nir_intrinsic_ssbo_atomic_xor
:
4396 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4398 case nir_intrinsic_ssbo_atomic_exchange
:
4399 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4401 case nir_intrinsic_ssbo_atomic_comp_swap
:
4402 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4404 case nir_intrinsic_ssbo_atomic_fmin
:
4405 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4407 case nir_intrinsic_ssbo_atomic_fmax
:
4408 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4410 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4411 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4414 case nir_intrinsic_get_buffer_size
: {
4415 assert(nir_src_num_components(instr
->src
[0]) == 1);
4416 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4417 nir_src_as_uint(instr
->src
[0]) : 0;
4419 /* A resinfo's sampler message is used to get the buffer size. The
4420 * SIMD8's writeback message consists of four registers and SIMD16's
4421 * writeback message consists of 8 destination registers (two per each
4422 * component). Because we are only interested on the first channel of
4423 * the first returned component, where resinfo returns the buffer size
4424 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4425 * the dispatch width.
4427 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4428 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4429 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4432 ubld
.MOV(src_payload
, brw_imm_d(0));
4434 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4435 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4436 src_payload
, brw_imm_ud(index
));
4437 inst
->header_size
= 0;
4439 inst
->size_written
= 4 * REG_SIZE
;
4441 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4443 * "Out-of-bounds checking is always performed at a DWord granularity. If
4444 * any part of the DWord is out-of-bounds then the whole DWord is
4445 * considered out-of-bounds."
4447 * This implies that types with size smaller than 4-bytes need to be
4448 * padded if they don't complete the last dword of the buffer. But as we
4449 * need to maintain the original size we need to reverse the padding
4450 * calculation to return the correct size to know the number of elements
4451 * of an unsized array. As we stored in the last two bits of the surface
4452 * size the needed padding for the buffer, we calculate here the
4453 * original buffer_size reversing the surface_size calculation:
4455 * surface_size = isl_align(buffer_size, 4) +
4456 * (isl_align(buffer_size) - buffer_size)
4458 * buffer_size = surface_size & ~3 - surface_size & 3
4461 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4462 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4463 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4465 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4466 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4467 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4469 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4473 case nir_intrinsic_load_subgroup_invocation
:
4474 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4475 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4478 case nir_intrinsic_load_subgroup_eq_mask
:
4479 case nir_intrinsic_load_subgroup_ge_mask
:
4480 case nir_intrinsic_load_subgroup_gt_mask
:
4481 case nir_intrinsic_load_subgroup_le_mask
:
4482 case nir_intrinsic_load_subgroup_lt_mask
:
4483 unreachable("not reached");
4485 case nir_intrinsic_vote_any
: {
4486 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4488 /* The any/all predicates do not consider channel enables. To prevent
4489 * dead channels from affecting the result, we initialize the flag with
4490 * with the identity value for the logical operation.
4492 if (dispatch_width
== 32) {
4493 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4494 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4497 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4499 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4501 /* For some reason, the any/all predicates don't work properly with
4502 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4503 * doesn't read the correct subset of the flag register and you end up
4504 * getting garbage in the second half. Work around this by using a pair
4505 * of 1-wide MOVs and scattering the result.
4507 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4508 ubld
.MOV(res1
, brw_imm_d(0));
4509 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4510 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4511 BRW_PREDICATE_ALIGN1_ANY32H
,
4512 ubld
.MOV(res1
, brw_imm_d(-1)));
4514 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4517 case nir_intrinsic_vote_all
: {
4518 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4520 /* The any/all predicates do not consider channel enables. To prevent
4521 * dead channels from affecting the result, we initialize the flag with
4522 * with the identity value for the logical operation.
4524 if (dispatch_width
== 32) {
4525 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4526 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4527 brw_imm_ud(0xffffffff));
4529 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4531 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4533 /* For some reason, the any/all predicates don't work properly with
4534 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4535 * doesn't read the correct subset of the flag register and you end up
4536 * getting garbage in the second half. Work around this by using a pair
4537 * of 1-wide MOVs and scattering the result.
4539 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4540 ubld
.MOV(res1
, brw_imm_d(0));
4541 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4542 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4543 BRW_PREDICATE_ALIGN1_ALL32H
,
4544 ubld
.MOV(res1
, brw_imm_d(-1)));
4546 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4549 case nir_intrinsic_vote_feq
:
4550 case nir_intrinsic_vote_ieq
: {
4551 fs_reg value
= get_nir_src(instr
->src
[0]);
4552 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4553 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4554 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4555 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4558 fs_reg uniformized
= bld
.emit_uniformize(value
);
4559 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4561 /* The any/all predicates do not consider channel enables. To prevent
4562 * dead channels from affecting the result, we initialize the flag with
4563 * with the identity value for the logical operation.
4565 if (dispatch_width
== 32) {
4566 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4567 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4568 brw_imm_ud(0xffffffff));
4570 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4572 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4574 /* For some reason, the any/all predicates don't work properly with
4575 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4576 * doesn't read the correct subset of the flag register and you end up
4577 * getting garbage in the second half. Work around this by using a pair
4578 * of 1-wide MOVs and scattering the result.
4580 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4581 ubld
.MOV(res1
, brw_imm_d(0));
4582 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4583 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4584 BRW_PREDICATE_ALIGN1_ALL32H
,
4585 ubld
.MOV(res1
, brw_imm_d(-1)));
4587 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4591 case nir_intrinsic_ballot
: {
4592 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4593 BRW_REGISTER_TYPE_UD
);
4594 struct brw_reg flag
= brw_flag_reg(0, 0);
4595 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4596 * as f0.0. This is a problem for fragment programs as we currently use
4597 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4598 * programs yet so this isn't a problem. When we do, something will
4601 if (dispatch_width
== 32)
4602 flag
.type
= BRW_REGISTER_TYPE_UD
;
4604 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4605 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4607 if (instr
->dest
.ssa
.bit_size
> 32) {
4608 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4610 dest
.type
= BRW_REGISTER_TYPE_UD
;
4612 bld
.MOV(dest
, flag
);
4616 case nir_intrinsic_read_invocation
: {
4617 const fs_reg value
= get_nir_src(instr
->src
[0]);
4618 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4619 fs_reg tmp
= bld
.vgrf(value
.type
);
4621 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4622 bld
.emit_uniformize(invocation
));
4624 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4628 case nir_intrinsic_read_first_invocation
: {
4629 const fs_reg value
= get_nir_src(instr
->src
[0]);
4630 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4634 case nir_intrinsic_shuffle
: {
4635 const fs_reg value
= get_nir_src(instr
->src
[0]);
4636 const fs_reg index
= get_nir_src(instr
->src
[1]);
4638 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4642 case nir_intrinsic_first_invocation
: {
4643 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4644 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4645 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4646 fs_reg(component(tmp
, 0)));
4650 case nir_intrinsic_quad_broadcast
: {
4651 const fs_reg value
= get_nir_src(instr
->src
[0]);
4652 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4654 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4655 value
, brw_imm_ud(index
), brw_imm_ud(4));
4659 case nir_intrinsic_quad_swap_horizontal
: {
4660 const fs_reg value
= get_nir_src(instr
->src
[0]);
4661 const fs_reg tmp
= bld
.vgrf(value
.type
);
4662 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4664 const fs_reg src_left
= horiz_stride(value
, 2);
4665 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4666 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4667 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4669 ubld
.MOV(tmp_left
, src_right
);
4670 ubld
.MOV(tmp_right
, src_left
);
4672 bld
.MOV(retype(dest
, value
.type
), tmp
);
4676 case nir_intrinsic_quad_swap_vertical
: {
4677 const fs_reg value
= get_nir_src(instr
->src
[0]);
4678 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4679 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4680 const fs_reg tmp
= bld
.vgrf(value
.type
);
4681 const fs_builder ubld
= bld
.exec_all();
4682 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4683 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4684 bld
.MOV(retype(dest
, value
.type
), tmp
);
4686 /* For larger data types, we have to either emit dispatch_width many
4687 * MOVs or else fall back to doing indirects.
4689 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4690 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4692 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4697 case nir_intrinsic_quad_swap_diagonal
: {
4698 const fs_reg value
= get_nir_src(instr
->src
[0]);
4699 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4700 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4701 const fs_reg tmp
= bld
.vgrf(value
.type
);
4702 const fs_builder ubld
= bld
.exec_all();
4703 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4704 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4705 bld
.MOV(retype(dest
, value
.type
), tmp
);
4707 /* For larger data types, we have to either emit dispatch_width many
4708 * MOVs or else fall back to doing indirects.
4710 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4711 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4713 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4718 case nir_intrinsic_reduce
: {
4719 fs_reg src
= get_nir_src(instr
->src
[0]);
4720 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4721 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4722 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4723 cluster_size
= dispatch_width
;
4725 /* Figure out the source type */
4726 src
.type
= brw_type_for_nir_type(devinfo
,
4727 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4728 nir_src_bit_size(instr
->src
[0])));
4730 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4731 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4732 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4734 /* Set up a register for all of our scratching around and initialize it
4735 * to reduction operation's identity value.
4737 fs_reg scan
= bld
.vgrf(src
.type
);
4738 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4740 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4742 dest
.type
= src
.type
;
4743 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4744 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4745 * the distance between clusters is at least 2 GRFs. In this case,
4746 * we don't need the weird striding of the CLUSTER_BROADCAST
4747 * instruction and can just do regular MOVs.
4749 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4750 const unsigned groups
=
4751 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4752 const unsigned group_size
= dispatch_width
/ groups
;
4753 for (unsigned i
= 0; i
< groups
; i
++) {
4754 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4755 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4756 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4757 component(scan
, comp
));
4760 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4761 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4766 case nir_intrinsic_inclusive_scan
:
4767 case nir_intrinsic_exclusive_scan
: {
4768 fs_reg src
= get_nir_src(instr
->src
[0]);
4769 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4771 /* Figure out the source type */
4772 src
.type
= brw_type_for_nir_type(devinfo
,
4773 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4774 nir_src_bit_size(instr
->src
[0])));
4776 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4777 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4778 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4780 /* Set up a register for all of our scratching around and initialize it
4781 * to reduction operation's identity value.
4783 fs_reg scan
= bld
.vgrf(src
.type
);
4784 const fs_builder allbld
= bld
.exec_all();
4785 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4787 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4788 /* Exclusive scan is a bit harder because we have to do an annoying
4789 * shift of the contents before we can begin. To make things worse,
4790 * we can't do this with a normal stride; we have to use indirects.
4792 fs_reg shifted
= bld
.vgrf(src
.type
);
4793 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4794 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4796 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4797 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4801 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4803 bld
.MOV(retype(dest
, src
.type
), scan
);
4807 case nir_intrinsic_begin_invocation_interlock
: {
4808 const fs_builder ubld
= bld
.group(8, 0);
4809 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4811 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4817 case nir_intrinsic_end_invocation_interlock
: {
4818 /* We don't need to do anything here */
4823 unreachable("unknown intrinsic");
4828 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4829 int op
, nir_intrinsic_instr
*instr
)
4831 if (stage
== MESA_SHADER_FRAGMENT
)
4832 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4835 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4836 dest
= get_nir_dest(instr
->dest
);
4838 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4839 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4840 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4841 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4842 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4845 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4846 data
= get_nir_src(instr
->src
[2]);
4848 if (op
== BRW_AOP_CMPWR
) {
4849 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4850 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4851 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4854 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4856 /* Emit the actual atomic operation */
4858 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4859 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4863 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4864 int op
, nir_intrinsic_instr
*instr
)
4866 if (stage
== MESA_SHADER_FRAGMENT
)
4867 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4870 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4871 dest
= get_nir_dest(instr
->dest
);
4873 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4874 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4875 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4876 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4877 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4879 fs_reg data
= get_nir_src(instr
->src
[2]);
4880 if (op
== BRW_AOP_FCMPWR
) {
4881 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4882 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4883 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4886 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4888 /* Emit the actual atomic operation */
4890 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4891 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4895 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4896 int op
, nir_intrinsic_instr
*instr
)
4899 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4900 dest
= get_nir_dest(instr
->dest
);
4902 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4903 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4904 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4905 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4908 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4909 data
= get_nir_src(instr
->src
[1]);
4910 if (op
== BRW_AOP_CMPWR
) {
4911 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4912 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4913 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4916 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4918 /* Get the offset */
4919 if (nir_src_is_const(instr
->src
[0])) {
4920 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4921 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4923 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4924 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4925 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4926 brw_imm_ud(instr
->const_index
[0]));
4929 /* Emit the actual atomic operation operation */
4931 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4932 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4936 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4937 int op
, nir_intrinsic_instr
*instr
)
4940 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4941 dest
= get_nir_dest(instr
->dest
);
4943 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4944 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4945 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4946 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4948 fs_reg data
= get_nir_src(instr
->src
[1]);
4949 if (op
== BRW_AOP_FCMPWR
) {
4950 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4951 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4952 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4955 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4957 /* Get the offset */
4958 if (nir_src_is_const(instr
->src
[0])) {
4959 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4960 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4962 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4963 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4964 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4965 brw_imm_ud(instr
->const_index
[0]));
4968 /* Emit the actual atomic operation operation */
4970 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4971 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4975 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
4976 int op
, nir_intrinsic_instr
*instr
)
4978 if (stage
== MESA_SHADER_FRAGMENT
)
4979 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4982 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4983 dest
= get_nir_dest(instr
->dest
);
4985 fs_reg addr
= get_nir_src(instr
->src
[0]);
4988 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4989 data
= get_nir_src(instr
->src
[1]);
4991 if (op
== BRW_AOP_CMPWR
) {
4992 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4993 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4994 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4998 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4999 dest
, addr
, data
, brw_imm_ud(op
));
5003 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5004 int op
, nir_intrinsic_instr
*instr
)
5006 if (stage
== MESA_SHADER_FRAGMENT
)
5007 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5009 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5010 fs_reg dest
= get_nir_dest(instr
->dest
);
5012 fs_reg addr
= get_nir_src(instr
->src
[0]);
5014 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5015 fs_reg data
= get_nir_src(instr
->src
[1]);
5017 if (op
== BRW_AOP_FCMPWR
) {
5018 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5019 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5020 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5024 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5025 dest
, addr
, data
, brw_imm_ud(op
));
5029 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5031 unsigned texture
= instr
->texture_index
;
5032 unsigned sampler
= instr
->sampler_index
;
5034 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5036 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5037 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5039 int lod_components
= 0;
5041 /* The hardware requires a LOD for buffer textures */
5042 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5043 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5045 uint32_t header_bits
= 0;
5046 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5047 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5048 switch (instr
->src
[i
].src_type
) {
5049 case nir_tex_src_bias
:
5050 srcs
[TEX_LOGICAL_SRC_LOD
] =
5051 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5053 case nir_tex_src_comparator
:
5054 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5056 case nir_tex_src_coord
:
5057 switch (instr
->op
) {
5059 case nir_texop_txf_ms
:
5060 case nir_texop_txf_ms_mcs
:
5061 case nir_texop_samples_identical
:
5062 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5065 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5069 case nir_tex_src_ddx
:
5070 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5071 lod_components
= nir_tex_instr_src_size(instr
, i
);
5073 case nir_tex_src_ddy
:
5074 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5076 case nir_tex_src_lod
:
5077 switch (instr
->op
) {
5079 srcs
[TEX_LOGICAL_SRC_LOD
] =
5080 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5083 srcs
[TEX_LOGICAL_SRC_LOD
] =
5084 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5087 srcs
[TEX_LOGICAL_SRC_LOD
] =
5088 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5092 case nir_tex_src_min_lod
:
5093 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5094 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5096 case nir_tex_src_ms_index
:
5097 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5100 case nir_tex_src_offset
: {
5101 uint32_t offset_bits
= 0;
5102 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5103 header_bits
|= offset_bits
;
5105 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5106 retype(src
, BRW_REGISTER_TYPE_D
);
5111 case nir_tex_src_projector
:
5112 unreachable("should be lowered");
5114 case nir_tex_src_texture_offset
: {
5115 /* Emit code to evaluate the actual indexing expression */
5116 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5117 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5118 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5122 case nir_tex_src_sampler_offset
: {
5123 /* Emit code to evaluate the actual indexing expression */
5124 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5125 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5126 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5130 case nir_tex_src_ms_mcs
:
5131 assert(instr
->op
== nir_texop_txf_ms
);
5132 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5135 case nir_tex_src_plane
: {
5136 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5137 const uint32_t texture_index
=
5138 instr
->texture_index
+
5139 stage_prog_data
->binding_table
.plane_start
[plane
] -
5140 stage_prog_data
->binding_table
.texture_start
;
5142 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5147 unreachable("unknown texture source");
5151 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5152 (instr
->op
== nir_texop_txf_ms
||
5153 instr
->op
== nir_texop_samples_identical
)) {
5154 if (devinfo
->gen
>= 7 &&
5155 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5156 srcs
[TEX_LOGICAL_SRC_MCS
] =
5157 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5158 instr
->coord_components
,
5159 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5161 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5165 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5166 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5168 bool shader_supports_implicit_lod
= stage
== MESA_SHADER_FRAGMENT
||
5169 (stage
== MESA_SHADER_COMPUTE
&&
5170 nir
->info
.cs
.derivative_group
!= DERIVATIVE_GROUP_NONE
);
5173 switch (instr
->op
) {
5175 opcode
= shader_supports_implicit_lod
?
5176 SHADER_OPCODE_TEX_LOGICAL
: SHADER_OPCODE_TXL_LOGICAL
;
5179 opcode
= FS_OPCODE_TXB_LOGICAL
;
5182 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5185 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5188 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5190 case nir_texop_txf_ms
:
5191 if ((key_tex
->msaa_16
& (1 << sampler
)))
5192 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5194 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5196 case nir_texop_txf_ms_mcs
:
5197 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5199 case nir_texop_query_levels
:
5201 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5204 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5207 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5208 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5210 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5212 case nir_texop_texture_samples
:
5213 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5215 case nir_texop_samples_identical
: {
5216 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5218 /* If mcs is an immediate value, it means there is no MCS. In that case
5219 * just return false.
5221 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5222 bld
.MOV(dst
, brw_imm_ud(0u));
5223 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5224 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5225 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5226 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5227 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5229 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5230 BRW_CONDITIONAL_EQ
);
5235 unreachable("unknown texture opcode");
5238 if (instr
->op
== nir_texop_tg4
) {
5239 if (instr
->component
== 1 &&
5240 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5241 /* gather4 sampler is broken for green channel on RG32F --
5242 * we must ask for blue instead.
5244 header_bits
|= 2 << 16;
5246 header_bits
|= instr
->component
<< 16;
5250 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5251 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5252 inst
->offset
= header_bits
;
5254 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5255 if (devinfo
->gen
>= 9 &&
5256 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5257 unsigned write_mask
= instr
->dest
.is_ssa
?
5258 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5259 (1 << dest_size
) - 1;
5260 assert(write_mask
!= 0); /* dead code should have been eliminated */
5261 inst
->size_written
= util_last_bit(write_mask
) *
5262 inst
->dst
.component_size(inst
->exec_size
);
5264 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5267 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5268 inst
->shadow_compare
= true;
5270 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5271 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5274 for (unsigned i
= 0; i
< dest_size
; i
++)
5275 nir_dest
[i
] = offset(dst
, bld
, i
);
5277 if (instr
->op
== nir_texop_query_levels
) {
5278 /* # levels is in .w */
5279 nir_dest
[0] = offset(dst
, bld
, 3);
5280 } else if (instr
->op
== nir_texop_txs
&&
5281 dest_size
>= 3 && devinfo
->gen
< 7) {
5282 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5283 fs_reg depth
= offset(dst
, bld
, 2);
5284 nir_dest
[2] = vgrf(glsl_type::int_type
);
5285 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5288 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5292 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5294 switch (instr
->type
) {
5295 case nir_jump_break
:
5296 bld
.emit(BRW_OPCODE_BREAK
);
5298 case nir_jump_continue
:
5299 bld
.emit(BRW_OPCODE_CONTINUE
);
5301 case nir_jump_return
:
5303 unreachable("unknown jump");
5308 * This helper takes a source register and un/shuffles it into the destination
5311 * If source type size is smaller than destination type size the operation
5312 * needed is a component shuffle. The opposite case would be an unshuffle. If
5313 * source/destination type size is equal a shuffle is done that would be
5314 * equivalent to a simple MOV.
5316 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5317 * components .xyz 16-bit vector on SIMD8 would be.
5319 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5320 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5322 * This helper will return the following 2 32-bit components with the 16-bit
5325 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5326 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5328 * For unshuffle, the example would be the opposite, a 64-bit type source
5329 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5332 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5333 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5334 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5335 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5337 * The returned result would be the following 4 32-bit components unshuffled:
5339 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5340 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5341 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5342 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5344 * - Source and destination register must not be overlapped.
5345 * - components units are measured in terms of the smaller type between
5346 * source and destination because we are un/shuffling the smaller
5347 * components from/into the bigger ones.
5348 * - first_component parameter allows skipping source components.
5351 shuffle_src_to_dst(const fs_builder
&bld
,
5354 uint32_t first_component
,
5355 uint32_t components
)
5357 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5358 assert(!regions_overlap(dst
,
5359 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5360 offset(src
, bld
, first_component
),
5361 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5362 for (unsigned i
= 0; i
< components
; i
++) {
5363 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5364 offset(src
, bld
, i
+ first_component
));
5366 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5367 /* Source is shuffled into destination */
5368 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5369 assert(!regions_overlap(dst
,
5370 type_sz(dst
.type
) * bld
.dispatch_width() *
5371 DIV_ROUND_UP(components
, size_ratio
),
5372 offset(src
, bld
, first_component
),
5373 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5375 brw_reg_type shuffle_type
=
5376 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5377 BRW_REGISTER_TYPE_D
);
5378 for (unsigned i
= 0; i
< components
; i
++) {
5379 fs_reg shuffle_component_i
=
5380 subscript(offset(dst
, bld
, i
/ size_ratio
),
5381 shuffle_type
, i
% size_ratio
);
5382 bld
.MOV(shuffle_component_i
,
5383 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5386 /* Source is unshuffled into destination */
5387 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5388 assert(!regions_overlap(dst
,
5389 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5390 offset(src
, bld
, first_component
/ size_ratio
),
5391 type_sz(src
.type
) * bld
.dispatch_width() *
5392 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5395 brw_reg_type shuffle_type
=
5396 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5397 BRW_REGISTER_TYPE_D
);
5398 for (unsigned i
= 0; i
< components
; i
++) {
5399 fs_reg shuffle_component_i
=
5400 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5401 shuffle_type
, (first_component
+ i
) % size_ratio
);
5402 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5403 shuffle_component_i
);
5409 shuffle_from_32bit_read(const fs_builder
&bld
,
5412 uint32_t first_component
,
5413 uint32_t components
)
5415 assert(type_sz(src
.type
) == 4);
5417 /* This function takes components in units of the destination type while
5418 * shuffle_src_to_dst takes components in units of the smallest type
5420 if (type_sz(dst
.type
) > 4) {
5421 assert(type_sz(dst
.type
) == 8);
5422 first_component
*= 2;
5426 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5430 shuffle_for_32bit_write(const fs_builder
&bld
,
5432 uint32_t first_component
,
5433 uint32_t components
)
5435 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5436 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5437 /* This function takes components in units of the source type while
5438 * shuffle_src_to_dst takes components in units of the smallest type
5440 if (type_sz(src
.type
) > 4) {
5441 assert(type_sz(src
.type
) == 8);
5442 first_component
*= 2;
5446 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5452 setup_imm_df(const fs_builder
&bld
, double v
)
5454 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5455 assert(devinfo
->gen
>= 7);
5457 if (devinfo
->gen
>= 8)
5458 return brw_imm_df(v
);
5460 /* gen7.5 does not support DF immediates straighforward but the DIM
5461 * instruction allows to set the 64-bit immediate value.
5463 if (devinfo
->is_haswell
) {
5464 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5465 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5466 ubld
.DIM(dst
, brw_imm_df(v
));
5467 return component(dst
, 0);
5470 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5471 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5472 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5474 * Alternatively, we could also produce a normal VGRF (without stride 0)
5475 * by writing to all the channels in the VGRF, however, that would hit the
5476 * gen7 bug where we have to split writes that span more than 1 register
5477 * into instructions with a width of 4 (otherwise the write to the second
5478 * register written runs into an execmask hardware bug) which isn't very
5491 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5492 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5493 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5494 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5496 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5500 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5502 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5503 bld
.MOV(tmp
, brw_imm_w(v
));
5508 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5510 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5511 bld
.MOV(tmp
, brw_imm_uw(v
));