2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 nir_foreach_variable(var
, &nir
->outputs
) {
71 const int loc
= var
->data
.driver_location
;
72 if (outputs
[loc
].file
== BAD_FILE
) {
73 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
[loc
]);
74 for (unsigned i
= 0; i
< vec4s
[loc
]; i
++) {
75 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
82 fs_visitor::nir_setup_uniforms()
84 /* Only the first compile gets to set up uniforms. */
85 if (push_constant_loc
) {
86 assert(pull_constant_loc
);
90 uniforms
= nir
->num_uniforms
/ 4;
92 if (stage
== MESA_SHADER_COMPUTE
) {
93 /* Add a uniform for the thread local id. It must be the last uniform
96 assert(uniforms
== prog_data
->nr_params
);
97 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
98 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
99 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
104 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
108 nir_foreach_instr(instr
, block
) {
109 if (instr
->type
!= nir_instr_type_intrinsic
)
112 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
113 switch (intrin
->intrinsic
) {
114 case nir_intrinsic_load_vertex_id
:
115 case nir_intrinsic_load_base_vertex
:
116 unreachable("should be lowered by nir_lower_system_values().");
118 case nir_intrinsic_load_vertex_id_zero_base
:
119 case nir_intrinsic_load_is_indexed_draw
:
120 case nir_intrinsic_load_first_vertex
:
121 case nir_intrinsic_load_instance_id
:
122 case nir_intrinsic_load_base_instance
:
123 case nir_intrinsic_load_draw_id
:
124 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
126 case nir_intrinsic_load_invocation_id
:
127 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
129 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
130 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
131 if (reg
->file
== BAD_FILE
) {
132 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
133 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
134 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
135 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
140 case nir_intrinsic_load_sample_pos
:
141 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
142 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
143 if (reg
->file
== BAD_FILE
)
144 *reg
= *v
->emit_samplepos_setup();
147 case nir_intrinsic_load_sample_id
:
148 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_sampleid_setup();
154 case nir_intrinsic_load_sample_mask_in
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 assert(v
->devinfo
->gen
>= 7);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_samplemaskin_setup();
162 case nir_intrinsic_load_work_group_id
:
163 assert(v
->stage
== MESA_SHADER_COMPUTE
);
164 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
165 if (reg
->file
== BAD_FILE
)
166 *reg
= *v
->emit_cs_work_group_id_setup();
169 case nir_intrinsic_load_helper_invocation
:
170 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
171 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
172 if (reg
->file
== BAD_FILE
) {
173 const fs_builder abld
=
174 v
->bld
.annotate("gl_HelperInvocation", NULL
);
176 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
177 * pixel mask is in g1.7 of the thread payload.
179 * We move the per-channel pixel enable bit to the low bit of each
180 * channel by shifting the byte containing the pixel mask by the
181 * vector immediate 0x76543210UV.
183 * The region of <1,8,0> reads only 1 byte (the pixel masks for
184 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
185 * masks for 2 and 3) in SIMD16.
187 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
189 stride(byte_offset(retype(brw_vec1_grf(1, 0),
190 BRW_REGISTER_TYPE_UB
), 28),
192 brw_imm_v(0x76543210));
194 /* A set bit in the pixel mask means the channel is enabled, but
195 * that is the opposite of gl_HelperInvocation so we need to invert
198 * The negate source-modifier bit of logical instructions on Gen8+
199 * performs 1's complement negation, so we can use that instead of
202 fs_reg inverted
= negate(shifted
);
203 if (v
->devinfo
->gen
< 8) {
204 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
205 abld
.NOT(inverted
, shifted
);
208 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
209 * with 1 and negating.
211 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
212 abld
.AND(anded
, inverted
, brw_imm_uw(1));
214 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
215 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
229 fs_visitor::nir_emit_system_values()
231 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
232 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
233 nir_system_values
[i
] = fs_reg();
236 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
237 * never end up using it.
240 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
241 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
242 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
244 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
245 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
246 if (dispatch_width
> 8)
247 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
248 if (dispatch_width
> 16) {
249 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
250 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
254 nir_foreach_function(function
, nir
) {
255 assert(strcmp(function
->name
, "main") == 0);
256 assert(function
->impl
);
257 nir_foreach_block(block
, function
->impl
) {
258 emit_system_values_block(block
, this);
264 * Returns a type based on a reference_type (word, float, half-float) and a
267 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
269 * @FIXME: 64-bit return types are always DF on integer types to maintain
270 * compability with uses of DF previously to the introduction of int64
274 brw_reg_type_from_bit_size(const unsigned bit_size
,
275 const brw_reg_type reference_type
)
277 switch(reference_type
) {
278 case BRW_REGISTER_TYPE_HF
:
279 case BRW_REGISTER_TYPE_F
:
280 case BRW_REGISTER_TYPE_DF
:
283 return BRW_REGISTER_TYPE_HF
;
285 return BRW_REGISTER_TYPE_F
;
287 return BRW_REGISTER_TYPE_DF
;
289 unreachable("Invalid bit size");
291 case BRW_REGISTER_TYPE_W
:
292 case BRW_REGISTER_TYPE_D
:
293 case BRW_REGISTER_TYPE_Q
:
296 return BRW_REGISTER_TYPE_W
;
298 return BRW_REGISTER_TYPE_D
;
300 return BRW_REGISTER_TYPE_Q
;
302 unreachable("Invalid bit size");
304 case BRW_REGISTER_TYPE_UW
:
305 case BRW_REGISTER_TYPE_UD
:
306 case BRW_REGISTER_TYPE_UQ
:
309 return BRW_REGISTER_TYPE_UW
;
311 return BRW_REGISTER_TYPE_UD
;
313 return BRW_REGISTER_TYPE_UQ
;
315 unreachable("Invalid bit size");
318 unreachable("Unknown type");
323 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
325 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
326 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
327 nir_locals
[i
] = fs_reg();
330 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
331 unsigned array_elems
=
332 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
333 unsigned size
= array_elems
* reg
->num_components
;
334 const brw_reg_type reg_type
=
335 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
336 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
339 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
342 nir_emit_cf_list(&impl
->body
);
346 fs_visitor::nir_emit_cf_list(exec_list
*list
)
348 exec_list_validate(list
);
349 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
350 switch (node
->type
) {
352 nir_emit_if(nir_cf_node_as_if(node
));
355 case nir_cf_node_loop
:
356 nir_emit_loop(nir_cf_node_as_loop(node
));
359 case nir_cf_node_block
:
360 nir_emit_block(nir_cf_node_as_block(node
));
364 unreachable("Invalid CFG node block");
370 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
372 /* first, put the condition into f0 */
373 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
374 retype(get_nir_src(if_stmt
->condition
),
375 BRW_REGISTER_TYPE_D
));
376 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
378 bld
.IF(BRW_PREDICATE_NORMAL
);
380 nir_emit_cf_list(&if_stmt
->then_list
);
382 /* note: if the else is empty, dead CF elimination will remove it */
383 bld
.emit(BRW_OPCODE_ELSE
);
385 nir_emit_cf_list(&if_stmt
->else_list
);
387 bld
.emit(BRW_OPCODE_ENDIF
);
389 if (devinfo
->gen
< 7)
390 limit_dispatch_width(16, "Non-uniform control flow unsupported "
395 fs_visitor::nir_emit_loop(nir_loop
*loop
)
397 bld
.emit(BRW_OPCODE_DO
);
399 nir_emit_cf_list(&loop
->body
);
401 bld
.emit(BRW_OPCODE_WHILE
);
403 if (devinfo
->gen
< 7)
404 limit_dispatch_width(16, "Non-uniform control flow unsupported "
409 fs_visitor::nir_emit_block(nir_block
*block
)
411 nir_foreach_instr(instr
, block
) {
412 nir_emit_instr(instr
);
417 fs_visitor::nir_emit_instr(nir_instr
*instr
)
419 const fs_builder abld
= bld
.annotate(NULL
, instr
);
421 switch (instr
->type
) {
422 case nir_instr_type_alu
:
423 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
426 case nir_instr_type_deref
:
427 /* Derefs can exist for images but they do nothing */
430 case nir_instr_type_intrinsic
:
432 case MESA_SHADER_VERTEX
:
433 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
435 case MESA_SHADER_TESS_CTRL
:
436 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
438 case MESA_SHADER_TESS_EVAL
:
439 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
441 case MESA_SHADER_GEOMETRY
:
442 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
444 case MESA_SHADER_FRAGMENT
:
445 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
447 case MESA_SHADER_COMPUTE
:
448 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
451 unreachable("unsupported shader stage");
455 case nir_instr_type_tex
:
456 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
459 case nir_instr_type_load_const
:
460 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
463 case nir_instr_type_ssa_undef
:
464 /* We create a new VGRF for undefs on every use (by handling
465 * them in get_nir_src()), rather than for each definition.
466 * This helps register coalescing eliminate MOVs from undef.
470 case nir_instr_type_jump
:
471 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
475 unreachable("unknown instruction type");
480 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
484 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
485 const fs_reg
&result
)
487 if (!instr
->src
[0].src
.is_ssa
||
488 !instr
->src
[0].src
.ssa
->parent_instr
)
491 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
494 nir_alu_instr
*src0
=
495 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
497 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
498 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
501 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
502 assert(element
!= NULL
);
504 /* Element type to extract.*/
505 const brw_reg_type type
= brw_int_type(
506 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
507 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
509 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
510 op0
.type
= brw_type_for_nir_type(devinfo
,
511 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
512 nir_src_bit_size(src0
->src
[0].src
)));
513 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
515 set_saturate(instr
->dest
.saturate
,
516 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
521 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
522 const fs_reg
&result
)
524 if (!instr
->src
[0].src
.is_ssa
||
525 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
528 nir_intrinsic_instr
*src0
=
529 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
531 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
534 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
535 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
538 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
539 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
542 fs_reg tmp
= vgrf(glsl_type::int_type
);
544 if (devinfo
->gen
>= 6) {
545 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
546 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
548 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
550 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
551 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
553 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
555 * This negation looks like it's safe in practice, because bits 0:4 will
556 * surely be TRIANGLES
559 if (value1
->f32
[0] == -1.0f
) {
563 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
564 g0
, brw_imm_uw(0x3f80));
566 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
567 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
569 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
571 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
572 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
574 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
576 * This negation looks like it's safe in practice, because bits 0:4 will
577 * surely be TRIANGLES
580 if (value1
->f32
[0] == -1.0f
) {
584 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
586 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
592 emit_find_msb_using_lzd(const fs_builder
&bld
,
593 const fs_reg
&result
,
601 /* LZD of an absolute value source almost always does the right
602 * thing. There are two problem values:
604 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
605 * 0. However, findMSB(int(0x80000000)) == 30.
607 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
608 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
610 * For a value of zero or negative one, -1 will be returned.
612 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
613 * findMSB(-(1<<x)) should return x-1.
615 * For all negative number cases, including 0x80000000 and
616 * 0xffffffff, the correct value is obtained from LZD if instead of
617 * negating the (already negative) value the logical-not is used. A
618 * conditonal logical-not can be achieved in two instructions.
620 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
622 bld
.ASR(temp
, src
, brw_imm_d(31));
623 bld
.XOR(temp
, temp
, src
);
626 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
627 retype(temp
, BRW_REGISTER_TYPE_UD
));
629 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
630 * from the LSB side. Subtract the result from 31 to convert the MSB
631 * count into an LSB count. If no bits are set, LZD will return 32.
632 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
634 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
635 inst
->src
[0].negate
= true;
639 brw_rnd_mode_from_nir_op (const nir_op op
) {
641 case nir_op_f2f16_rtz
:
642 return BRW_RND_MODE_RTZ
;
643 case nir_op_f2f16_rtne
:
644 return BRW_RND_MODE_RTNE
;
646 unreachable("Operation doesn't support rounding mode");
651 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
653 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
656 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
657 result
.type
= brw_type_for_nir_type(devinfo
,
658 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
659 nir_dest_bit_size(instr
->dest
.dest
)));
662 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
663 op
[i
] = get_nir_src(instr
->src
[i
].src
);
664 op
[i
].type
= brw_type_for_nir_type(devinfo
,
665 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
666 nir_src_bit_size(instr
->src
[i
].src
)));
667 op
[i
].abs
= instr
->src
[i
].abs
;
668 op
[i
].negate
= instr
->src
[i
].negate
;
671 /* We get a bunch of mov's out of the from_ssa pass and they may still
672 * be vectorized. We'll handle them as a special-case. We'll also
673 * handle vecN here because it's basically the same thing.
681 fs_reg temp
= result
;
682 bool need_extra_copy
= false;
683 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
684 if (!instr
->src
[i
].src
.is_ssa
&&
685 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
686 need_extra_copy
= true;
687 temp
= bld
.vgrf(result
.type
, 4);
692 for (unsigned i
= 0; i
< 4; i
++) {
693 if (!(instr
->dest
.write_mask
& (1 << i
)))
696 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
697 inst
= bld
.MOV(offset(temp
, bld
, i
),
698 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
700 inst
= bld
.MOV(offset(temp
, bld
, i
),
701 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
703 inst
->saturate
= instr
->dest
.saturate
;
706 /* In this case the source and destination registers were the same,
707 * so we need to insert an extra set of moves in order to deal with
710 if (need_extra_copy
) {
711 for (unsigned i
= 0; i
< 4; i
++) {
712 if (!(instr
->dest
.write_mask
& (1 << i
)))
715 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
724 /* At this point, we have dealt with any instruction that operates on
725 * more than a single channel. Therefore, we can just adjust the source
726 * and destination registers for that channel and emit the instruction.
728 unsigned channel
= 0;
729 if (nir_op_infos
[instr
->op
].output_size
== 0) {
730 /* Since NIR is doing the scalarizing for us, we should only ever see
731 * vectorized operations with a single channel.
733 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
734 channel
= ffs(instr
->dest
.write_mask
) - 1;
736 result
= offset(result
, bld
, channel
);
739 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
740 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
741 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
747 if (optimize_extract_to_float(instr
, result
))
749 inst
= bld
.MOV(result
, op
[0]);
750 inst
->saturate
= instr
->dest
.saturate
;
753 case nir_op_f2f16_rtne
:
754 case nir_op_f2f16_rtz
:
755 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
756 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
759 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
760 * on the HW gen, it is a special hw opcode or just a MOV, and
761 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
763 * But if we want to use that opcode, we need to provide support on
764 * different optimizations and lowerings. As right now HF support is
765 * only for gen8+, it will be better to use directly the MOV, and use
766 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
769 case nir_op_f2f16_undef
:
770 inst
= bld
.MOV(result
, op
[0]);
771 inst
->saturate
= instr
->dest
.saturate
;
781 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
783 * "When source or destination is 64b (...), regioning in Align1
784 * must follow these rules:
786 * 1. Source and destination horizontal stride must be aligned to
790 * This means that conversions from bit-sizes smaller than 64-bit to
791 * 64-bit need to have the source data elements aligned to 64-bit.
792 * This restriction does not apply to BDW and later.
794 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
795 nir_src_bit_size(instr
->src
[0].src
) < 64 &&
796 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
797 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
798 tmp
= subscript(tmp
, op
[0].type
, 0);
799 inst
= bld
.MOV(tmp
, op
[0]);
800 inst
= bld
.MOV(result
, tmp
);
801 inst
->saturate
= instr
->dest
.saturate
;
816 inst
= bld
.MOV(result
, op
[0]);
817 inst
->saturate
= instr
->dest
.saturate
;
822 /* Straightforward since the source can be assumed to be
825 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
826 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
828 } else if (type_sz(op
[0].type
) < 8) {
829 /* AND(val, 0x80000000) gives the sign bit.
831 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
834 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
836 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
837 op
[0].type
= BRW_REGISTER_TYPE_UD
;
838 result
.type
= BRW_REGISTER_TYPE_UD
;
839 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
841 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
842 inst
->predicate
= BRW_PREDICATE_NORMAL
;
843 if (instr
->dest
.saturate
) {
844 inst
= bld
.MOV(result
, result
);
845 inst
->saturate
= true;
848 /* For doubles we do the same but we need to consider:
850 * - 2-src instructions can't operate with 64-bit immediates
851 * - The sign is encoded in the high 32-bit of each DF
852 * - We need to produce a DF result.
855 fs_reg zero
= vgrf(glsl_type::double_type
);
856 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
857 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
859 bld
.MOV(result
, zero
);
861 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
862 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
863 brw_imm_ud(0x80000000u
));
865 set_predicate(BRW_PREDICATE_NORMAL
,
866 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
868 if (instr
->dest
.saturate
) {
869 inst
= bld
.MOV(result
, result
);
870 inst
->saturate
= true;
877 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
878 * -> non-negative val generates 0x00000000.
879 * Predicated OR sets 1 if val is positive.
881 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
882 assert(bit_size
== 32 || bit_size
== 16);
884 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
885 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
886 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
888 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
889 bld
.ASR(result
, op
[0], shift
);
890 inst
= bld
.OR(result
, result
, one
);
891 inst
->predicate
= BRW_PREDICATE_NORMAL
;
896 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
897 inst
->saturate
= instr
->dest
.saturate
;
901 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
902 inst
->saturate
= instr
->dest
.saturate
;
906 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
907 inst
->saturate
= instr
->dest
.saturate
;
911 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
912 inst
->saturate
= instr
->dest
.saturate
;
916 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
917 inst
->saturate
= instr
->dest
.saturate
;
921 if (fs_key
->high_quality_derivatives
) {
922 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
924 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
926 inst
->saturate
= instr
->dest
.saturate
;
928 case nir_op_fddx_fine
:
929 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
930 inst
->saturate
= instr
->dest
.saturate
;
932 case nir_op_fddx_coarse
:
933 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
934 inst
->saturate
= instr
->dest
.saturate
;
937 if (fs_key
->high_quality_derivatives
) {
938 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
940 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
942 inst
->saturate
= instr
->dest
.saturate
;
944 case nir_op_fddy_fine
:
945 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
946 inst
->saturate
= instr
->dest
.saturate
;
948 case nir_op_fddy_coarse
:
949 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
950 inst
->saturate
= instr
->dest
.saturate
;
955 inst
= bld
.ADD(result
, op
[0], op
[1]);
956 inst
->saturate
= instr
->dest
.saturate
;
960 inst
= bld
.MUL(result
, op
[0], op
[1]);
961 inst
->saturate
= instr
->dest
.saturate
;
965 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
966 bld
.MUL(result
, op
[0], op
[1]);
969 case nir_op_imul_high
:
970 case nir_op_umul_high
:
971 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
972 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
977 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
978 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
981 case nir_op_uadd_carry
:
982 unreachable("Should have been lowered by carry_to_arith().");
984 case nir_op_usub_borrow
:
985 unreachable("Should have been lowered by borrow_to_arith().");
989 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
990 * appears that our hardware just does the right thing for signed
993 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
994 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
998 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
999 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1001 /* Math instructions don't support conditional mod */
1002 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1003 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1005 /* Now, we need to determine if signs of the sources are different.
1006 * When we XOR the sources, the top bit is 0 if they are the same and 1
1007 * if they are different. We can then use a conditional modifier to
1008 * turn that into a predicate. This leads us to an XOR.l instruction.
1010 * Technically, according to the PRM, you're not allowed to use .l on a
1011 * XOR instruction. However, emperical experiments and Curro's reading
1012 * of the simulator source both indicate that it's safe.
1014 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1015 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1016 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1017 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1019 /* If the result of the initial remainder operation is non-zero and the
1020 * two sources have different signs, add in a copy of op[1] to get the
1021 * final integer modulus value.
1023 inst
= bld
.ADD(result
, result
, op
[1]);
1024 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1032 fs_reg dest
= result
;
1034 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1036 dest
= bld
.vgrf(op
[0].type
, 1);
1038 brw_conditional_mod cond
;
1039 switch (instr
->op
) {
1041 cond
= BRW_CONDITIONAL_L
;
1044 cond
= BRW_CONDITIONAL_GE
;
1047 cond
= BRW_CONDITIONAL_Z
;
1050 cond
= BRW_CONDITIONAL_NZ
;
1053 unreachable("bad opcode");
1056 bld
.CMP(dest
, op
[0], op
[1], cond
);
1058 if (bit_size
> 32) {
1059 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1060 } else if(bit_size
< 32) {
1061 /* When we convert the result to 32-bit we need to be careful and do
1062 * it as a signed conversion to get sign extension (for 32-bit true)
1064 const brw_reg_type src_type
=
1065 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1067 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1078 fs_reg dest
= result
;
1080 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1082 dest
= bld
.vgrf(op
[0].type
, 1);
1084 brw_conditional_mod cond
;
1085 switch (instr
->op
) {
1088 cond
= BRW_CONDITIONAL_L
;
1092 cond
= BRW_CONDITIONAL_GE
;
1095 cond
= BRW_CONDITIONAL_Z
;
1098 cond
= BRW_CONDITIONAL_NZ
;
1101 unreachable("bad opcode");
1103 bld
.CMP(dest
, op
[0], op
[1], cond
);
1105 if (bit_size
> 32) {
1106 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1107 } else if (bit_size
< 32) {
1108 /* When we convert the result to 32-bit we need to be careful and do
1109 * it as a signed conversion to get sign extension (for 32-bit true)
1111 const brw_reg_type src_type
=
1112 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1114 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1120 if (devinfo
->gen
>= 8) {
1121 op
[0] = resolve_source_modifiers(op
[0]);
1123 bld
.NOT(result
, op
[0]);
1126 if (devinfo
->gen
>= 8) {
1127 op
[0] = resolve_source_modifiers(op
[0]);
1128 op
[1] = resolve_source_modifiers(op
[1]);
1130 bld
.XOR(result
, op
[0], op
[1]);
1133 if (devinfo
->gen
>= 8) {
1134 op
[0] = resolve_source_modifiers(op
[0]);
1135 op
[1] = resolve_source_modifiers(op
[1]);
1137 bld
.OR(result
, op
[0], op
[1]);
1140 if (devinfo
->gen
>= 8) {
1141 op
[0] = resolve_source_modifiers(op
[0]);
1142 op
[1] = resolve_source_modifiers(op
[1]);
1144 bld
.AND(result
, op
[0], op
[1]);
1150 case nir_op_ball_fequal2
:
1151 case nir_op_ball_iequal2
:
1152 case nir_op_ball_fequal3
:
1153 case nir_op_ball_iequal3
:
1154 case nir_op_ball_fequal4
:
1155 case nir_op_ball_iequal4
:
1156 case nir_op_bany_fnequal2
:
1157 case nir_op_bany_inequal2
:
1158 case nir_op_bany_fnequal3
:
1159 case nir_op_bany_inequal3
:
1160 case nir_op_bany_fnequal4
:
1161 case nir_op_bany_inequal4
:
1162 unreachable("Lowered by nir_lower_alu_reductions");
1164 case nir_op_fnoise1_1
:
1165 case nir_op_fnoise1_2
:
1166 case nir_op_fnoise1_3
:
1167 case nir_op_fnoise1_4
:
1168 case nir_op_fnoise2_1
:
1169 case nir_op_fnoise2_2
:
1170 case nir_op_fnoise2_3
:
1171 case nir_op_fnoise2_4
:
1172 case nir_op_fnoise3_1
:
1173 case nir_op_fnoise3_2
:
1174 case nir_op_fnoise3_3
:
1175 case nir_op_fnoise3_4
:
1176 case nir_op_fnoise4_1
:
1177 case nir_op_fnoise4_2
:
1178 case nir_op_fnoise4_3
:
1179 case nir_op_fnoise4_4
:
1180 unreachable("not reached: should be handled by lower_noise");
1183 unreachable("not reached: should be handled by ldexp_to_arith()");
1186 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1187 inst
->saturate
= instr
->dest
.saturate
;
1191 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1192 inst
->saturate
= instr
->dest
.saturate
;
1197 bld
.MOV(result
, negate(op
[0]));
1202 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1203 if (bit_size
== 64) {
1204 /* two-argument instructions can't take 64-bit immediates */
1208 if (instr
->op
== nir_op_f2b
) {
1209 zero
= vgrf(glsl_type::double_type
);
1210 tmp
= vgrf(glsl_type::double_type
);
1211 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1213 zero
= vgrf(glsl_type::int64_t_type
);
1214 tmp
= vgrf(glsl_type::int64_t_type
);
1215 bld
.MOV(zero
, brw_imm_q(0));
1218 /* A SIMD16 execution needs to be split in two instructions, so use
1219 * a vgrf instead of the flag register as dst so instruction splitting
1222 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1223 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1226 if (bit_size
== 32) {
1227 zero
= instr
->op
== nir_op_f2b
? brw_imm_f(0.0f
) : brw_imm_d(0);
1229 assert(bit_size
== 16);
1230 zero
= instr
->op
== nir_op_f2b
?
1231 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1233 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1239 inst
= bld
.RNDZ(result
, op
[0]);
1240 inst
->saturate
= instr
->dest
.saturate
;
1243 case nir_op_fceil
: {
1244 op
[0].negate
= !op
[0].negate
;
1245 fs_reg temp
= vgrf(glsl_type::float_type
);
1246 bld
.RNDD(temp
, op
[0]);
1248 inst
= bld
.MOV(result
, temp
);
1249 inst
->saturate
= instr
->dest
.saturate
;
1253 inst
= bld
.RNDD(result
, op
[0]);
1254 inst
->saturate
= instr
->dest
.saturate
;
1257 inst
= bld
.FRC(result
, op
[0]);
1258 inst
->saturate
= instr
->dest
.saturate
;
1260 case nir_op_fround_even
:
1261 inst
= bld
.RNDE(result
, op
[0]);
1262 inst
->saturate
= instr
->dest
.saturate
;
1265 case nir_op_fquantize2f16
: {
1266 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1267 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1268 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1270 /* The destination stride must be at least as big as the source stride. */
1271 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1274 /* Check for denormal */
1275 fs_reg abs_src0
= op
[0];
1276 abs_src0
.abs
= true;
1277 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1279 /* Get the appropriately signed zero */
1280 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1281 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1282 brw_imm_ud(0x80000000));
1283 /* Do the actual F32 -> F16 -> F32 conversion */
1284 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1285 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1286 /* Select that or zero based on normal status */
1287 inst
= bld
.SEL(result
, zero
, tmp32
);
1288 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1289 inst
->saturate
= instr
->dest
.saturate
;
1296 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1297 inst
->saturate
= instr
->dest
.saturate
;
1303 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1304 inst
->saturate
= instr
->dest
.saturate
;
1307 case nir_op_pack_snorm_2x16
:
1308 case nir_op_pack_snorm_4x8
:
1309 case nir_op_pack_unorm_2x16
:
1310 case nir_op_pack_unorm_4x8
:
1311 case nir_op_unpack_snorm_2x16
:
1312 case nir_op_unpack_snorm_4x8
:
1313 case nir_op_unpack_unorm_2x16
:
1314 case nir_op_unpack_unorm_4x8
:
1315 case nir_op_unpack_half_2x16
:
1316 case nir_op_pack_half_2x16
:
1317 unreachable("not reached: should be handled by lower_packing_builtins");
1319 case nir_op_unpack_half_2x16_split_x
:
1320 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1321 inst
->saturate
= instr
->dest
.saturate
;
1323 case nir_op_unpack_half_2x16_split_y
:
1324 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1325 inst
->saturate
= instr
->dest
.saturate
;
1328 case nir_op_pack_64_2x32_split
:
1329 case nir_op_pack_32_2x16_split
:
1330 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1333 case nir_op_unpack_64_2x32_split_x
:
1334 case nir_op_unpack_64_2x32_split_y
: {
1335 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1336 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1338 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1342 case nir_op_unpack_32_2x16_split_x
:
1343 case nir_op_unpack_32_2x16_split_y
: {
1344 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1345 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1347 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1352 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1353 inst
->saturate
= instr
->dest
.saturate
;
1356 case nir_op_bitfield_reverse
:
1357 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1358 bld
.BFREV(result
, op
[0]);
1361 case nir_op_bit_count
:
1362 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1363 bld
.CBIT(result
, op
[0]);
1366 case nir_op_ufind_msb
: {
1367 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1368 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1372 case nir_op_ifind_msb
: {
1373 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1375 if (devinfo
->gen
< 7) {
1376 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1378 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1380 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1381 * count from the LSB side. If FBH didn't return an error
1382 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1383 * count into an LSB count.
1385 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1387 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1388 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1389 inst
->src
[0].negate
= true;
1394 case nir_op_find_lsb
:
1395 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1397 if (devinfo
->gen
< 7) {
1398 fs_reg temp
= vgrf(glsl_type::int_type
);
1400 /* (x & -x) generates a value that consists of only the LSB of x.
1401 * For all powers of 2, findMSB(y) == findLSB(y).
1403 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1404 fs_reg negated_src
= src
;
1406 /* One must be negated, and the other must be non-negated. It
1407 * doesn't matter which is which.
1409 negated_src
.negate
= true;
1412 bld
.AND(temp
, src
, negated_src
);
1413 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1415 bld
.FBL(result
, op
[0]);
1419 case nir_op_ubitfield_extract
:
1420 case nir_op_ibitfield_extract
:
1421 unreachable("should have been lowered");
1424 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1425 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1428 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1429 bld
.BFI1(result
, op
[0], op
[1]);
1432 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1433 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1436 case nir_op_bitfield_insert
:
1437 unreachable("not reached: should have been lowered");
1442 fs_reg shift_count
= op
[1];
1444 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1445 if (op
[1].file
== VGRF
&&
1446 (result
.type
== BRW_REGISTER_TYPE_Q
||
1447 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1448 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1449 BRW_REGISTER_TYPE_UD
);
1450 shift_count
.stride
= 2;
1451 bld
.MOV(shift_count
, op
[1]);
1455 switch (instr
->op
) {
1457 bld
.SHL(result
, op
[0], shift_count
);
1460 bld
.ASR(result
, op
[0], shift_count
);
1463 bld
.SHR(result
, op
[0], shift_count
);
1466 unreachable("not reached");
1471 case nir_op_pack_half_2x16_split
:
1472 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1476 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1477 inst
->saturate
= instr
->dest
.saturate
;
1481 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1482 inst
->saturate
= instr
->dest
.saturate
;
1486 if (optimize_frontfacing_ternary(instr
, result
))
1489 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1490 inst
= bld
.SEL(result
, op
[1], op
[2]);
1491 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1494 case nir_op_extract_u8
:
1495 case nir_op_extract_i8
: {
1496 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1497 assert(byte
!= NULL
);
1502 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1503 * Use two instructions and a word or DWord intermediate integer type.
1505 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1506 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1508 if (instr
->op
== nir_op_extract_i8
) {
1509 /* If we need to sign extend, extract to a word first */
1510 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1511 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
->u32
[0]));
1512 bld
.MOV(result
, w_temp
);
1514 /* Otherwise use an AND with 0xff and a word type */
1515 bld
.AND(result
, subscript(op
[0], type
, byte
->u32
[0] / 2), brw_imm_uw(0xff));
1518 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1519 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1524 case nir_op_extract_u16
:
1525 case nir_op_extract_i16
: {
1526 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1527 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1528 assert(word
!= NULL
);
1529 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1534 unreachable("unhandled instruction");
1537 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1538 * to sign extend the low bit to 0/~0
1540 if (devinfo
->gen
<= 5 &&
1541 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1542 fs_reg masked
= vgrf(glsl_type::int_type
);
1543 bld
.AND(masked
, result
, brw_imm_d(1));
1544 masked
.negate
= true;
1545 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1550 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1551 nir_load_const_instr
*instr
)
1553 const brw_reg_type reg_type
=
1554 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1555 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1557 switch (instr
->def
.bit_size
) {
1559 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1560 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1564 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1565 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1569 assert(devinfo
->gen
>= 7);
1570 if (devinfo
->gen
== 7) {
1571 /* We don't get 64-bit integer types until gen8 */
1572 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1573 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1574 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1577 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1578 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1583 unreachable("Invalid bit size");
1586 nir_ssa_values
[instr
->def
.index
] = reg
;
1590 fs_visitor::get_nir_src(const nir_src
&src
)
1594 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1595 const brw_reg_type reg_type
=
1596 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1597 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1599 reg
= nir_ssa_values
[src
.ssa
->index
];
1602 /* We don't handle indirects on locals */
1603 assert(src
.reg
.indirect
== NULL
);
1604 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1605 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1608 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1609 /* The only 64-bit type available on gen7 is DF, so use that. */
1610 reg
.type
= BRW_REGISTER_TYPE_DF
;
1612 /* To avoid floating-point denorm flushing problems, set the type by
1613 * default to an integer type - instructions that need floating point
1614 * semantics will set this to F if they need to
1616 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1617 BRW_REGISTER_TYPE_D
);
1624 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1626 * This function should not be called on any value which may be 64 bits.
1627 * We could theoretically support 64-bit on gen8+ but we choose not to
1628 * because it wouldn't work in general (no gen7 support) and there are
1629 * enough restrictions in 64-bit immediates that you can't take the return
1630 * value and treat it the same as the result of get_nir_src().
1633 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1635 nir_const_value
*val
= nir_src_as_const_value(src
);
1636 assert(nir_src_bit_size(src
) == 32);
1637 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1641 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1644 const brw_reg_type reg_type
=
1645 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1646 nir_ssa_values
[dest
.ssa
.index
] =
1647 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1648 return nir_ssa_values
[dest
.ssa
.index
];
1650 /* We don't handle indirects on locals */
1651 assert(dest
.reg
.indirect
== NULL
);
1652 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1653 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1658 fs_visitor::get_nir_image_deref(nir_deref_instr
*deref
)
1660 fs_reg arr_offset
= brw_imm_ud(0);
1661 unsigned array_size
= BRW_IMAGE_PARAM_SIZE
* 4;
1662 nir_deref_instr
*head
= deref
;
1663 while (head
->deref_type
!= nir_deref_type_var
) {
1664 assert(head
->deref_type
== nir_deref_type_array
);
1666 /* This level's element size is the previous level's array size */
1667 const unsigned elem_size
= array_size
;
1669 fs_reg index
= retype(get_nir_src_imm(head
->arr
.index
),
1670 BRW_REGISTER_TYPE_UD
);
1671 if (arr_offset
.file
== BRW_IMMEDIATE_VALUE
&&
1672 index
.file
== BRW_IMMEDIATE_VALUE
) {
1673 arr_offset
.ud
+= index
.ud
* elem_size
;
1674 } else if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1675 bld
.ADD(arr_offset
, arr_offset
, brw_imm_ud(index
.ud
* elem_size
));
1677 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
1678 bld
.MUL(tmp
, index
, brw_imm_ud(elem_size
));
1679 bld
.ADD(tmp
, tmp
, arr_offset
);
1683 head
= nir_deref_instr_parent(head
);
1684 assert(glsl_type_is_array(head
->type
));
1685 array_size
= elem_size
* glsl_get_length(head
->type
);
1688 assert(head
->deref_type
== nir_deref_type_var
);
1689 const unsigned max_arr_offset
= array_size
- (BRW_IMAGE_PARAM_SIZE
* 4);
1690 fs_reg
image(UNIFORM
, head
->var
->data
.driver_location
/ 4,
1691 BRW_REGISTER_TYPE_UD
);
1693 if (arr_offset
.file
== BRW_IMMEDIATE_VALUE
) {
1694 /* The offset is in bytes but we want it in dwords */
1695 return offset(image
, bld
, MIN2(arr_offset
.ud
, max_arr_offset
) / 4);
1697 /* Accessing an invalid surface index with the dataport can result
1698 * in a hang. According to the spec "if the index used to
1699 * select an individual element is negative or greater than or
1700 * equal to the size of the array, the results of the operation
1701 * are undefined but may not lead to termination" -- which is one
1702 * of the possible outcomes of the hang. Clamp the index to
1703 * prevent access outside of the array bounds.
1705 bld
.emit_minmax(arr_offset
, arr_offset
, brw_imm_ud(max_arr_offset
),
1708 /* Emit a pile of MOVs to load the uniform into a temporary. The
1709 * dead-code elimination pass will get rid of what we don't use.
1711 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1712 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1713 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1714 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1715 arr_offset
, brw_imm_ud(max_arr_offset
+ 4));
1722 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1725 for (unsigned i
= 0; i
< 4; i
++) {
1726 if (!((wr_mask
>> i
) & 1))
1729 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1730 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1731 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1732 if (new_inst
->src
[j
].file
== VGRF
)
1733 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1740 * Get the matching channel register datatype for an image intrinsic of the
1741 * specified GLSL image type.
1744 get_image_base_type(const glsl_type
*type
)
1746 switch ((glsl_base_type
)type
->sampled_type
) {
1747 case GLSL_TYPE_UINT
:
1748 return BRW_REGISTER_TYPE_UD
;
1750 return BRW_REGISTER_TYPE_D
;
1751 case GLSL_TYPE_FLOAT
:
1752 return BRW_REGISTER_TYPE_F
;
1754 unreachable("Not reached.");
1759 * Get the appropriate atomic op for an image atomic intrinsic.
1762 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1765 case nir_intrinsic_image_deref_atomic_add
:
1767 case nir_intrinsic_image_deref_atomic_min
:
1768 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1769 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1770 case nir_intrinsic_image_deref_atomic_max
:
1771 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1772 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1773 case nir_intrinsic_image_deref_atomic_and
:
1775 case nir_intrinsic_image_deref_atomic_or
:
1777 case nir_intrinsic_image_deref_atomic_xor
:
1779 case nir_intrinsic_image_deref_atomic_exchange
:
1781 case nir_intrinsic_image_deref_atomic_comp_swap
:
1782 return BRW_AOP_CMPWR
;
1784 unreachable("Not reachable.");
1789 emit_pixel_interpolater_send(const fs_builder
&bld
,
1794 glsl_interp_mode interpolation
)
1796 struct brw_wm_prog_data
*wm_prog_data
=
1797 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1802 if (src
.file
== BAD_FILE
) {
1804 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1808 mlen
= 2 * bld
.dispatch_width() / 8;
1811 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1813 /* 2 floats per slot returned */
1814 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1815 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1817 wm_prog_data
->pulls_bary
= true;
1823 * Computes 1 << x, given a D/UD register containing some value x.
1826 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1828 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1830 fs_reg result
= bld
.vgrf(x
.type
, 1);
1831 fs_reg one
= bld
.vgrf(x
.type
, 1);
1833 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1834 bld
.SHL(result
, one
, x
);
1839 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1841 assert(stage
== MESA_SHADER_GEOMETRY
);
1843 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1845 if (gs_compile
->control_data_header_size_bits
== 0)
1848 /* We can only do EndPrimitive() functionality when the control data
1849 * consists of cut bits. Fortunately, the only time it isn't is when the
1850 * output type is points, in which case EndPrimitive() is a no-op.
1852 if (gs_prog_data
->control_data_format
!=
1853 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1857 /* Cut bits use one bit per vertex. */
1858 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1860 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1861 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1863 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1864 * vertex n, 0 otherwise. So all we need to do here is mark bit
1865 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1866 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1867 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1869 * Note that if EndPrimitive() is called before emitting any vertices, this
1870 * will cause us to set bit 31 of the control_data_bits register to 1.
1871 * That's fine because:
1873 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1874 * output, so the hardware will ignore cut bit 31.
1876 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1877 * last vertex, so setting cut bit 31 has no effect (since the primitive
1878 * is automatically ended when the GS terminates).
1880 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1881 * control_data_bits register to 0 when the first vertex is emitted.
1884 const fs_builder abld
= bld
.annotate("end primitive");
1886 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1887 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1888 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1889 fs_reg mask
= intexp2(abld
, prev_count
);
1890 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1891 * attention to the lower 5 bits of its second source argument, so on this
1892 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1893 * ((vertex_count - 1) % 32).
1895 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1899 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1901 assert(stage
== MESA_SHADER_GEOMETRY
);
1902 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1904 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1906 const fs_builder abld
= bld
.annotate("emit control data bits");
1907 const fs_builder fwa_bld
= bld
.exec_all();
1909 /* We use a single UD register to accumulate control data bits (32 bits
1910 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1913 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1914 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1915 * use the Channel Mask phase to enable/disable which DWord within that
1916 * group to write. (Remember, different SIMD8 channels may have emitted
1917 * different numbers of vertices, so we may need per-slot offsets.)
1919 * Channel masking presents an annoying problem: we may have to replicate
1920 * the data up to 4 times:
1922 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1924 * To avoid penalizing shaders that emit a small number of vertices, we
1925 * can avoid these sometimes: if the size of the control data header is
1926 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1927 * land in the same 128-bit group, so we can skip per-slot offsets.
1929 * Similarly, if the control data header is <= 32 bits, there is only one
1930 * DWord, so we can skip channel masks.
1932 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1934 fs_reg channel_mask
, per_slot_offset
;
1936 if (gs_compile
->control_data_header_size_bits
> 32) {
1937 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1938 channel_mask
= vgrf(glsl_type::uint_type
);
1941 if (gs_compile
->control_data_header_size_bits
> 128) {
1942 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1943 per_slot_offset
= vgrf(glsl_type::uint_type
);
1946 /* Figure out which DWord we're trying to write to using the formula:
1948 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1950 * Since bits_per_vertex is a power of two, and is known at compile
1951 * time, this can be optimized to:
1953 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1955 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1956 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1957 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1958 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1959 unsigned log2_bits_per_vertex
=
1960 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1961 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1963 if (per_slot_offset
.file
!= BAD_FILE
) {
1964 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1965 * the appropriate OWord within the control data header.
1967 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1970 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1971 * write to the appropriate DWORD within the OWORD.
1973 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1974 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1975 channel_mask
= intexp2(fwa_bld
, channel
);
1976 /* Then the channel masks need to be in bits 23:16. */
1977 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1980 /* Store the control data bits in the message payload and send it. */
1982 if (channel_mask
.file
!= BAD_FILE
)
1983 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1984 if (per_slot_offset
.file
!= BAD_FILE
)
1987 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1988 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1990 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1991 if (per_slot_offset
.file
!= BAD_FILE
)
1992 sources
[i
++] = per_slot_offset
;
1993 if (channel_mask
.file
!= BAD_FILE
)
1994 sources
[i
++] = channel_mask
;
1996 sources
[i
++] = this->control_data_bits
;
1999 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2000 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2002 /* We need to increment Global Offset by 256-bits to make room for
2003 * Broadwell's extra "Vertex Count" payload at the beginning of the
2004 * URB entry. Since this is an OWord message, Global Offset is counted
2005 * in 128-bit units, so we must set it to 2.
2007 if (gs_prog_data
->static_vertex_count
== -1)
2012 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2015 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2017 /* Note: we are calling this *before* increasing vertex_count, so
2018 * this->vertex_count == vertex_count - 1 in the formula above.
2021 /* Stream mode uses 2 bits per vertex */
2022 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2024 /* Must be a valid stream */
2025 assert(stream_id
< MAX_VERTEX_STREAMS
);
2027 /* Control data bits are initialized to 0 so we don't have to set any
2028 * bits when sending vertices to stream 0.
2033 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2035 /* reg::sid = stream_id */
2036 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2037 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2039 /* reg:shift_count = 2 * (vertex_count - 1) */
2040 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2041 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2043 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2044 * attention to the lower 5 bits of its second source argument, so on this
2045 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2046 * stream_id << ((2 * (vertex_count - 1)) % 32).
2048 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2049 abld
.SHL(mask
, sid
, shift_count
);
2050 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2054 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2057 assert(stage
== MESA_SHADER_GEOMETRY
);
2059 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2061 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2062 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2064 /* Haswell and later hardware ignores the "Render Stream Select" bits
2065 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2066 * and instead sends all primitives down the pipeline for rasterization.
2067 * If the SOL stage is enabled, "Render Stream Select" is honored and
2068 * primitives bound to non-zero streams are discarded after stream output.
2070 * Since the only purpose of primives sent to non-zero streams is to
2071 * be recorded by transform feedback, we can simply discard all geometry
2072 * bound to these streams when transform feedback is disabled.
2074 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2077 /* If we're outputting 32 control data bits or less, then we can wait
2078 * until the shader is over to output them all. Otherwise we need to
2079 * output them as we go. Now is the time to do it, since we're about to
2080 * output the vertex_count'th vertex, so it's guaranteed that the
2081 * control data bits associated with the (vertex_count - 1)th vertex are
2084 if (gs_compile
->control_data_header_size_bits
> 32) {
2085 const fs_builder abld
=
2086 bld
.annotate("emit vertex: emit control data bits");
2088 /* Only emit control data bits if we've finished accumulating a batch
2089 * of 32 bits. This is the case when:
2091 * (vertex_count * bits_per_vertex) % 32 == 0
2093 * (in other words, when the last 5 bits of vertex_count *
2094 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2095 * integer n (which is always the case, since bits_per_vertex is
2096 * always 1 or 2), this is equivalent to requiring that the last 5-n
2097 * bits of vertex_count are 0:
2099 * vertex_count & (2^(5-n) - 1) == 0
2101 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2104 * vertex_count & (32 / bits_per_vertex - 1) == 0
2106 * TODO: If vertex_count is an immediate, we could do some of this math
2107 * at compile time...
2110 abld
.AND(bld
.null_reg_d(), vertex_count
,
2111 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2112 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2114 abld
.IF(BRW_PREDICATE_NORMAL
);
2115 /* If vertex_count is 0, then no control data bits have been
2116 * accumulated yet, so we can skip emitting them.
2118 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2119 BRW_CONDITIONAL_NEQ
);
2120 abld
.IF(BRW_PREDICATE_NORMAL
);
2121 emit_gs_control_data_bits(vertex_count
);
2122 abld
.emit(BRW_OPCODE_ENDIF
);
2124 /* Reset control_data_bits to 0 so we can start accumulating a new
2127 * Note: in the case where vertex_count == 0, this neutralizes the
2128 * effect of any call to EndPrimitive() that the shader may have
2129 * made before outputting its first vertex.
2131 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2132 inst
->force_writemask_all
= true;
2133 abld
.emit(BRW_OPCODE_ENDIF
);
2136 emit_urb_writes(vertex_count
);
2138 /* In stream mode we have to set control data bits for all vertices
2139 * unless we have disabled control data bits completely (which we do
2140 * do for GL_POINTS outputs that don't use streams).
2142 if (gs_compile
->control_data_header_size_bits
> 0 &&
2143 gs_prog_data
->control_data_format
==
2144 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2145 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2150 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2151 const nir_src
&vertex_src
,
2152 unsigned base_offset
,
2153 const nir_src
&offset_src
,
2154 unsigned num_components
,
2155 unsigned first_component
)
2157 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2159 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2160 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2161 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2163 /* TODO: figure out push input layout for invocations == 1 */
2164 /* TODO: make this work with 64-bit inputs */
2165 if (gs_prog_data
->invocations
== 1 &&
2166 type_sz(dst
.type
) <= 4 &&
2167 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2168 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2169 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2170 vertex_const
->u32
[0] * push_reg_count
;
2171 for (unsigned i
= 0; i
< num_components
; i
++) {
2172 bld
.MOV(offset(dst
, bld
, i
),
2173 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2178 /* Resort to the pull model. Ensure the VUE handles are provided. */
2179 assert(gs_prog_data
->base
.include_vue_handles
);
2181 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2182 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2184 if (gs_prog_data
->invocations
== 1) {
2186 /* The vertex index is constant; just select the proper URB handle. */
2188 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2189 BRW_REGISTER_TYPE_UD
);
2191 /* The vertex index is non-constant. We need to use indirect
2192 * addressing to fetch the proper URB handle.
2194 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2195 * indicating that channel <n> should read the handle from
2196 * DWord <n>. We convert that to bytes by multiplying by 4.
2198 * Next, we convert the vertex index to bytes by multiplying
2199 * by 32 (shifting by 5), and add the two together. This is
2200 * the final indirect byte offset.
2202 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2203 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2204 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2205 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2207 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2208 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2209 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2210 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2211 /* Convert vertex_index to bytes (multiply by 32) */
2212 bld
.SHL(vertex_offset_bytes
,
2213 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2215 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2217 /* Use first_icp_handle as the base offset. There is one register
2218 * of URB handles per vertex, so inform the register allocator that
2219 * we might read up to nir->info.gs.vertices_in registers.
2221 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2222 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2223 fs_reg(icp_offset_bytes
),
2224 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2227 assert(gs_prog_data
->invocations
> 1);
2230 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2232 retype(brw_vec1_grf(first_icp_handle
+
2233 vertex_const
->i32
[0] / 8,
2234 vertex_const
->i32
[0] % 8),
2235 BRW_REGISTER_TYPE_UD
));
2237 /* The vertex index is non-constant. We need to use indirect
2238 * addressing to fetch the proper URB handle.
2241 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2243 /* Convert vertex_index to bytes (multiply by 4) */
2244 bld
.SHL(icp_offset_bytes
,
2245 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2248 /* Use first_icp_handle as the base offset. There is one DWord
2249 * of URB handles per vertex, so inform the register allocator that
2250 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2252 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2253 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2254 fs_reg(icp_offset_bytes
),
2255 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2262 fs_reg tmp_dst
= dst
;
2263 fs_reg indirect_offset
= get_nir_src(offset_src
);
2264 unsigned num_iterations
= 1;
2265 unsigned orig_num_components
= num_components
;
2267 if (type_sz(dst
.type
) == 8) {
2268 if (num_components
> 2) {
2272 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2274 first_component
= first_component
/ 2;
2277 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2279 /* Constant indexing - use global offset. */
2280 if (first_component
!= 0) {
2281 unsigned read_components
= num_components
+ first_component
;
2282 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2283 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2284 inst
->size_written
= read_components
*
2285 tmp
.component_size(inst
->exec_size
);
2286 for (unsigned i
= 0; i
< num_components
; i
++) {
2287 bld
.MOV(offset(tmp_dst
, bld
, i
),
2288 offset(tmp
, bld
, i
+ first_component
));
2291 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2293 inst
->size_written
= num_components
*
2294 tmp_dst
.component_size(inst
->exec_size
);
2296 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2299 /* Indirect indexing - use per-slot offsets as well. */
2300 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2301 unsigned read_components
= num_components
+ first_component
;
2302 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2303 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2304 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2305 if (first_component
!= 0) {
2306 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2308 inst
->size_written
= read_components
*
2309 tmp
.component_size(inst
->exec_size
);
2310 for (unsigned i
= 0; i
< num_components
; i
++) {
2311 bld
.MOV(offset(tmp_dst
, bld
, i
),
2312 offset(tmp
, bld
, i
+ first_component
));
2315 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2317 inst
->size_written
= num_components
*
2318 tmp_dst
.component_size(inst
->exec_size
);
2320 inst
->offset
= base_offset
;
2324 if (type_sz(dst
.type
) == 8) {
2325 shuffle_from_32bit_read(bld
,
2326 offset(dst
, bld
, iter
* 2),
2327 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2332 if (num_iterations
> 1) {
2333 num_components
= orig_num_components
- 2;
2337 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2338 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2339 indirect_offset
= new_indirect
;
2346 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2348 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2349 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2352 /* The only constant offset we should find is 0. brw_nir.c's
2353 * add_const_offset_to_base() will fold other constant offsets
2354 * into instr->const_index[0].
2356 assert(const_value
->u32
[0] == 0);
2360 return get_nir_src(*offset_src
);
2364 do_untyped_vector_read(const fs_builder
&bld
,
2366 const fs_reg surf_index
,
2367 const fs_reg offset_reg
,
2368 unsigned num_components
)
2370 if (type_sz(dest
.type
) <= 2) {
2371 assert(dest
.stride
== 1);
2372 boolean is_const_offset
= offset_reg
.file
== BRW_IMMEDIATE_VALUE
;
2374 if (is_const_offset
) {
2375 uint32_t start
= offset_reg
.ud
& ~3;
2376 uint32_t end
= offset_reg
.ud
+ num_components
* type_sz(dest
.type
);
2377 end
= ALIGN(end
, 4);
2378 assert (end
- start
<= 16);
2380 /* At this point we have 16-bit component/s that have constant
2381 * offset aligned to 4-bytes that can be read with untyped_reads.
2382 * untyped_read message requires 32-bit aligned offsets.
2384 unsigned first_component
= (offset_reg
.ud
& 3) / type_sz(dest
.type
);
2385 unsigned num_components_32bit
= (end
- start
) / 4;
2387 fs_reg read_result
=
2388 emit_untyped_read(bld
, surf_index
, brw_imm_ud(start
),
2390 num_components_32bit
,
2391 BRW_PREDICATE_NONE
);
2392 shuffle_from_32bit_read(bld
, dest
, read_result
, first_component
,
2395 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2396 for (unsigned i
= 0; i
< num_components
; i
++) {
2398 bld
.MOV(read_offset
, offset_reg
);
2400 bld
.ADD(read_offset
, offset_reg
,
2401 brw_imm_ud(i
* type_sz(dest
.type
)));
2403 /* Non constant offsets are not guaranteed to be aligned 32-bits
2404 * so they are read using one byte_scattered_read message
2405 * for each component.
2407 fs_reg read_result
=
2408 emit_byte_scattered_read(bld
, surf_index
, read_offset
,
2410 type_sz(dest
.type
) * 8 /* bit_size */,
2411 BRW_PREDICATE_NONE
);
2412 bld
.MOV(offset(dest
, bld
, i
),
2413 subscript (read_result
, dest
.type
, 0));
2416 } else if (type_sz(dest
.type
) == 4) {
2417 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2420 BRW_PREDICATE_NONE
);
2421 read_result
.type
= dest
.type
;
2422 for (unsigned i
= 0; i
< num_components
; i
++)
2423 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2424 } else if (type_sz(dest
.type
) == 8) {
2425 /* Reading a dvec, so we need to:
2427 * 1. Multiply num_components by 2, to account for the fact that we
2428 * need to read 64-bit components.
2429 * 2. Shuffle the result of the load to form valid 64-bit elements
2430 * 3. Emit a second load (for components z/w) if needed.
2432 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2433 bld
.MOV(read_offset
, offset_reg
);
2435 int iters
= num_components
<= 2 ? 1 : 2;
2437 /* Load the dvec, the first iteration loads components x/y, the second
2438 * iteration, if needed, loads components z/w
2440 for (int it
= 0; it
< iters
; it
++) {
2441 /* Compute number of components to read in this iteration */
2442 int iter_components
= MIN2(2, num_components
);
2443 num_components
-= iter_components
;
2445 /* Read. Since this message reads 32-bit components, we need to
2446 * read twice as many components.
2448 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2450 iter_components
* 2,
2451 BRW_PREDICATE_NONE
);
2453 /* Shuffle the 32-bit load result into valid 64-bit data */
2454 shuffle_from_32bit_read(bld
, offset(dest
, bld
, it
* 2),
2455 read_result
, 0, iter_components
);
2457 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2460 unreachable("Unsupported type");
2465 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2466 nir_intrinsic_instr
*instr
)
2468 assert(stage
== MESA_SHADER_VERTEX
);
2471 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2472 dest
= get_nir_dest(instr
->dest
);
2474 switch (instr
->intrinsic
) {
2475 case nir_intrinsic_load_vertex_id
:
2476 case nir_intrinsic_load_base_vertex
:
2477 unreachable("should be lowered by nir_lower_system_values()");
2479 case nir_intrinsic_load_vertex_id_zero_base
:
2480 case nir_intrinsic_load_instance_id
:
2481 case nir_intrinsic_load_base_instance
:
2482 case nir_intrinsic_load_draw_id
: {
2483 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2484 fs_reg val
= nir_system_values
[sv
];
2485 assert(val
.file
!= BAD_FILE
);
2486 dest
.type
= val
.type
;
2491 case nir_intrinsic_load_input
: {
2492 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2493 unsigned first_component
= nir_intrinsic_component(instr
);
2494 unsigned num_components
= instr
->num_components
;
2496 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2497 assert(const_offset
&& "Indirect input loads not allowed");
2498 src
= offset(src
, bld
, const_offset
->u32
[0]);
2500 if (type_sz(dest
.type
) == 8)
2501 first_component
/= 2;
2503 /* For 16-bit support maybe a temporary will be needed to copy from
2506 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2507 first_component
, num_components
);
2511 case nir_intrinsic_load_first_vertex
:
2512 case nir_intrinsic_load_is_indexed_draw
:
2513 unreachable("lowered by brw_nir_lower_vs_inputs");
2516 nir_emit_intrinsic(bld
, instr
);
2522 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2523 nir_intrinsic_instr
*instr
)
2525 assert(stage
== MESA_SHADER_TESS_CTRL
);
2526 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2527 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2530 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2531 dst
= get_nir_dest(instr
->dest
);
2533 switch (instr
->intrinsic
) {
2534 case nir_intrinsic_load_primitive_id
:
2535 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2537 case nir_intrinsic_load_invocation_id
:
2538 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2540 case nir_intrinsic_load_patch_vertices_in
:
2541 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2542 brw_imm_d(tcs_key
->input_vertices
));
2545 case nir_intrinsic_barrier
: {
2546 if (tcs_prog_data
->instances
== 1)
2549 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2550 fs_reg m0_2
= component(m0
, 2);
2552 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2554 /* Zero the message header */
2555 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2557 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2558 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2559 brw_imm_ud(INTEL_MASK(16, 13)));
2561 /* Shift it up to bits 27:24. */
2562 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2564 /* Set the Barrier Count and the enable bit */
2565 chanbld
.OR(m0_2
, m0_2
,
2566 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2568 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2572 case nir_intrinsic_load_input
:
2573 unreachable("nir_lower_io should never give us these.");
2576 case nir_intrinsic_load_per_vertex_input
: {
2577 fs_reg indirect_offset
= get_indirect_offset(instr
);
2578 unsigned imm_offset
= instr
->const_index
[0];
2580 const nir_src
&vertex_src
= instr
->src
[0];
2581 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2588 /* Emit a MOV to resolve <0,1,0> regioning. */
2589 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2591 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2592 vertex_const
->i32
[0] & 7),
2593 BRW_REGISTER_TYPE_UD
));
2594 } else if (tcs_prog_data
->instances
== 1 &&
2595 vertex_src
.is_ssa
&&
2596 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2597 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2598 /* For the common case of only 1 instance, an array index of
2599 * gl_InvocationID means reading g1. Skip all the indirect work.
2601 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2603 /* The vertex index is non-constant. We need to use indirect
2604 * addressing to fetch the proper URB handle.
2606 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2608 /* Each ICP handle is a single DWord (4 bytes) */
2609 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2610 bld
.SHL(vertex_offset_bytes
,
2611 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2614 /* Start at g1. We might read up to 4 registers. */
2615 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2616 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2617 brw_imm_ud(4 * REG_SIZE
));
2620 /* We can only read two double components with each URB read, so
2621 * we send two read messages in that case, each one loading up to
2622 * two double components.
2624 unsigned num_iterations
= 1;
2625 unsigned num_components
= instr
->num_components
;
2626 unsigned first_component
= nir_intrinsic_component(instr
);
2627 fs_reg orig_dst
= dst
;
2628 if (type_sz(dst
.type
) == 8) {
2629 first_component
= first_component
/ 2;
2630 if (instr
->num_components
> 2) {
2635 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2639 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2640 if (indirect_offset
.file
== BAD_FILE
) {
2641 /* Constant indexing - use global offset. */
2642 if (first_component
!= 0) {
2643 unsigned read_components
= num_components
+ first_component
;
2644 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2645 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2646 for (unsigned i
= 0; i
< num_components
; i
++) {
2647 bld
.MOV(offset(dst
, bld
, i
),
2648 offset(tmp
, bld
, i
+ first_component
));
2651 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2653 inst
->offset
= imm_offset
;
2656 /* Indirect indexing - use per-slot offsets as well. */
2657 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2658 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2659 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2660 if (first_component
!= 0) {
2661 unsigned read_components
= num_components
+ first_component
;
2662 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2663 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2665 for (unsigned i
= 0; i
< num_components
; i
++) {
2666 bld
.MOV(offset(dst
, bld
, i
),
2667 offset(tmp
, bld
, i
+ first_component
));
2670 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2673 inst
->offset
= imm_offset
;
2676 inst
->size_written
= (num_components
+ first_component
) *
2677 inst
->dst
.component_size(inst
->exec_size
);
2679 /* If we are reading 64-bit data using 32-bit read messages we need
2680 * build proper 64-bit data elements by shuffling the low and high
2681 * 32-bit components around like we do for other things like UBOs
2684 if (type_sz(dst
.type
) == 8) {
2685 shuffle_from_32bit_read(bld
,
2686 offset(orig_dst
, bld
, iter
* 2),
2687 retype(dst
, BRW_REGISTER_TYPE_D
),
2691 /* Copy the temporary to the destination to deal with writemasking.
2693 * Also attempt to deal with gl_PointSize being in the .w component.
2695 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2696 assert(type_sz(dst
.type
) < 8);
2697 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2698 inst
->size_written
= 4 * REG_SIZE
;
2699 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2702 /* If we are loading double data and we need a second read message
2703 * adjust the write offset
2705 if (num_iterations
> 1) {
2706 num_components
= instr
->num_components
- 2;
2713 case nir_intrinsic_load_output
:
2714 case nir_intrinsic_load_per_vertex_output
: {
2715 fs_reg indirect_offset
= get_indirect_offset(instr
);
2716 unsigned imm_offset
= instr
->const_index
[0];
2717 unsigned first_component
= nir_intrinsic_component(instr
);
2720 if (indirect_offset
.file
== BAD_FILE
) {
2721 /* Replicate the patch handle to all enabled channels */
2722 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2723 bld
.MOV(patch_handle
,
2724 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2727 if (first_component
!= 0) {
2728 unsigned read_components
=
2729 instr
->num_components
+ first_component
;
2730 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2731 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2733 inst
->size_written
= read_components
* REG_SIZE
;
2734 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2735 bld
.MOV(offset(dst
, bld
, i
),
2736 offset(tmp
, bld
, i
+ first_component
));
2739 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2741 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2743 inst
->offset
= imm_offset
;
2747 /* Indirect indexing - use per-slot offsets as well. */
2748 const fs_reg srcs
[] = {
2749 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2752 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2753 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2754 if (first_component
!= 0) {
2755 unsigned read_components
=
2756 instr
->num_components
+ first_component
;
2757 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2758 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2760 inst
->size_written
= read_components
* REG_SIZE
;
2761 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2762 bld
.MOV(offset(dst
, bld
, i
),
2763 offset(tmp
, bld
, i
+ first_component
));
2766 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2768 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2770 inst
->offset
= imm_offset
;
2776 case nir_intrinsic_store_output
:
2777 case nir_intrinsic_store_per_vertex_output
: {
2778 fs_reg value
= get_nir_src(instr
->src
[0]);
2779 bool is_64bit
= (instr
->src
[0].is_ssa
?
2780 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2781 fs_reg indirect_offset
= get_indirect_offset(instr
);
2782 unsigned imm_offset
= instr
->const_index
[0];
2783 unsigned mask
= instr
->const_index
[1];
2784 unsigned header_regs
= 0;
2786 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2788 if (indirect_offset
.file
!= BAD_FILE
) {
2789 srcs
[header_regs
++] = indirect_offset
;
2795 unsigned num_components
= util_last_bit(mask
);
2798 /* We can only pack two 64-bit components in a single message, so send
2799 * 2 messages if we have more components
2801 unsigned num_iterations
= 1;
2802 unsigned iter_components
= num_components
;
2803 unsigned first_component
= nir_intrinsic_component(instr
);
2805 first_component
= first_component
/ 2;
2806 if (instr
->num_components
> 2) {
2808 iter_components
= 2;
2812 mask
= mask
<< first_component
;
2814 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2815 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2816 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2817 opcode
= indirect_offset
.file
!= BAD_FILE
?
2818 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2819 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2820 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2821 /* Expand the 64-bit mask to 32-bit channels. We only handle
2822 * two channels in each iteration, so we only care about X/Y.
2824 unsigned mask32
= 0;
2825 if (mask
& WRITEMASK_X
)
2826 mask32
|= WRITEMASK_XY
;
2827 if (mask
& WRITEMASK_Y
)
2828 mask32
|= WRITEMASK_ZW
;
2830 /* If the mask does not include any of the channels X or Y there
2831 * is nothing to do in this iteration. Move on to the next couple
2832 * of 64-bit channels.
2840 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2841 opcode
= indirect_offset
.file
!= BAD_FILE
?
2842 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2843 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2845 opcode
= indirect_offset
.file
!= BAD_FILE
?
2846 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2847 SHADER_OPCODE_URB_WRITE_SIMD8
;
2850 for (unsigned i
= 0; i
< iter_components
; i
++) {
2851 if (!(mask
& (1 << (i
+ first_component
))))
2855 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2857 /* We need to shuffle the 64-bit data to match the layout
2858 * expected by our 32-bit URB write messages. We use a temporary
2861 unsigned channel
= iter
* 2 + i
;
2862 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2864 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2865 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2866 offset(dest
, bld
, 1);
2871 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2872 (is_64bit
? 2 * first_component
: first_component
);
2874 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2875 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2877 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2878 inst
->offset
= imm_offset
;
2881 /* If this is a 64-bit attribute, select the next two 64-bit channels
2882 * to be handled in the next iteration.
2893 nir_emit_intrinsic(bld
, instr
);
2899 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2900 nir_intrinsic_instr
*instr
)
2902 assert(stage
== MESA_SHADER_TESS_EVAL
);
2903 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2906 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2907 dest
= get_nir_dest(instr
->dest
);
2909 switch (instr
->intrinsic
) {
2910 case nir_intrinsic_load_primitive_id
:
2911 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2913 case nir_intrinsic_load_tess_coord
:
2914 /* gl_TessCoord is part of the payload in g1-3 */
2915 for (unsigned i
= 0; i
< 3; i
++) {
2916 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2920 case nir_intrinsic_load_input
:
2921 case nir_intrinsic_load_per_vertex_input
: {
2922 fs_reg indirect_offset
= get_indirect_offset(instr
);
2923 unsigned imm_offset
= instr
->const_index
[0];
2924 unsigned first_component
= nir_intrinsic_component(instr
);
2926 if (type_sz(dest
.type
) == 8) {
2927 first_component
= first_component
/ 2;
2931 if (indirect_offset
.file
== BAD_FILE
) {
2932 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2933 * which is 16 registers (since each holds 2 vec4 slots).
2935 unsigned slot_count
= 1;
2936 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2939 const unsigned max_push_slots
= 32;
2940 if (imm_offset
+ slot_count
<= max_push_slots
) {
2941 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2942 for (int i
= 0; i
< instr
->num_components
; i
++) {
2943 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2944 i
+ first_component
;
2945 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2948 tes_prog_data
->base
.urb_read_length
=
2949 MAX2(tes_prog_data
->base
.urb_read_length
,
2950 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2952 /* Replicate the patch handle to all enabled channels */
2953 const fs_reg srcs
[] = {
2954 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2956 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2957 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2959 if (first_component
!= 0) {
2960 unsigned read_components
=
2961 instr
->num_components
+ first_component
;
2962 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2963 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2965 inst
->size_written
= read_components
* REG_SIZE
;
2966 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2967 bld
.MOV(offset(dest
, bld
, i
),
2968 offset(tmp
, bld
, i
+ first_component
));
2971 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2973 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2976 inst
->offset
= imm_offset
;
2979 /* Indirect indexing - use per-slot offsets as well. */
2981 /* We can only read two double components with each URB read, so
2982 * we send two read messages in that case, each one loading up to
2983 * two double components.
2985 unsigned num_iterations
= 1;
2986 unsigned num_components
= instr
->num_components
;
2987 fs_reg orig_dest
= dest
;
2988 if (type_sz(dest
.type
) == 8) {
2989 if (instr
->num_components
> 2) {
2993 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2997 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2998 const fs_reg srcs
[] = {
2999 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3002 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3003 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3005 if (first_component
!= 0) {
3006 unsigned read_components
=
3007 num_components
+ first_component
;
3008 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3009 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3011 for (unsigned i
= 0; i
< num_components
; i
++) {
3012 bld
.MOV(offset(dest
, bld
, i
),
3013 offset(tmp
, bld
, i
+ first_component
));
3016 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3020 inst
->offset
= imm_offset
;
3021 inst
->size_written
= (num_components
+ first_component
) *
3022 inst
->dst
.component_size(inst
->exec_size
);
3024 /* If we are reading 64-bit data using 32-bit read messages we need
3025 * build proper 64-bit data elements by shuffling the low and high
3026 * 32-bit components around like we do for other things like UBOs
3029 if (type_sz(dest
.type
) == 8) {
3030 shuffle_from_32bit_read(bld
,
3031 offset(orig_dest
, bld
, iter
* 2),
3032 retype(dest
, BRW_REGISTER_TYPE_D
),
3036 /* If we are loading double data and we need a second read message
3039 if (num_iterations
> 1) {
3040 num_components
= instr
->num_components
- 2;
3048 nir_emit_intrinsic(bld
, instr
);
3054 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3055 nir_intrinsic_instr
*instr
)
3057 assert(stage
== MESA_SHADER_GEOMETRY
);
3058 fs_reg indirect_offset
;
3061 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3062 dest
= get_nir_dest(instr
->dest
);
3064 switch (instr
->intrinsic
) {
3065 case nir_intrinsic_load_primitive_id
:
3066 assert(stage
== MESA_SHADER_GEOMETRY
);
3067 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3068 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3069 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3072 case nir_intrinsic_load_input
:
3073 unreachable("load_input intrinsics are invalid for the GS stage");
3075 case nir_intrinsic_load_per_vertex_input
:
3076 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3077 instr
->src
[1], instr
->num_components
,
3078 nir_intrinsic_component(instr
));
3081 case nir_intrinsic_emit_vertex_with_counter
:
3082 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3085 case nir_intrinsic_end_primitive_with_counter
:
3086 emit_gs_end_primitive(instr
->src
[0]);
3089 case nir_intrinsic_set_vertex_count
:
3090 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3093 case nir_intrinsic_load_invocation_id
: {
3094 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3095 assert(val
.file
!= BAD_FILE
);
3096 dest
.type
= val
.type
;
3102 nir_emit_intrinsic(bld
, instr
);
3108 * Fetch the current render target layer index.
3111 fetch_render_target_array_index(const fs_builder
&bld
)
3113 if (bld
.shader
->devinfo
->gen
>= 6) {
3114 /* The render target array index is provided in the thread payload as
3115 * bits 26:16 of r0.0.
3117 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3118 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3122 /* Pre-SNB we only ever render into the first layer of the framebuffer
3123 * since layered rendering is not implemented.
3125 return brw_imm_ud(0);
3130 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3131 * framebuffer at the current fragment coordinates and sample index.
3134 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3137 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3139 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3140 const brw_wm_prog_key
*wm_key
=
3141 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3142 assert(!wm_key
->coherent_fb_fetch
);
3143 const struct brw_wm_prog_data
*wm_prog_data
=
3144 brw_wm_prog_data(stage_prog_data
);
3146 /* Calculate the surface index relative to the start of the texture binding
3147 * table block, since that's what the texturing messages expect.
3149 const unsigned surface
= target
+
3150 wm_prog_data
->binding_table
.render_target_read_start
-
3151 wm_prog_data
->base
.binding_table
.texture_start
;
3153 brw_mark_surface_used(
3154 bld
.shader
->stage_prog_data
,
3155 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3157 /* Calculate the fragment coordinates. */
3158 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3159 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3160 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3161 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3163 /* Calculate the sample index and MCS payload when multisampling. Luckily
3164 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3165 * shouldn't be necessary to recompile based on whether the framebuffer is
3168 if (wm_key
->multisample_fbo
&&
3169 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3170 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3172 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3173 const fs_reg mcs
= wm_key
->multisample_fbo
?
3174 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3176 /* Use either a normal or a CMS texel fetch message depending on whether
3177 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3178 * message just in case the framebuffer uses 16x multisampling, it should
3179 * be equivalent to the normal CMS fetch for lower multisampling modes.
3181 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3182 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3183 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3185 /* Emit the instruction. */
3186 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3188 brw_imm_ud(surface
), brw_imm_ud(0),
3189 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3190 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3192 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3193 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3199 * Actual coherent framebuffer read implemented using the native render target
3200 * read message. Requires SKL+.
3203 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3205 assert(bld
.shader
->devinfo
->gen
>= 9);
3206 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3207 inst
->target
= target
;
3208 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3214 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3216 if (n
&& regs
[0].file
!= BAD_FILE
) {
3220 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3222 for (unsigned i
= 0; i
< n
; i
++)
3230 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3232 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3233 const brw_wm_prog_key
*const key
=
3234 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3235 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3236 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3238 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3239 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3241 else if (l
== FRAG_RESULT_COLOR
)
3242 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3243 MAX2(key
->nr_color_regions
, 1));
3245 else if (l
== FRAG_RESULT_DEPTH
)
3246 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3248 else if (l
== FRAG_RESULT_STENCIL
)
3249 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3251 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3252 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3254 else if (l
>= FRAG_RESULT_DATA0
&&
3255 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3256 return alloc_temporary(v
->bld
, 4,
3257 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3260 unreachable("Invalid location");
3264 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3265 nir_intrinsic_instr
*instr
)
3267 assert(stage
== MESA_SHADER_FRAGMENT
);
3270 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3271 dest
= get_nir_dest(instr
->dest
);
3273 switch (instr
->intrinsic
) {
3274 case nir_intrinsic_load_front_face
:
3275 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3276 *emit_frontfacing_interpolation());
3279 case nir_intrinsic_load_sample_pos
: {
3280 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3281 assert(sample_pos
.file
!= BAD_FILE
);
3282 dest
.type
= sample_pos
.type
;
3283 bld
.MOV(dest
, sample_pos
);
3284 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3288 case nir_intrinsic_load_layer_id
:
3289 dest
.type
= BRW_REGISTER_TYPE_UD
;
3290 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3293 case nir_intrinsic_load_helper_invocation
:
3294 case nir_intrinsic_load_sample_mask_in
:
3295 case nir_intrinsic_load_sample_id
: {
3296 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3297 fs_reg val
= nir_system_values
[sv
];
3298 assert(val
.file
!= BAD_FILE
);
3299 dest
.type
= val
.type
;
3304 case nir_intrinsic_store_output
: {
3305 const fs_reg src
= get_nir_src(instr
->src
[0]);
3306 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3307 assert(const_offset
&& "Indirect output stores not allowed");
3308 const unsigned location
= nir_intrinsic_base(instr
) +
3309 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3310 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3313 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3314 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3315 offset(src
, bld
, j
));
3320 case nir_intrinsic_load_output
: {
3321 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3322 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3323 assert(l
>= FRAG_RESULT_DATA0
);
3324 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3325 assert(const_offset
&& "Indirect output loads not allowed");
3326 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3327 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3329 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3330 emit_coherent_fb_read(bld
, tmp
, target
);
3332 emit_non_coherent_fb_read(bld
, tmp
, target
);
3334 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3335 bld
.MOV(offset(dest
, bld
, j
),
3336 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3342 case nir_intrinsic_discard
:
3343 case nir_intrinsic_discard_if
: {
3344 /* We track our discarded pixels in f0.1. By predicating on it, we can
3345 * update just the flag bits that aren't yet discarded. If there's no
3346 * condition, we emit a CMP of g0 != g0, so all currently executing
3347 * channels will get turned off.
3350 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3351 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3352 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3354 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3355 BRW_REGISTER_TYPE_UW
));
3356 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3358 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3359 cmp
->flag_subreg
= 1;
3361 if (devinfo
->gen
>= 6) {
3362 emit_discard_jump();
3365 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3369 case nir_intrinsic_load_input
: {
3370 /* load_input is only used for flat inputs */
3371 unsigned base
= nir_intrinsic_base(instr
);
3372 unsigned comp
= nir_intrinsic_component(instr
);
3373 unsigned num_components
= instr
->num_components
;
3374 fs_reg orig_dest
= dest
;
3375 enum brw_reg_type type
= dest
.type
;
3377 /* Special case fields in the VUE header */
3378 if (base
== VARYING_SLOT_LAYER
)
3380 else if (base
== VARYING_SLOT_VIEWPORT
)
3383 if (nir_dest_bit_size(instr
->dest
) == 64) {
3384 /* const_index is in 32-bit type size units that could not be aligned
3385 * with DF. We need to read the double vector as if it was a float
3386 * vector of twice the number of components to fetch the right data.
3388 type
= BRW_REGISTER_TYPE_F
;
3389 num_components
*= 2;
3390 dest
= bld
.vgrf(type
, num_components
);
3393 for (unsigned int i
= 0; i
< num_components
; i
++) {
3394 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3395 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3398 if (nir_dest_bit_size(instr
->dest
) == 64) {
3399 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3400 instr
->num_components
);
3405 case nir_intrinsic_load_barycentric_pixel
:
3406 case nir_intrinsic_load_barycentric_centroid
:
3407 case nir_intrinsic_load_barycentric_sample
:
3408 /* Do nothing - load_interpolated_input handling will handle it later. */
3411 case nir_intrinsic_load_barycentric_at_sample
: {
3412 const glsl_interp_mode interpolation
=
3413 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3415 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3418 unsigned msg_data
= const_sample
->i32
[0] << 4;
3420 emit_pixel_interpolater_send(bld
,
3421 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3424 brw_imm_ud(msg_data
),
3427 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3428 BRW_REGISTER_TYPE_UD
);
3430 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3431 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3432 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3433 bld
.exec_all().group(1, 0)
3434 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3435 emit_pixel_interpolater_send(bld
,
3436 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3442 /* Make a loop that sends a message to the pixel interpolater
3443 * for the sample number in each live channel. If there are
3444 * multiple channels with the same sample number then these
3445 * will be handled simultaneously with a single interation of
3448 bld
.emit(BRW_OPCODE_DO
);
3450 /* Get the next live sample number into sample_id_reg */
3451 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3453 /* Set the flag register so that we can perform the send
3454 * message on all channels that have the same sample number
3456 bld
.CMP(bld
.null_reg_ud(),
3457 sample_src
, sample_id
,
3458 BRW_CONDITIONAL_EQ
);
3459 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3460 bld
.exec_all().group(1, 0)
3461 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3463 emit_pixel_interpolater_send(bld
,
3464 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3469 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3471 /* Continue the loop if there are any live channels left */
3472 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3474 bld
.emit(BRW_OPCODE_WHILE
));
3480 case nir_intrinsic_load_barycentric_at_offset
: {
3481 const glsl_interp_mode interpolation
=
3482 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3484 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3487 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3488 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3490 emit_pixel_interpolater_send(bld
,
3491 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3494 brw_imm_ud(off_x
| (off_y
<< 4)),
3497 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3498 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3499 BRW_REGISTER_TYPE_F
);
3500 for (int i
= 0; i
< 2; i
++) {
3501 fs_reg temp
= vgrf(glsl_type::float_type
);
3502 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3503 fs_reg itemp
= vgrf(glsl_type::int_type
);
3505 bld
.MOV(itemp
, temp
);
3507 /* Clamp the upper end of the range to +7/16.
3508 * ARB_gpu_shader5 requires that we support a maximum offset
3509 * of +0.5, which isn't representable in a S0.4 value -- if
3510 * we didn't clamp it, we'd end up with -8/16, which is the
3511 * opposite of what the shader author wanted.
3513 * This is legal due to ARB_gpu_shader5's quantization
3516 * "Not all values of <offset> may be supported; x and y
3517 * offsets may be rounded to fixed-point values with the
3518 * number of fraction bits given by the
3519 * implementation-dependent constant
3520 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3522 set_condmod(BRW_CONDITIONAL_L
,
3523 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3526 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3527 emit_pixel_interpolater_send(bld
,
3537 case nir_intrinsic_load_interpolated_input
: {
3538 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3539 emit_fragcoord_interpolation(dest
);
3543 assert(instr
->src
[0].ssa
&&
3544 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3545 nir_intrinsic_instr
*bary_intrinsic
=
3546 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3547 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3548 enum glsl_interp_mode interp_mode
=
3549 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3552 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3553 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3554 /* Use the result of the PI message */
3555 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3557 /* Use the delta_xy values computed from the payload */
3558 enum brw_barycentric_mode bary
=
3559 brw_barycentric_mode(interp_mode
, bary_intrin
);
3561 dst_xy
= this->delta_xy
[bary
];
3564 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3566 component(interp_reg(nir_intrinsic_base(instr
),
3567 nir_intrinsic_component(instr
) + i
), 0);
3568 interp
.type
= BRW_REGISTER_TYPE_F
;
3569 dest
.type
= BRW_REGISTER_TYPE_F
;
3571 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3572 fs_reg tmp
= vgrf(glsl_type::float_type
);
3573 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3574 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3576 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3583 nir_emit_intrinsic(bld
, instr
);
3589 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3590 nir_intrinsic_instr
*instr
)
3592 assert(stage
== MESA_SHADER_COMPUTE
);
3593 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3596 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3597 dest
= get_nir_dest(instr
->dest
);
3599 switch (instr
->intrinsic
) {
3600 case nir_intrinsic_barrier
:
3602 cs_prog_data
->uses_barrier
= true;
3605 case nir_intrinsic_load_subgroup_id
:
3606 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3609 case nir_intrinsic_load_local_invocation_id
:
3610 case nir_intrinsic_load_work_group_id
: {
3611 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3612 fs_reg val
= nir_system_values
[sv
];
3613 assert(val
.file
!= BAD_FILE
);
3614 dest
.type
= val
.type
;
3615 for (unsigned i
= 0; i
< 3; i
++)
3616 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3620 case nir_intrinsic_load_num_work_groups
: {
3621 const unsigned surface
=
3622 cs_prog_data
->binding_table
.work_groups_start
;
3624 cs_prog_data
->uses_num_work_groups
= true;
3626 fs_reg surf_index
= brw_imm_ud(surface
);
3627 brw_mark_surface_used(prog_data
, surface
);
3629 /* Read the 3 GLuint components of gl_NumWorkGroups */
3630 for (unsigned i
= 0; i
< 3; i
++) {
3631 fs_reg read_result
=
3632 emit_untyped_read(bld
, surf_index
,
3634 1 /* dims */, 1 /* size */,
3635 BRW_PREDICATE_NONE
);
3636 read_result
.type
= dest
.type
;
3637 bld
.MOV(dest
, read_result
);
3638 dest
= offset(dest
, bld
, 1);
3643 case nir_intrinsic_shared_atomic_add
:
3644 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3646 case nir_intrinsic_shared_atomic_imin
:
3647 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3649 case nir_intrinsic_shared_atomic_umin
:
3650 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3652 case nir_intrinsic_shared_atomic_imax
:
3653 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3655 case nir_intrinsic_shared_atomic_umax
:
3656 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3658 case nir_intrinsic_shared_atomic_and
:
3659 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3661 case nir_intrinsic_shared_atomic_or
:
3662 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3664 case nir_intrinsic_shared_atomic_xor
:
3665 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3667 case nir_intrinsic_shared_atomic_exchange
:
3668 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3670 case nir_intrinsic_shared_atomic_comp_swap
:
3671 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3674 case nir_intrinsic_load_shared
: {
3675 assert(devinfo
->gen
>= 7);
3677 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3679 /* Get the offset to read from */
3681 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3683 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3685 offset_reg
= vgrf(glsl_type::uint_type
);
3687 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3688 brw_imm_ud(instr
->const_index
[0]));
3691 /* Read the vector */
3692 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3693 instr
->num_components
);
3697 case nir_intrinsic_store_shared
: {
3698 assert(devinfo
->gen
>= 7);
3701 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3704 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3707 unsigned writemask
= instr
->const_index
[1];
3709 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3710 * since the untyped writes below operate in units of 32-bits, which
3711 * means that we need to write twice as many components each time.
3712 * Also, we have to suffle 64-bit data to be in the appropriate layout
3713 * expected by our 32-bit write messages.
3715 unsigned type_size
= 4;
3716 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3718 val_reg
= shuffle_for_32bit_write(bld
, val_reg
, 0,
3719 instr
->num_components
);
3722 unsigned type_slots
= type_size
/ 4;
3724 /* Combine groups of consecutive enabled channels in one write
3725 * message. We use ffs to find the first enabled channel and then ffs on
3726 * the bit-inverse, down-shifted writemask to determine the length of
3727 * the block of enabled bits.
3730 unsigned first_component
= ffs(writemask
) - 1;
3731 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3733 /* We can't write more than 2 64-bit components at once. Limit the
3734 * length of the write to what we can do and let the next iteration
3738 length
= MIN2(2, length
);
3741 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3743 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3744 type_size
* first_component
);
3746 offset_reg
= vgrf(glsl_type::uint_type
);
3748 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3749 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3752 emit_untyped_write(bld
, surf_index
, offset_reg
,
3753 offset(val_reg
, bld
, first_component
* type_slots
),
3754 1 /* dims */, length
* type_slots
,
3755 BRW_PREDICATE_NONE
);
3757 /* Clear the bits in the writemask that we just wrote, then try
3758 * again to see if more channels are left.
3760 writemask
&= (15 << (first_component
+ length
));
3767 nir_emit_intrinsic(bld
, instr
);
3773 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3774 nir_op op
, brw_reg_type type
)
3776 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3777 switch (type_sz(type
)) {
3779 assert(type
!= BRW_REGISTER_TYPE_HF
);
3780 return retype(brw_imm_uw(value
.u16
[0]), type
);
3782 return retype(brw_imm_ud(value
.u32
[0]), type
);
3784 if (type
== BRW_REGISTER_TYPE_DF
)
3785 return setup_imm_df(bld
, value
.f64
[0]);
3787 return retype(brw_imm_u64(value
.u64
[0]), type
);
3789 unreachable("Invalid type size");
3794 brw_op_for_nir_reduction_op(nir_op op
)
3797 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3798 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3799 case nir_op_imul
: return BRW_OPCODE_MUL
;
3800 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3801 case nir_op_imin
: return BRW_OPCODE_SEL
;
3802 case nir_op_umin
: return BRW_OPCODE_SEL
;
3803 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3804 case nir_op_imax
: return BRW_OPCODE_SEL
;
3805 case nir_op_umax
: return BRW_OPCODE_SEL
;
3806 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3807 case nir_op_iand
: return BRW_OPCODE_AND
;
3808 case nir_op_ior
: return BRW_OPCODE_OR
;
3809 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3811 unreachable("Invalid reduction operation");
3815 static brw_conditional_mod
3816 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3819 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3820 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3821 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3822 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3823 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3824 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3825 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3826 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3827 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3828 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3829 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3830 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3831 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3833 unreachable("Invalid reduction operation");
3838 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3841 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3842 dest
= get_nir_dest(instr
->dest
);
3844 switch (instr
->intrinsic
) {
3845 case nir_intrinsic_image_deref_load
:
3846 case nir_intrinsic_image_deref_store
:
3847 case nir_intrinsic_image_deref_atomic_add
:
3848 case nir_intrinsic_image_deref_atomic_min
:
3849 case nir_intrinsic_image_deref_atomic_max
:
3850 case nir_intrinsic_image_deref_atomic_and
:
3851 case nir_intrinsic_image_deref_atomic_or
:
3852 case nir_intrinsic_image_deref_atomic_xor
:
3853 case nir_intrinsic_image_deref_atomic_exchange
:
3854 case nir_intrinsic_image_deref_atomic_comp_swap
: {
3855 using namespace image_access
;
3857 if (stage
== MESA_SHADER_FRAGMENT
&&
3858 instr
->intrinsic
!= nir_intrinsic_image_deref_load
)
3859 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3861 /* Get the referenced image variable and type. */
3862 nir_deref_instr
*deref
= nir_src_as_deref(instr
->src
[0]);
3863 const nir_variable
*var
= nir_deref_instr_get_variable(deref
);
3864 const glsl_type
*type
= var
->type
->without_array();
3865 const brw_reg_type base_type
= get_image_base_type(type
);
3867 /* Get some metadata from the image intrinsic. */
3868 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3869 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3870 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3871 const unsigned format
= var
->data
.image
.format
;
3872 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3874 /* Get the arguments of the image intrinsic. */
3875 const fs_reg image
= get_nir_image_deref(deref
);
3876 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3877 BRW_REGISTER_TYPE_UD
);
3878 const fs_reg src0
= (info
->num_srcs
>= 4 ?
3879 retype(get_nir_src(instr
->src
[3]), base_type
) :
3881 const fs_reg src1
= (info
->num_srcs
>= 5 ?
3882 retype(get_nir_src(instr
->src
[4]), base_type
) :
3886 /* Emit an image load, store or atomic op. */
3887 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
)
3888 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3890 else if (instr
->intrinsic
== nir_intrinsic_image_deref_store
)
3891 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3892 var
->data
.image
.write_only
? GL_NONE
: format
);
3895 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3896 surf_dims
, arr_dims
, dest_components
,
3897 get_image_atomic_op(instr
->intrinsic
, type
));
3899 /* Assign the result. */
3900 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3901 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3902 offset(tmp
, bld
, c
));
3907 case nir_intrinsic_memory_barrier_atomic_counter
:
3908 case nir_intrinsic_memory_barrier_buffer
:
3909 case nir_intrinsic_memory_barrier_image
:
3910 case nir_intrinsic_memory_barrier
: {
3911 const fs_builder ubld
= bld
.group(8, 0);
3912 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3913 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3914 ->size_written
= 2 * REG_SIZE
;
3918 case nir_intrinsic_group_memory_barrier
:
3919 case nir_intrinsic_memory_barrier_shared
:
3920 /* We treat these workgroup-level barriers as no-ops. This should be
3921 * safe at present and as long as:
3923 * - Memory access instructions are not subsequently reordered by the
3924 * compiler back-end.
3926 * - All threads from a given compute shader workgroup fit within a
3927 * single subslice and therefore talk to the same HDC shared unit
3928 * what supposedly guarantees ordering and coherency between threads
3929 * from the same workgroup. This may change in the future when we
3930 * start splitting workgroups across multiple subslices.
3932 * - The context is not in fault-and-stream mode, which could cause
3933 * memory transactions (including to SLM) prior to the barrier to be
3934 * replayed after the barrier if a pagefault occurs. This shouldn't
3935 * be a problem up to and including SKL because fault-and-stream is
3936 * not usable due to hardware issues, but that's likely to change in
3941 case nir_intrinsic_shader_clock
: {
3942 /* We cannot do anything if there is an event, so ignore it for now */
3943 const fs_reg shader_clock
= get_timestamp(bld
);
3944 const fs_reg srcs
[] = { component(shader_clock
, 0),
3945 component(shader_clock
, 1) };
3946 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3950 case nir_intrinsic_image_deref_size
: {
3951 /* Get the referenced image variable and type. */
3952 nir_deref_instr
*deref
= nir_src_as_deref(instr
->src
[0]);
3953 const nir_variable
*var
= nir_deref_instr_get_variable(deref
);
3954 const glsl_type
*type
= var
->type
->without_array();
3956 /* Get the size of the image. */
3957 const fs_reg image
= get_nir_image_deref(deref
);
3958 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3960 /* For 1DArray image types, the array index is stored in the Z component.
3961 * Fix this by swizzling the Z component to the Y component.
3963 const bool is_1d_array_image
=
3964 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3965 type
->sampler_array
;
3967 /* For CubeArray images, we should count the number of cubes instead
3968 * of the number of faces. Fix it by dividing the (Z component) by 6.
3970 const bool is_cube_array_image
=
3971 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3972 type
->sampler_array
;
3974 /* Copy all the components. */
3975 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3976 if ((int)c
>= type
->coordinate_components()) {
3977 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3979 } else if (c
== 1 && is_1d_array_image
) {
3980 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3981 offset(size
, bld
, 2));
3982 } else if (c
== 2 && is_cube_array_image
) {
3983 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3984 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3985 offset(size
, bld
, c
), brw_imm_d(6));
3987 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3988 offset(size
, bld
, c
));
3995 case nir_intrinsic_image_deref_samples
:
3996 /* The driver does not support multi-sampled images. */
3997 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4000 case nir_intrinsic_load_uniform
: {
4001 /* Offsets are in bytes but they should always aligned to
4004 assert(instr
->const_index
[0] % 4 == 0 ||
4005 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4007 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4009 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4011 assert(const_offset
->u32
[0] % type_sz(dest
.type
) == 0);
4012 /* For 16-bit types we add the module of the const_index[0]
4013 * offset to access to not 32-bit aligned element
4015 src
.offset
= const_offset
->u32
[0] + instr
->const_index
[0] % 4;
4017 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4018 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4021 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4022 BRW_REGISTER_TYPE_UD
);
4024 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4025 * go past the end of the uniform. In order to keep the n'th
4026 * component from running past, we subtract off the size of all but
4027 * one component of the vector.
4029 assert(instr
->const_index
[1] >=
4030 instr
->num_components
* (int) type_sz(dest
.type
));
4031 unsigned read_size
= instr
->const_index
[1] -
4032 (instr
->num_components
- 1) * type_sz(dest
.type
);
4034 bool supports_64bit_indirects
=
4035 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4037 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4038 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4039 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4040 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4041 indirect
, brw_imm_ud(read_size
));
4044 const unsigned num_mov_indirects
=
4045 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4046 /* We read a little bit less per MOV INDIRECT, as they are now
4047 * 32-bits ones instead of 64-bit. Fix read_size then.
4049 const unsigned read_size_32bit
= read_size
-
4050 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4051 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4052 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4053 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4054 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4055 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4056 indirect
, brw_imm_ud(read_size_32bit
));
4064 case nir_intrinsic_load_ubo
: {
4065 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4069 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4070 const_index
->u32
[0];
4071 surf_index
= brw_imm_ud(index
);
4072 brw_mark_surface_used(prog_data
, index
);
4074 /* The block index is not a constant. Evaluate the index expression
4075 * per-channel and add the base UBO index; we have to select a value
4076 * from any live channel.
4078 surf_index
= vgrf(glsl_type::uint_type
);
4079 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4080 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4081 surf_index
= bld
.emit_uniformize(surf_index
);
4083 /* Assume this may touch any UBO. It would be nice to provide
4084 * a tighter bound, but the array information is already lowered away.
4086 brw_mark_surface_used(prog_data
,
4087 stage_prog_data
->binding_table
.ubo_start
+
4088 nir
->info
.num_ubos
- 1);
4091 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4092 if (const_offset
== NULL
) {
4093 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4094 BRW_REGISTER_TYPE_UD
);
4096 for (int i
= 0; i
< instr
->num_components
; i
++)
4097 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4098 base_offset
, i
* type_sz(dest
.type
));
4100 /* Even if we are loading doubles, a pull constant load will load
4101 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4102 * need to load a full dvec4 we will have to emit 2 loads. This is
4103 * similar to demote_pull_constants(), except that in that case we
4104 * see individual accesses to each component of the vector and then
4105 * we let CSE deal with duplicate loads. Here we see a vector access
4106 * and we have to split it if necessary.
4108 const unsigned type_size
= type_sz(dest
.type
);
4110 /* See if we've selected this as a push constant candidate */
4112 const unsigned ubo_block
= const_index
->u32
[0];
4113 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
4116 for (int i
= 0; i
< 4; i
++) {
4117 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4118 if (range
->block
== ubo_block
&&
4119 offset_256b
>= range
->start
&&
4120 offset_256b
< range
->start
+ range
->length
) {
4122 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4123 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
4128 if (push_reg
.file
!= BAD_FILE
) {
4129 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4130 bld
.MOV(offset(dest
, bld
, i
),
4131 byte_offset(push_reg
, i
* type_size
));
4137 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4138 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4139 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4141 for (unsigned c
= 0; c
< instr
->num_components
;) {
4142 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4143 /* Number of usable components in the next block-aligned load. */
4144 const unsigned count
= MIN2(instr
->num_components
- c
,
4145 (block_sz
- base
% block_sz
) / type_size
);
4147 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4148 packed_consts
, surf_index
,
4149 brw_imm_ud(base
& ~(block_sz
- 1)));
4151 const fs_reg consts
=
4152 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4155 for (unsigned d
= 0; d
< count
; d
++)
4156 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4164 case nir_intrinsic_load_ssbo
: {
4165 assert(devinfo
->gen
>= 7);
4167 nir_const_value
*const_uniform_block
=
4168 nir_src_as_const_value(instr
->src
[0]);
4171 if (const_uniform_block
) {
4172 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4173 const_uniform_block
->u32
[0];
4174 surf_index
= brw_imm_ud(index
);
4175 brw_mark_surface_used(prog_data
, index
);
4177 surf_index
= vgrf(glsl_type::uint_type
);
4178 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4179 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4181 /* Assume this may touch any UBO. It would be nice to provide
4182 * a tighter bound, but the array information is already lowered away.
4184 brw_mark_surface_used(prog_data
,
4185 stage_prog_data
->binding_table
.ssbo_start
+
4186 nir
->info
.num_ssbos
- 1);
4190 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4192 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4194 offset_reg
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
);
4197 /* Read the vector */
4198 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4199 instr
->num_components
);
4204 case nir_intrinsic_store_ssbo
: {
4205 assert(devinfo
->gen
>= 7);
4207 if (stage
== MESA_SHADER_FRAGMENT
)
4208 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4212 nir_const_value
*const_uniform_block
=
4213 nir_src_as_const_value(instr
->src
[1]);
4214 if (const_uniform_block
) {
4215 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4216 const_uniform_block
->u32
[0];
4217 surf_index
= brw_imm_ud(index
);
4218 brw_mark_surface_used(prog_data
, index
);
4220 surf_index
= vgrf(glsl_type::uint_type
);
4221 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4222 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4224 brw_mark_surface_used(prog_data
,
4225 stage_prog_data
->binding_table
.ssbo_start
+
4226 nir
->info
.num_ssbos
- 1);
4230 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4233 unsigned writemask
= instr
->const_index
[0];
4235 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4236 * since the untyped writes below operate in units of 32-bits, which
4237 * means that we need to write twice as many components each time.
4238 * Also, we have to suffle 64-bit data to be in the appropriate layout
4239 * expected by our 32-bit write messages.
4241 unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4242 unsigned type_size
= bit_size
/ 8;
4244 /* Combine groups of consecutive enabled channels in one write
4245 * message. We use ffs to find the first enabled channel and then ffs on
4246 * the bit-inverse, down-shifted writemask to determine the num_components
4247 * of the block of enabled bits.
4250 unsigned first_component
= ffs(writemask
) - 1;
4251 unsigned num_components
= ffs(~(writemask
>> first_component
)) - 1;
4252 fs_reg write_src
= offset(val_reg
, bld
, first_component
);
4254 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4256 if (type_size
> 4) {
4257 /* We can't write more than 2 64-bit components at once. Limit
4258 * the num_components of the write to what we can do and let the next
4259 * iteration handle the rest.
4261 num_components
= MIN2(2, num_components
);
4262 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4264 } else if (type_size
< 4) {
4265 assert(type_size
== 2);
4266 /* For 16-bit types we pack two consecutive values into a 32-bit
4267 * word and use an untyped write message. For single values or not
4268 * 32-bit-aligned we need to use byte-scattered writes because
4269 * untyped writes works with 32-bit components with 32-bit
4270 * alignment. byte_scattered_write messages only support one
4271 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4272 * could be enabled we can not guarantee that not constant offsets
4273 * to be 32-bit aligned for 16-bit types. For example an array, of
4274 * 16-bit vec3 with array element stride of 6.
4276 * In the case of 32-bit aligned constant offsets if there is
4277 * a 3-components vector we submit one untyped-write message
4278 * of 32-bit (first two components), and one byte-scattered
4279 * write message (the last component).
4282 if ( !const_offset
|| ((const_offset
->u32
[0] +
4283 type_size
* first_component
) % 4)) {
4284 /* If we use a .yz writemask we also need to emit 2
4285 * byte-scattered write messages because of y-component not
4286 * being aligned to 32-bit.
4289 } else if (num_components
> 2 && (num_components
% 2)) {
4290 /* If there is an odd number of consecutive components we left
4291 * the not paired component for a following emit of length == 1
4292 * with byte_scattered_write.
4296 /* For num_components == 1 we are also shuffling the component
4297 * because byte scattered writes of 16-bit need values to be dword
4298 * aligned. Shuffling only one component would be the same as
4301 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4308 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4309 type_size
* first_component
);
4311 offset_reg
= vgrf(glsl_type::uint_type
);
4313 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4314 brw_imm_ud(type_size
* first_component
));
4317 if (type_size
< 4 && num_components
== 1) {
4318 assert(type_size
== 2);
4319 /* Untyped Surface messages have a fixed 32-bit size, so we need
4320 * to rely on byte scattered in order to write 16-bit elements.
4321 * The byte_scattered_write message needs that every written 16-bit
4322 * type to be aligned 32-bits (stride=2).
4324 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4328 BRW_PREDICATE_NONE
);
4330 assert(num_components
* type_size
<= 16);
4331 assert((num_components
* type_size
) % 4 == 0);
4332 assert(offset_reg
.file
!= BRW_IMMEDIATE_VALUE
||
4333 offset_reg
.ud
% 4 == 0);
4334 unsigned num_slots
= (num_components
* type_size
) / 4;
4336 emit_untyped_write(bld
, surf_index
, offset_reg
,
4338 1 /* dims */, num_slots
,
4339 BRW_PREDICATE_NONE
);
4342 /* Clear the bits in the writemask that we just wrote, then try
4343 * again to see if more channels are left.
4345 writemask
&= (15 << (first_component
+ num_components
));
4350 case nir_intrinsic_store_output
: {
4351 fs_reg src
= get_nir_src(instr
->src
[0]);
4353 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4354 assert(const_offset
&& "Indirect output stores not allowed");
4356 unsigned num_components
= instr
->num_components
;
4357 unsigned first_component
= nir_intrinsic_component(instr
);
4358 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4359 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4360 num_components
*= 2;
4363 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4364 4 * const_offset
->u32
[0]), src
.type
);
4365 for (unsigned j
= 0; j
< num_components
; j
++) {
4366 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4367 offset(src
, bld
, j
));
4372 case nir_intrinsic_ssbo_atomic_add
:
4373 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4375 case nir_intrinsic_ssbo_atomic_imin
:
4376 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4378 case nir_intrinsic_ssbo_atomic_umin
:
4379 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4381 case nir_intrinsic_ssbo_atomic_imax
:
4382 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4384 case nir_intrinsic_ssbo_atomic_umax
:
4385 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4387 case nir_intrinsic_ssbo_atomic_and
:
4388 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4390 case nir_intrinsic_ssbo_atomic_or
:
4391 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4393 case nir_intrinsic_ssbo_atomic_xor
:
4394 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4396 case nir_intrinsic_ssbo_atomic_exchange
:
4397 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4399 case nir_intrinsic_ssbo_atomic_comp_swap
:
4400 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4403 case nir_intrinsic_get_buffer_size
: {
4404 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4405 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4407 /* A resinfo's sampler message is used to get the buffer size. The
4408 * SIMD8's writeback message consists of four registers and SIMD16's
4409 * writeback message consists of 8 destination registers (two per each
4410 * component). Because we are only interested on the first channel of
4411 * the first returned component, where resinfo returns the buffer size
4412 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4413 * the dispatch width.
4415 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4416 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4417 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4420 ubld
.MOV(src_payload
, brw_imm_d(0));
4422 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4423 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4424 src_payload
, brw_imm_ud(index
));
4425 inst
->header_size
= 0;
4427 inst
->size_written
= 4 * REG_SIZE
;
4429 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4431 * "Out-of-bounds checking is always performed at a DWord granularity. If
4432 * any part of the DWord is out-of-bounds then the whole DWord is
4433 * considered out-of-bounds."
4435 * This implies that types with size smaller than 4-bytes need to be
4436 * padded if they don't complete the last dword of the buffer. But as we
4437 * need to maintain the original size we need to reverse the padding
4438 * calculation to return the correct size to know the number of elements
4439 * of an unsized array. As we stored in the last two bits of the surface
4440 * size the needed padding for the buffer, we calculate here the
4441 * original buffer_size reversing the surface_size calculation:
4443 * surface_size = isl_align(buffer_size, 4) +
4444 * (isl_align(buffer_size) - buffer_size)
4446 * buffer_size = surface_size & ~3 - surface_size & 3
4449 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4450 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4451 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4453 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4454 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4455 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4457 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4459 brw_mark_surface_used(prog_data
, index
);
4463 case nir_intrinsic_load_subgroup_invocation
:
4464 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4465 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4468 case nir_intrinsic_load_subgroup_eq_mask
:
4469 case nir_intrinsic_load_subgroup_ge_mask
:
4470 case nir_intrinsic_load_subgroup_gt_mask
:
4471 case nir_intrinsic_load_subgroup_le_mask
:
4472 case nir_intrinsic_load_subgroup_lt_mask
:
4473 unreachable("not reached");
4475 case nir_intrinsic_vote_any
: {
4476 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4478 /* The any/all predicates do not consider channel enables. To prevent
4479 * dead channels from affecting the result, we initialize the flag with
4480 * with the identity value for the logical operation.
4482 if (dispatch_width
== 32) {
4483 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4484 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4487 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4489 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4491 /* For some reason, the any/all predicates don't work properly with
4492 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4493 * doesn't read the correct subset of the flag register and you end up
4494 * getting garbage in the second half. Work around this by using a pair
4495 * of 1-wide MOVs and scattering the result.
4497 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4498 ubld
.MOV(res1
, brw_imm_d(0));
4499 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4500 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4501 BRW_PREDICATE_ALIGN1_ANY32H
,
4502 ubld
.MOV(res1
, brw_imm_d(-1)));
4504 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4507 case nir_intrinsic_vote_all
: {
4508 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4510 /* The any/all predicates do not consider channel enables. To prevent
4511 * dead channels from affecting the result, we initialize the flag with
4512 * with the identity value for the logical operation.
4514 if (dispatch_width
== 32) {
4515 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4516 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4517 brw_imm_ud(0xffffffff));
4519 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4521 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4523 /* For some reason, the any/all predicates don't work properly with
4524 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4525 * doesn't read the correct subset of the flag register and you end up
4526 * getting garbage in the second half. Work around this by using a pair
4527 * of 1-wide MOVs and scattering the result.
4529 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4530 ubld
.MOV(res1
, brw_imm_d(0));
4531 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4532 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4533 BRW_PREDICATE_ALIGN1_ALL32H
,
4534 ubld
.MOV(res1
, brw_imm_d(-1)));
4536 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4539 case nir_intrinsic_vote_feq
:
4540 case nir_intrinsic_vote_ieq
: {
4541 fs_reg value
= get_nir_src(instr
->src
[0]);
4542 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4543 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4544 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4547 fs_reg uniformized
= bld
.emit_uniformize(value
);
4548 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4550 /* The any/all predicates do not consider channel enables. To prevent
4551 * dead channels from affecting the result, we initialize the flag with
4552 * with the identity value for the logical operation.
4554 if (dispatch_width
== 32) {
4555 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4556 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4557 brw_imm_ud(0xffffffff));
4559 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4561 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4563 /* For some reason, the any/all predicates don't work properly with
4564 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4565 * doesn't read the correct subset of the flag register and you end up
4566 * getting garbage in the second half. Work around this by using a pair
4567 * of 1-wide MOVs and scattering the result.
4569 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4570 ubld
.MOV(res1
, brw_imm_d(0));
4571 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4572 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4573 BRW_PREDICATE_ALIGN1_ALL32H
,
4574 ubld
.MOV(res1
, brw_imm_d(-1)));
4576 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4580 case nir_intrinsic_ballot
: {
4581 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4582 BRW_REGISTER_TYPE_UD
);
4583 struct brw_reg flag
= brw_flag_reg(0, 0);
4584 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4585 * as f0.0. This is a problem for fragment programs as we currently use
4586 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4587 * programs yet so this isn't a problem. When we do, something will
4590 if (dispatch_width
== 32)
4591 flag
.type
= BRW_REGISTER_TYPE_UD
;
4593 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4594 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4596 if (instr
->dest
.ssa
.bit_size
> 32) {
4597 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4599 dest
.type
= BRW_REGISTER_TYPE_UD
;
4601 bld
.MOV(dest
, flag
);
4605 case nir_intrinsic_read_invocation
: {
4606 const fs_reg value
= get_nir_src(instr
->src
[0]);
4607 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4608 fs_reg tmp
= bld
.vgrf(value
.type
);
4610 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4611 bld
.emit_uniformize(invocation
));
4613 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4617 case nir_intrinsic_read_first_invocation
: {
4618 const fs_reg value
= get_nir_src(instr
->src
[0]);
4619 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4623 case nir_intrinsic_shuffle
: {
4624 const fs_reg value
= get_nir_src(instr
->src
[0]);
4625 const fs_reg index
= get_nir_src(instr
->src
[1]);
4627 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4631 case nir_intrinsic_first_invocation
: {
4632 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4633 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4634 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4635 fs_reg(component(tmp
, 0)));
4639 case nir_intrinsic_quad_broadcast
: {
4640 const fs_reg value
= get_nir_src(instr
->src
[0]);
4641 nir_const_value
*index
= nir_src_as_const_value(instr
->src
[1]);
4642 assert(nir_src_bit_size(instr
->src
[1]) == 32);
4644 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4645 value
, brw_imm_ud(index
->u32
[0]), brw_imm_ud(4));
4649 case nir_intrinsic_quad_swap_horizontal
: {
4650 const fs_reg value
= get_nir_src(instr
->src
[0]);
4651 const fs_reg tmp
= bld
.vgrf(value
.type
);
4652 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4654 const fs_reg src_left
= horiz_stride(value
, 2);
4655 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4656 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4657 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4659 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4661 * "When source or destination datatype is 64b or operation is
4662 * integer DWord multiply, regioning in Align1 must follow
4667 * 3. Source and Destination offset must be the same, except
4668 * the case of scalar source."
4670 * In order to work around this, we have to emit two 32-bit MOVs instead
4671 * of a single 64-bit MOV to do the shuffle.
4673 if (type_sz(value
.type
) > 4 &&
4674 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4675 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4676 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4677 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4678 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4679 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4680 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4681 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4682 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4684 ubld
.MOV(tmp_left
, src_right
);
4685 ubld
.MOV(tmp_right
, src_left
);
4687 bld
.MOV(retype(dest
, value
.type
), tmp
);
4691 case nir_intrinsic_quad_swap_vertical
: {
4692 const fs_reg value
= get_nir_src(instr
->src
[0]);
4693 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4694 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4695 const fs_reg tmp
= bld
.vgrf(value
.type
);
4696 const fs_builder ubld
= bld
.exec_all();
4697 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4698 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4699 bld
.MOV(retype(dest
, value
.type
), tmp
);
4701 /* For larger data types, we have to either emit dispatch_width many
4702 * MOVs or else fall back to doing indirects.
4704 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4705 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4707 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4712 case nir_intrinsic_quad_swap_diagonal
: {
4713 const fs_reg value
= get_nir_src(instr
->src
[0]);
4714 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4715 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4716 const fs_reg tmp
= bld
.vgrf(value
.type
);
4717 const fs_builder ubld
= bld
.exec_all();
4718 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4719 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4720 bld
.MOV(retype(dest
, value
.type
), tmp
);
4722 /* For larger data types, we have to either emit dispatch_width many
4723 * MOVs or else fall back to doing indirects.
4725 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4726 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4728 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4733 case nir_intrinsic_reduce
: {
4734 fs_reg src
= get_nir_src(instr
->src
[0]);
4735 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4736 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4737 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4738 cluster_size
= dispatch_width
;
4740 /* Figure out the source type */
4741 src
.type
= brw_type_for_nir_type(devinfo
,
4742 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4743 nir_src_bit_size(instr
->src
[0])));
4745 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4746 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4747 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4749 /* Set up a register for all of our scratching around and initialize it
4750 * to reduction operation's identity value.
4752 fs_reg scan
= bld
.vgrf(src
.type
);
4753 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4755 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4757 dest
.type
= src
.type
;
4758 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4759 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4760 * the distance between clusters is at least 2 GRFs. In this case,
4761 * we don't need the weird striding of the CLUSTER_BROADCAST
4762 * instruction and can just do regular MOVs.
4764 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4765 const unsigned groups
=
4766 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4767 const unsigned group_size
= dispatch_width
/ groups
;
4768 for (unsigned i
= 0; i
< groups
; i
++) {
4769 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4770 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4771 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4772 component(scan
, comp
));
4775 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4776 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4781 case nir_intrinsic_inclusive_scan
:
4782 case nir_intrinsic_exclusive_scan
: {
4783 fs_reg src
= get_nir_src(instr
->src
[0]);
4784 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4786 /* Figure out the source type */
4787 src
.type
= brw_type_for_nir_type(devinfo
,
4788 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4789 nir_src_bit_size(instr
->src
[0])));
4791 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4792 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4793 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4795 /* Set up a register for all of our scratching around and initialize it
4796 * to reduction operation's identity value.
4798 fs_reg scan
= bld
.vgrf(src
.type
);
4799 const fs_builder allbld
= bld
.exec_all();
4800 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4802 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4803 /* Exclusive scan is a bit harder because we have to do an annoying
4804 * shift of the contents before we can begin. To make things worse,
4805 * we can't do this with a normal stride; we have to use indirects.
4807 fs_reg shifted
= bld
.vgrf(src
.type
);
4808 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4809 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4811 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4812 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4816 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4818 bld
.MOV(retype(dest
, src
.type
), scan
);
4822 case nir_intrinsic_begin_invocation_interlock
: {
4823 const fs_builder ubld
= bld
.group(8, 0);
4824 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4826 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4832 case nir_intrinsic_end_invocation_interlock
: {
4833 /* We don't need to do anything here */
4838 unreachable("unknown intrinsic");
4843 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4844 int op
, nir_intrinsic_instr
*instr
)
4846 if (stage
== MESA_SHADER_FRAGMENT
)
4847 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4850 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4851 dest
= get_nir_dest(instr
->dest
);
4854 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4855 if (const_surface
) {
4856 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4857 const_surface
->u32
[0];
4858 surface
= brw_imm_ud(surf_index
);
4859 brw_mark_surface_used(prog_data
, surf_index
);
4861 surface
= vgrf(glsl_type::uint_type
);
4862 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4863 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4865 /* Assume this may touch any SSBO. This is the same we do for other
4866 * UBO/SSBO accesses with non-constant surface.
4868 brw_mark_surface_used(prog_data
,
4869 stage_prog_data
->binding_table
.ssbo_start
+
4870 nir
->info
.num_ssbos
- 1);
4873 fs_reg offset
= get_nir_src(instr
->src
[1]);
4874 fs_reg data1
= get_nir_src(instr
->src
[2]);
4876 if (op
== BRW_AOP_CMPWR
)
4877 data2
= get_nir_src(instr
->src
[3]);
4879 /* Emit the actual atomic operation */
4881 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4883 1 /* dims */, 1 /* rsize */,
4885 BRW_PREDICATE_NONE
);
4886 dest
.type
= atomic_result
.type
;
4887 bld
.MOV(dest
, atomic_result
);
4891 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4892 int op
, nir_intrinsic_instr
*instr
)
4895 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4896 dest
= get_nir_dest(instr
->dest
);
4898 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4900 fs_reg data1
= get_nir_src(instr
->src
[1]);
4902 if (op
== BRW_AOP_CMPWR
)
4903 data2
= get_nir_src(instr
->src
[2]);
4905 /* Get the offset */
4906 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4908 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4910 offset
= vgrf(glsl_type::uint_type
);
4912 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4913 brw_imm_ud(instr
->const_index
[0]));
4916 /* Emit the actual atomic operation operation */
4918 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4920 1 /* dims */, 1 /* rsize */,
4922 BRW_PREDICATE_NONE
);
4923 dest
.type
= atomic_result
.type
;
4924 bld
.MOV(dest
, atomic_result
);
4928 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4930 unsigned texture
= instr
->texture_index
;
4931 unsigned sampler
= instr
->sampler_index
;
4933 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4935 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4936 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4938 int lod_components
= 0;
4940 /* The hardware requires a LOD for buffer textures */
4941 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4942 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4944 uint32_t header_bits
= 0;
4945 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4946 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4947 switch (instr
->src
[i
].src_type
) {
4948 case nir_tex_src_bias
:
4949 srcs
[TEX_LOGICAL_SRC_LOD
] =
4950 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4952 case nir_tex_src_comparator
:
4953 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4955 case nir_tex_src_coord
:
4956 switch (instr
->op
) {
4958 case nir_texop_txf_ms
:
4959 case nir_texop_txf_ms_mcs
:
4960 case nir_texop_samples_identical
:
4961 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4964 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4968 case nir_tex_src_ddx
:
4969 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4970 lod_components
= nir_tex_instr_src_size(instr
, i
);
4972 case nir_tex_src_ddy
:
4973 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4975 case nir_tex_src_lod
:
4976 switch (instr
->op
) {
4978 srcs
[TEX_LOGICAL_SRC_LOD
] =
4979 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4982 srcs
[TEX_LOGICAL_SRC_LOD
] =
4983 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4986 srcs
[TEX_LOGICAL_SRC_LOD
] =
4987 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4991 case nir_tex_src_ms_index
:
4992 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4995 case nir_tex_src_offset
: {
4996 nir_const_value
*const_offset
=
4997 nir_src_as_const_value(instr
->src
[i
].src
);
4998 unsigned offset_bits
= 0;
5000 brw_texture_offset(const_offset
->i32
,
5001 nir_tex_instr_src_size(instr
, i
),
5003 header_bits
|= offset_bits
;
5005 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5006 retype(src
, BRW_REGISTER_TYPE_D
);
5011 case nir_tex_src_projector
:
5012 unreachable("should be lowered");
5014 case nir_tex_src_texture_offset
: {
5015 /* Figure out the highest possible texture index and mark it as used */
5016 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
5017 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
5018 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
5020 max_used
+= stage_prog_data
->binding_table
.texture_start
;
5022 brw_mark_surface_used(prog_data
, max_used
);
5024 /* Emit code to evaluate the actual indexing expression */
5025 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5026 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5027 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5031 case nir_tex_src_sampler_offset
: {
5032 /* Emit code to evaluate the actual indexing expression */
5033 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5034 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5035 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5039 case nir_tex_src_ms_mcs
:
5040 assert(instr
->op
== nir_texop_txf_ms
);
5041 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5044 case nir_tex_src_plane
: {
5045 nir_const_value
*const_plane
=
5046 nir_src_as_const_value(instr
->src
[i
].src
);
5047 const uint32_t plane
= const_plane
->u32
[0];
5048 const uint32_t texture_index
=
5049 instr
->texture_index
+
5050 stage_prog_data
->binding_table
.plane_start
[plane
] -
5051 stage_prog_data
->binding_table
.texture_start
;
5053 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5058 unreachable("unknown texture source");
5062 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5063 (instr
->op
== nir_texop_txf_ms
||
5064 instr
->op
== nir_texop_samples_identical
)) {
5065 if (devinfo
->gen
>= 7 &&
5066 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5067 srcs
[TEX_LOGICAL_SRC_MCS
] =
5068 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5069 instr
->coord_components
,
5070 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5072 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5076 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5077 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5080 switch (instr
->op
) {
5082 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5083 SHADER_OPCODE_TXL_LOGICAL
);
5086 opcode
= FS_OPCODE_TXB_LOGICAL
;
5089 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5092 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5095 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5097 case nir_texop_txf_ms
:
5098 if ((key_tex
->msaa_16
& (1 << sampler
)))
5099 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5101 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5103 case nir_texop_txf_ms_mcs
:
5104 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5106 case nir_texop_query_levels
:
5108 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5111 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5114 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5115 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5117 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5119 case nir_texop_texture_samples
:
5120 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5122 case nir_texop_samples_identical
: {
5123 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5125 /* If mcs is an immediate value, it means there is no MCS. In that case
5126 * just return false.
5128 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5129 bld
.MOV(dst
, brw_imm_ud(0u));
5130 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5131 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5132 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5133 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5134 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5136 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5137 BRW_CONDITIONAL_EQ
);
5142 unreachable("unknown texture opcode");
5145 if (instr
->op
== nir_texop_tg4
) {
5146 if (instr
->component
== 1 &&
5147 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5148 /* gather4 sampler is broken for green channel on RG32F --
5149 * we must ask for blue instead.
5151 header_bits
|= 2 << 16;
5153 header_bits
|= instr
->component
<< 16;
5157 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5158 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5159 inst
->offset
= header_bits
;
5161 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5162 if (devinfo
->gen
>= 9 &&
5163 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5164 unsigned write_mask
= instr
->dest
.is_ssa
?
5165 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5166 (1 << dest_size
) - 1;
5167 assert(write_mask
!= 0); /* dead code should have been eliminated */
5168 inst
->size_written
= util_last_bit(write_mask
) *
5169 inst
->dst
.component_size(inst
->exec_size
);
5171 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5174 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5175 inst
->shadow_compare
= true;
5177 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5178 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5181 for (unsigned i
= 0; i
< dest_size
; i
++)
5182 nir_dest
[i
] = offset(dst
, bld
, i
);
5184 if (instr
->op
== nir_texop_query_levels
) {
5185 /* # levels is in .w */
5186 nir_dest
[0] = offset(dst
, bld
, 3);
5187 } else if (instr
->op
== nir_texop_txs
&&
5188 dest_size
>= 3 && devinfo
->gen
< 7) {
5189 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5190 fs_reg depth
= offset(dst
, bld
, 2);
5191 nir_dest
[2] = vgrf(glsl_type::int_type
);
5192 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5195 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5199 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5201 switch (instr
->type
) {
5202 case nir_jump_break
:
5203 bld
.emit(BRW_OPCODE_BREAK
);
5205 case nir_jump_continue
:
5206 bld
.emit(BRW_OPCODE_CONTINUE
);
5208 case nir_jump_return
:
5210 unreachable("unknown jump");
5215 * This helper takes a source register and un/shuffles it into the destination
5218 * If source type size is smaller than destination type size the operation
5219 * needed is a component shuffle. The opposite case would be an unshuffle. If
5220 * source/destination type size is equal a shuffle is done that would be
5221 * equivalent to a simple MOV.
5223 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5224 * components .xyz 16-bit vector on SIMD8 would be.
5226 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5227 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5229 * This helper will return the following 2 32-bit components with the 16-bit
5232 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5233 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5235 * For unshuffle, the example would be the opposite, a 64-bit type source
5236 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5239 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5240 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5241 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5242 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5244 * The returned result would be the following 4 32-bit components unshuffled:
5246 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5247 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5248 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5249 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5251 * - Source and destination register must not be overlapped.
5252 * - components units are measured in terms of the smaller type between
5253 * source and destination because we are un/shuffling the smaller
5254 * components from/into the bigger ones.
5255 * - first_component parameter allows skipping source components.
5258 shuffle_src_to_dst(const fs_builder
&bld
,
5261 uint32_t first_component
,
5262 uint32_t components
)
5264 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5265 assert(!regions_overlap(dst
,
5266 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5267 offset(src
, bld
, first_component
),
5268 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5269 for (unsigned i
= 0; i
< components
; i
++) {
5270 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5271 offset(src
, bld
, i
+ first_component
));
5273 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5274 /* Source is shuffled into destination */
5275 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5276 assert(!regions_overlap(dst
,
5277 type_sz(dst
.type
) * bld
.dispatch_width() *
5278 DIV_ROUND_UP(components
, size_ratio
),
5279 offset(src
, bld
, first_component
),
5280 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5282 brw_reg_type shuffle_type
=
5283 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5284 BRW_REGISTER_TYPE_D
);
5285 for (unsigned i
= 0; i
< components
; i
++) {
5286 fs_reg shuffle_component_i
=
5287 subscript(offset(dst
, bld
, i
/ size_ratio
),
5288 shuffle_type
, i
% size_ratio
);
5289 bld
.MOV(shuffle_component_i
,
5290 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5293 /* Source is unshuffled into destination */
5294 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5295 assert(!regions_overlap(dst
,
5296 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5297 offset(src
, bld
, first_component
/ size_ratio
),
5298 type_sz(src
.type
) * bld
.dispatch_width() *
5299 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5302 brw_reg_type shuffle_type
=
5303 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5304 BRW_REGISTER_TYPE_D
);
5305 for (unsigned i
= 0; i
< components
; i
++) {
5306 fs_reg shuffle_component_i
=
5307 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5308 shuffle_type
, (first_component
+ i
) % size_ratio
);
5309 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5310 shuffle_component_i
);
5316 shuffle_from_32bit_read(const fs_builder
&bld
,
5319 uint32_t first_component
,
5320 uint32_t components
)
5322 assert(type_sz(src
.type
) == 4);
5324 /* This function takes components in units of the destination type while
5325 * shuffle_src_to_dst takes components in units of the smallest type
5327 if (type_sz(dst
.type
) > 4) {
5328 assert(type_sz(dst
.type
) == 8);
5329 first_component
*= 2;
5333 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5337 shuffle_for_32bit_write(const fs_builder
&bld
,
5339 uint32_t first_component
,
5340 uint32_t components
)
5342 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5343 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5344 /* This function takes components in units of the source type while
5345 * shuffle_src_to_dst takes components in units of the smallest type
5347 if (type_sz(src
.type
) > 4) {
5348 assert(type_sz(src
.type
) == 8);
5349 first_component
*= 2;
5353 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5359 setup_imm_df(const fs_builder
&bld
, double v
)
5361 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5362 assert(devinfo
->gen
>= 7);
5364 if (devinfo
->gen
>= 8)
5365 return brw_imm_df(v
);
5367 /* gen7.5 does not support DF immediates straighforward but the DIM
5368 * instruction allows to set the 64-bit immediate value.
5370 if (devinfo
->is_haswell
) {
5371 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5372 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5373 ubld
.DIM(dst
, brw_imm_df(v
));
5374 return component(dst
, 0);
5377 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5378 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5379 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5381 * Alternatively, we could also produce a normal VGRF (without stride 0)
5382 * by writing to all the channels in the VGRF, however, that would hit the
5383 * gen7 bug where we have to split writes that span more than 1 register
5384 * into instructions with a width of 4 (otherwise the write to the second
5385 * register written runs into an execmask hardware bug) which isn't very
5398 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5399 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5400 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5401 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5403 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);