2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
71 if (vec4s
[loc
] == 0) {
76 unsigned reg_size
= vec4s
[loc
];
78 /* Check if there are any ranges that start within this range and extend
79 * past it. If so, include them in this allocation.
81 for (unsigned i
= 1; i
< reg_size
; i
++)
82 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
84 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
85 for (unsigned i
= 0; i
< reg_size
; i
++)
86 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
93 fs_visitor::nir_setup_uniforms()
95 /* Only the first compile gets to set up uniforms. */
96 if (push_constant_loc
) {
97 assert(pull_constant_loc
);
101 uniforms
= nir
->num_uniforms
/ 4;
103 if (stage
== MESA_SHADER_COMPUTE
) {
104 /* Add a uniform for the thread local id. It must be the last uniform
107 assert(uniforms
== prog_data
->nr_params
);
108 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
109 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
110 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
115 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
119 nir_foreach_instr(instr
, block
) {
120 if (instr
->type
!= nir_instr_type_intrinsic
)
123 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
124 switch (intrin
->intrinsic
) {
125 case nir_intrinsic_load_vertex_id
:
126 case nir_intrinsic_load_base_vertex
:
127 unreachable("should be lowered by nir_lower_system_values().");
129 case nir_intrinsic_load_vertex_id_zero_base
:
130 case nir_intrinsic_load_is_indexed_draw
:
131 case nir_intrinsic_load_first_vertex
:
132 case nir_intrinsic_load_instance_id
:
133 case nir_intrinsic_load_base_instance
:
134 case nir_intrinsic_load_draw_id
:
135 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
137 case nir_intrinsic_load_invocation_id
:
138 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
140 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
141 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
142 if (reg
->file
== BAD_FILE
) {
143 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
144 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
145 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
146 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
151 case nir_intrinsic_load_sample_pos
:
152 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
153 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
154 if (reg
->file
== BAD_FILE
)
155 *reg
= *v
->emit_samplepos_setup();
158 case nir_intrinsic_load_sample_id
:
159 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
160 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
161 if (reg
->file
== BAD_FILE
)
162 *reg
= *v
->emit_sampleid_setup();
165 case nir_intrinsic_load_sample_mask_in
:
166 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
167 assert(v
->devinfo
->gen
>= 7);
168 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
169 if (reg
->file
== BAD_FILE
)
170 *reg
= *v
->emit_samplemaskin_setup();
173 case nir_intrinsic_load_work_group_id
:
174 assert(v
->stage
== MESA_SHADER_COMPUTE
);
175 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
176 if (reg
->file
== BAD_FILE
)
177 *reg
= *v
->emit_cs_work_group_id_setup();
180 case nir_intrinsic_load_helper_invocation
:
181 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
182 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
183 if (reg
->file
== BAD_FILE
) {
184 const fs_builder abld
=
185 v
->bld
.annotate("gl_HelperInvocation", NULL
);
187 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
188 * pixel mask is in g1.7 of the thread payload.
190 * We move the per-channel pixel enable bit to the low bit of each
191 * channel by shifting the byte containing the pixel mask by the
192 * vector immediate 0x76543210UV.
194 * The region of <1,8,0> reads only 1 byte (the pixel masks for
195 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
196 * masks for 2 and 3) in SIMD16.
198 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
200 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
201 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
202 hbld
.SHR(offset(shifted
, hbld
, i
),
203 stride(retype(brw_vec1_grf(1 + i
, 7),
204 BRW_REGISTER_TYPE_UB
),
206 brw_imm_v(0x76543210));
209 /* A set bit in the pixel mask means the channel is enabled, but
210 * that is the opposite of gl_HelperInvocation so we need to invert
213 * The negate source-modifier bit of logical instructions on Gen8+
214 * performs 1's complement negation, so we can use that instead of
217 fs_reg inverted
= negate(shifted
);
218 if (v
->devinfo
->gen
< 8) {
219 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
220 abld
.NOT(inverted
, shifted
);
223 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
224 * with 1 and negating.
226 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
227 abld
.AND(anded
, inverted
, brw_imm_uw(1));
229 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
230 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
244 fs_visitor::nir_emit_system_values()
246 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
247 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
248 nir_system_values
[i
] = fs_reg();
251 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
252 * never end up using it.
255 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
256 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
257 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
259 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
260 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
261 if (dispatch_width
> 8)
262 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
263 if (dispatch_width
> 16) {
264 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
265 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
269 nir_foreach_function(function
, nir
) {
270 assert(strcmp(function
->name
, "main") == 0);
271 assert(function
->impl
);
272 nir_foreach_block(block
, function
->impl
) {
273 emit_system_values_block(block
, this);
279 * Returns a type based on a reference_type (word, float, half-float) and a
282 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
284 * @FIXME: 64-bit return types are always DF on integer types to maintain
285 * compability with uses of DF previously to the introduction of int64
289 brw_reg_type_from_bit_size(const unsigned bit_size
,
290 const brw_reg_type reference_type
)
292 switch(reference_type
) {
293 case BRW_REGISTER_TYPE_HF
:
294 case BRW_REGISTER_TYPE_F
:
295 case BRW_REGISTER_TYPE_DF
:
298 return BRW_REGISTER_TYPE_HF
;
300 return BRW_REGISTER_TYPE_F
;
302 return BRW_REGISTER_TYPE_DF
;
304 unreachable("Invalid bit size");
306 case BRW_REGISTER_TYPE_W
:
307 case BRW_REGISTER_TYPE_D
:
308 case BRW_REGISTER_TYPE_Q
:
311 return BRW_REGISTER_TYPE_W
;
313 return BRW_REGISTER_TYPE_D
;
315 return BRW_REGISTER_TYPE_Q
;
317 unreachable("Invalid bit size");
319 case BRW_REGISTER_TYPE_UW
:
320 case BRW_REGISTER_TYPE_UD
:
321 case BRW_REGISTER_TYPE_UQ
:
324 return BRW_REGISTER_TYPE_UW
;
326 return BRW_REGISTER_TYPE_UD
;
328 return BRW_REGISTER_TYPE_UQ
;
330 unreachable("Invalid bit size");
333 unreachable("Unknown type");
338 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
340 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
341 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
342 nir_locals
[i
] = fs_reg();
345 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
346 unsigned array_elems
=
347 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
348 unsigned size
= array_elems
* reg
->num_components
;
349 const brw_reg_type reg_type
=
350 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
351 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
354 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
357 nir_emit_cf_list(&impl
->body
);
361 fs_visitor::nir_emit_cf_list(exec_list
*list
)
363 exec_list_validate(list
);
364 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
365 switch (node
->type
) {
367 nir_emit_if(nir_cf_node_as_if(node
));
370 case nir_cf_node_loop
:
371 nir_emit_loop(nir_cf_node_as_loop(node
));
374 case nir_cf_node_block
:
375 nir_emit_block(nir_cf_node_as_block(node
));
379 unreachable("Invalid CFG node block");
385 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
387 /* first, put the condition into f0 */
388 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
389 retype(get_nir_src(if_stmt
->condition
),
390 BRW_REGISTER_TYPE_D
));
391 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
393 bld
.IF(BRW_PREDICATE_NORMAL
);
395 nir_emit_cf_list(&if_stmt
->then_list
);
397 /* note: if the else is empty, dead CF elimination will remove it */
398 bld
.emit(BRW_OPCODE_ELSE
);
400 nir_emit_cf_list(&if_stmt
->else_list
);
402 bld
.emit(BRW_OPCODE_ENDIF
);
404 if (devinfo
->gen
< 7)
405 limit_dispatch_width(16, "Non-uniform control flow unsupported "
410 fs_visitor::nir_emit_loop(nir_loop
*loop
)
412 bld
.emit(BRW_OPCODE_DO
);
414 nir_emit_cf_list(&loop
->body
);
416 bld
.emit(BRW_OPCODE_WHILE
);
418 if (devinfo
->gen
< 7)
419 limit_dispatch_width(16, "Non-uniform control flow unsupported "
424 fs_visitor::nir_emit_block(nir_block
*block
)
426 nir_foreach_instr(instr
, block
) {
427 nir_emit_instr(instr
);
432 fs_visitor::nir_emit_instr(nir_instr
*instr
)
434 const fs_builder abld
= bld
.annotate(NULL
, instr
);
436 switch (instr
->type
) {
437 case nir_instr_type_alu
:
438 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
441 case nir_instr_type_deref
:
442 /* Derefs can exist for images but they do nothing */
445 case nir_instr_type_intrinsic
:
447 case MESA_SHADER_VERTEX
:
448 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
450 case MESA_SHADER_TESS_CTRL
:
451 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
453 case MESA_SHADER_TESS_EVAL
:
454 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_GEOMETRY
:
457 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_FRAGMENT
:
460 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case MESA_SHADER_COMPUTE
:
463 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
466 unreachable("unsupported shader stage");
470 case nir_instr_type_tex
:
471 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
474 case nir_instr_type_load_const
:
475 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
478 case nir_instr_type_ssa_undef
:
479 /* We create a new VGRF for undefs on every use (by handling
480 * them in get_nir_src()), rather than for each definition.
481 * This helps register coalescing eliminate MOVs from undef.
485 case nir_instr_type_jump
:
486 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
490 unreachable("unknown instruction type");
495 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
499 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
500 const fs_reg
&result
)
502 if (!instr
->src
[0].src
.is_ssa
||
503 !instr
->src
[0].src
.ssa
->parent_instr
)
506 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
509 nir_alu_instr
*src0
=
510 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
512 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
513 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
516 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
517 assert(element
!= NULL
);
519 /* Element type to extract.*/
520 const brw_reg_type type
= brw_int_type(
521 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
522 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
524 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
525 op0
.type
= brw_type_for_nir_type(devinfo
,
526 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
527 nir_src_bit_size(src0
->src
[0].src
)));
528 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
530 set_saturate(instr
->dest
.saturate
,
531 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
536 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
537 const fs_reg
&result
)
539 if (!instr
->src
[0].src
.is_ssa
||
540 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
543 nir_intrinsic_instr
*src0
=
544 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
546 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
549 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
550 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
553 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
554 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
557 fs_reg tmp
= vgrf(glsl_type::int_type
);
559 if (devinfo
->gen
>= 6) {
560 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
561 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
563 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
565 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
566 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
568 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
570 * This negation looks like it's safe in practice, because bits 0:4 will
571 * surely be TRIANGLES
574 if (value1
->f32
[0] == -1.0f
) {
578 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
579 g0
, brw_imm_uw(0x3f80));
581 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
582 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
584 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
586 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
587 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
589 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
591 * This negation looks like it's safe in practice, because bits 0:4 will
592 * surely be TRIANGLES
595 if (value1
->f32
[0] == -1.0f
) {
599 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
601 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
607 emit_find_msb_using_lzd(const fs_builder
&bld
,
608 const fs_reg
&result
,
616 /* LZD of an absolute value source almost always does the right
617 * thing. There are two problem values:
619 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
620 * 0. However, findMSB(int(0x80000000)) == 30.
622 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
623 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
625 * For a value of zero or negative one, -1 will be returned.
627 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
628 * findMSB(-(1<<x)) should return x-1.
630 * For all negative number cases, including 0x80000000 and
631 * 0xffffffff, the correct value is obtained from LZD if instead of
632 * negating the (already negative) value the logical-not is used. A
633 * conditonal logical-not can be achieved in two instructions.
635 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
637 bld
.ASR(temp
, src
, brw_imm_d(31));
638 bld
.XOR(temp
, temp
, src
);
641 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
642 retype(temp
, BRW_REGISTER_TYPE_UD
));
644 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
645 * from the LSB side. Subtract the result from 31 to convert the MSB
646 * count into an LSB count. If no bits are set, LZD will return 32.
647 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
649 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
650 inst
->src
[0].negate
= true;
654 brw_rnd_mode_from_nir_op (const nir_op op
) {
656 case nir_op_f2f16_rtz
:
657 return BRW_RND_MODE_RTZ
;
658 case nir_op_f2f16_rtne
:
659 return BRW_RND_MODE_RTNE
;
661 unreachable("Operation doesn't support rounding mode");
666 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
668 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
671 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
672 result
.type
= brw_type_for_nir_type(devinfo
,
673 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
674 nir_dest_bit_size(instr
->dest
.dest
)));
677 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
678 op
[i
] = get_nir_src(instr
->src
[i
].src
);
679 op
[i
].type
= brw_type_for_nir_type(devinfo
,
680 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
681 nir_src_bit_size(instr
->src
[i
].src
)));
682 op
[i
].abs
= instr
->src
[i
].abs
;
683 op
[i
].negate
= instr
->src
[i
].negate
;
686 /* We get a bunch of mov's out of the from_ssa pass and they may still
687 * be vectorized. We'll handle them as a special-case. We'll also
688 * handle vecN here because it's basically the same thing.
696 fs_reg temp
= result
;
697 bool need_extra_copy
= false;
698 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
699 if (!instr
->src
[i
].src
.is_ssa
&&
700 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
701 need_extra_copy
= true;
702 temp
= bld
.vgrf(result
.type
, 4);
707 for (unsigned i
= 0; i
< 4; i
++) {
708 if (!(instr
->dest
.write_mask
& (1 << i
)))
711 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
712 inst
= bld
.MOV(offset(temp
, bld
, i
),
713 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
715 inst
= bld
.MOV(offset(temp
, bld
, i
),
716 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
718 inst
->saturate
= instr
->dest
.saturate
;
721 /* In this case the source and destination registers were the same,
722 * so we need to insert an extra set of moves in order to deal with
725 if (need_extra_copy
) {
726 for (unsigned i
= 0; i
< 4; i
++) {
727 if (!(instr
->dest
.write_mask
& (1 << i
)))
730 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
739 /* At this point, we have dealt with any instruction that operates on
740 * more than a single channel. Therefore, we can just adjust the source
741 * and destination registers for that channel and emit the instruction.
743 unsigned channel
= 0;
744 if (nir_op_infos
[instr
->op
].output_size
== 0) {
745 /* Since NIR is doing the scalarizing for us, we should only ever see
746 * vectorized operations with a single channel.
748 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
749 channel
= ffs(instr
->dest
.write_mask
) - 1;
751 result
= offset(result
, bld
, channel
);
754 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
755 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
756 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
762 if (optimize_extract_to_float(instr
, result
))
764 inst
= bld
.MOV(result
, op
[0]);
765 inst
->saturate
= instr
->dest
.saturate
;
768 case nir_op_f2f16_rtne
:
769 case nir_op_f2f16_rtz
:
770 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
771 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
774 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
775 * on the HW gen, it is a special hw opcode or just a MOV, and
776 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
778 * But if we want to use that opcode, we need to provide support on
779 * different optimizations and lowerings. As right now HF support is
780 * only for gen8+, it will be better to use directly the MOV, and use
781 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
784 case nir_op_f2f16_undef
:
785 inst
= bld
.MOV(result
, op
[0]);
786 inst
->saturate
= instr
->dest
.saturate
;
796 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
798 * "When source or destination is 64b (...), regioning in Align1
799 * must follow these rules:
801 * 1. Source and destination horizontal stride must be aligned to
805 * This means that conversions from bit-sizes smaller than 64-bit to
806 * 64-bit need to have the source data elements aligned to 64-bit.
807 * This restriction does not apply to BDW and later.
809 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
810 nir_src_bit_size(instr
->src
[0].src
) < 64 &&
811 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
812 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
813 tmp
= subscript(tmp
, op
[0].type
, 0);
814 inst
= bld
.MOV(tmp
, op
[0]);
815 inst
= bld
.MOV(result
, tmp
);
816 inst
->saturate
= instr
->dest
.saturate
;
831 inst
= bld
.MOV(result
, op
[0]);
832 inst
->saturate
= instr
->dest
.saturate
;
837 /* Straightforward since the source can be assumed to be
840 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
841 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
843 } else if (type_sz(op
[0].type
) < 8) {
844 /* AND(val, 0x80000000) gives the sign bit.
846 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
849 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
851 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
852 op
[0].type
= BRW_REGISTER_TYPE_UD
;
853 result
.type
= BRW_REGISTER_TYPE_UD
;
854 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
856 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
857 inst
->predicate
= BRW_PREDICATE_NORMAL
;
858 if (instr
->dest
.saturate
) {
859 inst
= bld
.MOV(result
, result
);
860 inst
->saturate
= true;
863 /* For doubles we do the same but we need to consider:
865 * - 2-src instructions can't operate with 64-bit immediates
866 * - The sign is encoded in the high 32-bit of each DF
867 * - We need to produce a DF result.
870 fs_reg zero
= vgrf(glsl_type::double_type
);
871 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
872 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
874 bld
.MOV(result
, zero
);
876 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
877 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
878 brw_imm_ud(0x80000000u
));
880 set_predicate(BRW_PREDICATE_NORMAL
,
881 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
883 if (instr
->dest
.saturate
) {
884 inst
= bld
.MOV(result
, result
);
885 inst
->saturate
= true;
892 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
893 * -> non-negative val generates 0x00000000.
894 * Predicated OR sets 1 if val is positive.
896 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
897 assert(bit_size
== 32 || bit_size
== 16);
899 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
900 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
901 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
903 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
904 bld
.ASR(result
, op
[0], shift
);
905 inst
= bld
.OR(result
, result
, one
);
906 inst
->predicate
= BRW_PREDICATE_NORMAL
;
911 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
912 inst
->saturate
= instr
->dest
.saturate
;
916 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
917 inst
->saturate
= instr
->dest
.saturate
;
921 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
922 inst
->saturate
= instr
->dest
.saturate
;
926 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
927 inst
->saturate
= instr
->dest
.saturate
;
931 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
932 inst
->saturate
= instr
->dest
.saturate
;
936 if (fs_key
->high_quality_derivatives
) {
937 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
939 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
941 inst
->saturate
= instr
->dest
.saturate
;
943 case nir_op_fddx_fine
:
944 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
945 inst
->saturate
= instr
->dest
.saturate
;
947 case nir_op_fddx_coarse
:
948 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
949 inst
->saturate
= instr
->dest
.saturate
;
952 if (fs_key
->high_quality_derivatives
) {
953 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
955 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
957 inst
->saturate
= instr
->dest
.saturate
;
959 case nir_op_fddy_fine
:
960 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
961 inst
->saturate
= instr
->dest
.saturate
;
963 case nir_op_fddy_coarse
:
964 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
965 inst
->saturate
= instr
->dest
.saturate
;
970 inst
= bld
.ADD(result
, op
[0], op
[1]);
971 inst
->saturate
= instr
->dest
.saturate
;
975 inst
= bld
.MUL(result
, op
[0], op
[1]);
976 inst
->saturate
= instr
->dest
.saturate
;
980 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
981 bld
.MUL(result
, op
[0], op
[1]);
984 case nir_op_imul_high
:
985 case nir_op_umul_high
:
986 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
987 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
992 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
993 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
996 case nir_op_uadd_carry
:
997 unreachable("Should have been lowered by carry_to_arith().");
999 case nir_op_usub_borrow
:
1000 unreachable("Should have been lowered by borrow_to_arith().");
1004 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1005 * appears that our hardware just does the right thing for signed
1008 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1009 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1013 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1014 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1016 /* Math instructions don't support conditional mod */
1017 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1018 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1020 /* Now, we need to determine if signs of the sources are different.
1021 * When we XOR the sources, the top bit is 0 if they are the same and 1
1022 * if they are different. We can then use a conditional modifier to
1023 * turn that into a predicate. This leads us to an XOR.l instruction.
1025 * Technically, according to the PRM, you're not allowed to use .l on a
1026 * XOR instruction. However, emperical experiments and Curro's reading
1027 * of the simulator source both indicate that it's safe.
1029 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1030 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1031 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1032 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1034 /* If the result of the initial remainder operation is non-zero and the
1035 * two sources have different signs, add in a copy of op[1] to get the
1036 * final integer modulus value.
1038 inst
= bld
.ADD(result
, result
, op
[1]);
1039 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1047 fs_reg dest
= result
;
1049 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1051 dest
= bld
.vgrf(op
[0].type
, 1);
1053 brw_conditional_mod cond
;
1054 switch (instr
->op
) {
1056 cond
= BRW_CONDITIONAL_L
;
1059 cond
= BRW_CONDITIONAL_GE
;
1062 cond
= BRW_CONDITIONAL_Z
;
1065 cond
= BRW_CONDITIONAL_NZ
;
1068 unreachable("bad opcode");
1071 bld
.CMP(dest
, op
[0], op
[1], cond
);
1073 if (bit_size
> 32) {
1074 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1075 } else if(bit_size
< 32) {
1076 /* When we convert the result to 32-bit we need to be careful and do
1077 * it as a signed conversion to get sign extension (for 32-bit true)
1079 const brw_reg_type src_type
=
1080 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1082 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1093 fs_reg dest
= result
;
1095 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1097 dest
= bld
.vgrf(op
[0].type
, 1);
1099 brw_conditional_mod cond
;
1100 switch (instr
->op
) {
1103 cond
= BRW_CONDITIONAL_L
;
1107 cond
= BRW_CONDITIONAL_GE
;
1110 cond
= BRW_CONDITIONAL_Z
;
1113 cond
= BRW_CONDITIONAL_NZ
;
1116 unreachable("bad opcode");
1118 bld
.CMP(dest
, op
[0], op
[1], cond
);
1120 if (bit_size
> 32) {
1121 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1122 } else if (bit_size
< 32) {
1123 /* When we convert the result to 32-bit we need to be careful and do
1124 * it as a signed conversion to get sign extension (for 32-bit true)
1126 const brw_reg_type src_type
=
1127 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1129 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1135 if (devinfo
->gen
>= 8) {
1136 op
[0] = resolve_source_modifiers(op
[0]);
1138 bld
.NOT(result
, op
[0]);
1141 if (devinfo
->gen
>= 8) {
1142 op
[0] = resolve_source_modifiers(op
[0]);
1143 op
[1] = resolve_source_modifiers(op
[1]);
1145 bld
.XOR(result
, op
[0], op
[1]);
1148 if (devinfo
->gen
>= 8) {
1149 op
[0] = resolve_source_modifiers(op
[0]);
1150 op
[1] = resolve_source_modifiers(op
[1]);
1152 bld
.OR(result
, op
[0], op
[1]);
1155 if (devinfo
->gen
>= 8) {
1156 op
[0] = resolve_source_modifiers(op
[0]);
1157 op
[1] = resolve_source_modifiers(op
[1]);
1159 bld
.AND(result
, op
[0], op
[1]);
1165 case nir_op_ball_fequal2
:
1166 case nir_op_ball_iequal2
:
1167 case nir_op_ball_fequal3
:
1168 case nir_op_ball_iequal3
:
1169 case nir_op_ball_fequal4
:
1170 case nir_op_ball_iequal4
:
1171 case nir_op_bany_fnequal2
:
1172 case nir_op_bany_inequal2
:
1173 case nir_op_bany_fnequal3
:
1174 case nir_op_bany_inequal3
:
1175 case nir_op_bany_fnequal4
:
1176 case nir_op_bany_inequal4
:
1177 unreachable("Lowered by nir_lower_alu_reductions");
1179 case nir_op_fnoise1_1
:
1180 case nir_op_fnoise1_2
:
1181 case nir_op_fnoise1_3
:
1182 case nir_op_fnoise1_4
:
1183 case nir_op_fnoise2_1
:
1184 case nir_op_fnoise2_2
:
1185 case nir_op_fnoise2_3
:
1186 case nir_op_fnoise2_4
:
1187 case nir_op_fnoise3_1
:
1188 case nir_op_fnoise3_2
:
1189 case nir_op_fnoise3_3
:
1190 case nir_op_fnoise3_4
:
1191 case nir_op_fnoise4_1
:
1192 case nir_op_fnoise4_2
:
1193 case nir_op_fnoise4_3
:
1194 case nir_op_fnoise4_4
:
1195 unreachable("not reached: should be handled by lower_noise");
1198 unreachable("not reached: should be handled by ldexp_to_arith()");
1201 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1202 inst
->saturate
= instr
->dest
.saturate
;
1206 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1207 inst
->saturate
= instr
->dest
.saturate
;
1212 bld
.MOV(result
, negate(op
[0]));
1217 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1218 if (bit_size
== 64) {
1219 /* two-argument instructions can't take 64-bit immediates */
1223 if (instr
->op
== nir_op_f2b
) {
1224 zero
= vgrf(glsl_type::double_type
);
1225 tmp
= vgrf(glsl_type::double_type
);
1226 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1228 zero
= vgrf(glsl_type::int64_t_type
);
1229 tmp
= vgrf(glsl_type::int64_t_type
);
1230 bld
.MOV(zero
, brw_imm_q(0));
1233 /* A SIMD16 execution needs to be split in two instructions, so use
1234 * a vgrf instead of the flag register as dst so instruction splitting
1237 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1238 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1241 if (bit_size
== 32) {
1242 zero
= instr
->op
== nir_op_f2b
? brw_imm_f(0.0f
) : brw_imm_d(0);
1244 assert(bit_size
== 16);
1245 zero
= instr
->op
== nir_op_f2b
?
1246 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1248 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1254 inst
= bld
.RNDZ(result
, op
[0]);
1255 inst
->saturate
= instr
->dest
.saturate
;
1258 case nir_op_fceil
: {
1259 op
[0].negate
= !op
[0].negate
;
1260 fs_reg temp
= vgrf(glsl_type::float_type
);
1261 bld
.RNDD(temp
, op
[0]);
1263 inst
= bld
.MOV(result
, temp
);
1264 inst
->saturate
= instr
->dest
.saturate
;
1268 inst
= bld
.RNDD(result
, op
[0]);
1269 inst
->saturate
= instr
->dest
.saturate
;
1272 inst
= bld
.FRC(result
, op
[0]);
1273 inst
->saturate
= instr
->dest
.saturate
;
1275 case nir_op_fround_even
:
1276 inst
= bld
.RNDE(result
, op
[0]);
1277 inst
->saturate
= instr
->dest
.saturate
;
1280 case nir_op_fquantize2f16
: {
1281 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1282 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1283 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1285 /* The destination stride must be at least as big as the source stride. */
1286 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1289 /* Check for denormal */
1290 fs_reg abs_src0
= op
[0];
1291 abs_src0
.abs
= true;
1292 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1294 /* Get the appropriately signed zero */
1295 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1296 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1297 brw_imm_ud(0x80000000));
1298 /* Do the actual F32 -> F16 -> F32 conversion */
1299 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1300 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1301 /* Select that or zero based on normal status */
1302 inst
= bld
.SEL(result
, zero
, tmp32
);
1303 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1304 inst
->saturate
= instr
->dest
.saturate
;
1311 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1312 inst
->saturate
= instr
->dest
.saturate
;
1318 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1319 inst
->saturate
= instr
->dest
.saturate
;
1322 case nir_op_pack_snorm_2x16
:
1323 case nir_op_pack_snorm_4x8
:
1324 case nir_op_pack_unorm_2x16
:
1325 case nir_op_pack_unorm_4x8
:
1326 case nir_op_unpack_snorm_2x16
:
1327 case nir_op_unpack_snorm_4x8
:
1328 case nir_op_unpack_unorm_2x16
:
1329 case nir_op_unpack_unorm_4x8
:
1330 case nir_op_unpack_half_2x16
:
1331 case nir_op_pack_half_2x16
:
1332 unreachable("not reached: should be handled by lower_packing_builtins");
1334 case nir_op_unpack_half_2x16_split_x
:
1335 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1336 inst
->saturate
= instr
->dest
.saturate
;
1338 case nir_op_unpack_half_2x16_split_y
:
1339 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1340 inst
->saturate
= instr
->dest
.saturate
;
1343 case nir_op_pack_64_2x32_split
:
1344 case nir_op_pack_32_2x16_split
:
1345 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1348 case nir_op_unpack_64_2x32_split_x
:
1349 case nir_op_unpack_64_2x32_split_y
: {
1350 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1351 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1353 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1357 case nir_op_unpack_32_2x16_split_x
:
1358 case nir_op_unpack_32_2x16_split_y
: {
1359 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1360 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1362 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1367 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1368 inst
->saturate
= instr
->dest
.saturate
;
1371 case nir_op_bitfield_reverse
:
1372 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1373 bld
.BFREV(result
, op
[0]);
1376 case nir_op_bit_count
:
1377 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1378 bld
.CBIT(result
, op
[0]);
1381 case nir_op_ufind_msb
: {
1382 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1383 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1387 case nir_op_ifind_msb
: {
1388 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1390 if (devinfo
->gen
< 7) {
1391 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1393 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1395 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1396 * count from the LSB side. If FBH didn't return an error
1397 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1398 * count into an LSB count.
1400 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1402 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1403 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1404 inst
->src
[0].negate
= true;
1409 case nir_op_find_lsb
:
1410 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1412 if (devinfo
->gen
< 7) {
1413 fs_reg temp
= vgrf(glsl_type::int_type
);
1415 /* (x & -x) generates a value that consists of only the LSB of x.
1416 * For all powers of 2, findMSB(y) == findLSB(y).
1418 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1419 fs_reg negated_src
= src
;
1421 /* One must be negated, and the other must be non-negated. It
1422 * doesn't matter which is which.
1424 negated_src
.negate
= true;
1427 bld
.AND(temp
, src
, negated_src
);
1428 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1430 bld
.FBL(result
, op
[0]);
1434 case nir_op_ubitfield_extract
:
1435 case nir_op_ibitfield_extract
:
1436 unreachable("should have been lowered");
1439 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1440 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1443 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1444 bld
.BFI1(result
, op
[0], op
[1]);
1447 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1448 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1451 case nir_op_bitfield_insert
:
1452 unreachable("not reached: should have been lowered");
1457 fs_reg shift_count
= op
[1];
1459 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1460 if (op
[1].file
== VGRF
&&
1461 (result
.type
== BRW_REGISTER_TYPE_Q
||
1462 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1463 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1464 BRW_REGISTER_TYPE_UD
);
1465 shift_count
.stride
= 2;
1466 bld
.MOV(shift_count
, op
[1]);
1470 switch (instr
->op
) {
1472 bld
.SHL(result
, op
[0], shift_count
);
1475 bld
.ASR(result
, op
[0], shift_count
);
1478 bld
.SHR(result
, op
[0], shift_count
);
1481 unreachable("not reached");
1486 case nir_op_pack_half_2x16_split
:
1487 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1491 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1492 inst
->saturate
= instr
->dest
.saturate
;
1496 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1497 inst
->saturate
= instr
->dest
.saturate
;
1501 if (optimize_frontfacing_ternary(instr
, result
))
1504 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1505 inst
= bld
.SEL(result
, op
[1], op
[2]);
1506 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1509 case nir_op_extract_u8
:
1510 case nir_op_extract_i8
: {
1511 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1512 assert(byte
!= NULL
);
1517 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1518 * Use two instructions and a word or DWord intermediate integer type.
1520 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1521 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1523 if (instr
->op
== nir_op_extract_i8
) {
1524 /* If we need to sign extend, extract to a word first */
1525 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1526 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
->u32
[0]));
1527 bld
.MOV(result
, w_temp
);
1529 /* Otherwise use an AND with 0xff and a word type */
1530 bld
.AND(result
, subscript(op
[0], type
, byte
->u32
[0] / 2), brw_imm_uw(0xff));
1533 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1534 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1539 case nir_op_extract_u16
:
1540 case nir_op_extract_i16
: {
1541 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1542 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1543 assert(word
!= NULL
);
1544 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1549 unreachable("unhandled instruction");
1552 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1553 * to sign extend the low bit to 0/~0
1555 if (devinfo
->gen
<= 5 &&
1556 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1557 fs_reg masked
= vgrf(glsl_type::int_type
);
1558 bld
.AND(masked
, result
, brw_imm_d(1));
1559 masked
.negate
= true;
1560 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1565 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1566 nir_load_const_instr
*instr
)
1568 const brw_reg_type reg_type
=
1569 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1570 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1572 switch (instr
->def
.bit_size
) {
1574 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1575 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1579 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1580 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1584 assert(devinfo
->gen
>= 7);
1585 if (devinfo
->gen
== 7) {
1586 /* We don't get 64-bit integer types until gen8 */
1587 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1588 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1589 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1592 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1593 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1598 unreachable("Invalid bit size");
1601 nir_ssa_values
[instr
->def
.index
] = reg
;
1605 fs_visitor::get_nir_src(const nir_src
&src
)
1609 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1610 const brw_reg_type reg_type
=
1611 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1612 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1614 reg
= nir_ssa_values
[src
.ssa
->index
];
1617 /* We don't handle indirects on locals */
1618 assert(src
.reg
.indirect
== NULL
);
1619 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1620 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1623 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1624 /* The only 64-bit type available on gen7 is DF, so use that. */
1625 reg
.type
= BRW_REGISTER_TYPE_DF
;
1627 /* To avoid floating-point denorm flushing problems, set the type by
1628 * default to an integer type - instructions that need floating point
1629 * semantics will set this to F if they need to
1631 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1632 BRW_REGISTER_TYPE_D
);
1639 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1641 * This function should not be called on any value which may be 64 bits.
1642 * We could theoretically support 64-bit on gen8+ but we choose not to
1643 * because it wouldn't work in general (no gen7 support) and there are
1644 * enough restrictions in 64-bit immediates that you can't take the return
1645 * value and treat it the same as the result of get_nir_src().
1648 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1650 nir_const_value
*val
= nir_src_as_const_value(src
);
1651 assert(nir_src_bit_size(src
) == 32);
1652 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1656 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1659 const brw_reg_type reg_type
=
1660 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1661 nir_ssa_values
[dest
.ssa
.index
] =
1662 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1663 return nir_ssa_values
[dest
.ssa
.index
];
1665 /* We don't handle indirects on locals */
1666 assert(dest
.reg
.indirect
== NULL
);
1667 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1668 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1673 fs_visitor::get_nir_image_deref(nir_deref_instr
*deref
)
1675 fs_reg arr_offset
= brw_imm_ud(0);
1676 unsigned array_size
= BRW_IMAGE_PARAM_SIZE
* 4;
1677 nir_deref_instr
*head
= deref
;
1678 while (head
->deref_type
!= nir_deref_type_var
) {
1679 assert(head
->deref_type
== nir_deref_type_array
);
1681 /* This level's element size is the previous level's array size */
1682 const unsigned elem_size
= array_size
;
1684 fs_reg index
= retype(get_nir_src_imm(head
->arr
.index
),
1685 BRW_REGISTER_TYPE_UD
);
1686 if (arr_offset
.file
== BRW_IMMEDIATE_VALUE
&&
1687 index
.file
== BRW_IMMEDIATE_VALUE
) {
1688 arr_offset
.ud
+= index
.ud
* elem_size
;
1689 } else if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1690 bld
.ADD(arr_offset
, arr_offset
, brw_imm_ud(index
.ud
* elem_size
));
1692 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
1693 bld
.MUL(tmp
, index
, brw_imm_ud(elem_size
));
1694 bld
.ADD(tmp
, tmp
, arr_offset
);
1698 head
= nir_deref_instr_parent(head
);
1699 assert(glsl_type_is_array(head
->type
));
1700 array_size
= elem_size
* glsl_get_length(head
->type
);
1703 assert(head
->deref_type
== nir_deref_type_var
);
1704 const unsigned max_arr_offset
= array_size
- (BRW_IMAGE_PARAM_SIZE
* 4);
1705 fs_reg
image(UNIFORM
, head
->var
->data
.driver_location
/ 4,
1706 BRW_REGISTER_TYPE_UD
);
1708 if (arr_offset
.file
== BRW_IMMEDIATE_VALUE
) {
1709 /* The offset is in bytes but we want it in dwords */
1710 return offset(image
, bld
, MIN2(arr_offset
.ud
, max_arr_offset
) / 4);
1712 /* Accessing an invalid surface index with the dataport can result
1713 * in a hang. According to the spec "if the index used to
1714 * select an individual element is negative or greater than or
1715 * equal to the size of the array, the results of the operation
1716 * are undefined but may not lead to termination" -- which is one
1717 * of the possible outcomes of the hang. Clamp the index to
1718 * prevent access outside of the array bounds.
1720 bld
.emit_minmax(arr_offset
, arr_offset
, brw_imm_ud(max_arr_offset
),
1723 /* Emit a pile of MOVs to load the uniform into a temporary. The
1724 * dead-code elimination pass will get rid of what we don't use.
1726 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1727 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1728 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1729 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1730 arr_offset
, brw_imm_ud(max_arr_offset
+ 4));
1737 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1740 for (unsigned i
= 0; i
< 4; i
++) {
1741 if (!((wr_mask
>> i
) & 1))
1744 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1745 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1746 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1747 if (new_inst
->src
[j
].file
== VGRF
)
1748 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1755 * Get the matching channel register datatype for an image intrinsic of the
1756 * specified GLSL image type.
1759 get_image_base_type(const glsl_type
*type
)
1761 switch ((glsl_base_type
)type
->sampled_type
) {
1762 case GLSL_TYPE_UINT
:
1763 return BRW_REGISTER_TYPE_UD
;
1765 return BRW_REGISTER_TYPE_D
;
1766 case GLSL_TYPE_FLOAT
:
1767 return BRW_REGISTER_TYPE_F
;
1769 unreachable("Not reached.");
1774 * Get the appropriate atomic op for an image atomic intrinsic.
1777 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1780 case nir_intrinsic_image_deref_atomic_add
:
1782 case nir_intrinsic_image_deref_atomic_min
:
1783 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1784 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1785 case nir_intrinsic_image_deref_atomic_max
:
1786 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1787 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1788 case nir_intrinsic_image_deref_atomic_and
:
1790 case nir_intrinsic_image_deref_atomic_or
:
1792 case nir_intrinsic_image_deref_atomic_xor
:
1794 case nir_intrinsic_image_deref_atomic_exchange
:
1796 case nir_intrinsic_image_deref_atomic_comp_swap
:
1797 return BRW_AOP_CMPWR
;
1799 unreachable("Not reachable.");
1804 emit_pixel_interpolater_send(const fs_builder
&bld
,
1809 glsl_interp_mode interpolation
)
1811 struct brw_wm_prog_data
*wm_prog_data
=
1812 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1814 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1815 /* 2 floats per slot returned */
1816 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1817 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1819 wm_prog_data
->pulls_bary
= true;
1825 * Computes 1 << x, given a D/UD register containing some value x.
1828 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1830 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1832 fs_reg result
= bld
.vgrf(x
.type
, 1);
1833 fs_reg one
= bld
.vgrf(x
.type
, 1);
1835 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1836 bld
.SHL(result
, one
, x
);
1841 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1843 assert(stage
== MESA_SHADER_GEOMETRY
);
1845 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1847 if (gs_compile
->control_data_header_size_bits
== 0)
1850 /* We can only do EndPrimitive() functionality when the control data
1851 * consists of cut bits. Fortunately, the only time it isn't is when the
1852 * output type is points, in which case EndPrimitive() is a no-op.
1854 if (gs_prog_data
->control_data_format
!=
1855 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1859 /* Cut bits use one bit per vertex. */
1860 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1862 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1863 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1865 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1866 * vertex n, 0 otherwise. So all we need to do here is mark bit
1867 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1868 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1869 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1871 * Note that if EndPrimitive() is called before emitting any vertices, this
1872 * will cause us to set bit 31 of the control_data_bits register to 1.
1873 * That's fine because:
1875 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1876 * output, so the hardware will ignore cut bit 31.
1878 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1879 * last vertex, so setting cut bit 31 has no effect (since the primitive
1880 * is automatically ended when the GS terminates).
1882 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1883 * control_data_bits register to 0 when the first vertex is emitted.
1886 const fs_builder abld
= bld
.annotate("end primitive");
1888 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1889 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1890 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1891 fs_reg mask
= intexp2(abld
, prev_count
);
1892 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1893 * attention to the lower 5 bits of its second source argument, so on this
1894 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1895 * ((vertex_count - 1) % 32).
1897 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1901 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1903 assert(stage
== MESA_SHADER_GEOMETRY
);
1904 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1906 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1908 const fs_builder abld
= bld
.annotate("emit control data bits");
1909 const fs_builder fwa_bld
= bld
.exec_all();
1911 /* We use a single UD register to accumulate control data bits (32 bits
1912 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1915 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1916 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1917 * use the Channel Mask phase to enable/disable which DWord within that
1918 * group to write. (Remember, different SIMD8 channels may have emitted
1919 * different numbers of vertices, so we may need per-slot offsets.)
1921 * Channel masking presents an annoying problem: we may have to replicate
1922 * the data up to 4 times:
1924 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1926 * To avoid penalizing shaders that emit a small number of vertices, we
1927 * can avoid these sometimes: if the size of the control data header is
1928 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1929 * land in the same 128-bit group, so we can skip per-slot offsets.
1931 * Similarly, if the control data header is <= 32 bits, there is only one
1932 * DWord, so we can skip channel masks.
1934 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1936 fs_reg channel_mask
, per_slot_offset
;
1938 if (gs_compile
->control_data_header_size_bits
> 32) {
1939 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1940 channel_mask
= vgrf(glsl_type::uint_type
);
1943 if (gs_compile
->control_data_header_size_bits
> 128) {
1944 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1945 per_slot_offset
= vgrf(glsl_type::uint_type
);
1948 /* Figure out which DWord we're trying to write to using the formula:
1950 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1952 * Since bits_per_vertex is a power of two, and is known at compile
1953 * time, this can be optimized to:
1955 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1957 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1958 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1959 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1960 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1961 unsigned log2_bits_per_vertex
=
1962 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1963 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1965 if (per_slot_offset
.file
!= BAD_FILE
) {
1966 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1967 * the appropriate OWord within the control data header.
1969 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1972 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1973 * write to the appropriate DWORD within the OWORD.
1975 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1976 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1977 channel_mask
= intexp2(fwa_bld
, channel
);
1978 /* Then the channel masks need to be in bits 23:16. */
1979 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1982 /* Store the control data bits in the message payload and send it. */
1984 if (channel_mask
.file
!= BAD_FILE
)
1985 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1986 if (per_slot_offset
.file
!= BAD_FILE
)
1989 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1990 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1992 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1993 if (per_slot_offset
.file
!= BAD_FILE
)
1994 sources
[i
++] = per_slot_offset
;
1995 if (channel_mask
.file
!= BAD_FILE
)
1996 sources
[i
++] = channel_mask
;
1998 sources
[i
++] = this->control_data_bits
;
2001 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2002 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2004 /* We need to increment Global Offset by 256-bits to make room for
2005 * Broadwell's extra "Vertex Count" payload at the beginning of the
2006 * URB entry. Since this is an OWord message, Global Offset is counted
2007 * in 128-bit units, so we must set it to 2.
2009 if (gs_prog_data
->static_vertex_count
== -1)
2014 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2017 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2019 /* Note: we are calling this *before* increasing vertex_count, so
2020 * this->vertex_count == vertex_count - 1 in the formula above.
2023 /* Stream mode uses 2 bits per vertex */
2024 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2026 /* Must be a valid stream */
2027 assert(stream_id
< MAX_VERTEX_STREAMS
);
2029 /* Control data bits are initialized to 0 so we don't have to set any
2030 * bits when sending vertices to stream 0.
2035 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2037 /* reg::sid = stream_id */
2038 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2039 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2041 /* reg:shift_count = 2 * (vertex_count - 1) */
2042 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2043 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2045 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2046 * attention to the lower 5 bits of its second source argument, so on this
2047 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2048 * stream_id << ((2 * (vertex_count - 1)) % 32).
2050 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2051 abld
.SHL(mask
, sid
, shift_count
);
2052 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2056 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2059 assert(stage
== MESA_SHADER_GEOMETRY
);
2061 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2063 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2064 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2066 /* Haswell and later hardware ignores the "Render Stream Select" bits
2067 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2068 * and instead sends all primitives down the pipeline for rasterization.
2069 * If the SOL stage is enabled, "Render Stream Select" is honored and
2070 * primitives bound to non-zero streams are discarded after stream output.
2072 * Since the only purpose of primives sent to non-zero streams is to
2073 * be recorded by transform feedback, we can simply discard all geometry
2074 * bound to these streams when transform feedback is disabled.
2076 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2079 /* If we're outputting 32 control data bits or less, then we can wait
2080 * until the shader is over to output them all. Otherwise we need to
2081 * output them as we go. Now is the time to do it, since we're about to
2082 * output the vertex_count'th vertex, so it's guaranteed that the
2083 * control data bits associated with the (vertex_count - 1)th vertex are
2086 if (gs_compile
->control_data_header_size_bits
> 32) {
2087 const fs_builder abld
=
2088 bld
.annotate("emit vertex: emit control data bits");
2090 /* Only emit control data bits if we've finished accumulating a batch
2091 * of 32 bits. This is the case when:
2093 * (vertex_count * bits_per_vertex) % 32 == 0
2095 * (in other words, when the last 5 bits of vertex_count *
2096 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2097 * integer n (which is always the case, since bits_per_vertex is
2098 * always 1 or 2), this is equivalent to requiring that the last 5-n
2099 * bits of vertex_count are 0:
2101 * vertex_count & (2^(5-n) - 1) == 0
2103 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2106 * vertex_count & (32 / bits_per_vertex - 1) == 0
2108 * TODO: If vertex_count is an immediate, we could do some of this math
2109 * at compile time...
2112 abld
.AND(bld
.null_reg_d(), vertex_count
,
2113 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2114 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2116 abld
.IF(BRW_PREDICATE_NORMAL
);
2117 /* If vertex_count is 0, then no control data bits have been
2118 * accumulated yet, so we can skip emitting them.
2120 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2121 BRW_CONDITIONAL_NEQ
);
2122 abld
.IF(BRW_PREDICATE_NORMAL
);
2123 emit_gs_control_data_bits(vertex_count
);
2124 abld
.emit(BRW_OPCODE_ENDIF
);
2126 /* Reset control_data_bits to 0 so we can start accumulating a new
2129 * Note: in the case where vertex_count == 0, this neutralizes the
2130 * effect of any call to EndPrimitive() that the shader may have
2131 * made before outputting its first vertex.
2133 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2134 inst
->force_writemask_all
= true;
2135 abld
.emit(BRW_OPCODE_ENDIF
);
2138 emit_urb_writes(vertex_count
);
2140 /* In stream mode we have to set control data bits for all vertices
2141 * unless we have disabled control data bits completely (which we do
2142 * do for GL_POINTS outputs that don't use streams).
2144 if (gs_compile
->control_data_header_size_bits
> 0 &&
2145 gs_prog_data
->control_data_format
==
2146 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2147 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2152 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2153 const nir_src
&vertex_src
,
2154 unsigned base_offset
,
2155 const nir_src
&offset_src
,
2156 unsigned num_components
,
2157 unsigned first_component
)
2159 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2161 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2162 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2163 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2165 /* TODO: figure out push input layout for invocations == 1 */
2166 /* TODO: make this work with 64-bit inputs */
2167 if (gs_prog_data
->invocations
== 1 &&
2168 type_sz(dst
.type
) <= 4 &&
2169 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2170 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2171 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2172 vertex_const
->u32
[0] * push_reg_count
;
2173 for (unsigned i
= 0; i
< num_components
; i
++) {
2174 bld
.MOV(offset(dst
, bld
, i
),
2175 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2180 /* Resort to the pull model. Ensure the VUE handles are provided. */
2181 assert(gs_prog_data
->base
.include_vue_handles
);
2183 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2184 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2186 if (gs_prog_data
->invocations
== 1) {
2188 /* The vertex index is constant; just select the proper URB handle. */
2190 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2191 BRW_REGISTER_TYPE_UD
);
2193 /* The vertex index is non-constant. We need to use indirect
2194 * addressing to fetch the proper URB handle.
2196 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2197 * indicating that channel <n> should read the handle from
2198 * DWord <n>. We convert that to bytes by multiplying by 4.
2200 * Next, we convert the vertex index to bytes by multiplying
2201 * by 32 (shifting by 5), and add the two together. This is
2202 * the final indirect byte offset.
2204 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2205 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2206 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2207 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2209 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2210 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2211 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2212 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2213 /* Convert vertex_index to bytes (multiply by 32) */
2214 bld
.SHL(vertex_offset_bytes
,
2215 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2217 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2219 /* Use first_icp_handle as the base offset. There is one register
2220 * of URB handles per vertex, so inform the register allocator that
2221 * we might read up to nir->info.gs.vertices_in registers.
2223 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2224 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2225 fs_reg(icp_offset_bytes
),
2226 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2229 assert(gs_prog_data
->invocations
> 1);
2232 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2234 retype(brw_vec1_grf(first_icp_handle
+
2235 vertex_const
->i32
[0] / 8,
2236 vertex_const
->i32
[0] % 8),
2237 BRW_REGISTER_TYPE_UD
));
2239 /* The vertex index is non-constant. We need to use indirect
2240 * addressing to fetch the proper URB handle.
2243 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2245 /* Convert vertex_index to bytes (multiply by 4) */
2246 bld
.SHL(icp_offset_bytes
,
2247 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2250 /* Use first_icp_handle as the base offset. There is one DWord
2251 * of URB handles per vertex, so inform the register allocator that
2252 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2254 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2255 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2256 fs_reg(icp_offset_bytes
),
2257 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2264 fs_reg tmp_dst
= dst
;
2265 fs_reg indirect_offset
= get_nir_src(offset_src
);
2266 unsigned num_iterations
= 1;
2267 unsigned orig_num_components
= num_components
;
2269 if (type_sz(dst
.type
) == 8) {
2270 if (num_components
> 2) {
2274 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2276 first_component
= first_component
/ 2;
2279 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2281 /* Constant indexing - use global offset. */
2282 if (first_component
!= 0) {
2283 unsigned read_components
= num_components
+ first_component
;
2284 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2285 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2286 inst
->size_written
= read_components
*
2287 tmp
.component_size(inst
->exec_size
);
2288 for (unsigned i
= 0; i
< num_components
; i
++) {
2289 bld
.MOV(offset(tmp_dst
, bld
, i
),
2290 offset(tmp
, bld
, i
+ first_component
));
2293 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2295 inst
->size_written
= num_components
*
2296 tmp_dst
.component_size(inst
->exec_size
);
2298 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2301 /* Indirect indexing - use per-slot offsets as well. */
2302 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2303 unsigned read_components
= num_components
+ first_component
;
2304 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2305 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2306 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2307 if (first_component
!= 0) {
2308 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2310 inst
->size_written
= read_components
*
2311 tmp
.component_size(inst
->exec_size
);
2312 for (unsigned i
= 0; i
< num_components
; i
++) {
2313 bld
.MOV(offset(tmp_dst
, bld
, i
),
2314 offset(tmp
, bld
, i
+ first_component
));
2317 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2319 inst
->size_written
= num_components
*
2320 tmp_dst
.component_size(inst
->exec_size
);
2322 inst
->offset
= base_offset
;
2326 if (type_sz(dst
.type
) == 8) {
2327 shuffle_from_32bit_read(bld
,
2328 offset(dst
, bld
, iter
* 2),
2329 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2334 if (num_iterations
> 1) {
2335 num_components
= orig_num_components
- 2;
2339 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2340 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2341 indirect_offset
= new_indirect
;
2348 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2350 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2351 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2354 /* The only constant offset we should find is 0. brw_nir.c's
2355 * add_const_offset_to_base() will fold other constant offsets
2356 * into instr->const_index[0].
2358 assert(const_value
->u32
[0] == 0);
2362 return get_nir_src(*offset_src
);
2366 do_untyped_vector_read(const fs_builder
&bld
,
2368 const fs_reg surf_index
,
2369 const fs_reg offset_reg
,
2370 unsigned num_components
)
2372 if (type_sz(dest
.type
) <= 2) {
2373 assert(dest
.stride
== 1);
2374 boolean is_const_offset
= offset_reg
.file
== BRW_IMMEDIATE_VALUE
;
2376 if (is_const_offset
) {
2377 uint32_t start
= offset_reg
.ud
& ~3;
2378 uint32_t end
= offset_reg
.ud
+ num_components
* type_sz(dest
.type
);
2379 end
= ALIGN(end
, 4);
2380 assert (end
- start
<= 16);
2382 /* At this point we have 16-bit component/s that have constant
2383 * offset aligned to 4-bytes that can be read with untyped_reads.
2384 * untyped_read message requires 32-bit aligned offsets.
2386 unsigned first_component
= (offset_reg
.ud
& 3) / type_sz(dest
.type
);
2387 unsigned num_components_32bit
= (end
- start
) / 4;
2389 fs_reg read_result
=
2390 emit_untyped_read(bld
, surf_index
, brw_imm_ud(start
),
2392 num_components_32bit
,
2393 BRW_PREDICATE_NONE
);
2394 shuffle_from_32bit_read(bld
, dest
, read_result
, first_component
,
2397 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2398 for (unsigned i
= 0; i
< num_components
; i
++) {
2400 bld
.MOV(read_offset
, offset_reg
);
2402 bld
.ADD(read_offset
, offset_reg
,
2403 brw_imm_ud(i
* type_sz(dest
.type
)));
2405 /* Non constant offsets are not guaranteed to be aligned 32-bits
2406 * so they are read using one byte_scattered_read message
2407 * for each component.
2409 fs_reg read_result
=
2410 emit_byte_scattered_read(bld
, surf_index
, read_offset
,
2412 type_sz(dest
.type
) * 8 /* bit_size */,
2413 BRW_PREDICATE_NONE
);
2414 bld
.MOV(offset(dest
, bld
, i
),
2415 subscript (read_result
, dest
.type
, 0));
2418 } else if (type_sz(dest
.type
) == 4) {
2419 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2422 BRW_PREDICATE_NONE
);
2423 read_result
.type
= dest
.type
;
2424 for (unsigned i
= 0; i
< num_components
; i
++)
2425 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2426 } else if (type_sz(dest
.type
) == 8) {
2427 /* Reading a dvec, so we need to:
2429 * 1. Multiply num_components by 2, to account for the fact that we
2430 * need to read 64-bit components.
2431 * 2. Shuffle the result of the load to form valid 64-bit elements
2432 * 3. Emit a second load (for components z/w) if needed.
2434 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2435 bld
.MOV(read_offset
, offset_reg
);
2437 int iters
= num_components
<= 2 ? 1 : 2;
2439 /* Load the dvec, the first iteration loads components x/y, the second
2440 * iteration, if needed, loads components z/w
2442 for (int it
= 0; it
< iters
; it
++) {
2443 /* Compute number of components to read in this iteration */
2444 int iter_components
= MIN2(2, num_components
);
2445 num_components
-= iter_components
;
2447 /* Read. Since this message reads 32-bit components, we need to
2448 * read twice as many components.
2450 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2452 iter_components
* 2,
2453 BRW_PREDICATE_NONE
);
2455 /* Shuffle the 32-bit load result into valid 64-bit data */
2456 shuffle_from_32bit_read(bld
, offset(dest
, bld
, it
* 2),
2457 read_result
, 0, iter_components
);
2459 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2462 unreachable("Unsupported type");
2467 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2468 nir_intrinsic_instr
*instr
)
2470 assert(stage
== MESA_SHADER_VERTEX
);
2473 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2474 dest
= get_nir_dest(instr
->dest
);
2476 switch (instr
->intrinsic
) {
2477 case nir_intrinsic_load_vertex_id
:
2478 case nir_intrinsic_load_base_vertex
:
2479 unreachable("should be lowered by nir_lower_system_values()");
2481 case nir_intrinsic_load_vertex_id_zero_base
:
2482 case nir_intrinsic_load_instance_id
:
2483 case nir_intrinsic_load_base_instance
:
2484 case nir_intrinsic_load_draw_id
: {
2485 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2486 fs_reg val
= nir_system_values
[sv
];
2487 assert(val
.file
!= BAD_FILE
);
2488 dest
.type
= val
.type
;
2493 case nir_intrinsic_load_input
: {
2494 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2495 unsigned first_component
= nir_intrinsic_component(instr
);
2496 unsigned num_components
= instr
->num_components
;
2498 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2499 assert(const_offset
&& "Indirect input loads not allowed");
2500 src
= offset(src
, bld
, const_offset
->u32
[0]);
2502 if (type_sz(dest
.type
) == 8)
2503 first_component
/= 2;
2505 /* For 16-bit support maybe a temporary will be needed to copy from
2508 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2509 first_component
, num_components
);
2513 case nir_intrinsic_load_first_vertex
:
2514 case nir_intrinsic_load_is_indexed_draw
:
2515 unreachable("lowered by brw_nir_lower_vs_inputs");
2518 nir_emit_intrinsic(bld
, instr
);
2524 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2525 nir_intrinsic_instr
*instr
)
2527 assert(stage
== MESA_SHADER_TESS_CTRL
);
2528 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2529 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2532 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2533 dst
= get_nir_dest(instr
->dest
);
2535 switch (instr
->intrinsic
) {
2536 case nir_intrinsic_load_primitive_id
:
2537 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2539 case nir_intrinsic_load_invocation_id
:
2540 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2542 case nir_intrinsic_load_patch_vertices_in
:
2543 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2544 brw_imm_d(tcs_key
->input_vertices
));
2547 case nir_intrinsic_barrier
: {
2548 if (tcs_prog_data
->instances
== 1)
2551 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2552 fs_reg m0_2
= component(m0
, 2);
2554 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2556 /* Zero the message header */
2557 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2559 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2560 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2561 brw_imm_ud(INTEL_MASK(16, 13)));
2563 /* Shift it up to bits 27:24. */
2564 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2566 /* Set the Barrier Count and the enable bit */
2567 chanbld
.OR(m0_2
, m0_2
,
2568 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2570 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2574 case nir_intrinsic_load_input
:
2575 unreachable("nir_lower_io should never give us these.");
2578 case nir_intrinsic_load_per_vertex_input
: {
2579 fs_reg indirect_offset
= get_indirect_offset(instr
);
2580 unsigned imm_offset
= instr
->const_index
[0];
2582 const nir_src
&vertex_src
= instr
->src
[0];
2583 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2590 /* Emit a MOV to resolve <0,1,0> regioning. */
2591 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2593 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2594 vertex_const
->i32
[0] & 7),
2595 BRW_REGISTER_TYPE_UD
));
2596 } else if (tcs_prog_data
->instances
== 1 &&
2597 vertex_src
.is_ssa
&&
2598 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2599 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2600 /* For the common case of only 1 instance, an array index of
2601 * gl_InvocationID means reading g1. Skip all the indirect work.
2603 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2605 /* The vertex index is non-constant. We need to use indirect
2606 * addressing to fetch the proper URB handle.
2608 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2610 /* Each ICP handle is a single DWord (4 bytes) */
2611 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2612 bld
.SHL(vertex_offset_bytes
,
2613 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2616 /* Start at g1. We might read up to 4 registers. */
2617 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2618 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2619 brw_imm_ud(4 * REG_SIZE
));
2622 /* We can only read two double components with each URB read, so
2623 * we send two read messages in that case, each one loading up to
2624 * two double components.
2626 unsigned num_iterations
= 1;
2627 unsigned num_components
= instr
->num_components
;
2628 unsigned first_component
= nir_intrinsic_component(instr
);
2629 fs_reg orig_dst
= dst
;
2630 if (type_sz(dst
.type
) == 8) {
2631 first_component
= first_component
/ 2;
2632 if (instr
->num_components
> 2) {
2637 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2641 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2642 if (indirect_offset
.file
== BAD_FILE
) {
2643 /* Constant indexing - use global offset. */
2644 if (first_component
!= 0) {
2645 unsigned read_components
= num_components
+ first_component
;
2646 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2647 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2648 for (unsigned i
= 0; i
< num_components
; i
++) {
2649 bld
.MOV(offset(dst
, bld
, i
),
2650 offset(tmp
, bld
, i
+ first_component
));
2653 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2655 inst
->offset
= imm_offset
;
2658 /* Indirect indexing - use per-slot offsets as well. */
2659 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2660 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2661 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2662 if (first_component
!= 0) {
2663 unsigned read_components
= num_components
+ first_component
;
2664 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2665 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2667 for (unsigned i
= 0; i
< num_components
; i
++) {
2668 bld
.MOV(offset(dst
, bld
, i
),
2669 offset(tmp
, bld
, i
+ first_component
));
2672 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2675 inst
->offset
= imm_offset
;
2678 inst
->size_written
= (num_components
+ first_component
) *
2679 inst
->dst
.component_size(inst
->exec_size
);
2681 /* If we are reading 64-bit data using 32-bit read messages we need
2682 * build proper 64-bit data elements by shuffling the low and high
2683 * 32-bit components around like we do for other things like UBOs
2686 if (type_sz(dst
.type
) == 8) {
2687 shuffle_from_32bit_read(bld
,
2688 offset(orig_dst
, bld
, iter
* 2),
2689 retype(dst
, BRW_REGISTER_TYPE_D
),
2693 /* Copy the temporary to the destination to deal with writemasking.
2695 * Also attempt to deal with gl_PointSize being in the .w component.
2697 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2698 assert(type_sz(dst
.type
) < 8);
2699 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2700 inst
->size_written
= 4 * REG_SIZE
;
2701 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2704 /* If we are loading double data and we need a second read message
2705 * adjust the write offset
2707 if (num_iterations
> 1) {
2708 num_components
= instr
->num_components
- 2;
2715 case nir_intrinsic_load_output
:
2716 case nir_intrinsic_load_per_vertex_output
: {
2717 fs_reg indirect_offset
= get_indirect_offset(instr
);
2718 unsigned imm_offset
= instr
->const_index
[0];
2719 unsigned first_component
= nir_intrinsic_component(instr
);
2722 if (indirect_offset
.file
== BAD_FILE
) {
2723 /* Replicate the patch handle to all enabled channels */
2724 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2725 bld
.MOV(patch_handle
,
2726 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2729 if (first_component
!= 0) {
2730 unsigned read_components
=
2731 instr
->num_components
+ first_component
;
2732 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2733 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2735 inst
->size_written
= read_components
* REG_SIZE
;
2736 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2737 bld
.MOV(offset(dst
, bld
, i
),
2738 offset(tmp
, bld
, i
+ first_component
));
2741 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2743 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2745 inst
->offset
= imm_offset
;
2749 /* Indirect indexing - use per-slot offsets as well. */
2750 const fs_reg srcs
[] = {
2751 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2754 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2755 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2756 if (first_component
!= 0) {
2757 unsigned read_components
=
2758 instr
->num_components
+ first_component
;
2759 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2760 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2762 inst
->size_written
= read_components
* REG_SIZE
;
2763 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2764 bld
.MOV(offset(dst
, bld
, i
),
2765 offset(tmp
, bld
, i
+ first_component
));
2768 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2770 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2772 inst
->offset
= imm_offset
;
2778 case nir_intrinsic_store_output
:
2779 case nir_intrinsic_store_per_vertex_output
: {
2780 fs_reg value
= get_nir_src(instr
->src
[0]);
2781 bool is_64bit
= (instr
->src
[0].is_ssa
?
2782 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2783 fs_reg indirect_offset
= get_indirect_offset(instr
);
2784 unsigned imm_offset
= instr
->const_index
[0];
2785 unsigned mask
= instr
->const_index
[1];
2786 unsigned header_regs
= 0;
2788 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2790 if (indirect_offset
.file
!= BAD_FILE
) {
2791 srcs
[header_regs
++] = indirect_offset
;
2797 unsigned num_components
= util_last_bit(mask
);
2800 /* We can only pack two 64-bit components in a single message, so send
2801 * 2 messages if we have more components
2803 unsigned num_iterations
= 1;
2804 unsigned iter_components
= num_components
;
2805 unsigned first_component
= nir_intrinsic_component(instr
);
2807 first_component
= first_component
/ 2;
2808 if (instr
->num_components
> 2) {
2810 iter_components
= 2;
2814 mask
= mask
<< first_component
;
2816 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2817 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2818 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2819 opcode
= indirect_offset
.file
!= BAD_FILE
?
2820 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2821 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2822 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2823 /* Expand the 64-bit mask to 32-bit channels. We only handle
2824 * two channels in each iteration, so we only care about X/Y.
2826 unsigned mask32
= 0;
2827 if (mask
& WRITEMASK_X
)
2828 mask32
|= WRITEMASK_XY
;
2829 if (mask
& WRITEMASK_Y
)
2830 mask32
|= WRITEMASK_ZW
;
2832 /* If the mask does not include any of the channels X or Y there
2833 * is nothing to do in this iteration. Move on to the next couple
2834 * of 64-bit channels.
2842 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2843 opcode
= indirect_offset
.file
!= BAD_FILE
?
2844 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2845 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2847 opcode
= indirect_offset
.file
!= BAD_FILE
?
2848 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2849 SHADER_OPCODE_URB_WRITE_SIMD8
;
2852 for (unsigned i
= 0; i
< iter_components
; i
++) {
2853 if (!(mask
& (1 << (i
+ first_component
))))
2857 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2859 /* We need to shuffle the 64-bit data to match the layout
2860 * expected by our 32-bit URB write messages. We use a temporary
2863 unsigned channel
= iter
* 2 + i
;
2864 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2866 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2867 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2868 offset(dest
, bld
, 1);
2873 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2874 (is_64bit
? 2 * first_component
: first_component
);
2876 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2877 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2879 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2880 inst
->offset
= imm_offset
;
2883 /* If this is a 64-bit attribute, select the next two 64-bit channels
2884 * to be handled in the next iteration.
2895 nir_emit_intrinsic(bld
, instr
);
2901 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2902 nir_intrinsic_instr
*instr
)
2904 assert(stage
== MESA_SHADER_TESS_EVAL
);
2905 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2908 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2909 dest
= get_nir_dest(instr
->dest
);
2911 switch (instr
->intrinsic
) {
2912 case nir_intrinsic_load_primitive_id
:
2913 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2915 case nir_intrinsic_load_tess_coord
:
2916 /* gl_TessCoord is part of the payload in g1-3 */
2917 for (unsigned i
= 0; i
< 3; i
++) {
2918 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2922 case nir_intrinsic_load_input
:
2923 case nir_intrinsic_load_per_vertex_input
: {
2924 fs_reg indirect_offset
= get_indirect_offset(instr
);
2925 unsigned imm_offset
= instr
->const_index
[0];
2926 unsigned first_component
= nir_intrinsic_component(instr
);
2928 if (type_sz(dest
.type
) == 8) {
2929 first_component
= first_component
/ 2;
2933 if (indirect_offset
.file
== BAD_FILE
) {
2934 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2935 * which is 16 registers (since each holds 2 vec4 slots).
2937 unsigned slot_count
= 1;
2938 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2941 const unsigned max_push_slots
= 32;
2942 if (imm_offset
+ slot_count
<= max_push_slots
) {
2943 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2944 for (int i
= 0; i
< instr
->num_components
; i
++) {
2945 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2946 i
+ first_component
;
2947 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2950 tes_prog_data
->base
.urb_read_length
=
2951 MAX2(tes_prog_data
->base
.urb_read_length
,
2952 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2954 /* Replicate the patch handle to all enabled channels */
2955 const fs_reg srcs
[] = {
2956 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2958 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2959 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2961 if (first_component
!= 0) {
2962 unsigned read_components
=
2963 instr
->num_components
+ first_component
;
2964 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2965 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2967 inst
->size_written
= read_components
* REG_SIZE
;
2968 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2969 bld
.MOV(offset(dest
, bld
, i
),
2970 offset(tmp
, bld
, i
+ first_component
));
2973 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2975 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2978 inst
->offset
= imm_offset
;
2981 /* Indirect indexing - use per-slot offsets as well. */
2983 /* We can only read two double components with each URB read, so
2984 * we send two read messages in that case, each one loading up to
2985 * two double components.
2987 unsigned num_iterations
= 1;
2988 unsigned num_components
= instr
->num_components
;
2989 fs_reg orig_dest
= dest
;
2990 if (type_sz(dest
.type
) == 8) {
2991 if (instr
->num_components
> 2) {
2995 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2999 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3000 const fs_reg srcs
[] = {
3001 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3004 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3005 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3007 if (first_component
!= 0) {
3008 unsigned read_components
=
3009 num_components
+ first_component
;
3010 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3011 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3013 for (unsigned i
= 0; i
< num_components
; i
++) {
3014 bld
.MOV(offset(dest
, bld
, i
),
3015 offset(tmp
, bld
, i
+ first_component
));
3018 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3022 inst
->offset
= imm_offset
;
3023 inst
->size_written
= (num_components
+ first_component
) *
3024 inst
->dst
.component_size(inst
->exec_size
);
3026 /* If we are reading 64-bit data using 32-bit read messages we need
3027 * build proper 64-bit data elements by shuffling the low and high
3028 * 32-bit components around like we do for other things like UBOs
3031 if (type_sz(dest
.type
) == 8) {
3032 shuffle_from_32bit_read(bld
,
3033 offset(orig_dest
, bld
, iter
* 2),
3034 retype(dest
, BRW_REGISTER_TYPE_D
),
3038 /* If we are loading double data and we need a second read message
3041 if (num_iterations
> 1) {
3042 num_components
= instr
->num_components
- 2;
3050 nir_emit_intrinsic(bld
, instr
);
3056 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3057 nir_intrinsic_instr
*instr
)
3059 assert(stage
== MESA_SHADER_GEOMETRY
);
3060 fs_reg indirect_offset
;
3063 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3064 dest
= get_nir_dest(instr
->dest
);
3066 switch (instr
->intrinsic
) {
3067 case nir_intrinsic_load_primitive_id
:
3068 assert(stage
== MESA_SHADER_GEOMETRY
);
3069 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3070 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3071 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3074 case nir_intrinsic_load_input
:
3075 unreachable("load_input intrinsics are invalid for the GS stage");
3077 case nir_intrinsic_load_per_vertex_input
:
3078 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3079 instr
->src
[1], instr
->num_components
,
3080 nir_intrinsic_component(instr
));
3083 case nir_intrinsic_emit_vertex_with_counter
:
3084 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3087 case nir_intrinsic_end_primitive_with_counter
:
3088 emit_gs_end_primitive(instr
->src
[0]);
3091 case nir_intrinsic_set_vertex_count
:
3092 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3095 case nir_intrinsic_load_invocation_id
: {
3096 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3097 assert(val
.file
!= BAD_FILE
);
3098 dest
.type
= val
.type
;
3104 nir_emit_intrinsic(bld
, instr
);
3110 * Fetch the current render target layer index.
3113 fetch_render_target_array_index(const fs_builder
&bld
)
3115 if (bld
.shader
->devinfo
->gen
>= 6) {
3116 /* The render target array index is provided in the thread payload as
3117 * bits 26:16 of r0.0.
3119 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3120 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3124 /* Pre-SNB we only ever render into the first layer of the framebuffer
3125 * since layered rendering is not implemented.
3127 return brw_imm_ud(0);
3132 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3133 * framebuffer at the current fragment coordinates and sample index.
3136 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3139 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3141 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3142 const brw_wm_prog_key
*wm_key
=
3143 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3144 assert(!wm_key
->coherent_fb_fetch
);
3145 const struct brw_wm_prog_data
*wm_prog_data
=
3146 brw_wm_prog_data(stage_prog_data
);
3148 /* Calculate the surface index relative to the start of the texture binding
3149 * table block, since that's what the texturing messages expect.
3151 const unsigned surface
= target
+
3152 wm_prog_data
->binding_table
.render_target_read_start
-
3153 wm_prog_data
->base
.binding_table
.texture_start
;
3155 brw_mark_surface_used(
3156 bld
.shader
->stage_prog_data
,
3157 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3159 /* Calculate the fragment coordinates. */
3160 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3161 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3162 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3163 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3165 /* Calculate the sample index and MCS payload when multisampling. Luckily
3166 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3167 * shouldn't be necessary to recompile based on whether the framebuffer is
3170 if (wm_key
->multisample_fbo
&&
3171 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3172 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3174 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3175 const fs_reg mcs
= wm_key
->multisample_fbo
?
3176 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3178 /* Use either a normal or a CMS texel fetch message depending on whether
3179 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3180 * message just in case the framebuffer uses 16x multisampling, it should
3181 * be equivalent to the normal CMS fetch for lower multisampling modes.
3183 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3184 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3185 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3187 /* Emit the instruction. */
3188 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3190 brw_imm_ud(surface
), brw_imm_ud(0),
3191 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3192 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3194 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3195 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3201 * Actual coherent framebuffer read implemented using the native render target
3202 * read message. Requires SKL+.
3205 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3207 assert(bld
.shader
->devinfo
->gen
>= 9);
3208 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3209 inst
->target
= target
;
3210 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3216 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3218 if (n
&& regs
[0].file
!= BAD_FILE
) {
3222 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3224 for (unsigned i
= 0; i
< n
; i
++)
3232 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3234 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3235 const brw_wm_prog_key
*const key
=
3236 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3237 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3238 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3240 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3241 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3243 else if (l
== FRAG_RESULT_COLOR
)
3244 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3245 MAX2(key
->nr_color_regions
, 1));
3247 else if (l
== FRAG_RESULT_DEPTH
)
3248 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3250 else if (l
== FRAG_RESULT_STENCIL
)
3251 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3253 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3254 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3256 else if (l
>= FRAG_RESULT_DATA0
&&
3257 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3258 return alloc_temporary(v
->bld
, 4,
3259 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3262 unreachable("Invalid location");
3266 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3267 nir_intrinsic_instr
*instr
)
3269 assert(stage
== MESA_SHADER_FRAGMENT
);
3272 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3273 dest
= get_nir_dest(instr
->dest
);
3275 switch (instr
->intrinsic
) {
3276 case nir_intrinsic_load_front_face
:
3277 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3278 *emit_frontfacing_interpolation());
3281 case nir_intrinsic_load_sample_pos
: {
3282 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3283 assert(sample_pos
.file
!= BAD_FILE
);
3284 dest
.type
= sample_pos
.type
;
3285 bld
.MOV(dest
, sample_pos
);
3286 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3290 case nir_intrinsic_load_layer_id
:
3291 dest
.type
= BRW_REGISTER_TYPE_UD
;
3292 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3295 case nir_intrinsic_load_helper_invocation
:
3296 case nir_intrinsic_load_sample_mask_in
:
3297 case nir_intrinsic_load_sample_id
: {
3298 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3299 fs_reg val
= nir_system_values
[sv
];
3300 assert(val
.file
!= BAD_FILE
);
3301 dest
.type
= val
.type
;
3306 case nir_intrinsic_store_output
: {
3307 const fs_reg src
= get_nir_src(instr
->src
[0]);
3308 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3309 assert(const_offset
&& "Indirect output stores not allowed");
3310 const unsigned location
= nir_intrinsic_base(instr
) +
3311 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3312 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3315 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3316 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3317 offset(src
, bld
, j
));
3322 case nir_intrinsic_load_output
: {
3323 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3324 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3325 assert(l
>= FRAG_RESULT_DATA0
);
3326 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3327 assert(const_offset
&& "Indirect output loads not allowed");
3328 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3329 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3331 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3332 emit_coherent_fb_read(bld
, tmp
, target
);
3334 emit_non_coherent_fb_read(bld
, tmp
, target
);
3336 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3337 bld
.MOV(offset(dest
, bld
, j
),
3338 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3344 case nir_intrinsic_discard
:
3345 case nir_intrinsic_discard_if
: {
3346 /* We track our discarded pixels in f0.1. By predicating on it, we can
3347 * update just the flag bits that aren't yet discarded. If there's no
3348 * condition, we emit a CMP of g0 != g0, so all currently executing
3349 * channels will get turned off.
3352 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3353 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3354 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3356 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3357 BRW_REGISTER_TYPE_UW
));
3358 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3360 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3361 cmp
->flag_subreg
= 1;
3363 if (devinfo
->gen
>= 6) {
3364 emit_discard_jump();
3367 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3371 case nir_intrinsic_load_input
: {
3372 /* load_input is only used for flat inputs */
3373 unsigned base
= nir_intrinsic_base(instr
);
3374 unsigned comp
= nir_intrinsic_component(instr
);
3375 unsigned num_components
= instr
->num_components
;
3376 fs_reg orig_dest
= dest
;
3377 enum brw_reg_type type
= dest
.type
;
3379 /* Special case fields in the VUE header */
3380 if (base
== VARYING_SLOT_LAYER
)
3382 else if (base
== VARYING_SLOT_VIEWPORT
)
3385 if (nir_dest_bit_size(instr
->dest
) == 64) {
3386 /* const_index is in 32-bit type size units that could not be aligned
3387 * with DF. We need to read the double vector as if it was a float
3388 * vector of twice the number of components to fetch the right data.
3390 type
= BRW_REGISTER_TYPE_F
;
3391 num_components
*= 2;
3392 dest
= bld
.vgrf(type
, num_components
);
3395 for (unsigned int i
= 0; i
< num_components
; i
++) {
3396 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3397 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3400 if (nir_dest_bit_size(instr
->dest
) == 64) {
3401 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3402 instr
->num_components
);
3407 case nir_intrinsic_load_barycentric_pixel
:
3408 case nir_intrinsic_load_barycentric_centroid
:
3409 case nir_intrinsic_load_barycentric_sample
:
3410 /* Do nothing - load_interpolated_input handling will handle it later. */
3413 case nir_intrinsic_load_barycentric_at_sample
: {
3414 const glsl_interp_mode interpolation
=
3415 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3417 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3420 unsigned msg_data
= const_sample
->i32
[0] << 4;
3422 emit_pixel_interpolater_send(bld
,
3423 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3426 brw_imm_ud(msg_data
),
3429 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3430 BRW_REGISTER_TYPE_UD
);
3432 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3433 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3434 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3435 bld
.exec_all().group(1, 0)
3436 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3437 emit_pixel_interpolater_send(bld
,
3438 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3444 /* Make a loop that sends a message to the pixel interpolater
3445 * for the sample number in each live channel. If there are
3446 * multiple channels with the same sample number then these
3447 * will be handled simultaneously with a single interation of
3450 bld
.emit(BRW_OPCODE_DO
);
3452 /* Get the next live sample number into sample_id_reg */
3453 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3455 /* Set the flag register so that we can perform the send
3456 * message on all channels that have the same sample number
3458 bld
.CMP(bld
.null_reg_ud(),
3459 sample_src
, sample_id
,
3460 BRW_CONDITIONAL_EQ
);
3461 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3462 bld
.exec_all().group(1, 0)
3463 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3465 emit_pixel_interpolater_send(bld
,
3466 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3469 component(msg_data
, 0),
3471 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3473 /* Continue the loop if there are any live channels left */
3474 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3476 bld
.emit(BRW_OPCODE_WHILE
));
3482 case nir_intrinsic_load_barycentric_at_offset
: {
3483 const glsl_interp_mode interpolation
=
3484 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3486 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3489 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3490 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3492 emit_pixel_interpolater_send(bld
,
3493 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3496 brw_imm_ud(off_x
| (off_y
<< 4)),
3499 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3500 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3501 BRW_REGISTER_TYPE_F
);
3502 for (int i
= 0; i
< 2; i
++) {
3503 fs_reg temp
= vgrf(glsl_type::float_type
);
3504 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3505 fs_reg itemp
= vgrf(glsl_type::int_type
);
3507 bld
.MOV(itemp
, temp
);
3509 /* Clamp the upper end of the range to +7/16.
3510 * ARB_gpu_shader5 requires that we support a maximum offset
3511 * of +0.5, which isn't representable in a S0.4 value -- if
3512 * we didn't clamp it, we'd end up with -8/16, which is the
3513 * opposite of what the shader author wanted.
3515 * This is legal due to ARB_gpu_shader5's quantization
3518 * "Not all values of <offset> may be supported; x and y
3519 * offsets may be rounded to fixed-point values with the
3520 * number of fraction bits given by the
3521 * implementation-dependent constant
3522 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3524 set_condmod(BRW_CONDITIONAL_L
,
3525 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3528 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3529 emit_pixel_interpolater_send(bld
,
3539 case nir_intrinsic_load_interpolated_input
: {
3540 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3541 emit_fragcoord_interpolation(dest
);
3545 assert(instr
->src
[0].ssa
&&
3546 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3547 nir_intrinsic_instr
*bary_intrinsic
=
3548 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3549 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3550 enum glsl_interp_mode interp_mode
=
3551 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3554 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3555 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3556 /* Use the result of the PI message */
3557 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3559 /* Use the delta_xy values computed from the payload */
3560 enum brw_barycentric_mode bary
=
3561 brw_barycentric_mode(interp_mode
, bary_intrin
);
3563 dst_xy
= this->delta_xy
[bary
];
3566 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3568 component(interp_reg(nir_intrinsic_base(instr
),
3569 nir_intrinsic_component(instr
) + i
), 0);
3570 interp
.type
= BRW_REGISTER_TYPE_F
;
3571 dest
.type
= BRW_REGISTER_TYPE_F
;
3573 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3574 fs_reg tmp
= vgrf(glsl_type::float_type
);
3575 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3576 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3578 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3585 nir_emit_intrinsic(bld
, instr
);
3591 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3592 nir_intrinsic_instr
*instr
)
3594 assert(stage
== MESA_SHADER_COMPUTE
);
3595 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3598 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3599 dest
= get_nir_dest(instr
->dest
);
3601 switch (instr
->intrinsic
) {
3602 case nir_intrinsic_barrier
:
3604 cs_prog_data
->uses_barrier
= true;
3607 case nir_intrinsic_load_subgroup_id
:
3608 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3611 case nir_intrinsic_load_local_invocation_id
:
3612 case nir_intrinsic_load_work_group_id
: {
3613 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3614 fs_reg val
= nir_system_values
[sv
];
3615 assert(val
.file
!= BAD_FILE
);
3616 dest
.type
= val
.type
;
3617 for (unsigned i
= 0; i
< 3; i
++)
3618 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3622 case nir_intrinsic_load_num_work_groups
: {
3623 const unsigned surface
=
3624 cs_prog_data
->binding_table
.work_groups_start
;
3626 cs_prog_data
->uses_num_work_groups
= true;
3628 fs_reg surf_index
= brw_imm_ud(surface
);
3629 brw_mark_surface_used(prog_data
, surface
);
3631 /* Read the 3 GLuint components of gl_NumWorkGroups */
3632 for (unsigned i
= 0; i
< 3; i
++) {
3633 fs_reg read_result
=
3634 emit_untyped_read(bld
, surf_index
,
3636 1 /* dims */, 1 /* size */,
3637 BRW_PREDICATE_NONE
);
3638 read_result
.type
= dest
.type
;
3639 bld
.MOV(dest
, read_result
);
3640 dest
= offset(dest
, bld
, 1);
3645 case nir_intrinsic_shared_atomic_add
:
3646 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3648 case nir_intrinsic_shared_atomic_imin
:
3649 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3651 case nir_intrinsic_shared_atomic_umin
:
3652 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3654 case nir_intrinsic_shared_atomic_imax
:
3655 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3657 case nir_intrinsic_shared_atomic_umax
:
3658 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3660 case nir_intrinsic_shared_atomic_and
:
3661 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3663 case nir_intrinsic_shared_atomic_or
:
3664 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3666 case nir_intrinsic_shared_atomic_xor
:
3667 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3669 case nir_intrinsic_shared_atomic_exchange
:
3670 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3672 case nir_intrinsic_shared_atomic_comp_swap
:
3673 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3676 case nir_intrinsic_load_shared
: {
3677 assert(devinfo
->gen
>= 7);
3679 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3681 /* Get the offset to read from */
3683 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3685 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3687 offset_reg
= vgrf(glsl_type::uint_type
);
3689 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3690 brw_imm_ud(instr
->const_index
[0]));
3693 /* Read the vector */
3694 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3695 instr
->num_components
);
3699 case nir_intrinsic_store_shared
: {
3700 assert(devinfo
->gen
>= 7);
3703 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3706 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3709 unsigned writemask
= instr
->const_index
[1];
3711 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3712 * since the untyped writes below operate in units of 32-bits, which
3713 * means that we need to write twice as many components each time.
3714 * Also, we have to suffle 64-bit data to be in the appropriate layout
3715 * expected by our 32-bit write messages.
3717 unsigned type_size
= 4;
3718 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3720 val_reg
= shuffle_for_32bit_write(bld
, val_reg
, 0,
3721 instr
->num_components
);
3724 unsigned type_slots
= type_size
/ 4;
3726 /* Combine groups of consecutive enabled channels in one write
3727 * message. We use ffs to find the first enabled channel and then ffs on
3728 * the bit-inverse, down-shifted writemask to determine the length of
3729 * the block of enabled bits.
3732 unsigned first_component
= ffs(writemask
) - 1;
3733 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3735 /* We can't write more than 2 64-bit components at once. Limit the
3736 * length of the write to what we can do and let the next iteration
3740 length
= MIN2(2, length
);
3743 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3745 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3746 type_size
* first_component
);
3748 offset_reg
= vgrf(glsl_type::uint_type
);
3750 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3751 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3754 emit_untyped_write(bld
, surf_index
, offset_reg
,
3755 offset(val_reg
, bld
, first_component
* type_slots
),
3756 1 /* dims */, length
* type_slots
,
3757 BRW_PREDICATE_NONE
);
3759 /* Clear the bits in the writemask that we just wrote, then try
3760 * again to see if more channels are left.
3762 writemask
&= (15 << (first_component
+ length
));
3769 nir_emit_intrinsic(bld
, instr
);
3775 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3776 nir_op op
, brw_reg_type type
)
3778 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3779 switch (type_sz(type
)) {
3781 assert(type
!= BRW_REGISTER_TYPE_HF
);
3782 return retype(brw_imm_uw(value
.u16
[0]), type
);
3784 return retype(brw_imm_ud(value
.u32
[0]), type
);
3786 if (type
== BRW_REGISTER_TYPE_DF
)
3787 return setup_imm_df(bld
, value
.f64
[0]);
3789 return retype(brw_imm_u64(value
.u64
[0]), type
);
3791 unreachable("Invalid type size");
3796 brw_op_for_nir_reduction_op(nir_op op
)
3799 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3800 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3801 case nir_op_imul
: return BRW_OPCODE_MUL
;
3802 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3803 case nir_op_imin
: return BRW_OPCODE_SEL
;
3804 case nir_op_umin
: return BRW_OPCODE_SEL
;
3805 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3806 case nir_op_imax
: return BRW_OPCODE_SEL
;
3807 case nir_op_umax
: return BRW_OPCODE_SEL
;
3808 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3809 case nir_op_iand
: return BRW_OPCODE_AND
;
3810 case nir_op_ior
: return BRW_OPCODE_OR
;
3811 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3813 unreachable("Invalid reduction operation");
3817 static brw_conditional_mod
3818 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3821 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3822 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3823 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3824 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3825 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3826 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3827 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3828 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3829 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3830 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3831 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3832 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3833 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3835 unreachable("Invalid reduction operation");
3840 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3843 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3844 dest
= get_nir_dest(instr
->dest
);
3846 switch (instr
->intrinsic
) {
3847 case nir_intrinsic_image_deref_load
:
3848 case nir_intrinsic_image_deref_store
:
3849 case nir_intrinsic_image_deref_atomic_add
:
3850 case nir_intrinsic_image_deref_atomic_min
:
3851 case nir_intrinsic_image_deref_atomic_max
:
3852 case nir_intrinsic_image_deref_atomic_and
:
3853 case nir_intrinsic_image_deref_atomic_or
:
3854 case nir_intrinsic_image_deref_atomic_xor
:
3855 case nir_intrinsic_image_deref_atomic_exchange
:
3856 case nir_intrinsic_image_deref_atomic_comp_swap
: {
3857 using namespace image_access
;
3859 if (stage
== MESA_SHADER_FRAGMENT
&&
3860 instr
->intrinsic
!= nir_intrinsic_image_deref_load
)
3861 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3863 /* Get the referenced image variable and type. */
3864 nir_deref_instr
*deref
= nir_src_as_deref(instr
->src
[0]);
3865 const nir_variable
*var
= nir_deref_instr_get_variable(deref
);
3866 const glsl_type
*type
= var
->type
->without_array();
3867 const brw_reg_type base_type
= get_image_base_type(type
);
3869 /* Get some metadata from the image intrinsic. */
3870 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3871 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3872 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3873 const unsigned format
= var
->data
.image
.format
;
3874 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3876 /* Get the arguments of the image intrinsic. */
3877 const fs_reg image
= get_nir_image_deref(deref
);
3878 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3879 BRW_REGISTER_TYPE_UD
);
3880 const fs_reg src0
= (info
->num_srcs
>= 4 ?
3881 retype(get_nir_src(instr
->src
[3]), base_type
) :
3883 const fs_reg src1
= (info
->num_srcs
>= 5 ?
3884 retype(get_nir_src(instr
->src
[4]), base_type
) :
3888 /* Emit an image load, store or atomic op. */
3889 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
)
3890 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3892 else if (instr
->intrinsic
== nir_intrinsic_image_deref_store
)
3893 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3894 var
->data
.image
.write_only
? GL_NONE
: format
);
3897 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3898 surf_dims
, arr_dims
, dest_components
,
3899 get_image_atomic_op(instr
->intrinsic
, type
));
3901 /* Assign the result. */
3902 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3903 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3904 offset(tmp
, bld
, c
));
3909 case nir_intrinsic_memory_barrier_atomic_counter
:
3910 case nir_intrinsic_memory_barrier_buffer
:
3911 case nir_intrinsic_memory_barrier_image
:
3912 case nir_intrinsic_memory_barrier
: {
3913 const fs_builder ubld
= bld
.group(8, 0);
3914 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3915 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3916 ->size_written
= 2 * REG_SIZE
;
3920 case nir_intrinsic_group_memory_barrier
:
3921 case nir_intrinsic_memory_barrier_shared
:
3922 /* We treat these workgroup-level barriers as no-ops. This should be
3923 * safe at present and as long as:
3925 * - Memory access instructions are not subsequently reordered by the
3926 * compiler back-end.
3928 * - All threads from a given compute shader workgroup fit within a
3929 * single subslice and therefore talk to the same HDC shared unit
3930 * what supposedly guarantees ordering and coherency between threads
3931 * from the same workgroup. This may change in the future when we
3932 * start splitting workgroups across multiple subslices.
3934 * - The context is not in fault-and-stream mode, which could cause
3935 * memory transactions (including to SLM) prior to the barrier to be
3936 * replayed after the barrier if a pagefault occurs. This shouldn't
3937 * be a problem up to and including SKL because fault-and-stream is
3938 * not usable due to hardware issues, but that's likely to change in
3943 case nir_intrinsic_shader_clock
: {
3944 /* We cannot do anything if there is an event, so ignore it for now */
3945 const fs_reg shader_clock
= get_timestamp(bld
);
3946 const fs_reg srcs
[] = { component(shader_clock
, 0),
3947 component(shader_clock
, 1) };
3948 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3952 case nir_intrinsic_image_deref_size
: {
3953 /* Get the referenced image variable and type. */
3954 nir_deref_instr
*deref
= nir_src_as_deref(instr
->src
[0]);
3955 const nir_variable
*var
= nir_deref_instr_get_variable(deref
);
3956 const glsl_type
*type
= var
->type
->without_array();
3958 /* Get the size of the image. */
3959 const fs_reg image
= get_nir_image_deref(deref
);
3960 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3962 /* For 1DArray image types, the array index is stored in the Z component.
3963 * Fix this by swizzling the Z component to the Y component.
3965 const bool is_1d_array_image
=
3966 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3967 type
->sampler_array
;
3969 /* For CubeArray images, we should count the number of cubes instead
3970 * of the number of faces. Fix it by dividing the (Z component) by 6.
3972 const bool is_cube_array_image
=
3973 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3974 type
->sampler_array
;
3976 /* Copy all the components. */
3977 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3978 if ((int)c
>= type
->coordinate_components()) {
3979 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3981 } else if (c
== 1 && is_1d_array_image
) {
3982 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3983 offset(size
, bld
, 2));
3984 } else if (c
== 2 && is_cube_array_image
) {
3985 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3986 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3987 offset(size
, bld
, c
), brw_imm_d(6));
3989 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3990 offset(size
, bld
, c
));
3997 case nir_intrinsic_image_deref_samples
:
3998 /* The driver does not support multi-sampled images. */
3999 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4002 case nir_intrinsic_load_uniform
: {
4003 /* Offsets are in bytes but they should always aligned to
4006 assert(instr
->const_index
[0] % 4 == 0 ||
4007 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4009 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4011 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4013 assert(const_offset
->u32
[0] % type_sz(dest
.type
) == 0);
4014 /* For 16-bit types we add the module of the const_index[0]
4015 * offset to access to not 32-bit aligned element
4017 src
.offset
= const_offset
->u32
[0] + instr
->const_index
[0] % 4;
4019 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4020 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4023 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4024 BRW_REGISTER_TYPE_UD
);
4026 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4027 * go past the end of the uniform. In order to keep the n'th
4028 * component from running past, we subtract off the size of all but
4029 * one component of the vector.
4031 assert(instr
->const_index
[1] >=
4032 instr
->num_components
* (int) type_sz(dest
.type
));
4033 unsigned read_size
= instr
->const_index
[1] -
4034 (instr
->num_components
- 1) * type_sz(dest
.type
);
4036 bool supports_64bit_indirects
=
4037 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4039 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4040 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4041 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4042 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4043 indirect
, brw_imm_ud(read_size
));
4046 const unsigned num_mov_indirects
=
4047 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4048 /* We read a little bit less per MOV INDIRECT, as they are now
4049 * 32-bits ones instead of 64-bit. Fix read_size then.
4051 const unsigned read_size_32bit
= read_size
-
4052 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4053 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4054 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4055 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4056 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4057 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4058 indirect
, brw_imm_ud(read_size_32bit
));
4066 case nir_intrinsic_load_ubo
: {
4067 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4071 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4072 const_index
->u32
[0];
4073 surf_index
= brw_imm_ud(index
);
4074 brw_mark_surface_used(prog_data
, index
);
4076 /* The block index is not a constant. Evaluate the index expression
4077 * per-channel and add the base UBO index; we have to select a value
4078 * from any live channel.
4080 surf_index
= vgrf(glsl_type::uint_type
);
4081 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4082 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4083 surf_index
= bld
.emit_uniformize(surf_index
);
4085 /* Assume this may touch any UBO. It would be nice to provide
4086 * a tighter bound, but the array information is already lowered away.
4088 brw_mark_surface_used(prog_data
,
4089 stage_prog_data
->binding_table
.ubo_start
+
4090 nir
->info
.num_ubos
- 1);
4093 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4094 if (const_offset
== NULL
) {
4095 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4096 BRW_REGISTER_TYPE_UD
);
4098 for (int i
= 0; i
< instr
->num_components
; i
++)
4099 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4100 base_offset
, i
* type_sz(dest
.type
));
4102 /* Even if we are loading doubles, a pull constant load will load
4103 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4104 * need to load a full dvec4 we will have to emit 2 loads. This is
4105 * similar to demote_pull_constants(), except that in that case we
4106 * see individual accesses to each component of the vector and then
4107 * we let CSE deal with duplicate loads. Here we see a vector access
4108 * and we have to split it if necessary.
4110 const unsigned type_size
= type_sz(dest
.type
);
4112 /* See if we've selected this as a push constant candidate */
4114 const unsigned ubo_block
= const_index
->u32
[0];
4115 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
4118 for (int i
= 0; i
< 4; i
++) {
4119 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4120 if (range
->block
== ubo_block
&&
4121 offset_256b
>= range
->start
&&
4122 offset_256b
< range
->start
+ range
->length
) {
4124 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4125 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
4130 if (push_reg
.file
!= BAD_FILE
) {
4131 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4132 bld
.MOV(offset(dest
, bld
, i
),
4133 byte_offset(push_reg
, i
* type_size
));
4139 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4140 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4141 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4143 for (unsigned c
= 0; c
< instr
->num_components
;) {
4144 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4145 /* Number of usable components in the next block-aligned load. */
4146 const unsigned count
= MIN2(instr
->num_components
- c
,
4147 (block_sz
- base
% block_sz
) / type_size
);
4149 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4150 packed_consts
, surf_index
,
4151 brw_imm_ud(base
& ~(block_sz
- 1)));
4153 const fs_reg consts
=
4154 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4157 for (unsigned d
= 0; d
< count
; d
++)
4158 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4166 case nir_intrinsic_load_ssbo
: {
4167 assert(devinfo
->gen
>= 7);
4169 nir_const_value
*const_uniform_block
=
4170 nir_src_as_const_value(instr
->src
[0]);
4173 if (const_uniform_block
) {
4174 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4175 const_uniform_block
->u32
[0];
4176 surf_index
= brw_imm_ud(index
);
4177 brw_mark_surface_used(prog_data
, index
);
4179 surf_index
= vgrf(glsl_type::uint_type
);
4180 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4181 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4183 /* Assume this may touch any UBO. It would be nice to provide
4184 * a tighter bound, but the array information is already lowered away.
4186 brw_mark_surface_used(prog_data
,
4187 stage_prog_data
->binding_table
.ssbo_start
+
4188 nir
->info
.num_ssbos
- 1);
4192 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4194 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4196 offset_reg
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
);
4199 /* Read the vector */
4200 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4201 instr
->num_components
);
4206 case nir_intrinsic_store_ssbo
: {
4207 assert(devinfo
->gen
>= 7);
4209 if (stage
== MESA_SHADER_FRAGMENT
)
4210 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4214 nir_const_value
*const_uniform_block
=
4215 nir_src_as_const_value(instr
->src
[1]);
4216 if (const_uniform_block
) {
4217 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4218 const_uniform_block
->u32
[0];
4219 surf_index
= brw_imm_ud(index
);
4220 brw_mark_surface_used(prog_data
, index
);
4222 surf_index
= vgrf(glsl_type::uint_type
);
4223 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4224 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4226 brw_mark_surface_used(prog_data
,
4227 stage_prog_data
->binding_table
.ssbo_start
+
4228 nir
->info
.num_ssbos
- 1);
4232 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4235 unsigned writemask
= instr
->const_index
[0];
4237 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4238 * since the untyped writes below operate in units of 32-bits, which
4239 * means that we need to write twice as many components each time.
4240 * Also, we have to suffle 64-bit data to be in the appropriate layout
4241 * expected by our 32-bit write messages.
4243 unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4244 unsigned type_size
= bit_size
/ 8;
4246 /* Combine groups of consecutive enabled channels in one write
4247 * message. We use ffs to find the first enabled channel and then ffs on
4248 * the bit-inverse, down-shifted writemask to determine the num_components
4249 * of the block of enabled bits.
4252 unsigned first_component
= ffs(writemask
) - 1;
4253 unsigned num_components
= ffs(~(writemask
>> first_component
)) - 1;
4254 fs_reg write_src
= offset(val_reg
, bld
, first_component
);
4256 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4258 if (type_size
> 4) {
4259 /* We can't write more than 2 64-bit components at once. Limit
4260 * the num_components of the write to what we can do and let the next
4261 * iteration handle the rest.
4263 num_components
= MIN2(2, num_components
);
4264 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4266 } else if (type_size
< 4) {
4267 assert(type_size
== 2);
4268 /* For 16-bit types we pack two consecutive values into a 32-bit
4269 * word and use an untyped write message. For single values or not
4270 * 32-bit-aligned we need to use byte-scattered writes because
4271 * untyped writes works with 32-bit components with 32-bit
4272 * alignment. byte_scattered_write messages only support one
4273 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4274 * could be enabled we can not guarantee that not constant offsets
4275 * to be 32-bit aligned for 16-bit types. For example an array, of
4276 * 16-bit vec3 with array element stride of 6.
4278 * In the case of 32-bit aligned constant offsets if there is
4279 * a 3-components vector we submit one untyped-write message
4280 * of 32-bit (first two components), and one byte-scattered
4281 * write message (the last component).
4284 if ( !const_offset
|| ((const_offset
->u32
[0] +
4285 type_size
* first_component
) % 4)) {
4286 /* If we use a .yz writemask we also need to emit 2
4287 * byte-scattered write messages because of y-component not
4288 * being aligned to 32-bit.
4291 } else if (num_components
> 2 && (num_components
% 2)) {
4292 /* If there is an odd number of consecutive components we left
4293 * the not paired component for a following emit of length == 1
4294 * with byte_scattered_write.
4298 /* For num_components == 1 we are also shuffling the component
4299 * because byte scattered writes of 16-bit need values to be dword
4300 * aligned. Shuffling only one component would be the same as
4303 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4310 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4311 type_size
* first_component
);
4313 offset_reg
= vgrf(glsl_type::uint_type
);
4315 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4316 brw_imm_ud(type_size
* first_component
));
4319 if (type_size
< 4 && num_components
== 1) {
4320 assert(type_size
== 2);
4321 /* Untyped Surface messages have a fixed 32-bit size, so we need
4322 * to rely on byte scattered in order to write 16-bit elements.
4323 * The byte_scattered_write message needs that every written 16-bit
4324 * type to be aligned 32-bits (stride=2).
4326 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4330 BRW_PREDICATE_NONE
);
4332 assert(num_components
* type_size
<= 16);
4333 assert((num_components
* type_size
) % 4 == 0);
4334 assert(offset_reg
.file
!= BRW_IMMEDIATE_VALUE
||
4335 offset_reg
.ud
% 4 == 0);
4336 unsigned num_slots
= (num_components
* type_size
) / 4;
4338 emit_untyped_write(bld
, surf_index
, offset_reg
,
4340 1 /* dims */, num_slots
,
4341 BRW_PREDICATE_NONE
);
4344 /* Clear the bits in the writemask that we just wrote, then try
4345 * again to see if more channels are left.
4347 writemask
&= (15 << (first_component
+ num_components
));
4352 case nir_intrinsic_store_output
: {
4353 fs_reg src
= get_nir_src(instr
->src
[0]);
4355 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4356 assert(const_offset
&& "Indirect output stores not allowed");
4358 unsigned num_components
= instr
->num_components
;
4359 unsigned first_component
= nir_intrinsic_component(instr
);
4360 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4361 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4362 num_components
*= 2;
4365 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4366 4 * const_offset
->u32
[0]), src
.type
);
4367 for (unsigned j
= 0; j
< num_components
; j
++) {
4368 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4369 offset(src
, bld
, j
));
4374 case nir_intrinsic_ssbo_atomic_add
:
4375 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4377 case nir_intrinsic_ssbo_atomic_imin
:
4378 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4380 case nir_intrinsic_ssbo_atomic_umin
:
4381 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4383 case nir_intrinsic_ssbo_atomic_imax
:
4384 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4386 case nir_intrinsic_ssbo_atomic_umax
:
4387 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4389 case nir_intrinsic_ssbo_atomic_and
:
4390 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4392 case nir_intrinsic_ssbo_atomic_or
:
4393 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4395 case nir_intrinsic_ssbo_atomic_xor
:
4396 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4398 case nir_intrinsic_ssbo_atomic_exchange
:
4399 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4401 case nir_intrinsic_ssbo_atomic_comp_swap
:
4402 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4405 case nir_intrinsic_get_buffer_size
: {
4406 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4407 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4409 /* A resinfo's sampler message is used to get the buffer size. The
4410 * SIMD8's writeback message consists of four registers and SIMD16's
4411 * writeback message consists of 8 destination registers (two per each
4412 * component). Because we are only interested on the first channel of
4413 * the first returned component, where resinfo returns the buffer size
4414 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4415 * the dispatch width.
4417 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4418 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4419 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4422 ubld
.MOV(src_payload
, brw_imm_d(0));
4424 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4425 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4426 src_payload
, brw_imm_ud(index
));
4427 inst
->header_size
= 0;
4429 inst
->size_written
= 4 * REG_SIZE
;
4431 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4433 * "Out-of-bounds checking is always performed at a DWord granularity. If
4434 * any part of the DWord is out-of-bounds then the whole DWord is
4435 * considered out-of-bounds."
4437 * This implies that types with size smaller than 4-bytes need to be
4438 * padded if they don't complete the last dword of the buffer. But as we
4439 * need to maintain the original size we need to reverse the padding
4440 * calculation to return the correct size to know the number of elements
4441 * of an unsized array. As we stored in the last two bits of the surface
4442 * size the needed padding for the buffer, we calculate here the
4443 * original buffer_size reversing the surface_size calculation:
4445 * surface_size = isl_align(buffer_size, 4) +
4446 * (isl_align(buffer_size) - buffer_size)
4448 * buffer_size = surface_size & ~3 - surface_size & 3
4451 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4452 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4453 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4455 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4456 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4457 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4459 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4461 brw_mark_surface_used(prog_data
, index
);
4465 case nir_intrinsic_load_subgroup_invocation
:
4466 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4467 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4470 case nir_intrinsic_load_subgroup_eq_mask
:
4471 case nir_intrinsic_load_subgroup_ge_mask
:
4472 case nir_intrinsic_load_subgroup_gt_mask
:
4473 case nir_intrinsic_load_subgroup_le_mask
:
4474 case nir_intrinsic_load_subgroup_lt_mask
:
4475 unreachable("not reached");
4477 case nir_intrinsic_vote_any
: {
4478 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4480 /* The any/all predicates do not consider channel enables. To prevent
4481 * dead channels from affecting the result, we initialize the flag with
4482 * with the identity value for the logical operation.
4484 if (dispatch_width
== 32) {
4485 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4486 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4489 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4491 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4493 /* For some reason, the any/all predicates don't work properly with
4494 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4495 * doesn't read the correct subset of the flag register and you end up
4496 * getting garbage in the second half. Work around this by using a pair
4497 * of 1-wide MOVs and scattering the result.
4499 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4500 ubld
.MOV(res1
, brw_imm_d(0));
4501 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4502 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4503 BRW_PREDICATE_ALIGN1_ANY32H
,
4504 ubld
.MOV(res1
, brw_imm_d(-1)));
4506 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4509 case nir_intrinsic_vote_all
: {
4510 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4512 /* The any/all predicates do not consider channel enables. To prevent
4513 * dead channels from affecting the result, we initialize the flag with
4514 * with the identity value for the logical operation.
4516 if (dispatch_width
== 32) {
4517 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4518 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4519 brw_imm_ud(0xffffffff));
4521 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4523 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4525 /* For some reason, the any/all predicates don't work properly with
4526 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4527 * doesn't read the correct subset of the flag register and you end up
4528 * getting garbage in the second half. Work around this by using a pair
4529 * of 1-wide MOVs and scattering the result.
4531 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4532 ubld
.MOV(res1
, brw_imm_d(0));
4533 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4534 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4535 BRW_PREDICATE_ALIGN1_ALL32H
,
4536 ubld
.MOV(res1
, brw_imm_d(-1)));
4538 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4541 case nir_intrinsic_vote_feq
:
4542 case nir_intrinsic_vote_ieq
: {
4543 fs_reg value
= get_nir_src(instr
->src
[0]);
4544 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4545 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4546 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4549 fs_reg uniformized
= bld
.emit_uniformize(value
);
4550 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4552 /* The any/all predicates do not consider channel enables. To prevent
4553 * dead channels from affecting the result, we initialize the flag with
4554 * with the identity value for the logical operation.
4556 if (dispatch_width
== 32) {
4557 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4558 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4559 brw_imm_ud(0xffffffff));
4561 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4563 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4565 /* For some reason, the any/all predicates don't work properly with
4566 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4567 * doesn't read the correct subset of the flag register and you end up
4568 * getting garbage in the second half. Work around this by using a pair
4569 * of 1-wide MOVs and scattering the result.
4571 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4572 ubld
.MOV(res1
, brw_imm_d(0));
4573 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4574 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4575 BRW_PREDICATE_ALIGN1_ALL32H
,
4576 ubld
.MOV(res1
, brw_imm_d(-1)));
4578 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4582 case nir_intrinsic_ballot
: {
4583 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4584 BRW_REGISTER_TYPE_UD
);
4585 struct brw_reg flag
= brw_flag_reg(0, 0);
4586 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4587 * as f0.0. This is a problem for fragment programs as we currently use
4588 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4589 * programs yet so this isn't a problem. When we do, something will
4592 if (dispatch_width
== 32)
4593 flag
.type
= BRW_REGISTER_TYPE_UD
;
4595 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4596 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4598 if (instr
->dest
.ssa
.bit_size
> 32) {
4599 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4601 dest
.type
= BRW_REGISTER_TYPE_UD
;
4603 bld
.MOV(dest
, flag
);
4607 case nir_intrinsic_read_invocation
: {
4608 const fs_reg value
= get_nir_src(instr
->src
[0]);
4609 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4610 fs_reg tmp
= bld
.vgrf(value
.type
);
4612 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4613 bld
.emit_uniformize(invocation
));
4615 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4619 case nir_intrinsic_read_first_invocation
: {
4620 const fs_reg value
= get_nir_src(instr
->src
[0]);
4621 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4625 case nir_intrinsic_shuffle
: {
4626 const fs_reg value
= get_nir_src(instr
->src
[0]);
4627 const fs_reg index
= get_nir_src(instr
->src
[1]);
4629 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4633 case nir_intrinsic_first_invocation
: {
4634 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4635 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4636 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4637 fs_reg(component(tmp
, 0)));
4641 case nir_intrinsic_quad_broadcast
: {
4642 const fs_reg value
= get_nir_src(instr
->src
[0]);
4643 nir_const_value
*index
= nir_src_as_const_value(instr
->src
[1]);
4644 assert(nir_src_bit_size(instr
->src
[1]) == 32);
4646 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4647 value
, brw_imm_ud(index
->u32
[0]), brw_imm_ud(4));
4651 case nir_intrinsic_quad_swap_horizontal
: {
4652 const fs_reg value
= get_nir_src(instr
->src
[0]);
4653 const fs_reg tmp
= bld
.vgrf(value
.type
);
4654 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4656 const fs_reg src_left
= horiz_stride(value
, 2);
4657 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4658 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4659 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4661 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4663 * "When source or destination datatype is 64b or operation is
4664 * integer DWord multiply, regioning in Align1 must follow
4669 * 3. Source and Destination offset must be the same, except
4670 * the case of scalar source."
4672 * In order to work around this, we have to emit two 32-bit MOVs instead
4673 * of a single 64-bit MOV to do the shuffle.
4675 if (type_sz(value
.type
) > 4 &&
4676 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4677 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4678 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4679 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4680 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4681 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4682 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4683 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4684 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4686 ubld
.MOV(tmp_left
, src_right
);
4687 ubld
.MOV(tmp_right
, src_left
);
4689 bld
.MOV(retype(dest
, value
.type
), tmp
);
4693 case nir_intrinsic_quad_swap_vertical
: {
4694 const fs_reg value
= get_nir_src(instr
->src
[0]);
4695 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4696 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4697 const fs_reg tmp
= bld
.vgrf(value
.type
);
4698 const fs_builder ubld
= bld
.exec_all();
4699 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4700 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4701 bld
.MOV(retype(dest
, value
.type
), tmp
);
4703 /* For larger data types, we have to either emit dispatch_width many
4704 * MOVs or else fall back to doing indirects.
4706 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4707 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4709 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4714 case nir_intrinsic_quad_swap_diagonal
: {
4715 const fs_reg value
= get_nir_src(instr
->src
[0]);
4716 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4717 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4718 const fs_reg tmp
= bld
.vgrf(value
.type
);
4719 const fs_builder ubld
= bld
.exec_all();
4720 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4721 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4722 bld
.MOV(retype(dest
, value
.type
), tmp
);
4724 /* For larger data types, we have to either emit dispatch_width many
4725 * MOVs or else fall back to doing indirects.
4727 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4728 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4730 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4735 case nir_intrinsic_reduce
: {
4736 fs_reg src
= get_nir_src(instr
->src
[0]);
4737 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4738 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4739 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4740 cluster_size
= dispatch_width
;
4742 /* Figure out the source type */
4743 src
.type
= brw_type_for_nir_type(devinfo
,
4744 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4745 nir_src_bit_size(instr
->src
[0])));
4747 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4748 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4749 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4751 /* Set up a register for all of our scratching around and initialize it
4752 * to reduction operation's identity value.
4754 fs_reg scan
= bld
.vgrf(src
.type
);
4755 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4757 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4759 dest
.type
= src
.type
;
4760 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4761 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4762 * the distance between clusters is at least 2 GRFs. In this case,
4763 * we don't need the weird striding of the CLUSTER_BROADCAST
4764 * instruction and can just do regular MOVs.
4766 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4767 const unsigned groups
=
4768 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4769 const unsigned group_size
= dispatch_width
/ groups
;
4770 for (unsigned i
= 0; i
< groups
; i
++) {
4771 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4772 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4773 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4774 component(scan
, comp
));
4777 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4778 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4783 case nir_intrinsic_inclusive_scan
:
4784 case nir_intrinsic_exclusive_scan
: {
4785 fs_reg src
= get_nir_src(instr
->src
[0]);
4786 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4788 /* Figure out the source type */
4789 src
.type
= brw_type_for_nir_type(devinfo
,
4790 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4791 nir_src_bit_size(instr
->src
[0])));
4793 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4794 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4795 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4797 /* Set up a register for all of our scratching around and initialize it
4798 * to reduction operation's identity value.
4800 fs_reg scan
= bld
.vgrf(src
.type
);
4801 const fs_builder allbld
= bld
.exec_all();
4802 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4804 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4805 /* Exclusive scan is a bit harder because we have to do an annoying
4806 * shift of the contents before we can begin. To make things worse,
4807 * we can't do this with a normal stride; we have to use indirects.
4809 fs_reg shifted
= bld
.vgrf(src
.type
);
4810 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4811 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4813 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4814 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4818 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4820 bld
.MOV(retype(dest
, src
.type
), scan
);
4824 case nir_intrinsic_begin_invocation_interlock
: {
4825 const fs_builder ubld
= bld
.group(8, 0);
4826 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4828 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4834 case nir_intrinsic_end_invocation_interlock
: {
4835 /* We don't need to do anything here */
4840 unreachable("unknown intrinsic");
4845 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4846 int op
, nir_intrinsic_instr
*instr
)
4848 if (stage
== MESA_SHADER_FRAGMENT
)
4849 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4852 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4853 dest
= get_nir_dest(instr
->dest
);
4856 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4857 if (const_surface
) {
4858 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4859 const_surface
->u32
[0];
4860 surface
= brw_imm_ud(surf_index
);
4861 brw_mark_surface_used(prog_data
, surf_index
);
4863 surface
= vgrf(glsl_type::uint_type
);
4864 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4865 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4867 /* Assume this may touch any SSBO. This is the same we do for other
4868 * UBO/SSBO accesses with non-constant surface.
4870 brw_mark_surface_used(prog_data
,
4871 stage_prog_data
->binding_table
.ssbo_start
+
4872 nir
->info
.num_ssbos
- 1);
4875 fs_reg offset
= get_nir_src(instr
->src
[1]);
4876 fs_reg data1
= get_nir_src(instr
->src
[2]);
4878 if (op
== BRW_AOP_CMPWR
)
4879 data2
= get_nir_src(instr
->src
[3]);
4881 /* Emit the actual atomic operation */
4883 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4885 1 /* dims */, 1 /* rsize */,
4887 BRW_PREDICATE_NONE
);
4888 dest
.type
= atomic_result
.type
;
4889 bld
.MOV(dest
, atomic_result
);
4893 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4894 int op
, nir_intrinsic_instr
*instr
)
4897 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4898 dest
= get_nir_dest(instr
->dest
);
4900 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4902 fs_reg data1
= get_nir_src(instr
->src
[1]);
4904 if (op
== BRW_AOP_CMPWR
)
4905 data2
= get_nir_src(instr
->src
[2]);
4907 /* Get the offset */
4908 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4910 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4912 offset
= vgrf(glsl_type::uint_type
);
4914 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4915 brw_imm_ud(instr
->const_index
[0]));
4918 /* Emit the actual atomic operation operation */
4920 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4922 1 /* dims */, 1 /* rsize */,
4924 BRW_PREDICATE_NONE
);
4925 dest
.type
= atomic_result
.type
;
4926 bld
.MOV(dest
, atomic_result
);
4930 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4932 unsigned texture
= instr
->texture_index
;
4933 unsigned sampler
= instr
->sampler_index
;
4935 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4937 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4938 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4940 int lod_components
= 0;
4942 /* The hardware requires a LOD for buffer textures */
4943 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4944 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4946 uint32_t header_bits
= 0;
4947 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4948 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4949 switch (instr
->src
[i
].src_type
) {
4950 case nir_tex_src_bias
:
4951 srcs
[TEX_LOGICAL_SRC_LOD
] =
4952 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4954 case nir_tex_src_comparator
:
4955 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4957 case nir_tex_src_coord
:
4958 switch (instr
->op
) {
4960 case nir_texop_txf_ms
:
4961 case nir_texop_txf_ms_mcs
:
4962 case nir_texop_samples_identical
:
4963 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4966 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4970 case nir_tex_src_ddx
:
4971 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4972 lod_components
= nir_tex_instr_src_size(instr
, i
);
4974 case nir_tex_src_ddy
:
4975 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4977 case nir_tex_src_lod
:
4978 switch (instr
->op
) {
4980 srcs
[TEX_LOGICAL_SRC_LOD
] =
4981 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4984 srcs
[TEX_LOGICAL_SRC_LOD
] =
4985 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4988 srcs
[TEX_LOGICAL_SRC_LOD
] =
4989 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4993 case nir_tex_src_ms_index
:
4994 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4997 case nir_tex_src_offset
: {
4998 nir_const_value
*const_offset
=
4999 nir_src_as_const_value(instr
->src
[i
].src
);
5000 unsigned offset_bits
= 0;
5002 brw_texture_offset(const_offset
->i32
,
5003 nir_tex_instr_src_size(instr
, i
),
5005 header_bits
|= offset_bits
;
5007 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5008 retype(src
, BRW_REGISTER_TYPE_D
);
5013 case nir_tex_src_projector
:
5014 unreachable("should be lowered");
5016 case nir_tex_src_texture_offset
: {
5017 /* Figure out the highest possible texture index and mark it as used */
5018 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
5019 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
5020 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
5022 max_used
+= stage_prog_data
->binding_table
.texture_start
;
5024 brw_mark_surface_used(prog_data
, max_used
);
5026 /* Emit code to evaluate the actual indexing expression */
5027 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5028 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5029 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5033 case nir_tex_src_sampler_offset
: {
5034 /* Emit code to evaluate the actual indexing expression */
5035 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5036 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5037 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5041 case nir_tex_src_ms_mcs
:
5042 assert(instr
->op
== nir_texop_txf_ms
);
5043 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5046 case nir_tex_src_plane
: {
5047 nir_const_value
*const_plane
=
5048 nir_src_as_const_value(instr
->src
[i
].src
);
5049 const uint32_t plane
= const_plane
->u32
[0];
5050 const uint32_t texture_index
=
5051 instr
->texture_index
+
5052 stage_prog_data
->binding_table
.plane_start
[plane
] -
5053 stage_prog_data
->binding_table
.texture_start
;
5055 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5060 unreachable("unknown texture source");
5064 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5065 (instr
->op
== nir_texop_txf_ms
||
5066 instr
->op
== nir_texop_samples_identical
)) {
5067 if (devinfo
->gen
>= 7 &&
5068 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5069 srcs
[TEX_LOGICAL_SRC_MCS
] =
5070 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5071 instr
->coord_components
,
5072 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5074 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5078 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5079 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5082 switch (instr
->op
) {
5084 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5085 SHADER_OPCODE_TXL_LOGICAL
);
5088 opcode
= FS_OPCODE_TXB_LOGICAL
;
5091 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5094 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5097 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5099 case nir_texop_txf_ms
:
5100 if ((key_tex
->msaa_16
& (1 << sampler
)))
5101 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5103 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5105 case nir_texop_txf_ms_mcs
:
5106 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5108 case nir_texop_query_levels
:
5110 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5113 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5116 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5117 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5119 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5121 case nir_texop_texture_samples
:
5122 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5124 case nir_texop_samples_identical
: {
5125 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5127 /* If mcs is an immediate value, it means there is no MCS. In that case
5128 * just return false.
5130 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5131 bld
.MOV(dst
, brw_imm_ud(0u));
5132 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5133 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5134 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5135 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5136 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5138 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5139 BRW_CONDITIONAL_EQ
);
5144 unreachable("unknown texture opcode");
5147 if (instr
->op
== nir_texop_tg4
) {
5148 if (instr
->component
== 1 &&
5149 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5150 /* gather4 sampler is broken for green channel on RG32F --
5151 * we must ask for blue instead.
5153 header_bits
|= 2 << 16;
5155 header_bits
|= instr
->component
<< 16;
5159 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5160 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5161 inst
->offset
= header_bits
;
5163 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5164 if (devinfo
->gen
>= 9 &&
5165 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5166 unsigned write_mask
= instr
->dest
.is_ssa
?
5167 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5168 (1 << dest_size
) - 1;
5169 assert(write_mask
!= 0); /* dead code should have been eliminated */
5170 inst
->size_written
= util_last_bit(write_mask
) *
5171 inst
->dst
.component_size(inst
->exec_size
);
5173 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5176 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5177 inst
->shadow_compare
= true;
5179 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5180 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5183 for (unsigned i
= 0; i
< dest_size
; i
++)
5184 nir_dest
[i
] = offset(dst
, bld
, i
);
5186 if (instr
->op
== nir_texop_query_levels
) {
5187 /* # levels is in .w */
5188 nir_dest
[0] = offset(dst
, bld
, 3);
5189 } else if (instr
->op
== nir_texop_txs
&&
5190 dest_size
>= 3 && devinfo
->gen
< 7) {
5191 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5192 fs_reg depth
= offset(dst
, bld
, 2);
5193 nir_dest
[2] = vgrf(glsl_type::int_type
);
5194 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5197 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5201 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5203 switch (instr
->type
) {
5204 case nir_jump_break
:
5205 bld
.emit(BRW_OPCODE_BREAK
);
5207 case nir_jump_continue
:
5208 bld
.emit(BRW_OPCODE_CONTINUE
);
5210 case nir_jump_return
:
5212 unreachable("unknown jump");
5217 * This helper takes a source register and un/shuffles it into the destination
5220 * If source type size is smaller than destination type size the operation
5221 * needed is a component shuffle. The opposite case would be an unshuffle. If
5222 * source/destination type size is equal a shuffle is done that would be
5223 * equivalent to a simple MOV.
5225 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5226 * components .xyz 16-bit vector on SIMD8 would be.
5228 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5229 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5231 * This helper will return the following 2 32-bit components with the 16-bit
5234 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5235 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5237 * For unshuffle, the example would be the opposite, a 64-bit type source
5238 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5241 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5242 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5243 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5244 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5246 * The returned result would be the following 4 32-bit components unshuffled:
5248 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5249 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5250 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5251 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5253 * - Source and destination register must not be overlapped.
5254 * - components units are measured in terms of the smaller type between
5255 * source and destination because we are un/shuffling the smaller
5256 * components from/into the bigger ones.
5257 * - first_component parameter allows skipping source components.
5260 shuffle_src_to_dst(const fs_builder
&bld
,
5263 uint32_t first_component
,
5264 uint32_t components
)
5266 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5267 assert(!regions_overlap(dst
,
5268 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5269 offset(src
, bld
, first_component
),
5270 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5271 for (unsigned i
= 0; i
< components
; i
++) {
5272 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5273 offset(src
, bld
, i
+ first_component
));
5275 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5276 /* Source is shuffled into destination */
5277 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5278 assert(!regions_overlap(dst
,
5279 type_sz(dst
.type
) * bld
.dispatch_width() *
5280 DIV_ROUND_UP(components
, size_ratio
),
5281 offset(src
, bld
, first_component
),
5282 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5284 brw_reg_type shuffle_type
=
5285 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5286 BRW_REGISTER_TYPE_D
);
5287 for (unsigned i
= 0; i
< components
; i
++) {
5288 fs_reg shuffle_component_i
=
5289 subscript(offset(dst
, bld
, i
/ size_ratio
),
5290 shuffle_type
, i
% size_ratio
);
5291 bld
.MOV(shuffle_component_i
,
5292 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5295 /* Source is unshuffled into destination */
5296 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5297 assert(!regions_overlap(dst
,
5298 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5299 offset(src
, bld
, first_component
/ size_ratio
),
5300 type_sz(src
.type
) * bld
.dispatch_width() *
5301 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5304 brw_reg_type shuffle_type
=
5305 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5306 BRW_REGISTER_TYPE_D
);
5307 for (unsigned i
= 0; i
< components
; i
++) {
5308 fs_reg shuffle_component_i
=
5309 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5310 shuffle_type
, (first_component
+ i
) % size_ratio
);
5311 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5312 shuffle_component_i
);
5318 shuffle_from_32bit_read(const fs_builder
&bld
,
5321 uint32_t first_component
,
5322 uint32_t components
)
5324 assert(type_sz(src
.type
) == 4);
5326 /* This function takes components in units of the destination type while
5327 * shuffle_src_to_dst takes components in units of the smallest type
5329 if (type_sz(dst
.type
) > 4) {
5330 assert(type_sz(dst
.type
) == 8);
5331 first_component
*= 2;
5335 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5339 shuffle_for_32bit_write(const fs_builder
&bld
,
5341 uint32_t first_component
,
5342 uint32_t components
)
5344 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5345 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5346 /* This function takes components in units of the source type while
5347 * shuffle_src_to_dst takes components in units of the smallest type
5349 if (type_sz(src
.type
) > 4) {
5350 assert(type_sz(src
.type
) == 8);
5351 first_component
*= 2;
5355 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5361 setup_imm_df(const fs_builder
&bld
, double v
)
5363 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5364 assert(devinfo
->gen
>= 7);
5366 if (devinfo
->gen
>= 8)
5367 return brw_imm_df(v
);
5369 /* gen7.5 does not support DF immediates straighforward but the DIM
5370 * instruction allows to set the 64-bit immediate value.
5372 if (devinfo
->is_haswell
) {
5373 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5374 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5375 ubld
.DIM(dst
, brw_imm_df(v
));
5376 return component(dst
, 0);
5379 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5380 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5381 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5383 * Alternatively, we could also produce a normal VGRF (without stride 0)
5384 * by writing to all the channels in the VGRF, however, that would hit the
5385 * gen7 bug where we have to split writes that span more than 1 register
5386 * into instructions with a width of 4 (otherwise the write to the second
5387 * register written runs into an execmask hardware bug) which isn't very
5400 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5401 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5402 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5403 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5405 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);