2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "util/u_math.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
47 fs_visitor::nir_setup_outputs()
49 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
52 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
54 /* Calculate the size of output registers in a separate pass, before
55 * allocating them. With ARB_enhanced_layouts, multiple output variables
56 * may occupy the same slot, but have different type sizes.
58 nir_foreach_variable(var
, &nir
->outputs
) {
59 const int loc
= var
->data
.driver_location
;
60 const unsigned var_vec4s
=
61 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
62 : type_size_vec4(var
->type
);
63 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
66 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
67 if (vec4s
[loc
] == 0) {
72 unsigned reg_size
= vec4s
[loc
];
74 /* Check if there are any ranges that start within this range and extend
75 * past it. If so, include them in this allocation.
77 for (unsigned i
= 1; i
< reg_size
; i
++)
78 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
80 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
81 for (unsigned i
= 0; i
< reg_size
; i
++)
82 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
89 fs_visitor::nir_setup_uniforms()
91 /* Only the first compile gets to set up uniforms. */
92 if (push_constant_loc
) {
93 assert(pull_constant_loc
);
97 uniforms
= nir
->num_uniforms
/ 4;
99 if (stage
== MESA_SHADER_COMPUTE
) {
100 /* Add a uniform for the thread local id. It must be the last uniform
103 assert(uniforms
== prog_data
->nr_params
);
104 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
105 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
106 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
111 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
115 nir_foreach_instr(instr
, block
) {
116 if (instr
->type
!= nir_instr_type_intrinsic
)
119 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
120 switch (intrin
->intrinsic
) {
121 case nir_intrinsic_load_vertex_id
:
122 case nir_intrinsic_load_base_vertex
:
123 unreachable("should be lowered by nir_lower_system_values().");
125 case nir_intrinsic_load_vertex_id_zero_base
:
126 case nir_intrinsic_load_is_indexed_draw
:
127 case nir_intrinsic_load_first_vertex
:
128 case nir_intrinsic_load_instance_id
:
129 case nir_intrinsic_load_base_instance
:
130 case nir_intrinsic_load_draw_id
:
131 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
133 case nir_intrinsic_load_invocation_id
:
134 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
136 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
137 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
138 if (reg
->file
== BAD_FILE
) {
139 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
140 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
141 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
142 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
147 case nir_intrinsic_load_sample_pos
:
148 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_samplepos_setup();
154 case nir_intrinsic_load_sample_id
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
157 if (reg
->file
== BAD_FILE
)
158 *reg
= *v
->emit_sampleid_setup();
161 case nir_intrinsic_load_sample_mask_in
:
162 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
163 assert(v
->devinfo
->gen
>= 7);
164 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
165 if (reg
->file
== BAD_FILE
)
166 *reg
= *v
->emit_samplemaskin_setup();
169 case nir_intrinsic_load_work_group_id
:
170 assert(v
->stage
== MESA_SHADER_COMPUTE
);
171 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
172 if (reg
->file
== BAD_FILE
)
173 *reg
= *v
->emit_cs_work_group_id_setup();
176 case nir_intrinsic_load_helper_invocation
:
177 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
178 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
179 if (reg
->file
== BAD_FILE
) {
180 const fs_builder abld
=
181 v
->bld
.annotate("gl_HelperInvocation", NULL
);
183 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
184 * pixel mask is in g1.7 of the thread payload.
186 * We move the per-channel pixel enable bit to the low bit of each
187 * channel by shifting the byte containing the pixel mask by the
188 * vector immediate 0x76543210UV.
190 * The region of <1,8,0> reads only 1 byte (the pixel masks for
191 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
192 * masks for 2 and 3) in SIMD16.
194 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
196 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
197 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
198 hbld
.SHR(offset(shifted
, hbld
, i
),
199 stride(retype(brw_vec1_grf(1 + i
, 7),
200 BRW_REGISTER_TYPE_UB
),
202 brw_imm_v(0x76543210));
205 /* A set bit in the pixel mask means the channel is enabled, but
206 * that is the opposite of gl_HelperInvocation so we need to invert
209 * The negate source-modifier bit of logical instructions on Gen8+
210 * performs 1's complement negation, so we can use that instead of
213 fs_reg inverted
= negate(shifted
);
214 if (v
->devinfo
->gen
< 8) {
215 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
216 abld
.NOT(inverted
, shifted
);
219 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
220 * with 1 and negating.
222 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
223 abld
.AND(anded
, inverted
, brw_imm_uw(1));
225 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
226 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
240 fs_visitor::nir_emit_system_values()
242 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
243 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
244 nir_system_values
[i
] = fs_reg();
247 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
248 * never end up using it.
251 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
252 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
253 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
255 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
256 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
257 if (dispatch_width
> 8)
258 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
259 if (dispatch_width
> 16) {
260 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
261 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
265 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
266 nir_foreach_block(block
, impl
)
267 emit_system_values_block(block
, this);
271 * Returns a type based on a reference_type (word, float, half-float) and a
274 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
276 * @FIXME: 64-bit return types are always DF on integer types to maintain
277 * compability with uses of DF previously to the introduction of int64
281 brw_reg_type_from_bit_size(const unsigned bit_size
,
282 const brw_reg_type reference_type
)
284 switch(reference_type
) {
285 case BRW_REGISTER_TYPE_HF
:
286 case BRW_REGISTER_TYPE_F
:
287 case BRW_REGISTER_TYPE_DF
:
290 return BRW_REGISTER_TYPE_HF
;
292 return BRW_REGISTER_TYPE_F
;
294 return BRW_REGISTER_TYPE_DF
;
296 unreachable("Invalid bit size");
298 case BRW_REGISTER_TYPE_B
:
299 case BRW_REGISTER_TYPE_W
:
300 case BRW_REGISTER_TYPE_D
:
301 case BRW_REGISTER_TYPE_Q
:
304 return BRW_REGISTER_TYPE_B
;
306 return BRW_REGISTER_TYPE_W
;
308 return BRW_REGISTER_TYPE_D
;
310 return BRW_REGISTER_TYPE_Q
;
312 unreachable("Invalid bit size");
314 case BRW_REGISTER_TYPE_UB
:
315 case BRW_REGISTER_TYPE_UW
:
316 case BRW_REGISTER_TYPE_UD
:
317 case BRW_REGISTER_TYPE_UQ
:
320 return BRW_REGISTER_TYPE_UB
;
322 return BRW_REGISTER_TYPE_UW
;
324 return BRW_REGISTER_TYPE_UD
;
326 return BRW_REGISTER_TYPE_UQ
;
328 unreachable("Invalid bit size");
331 unreachable("Unknown type");
336 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
338 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
339 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
340 nir_locals
[i
] = fs_reg();
343 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
344 unsigned array_elems
=
345 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
346 unsigned size
= array_elems
* reg
->num_components
;
347 const brw_reg_type reg_type
=
348 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
349 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
352 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
355 nir_emit_cf_list(&impl
->body
);
359 fs_visitor::nir_emit_cf_list(exec_list
*list
)
361 exec_list_validate(list
);
362 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
363 switch (node
->type
) {
365 nir_emit_if(nir_cf_node_as_if(node
));
368 case nir_cf_node_loop
:
369 nir_emit_loop(nir_cf_node_as_loop(node
));
372 case nir_cf_node_block
:
373 nir_emit_block(nir_cf_node_as_block(node
));
377 unreachable("Invalid CFG node block");
383 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
385 /* first, put the condition into f0 */
386 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
387 retype(get_nir_src(if_stmt
->condition
),
388 BRW_REGISTER_TYPE_D
));
389 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
391 bld
.IF(BRW_PREDICATE_NORMAL
);
393 nir_emit_cf_list(&if_stmt
->then_list
);
395 /* note: if the else is empty, dead CF elimination will remove it */
396 bld
.emit(BRW_OPCODE_ELSE
);
398 nir_emit_cf_list(&if_stmt
->else_list
);
400 bld
.emit(BRW_OPCODE_ENDIF
);
402 if (devinfo
->gen
< 7)
403 limit_dispatch_width(16, "Non-uniform control flow unsupported "
408 fs_visitor::nir_emit_loop(nir_loop
*loop
)
410 bld
.emit(BRW_OPCODE_DO
);
412 nir_emit_cf_list(&loop
->body
);
414 bld
.emit(BRW_OPCODE_WHILE
);
416 if (devinfo
->gen
< 7)
417 limit_dispatch_width(16, "Non-uniform control flow unsupported "
422 fs_visitor::nir_emit_block(nir_block
*block
)
424 nir_foreach_instr(instr
, block
) {
425 nir_emit_instr(instr
);
430 fs_visitor::nir_emit_instr(nir_instr
*instr
)
432 const fs_builder abld
= bld
.annotate(NULL
, instr
);
434 switch (instr
->type
) {
435 case nir_instr_type_alu
:
436 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
439 case nir_instr_type_deref
:
440 /* Derefs can exist for images but they do nothing */
443 case nir_instr_type_intrinsic
:
445 case MESA_SHADER_VERTEX
:
446 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
448 case MESA_SHADER_TESS_CTRL
:
449 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
451 case MESA_SHADER_TESS_EVAL
:
452 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
454 case MESA_SHADER_GEOMETRY
:
455 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
457 case MESA_SHADER_FRAGMENT
:
458 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
460 case MESA_SHADER_COMPUTE
:
461 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
464 unreachable("unsupported shader stage");
468 case nir_instr_type_tex
:
469 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
472 case nir_instr_type_load_const
:
473 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
476 case nir_instr_type_ssa_undef
:
477 /* We create a new VGRF for undefs on every use (by handling
478 * them in get_nir_src()), rather than for each definition.
479 * This helps register coalescing eliminate MOVs from undef.
483 case nir_instr_type_jump
:
484 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
488 unreachable("unknown instruction type");
493 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
497 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
498 const fs_reg
&result
)
500 if (!instr
->src
[0].src
.is_ssa
||
501 !instr
->src
[0].src
.ssa
->parent_instr
)
504 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
507 nir_alu_instr
*src0
=
508 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
510 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
511 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
514 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
516 /* Element type to extract.*/
517 const brw_reg_type type
= brw_int_type(
518 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
519 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
521 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
522 op0
.type
= brw_type_for_nir_type(devinfo
,
523 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
524 nir_src_bit_size(src0
->src
[0].src
)));
525 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
527 set_saturate(instr
->dest
.saturate
,
528 bld
.MOV(result
, subscript(op0
, type
, element
)));
533 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
534 const fs_reg
&result
)
536 if (!instr
->src
[0].src
.is_ssa
||
537 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
540 nir_intrinsic_instr
*src0
=
541 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
543 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
546 if (!nir_src_is_const(instr
->src
[1].src
) ||
547 !nir_src_is_const(instr
->src
[2].src
))
550 const float value1
= nir_src_as_float(instr
->src
[1].src
);
551 const float value2
= nir_src_as_float(instr
->src
[2].src
);
552 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
555 fs_reg tmp
= vgrf(glsl_type::int_type
);
557 if (devinfo
->gen
>= 6) {
558 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
559 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
561 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
563 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
564 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
566 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
568 * This negation looks like it's safe in practice, because bits 0:4 will
569 * surely be TRIANGLES
572 if (value1
== -1.0f
) {
576 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
577 g0
, brw_imm_uw(0x3f80));
579 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
580 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
582 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
584 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
585 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
587 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
589 * This negation looks like it's safe in practice, because bits 0:4 will
590 * surely be TRIANGLES
593 if (value1
== -1.0f
) {
597 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
599 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
605 emit_find_msb_using_lzd(const fs_builder
&bld
,
606 const fs_reg
&result
,
614 /* LZD of an absolute value source almost always does the right
615 * thing. There are two problem values:
617 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
618 * 0. However, findMSB(int(0x80000000)) == 30.
620 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
621 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
623 * For a value of zero or negative one, -1 will be returned.
625 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
626 * findMSB(-(1<<x)) should return x-1.
628 * For all negative number cases, including 0x80000000 and
629 * 0xffffffff, the correct value is obtained from LZD if instead of
630 * negating the (already negative) value the logical-not is used. A
631 * conditonal logical-not can be achieved in two instructions.
633 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
635 bld
.ASR(temp
, src
, brw_imm_d(31));
636 bld
.XOR(temp
, temp
, src
);
639 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
640 retype(temp
, BRW_REGISTER_TYPE_UD
));
642 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
643 * from the LSB side. Subtract the result from 31 to convert the MSB
644 * count into an LSB count. If no bits are set, LZD will return 32.
645 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
647 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
648 inst
->src
[0].negate
= true;
652 brw_rnd_mode_from_nir_op (const nir_op op
) {
654 case nir_op_f2f16_rtz
:
655 return BRW_RND_MODE_RTZ
;
656 case nir_op_f2f16_rtne
:
657 return BRW_RND_MODE_RTNE
;
659 unreachable("Operation doesn't support rounding mode");
664 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
666 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
669 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
670 result
.type
= brw_type_for_nir_type(devinfo
,
671 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
672 nir_dest_bit_size(instr
->dest
.dest
)));
675 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
676 op
[i
] = get_nir_src(instr
->src
[i
].src
);
677 op
[i
].type
= brw_type_for_nir_type(devinfo
,
678 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
679 nir_src_bit_size(instr
->src
[i
].src
)));
680 op
[i
].abs
= instr
->src
[i
].abs
;
681 op
[i
].negate
= instr
->src
[i
].negate
;
684 /* We get a bunch of mov's out of the from_ssa pass and they may still
685 * be vectorized. We'll handle them as a special-case. We'll also
686 * handle vecN here because it's basically the same thing.
694 fs_reg temp
= result
;
695 bool need_extra_copy
= false;
696 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
697 if (!instr
->src
[i
].src
.is_ssa
&&
698 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
699 need_extra_copy
= true;
700 temp
= bld
.vgrf(result
.type
, 4);
705 for (unsigned i
= 0; i
< 4; i
++) {
706 if (!(instr
->dest
.write_mask
& (1 << i
)))
709 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
710 inst
= bld
.MOV(offset(temp
, bld
, i
),
711 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
713 inst
= bld
.MOV(offset(temp
, bld
, i
),
714 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
716 inst
->saturate
= instr
->dest
.saturate
;
719 /* In this case the source and destination registers were the same,
720 * so we need to insert an extra set of moves in order to deal with
723 if (need_extra_copy
) {
724 for (unsigned i
= 0; i
< 4; i
++) {
725 if (!(instr
->dest
.write_mask
& (1 << i
)))
728 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
737 /* At this point, we have dealt with any instruction that operates on
738 * more than a single channel. Therefore, we can just adjust the source
739 * and destination registers for that channel and emit the instruction.
741 unsigned channel
= 0;
742 if (nir_op_infos
[instr
->op
].output_size
== 0) {
743 /* Since NIR is doing the scalarizing for us, we should only ever see
744 * vectorized operations with a single channel.
746 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
747 channel
= ffs(instr
->dest
.write_mask
) - 1;
749 result
= offset(result
, bld
, channel
);
752 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
753 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
754 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
760 if (optimize_extract_to_float(instr
, result
))
762 inst
= bld
.MOV(result
, op
[0]);
763 inst
->saturate
= instr
->dest
.saturate
;
766 case nir_op_f2f16_rtne
:
767 case nir_op_f2f16_rtz
:
768 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
769 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
772 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
773 * on the HW gen, it is a special hw opcode or just a MOV, and
774 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
776 * But if we want to use that opcode, we need to provide support on
777 * different optimizations and lowerings. As right now HF support is
778 * only for gen8+, it will be better to use directly the MOV, and use
779 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
783 inst
= bld
.MOV(result
, op
[0]);
784 inst
->saturate
= instr
->dest
.saturate
;
789 op
[0].type
= BRW_REGISTER_TYPE_D
;
790 op
[0].negate
= !op
[0].negate
;
799 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
801 * "When source or destination is 64b (...), regioning in Align1
802 * must follow these rules:
804 * 1. Source and destination horizontal stride must be aligned to
808 * This means that conversions from bit-sizes smaller than 64-bit to
809 * 64-bit need to have the source data elements aligned to 64-bit.
810 * This restriction does not apply to BDW and later.
812 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
813 nir_src_bit_size(instr
->src
[0].src
) < 64 &&
814 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
815 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
816 tmp
= subscript(tmp
, op
[0].type
, 0);
817 inst
= bld
.MOV(tmp
, op
[0]);
818 inst
= bld
.MOV(result
, tmp
);
819 inst
->saturate
= instr
->dest
.saturate
;
836 inst
= bld
.MOV(result
, op
[0]);
837 inst
->saturate
= instr
->dest
.saturate
;
841 assert(!instr
->dest
.saturate
);
843 /* Straightforward since the source can be assumed to be either
844 * strictly >= 0 or strictly <= 0 depending on the setting of the
847 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
849 inst
= (op
[0].negate
)
850 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
851 : bld
.MOV(result
, brw_imm_f(1.0f
));
853 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
854 } else if (type_sz(op
[0].type
) < 8) {
855 /* AND(val, 0x80000000) gives the sign bit.
857 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
860 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
862 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
863 op
[0].type
= BRW_REGISTER_TYPE_UD
;
864 result
.type
= BRW_REGISTER_TYPE_UD
;
865 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
867 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
868 inst
->predicate
= BRW_PREDICATE_NORMAL
;
870 /* For doubles we do the same but we need to consider:
872 * - 2-src instructions can't operate with 64-bit immediates
873 * - The sign is encoded in the high 32-bit of each DF
874 * - We need to produce a DF result.
877 fs_reg zero
= vgrf(glsl_type::double_type
);
878 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
879 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
881 bld
.MOV(result
, zero
);
883 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
884 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
885 brw_imm_ud(0x80000000u
));
887 set_predicate(BRW_PREDICATE_NORMAL
,
888 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
894 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
895 * -> non-negative val generates 0x00000000.
896 * Predicated OR sets 1 if val is positive.
898 uint32_t bit_size
= nir_dest_bit_size(instr
->dest
.dest
);
899 assert(bit_size
== 32 || bit_size
== 16);
901 fs_reg zero
= bit_size
== 32 ? brw_imm_d(0) : brw_imm_w(0);
902 fs_reg one
= bit_size
== 32 ? brw_imm_d(1) : brw_imm_w(1);
903 fs_reg shift
= bit_size
== 32 ? brw_imm_d(31) : brw_imm_w(15);
905 bld
.CMP(bld
.null_reg_d(), op
[0], zero
, BRW_CONDITIONAL_G
);
906 bld
.ASR(result
, op
[0], shift
);
907 inst
= bld
.OR(result
, result
, one
);
908 inst
->predicate
= BRW_PREDICATE_NORMAL
;
913 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
914 inst
->saturate
= instr
->dest
.saturate
;
918 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
919 inst
->saturate
= instr
->dest
.saturate
;
923 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
924 inst
->saturate
= instr
->dest
.saturate
;
928 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
929 inst
->saturate
= instr
->dest
.saturate
;
933 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
934 inst
->saturate
= instr
->dest
.saturate
;
938 if (fs_key
->high_quality_derivatives
) {
939 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
941 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
943 inst
->saturate
= instr
->dest
.saturate
;
945 case nir_op_fddx_fine
:
946 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
947 inst
->saturate
= instr
->dest
.saturate
;
949 case nir_op_fddx_coarse
:
950 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
951 inst
->saturate
= instr
->dest
.saturate
;
954 if (fs_key
->high_quality_derivatives
) {
955 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
957 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
959 inst
->saturate
= instr
->dest
.saturate
;
961 case nir_op_fddy_fine
:
962 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
963 inst
->saturate
= instr
->dest
.saturate
;
965 case nir_op_fddy_coarse
:
966 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
967 inst
->saturate
= instr
->dest
.saturate
;
972 inst
= bld
.ADD(result
, op
[0], op
[1]);
973 inst
->saturate
= instr
->dest
.saturate
;
977 inst
= bld
.MUL(result
, op
[0], op
[1]);
978 inst
->saturate
= instr
->dest
.saturate
;
982 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
983 bld
.MUL(result
, op
[0], op
[1]);
986 case nir_op_imul_high
:
987 case nir_op_umul_high
:
988 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
989 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
994 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
995 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
998 case nir_op_uadd_carry
:
999 unreachable("Should have been lowered by carry_to_arith().");
1001 case nir_op_usub_borrow
:
1002 unreachable("Should have been lowered by borrow_to_arith().");
1006 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1007 * appears that our hardware just does the right thing for signed
1010 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1011 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1015 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1016 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1018 /* Math instructions don't support conditional mod */
1019 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1020 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1022 /* Now, we need to determine if signs of the sources are different.
1023 * When we XOR the sources, the top bit is 0 if they are the same and 1
1024 * if they are different. We can then use a conditional modifier to
1025 * turn that into a predicate. This leads us to an XOR.l instruction.
1027 * Technically, according to the PRM, you're not allowed to use .l on a
1028 * XOR instruction. However, emperical experiments and Curro's reading
1029 * of the simulator source both indicate that it's safe.
1031 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1032 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1033 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1034 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1036 /* If the result of the initial remainder operation is non-zero and the
1037 * two sources have different signs, add in a copy of op[1] to get the
1038 * final integer modulus value.
1040 inst
= bld
.ADD(result
, result
, op
[1]);
1041 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1049 fs_reg dest
= result
;
1051 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1053 dest
= bld
.vgrf(op
[0].type
, 1);
1055 brw_conditional_mod cond
;
1056 switch (instr
->op
) {
1058 cond
= BRW_CONDITIONAL_L
;
1061 cond
= BRW_CONDITIONAL_GE
;
1064 cond
= BRW_CONDITIONAL_Z
;
1067 cond
= BRW_CONDITIONAL_NZ
;
1070 unreachable("bad opcode");
1073 bld
.CMP(dest
, op
[0], op
[1], cond
);
1075 if (bit_size
> 32) {
1076 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1077 } else if(bit_size
< 32) {
1078 /* When we convert the result to 32-bit we need to be careful and do
1079 * it as a signed conversion to get sign extension (for 32-bit true)
1081 const brw_reg_type src_type
=
1082 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1084 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1095 fs_reg dest
= result
;
1097 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1099 dest
= bld
.vgrf(op
[0].type
, 1);
1101 brw_conditional_mod cond
;
1102 switch (instr
->op
) {
1105 cond
= BRW_CONDITIONAL_L
;
1109 cond
= BRW_CONDITIONAL_GE
;
1112 cond
= BRW_CONDITIONAL_Z
;
1115 cond
= BRW_CONDITIONAL_NZ
;
1118 unreachable("bad opcode");
1120 bld
.CMP(dest
, op
[0], op
[1], cond
);
1122 if (bit_size
> 32) {
1123 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1124 } else if (bit_size
< 32) {
1125 /* When we convert the result to 32-bit we need to be careful and do
1126 * it as a signed conversion to get sign extension (for 32-bit true)
1128 const brw_reg_type src_type
=
1129 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1131 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1137 if (devinfo
->gen
>= 8) {
1138 op
[0] = resolve_source_modifiers(op
[0]);
1140 bld
.NOT(result
, op
[0]);
1143 if (devinfo
->gen
>= 8) {
1144 op
[0] = resolve_source_modifiers(op
[0]);
1145 op
[1] = resolve_source_modifiers(op
[1]);
1147 bld
.XOR(result
, op
[0], op
[1]);
1150 if (devinfo
->gen
>= 8) {
1151 op
[0] = resolve_source_modifiers(op
[0]);
1152 op
[1] = resolve_source_modifiers(op
[1]);
1154 bld
.OR(result
, op
[0], op
[1]);
1157 if (devinfo
->gen
>= 8) {
1158 op
[0] = resolve_source_modifiers(op
[0]);
1159 op
[1] = resolve_source_modifiers(op
[1]);
1161 bld
.AND(result
, op
[0], op
[1]);
1167 case nir_op_ball_fequal2
:
1168 case nir_op_ball_iequal2
:
1169 case nir_op_ball_fequal3
:
1170 case nir_op_ball_iequal3
:
1171 case nir_op_ball_fequal4
:
1172 case nir_op_ball_iequal4
:
1173 case nir_op_bany_fnequal2
:
1174 case nir_op_bany_inequal2
:
1175 case nir_op_bany_fnequal3
:
1176 case nir_op_bany_inequal3
:
1177 case nir_op_bany_fnequal4
:
1178 case nir_op_bany_inequal4
:
1179 unreachable("Lowered by nir_lower_alu_reductions");
1181 case nir_op_fnoise1_1
:
1182 case nir_op_fnoise1_2
:
1183 case nir_op_fnoise1_3
:
1184 case nir_op_fnoise1_4
:
1185 case nir_op_fnoise2_1
:
1186 case nir_op_fnoise2_2
:
1187 case nir_op_fnoise2_3
:
1188 case nir_op_fnoise2_4
:
1189 case nir_op_fnoise3_1
:
1190 case nir_op_fnoise3_2
:
1191 case nir_op_fnoise3_3
:
1192 case nir_op_fnoise3_4
:
1193 case nir_op_fnoise4_1
:
1194 case nir_op_fnoise4_2
:
1195 case nir_op_fnoise4_3
:
1196 case nir_op_fnoise4_4
:
1197 unreachable("not reached: should be handled by lower_noise");
1200 unreachable("not reached: should be handled by ldexp_to_arith()");
1203 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1204 inst
->saturate
= instr
->dest
.saturate
;
1208 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1209 inst
->saturate
= instr
->dest
.saturate
;
1214 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1215 if (bit_size
== 64) {
1216 /* two-argument instructions can't take 64-bit immediates */
1220 if (instr
->op
== nir_op_f2b
) {
1221 zero
= vgrf(glsl_type::double_type
);
1222 tmp
= vgrf(glsl_type::double_type
);
1223 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1225 zero
= vgrf(glsl_type::int64_t_type
);
1226 tmp
= vgrf(glsl_type::int64_t_type
);
1227 bld
.MOV(zero
, brw_imm_q(0));
1230 /* A SIMD16 execution needs to be split in two instructions, so use
1231 * a vgrf instead of the flag register as dst so instruction splitting
1234 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1235 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1238 if (bit_size
== 32) {
1239 zero
= instr
->op
== nir_op_f2b
? brw_imm_f(0.0f
) : brw_imm_d(0);
1241 assert(bit_size
== 16);
1242 zero
= instr
->op
== nir_op_f2b
?
1243 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1245 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1251 inst
= bld
.RNDZ(result
, op
[0]);
1252 inst
->saturate
= instr
->dest
.saturate
;
1255 case nir_op_fceil
: {
1256 op
[0].negate
= !op
[0].negate
;
1257 fs_reg temp
= vgrf(glsl_type::float_type
);
1258 bld
.RNDD(temp
, op
[0]);
1260 inst
= bld
.MOV(result
, temp
);
1261 inst
->saturate
= instr
->dest
.saturate
;
1265 inst
= bld
.RNDD(result
, op
[0]);
1266 inst
->saturate
= instr
->dest
.saturate
;
1269 inst
= bld
.FRC(result
, op
[0]);
1270 inst
->saturate
= instr
->dest
.saturate
;
1272 case nir_op_fround_even
:
1273 inst
= bld
.RNDE(result
, op
[0]);
1274 inst
->saturate
= instr
->dest
.saturate
;
1277 case nir_op_fquantize2f16
: {
1278 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1279 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1280 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1282 /* The destination stride must be at least as big as the source stride. */
1283 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1286 /* Check for denormal */
1287 fs_reg abs_src0
= op
[0];
1288 abs_src0
.abs
= true;
1289 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1291 /* Get the appropriately signed zero */
1292 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1293 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1294 brw_imm_ud(0x80000000));
1295 /* Do the actual F32 -> F16 -> F32 conversion */
1296 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1297 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1298 /* Select that or zero based on normal status */
1299 inst
= bld
.SEL(result
, zero
, tmp32
);
1300 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1301 inst
->saturate
= instr
->dest
.saturate
;
1308 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1309 inst
->saturate
= instr
->dest
.saturate
;
1315 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1316 inst
->saturate
= instr
->dest
.saturate
;
1319 case nir_op_pack_snorm_2x16
:
1320 case nir_op_pack_snorm_4x8
:
1321 case nir_op_pack_unorm_2x16
:
1322 case nir_op_pack_unorm_4x8
:
1323 case nir_op_unpack_snorm_2x16
:
1324 case nir_op_unpack_snorm_4x8
:
1325 case nir_op_unpack_unorm_2x16
:
1326 case nir_op_unpack_unorm_4x8
:
1327 case nir_op_unpack_half_2x16
:
1328 case nir_op_pack_half_2x16
:
1329 unreachable("not reached: should be handled by lower_packing_builtins");
1331 case nir_op_unpack_half_2x16_split_x
:
1332 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1333 inst
->saturate
= instr
->dest
.saturate
;
1335 case nir_op_unpack_half_2x16_split_y
:
1336 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1337 inst
->saturate
= instr
->dest
.saturate
;
1340 case nir_op_pack_64_2x32_split
:
1341 case nir_op_pack_32_2x16_split
:
1342 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1345 case nir_op_unpack_64_2x32_split_x
:
1346 case nir_op_unpack_64_2x32_split_y
: {
1347 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1348 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1350 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1354 case nir_op_unpack_32_2x16_split_x
:
1355 case nir_op_unpack_32_2x16_split_y
: {
1356 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1357 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1359 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1364 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1365 inst
->saturate
= instr
->dest
.saturate
;
1368 case nir_op_bitfield_reverse
:
1369 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1370 bld
.BFREV(result
, op
[0]);
1373 case nir_op_bit_count
:
1374 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1375 bld
.CBIT(result
, op
[0]);
1378 case nir_op_ufind_msb
: {
1379 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1380 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1384 case nir_op_ifind_msb
: {
1385 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1387 if (devinfo
->gen
< 7) {
1388 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1390 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1392 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1393 * count from the LSB side. If FBH didn't return an error
1394 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1395 * count into an LSB count.
1397 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1399 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1400 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1401 inst
->src
[0].negate
= true;
1406 case nir_op_find_lsb
:
1407 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1409 if (devinfo
->gen
< 7) {
1410 fs_reg temp
= vgrf(glsl_type::int_type
);
1412 /* (x & -x) generates a value that consists of only the LSB of x.
1413 * For all powers of 2, findMSB(y) == findLSB(y).
1415 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1416 fs_reg negated_src
= src
;
1418 /* One must be negated, and the other must be non-negated. It
1419 * doesn't matter which is which.
1421 negated_src
.negate
= true;
1424 bld
.AND(temp
, src
, negated_src
);
1425 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1427 bld
.FBL(result
, op
[0]);
1431 case nir_op_ubitfield_extract
:
1432 case nir_op_ibitfield_extract
:
1433 unreachable("should have been lowered");
1436 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1437 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1440 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1441 bld
.BFI1(result
, op
[0], op
[1]);
1444 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1445 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1448 case nir_op_bitfield_insert
:
1449 unreachable("not reached: should have been lowered");
1454 fs_reg shift_count
= op
[1];
1456 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1457 if (op
[1].file
== VGRF
&&
1458 (result
.type
== BRW_REGISTER_TYPE_Q
||
1459 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1460 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1461 BRW_REGISTER_TYPE_UD
);
1462 shift_count
.stride
= 2;
1463 bld
.MOV(shift_count
, op
[1]);
1467 switch (instr
->op
) {
1469 bld
.SHL(result
, op
[0], shift_count
);
1472 bld
.ASR(result
, op
[0], shift_count
);
1475 bld
.SHR(result
, op
[0], shift_count
);
1478 unreachable("not reached");
1483 case nir_op_pack_half_2x16_split
:
1484 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1488 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1489 inst
->saturate
= instr
->dest
.saturate
;
1493 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1494 inst
->saturate
= instr
->dest
.saturate
;
1498 if (optimize_frontfacing_ternary(instr
, result
))
1501 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1502 inst
= bld
.SEL(result
, op
[1], op
[2]);
1503 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1506 case nir_op_extract_u8
:
1507 case nir_op_extract_i8
: {
1508 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1513 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1514 * Use two instructions and a word or DWord intermediate integer type.
1516 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1517 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1519 if (instr
->op
== nir_op_extract_i8
) {
1520 /* If we need to sign extend, extract to a word first */
1521 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1522 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1523 bld
.MOV(result
, w_temp
);
1525 /* Otherwise use an AND with 0xff and a word type */
1526 bld
.AND(result
, subscript(op
[0], type
, byte
/ 2), brw_imm_uw(0xff));
1529 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1530 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1535 case nir_op_extract_u16
:
1536 case nir_op_extract_i16
: {
1537 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1538 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1539 bld
.MOV(result
, subscript(op
[0], type
, word
));
1544 unreachable("unhandled instruction");
1547 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1548 * to sign extend the low bit to 0/~0
1550 if (devinfo
->gen
<= 5 &&
1551 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1552 fs_reg masked
= vgrf(glsl_type::int_type
);
1553 bld
.AND(masked
, result
, brw_imm_d(1));
1554 masked
.negate
= true;
1555 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1560 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1561 nir_load_const_instr
*instr
)
1563 const brw_reg_type reg_type
=
1564 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1565 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1567 switch (instr
->def
.bit_size
) {
1569 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1570 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1574 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1575 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1579 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1580 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1584 assert(devinfo
->gen
>= 7);
1585 if (devinfo
->gen
== 7) {
1586 /* We don't get 64-bit integer types until gen8 */
1587 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1588 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1589 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1592 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1593 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1598 unreachable("Invalid bit size");
1601 nir_ssa_values
[instr
->def
.index
] = reg
;
1605 fs_visitor::get_nir_src(const nir_src
&src
)
1609 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1610 const brw_reg_type reg_type
=
1611 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1612 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1614 reg
= nir_ssa_values
[src
.ssa
->index
];
1617 /* We don't handle indirects on locals */
1618 assert(src
.reg
.indirect
== NULL
);
1619 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1620 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1623 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1624 /* The only 64-bit type available on gen7 is DF, so use that. */
1625 reg
.type
= BRW_REGISTER_TYPE_DF
;
1627 /* To avoid floating-point denorm flushing problems, set the type by
1628 * default to an integer type - instructions that need floating point
1629 * semantics will set this to F if they need to
1631 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1632 BRW_REGISTER_TYPE_D
);
1639 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1641 * This function should not be called on any value which may be 64 bits.
1642 * We could theoretically support 64-bit on gen8+ but we choose not to
1643 * because it wouldn't work in general (no gen7 support) and there are
1644 * enough restrictions in 64-bit immediates that you can't take the return
1645 * value and treat it the same as the result of get_nir_src().
1648 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1650 assert(nir_src_bit_size(src
) == 32);
1651 return nir_src_is_const(src
) ?
1652 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1656 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1659 const brw_reg_type reg_type
=
1660 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1661 dest
.ssa
.bit_size
== 8 ?
1662 BRW_REGISTER_TYPE_D
:
1663 BRW_REGISTER_TYPE_F
);
1664 nir_ssa_values
[dest
.ssa
.index
] =
1665 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1666 return nir_ssa_values
[dest
.ssa
.index
];
1668 /* We don't handle indirects on locals */
1669 assert(dest
.reg
.indirect
== NULL
);
1670 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1671 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1676 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1679 for (unsigned i
= 0; i
< 4; i
++) {
1680 if (!((wr_mask
>> i
) & 1))
1683 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1684 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1685 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1686 if (new_inst
->src
[j
].file
== VGRF
)
1687 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1694 emit_pixel_interpolater_send(const fs_builder
&bld
,
1699 glsl_interp_mode interpolation
)
1701 struct brw_wm_prog_data
*wm_prog_data
=
1702 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1704 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1705 /* 2 floats per slot returned */
1706 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1707 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1709 wm_prog_data
->pulls_bary
= true;
1715 * Computes 1 << x, given a D/UD register containing some value x.
1718 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1720 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1722 fs_reg result
= bld
.vgrf(x
.type
, 1);
1723 fs_reg one
= bld
.vgrf(x
.type
, 1);
1725 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1726 bld
.SHL(result
, one
, x
);
1731 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1733 assert(stage
== MESA_SHADER_GEOMETRY
);
1735 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1737 if (gs_compile
->control_data_header_size_bits
== 0)
1740 /* We can only do EndPrimitive() functionality when the control data
1741 * consists of cut bits. Fortunately, the only time it isn't is when the
1742 * output type is points, in which case EndPrimitive() is a no-op.
1744 if (gs_prog_data
->control_data_format
!=
1745 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1749 /* Cut bits use one bit per vertex. */
1750 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1752 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1753 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1755 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1756 * vertex n, 0 otherwise. So all we need to do here is mark bit
1757 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1758 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1759 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1761 * Note that if EndPrimitive() is called before emitting any vertices, this
1762 * will cause us to set bit 31 of the control_data_bits register to 1.
1763 * That's fine because:
1765 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1766 * output, so the hardware will ignore cut bit 31.
1768 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1769 * last vertex, so setting cut bit 31 has no effect (since the primitive
1770 * is automatically ended when the GS terminates).
1772 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1773 * control_data_bits register to 0 when the first vertex is emitted.
1776 const fs_builder abld
= bld
.annotate("end primitive");
1778 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1779 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1780 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1781 fs_reg mask
= intexp2(abld
, prev_count
);
1782 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1783 * attention to the lower 5 bits of its second source argument, so on this
1784 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1785 * ((vertex_count - 1) % 32).
1787 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1791 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1793 assert(stage
== MESA_SHADER_GEOMETRY
);
1794 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1796 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1798 const fs_builder abld
= bld
.annotate("emit control data bits");
1799 const fs_builder fwa_bld
= bld
.exec_all();
1801 /* We use a single UD register to accumulate control data bits (32 bits
1802 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1805 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1806 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1807 * use the Channel Mask phase to enable/disable which DWord within that
1808 * group to write. (Remember, different SIMD8 channels may have emitted
1809 * different numbers of vertices, so we may need per-slot offsets.)
1811 * Channel masking presents an annoying problem: we may have to replicate
1812 * the data up to 4 times:
1814 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1816 * To avoid penalizing shaders that emit a small number of vertices, we
1817 * can avoid these sometimes: if the size of the control data header is
1818 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1819 * land in the same 128-bit group, so we can skip per-slot offsets.
1821 * Similarly, if the control data header is <= 32 bits, there is only one
1822 * DWord, so we can skip channel masks.
1824 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1826 fs_reg channel_mask
, per_slot_offset
;
1828 if (gs_compile
->control_data_header_size_bits
> 32) {
1829 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1830 channel_mask
= vgrf(glsl_type::uint_type
);
1833 if (gs_compile
->control_data_header_size_bits
> 128) {
1834 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1835 per_slot_offset
= vgrf(glsl_type::uint_type
);
1838 /* Figure out which DWord we're trying to write to using the formula:
1840 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1842 * Since bits_per_vertex is a power of two, and is known at compile
1843 * time, this can be optimized to:
1845 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1847 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1848 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1849 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1850 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1851 unsigned log2_bits_per_vertex
=
1852 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1853 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1855 if (per_slot_offset
.file
!= BAD_FILE
) {
1856 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1857 * the appropriate OWord within the control data header.
1859 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1862 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1863 * write to the appropriate DWORD within the OWORD.
1865 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1866 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1867 channel_mask
= intexp2(fwa_bld
, channel
);
1868 /* Then the channel masks need to be in bits 23:16. */
1869 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1872 /* Store the control data bits in the message payload and send it. */
1874 if (channel_mask
.file
!= BAD_FILE
)
1875 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1876 if (per_slot_offset
.file
!= BAD_FILE
)
1879 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1880 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1882 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1883 if (per_slot_offset
.file
!= BAD_FILE
)
1884 sources
[i
++] = per_slot_offset
;
1885 if (channel_mask
.file
!= BAD_FILE
)
1886 sources
[i
++] = channel_mask
;
1888 sources
[i
++] = this->control_data_bits
;
1891 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1892 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1894 /* We need to increment Global Offset by 256-bits to make room for
1895 * Broadwell's extra "Vertex Count" payload at the beginning of the
1896 * URB entry. Since this is an OWord message, Global Offset is counted
1897 * in 128-bit units, so we must set it to 2.
1899 if (gs_prog_data
->static_vertex_count
== -1)
1904 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1907 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1909 /* Note: we are calling this *before* increasing vertex_count, so
1910 * this->vertex_count == vertex_count - 1 in the formula above.
1913 /* Stream mode uses 2 bits per vertex */
1914 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1916 /* Must be a valid stream */
1917 assert(stream_id
< MAX_VERTEX_STREAMS
);
1919 /* Control data bits are initialized to 0 so we don't have to set any
1920 * bits when sending vertices to stream 0.
1925 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1927 /* reg::sid = stream_id */
1928 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1929 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1931 /* reg:shift_count = 2 * (vertex_count - 1) */
1932 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1933 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1935 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1936 * attention to the lower 5 bits of its second source argument, so on this
1937 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1938 * stream_id << ((2 * (vertex_count - 1)) % 32).
1940 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1941 abld
.SHL(mask
, sid
, shift_count
);
1942 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1946 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1949 assert(stage
== MESA_SHADER_GEOMETRY
);
1951 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1953 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1954 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1956 /* Haswell and later hardware ignores the "Render Stream Select" bits
1957 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1958 * and instead sends all primitives down the pipeline for rasterization.
1959 * If the SOL stage is enabled, "Render Stream Select" is honored and
1960 * primitives bound to non-zero streams are discarded after stream output.
1962 * Since the only purpose of primives sent to non-zero streams is to
1963 * be recorded by transform feedback, we can simply discard all geometry
1964 * bound to these streams when transform feedback is disabled.
1966 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1969 /* If we're outputting 32 control data bits or less, then we can wait
1970 * until the shader is over to output them all. Otherwise we need to
1971 * output them as we go. Now is the time to do it, since we're about to
1972 * output the vertex_count'th vertex, so it's guaranteed that the
1973 * control data bits associated with the (vertex_count - 1)th vertex are
1976 if (gs_compile
->control_data_header_size_bits
> 32) {
1977 const fs_builder abld
=
1978 bld
.annotate("emit vertex: emit control data bits");
1980 /* Only emit control data bits if we've finished accumulating a batch
1981 * of 32 bits. This is the case when:
1983 * (vertex_count * bits_per_vertex) % 32 == 0
1985 * (in other words, when the last 5 bits of vertex_count *
1986 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1987 * integer n (which is always the case, since bits_per_vertex is
1988 * always 1 or 2), this is equivalent to requiring that the last 5-n
1989 * bits of vertex_count are 0:
1991 * vertex_count & (2^(5-n) - 1) == 0
1993 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1996 * vertex_count & (32 / bits_per_vertex - 1) == 0
1998 * TODO: If vertex_count is an immediate, we could do some of this math
1999 * at compile time...
2002 abld
.AND(bld
.null_reg_d(), vertex_count
,
2003 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2004 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2006 abld
.IF(BRW_PREDICATE_NORMAL
);
2007 /* If vertex_count is 0, then no control data bits have been
2008 * accumulated yet, so we can skip emitting them.
2010 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2011 BRW_CONDITIONAL_NEQ
);
2012 abld
.IF(BRW_PREDICATE_NORMAL
);
2013 emit_gs_control_data_bits(vertex_count
);
2014 abld
.emit(BRW_OPCODE_ENDIF
);
2016 /* Reset control_data_bits to 0 so we can start accumulating a new
2019 * Note: in the case where vertex_count == 0, this neutralizes the
2020 * effect of any call to EndPrimitive() that the shader may have
2021 * made before outputting its first vertex.
2023 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2024 inst
->force_writemask_all
= true;
2025 abld
.emit(BRW_OPCODE_ENDIF
);
2028 emit_urb_writes(vertex_count
);
2030 /* In stream mode we have to set control data bits for all vertices
2031 * unless we have disabled control data bits completely (which we do
2032 * do for GL_POINTS outputs that don't use streams).
2034 if (gs_compile
->control_data_header_size_bits
> 0 &&
2035 gs_prog_data
->control_data_format
==
2036 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2037 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2042 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2043 const nir_src
&vertex_src
,
2044 unsigned base_offset
,
2045 const nir_src
&offset_src
,
2046 unsigned num_components
,
2047 unsigned first_component
)
2049 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2050 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2052 /* TODO: figure out push input layout for invocations == 1 */
2053 /* TODO: make this work with 64-bit inputs */
2054 if (gs_prog_data
->invocations
== 1 &&
2055 type_sz(dst
.type
) <= 4 &&
2056 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2057 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2058 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2059 nir_src_as_uint(vertex_src
) * push_reg_count
;
2060 for (unsigned i
= 0; i
< num_components
; i
++) {
2061 bld
.MOV(offset(dst
, bld
, i
),
2062 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2067 /* Resort to the pull model. Ensure the VUE handles are provided. */
2068 assert(gs_prog_data
->base
.include_vue_handles
);
2070 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2071 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2073 if (gs_prog_data
->invocations
== 1) {
2074 if (nir_src_is_const(vertex_src
)) {
2075 /* The vertex index is constant; just select the proper URB handle. */
2077 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2078 BRW_REGISTER_TYPE_UD
);
2080 /* The vertex index is non-constant. We need to use indirect
2081 * addressing to fetch the proper URB handle.
2083 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2084 * indicating that channel <n> should read the handle from
2085 * DWord <n>. We convert that to bytes by multiplying by 4.
2087 * Next, we convert the vertex index to bytes by multiplying
2088 * by 32 (shifting by 5), and add the two together. This is
2089 * the final indirect byte offset.
2091 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2092 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2093 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2094 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2096 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2097 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2098 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2099 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2100 /* Convert vertex_index to bytes (multiply by 32) */
2101 bld
.SHL(vertex_offset_bytes
,
2102 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2104 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2106 /* Use first_icp_handle as the base offset. There is one register
2107 * of URB handles per vertex, so inform the register allocator that
2108 * we might read up to nir->info.gs.vertices_in registers.
2110 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2111 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2112 fs_reg(icp_offset_bytes
),
2113 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2116 assert(gs_prog_data
->invocations
> 1);
2118 if (nir_src_is_const(vertex_src
)) {
2119 unsigned vertex
= nir_src_as_uint(vertex_src
);
2120 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2122 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2123 BRW_REGISTER_TYPE_UD
));
2125 /* The vertex index is non-constant. We need to use indirect
2126 * addressing to fetch the proper URB handle.
2129 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2131 /* Convert vertex_index to bytes (multiply by 4) */
2132 bld
.SHL(icp_offset_bytes
,
2133 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2136 /* Use first_icp_handle as the base offset. There is one DWord
2137 * of URB handles per vertex, so inform the register allocator that
2138 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2140 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2141 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2142 fs_reg(icp_offset_bytes
),
2143 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2150 fs_reg tmp_dst
= dst
;
2151 fs_reg indirect_offset
= get_nir_src(offset_src
);
2152 unsigned num_iterations
= 1;
2153 unsigned orig_num_components
= num_components
;
2155 if (type_sz(dst
.type
) == 8) {
2156 if (num_components
> 2) {
2160 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2162 first_component
= first_component
/ 2;
2165 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2166 if (nir_src_is_const(offset_src
)) {
2167 /* Constant indexing - use global offset. */
2168 if (first_component
!= 0) {
2169 unsigned read_components
= num_components
+ first_component
;
2170 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2171 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2172 inst
->size_written
= read_components
*
2173 tmp
.component_size(inst
->exec_size
);
2174 for (unsigned i
= 0; i
< num_components
; i
++) {
2175 bld
.MOV(offset(tmp_dst
, bld
, i
),
2176 offset(tmp
, bld
, i
+ first_component
));
2179 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2181 inst
->size_written
= num_components
*
2182 tmp_dst
.component_size(inst
->exec_size
);
2184 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2187 /* Indirect indexing - use per-slot offsets as well. */
2188 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2189 unsigned read_components
= num_components
+ first_component
;
2190 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2191 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2192 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2193 if (first_component
!= 0) {
2194 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2196 inst
->size_written
= read_components
*
2197 tmp
.component_size(inst
->exec_size
);
2198 for (unsigned i
= 0; i
< num_components
; i
++) {
2199 bld
.MOV(offset(tmp_dst
, bld
, i
),
2200 offset(tmp
, bld
, i
+ first_component
));
2203 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2205 inst
->size_written
= num_components
*
2206 tmp_dst
.component_size(inst
->exec_size
);
2208 inst
->offset
= base_offset
;
2212 if (type_sz(dst
.type
) == 8) {
2213 shuffle_from_32bit_read(bld
,
2214 offset(dst
, bld
, iter
* 2),
2215 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2220 if (num_iterations
> 1) {
2221 num_components
= orig_num_components
- 2;
2222 if(nir_src_is_const(offset_src
)) {
2225 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2226 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2227 indirect_offset
= new_indirect
;
2234 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2236 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2238 if (nir_src_is_const(*offset_src
)) {
2239 /* The only constant offset we should find is 0. brw_nir.c's
2240 * add_const_offset_to_base() will fold other constant offsets
2241 * into instr->const_index[0].
2243 assert(nir_src_as_uint(*offset_src
) == 0);
2247 return get_nir_src(*offset_src
);
2251 do_untyped_vector_read(const fs_builder
&bld
,
2253 const fs_reg surf_index
,
2254 const fs_reg offset_reg
,
2255 unsigned num_components
)
2257 if (type_sz(dest
.type
) <= 2) {
2258 assert(dest
.stride
== 1);
2259 boolean is_const_offset
= offset_reg
.file
== BRW_IMMEDIATE_VALUE
;
2261 if (is_const_offset
) {
2262 uint32_t start
= offset_reg
.ud
& ~3;
2263 uint32_t end
= offset_reg
.ud
+ num_components
* type_sz(dest
.type
);
2264 end
= ALIGN(end
, 4);
2265 assert (end
- start
<= 16);
2267 /* At this point we have 16-bit component/s that have constant
2268 * offset aligned to 4-bytes that can be read with untyped_reads.
2269 * untyped_read message requires 32-bit aligned offsets.
2271 unsigned first_component
= (offset_reg
.ud
& 3) / type_sz(dest
.type
);
2272 unsigned num_components_32bit
= (end
- start
) / 4;
2274 fs_reg read_result
=
2275 emit_untyped_read(bld
, surf_index
, brw_imm_ud(start
),
2277 num_components_32bit
,
2278 BRW_PREDICATE_NONE
);
2279 shuffle_from_32bit_read(bld
, dest
, read_result
, first_component
,
2282 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2283 for (unsigned i
= 0; i
< num_components
; i
++) {
2285 bld
.MOV(read_offset
, offset_reg
);
2287 bld
.ADD(read_offset
, offset_reg
,
2288 brw_imm_ud(i
* type_sz(dest
.type
)));
2290 /* Non constant offsets are not guaranteed to be aligned 32-bits
2291 * so they are read using one byte_scattered_read message
2292 * for each component.
2294 fs_reg read_result
=
2295 emit_byte_scattered_read(bld
, surf_index
, read_offset
,
2297 type_sz(dest
.type
) * 8 /* bit_size */,
2298 BRW_PREDICATE_NONE
);
2299 bld
.MOV(offset(dest
, bld
, i
),
2300 subscript (read_result
, dest
.type
, 0));
2303 } else if (type_sz(dest
.type
) == 4) {
2304 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2307 BRW_PREDICATE_NONE
);
2308 read_result
.type
= dest
.type
;
2309 for (unsigned i
= 0; i
< num_components
; i
++)
2310 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2311 } else if (type_sz(dest
.type
) == 8) {
2312 /* Reading a dvec, so we need to:
2314 * 1. Multiply num_components by 2, to account for the fact that we
2315 * need to read 64-bit components.
2316 * 2. Shuffle the result of the load to form valid 64-bit elements
2317 * 3. Emit a second load (for components z/w) if needed.
2319 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2320 bld
.MOV(read_offset
, offset_reg
);
2322 int iters
= num_components
<= 2 ? 1 : 2;
2324 /* Load the dvec, the first iteration loads components x/y, the second
2325 * iteration, if needed, loads components z/w
2327 for (int it
= 0; it
< iters
; it
++) {
2328 /* Compute number of components to read in this iteration */
2329 int iter_components
= MIN2(2, num_components
);
2330 num_components
-= iter_components
;
2332 /* Read. Since this message reads 32-bit components, we need to
2333 * read twice as many components.
2335 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2337 iter_components
* 2,
2338 BRW_PREDICATE_NONE
);
2340 /* Shuffle the 32-bit load result into valid 64-bit data */
2341 shuffle_from_32bit_read(bld
, offset(dest
, bld
, it
* 2),
2342 read_result
, 0, iter_components
);
2344 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2347 unreachable("Unsupported type");
2352 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2353 nir_intrinsic_instr
*instr
)
2355 assert(stage
== MESA_SHADER_VERTEX
);
2358 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2359 dest
= get_nir_dest(instr
->dest
);
2361 switch (instr
->intrinsic
) {
2362 case nir_intrinsic_load_vertex_id
:
2363 case nir_intrinsic_load_base_vertex
:
2364 unreachable("should be lowered by nir_lower_system_values()");
2366 case nir_intrinsic_load_input
: {
2367 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2368 unsigned first_component
= nir_intrinsic_component(instr
);
2369 unsigned num_components
= instr
->num_components
;
2371 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2373 if (type_sz(dest
.type
) == 8)
2374 first_component
/= 2;
2376 /* For 16-bit support maybe a temporary will be needed to copy from
2379 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2380 first_component
, num_components
);
2384 case nir_intrinsic_load_vertex_id_zero_base
:
2385 case nir_intrinsic_load_instance_id
:
2386 case nir_intrinsic_load_base_instance
:
2387 case nir_intrinsic_load_draw_id
:
2388 case nir_intrinsic_load_first_vertex
:
2389 case nir_intrinsic_load_is_indexed_draw
:
2390 unreachable("lowered by brw_nir_lower_vs_inputs");
2393 nir_emit_intrinsic(bld
, instr
);
2399 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2400 nir_intrinsic_instr
*instr
)
2402 assert(stage
== MESA_SHADER_TESS_CTRL
);
2403 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2404 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2407 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2408 dst
= get_nir_dest(instr
->dest
);
2410 switch (instr
->intrinsic
) {
2411 case nir_intrinsic_load_primitive_id
:
2412 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2414 case nir_intrinsic_load_invocation_id
:
2415 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2417 case nir_intrinsic_load_patch_vertices_in
:
2418 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2419 brw_imm_d(tcs_key
->input_vertices
));
2422 case nir_intrinsic_barrier
: {
2423 if (tcs_prog_data
->instances
== 1)
2426 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2427 fs_reg m0_2
= component(m0
, 2);
2429 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2431 /* Zero the message header */
2432 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2434 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2435 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2436 brw_imm_ud(INTEL_MASK(16, 13)));
2438 /* Shift it up to bits 27:24. */
2439 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2441 /* Set the Barrier Count and the enable bit */
2442 chanbld
.OR(m0_2
, m0_2
,
2443 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2445 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2449 case nir_intrinsic_load_input
:
2450 unreachable("nir_lower_io should never give us these.");
2453 case nir_intrinsic_load_per_vertex_input
: {
2454 fs_reg indirect_offset
= get_indirect_offset(instr
);
2455 unsigned imm_offset
= instr
->const_index
[0];
2457 const nir_src
&vertex_src
= instr
->src
[0];
2463 if (nir_src_is_const(vertex_src
)) {
2464 /* Emit a MOV to resolve <0,1,0> regioning. */
2465 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2466 unsigned vertex
= nir_src_as_uint(vertex_src
);
2468 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2469 BRW_REGISTER_TYPE_UD
));
2470 } else if (tcs_prog_data
->instances
== 1 &&
2471 vertex_src
.is_ssa
&&
2472 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2473 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2474 /* For the common case of only 1 instance, an array index of
2475 * gl_InvocationID means reading g1. Skip all the indirect work.
2477 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2479 /* The vertex index is non-constant. We need to use indirect
2480 * addressing to fetch the proper URB handle.
2482 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2484 /* Each ICP handle is a single DWord (4 bytes) */
2485 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2486 bld
.SHL(vertex_offset_bytes
,
2487 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2490 /* Start at g1. We might read up to 4 registers. */
2491 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2492 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2493 brw_imm_ud(4 * REG_SIZE
));
2496 /* We can only read two double components with each URB read, so
2497 * we send two read messages in that case, each one loading up to
2498 * two double components.
2500 unsigned num_iterations
= 1;
2501 unsigned num_components
= instr
->num_components
;
2502 unsigned first_component
= nir_intrinsic_component(instr
);
2503 fs_reg orig_dst
= dst
;
2504 if (type_sz(dst
.type
) == 8) {
2505 first_component
= first_component
/ 2;
2506 if (instr
->num_components
> 2) {
2511 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2515 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2516 if (indirect_offset
.file
== BAD_FILE
) {
2517 /* Constant indexing - use global offset. */
2518 if (first_component
!= 0) {
2519 unsigned read_components
= num_components
+ first_component
;
2520 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2521 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2522 for (unsigned i
= 0; i
< num_components
; i
++) {
2523 bld
.MOV(offset(dst
, bld
, i
),
2524 offset(tmp
, bld
, i
+ first_component
));
2527 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2529 inst
->offset
= imm_offset
;
2532 /* Indirect indexing - use per-slot offsets as well. */
2533 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2534 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2535 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2536 if (first_component
!= 0) {
2537 unsigned read_components
= num_components
+ first_component
;
2538 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2539 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2541 for (unsigned i
= 0; i
< num_components
; i
++) {
2542 bld
.MOV(offset(dst
, bld
, i
),
2543 offset(tmp
, bld
, i
+ first_component
));
2546 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2549 inst
->offset
= imm_offset
;
2552 inst
->size_written
= (num_components
+ first_component
) *
2553 inst
->dst
.component_size(inst
->exec_size
);
2555 /* If we are reading 64-bit data using 32-bit read messages we need
2556 * build proper 64-bit data elements by shuffling the low and high
2557 * 32-bit components around like we do for other things like UBOs
2560 if (type_sz(dst
.type
) == 8) {
2561 shuffle_from_32bit_read(bld
,
2562 offset(orig_dst
, bld
, iter
* 2),
2563 retype(dst
, BRW_REGISTER_TYPE_D
),
2567 /* Copy the temporary to the destination to deal with writemasking.
2569 * Also attempt to deal with gl_PointSize being in the .w component.
2571 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2572 assert(type_sz(dst
.type
) < 8);
2573 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2574 inst
->size_written
= 4 * REG_SIZE
;
2575 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2578 /* If we are loading double data and we need a second read message
2579 * adjust the write offset
2581 if (num_iterations
> 1) {
2582 num_components
= instr
->num_components
- 2;
2589 case nir_intrinsic_load_output
:
2590 case nir_intrinsic_load_per_vertex_output
: {
2591 fs_reg indirect_offset
= get_indirect_offset(instr
);
2592 unsigned imm_offset
= instr
->const_index
[0];
2593 unsigned first_component
= nir_intrinsic_component(instr
);
2596 if (indirect_offset
.file
== BAD_FILE
) {
2597 /* Replicate the patch handle to all enabled channels */
2598 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2599 bld
.MOV(patch_handle
,
2600 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2603 if (first_component
!= 0) {
2604 unsigned read_components
=
2605 instr
->num_components
+ first_component
;
2606 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2607 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2609 inst
->size_written
= read_components
* REG_SIZE
;
2610 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2611 bld
.MOV(offset(dst
, bld
, i
),
2612 offset(tmp
, bld
, i
+ first_component
));
2615 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2617 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2619 inst
->offset
= imm_offset
;
2623 /* Indirect indexing - use per-slot offsets as well. */
2624 const fs_reg srcs
[] = {
2625 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2628 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2629 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2630 if (first_component
!= 0) {
2631 unsigned read_components
=
2632 instr
->num_components
+ first_component
;
2633 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2634 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2636 inst
->size_written
= read_components
* REG_SIZE
;
2637 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2638 bld
.MOV(offset(dst
, bld
, i
),
2639 offset(tmp
, bld
, i
+ first_component
));
2642 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2644 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2646 inst
->offset
= imm_offset
;
2652 case nir_intrinsic_store_output
:
2653 case nir_intrinsic_store_per_vertex_output
: {
2654 fs_reg value
= get_nir_src(instr
->src
[0]);
2655 bool is_64bit
= (instr
->src
[0].is_ssa
?
2656 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2657 fs_reg indirect_offset
= get_indirect_offset(instr
);
2658 unsigned imm_offset
= instr
->const_index
[0];
2659 unsigned mask
= instr
->const_index
[1];
2660 unsigned header_regs
= 0;
2662 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2664 if (indirect_offset
.file
!= BAD_FILE
) {
2665 srcs
[header_regs
++] = indirect_offset
;
2671 unsigned num_components
= util_last_bit(mask
);
2674 /* We can only pack two 64-bit components in a single message, so send
2675 * 2 messages if we have more components
2677 unsigned num_iterations
= 1;
2678 unsigned iter_components
= num_components
;
2679 unsigned first_component
= nir_intrinsic_component(instr
);
2681 first_component
= first_component
/ 2;
2682 if (instr
->num_components
> 2) {
2684 iter_components
= 2;
2688 mask
= mask
<< first_component
;
2690 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2691 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2692 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2693 opcode
= indirect_offset
.file
!= BAD_FILE
?
2694 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2695 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2696 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2697 /* Expand the 64-bit mask to 32-bit channels. We only handle
2698 * two channels in each iteration, so we only care about X/Y.
2700 unsigned mask32
= 0;
2701 if (mask
& WRITEMASK_X
)
2702 mask32
|= WRITEMASK_XY
;
2703 if (mask
& WRITEMASK_Y
)
2704 mask32
|= WRITEMASK_ZW
;
2706 /* If the mask does not include any of the channels X or Y there
2707 * is nothing to do in this iteration. Move on to the next couple
2708 * of 64-bit channels.
2716 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2717 opcode
= indirect_offset
.file
!= BAD_FILE
?
2718 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2719 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2721 opcode
= indirect_offset
.file
!= BAD_FILE
?
2722 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2723 SHADER_OPCODE_URB_WRITE_SIMD8
;
2726 for (unsigned i
= 0; i
< iter_components
; i
++) {
2727 if (!(mask
& (1 << (i
+ first_component
))))
2731 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2733 /* We need to shuffle the 64-bit data to match the layout
2734 * expected by our 32-bit URB write messages. We use a temporary
2737 unsigned channel
= iter
* 2 + i
;
2738 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2740 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2741 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2742 offset(dest
, bld
, 1);
2747 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2748 (is_64bit
? 2 * first_component
: first_component
);
2750 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2751 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2753 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2754 inst
->offset
= imm_offset
;
2757 /* If this is a 64-bit attribute, select the next two 64-bit channels
2758 * to be handled in the next iteration.
2769 nir_emit_intrinsic(bld
, instr
);
2775 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2776 nir_intrinsic_instr
*instr
)
2778 assert(stage
== MESA_SHADER_TESS_EVAL
);
2779 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2782 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2783 dest
= get_nir_dest(instr
->dest
);
2785 switch (instr
->intrinsic
) {
2786 case nir_intrinsic_load_primitive_id
:
2787 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2789 case nir_intrinsic_load_tess_coord
:
2790 /* gl_TessCoord is part of the payload in g1-3 */
2791 for (unsigned i
= 0; i
< 3; i
++) {
2792 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2796 case nir_intrinsic_load_input
:
2797 case nir_intrinsic_load_per_vertex_input
: {
2798 fs_reg indirect_offset
= get_indirect_offset(instr
);
2799 unsigned imm_offset
= instr
->const_index
[0];
2800 unsigned first_component
= nir_intrinsic_component(instr
);
2802 if (type_sz(dest
.type
) == 8) {
2803 first_component
= first_component
/ 2;
2807 if (indirect_offset
.file
== BAD_FILE
) {
2808 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2809 * which is 16 registers (since each holds 2 vec4 slots).
2811 unsigned slot_count
= 1;
2812 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2815 const unsigned max_push_slots
= 32;
2816 if (imm_offset
+ slot_count
<= max_push_slots
) {
2817 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2818 for (int i
= 0; i
< instr
->num_components
; i
++) {
2819 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2820 i
+ first_component
;
2821 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2824 tes_prog_data
->base
.urb_read_length
=
2825 MAX2(tes_prog_data
->base
.urb_read_length
,
2826 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2828 /* Replicate the patch handle to all enabled channels */
2829 const fs_reg srcs
[] = {
2830 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2832 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2833 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2835 if (first_component
!= 0) {
2836 unsigned read_components
=
2837 instr
->num_components
+ first_component
;
2838 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2839 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2841 inst
->size_written
= read_components
* REG_SIZE
;
2842 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2843 bld
.MOV(offset(dest
, bld
, i
),
2844 offset(tmp
, bld
, i
+ first_component
));
2847 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2849 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2852 inst
->offset
= imm_offset
;
2855 /* Indirect indexing - use per-slot offsets as well. */
2857 /* We can only read two double components with each URB read, so
2858 * we send two read messages in that case, each one loading up to
2859 * two double components.
2861 unsigned num_iterations
= 1;
2862 unsigned num_components
= instr
->num_components
;
2863 fs_reg orig_dest
= dest
;
2864 if (type_sz(dest
.type
) == 8) {
2865 if (instr
->num_components
> 2) {
2869 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2873 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2874 const fs_reg srcs
[] = {
2875 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2878 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2879 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2881 if (first_component
!= 0) {
2882 unsigned read_components
=
2883 num_components
+ first_component
;
2884 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2885 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2887 for (unsigned i
= 0; i
< num_components
; i
++) {
2888 bld
.MOV(offset(dest
, bld
, i
),
2889 offset(tmp
, bld
, i
+ first_component
));
2892 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2896 inst
->offset
= imm_offset
;
2897 inst
->size_written
= (num_components
+ first_component
) *
2898 inst
->dst
.component_size(inst
->exec_size
);
2900 /* If we are reading 64-bit data using 32-bit read messages we need
2901 * build proper 64-bit data elements by shuffling the low and high
2902 * 32-bit components around like we do for other things like UBOs
2905 if (type_sz(dest
.type
) == 8) {
2906 shuffle_from_32bit_read(bld
,
2907 offset(orig_dest
, bld
, iter
* 2),
2908 retype(dest
, BRW_REGISTER_TYPE_D
),
2912 /* If we are loading double data and we need a second read message
2915 if (num_iterations
> 1) {
2916 num_components
= instr
->num_components
- 2;
2924 nir_emit_intrinsic(bld
, instr
);
2930 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2931 nir_intrinsic_instr
*instr
)
2933 assert(stage
== MESA_SHADER_GEOMETRY
);
2934 fs_reg indirect_offset
;
2937 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2938 dest
= get_nir_dest(instr
->dest
);
2940 switch (instr
->intrinsic
) {
2941 case nir_intrinsic_load_primitive_id
:
2942 assert(stage
== MESA_SHADER_GEOMETRY
);
2943 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2944 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2945 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2948 case nir_intrinsic_load_input
:
2949 unreachable("load_input intrinsics are invalid for the GS stage");
2951 case nir_intrinsic_load_per_vertex_input
:
2952 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2953 instr
->src
[1], instr
->num_components
,
2954 nir_intrinsic_component(instr
));
2957 case nir_intrinsic_emit_vertex_with_counter
:
2958 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2961 case nir_intrinsic_end_primitive_with_counter
:
2962 emit_gs_end_primitive(instr
->src
[0]);
2965 case nir_intrinsic_set_vertex_count
:
2966 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2969 case nir_intrinsic_load_invocation_id
: {
2970 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2971 assert(val
.file
!= BAD_FILE
);
2972 dest
.type
= val
.type
;
2978 nir_emit_intrinsic(bld
, instr
);
2984 * Fetch the current render target layer index.
2987 fetch_render_target_array_index(const fs_builder
&bld
)
2989 if (bld
.shader
->devinfo
->gen
>= 6) {
2990 /* The render target array index is provided in the thread payload as
2991 * bits 26:16 of r0.0.
2993 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2994 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2998 /* Pre-SNB we only ever render into the first layer of the framebuffer
2999 * since layered rendering is not implemented.
3001 return brw_imm_ud(0);
3006 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3007 * framebuffer at the current fragment coordinates and sample index.
3010 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3013 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3015 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3016 const brw_wm_prog_key
*wm_key
=
3017 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3018 assert(!wm_key
->coherent_fb_fetch
);
3019 const struct brw_wm_prog_data
*wm_prog_data
=
3020 brw_wm_prog_data(stage_prog_data
);
3022 /* Calculate the surface index relative to the start of the texture binding
3023 * table block, since that's what the texturing messages expect.
3025 const unsigned surface
= target
+
3026 wm_prog_data
->binding_table
.render_target_read_start
-
3027 wm_prog_data
->base
.binding_table
.texture_start
;
3029 brw_mark_surface_used(
3030 bld
.shader
->stage_prog_data
,
3031 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3033 /* Calculate the fragment coordinates. */
3034 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3035 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3036 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3037 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3039 /* Calculate the sample index and MCS payload when multisampling. Luckily
3040 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3041 * shouldn't be necessary to recompile based on whether the framebuffer is
3044 if (wm_key
->multisample_fbo
&&
3045 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3046 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3048 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3049 const fs_reg mcs
= wm_key
->multisample_fbo
?
3050 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3052 /* Use either a normal or a CMS texel fetch message depending on whether
3053 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3054 * message just in case the framebuffer uses 16x multisampling, it should
3055 * be equivalent to the normal CMS fetch for lower multisampling modes.
3057 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3058 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3059 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3061 /* Emit the instruction. */
3062 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3064 brw_imm_ud(surface
), brw_imm_ud(0),
3065 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3066 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3068 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3069 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3075 * Actual coherent framebuffer read implemented using the native render target
3076 * read message. Requires SKL+.
3079 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3081 assert(bld
.shader
->devinfo
->gen
>= 9);
3082 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3083 inst
->target
= target
;
3084 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3090 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3092 if (n
&& regs
[0].file
!= BAD_FILE
) {
3096 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3098 for (unsigned i
= 0; i
< n
; i
++)
3106 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3108 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3109 const brw_wm_prog_key
*const key
=
3110 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3111 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3112 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3114 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3115 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3117 else if (l
== FRAG_RESULT_COLOR
)
3118 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3119 MAX2(key
->nr_color_regions
, 1));
3121 else if (l
== FRAG_RESULT_DEPTH
)
3122 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3124 else if (l
== FRAG_RESULT_STENCIL
)
3125 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3127 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3128 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3130 else if (l
>= FRAG_RESULT_DATA0
&&
3131 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3132 return alloc_temporary(v
->bld
, 4,
3133 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3136 unreachable("Invalid location");
3140 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3141 nir_intrinsic_instr
*instr
)
3143 assert(stage
== MESA_SHADER_FRAGMENT
);
3146 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3147 dest
= get_nir_dest(instr
->dest
);
3149 switch (instr
->intrinsic
) {
3150 case nir_intrinsic_load_front_face
:
3151 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3152 *emit_frontfacing_interpolation());
3155 case nir_intrinsic_load_sample_pos
: {
3156 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3157 assert(sample_pos
.file
!= BAD_FILE
);
3158 dest
.type
= sample_pos
.type
;
3159 bld
.MOV(dest
, sample_pos
);
3160 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3164 case nir_intrinsic_load_layer_id
:
3165 dest
.type
= BRW_REGISTER_TYPE_UD
;
3166 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3169 case nir_intrinsic_load_helper_invocation
:
3170 case nir_intrinsic_load_sample_mask_in
:
3171 case nir_intrinsic_load_sample_id
: {
3172 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3173 fs_reg val
= nir_system_values
[sv
];
3174 assert(val
.file
!= BAD_FILE
);
3175 dest
.type
= val
.type
;
3180 case nir_intrinsic_store_output
: {
3181 const fs_reg src
= get_nir_src(instr
->src
[0]);
3182 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3183 const unsigned location
= nir_intrinsic_base(instr
) +
3184 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3185 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3188 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3189 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3190 offset(src
, bld
, j
));
3195 case nir_intrinsic_load_output
: {
3196 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3197 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3198 assert(l
>= FRAG_RESULT_DATA0
);
3199 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3200 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3201 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3203 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3204 emit_coherent_fb_read(bld
, tmp
, target
);
3206 emit_non_coherent_fb_read(bld
, tmp
, target
);
3208 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3209 bld
.MOV(offset(dest
, bld
, j
),
3210 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3216 case nir_intrinsic_discard
:
3217 case nir_intrinsic_discard_if
: {
3218 /* We track our discarded pixels in f0.1. By predicating on it, we can
3219 * update just the flag bits that aren't yet discarded. If there's no
3220 * condition, we emit a CMP of g0 != g0, so all currently executing
3221 * channels will get turned off.
3224 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3225 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3226 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3228 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3229 BRW_REGISTER_TYPE_UW
));
3230 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3232 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3233 cmp
->flag_subreg
= 1;
3235 if (devinfo
->gen
>= 6) {
3236 emit_discard_jump();
3239 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3243 case nir_intrinsic_load_input
: {
3244 /* load_input is only used for flat inputs */
3245 unsigned base
= nir_intrinsic_base(instr
);
3246 unsigned comp
= nir_intrinsic_component(instr
);
3247 unsigned num_components
= instr
->num_components
;
3248 fs_reg orig_dest
= dest
;
3249 enum brw_reg_type type
= dest
.type
;
3251 /* Special case fields in the VUE header */
3252 if (base
== VARYING_SLOT_LAYER
)
3254 else if (base
== VARYING_SLOT_VIEWPORT
)
3257 if (nir_dest_bit_size(instr
->dest
) == 64) {
3258 /* const_index is in 32-bit type size units that could not be aligned
3259 * with DF. We need to read the double vector as if it was a float
3260 * vector of twice the number of components to fetch the right data.
3262 type
= BRW_REGISTER_TYPE_F
;
3263 num_components
*= 2;
3264 dest
= bld
.vgrf(type
, num_components
);
3267 for (unsigned int i
= 0; i
< num_components
; i
++) {
3268 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3269 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3272 if (nir_dest_bit_size(instr
->dest
) == 64) {
3273 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3274 instr
->num_components
);
3279 case nir_intrinsic_load_barycentric_pixel
:
3280 case nir_intrinsic_load_barycentric_centroid
:
3281 case nir_intrinsic_load_barycentric_sample
:
3282 /* Do nothing - load_interpolated_input handling will handle it later. */
3285 case nir_intrinsic_load_barycentric_at_sample
: {
3286 const glsl_interp_mode interpolation
=
3287 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3289 if (nir_src_is_const(instr
->src
[0])) {
3290 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3292 emit_pixel_interpolater_send(bld
,
3293 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3296 brw_imm_ud(msg_data
),
3299 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3300 BRW_REGISTER_TYPE_UD
);
3302 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3303 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3304 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3305 bld
.exec_all().group(1, 0)
3306 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3307 emit_pixel_interpolater_send(bld
,
3308 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3314 /* Make a loop that sends a message to the pixel interpolater
3315 * for the sample number in each live channel. If there are
3316 * multiple channels with the same sample number then these
3317 * will be handled simultaneously with a single interation of
3320 bld
.emit(BRW_OPCODE_DO
);
3322 /* Get the next live sample number into sample_id_reg */
3323 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3325 /* Set the flag register so that we can perform the send
3326 * message on all channels that have the same sample number
3328 bld
.CMP(bld
.null_reg_ud(),
3329 sample_src
, sample_id
,
3330 BRW_CONDITIONAL_EQ
);
3331 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3332 bld
.exec_all().group(1, 0)
3333 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3335 emit_pixel_interpolater_send(bld
,
3336 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3339 component(msg_data
, 0),
3341 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3343 /* Continue the loop if there are any live channels left */
3344 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3346 bld
.emit(BRW_OPCODE_WHILE
));
3352 case nir_intrinsic_load_barycentric_at_offset
: {
3353 const glsl_interp_mode interpolation
=
3354 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3356 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3359 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3360 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3361 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3363 emit_pixel_interpolater_send(bld
,
3364 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3367 brw_imm_ud(off_x
| (off_y
<< 4)),
3370 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3371 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3372 BRW_REGISTER_TYPE_F
);
3373 for (int i
= 0; i
< 2; i
++) {
3374 fs_reg temp
= vgrf(glsl_type::float_type
);
3375 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3376 fs_reg itemp
= vgrf(glsl_type::int_type
);
3378 bld
.MOV(itemp
, temp
);
3380 /* Clamp the upper end of the range to +7/16.
3381 * ARB_gpu_shader5 requires that we support a maximum offset
3382 * of +0.5, which isn't representable in a S0.4 value -- if
3383 * we didn't clamp it, we'd end up with -8/16, which is the
3384 * opposite of what the shader author wanted.
3386 * This is legal due to ARB_gpu_shader5's quantization
3389 * "Not all values of <offset> may be supported; x and y
3390 * offsets may be rounded to fixed-point values with the
3391 * number of fraction bits given by the
3392 * implementation-dependent constant
3393 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3395 set_condmod(BRW_CONDITIONAL_L
,
3396 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3399 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3400 emit_pixel_interpolater_send(bld
,
3410 case nir_intrinsic_load_interpolated_input
: {
3411 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3412 emit_fragcoord_interpolation(dest
);
3416 assert(instr
->src
[0].ssa
&&
3417 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3418 nir_intrinsic_instr
*bary_intrinsic
=
3419 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3420 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3421 enum glsl_interp_mode interp_mode
=
3422 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3425 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3426 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3427 /* Use the result of the PI message */
3428 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3430 /* Use the delta_xy values computed from the payload */
3431 enum brw_barycentric_mode bary
=
3432 brw_barycentric_mode(interp_mode
, bary_intrin
);
3434 dst_xy
= this->delta_xy
[bary
];
3437 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3439 component(interp_reg(nir_intrinsic_base(instr
),
3440 nir_intrinsic_component(instr
) + i
), 0);
3441 interp
.type
= BRW_REGISTER_TYPE_F
;
3442 dest
.type
= BRW_REGISTER_TYPE_F
;
3444 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3445 fs_reg tmp
= vgrf(glsl_type::float_type
);
3446 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3447 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3449 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3456 nir_emit_intrinsic(bld
, instr
);
3462 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3464 if (nir_src_is_const(instr
->src
[src
])) {
3465 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3468 else if (add_val
== -1)
3476 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3477 nir_intrinsic_instr
*instr
)
3479 assert(stage
== MESA_SHADER_COMPUTE
);
3480 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3483 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3484 dest
= get_nir_dest(instr
->dest
);
3486 switch (instr
->intrinsic
) {
3487 case nir_intrinsic_barrier
:
3489 cs_prog_data
->uses_barrier
= true;
3492 case nir_intrinsic_load_subgroup_id
:
3493 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3496 case nir_intrinsic_load_local_invocation_id
:
3497 case nir_intrinsic_load_work_group_id
: {
3498 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3499 fs_reg val
= nir_system_values
[sv
];
3500 assert(val
.file
!= BAD_FILE
);
3501 dest
.type
= val
.type
;
3502 for (unsigned i
= 0; i
< 3; i
++)
3503 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3507 case nir_intrinsic_load_num_work_groups
: {
3508 const unsigned surface
=
3509 cs_prog_data
->binding_table
.work_groups_start
;
3511 cs_prog_data
->uses_num_work_groups
= true;
3513 fs_reg surf_index
= brw_imm_ud(surface
);
3514 brw_mark_surface_used(prog_data
, surface
);
3516 /* Read the 3 GLuint components of gl_NumWorkGroups */
3517 for (unsigned i
= 0; i
< 3; i
++) {
3518 fs_reg read_result
=
3519 emit_untyped_read(bld
, surf_index
,
3521 1 /* dims */, 1 /* size */,
3522 BRW_PREDICATE_NONE
);
3523 read_result
.type
= dest
.type
;
3524 bld
.MOV(dest
, read_result
);
3525 dest
= offset(dest
, bld
, 1);
3530 case nir_intrinsic_shared_atomic_add
:
3531 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3533 case nir_intrinsic_shared_atomic_imin
:
3534 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3536 case nir_intrinsic_shared_atomic_umin
:
3537 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3539 case nir_intrinsic_shared_atomic_imax
:
3540 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3542 case nir_intrinsic_shared_atomic_umax
:
3543 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3545 case nir_intrinsic_shared_atomic_and
:
3546 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3548 case nir_intrinsic_shared_atomic_or
:
3549 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3551 case nir_intrinsic_shared_atomic_xor
:
3552 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3554 case nir_intrinsic_shared_atomic_exchange
:
3555 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3557 case nir_intrinsic_shared_atomic_comp_swap
:
3558 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3560 case nir_intrinsic_shared_atomic_fmin
:
3561 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3563 case nir_intrinsic_shared_atomic_fmax
:
3564 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3566 case nir_intrinsic_shared_atomic_fcomp_swap
:
3567 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3570 case nir_intrinsic_load_shared
: {
3571 assert(devinfo
->gen
>= 7);
3573 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3575 /* Get the offset to read from */
3577 if (nir_src_is_const(instr
->src
[0])) {
3578 offset_reg
= brw_imm_ud(instr
->const_index
[0] +
3579 nir_src_as_uint(instr
->src
[0]));
3581 offset_reg
= vgrf(glsl_type::uint_type
);
3583 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3584 brw_imm_ud(instr
->const_index
[0]));
3587 /* Read the vector */
3588 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3589 instr
->num_components
);
3593 case nir_intrinsic_store_shared
: {
3594 assert(devinfo
->gen
>= 7);
3597 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3600 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3603 unsigned writemask
= instr
->const_index
[1];
3605 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3606 * since the untyped writes below operate in units of 32-bits, which
3607 * means that we need to write twice as many components each time.
3608 * Also, we have to suffle 64-bit data to be in the appropriate layout
3609 * expected by our 32-bit write messages.
3611 unsigned type_size
= 4;
3612 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3614 val_reg
= shuffle_for_32bit_write(bld
, val_reg
, 0,
3615 instr
->num_components
);
3618 unsigned type_slots
= type_size
/ 4;
3620 /* Combine groups of consecutive enabled channels in one write
3621 * message. We use ffs to find the first enabled channel and then ffs on
3622 * the bit-inverse, down-shifted writemask to determine the length of
3623 * the block of enabled bits.
3626 unsigned first_component
= ffs(writemask
) - 1;
3627 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3629 /* We can't write more than 2 64-bit components at once. Limit the
3630 * length of the write to what we can do and let the next iteration
3634 length
= MIN2(2, length
);
3637 if (nir_src_is_const(instr
->src
[1])) {
3638 offset_reg
= brw_imm_ud(instr
->const_index
[0] +
3639 nir_src_as_uint(instr
->src
[1]) +
3640 type_size
* first_component
);
3642 offset_reg
= vgrf(glsl_type::uint_type
);
3644 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3645 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3648 emit_untyped_write(bld
, surf_index
, offset_reg
,
3649 offset(val_reg
, bld
, first_component
* type_slots
),
3650 1 /* dims */, length
* type_slots
,
3651 BRW_PREDICATE_NONE
);
3653 /* Clear the bits in the writemask that we just wrote, then try
3654 * again to see if more channels are left.
3656 writemask
&= (15 << (first_component
+ length
));
3663 nir_emit_intrinsic(bld
, instr
);
3669 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3670 nir_op op
, brw_reg_type type
)
3672 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3673 switch (type_sz(type
)) {
3675 assert(type
!= BRW_REGISTER_TYPE_HF
);
3676 return retype(brw_imm_uw(value
.u16
[0]), type
);
3678 return retype(brw_imm_ud(value
.u32
[0]), type
);
3680 if (type
== BRW_REGISTER_TYPE_DF
)
3681 return setup_imm_df(bld
, value
.f64
[0]);
3683 return retype(brw_imm_u64(value
.u64
[0]), type
);
3685 unreachable("Invalid type size");
3690 brw_op_for_nir_reduction_op(nir_op op
)
3693 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3694 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3695 case nir_op_imul
: return BRW_OPCODE_MUL
;
3696 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3697 case nir_op_imin
: return BRW_OPCODE_SEL
;
3698 case nir_op_umin
: return BRW_OPCODE_SEL
;
3699 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3700 case nir_op_imax
: return BRW_OPCODE_SEL
;
3701 case nir_op_umax
: return BRW_OPCODE_SEL
;
3702 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3703 case nir_op_iand
: return BRW_OPCODE_AND
;
3704 case nir_op_ior
: return BRW_OPCODE_OR
;
3705 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3707 unreachable("Invalid reduction operation");
3711 static brw_conditional_mod
3712 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3715 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3716 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3717 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3718 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3719 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3720 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3721 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3722 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3723 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3724 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3725 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3726 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3727 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3729 unreachable("Invalid reduction operation");
3734 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3735 nir_intrinsic_instr
*instr
)
3737 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3739 if (stage_prog_data
->binding_table
.image_start
> 0) {
3740 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3741 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3743 bld
.ADD(image
, image
,
3744 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3748 return bld
.emit_uniformize(image
);
3752 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3753 nir_intrinsic_instr
*instr
)
3755 /* SSBO stores are weird in that their index is in src[1] */
3756 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3759 if (nir_src_is_const(instr
->src
[src
])) {
3760 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3761 nir_src_as_uint(instr
->src
[src
]);
3762 surf_index
= brw_imm_ud(index
);
3763 brw_mark_surface_used(prog_data
, index
);
3765 surf_index
= vgrf(glsl_type::uint_type
);
3766 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3767 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3769 /* Assume this may touch any UBO. It would be nice to provide
3770 * a tighter bound, but the array information is already lowered away.
3772 brw_mark_surface_used(prog_data
,
3773 stage_prog_data
->binding_table
.ssbo_start
+
3774 nir
->info
.num_ssbos
- 1);
3781 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3783 switch (nir_intrinsic_image_dim(instr
)) {
3784 case GLSL_SAMPLER_DIM_1D
:
3785 return 1 + nir_intrinsic_image_array(instr
);
3786 case GLSL_SAMPLER_DIM_2D
:
3787 case GLSL_SAMPLER_DIM_RECT
:
3788 return 2 + nir_intrinsic_image_array(instr
);
3789 case GLSL_SAMPLER_DIM_3D
:
3790 case GLSL_SAMPLER_DIM_CUBE
:
3792 case GLSL_SAMPLER_DIM_BUF
:
3794 case GLSL_SAMPLER_DIM_MS
:
3795 return 2 + nir_intrinsic_image_array(instr
);
3797 unreachable("Invalid image dimension");
3802 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3805 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3806 dest
= get_nir_dest(instr
->dest
);
3808 switch (instr
->intrinsic
) {
3809 case nir_intrinsic_image_load
:
3810 case nir_intrinsic_image_store
:
3811 case nir_intrinsic_image_atomic_add
:
3812 case nir_intrinsic_image_atomic_min
:
3813 case nir_intrinsic_image_atomic_max
:
3814 case nir_intrinsic_image_atomic_and
:
3815 case nir_intrinsic_image_atomic_or
:
3816 case nir_intrinsic_image_atomic_xor
:
3817 case nir_intrinsic_image_atomic_exchange
:
3818 case nir_intrinsic_image_atomic_comp_swap
: {
3819 if (stage
== MESA_SHADER_FRAGMENT
&&
3820 instr
->intrinsic
!= nir_intrinsic_image_load
)
3821 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3823 /* Get some metadata from the image intrinsic. */
3824 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3825 const unsigned dims
= image_intrinsic_coord_components(instr
);
3826 const GLenum format
= nir_intrinsic_format(instr
);
3827 const unsigned dest_components
= nir_intrinsic_dest_components(instr
);
3829 /* Get the arguments of the image intrinsic. */
3830 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3831 const fs_reg coords
= retype(get_nir_src(instr
->src
[1]),
3832 BRW_REGISTER_TYPE_UD
);
3835 /* Emit an image load, store or atomic op. */
3836 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3837 tmp
= emit_typed_read(bld
, image
, coords
, dims
,
3838 instr
->num_components
);
3839 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3840 const fs_reg src0
= get_nir_src(instr
->src
[3]);
3841 emit_typed_write(bld
, image
, coords
, src0
, dims
,
3842 instr
->num_components
);
3845 unsigned num_srcs
= info
->num_srcs
;
3847 switch (instr
->intrinsic
) {
3848 case nir_intrinsic_image_atomic_add
:
3849 assert(num_srcs
== 4);
3851 op
= get_op_for_atomic_add(instr
, 3);
3853 if (op
!= BRW_AOP_ADD
)
3856 case nir_intrinsic_image_atomic_min
:
3857 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3858 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3860 case nir_intrinsic_image_atomic_max
:
3861 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3862 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3864 case nir_intrinsic_image_atomic_and
:
3867 case nir_intrinsic_image_atomic_or
:
3870 case nir_intrinsic_image_atomic_xor
:
3873 case nir_intrinsic_image_atomic_exchange
:
3876 case nir_intrinsic_image_atomic_comp_swap
:
3880 unreachable("Not reachable.");
3883 const fs_reg src0
= (num_srcs
>= 4 ?
3884 get_nir_src(instr
->src
[3]) : fs_reg());
3885 const fs_reg src1
= (num_srcs
>= 5 ?
3886 get_nir_src(instr
->src
[4]) : fs_reg());
3888 tmp
= emit_typed_atomic(bld
, image
, coords
, src0
, src1
, dims
, 1, op
);
3891 /* Assign the result. */
3892 for (unsigned c
= 0; c
< dest_components
; ++c
) {
3893 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3894 offset(tmp
, bld
, c
));
3899 case nir_intrinsic_image_size
: {
3900 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3901 * into will handle the binding table index for us in the geneerator.
3903 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3904 BRW_REGISTER_TYPE_UD
);
3905 image
= bld
.emit_uniformize(image
);
3907 /* Since the image size is always uniform, we can just emit a SIMD8
3908 * query instruction and splat the result out.
3910 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3912 /* The LOD also serves as the message payload */
3913 fs_reg lod
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3914 ubld
.MOV(lod
, brw_imm_ud(0));
3916 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3917 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE
, tmp
, lod
, image
);
3919 inst
->size_written
= 4 * REG_SIZE
;
3921 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3922 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3923 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3924 offset(retype(dest
, tmp
.type
), bld
, c
),
3925 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3927 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3928 component(offset(tmp
, ubld
, c
), 0));
3934 case nir_intrinsic_image_load_raw_intel
: {
3935 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3936 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3937 BRW_REGISTER_TYPE_UD
);
3939 fs_reg tmp
= emit_untyped_read(bld
, image
, addr
, 1,
3940 instr
->num_components
);
3942 for (unsigned c
= 0; c
< instr
->num_components
; ++c
) {
3943 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3944 offset(tmp
, bld
, c
));
3949 case nir_intrinsic_image_store_raw_intel
: {
3950 const fs_reg image
= get_nir_image_intrinsic_image(bld
, instr
);
3951 const fs_reg addr
= retype(get_nir_src(instr
->src
[1]),
3952 BRW_REGISTER_TYPE_UD
);
3953 const fs_reg data
= retype(get_nir_src(instr
->src
[2]),
3954 BRW_REGISTER_TYPE_UD
);
3956 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3958 emit_untyped_write(bld
, image
, addr
, data
, 1,
3959 instr
->num_components
);
3963 case nir_intrinsic_group_memory_barrier
:
3964 case nir_intrinsic_memory_barrier_shared
:
3965 case nir_intrinsic_memory_barrier_atomic_counter
:
3966 case nir_intrinsic_memory_barrier_buffer
:
3967 case nir_intrinsic_memory_barrier_image
:
3968 case nir_intrinsic_memory_barrier
: {
3969 const fs_builder ubld
= bld
.group(8, 0);
3970 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3971 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3972 ->size_written
= 2 * REG_SIZE
;
3976 case nir_intrinsic_shader_clock
: {
3977 /* We cannot do anything if there is an event, so ignore it for now */
3978 const fs_reg shader_clock
= get_timestamp(bld
);
3979 const fs_reg srcs
[] = { component(shader_clock
, 0),
3980 component(shader_clock
, 1) };
3981 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3985 case nir_intrinsic_image_samples
:
3986 /* The driver does not support multi-sampled images. */
3987 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3990 case nir_intrinsic_load_uniform
: {
3991 /* Offsets are in bytes but they should always aligned to
3994 assert(instr
->const_index
[0] % 4 == 0 ||
3995 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3997 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3999 if (nir_src_is_const(instr
->src
[0])) {
4000 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4001 assert(load_offset
% type_sz(dest
.type
) == 0);
4002 /* For 16-bit types we add the module of the const_index[0]
4003 * offset to access to not 32-bit aligned element
4005 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4007 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4008 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4011 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4012 BRW_REGISTER_TYPE_UD
);
4014 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4015 * go past the end of the uniform. In order to keep the n'th
4016 * component from running past, we subtract off the size of all but
4017 * one component of the vector.
4019 assert(instr
->const_index
[1] >=
4020 instr
->num_components
* (int) type_sz(dest
.type
));
4021 unsigned read_size
= instr
->const_index
[1] -
4022 (instr
->num_components
- 1) * type_sz(dest
.type
);
4024 bool supports_64bit_indirects
=
4025 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4027 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4028 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4029 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4030 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4031 indirect
, brw_imm_ud(read_size
));
4034 const unsigned num_mov_indirects
=
4035 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4036 /* We read a little bit less per MOV INDIRECT, as they are now
4037 * 32-bits ones instead of 64-bit. Fix read_size then.
4039 const unsigned read_size_32bit
= read_size
-
4040 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4041 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4042 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4043 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4044 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4045 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4046 indirect
, brw_imm_ud(read_size_32bit
));
4054 case nir_intrinsic_load_ubo
: {
4056 if (nir_src_is_const(instr
->src
[0])) {
4057 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4058 nir_src_as_uint(instr
->src
[0]);
4059 surf_index
= brw_imm_ud(index
);
4060 brw_mark_surface_used(prog_data
, index
);
4062 /* The block index is not a constant. Evaluate the index expression
4063 * per-channel and add the base UBO index; we have to select a value
4064 * from any live channel.
4066 surf_index
= vgrf(glsl_type::uint_type
);
4067 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4068 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4069 surf_index
= bld
.emit_uniformize(surf_index
);
4071 /* Assume this may touch any UBO. It would be nice to provide
4072 * a tighter bound, but the array information is already lowered away.
4074 brw_mark_surface_used(prog_data
,
4075 stage_prog_data
->binding_table
.ubo_start
+
4076 nir
->info
.num_ubos
- 1);
4079 if (!nir_src_is_const(instr
->src
[1])) {
4080 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4081 BRW_REGISTER_TYPE_UD
);
4083 for (int i
= 0; i
< instr
->num_components
; i
++)
4084 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4085 base_offset
, i
* type_sz(dest
.type
));
4087 /* Even if we are loading doubles, a pull constant load will load
4088 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4089 * need to load a full dvec4 we will have to emit 2 loads. This is
4090 * similar to demote_pull_constants(), except that in that case we
4091 * see individual accesses to each component of the vector and then
4092 * we let CSE deal with duplicate loads. Here we see a vector access
4093 * and we have to split it if necessary.
4095 const unsigned type_size
= type_sz(dest
.type
);
4096 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4098 /* See if we've selected this as a push constant candidate */
4099 if (nir_src_is_const(instr
->src
[0])) {
4100 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4101 const unsigned offset_256b
= load_offset
/ 32;
4104 for (int i
= 0; i
< 4; i
++) {
4105 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4106 if (range
->block
== ubo_block
&&
4107 offset_256b
>= range
->start
&&
4108 offset_256b
< range
->start
+ range
->length
) {
4110 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4111 push_reg
.offset
= load_offset
- 32 * range
->start
;
4116 if (push_reg
.file
!= BAD_FILE
) {
4117 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4118 bld
.MOV(offset(dest
, bld
, i
),
4119 byte_offset(push_reg
, i
* type_size
));
4125 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4126 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4127 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4129 for (unsigned c
= 0; c
< instr
->num_components
;) {
4130 const unsigned base
= load_offset
+ c
* type_size
;
4131 /* Number of usable components in the next block-aligned load. */
4132 const unsigned count
= MIN2(instr
->num_components
- c
,
4133 (block_sz
- base
% block_sz
) / type_size
);
4135 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4136 packed_consts
, surf_index
,
4137 brw_imm_ud(base
& ~(block_sz
- 1)));
4139 const fs_reg consts
=
4140 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4143 for (unsigned d
= 0; d
< count
; d
++)
4144 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4152 case nir_intrinsic_load_ssbo
: {
4153 assert(devinfo
->gen
>= 7);
4155 fs_reg surf_index
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4156 fs_reg offset_reg
= get_nir_src_imm(instr
->src
[1]);
4158 /* Read the vector */
4159 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4160 instr
->num_components
);
4165 case nir_intrinsic_store_ssbo
: {
4166 assert(devinfo
->gen
>= 7);
4168 if (stage
== MESA_SHADER_FRAGMENT
)
4169 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4171 fs_reg surf_index
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4174 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4177 unsigned writemask
= instr
->const_index
[0];
4179 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4180 * since the untyped writes below operate in units of 32-bits, which
4181 * means that we need to write twice as many components each time.
4182 * Also, we have to suffle 64-bit data to be in the appropriate layout
4183 * expected by our 32-bit write messages.
4185 unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4186 unsigned type_size
= bit_size
/ 8;
4188 /* Combine groups of consecutive enabled channels in one write
4189 * message. We use ffs to find the first enabled channel and then ffs on
4190 * the bit-inverse, down-shifted writemask to determine the num_components
4191 * of the block of enabled bits.
4194 unsigned first_component
= ffs(writemask
) - 1;
4195 unsigned num_components
= ffs(~(writemask
>> first_component
)) - 1;
4196 fs_reg write_src
= offset(val_reg
, bld
, first_component
);
4198 if (type_size
> 4) {
4199 /* We can't write more than 2 64-bit components at once. Limit
4200 * the num_components of the write to what we can do and let the next
4201 * iteration handle the rest.
4203 num_components
= MIN2(2, num_components
);
4204 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4206 } else if (type_size
< 4) {
4207 /* For 16-bit types we pack two consecutive values into a 32-bit
4208 * word and use an untyped write message. For single values or not
4209 * 32-bit-aligned we need to use byte-scattered writes because
4210 * untyped writes works with 32-bit components with 32-bit
4211 * alignment. byte_scattered_write messages only support one
4212 * 16-bit component at a time. As VK_KHR_relaxed_block_layout
4213 * could be enabled we can not guarantee that not constant offsets
4214 * to be 32-bit aligned for 16-bit types. For example an array, of
4215 * 16-bit vec3 with array element stride of 6.
4217 * In the case of 32-bit aligned constant offsets if there is
4218 * a 3-components vector we submit one untyped-write message
4219 * of 32-bit (first two components), and one byte-scattered
4220 * write message (the last component).
4223 if (!nir_src_is_const(instr
->src
[2]) ||
4224 ((nir_src_as_uint(instr
->src
[2]) +
4225 type_size
* first_component
) % 4)) {
4226 /* If we use a .yz writemask we also need to emit 2
4227 * byte-scattered write messages because of y-component not
4228 * being aligned to 32-bit.
4231 } else if (num_components
* type_size
> 4 &&
4232 (num_components
* type_size
% 4)) {
4233 /* If the pending components size is not a multiple of 4 bytes
4234 * we left the not aligned components for following emits of
4235 * length == 1 with byte_scattered_write.
4237 num_components
-= (num_components
* type_size
% 4) / type_size
;
4238 } else if (num_components
* type_size
< 4) {
4241 /* For num_components == 1 we are also shuffling the component
4242 * because byte scattered writes of 16-bit need values to be dword
4243 * aligned. Shuffling only one component would be the same as
4246 write_src
= shuffle_for_32bit_write(bld
, write_src
, 0,
4252 if (nir_src_is_const(instr
->src
[2])) {
4253 offset_reg
= brw_imm_ud(nir_src_as_uint(instr
->src
[2]) +
4254 type_size
* first_component
);
4256 offset_reg
= vgrf(glsl_type::uint_type
);
4258 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4259 brw_imm_ud(type_size
* first_component
));
4262 if (type_size
< 4 && num_components
== 1) {
4263 /* Untyped Surface messages have a fixed 32-bit size, so we need
4264 * to rely on byte scattered in order to write 16-bit elements.
4265 * The byte_scattered_write message needs that every written 16-bit
4266 * type to be aligned 32-bits (stride=2).
4268 emit_byte_scattered_write(bld
, surf_index
, offset_reg
,
4272 BRW_PREDICATE_NONE
);
4274 assert(num_components
* type_size
<= 16);
4275 assert((num_components
* type_size
) % 4 == 0);
4276 assert(offset_reg
.file
!= BRW_IMMEDIATE_VALUE
||
4277 offset_reg
.ud
% 4 == 0);
4278 unsigned num_slots
= (num_components
* type_size
) / 4;
4280 emit_untyped_write(bld
, surf_index
, offset_reg
,
4282 1 /* dims */, num_slots
,
4283 BRW_PREDICATE_NONE
);
4286 /* Clear the bits in the writemask that we just wrote, then try
4287 * again to see if more channels are left.
4289 writemask
&= (15 << (first_component
+ num_components
));
4294 case nir_intrinsic_store_output
: {
4295 fs_reg src
= get_nir_src(instr
->src
[0]);
4297 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4298 unsigned num_components
= instr
->num_components
;
4299 unsigned first_component
= nir_intrinsic_component(instr
);
4300 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4301 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4302 num_components
*= 2;
4305 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4306 4 * store_offset
), src
.type
);
4307 for (unsigned j
= 0; j
< num_components
; j
++) {
4308 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4309 offset(src
, bld
, j
));
4314 case nir_intrinsic_ssbo_atomic_add
:
4315 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4317 case nir_intrinsic_ssbo_atomic_imin
:
4318 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4320 case nir_intrinsic_ssbo_atomic_umin
:
4321 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4323 case nir_intrinsic_ssbo_atomic_imax
:
4324 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4326 case nir_intrinsic_ssbo_atomic_umax
:
4327 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4329 case nir_intrinsic_ssbo_atomic_and
:
4330 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4332 case nir_intrinsic_ssbo_atomic_or
:
4333 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4335 case nir_intrinsic_ssbo_atomic_xor
:
4336 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4338 case nir_intrinsic_ssbo_atomic_exchange
:
4339 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4341 case nir_intrinsic_ssbo_atomic_comp_swap
:
4342 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4344 case nir_intrinsic_ssbo_atomic_fmin
:
4345 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4347 case nir_intrinsic_ssbo_atomic_fmax
:
4348 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4350 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4351 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4354 case nir_intrinsic_get_buffer_size
: {
4355 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4356 nir_src_as_uint(instr
->src
[0]) : 0;
4358 /* A resinfo's sampler message is used to get the buffer size. The
4359 * SIMD8's writeback message consists of four registers and SIMD16's
4360 * writeback message consists of 8 destination registers (two per each
4361 * component). Because we are only interested on the first channel of
4362 * the first returned component, where resinfo returns the buffer size
4363 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4364 * the dispatch width.
4366 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4367 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4368 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4371 ubld
.MOV(src_payload
, brw_imm_d(0));
4373 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4374 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4375 src_payload
, brw_imm_ud(index
));
4376 inst
->header_size
= 0;
4378 inst
->size_written
= 4 * REG_SIZE
;
4380 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4382 * "Out-of-bounds checking is always performed at a DWord granularity. If
4383 * any part of the DWord is out-of-bounds then the whole DWord is
4384 * considered out-of-bounds."
4386 * This implies that types with size smaller than 4-bytes need to be
4387 * padded if they don't complete the last dword of the buffer. But as we
4388 * need to maintain the original size we need to reverse the padding
4389 * calculation to return the correct size to know the number of elements
4390 * of an unsized array. As we stored in the last two bits of the surface
4391 * size the needed padding for the buffer, we calculate here the
4392 * original buffer_size reversing the surface_size calculation:
4394 * surface_size = isl_align(buffer_size, 4) +
4395 * (isl_align(buffer_size) - buffer_size)
4397 * buffer_size = surface_size & ~3 - surface_size & 3
4400 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4401 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4402 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4404 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4405 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4406 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4408 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4410 brw_mark_surface_used(prog_data
, index
);
4414 case nir_intrinsic_load_subgroup_invocation
:
4415 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4416 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4419 case nir_intrinsic_load_subgroup_eq_mask
:
4420 case nir_intrinsic_load_subgroup_ge_mask
:
4421 case nir_intrinsic_load_subgroup_gt_mask
:
4422 case nir_intrinsic_load_subgroup_le_mask
:
4423 case nir_intrinsic_load_subgroup_lt_mask
:
4424 unreachable("not reached");
4426 case nir_intrinsic_vote_any
: {
4427 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4429 /* The any/all predicates do not consider channel enables. To prevent
4430 * dead channels from affecting the result, we initialize the flag with
4431 * with the identity value for the logical operation.
4433 if (dispatch_width
== 32) {
4434 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4435 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4438 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4440 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4442 /* For some reason, the any/all predicates don't work properly with
4443 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4444 * doesn't read the correct subset of the flag register and you end up
4445 * getting garbage in the second half. Work around this by using a pair
4446 * of 1-wide MOVs and scattering the result.
4448 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4449 ubld
.MOV(res1
, brw_imm_d(0));
4450 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4451 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4452 BRW_PREDICATE_ALIGN1_ANY32H
,
4453 ubld
.MOV(res1
, brw_imm_d(-1)));
4455 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4458 case nir_intrinsic_vote_all
: {
4459 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4461 /* The any/all predicates do not consider channel enables. To prevent
4462 * dead channels from affecting the result, we initialize the flag with
4463 * with the identity value for the logical operation.
4465 if (dispatch_width
== 32) {
4466 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4467 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4468 brw_imm_ud(0xffffffff));
4470 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4472 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4474 /* For some reason, the any/all predicates don't work properly with
4475 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4476 * doesn't read the correct subset of the flag register and you end up
4477 * getting garbage in the second half. Work around this by using a pair
4478 * of 1-wide MOVs and scattering the result.
4480 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4481 ubld
.MOV(res1
, brw_imm_d(0));
4482 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4483 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4484 BRW_PREDICATE_ALIGN1_ALL32H
,
4485 ubld
.MOV(res1
, brw_imm_d(-1)));
4487 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4490 case nir_intrinsic_vote_feq
:
4491 case nir_intrinsic_vote_ieq
: {
4492 fs_reg value
= get_nir_src(instr
->src
[0]);
4493 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4494 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4495 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4498 fs_reg uniformized
= bld
.emit_uniformize(value
);
4499 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4501 /* The any/all predicates do not consider channel enables. To prevent
4502 * dead channels from affecting the result, we initialize the flag with
4503 * with the identity value for the logical operation.
4505 if (dispatch_width
== 32) {
4506 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4507 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4508 brw_imm_ud(0xffffffff));
4510 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4512 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4514 /* For some reason, the any/all predicates don't work properly with
4515 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4516 * doesn't read the correct subset of the flag register and you end up
4517 * getting garbage in the second half. Work around this by using a pair
4518 * of 1-wide MOVs and scattering the result.
4520 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4521 ubld
.MOV(res1
, brw_imm_d(0));
4522 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4523 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4524 BRW_PREDICATE_ALIGN1_ALL32H
,
4525 ubld
.MOV(res1
, brw_imm_d(-1)));
4527 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4531 case nir_intrinsic_ballot
: {
4532 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4533 BRW_REGISTER_TYPE_UD
);
4534 struct brw_reg flag
= brw_flag_reg(0, 0);
4535 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4536 * as f0.0. This is a problem for fragment programs as we currently use
4537 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4538 * programs yet so this isn't a problem. When we do, something will
4541 if (dispatch_width
== 32)
4542 flag
.type
= BRW_REGISTER_TYPE_UD
;
4544 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4545 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4547 if (instr
->dest
.ssa
.bit_size
> 32) {
4548 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4550 dest
.type
= BRW_REGISTER_TYPE_UD
;
4552 bld
.MOV(dest
, flag
);
4556 case nir_intrinsic_read_invocation
: {
4557 const fs_reg value
= get_nir_src(instr
->src
[0]);
4558 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4559 fs_reg tmp
= bld
.vgrf(value
.type
);
4561 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4562 bld
.emit_uniformize(invocation
));
4564 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4568 case nir_intrinsic_read_first_invocation
: {
4569 const fs_reg value
= get_nir_src(instr
->src
[0]);
4570 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4574 case nir_intrinsic_shuffle
: {
4575 const fs_reg value
= get_nir_src(instr
->src
[0]);
4576 const fs_reg index
= get_nir_src(instr
->src
[1]);
4578 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4582 case nir_intrinsic_first_invocation
: {
4583 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4584 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4585 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4586 fs_reg(component(tmp
, 0)));
4590 case nir_intrinsic_quad_broadcast
: {
4591 const fs_reg value
= get_nir_src(instr
->src
[0]);
4592 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4594 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4595 value
, brw_imm_ud(index
), brw_imm_ud(4));
4599 case nir_intrinsic_quad_swap_horizontal
: {
4600 const fs_reg value
= get_nir_src(instr
->src
[0]);
4601 const fs_reg tmp
= bld
.vgrf(value
.type
);
4602 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4604 const fs_reg src_left
= horiz_stride(value
, 2);
4605 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4606 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4607 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4609 /* From the Cherryview PRM Vol. 7, "Register Region Restrictiosn":
4611 * "When source or destination datatype is 64b or operation is
4612 * integer DWord multiply, regioning in Align1 must follow
4617 * 3. Source and Destination offset must be the same, except
4618 * the case of scalar source."
4620 * In order to work around this, we have to emit two 32-bit MOVs instead
4621 * of a single 64-bit MOV to do the shuffle.
4623 if (type_sz(value
.type
) > 4 &&
4624 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
4625 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 0),
4626 subscript(src_right
, BRW_REGISTER_TYPE_D
, 0));
4627 ubld
.MOV(subscript(tmp_left
, BRW_REGISTER_TYPE_D
, 1),
4628 subscript(src_right
, BRW_REGISTER_TYPE_D
, 1));
4629 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 0),
4630 subscript(src_left
, BRW_REGISTER_TYPE_D
, 0));
4631 ubld
.MOV(subscript(tmp_right
, BRW_REGISTER_TYPE_D
, 1),
4632 subscript(src_left
, BRW_REGISTER_TYPE_D
, 1));
4634 ubld
.MOV(tmp_left
, src_right
);
4635 ubld
.MOV(tmp_right
, src_left
);
4637 bld
.MOV(retype(dest
, value
.type
), tmp
);
4641 case nir_intrinsic_quad_swap_vertical
: {
4642 const fs_reg value
= get_nir_src(instr
->src
[0]);
4643 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4644 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4645 const fs_reg tmp
= bld
.vgrf(value
.type
);
4646 const fs_builder ubld
= bld
.exec_all();
4647 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4648 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4649 bld
.MOV(retype(dest
, value
.type
), tmp
);
4651 /* For larger data types, we have to either emit dispatch_width many
4652 * MOVs or else fall back to doing indirects.
4654 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4655 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4657 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4662 case nir_intrinsic_quad_swap_diagonal
: {
4663 const fs_reg value
= get_nir_src(instr
->src
[0]);
4664 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4665 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4666 const fs_reg tmp
= bld
.vgrf(value
.type
);
4667 const fs_builder ubld
= bld
.exec_all();
4668 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4669 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4670 bld
.MOV(retype(dest
, value
.type
), tmp
);
4672 /* For larger data types, we have to either emit dispatch_width many
4673 * MOVs or else fall back to doing indirects.
4675 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4676 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4678 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4683 case nir_intrinsic_reduce
: {
4684 fs_reg src
= get_nir_src(instr
->src
[0]);
4685 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4686 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4687 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4688 cluster_size
= dispatch_width
;
4690 /* Figure out the source type */
4691 src
.type
= brw_type_for_nir_type(devinfo
,
4692 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4693 nir_src_bit_size(instr
->src
[0])));
4695 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4696 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4697 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4699 /* Set up a register for all of our scratching around and initialize it
4700 * to reduction operation's identity value.
4702 fs_reg scan
= bld
.vgrf(src
.type
);
4703 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4705 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4707 dest
.type
= src
.type
;
4708 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4709 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4710 * the distance between clusters is at least 2 GRFs. In this case,
4711 * we don't need the weird striding of the CLUSTER_BROADCAST
4712 * instruction and can just do regular MOVs.
4714 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4715 const unsigned groups
=
4716 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4717 const unsigned group_size
= dispatch_width
/ groups
;
4718 for (unsigned i
= 0; i
< groups
; i
++) {
4719 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4720 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4721 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4722 component(scan
, comp
));
4725 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4726 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4731 case nir_intrinsic_inclusive_scan
:
4732 case nir_intrinsic_exclusive_scan
: {
4733 fs_reg src
= get_nir_src(instr
->src
[0]);
4734 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4736 /* Figure out the source type */
4737 src
.type
= brw_type_for_nir_type(devinfo
,
4738 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4739 nir_src_bit_size(instr
->src
[0])));
4741 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4742 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4743 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4745 /* Set up a register for all of our scratching around and initialize it
4746 * to reduction operation's identity value.
4748 fs_reg scan
= bld
.vgrf(src
.type
);
4749 const fs_builder allbld
= bld
.exec_all();
4750 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4752 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4753 /* Exclusive scan is a bit harder because we have to do an annoying
4754 * shift of the contents before we can begin. To make things worse,
4755 * we can't do this with a normal stride; we have to use indirects.
4757 fs_reg shifted
= bld
.vgrf(src
.type
);
4758 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4759 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4761 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4762 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4766 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4768 bld
.MOV(retype(dest
, src
.type
), scan
);
4772 case nir_intrinsic_begin_fragment_shader_ordering
:
4773 case nir_intrinsic_begin_invocation_interlock
: {
4774 const fs_builder ubld
= bld
.group(8, 0);
4775 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4777 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4783 case nir_intrinsic_end_invocation_interlock
: {
4784 /* We don't need to do anything here */
4789 unreachable("unknown intrinsic");
4794 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4795 int op
, nir_intrinsic_instr
*instr
)
4797 if (stage
== MESA_SHADER_FRAGMENT
)
4798 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4801 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4802 dest
= get_nir_dest(instr
->dest
);
4804 fs_reg surface
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4805 fs_reg offset
= get_nir_src(instr
->src
[1]);
4807 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4808 data1
= get_nir_src(instr
->src
[2]);
4810 if (op
== BRW_AOP_CMPWR
)
4811 data2
= get_nir_src(instr
->src
[3]);
4813 /* Emit the actual atomic operation */
4815 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4817 1 /* dims */, 1 /* rsize */,
4819 BRW_PREDICATE_NONE
);
4820 dest
.type
= atomic_result
.type
;
4821 bld
.MOV(dest
, atomic_result
);
4825 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4826 int op
, nir_intrinsic_instr
*instr
)
4828 if (stage
== MESA_SHADER_FRAGMENT
)
4829 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4832 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4833 dest
= get_nir_dest(instr
->dest
);
4835 fs_reg surface
= get_nir_ssbo_intrinsic_index(bld
, instr
);
4836 fs_reg offset
= get_nir_src(instr
->src
[1]);
4837 fs_reg data1
= get_nir_src(instr
->src
[2]);
4839 if (op
== BRW_AOP_FCMPWR
)
4840 data2
= get_nir_src(instr
->src
[3]);
4842 /* Emit the actual atomic operation */
4844 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4846 1 /* dims */, 1 /* rsize */,
4848 BRW_PREDICATE_NONE
);
4849 dest
.type
= atomic_result
.type
;
4850 bld
.MOV(dest
, atomic_result
);
4854 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4855 int op
, nir_intrinsic_instr
*instr
)
4858 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4859 dest
= get_nir_dest(instr
->dest
);
4861 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4864 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4865 data1
= get_nir_src(instr
->src
[1]);
4867 if (op
== BRW_AOP_CMPWR
)
4868 data2
= get_nir_src(instr
->src
[2]);
4870 /* Get the offset */
4871 if (nir_src_is_const(instr
->src
[0])) {
4872 offset
= brw_imm_ud(instr
->const_index
[0] +
4873 nir_src_as_uint(instr
->src
[0]));
4875 offset
= vgrf(glsl_type::uint_type
);
4877 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4878 brw_imm_ud(instr
->const_index
[0]));
4881 /* Emit the actual atomic operation operation */
4883 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4885 1 /* dims */, 1 /* rsize */,
4887 BRW_PREDICATE_NONE
);
4888 dest
.type
= atomic_result
.type
;
4889 bld
.MOV(dest
, atomic_result
);
4893 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4894 int op
, nir_intrinsic_instr
*instr
)
4897 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4898 dest
= get_nir_dest(instr
->dest
);
4900 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4902 fs_reg data1
= get_nir_src(instr
->src
[1]);
4904 if (op
== BRW_AOP_FCMPWR
)
4905 data2
= get_nir_src(instr
->src
[2]);
4907 /* Get the offset */
4908 if (nir_src_is_const(instr
->src
[0])) {
4909 offset
= brw_imm_ud(instr
->const_index
[0] +
4910 nir_src_as_uint(instr
->src
[0]));
4912 offset
= vgrf(glsl_type::uint_type
);
4914 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4915 brw_imm_ud(instr
->const_index
[0]));
4918 /* Emit the actual atomic operation operation */
4920 fs_reg atomic_result
= emit_untyped_atomic_float(bld
, surface
, offset
,
4922 1 /* dims */, 1 /* rsize */,
4924 BRW_PREDICATE_NONE
);
4925 dest
.type
= atomic_result
.type
;
4926 bld
.MOV(dest
, atomic_result
);
4930 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4932 unsigned texture
= instr
->texture_index
;
4933 unsigned sampler
= instr
->sampler_index
;
4935 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4937 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4938 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4940 int lod_components
= 0;
4942 /* The hardware requires a LOD for buffer textures */
4943 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4944 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4946 uint32_t header_bits
= 0;
4947 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4948 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4949 switch (instr
->src
[i
].src_type
) {
4950 case nir_tex_src_bias
:
4951 srcs
[TEX_LOGICAL_SRC_LOD
] =
4952 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4954 case nir_tex_src_comparator
:
4955 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4957 case nir_tex_src_coord
:
4958 switch (instr
->op
) {
4960 case nir_texop_txf_ms
:
4961 case nir_texop_txf_ms_mcs
:
4962 case nir_texop_samples_identical
:
4963 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4966 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4970 case nir_tex_src_ddx
:
4971 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4972 lod_components
= nir_tex_instr_src_size(instr
, i
);
4974 case nir_tex_src_ddy
:
4975 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4977 case nir_tex_src_lod
:
4978 switch (instr
->op
) {
4980 srcs
[TEX_LOGICAL_SRC_LOD
] =
4981 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4984 srcs
[TEX_LOGICAL_SRC_LOD
] =
4985 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4988 srcs
[TEX_LOGICAL_SRC_LOD
] =
4989 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4993 case nir_tex_src_ms_index
:
4994 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4997 case nir_tex_src_offset
: {
4998 nir_const_value
*const_offset
=
4999 nir_src_as_const_value(instr
->src
[i
].src
);
5000 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
5001 unsigned offset_bits
= 0;
5003 brw_texture_offset(const_offset
->i32
,
5004 nir_tex_instr_src_size(instr
, i
),
5006 header_bits
|= offset_bits
;
5008 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5009 retype(src
, BRW_REGISTER_TYPE_D
);
5014 case nir_tex_src_projector
:
5015 unreachable("should be lowered");
5017 case nir_tex_src_texture_offset
: {
5018 /* Figure out the highest possible texture index and mark it as used */
5019 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
5020 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
5021 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
5023 max_used
+= stage_prog_data
->binding_table
.texture_start
;
5025 brw_mark_surface_used(prog_data
, max_used
);
5027 /* Emit code to evaluate the actual indexing expression */
5028 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5029 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5030 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5034 case nir_tex_src_sampler_offset
: {
5035 /* Emit code to evaluate the actual indexing expression */
5036 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5037 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5038 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5042 case nir_tex_src_ms_mcs
:
5043 assert(instr
->op
== nir_texop_txf_ms
);
5044 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5047 case nir_tex_src_plane
: {
5048 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5049 const uint32_t texture_index
=
5050 instr
->texture_index
+
5051 stage_prog_data
->binding_table
.plane_start
[plane
] -
5052 stage_prog_data
->binding_table
.texture_start
;
5054 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5059 unreachable("unknown texture source");
5063 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5064 (instr
->op
== nir_texop_txf_ms
||
5065 instr
->op
== nir_texop_samples_identical
)) {
5066 if (devinfo
->gen
>= 7 &&
5067 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5068 srcs
[TEX_LOGICAL_SRC_MCS
] =
5069 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5070 instr
->coord_components
,
5071 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5073 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5077 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5078 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5081 switch (instr
->op
) {
5083 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5084 SHADER_OPCODE_TXL_LOGICAL
);
5087 opcode
= FS_OPCODE_TXB_LOGICAL
;
5090 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5093 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5096 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5098 case nir_texop_txf_ms
:
5099 if ((key_tex
->msaa_16
& (1 << sampler
)))
5100 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5102 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5104 case nir_texop_txf_ms_mcs
:
5105 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5107 case nir_texop_query_levels
:
5109 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5112 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5115 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5116 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5118 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5120 case nir_texop_texture_samples
:
5121 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5123 case nir_texop_samples_identical
: {
5124 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5126 /* If mcs is an immediate value, it means there is no MCS. In that case
5127 * just return false.
5129 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5130 bld
.MOV(dst
, brw_imm_ud(0u));
5131 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5132 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5133 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5134 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5135 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5137 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5138 BRW_CONDITIONAL_EQ
);
5143 unreachable("unknown texture opcode");
5146 if (instr
->op
== nir_texop_tg4
) {
5147 if (instr
->component
== 1 &&
5148 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5149 /* gather4 sampler is broken for green channel on RG32F --
5150 * we must ask for blue instead.
5152 header_bits
|= 2 << 16;
5154 header_bits
|= instr
->component
<< 16;
5158 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5159 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5160 inst
->offset
= header_bits
;
5162 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5163 if (devinfo
->gen
>= 9 &&
5164 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5165 unsigned write_mask
= instr
->dest
.is_ssa
?
5166 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5167 (1 << dest_size
) - 1;
5168 assert(write_mask
!= 0); /* dead code should have been eliminated */
5169 inst
->size_written
= util_last_bit(write_mask
) *
5170 inst
->dst
.component_size(inst
->exec_size
);
5172 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5175 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5176 inst
->shadow_compare
= true;
5178 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5179 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5182 for (unsigned i
= 0; i
< dest_size
; i
++)
5183 nir_dest
[i
] = offset(dst
, bld
, i
);
5185 if (instr
->op
== nir_texop_query_levels
) {
5186 /* # levels is in .w */
5187 nir_dest
[0] = offset(dst
, bld
, 3);
5188 } else if (instr
->op
== nir_texop_txs
&&
5189 dest_size
>= 3 && devinfo
->gen
< 7) {
5190 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5191 fs_reg depth
= offset(dst
, bld
, 2);
5192 nir_dest
[2] = vgrf(glsl_type::int_type
);
5193 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5196 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5200 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5202 switch (instr
->type
) {
5203 case nir_jump_break
:
5204 bld
.emit(BRW_OPCODE_BREAK
);
5206 case nir_jump_continue
:
5207 bld
.emit(BRW_OPCODE_CONTINUE
);
5209 case nir_jump_return
:
5211 unreachable("unknown jump");
5216 * This helper takes a source register and un/shuffles it into the destination
5219 * If source type size is smaller than destination type size the operation
5220 * needed is a component shuffle. The opposite case would be an unshuffle. If
5221 * source/destination type size is equal a shuffle is done that would be
5222 * equivalent to a simple MOV.
5224 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5225 * components .xyz 16-bit vector on SIMD8 would be.
5227 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5228 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5230 * This helper will return the following 2 32-bit components with the 16-bit
5233 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5234 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5236 * For unshuffle, the example would be the opposite, a 64-bit type source
5237 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5240 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5241 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5242 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5243 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5245 * The returned result would be the following 4 32-bit components unshuffled:
5247 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5248 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5249 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5250 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5252 * - Source and destination register must not be overlapped.
5253 * - components units are measured in terms of the smaller type between
5254 * source and destination because we are un/shuffling the smaller
5255 * components from/into the bigger ones.
5256 * - first_component parameter allows skipping source components.
5259 shuffle_src_to_dst(const fs_builder
&bld
,
5262 uint32_t first_component
,
5263 uint32_t components
)
5265 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5266 assert(!regions_overlap(dst
,
5267 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5268 offset(src
, bld
, first_component
),
5269 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5270 for (unsigned i
= 0; i
< components
; i
++) {
5271 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5272 offset(src
, bld
, i
+ first_component
));
5274 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5275 /* Source is shuffled into destination */
5276 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5277 assert(!regions_overlap(dst
,
5278 type_sz(dst
.type
) * bld
.dispatch_width() *
5279 DIV_ROUND_UP(components
, size_ratio
),
5280 offset(src
, bld
, first_component
),
5281 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5283 brw_reg_type shuffle_type
=
5284 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5285 BRW_REGISTER_TYPE_D
);
5286 for (unsigned i
= 0; i
< components
; i
++) {
5287 fs_reg shuffle_component_i
=
5288 subscript(offset(dst
, bld
, i
/ size_ratio
),
5289 shuffle_type
, i
% size_ratio
);
5290 bld
.MOV(shuffle_component_i
,
5291 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5294 /* Source is unshuffled into destination */
5295 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5296 assert(!regions_overlap(dst
,
5297 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5298 offset(src
, bld
, first_component
/ size_ratio
),
5299 type_sz(src
.type
) * bld
.dispatch_width() *
5300 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5303 brw_reg_type shuffle_type
=
5304 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5305 BRW_REGISTER_TYPE_D
);
5306 for (unsigned i
= 0; i
< components
; i
++) {
5307 fs_reg shuffle_component_i
=
5308 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5309 shuffle_type
, (first_component
+ i
) % size_ratio
);
5310 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5311 shuffle_component_i
);
5317 shuffle_from_32bit_read(const fs_builder
&bld
,
5320 uint32_t first_component
,
5321 uint32_t components
)
5323 assert(type_sz(src
.type
) == 4);
5325 /* This function takes components in units of the destination type while
5326 * shuffle_src_to_dst takes components in units of the smallest type
5328 if (type_sz(dst
.type
) > 4) {
5329 assert(type_sz(dst
.type
) == 8);
5330 first_component
*= 2;
5334 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5338 shuffle_for_32bit_write(const fs_builder
&bld
,
5340 uint32_t first_component
,
5341 uint32_t components
)
5343 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5344 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5345 /* This function takes components in units of the source type while
5346 * shuffle_src_to_dst takes components in units of the smallest type
5348 if (type_sz(src
.type
) > 4) {
5349 assert(type_sz(src
.type
) == 8);
5350 first_component
*= 2;
5354 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5360 setup_imm_df(const fs_builder
&bld
, double v
)
5362 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5363 assert(devinfo
->gen
>= 7);
5365 if (devinfo
->gen
>= 8)
5366 return brw_imm_df(v
);
5368 /* gen7.5 does not support DF immediates straighforward but the DIM
5369 * instruction allows to set the 64-bit immediate value.
5371 if (devinfo
->is_haswell
) {
5372 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5373 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5374 ubld
.DIM(dst
, brw_imm_df(v
));
5375 return component(dst
, 0);
5378 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5379 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5380 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5382 * Alternatively, we could also produce a normal VGRF (without stride 0)
5383 * by writing to all the channels in the VGRF, however, that would hit the
5384 * gen7 bug where we have to split writes that span more than 1 register
5385 * into instructions with a width of 4 (otherwise the write to the second
5386 * register written runs into an execmask hardware bug) which isn't very
5399 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5400 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5401 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5402 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5404 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5408 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5410 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5411 bld
.MOV(tmp
, brw_imm_w(v
));
5416 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5418 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5419 bld
.MOV(tmp
, brw_imm_uw(v
));