2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 emit_shader_float_controls_execution_mode();
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
44 nir_emit_system_values();
46 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
50 fs_visitor::nir_setup_outputs()
52 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
55 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
57 /* Calculate the size of output registers in a separate pass, before
58 * allocating them. With ARB_enhanced_layouts, multiple output variables
59 * may occupy the same slot, but have different type sizes.
61 nir_foreach_variable(var
, &nir
->outputs
) {
62 const int loc
= var
->data
.driver_location
;
63 const unsigned var_vec4s
=
64 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
65 : type_size_vec4(var
->type
, true);
66 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
69 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
70 if (vec4s
[loc
] == 0) {
75 unsigned reg_size
= vec4s
[loc
];
77 /* Check if there are any ranges that start within this range and extend
78 * past it. If so, include them in this allocation.
80 for (unsigned i
= 1; i
< reg_size
; i
++)
81 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
83 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
84 for (unsigned i
= 0; i
< reg_size
; i
++)
85 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
92 fs_visitor::nir_setup_uniforms()
94 /* Only the first compile gets to set up uniforms. */
95 if (push_constant_loc
) {
96 assert(pull_constant_loc
);
100 uniforms
= nir
->num_uniforms
/ 4;
102 if (stage
== MESA_SHADER_COMPUTE
) {
103 /* Add a uniform for the thread local id. It must be the last uniform
106 assert(uniforms
== prog_data
->nr_params
);
107 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
108 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
109 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
114 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
118 nir_foreach_instr(instr
, block
) {
119 if (instr
->type
!= nir_instr_type_intrinsic
)
122 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
123 switch (intrin
->intrinsic
) {
124 case nir_intrinsic_load_vertex_id
:
125 case nir_intrinsic_load_base_vertex
:
126 unreachable("should be lowered by nir_lower_system_values().");
128 case nir_intrinsic_load_vertex_id_zero_base
:
129 case nir_intrinsic_load_is_indexed_draw
:
130 case nir_intrinsic_load_first_vertex
:
131 case nir_intrinsic_load_instance_id
:
132 case nir_intrinsic_load_base_instance
:
133 case nir_intrinsic_load_draw_id
:
134 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
136 case nir_intrinsic_load_invocation_id
:
137 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
139 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
140 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
141 if (reg
->file
== BAD_FILE
) {
142 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
143 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
144 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
145 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
150 case nir_intrinsic_load_sample_pos
:
151 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
152 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
153 if (reg
->file
== BAD_FILE
)
154 *reg
= *v
->emit_samplepos_setup();
157 case nir_intrinsic_load_sample_id
:
158 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
159 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
160 if (reg
->file
== BAD_FILE
)
161 *reg
= *v
->emit_sampleid_setup();
164 case nir_intrinsic_load_sample_mask_in
:
165 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
166 assert(v
->devinfo
->gen
>= 7);
167 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
168 if (reg
->file
== BAD_FILE
)
169 *reg
= *v
->emit_samplemaskin_setup();
172 case nir_intrinsic_load_work_group_id
:
173 assert(v
->stage
== MESA_SHADER_COMPUTE
);
174 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
175 if (reg
->file
== BAD_FILE
)
176 *reg
= *v
->emit_cs_work_group_id_setup();
179 case nir_intrinsic_load_helper_invocation
:
180 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
181 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
182 if (reg
->file
== BAD_FILE
) {
183 const fs_builder abld
=
184 v
->bld
.annotate("gl_HelperInvocation", NULL
);
186 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
187 * pixel mask is in g1.7 of the thread payload.
189 * We move the per-channel pixel enable bit to the low bit of each
190 * channel by shifting the byte containing the pixel mask by the
191 * vector immediate 0x76543210UV.
193 * The region of <1,8,0> reads only 1 byte (the pixel masks for
194 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
195 * masks for 2 and 3) in SIMD16.
197 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
199 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
200 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
201 hbld
.SHR(offset(shifted
, hbld
, i
),
202 stride(retype(brw_vec1_grf(1 + i
, 7),
203 BRW_REGISTER_TYPE_UB
),
205 brw_imm_v(0x76543210));
208 /* A set bit in the pixel mask means the channel is enabled, but
209 * that is the opposite of gl_HelperInvocation so we need to invert
212 * The negate source-modifier bit of logical instructions on Gen8+
213 * performs 1's complement negation, so we can use that instead of
216 fs_reg inverted
= negate(shifted
);
217 if (v
->devinfo
->gen
< 8) {
218 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
219 abld
.NOT(inverted
, shifted
);
222 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
223 * with 1 and negating.
225 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
226 abld
.AND(anded
, inverted
, brw_imm_uw(1));
228 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
229 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
243 fs_visitor::nir_emit_system_values()
245 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
246 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
247 nir_system_values
[i
] = fs_reg();
250 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
251 * never end up using it.
254 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
255 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
256 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
258 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
259 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
260 if (dispatch_width
> 8)
261 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
262 if (dispatch_width
> 16) {
263 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
264 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
268 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
269 nir_foreach_block(block
, impl
)
270 emit_system_values_block(block
, this);
274 * Returns a type based on a reference_type (word, float, half-float) and a
277 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
279 * @FIXME: 64-bit return types are always DF on integer types to maintain
280 * compability with uses of DF previously to the introduction of int64
284 brw_reg_type_from_bit_size(const unsigned bit_size
,
285 const brw_reg_type reference_type
)
287 switch(reference_type
) {
288 case BRW_REGISTER_TYPE_HF
:
289 case BRW_REGISTER_TYPE_F
:
290 case BRW_REGISTER_TYPE_DF
:
293 return BRW_REGISTER_TYPE_HF
;
295 return BRW_REGISTER_TYPE_F
;
297 return BRW_REGISTER_TYPE_DF
;
299 unreachable("Invalid bit size");
301 case BRW_REGISTER_TYPE_B
:
302 case BRW_REGISTER_TYPE_W
:
303 case BRW_REGISTER_TYPE_D
:
304 case BRW_REGISTER_TYPE_Q
:
307 return BRW_REGISTER_TYPE_B
;
309 return BRW_REGISTER_TYPE_W
;
311 return BRW_REGISTER_TYPE_D
;
313 return BRW_REGISTER_TYPE_Q
;
315 unreachable("Invalid bit size");
317 case BRW_REGISTER_TYPE_UB
:
318 case BRW_REGISTER_TYPE_UW
:
319 case BRW_REGISTER_TYPE_UD
:
320 case BRW_REGISTER_TYPE_UQ
:
323 return BRW_REGISTER_TYPE_UB
;
325 return BRW_REGISTER_TYPE_UW
;
327 return BRW_REGISTER_TYPE_UD
;
329 return BRW_REGISTER_TYPE_UQ
;
331 unreachable("Invalid bit size");
334 unreachable("Unknown type");
339 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
341 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
342 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
343 nir_locals
[i
] = fs_reg();
346 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
347 unsigned array_elems
=
348 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
349 unsigned size
= array_elems
* reg
->num_components
;
350 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
351 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
352 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
355 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
358 nir_emit_cf_list(&impl
->body
);
362 fs_visitor::nir_emit_cf_list(exec_list
*list
)
364 exec_list_validate(list
);
365 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
366 switch (node
->type
) {
368 nir_emit_if(nir_cf_node_as_if(node
));
371 case nir_cf_node_loop
:
372 nir_emit_loop(nir_cf_node_as_loop(node
));
375 case nir_cf_node_block
:
376 nir_emit_block(nir_cf_node_as_block(node
));
380 unreachable("Invalid CFG node block");
386 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
391 /* If the condition has the form !other_condition, use other_condition as
392 * the source, but invert the predicate on the if instruction.
394 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
395 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
396 assert(!cond
->src
[0].negate
);
397 assert(!cond
->src
[0].abs
);
400 cond_reg
= get_nir_src(cond
->src
[0].src
);
403 cond_reg
= get_nir_src(if_stmt
->condition
);
406 /* first, put the condition into f0 */
407 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
408 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
409 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
411 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
413 nir_emit_cf_list(&if_stmt
->then_list
);
415 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
416 bld
.emit(BRW_OPCODE_ELSE
);
417 nir_emit_cf_list(&if_stmt
->else_list
);
420 bld
.emit(BRW_OPCODE_ENDIF
);
422 if (devinfo
->gen
< 7)
423 limit_dispatch_width(16, "Non-uniform control flow unsupported "
428 fs_visitor::nir_emit_loop(nir_loop
*loop
)
430 bld
.emit(BRW_OPCODE_DO
);
432 nir_emit_cf_list(&loop
->body
);
434 bld
.emit(BRW_OPCODE_WHILE
);
436 if (devinfo
->gen
< 7)
437 limit_dispatch_width(16, "Non-uniform control flow unsupported "
442 fs_visitor::nir_emit_block(nir_block
*block
)
444 nir_foreach_instr(instr
, block
) {
445 nir_emit_instr(instr
);
450 fs_visitor::nir_emit_instr(nir_instr
*instr
)
452 const fs_builder abld
= bld
.annotate(NULL
, instr
);
454 switch (instr
->type
) {
455 case nir_instr_type_alu
:
456 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
459 case nir_instr_type_deref
:
460 unreachable("All derefs should've been lowered");
463 case nir_instr_type_intrinsic
:
465 case MESA_SHADER_VERTEX
:
466 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_TESS_CTRL
:
469 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_TESS_EVAL
:
472 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_GEOMETRY
:
475 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
477 case MESA_SHADER_FRAGMENT
:
478 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
480 case MESA_SHADER_COMPUTE
:
481 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
484 unreachable("unsupported shader stage");
488 case nir_instr_type_tex
:
489 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
492 case nir_instr_type_load_const
:
493 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
496 case nir_instr_type_ssa_undef
:
497 /* We create a new VGRF for undefs on every use (by handling
498 * them in get_nir_src()), rather than for each definition.
499 * This helps register coalescing eliminate MOVs from undef.
503 case nir_instr_type_jump
:
504 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
508 unreachable("unknown instruction type");
513 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
517 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
518 const fs_reg
&result
)
520 if (!instr
->src
[0].src
.is_ssa
||
521 !instr
->src
[0].src
.ssa
->parent_instr
)
524 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
527 nir_alu_instr
*src0
=
528 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
530 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
531 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
534 /* If either opcode has source modifiers, bail.
536 * TODO: We can potentially handle source modifiers if both of the opcodes
537 * we're combining are signed integers.
539 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
540 src0
->src
[0].abs
|| src0
->src
[0].negate
)
543 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
545 /* Element type to extract.*/
546 const brw_reg_type type
= brw_int_type(
547 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
548 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
550 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
551 op0
.type
= brw_type_for_nir_type(devinfo
,
552 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
553 nir_src_bit_size(src0
->src
[0].src
)));
554 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
556 set_saturate(instr
->dest
.saturate
,
557 bld
.MOV(result
, subscript(op0
, type
, element
)));
562 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
563 const fs_reg
&result
)
565 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
566 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
569 if (!nir_src_is_const(instr
->src
[1].src
) ||
570 !nir_src_is_const(instr
->src
[2].src
))
573 const float value1
= nir_src_as_float(instr
->src
[1].src
);
574 const float value2
= nir_src_as_float(instr
->src
[2].src
);
575 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
578 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
579 assert(value1
== -value2
);
581 fs_reg tmp
= vgrf(glsl_type::int_type
);
583 if (devinfo
->gen
>= 6) {
584 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
585 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
587 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
589 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
590 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
592 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
594 * This negation looks like it's safe in practice, because bits 0:4 will
595 * surely be TRIANGLES
598 if (value1
== -1.0f
) {
602 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
603 g0
, brw_imm_uw(0x3f80));
605 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
606 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
608 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
610 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
611 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
613 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
615 * This negation looks like it's safe in practice, because bits 0:4 will
616 * surely be TRIANGLES
619 if (value1
== -1.0f
) {
623 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
625 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
631 emit_find_msb_using_lzd(const fs_builder
&bld
,
632 const fs_reg
&result
,
640 /* LZD of an absolute value source almost always does the right
641 * thing. There are two problem values:
643 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
644 * 0. However, findMSB(int(0x80000000)) == 30.
646 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
647 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
649 * For a value of zero or negative one, -1 will be returned.
651 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
652 * findMSB(-(1<<x)) should return x-1.
654 * For all negative number cases, including 0x80000000 and
655 * 0xffffffff, the correct value is obtained from LZD if instead of
656 * negating the (already negative) value the logical-not is used. A
657 * conditonal logical-not can be achieved in two instructions.
659 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
661 bld
.ASR(temp
, src
, brw_imm_d(31));
662 bld
.XOR(temp
, temp
, src
);
665 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
666 retype(temp
, BRW_REGISTER_TYPE_UD
));
668 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
669 * from the LSB side. Subtract the result from 31 to convert the MSB
670 * count into an LSB count. If no bits are set, LZD will return 32.
671 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
673 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
674 inst
->src
[0].negate
= true;
678 brw_rnd_mode_from_nir_op (const nir_op op
) {
680 case nir_op_f2f16_rtz
:
681 return BRW_RND_MODE_RTZ
;
682 case nir_op_f2f16_rtne
:
683 return BRW_RND_MODE_RTNE
;
685 unreachable("Operation doesn't support rounding mode");
690 brw_rnd_mode_from_execution_mode(unsigned execution_mode
)
692 if (nir_has_any_rounding_mode_rtne(execution_mode
))
693 return BRW_RND_MODE_RTNE
;
694 if (nir_has_any_rounding_mode_rtz(execution_mode
))
695 return BRW_RND_MODE_RTZ
;
696 return BRW_RND_MODE_UNSPECIFIED
;
700 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
701 nir_alu_instr
*instr
,
706 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
708 result
.type
= brw_type_for_nir_type(devinfo
,
709 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
710 nir_dest_bit_size(instr
->dest
.dest
)));
712 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
713 op
[i
] = get_nir_src(instr
->src
[i
].src
);
714 op
[i
].type
= brw_type_for_nir_type(devinfo
,
715 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
716 nir_src_bit_size(instr
->src
[i
].src
)));
717 op
[i
].abs
= instr
->src
[i
].abs
;
718 op
[i
].negate
= instr
->src
[i
].negate
;
721 /* Move and vecN instrutions may still be vectored. Return the raw,
722 * vectored source and destination so that fs_visitor::nir_emit_alu can
723 * handle it. Other callers should not have to handle these kinds of
736 /* At this point, we have dealt with any instruction that operates on
737 * more than a single channel. Therefore, we can just adjust the source
738 * and destination registers for that channel and emit the instruction.
740 unsigned channel
= 0;
741 if (nir_op_infos
[instr
->op
].output_size
== 0) {
742 /* Since NIR is doing the scalarizing for us, we should only ever see
743 * vectorized operations with a single channel.
745 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
746 channel
= ffs(instr
->dest
.write_mask
) - 1;
748 result
= offset(result
, bld
, channel
);
751 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
752 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
753 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
760 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
763 for (unsigned i
= 0; i
< 2; i
++) {
764 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
766 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
767 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
768 /* The source of the inot is now the source of instr. */
769 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
771 assert(!op
[i
].negate
);
774 op
[i
] = resolve_source_modifiers(op
[i
]);
780 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
782 nir_alu_instr
*instr
)
784 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
787 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
789 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
792 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
793 * of valid size-changing combinations is a bit more complex.
795 * The source restriction is just because I was lazy about generating the
798 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
799 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
802 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
803 * this is float(1 + a).
807 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
809 /* Ignore the saturate modifier, if there is one. The result of the
810 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
812 bld
.ADD(result
, op
, brw_imm_d(1));
818 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
820 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
821 * the source of \c instr that is a \c nir_op_fsign.
824 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
825 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
829 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
830 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
832 if (instr
->op
!= nir_op_fsign
) {
833 const nir_alu_instr
*const fsign_instr
=
834 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
836 assert(!fsign_instr
->dest
.saturate
);
838 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
839 * fsign_src] has the other multiply source. This must be rearranged so
840 * that op[0] is the source of the fsign op[1] is the other multiply
846 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
848 const nir_alu_type t
=
849 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
850 nir_src_bit_size(fsign_instr
->src
[0].src
));
852 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
853 op
[0].abs
= fsign_instr
->src
[0].abs
;
854 op
[0].negate
= fsign_instr
->src
[0].negate
;
856 unsigned channel
= 0;
857 if (nir_op_infos
[instr
->op
].output_size
== 0) {
858 /* Since NIR is doing the scalarizing for us, we should only ever see
859 * vectorized operations with a single channel.
861 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
862 channel
= ffs(instr
->dest
.write_mask
) - 1;
865 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
867 assert(!instr
->dest
.saturate
);
871 /* Straightforward since the source can be assumed to be either strictly
872 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
874 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
876 if (instr
->op
== nir_op_fsign
) {
877 inst
= (op
[0].negate
)
878 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
879 : bld
.MOV(result
, brw_imm_f(1.0f
));
881 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
882 inst
= bld
.MOV(result
, op
[1]);
885 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
886 } else if (type_sz(op
[0].type
) == 2) {
887 /* AND(val, 0x8000) gives the sign bit.
889 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
891 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
892 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
894 op
[0].type
= BRW_REGISTER_TYPE_UW
;
895 result
.type
= BRW_REGISTER_TYPE_UW
;
896 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
898 if (instr
->op
== nir_op_fsign
)
899 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
901 /* Use XOR here to get the result sign correct. */
902 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
905 inst
->predicate
= BRW_PREDICATE_NORMAL
;
906 } else if (type_sz(op
[0].type
) == 4) {
907 /* AND(val, 0x80000000) gives the sign bit.
909 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
912 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
914 op
[0].type
= BRW_REGISTER_TYPE_UD
;
915 result
.type
= BRW_REGISTER_TYPE_UD
;
916 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
918 if (instr
->op
== nir_op_fsign
)
919 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
921 /* Use XOR here to get the result sign correct. */
922 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
925 inst
->predicate
= BRW_PREDICATE_NORMAL
;
927 /* For doubles we do the same but we need to consider:
929 * - 2-src instructions can't operate with 64-bit immediates
930 * - The sign is encoded in the high 32-bit of each DF
931 * - We need to produce a DF result.
934 fs_reg zero
= vgrf(glsl_type::double_type
);
935 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
936 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
938 bld
.MOV(result
, zero
);
940 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
941 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
942 brw_imm_ud(0x80000000u
));
944 if (instr
->op
== nir_op_fsign
) {
945 set_predicate(BRW_PREDICATE_NORMAL
,
946 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
948 /* This could be done better in some cases. If the scale is an
949 * immediate with the low 32-bits all 0, emitting a separate XOR and
950 * OR would allow an algebraic optimization to remove the OR. There
951 * are currently zero instances of fsign(double(x))*IMM in shader-db
952 * or any test suite, so it is hard to care at this time.
954 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
955 inst
= bld
.XOR(result_int64
, result_int64
,
956 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
962 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
964 * Checks the operands of a \c nir_op_fmul to determine whether or not
965 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
967 * \param instr The multiplication instruction
969 * \param fsign_src The source of \c instr that may or may not be a
973 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
975 assert(instr
->op
== nir_op_fmul
);
977 nir_alu_instr
*const fsign_instr
=
978 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
982 * 1. instr->src[fsign_src] must be a nir_op_fsign.
983 * 2. The nir_op_fsign can only be used by this multiplication.
984 * 3. The source that is the nir_op_fsign does not have source modifiers.
985 * \c emit_fsign only examines the source modifiers of the source of the
988 * The nir_op_fsign must also not have the saturate modifier, but steps
989 * have already been taken (in nir_opt_algebraic) to ensure that.
991 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
992 is_used_once(fsign_instr
) &&
993 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
997 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
1000 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
1002 unsigned execution_mode
=
1003 bld
.shader
->nir
->info
.float_controls_execution_mode
;
1006 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
1008 switch (instr
->op
) {
1013 fs_reg temp
= result
;
1014 bool need_extra_copy
= false;
1015 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1016 if (!instr
->src
[i
].src
.is_ssa
&&
1017 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1018 need_extra_copy
= true;
1019 temp
= bld
.vgrf(result
.type
, 4);
1024 for (unsigned i
= 0; i
< 4; i
++) {
1025 if (!(instr
->dest
.write_mask
& (1 << i
)))
1028 if (instr
->op
== nir_op_mov
) {
1029 inst
= bld
.MOV(offset(temp
, bld
, i
),
1030 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1032 inst
= bld
.MOV(offset(temp
, bld
, i
),
1033 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1035 inst
->saturate
= instr
->dest
.saturate
;
1038 /* In this case the source and destination registers were the same,
1039 * so we need to insert an extra set of moves in order to deal with
1042 if (need_extra_copy
) {
1043 for (unsigned i
= 0; i
< 4; i
++) {
1044 if (!(instr
->dest
.write_mask
& (1 << i
)))
1047 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1055 if (optimize_extract_to_float(instr
, result
))
1057 inst
= bld
.MOV(result
, op
[0]);
1058 inst
->saturate
= instr
->dest
.saturate
;
1061 case nir_op_f2f16_rtne
:
1062 case nir_op_f2f16_rtz
:
1063 case nir_op_f2f16
: {
1064 brw_rnd_mode rnd
= BRW_RND_MODE_UNSPECIFIED
;
1066 if (nir_op_f2f16
== instr
->op
)
1067 rnd
= brw_rnd_mode_from_execution_mode(execution_mode
);
1069 rnd
= brw_rnd_mode_from_nir_op(instr
->op
);
1071 if (BRW_RND_MODE_UNSPECIFIED
!= rnd
)
1072 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(), brw_imm_d(rnd
));
1074 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1075 * on the HW gen, it is a special hw opcode or just a MOV, and
1076 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1078 * But if we want to use that opcode, we need to provide support on
1079 * different optimizations and lowerings. As right now HF support is
1080 * only for gen8+, it will be better to use directly the MOV, and use
1081 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1083 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1084 inst
= bld
.MOV(result
, op
[0]);
1085 inst
->saturate
= instr
->dest
.saturate
;
1096 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1098 op
[0].type
= BRW_REGISTER_TYPE_D
;
1099 op
[0].negate
= !op
[0].negate
;
1122 if (result
.type
== BRW_REGISTER_TYPE_B
||
1123 result
.type
== BRW_REGISTER_TYPE_UB
||
1124 result
.type
== BRW_REGISTER_TYPE_HF
)
1125 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1127 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1128 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1129 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1130 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1132 inst
= bld
.MOV(result
, op
[0]);
1133 inst
->saturate
= instr
->dest
.saturate
;
1137 inst
= bld
.MOV(result
, op
[0]);
1138 inst
->saturate
= true;
1143 op
[0].negate
= true;
1144 inst
= bld
.MOV(result
, op
[0]);
1145 if (instr
->op
== nir_op_fneg
)
1146 inst
->saturate
= instr
->dest
.saturate
;
1151 op
[0].negate
= false;
1153 inst
= bld
.MOV(result
, op
[0]);
1154 if (instr
->op
== nir_op_fabs
)
1155 inst
->saturate
= instr
->dest
.saturate
;
1159 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1161 brw_rnd_mode_from_execution_mode(execution_mode
);
1162 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1166 if (op
[0].type
== BRW_REGISTER_TYPE_HF
)
1167 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1169 inst
= bld
.MOV(result
, op
[0]);
1170 inst
->saturate
= instr
->dest
.saturate
;
1174 emit_fsign(bld
, instr
, result
, op
, 0);
1178 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1179 inst
->saturate
= instr
->dest
.saturate
;
1183 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1184 inst
->saturate
= instr
->dest
.saturate
;
1188 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1189 inst
->saturate
= instr
->dest
.saturate
;
1193 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1194 inst
->saturate
= instr
->dest
.saturate
;
1198 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1199 inst
->saturate
= instr
->dest
.saturate
;
1203 if (fs_key
->high_quality_derivatives
) {
1204 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1206 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1208 inst
->saturate
= instr
->dest
.saturate
;
1210 case nir_op_fddx_fine
:
1211 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1212 inst
->saturate
= instr
->dest
.saturate
;
1214 case nir_op_fddx_coarse
:
1215 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1216 inst
->saturate
= instr
->dest
.saturate
;
1219 if (fs_key
->high_quality_derivatives
) {
1220 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1222 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1224 inst
->saturate
= instr
->dest
.saturate
;
1226 case nir_op_fddy_fine
:
1227 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1228 inst
->saturate
= instr
->dest
.saturate
;
1230 case nir_op_fddy_coarse
:
1231 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1232 inst
->saturate
= instr
->dest
.saturate
;
1236 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1238 brw_rnd_mode_from_execution_mode(execution_mode
);
1239 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1244 inst
= bld
.ADD(result
, op
[0], op
[1]);
1245 inst
->saturate
= instr
->dest
.saturate
;
1248 case nir_op_uadd_sat
:
1249 inst
= bld
.ADD(result
, op
[0], op
[1]);
1250 inst
->saturate
= true;
1254 for (unsigned i
= 0; i
< 2; i
++) {
1255 if (can_fuse_fmul_fsign(instr
, i
)) {
1256 emit_fsign(bld
, instr
, result
, op
, i
);
1261 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1263 brw_rnd_mode_from_execution_mode(execution_mode
);
1264 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1268 inst
= bld
.MUL(result
, op
[0], op
[1]);
1269 inst
->saturate
= instr
->dest
.saturate
;
1272 case nir_op_imul_2x32_64
:
1273 case nir_op_umul_2x32_64
:
1274 bld
.MUL(result
, op
[0], op
[1]);
1278 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1279 bld
.MUL(result
, op
[0], op
[1]);
1282 case nir_op_imul_high
:
1283 case nir_op_umul_high
:
1284 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1285 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1290 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1291 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1294 case nir_op_uadd_carry
:
1295 unreachable("Should have been lowered by carry_to_arith().");
1297 case nir_op_usub_borrow
:
1298 unreachable("Should have been lowered by borrow_to_arith().");
1302 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1303 * appears that our hardware just does the right thing for signed
1306 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1307 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1311 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1312 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1314 /* Math instructions don't support conditional mod */
1315 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1316 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1318 /* Now, we need to determine if signs of the sources are different.
1319 * When we XOR the sources, the top bit is 0 if they are the same and 1
1320 * if they are different. We can then use a conditional modifier to
1321 * turn that into a predicate. This leads us to an XOR.l instruction.
1323 * Technically, according to the PRM, you're not allowed to use .l on a
1324 * XOR instruction. However, emperical experiments and Curro's reading
1325 * of the simulator source both indicate that it's safe.
1327 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1328 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1329 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1330 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1332 /* If the result of the initial remainder operation is non-zero and the
1333 * two sources have different signs, add in a copy of op[1] to get the
1334 * final integer modulus value.
1336 inst
= bld
.ADD(result
, result
, op
[1]);
1337 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1344 case nir_op_fne32
: {
1345 fs_reg dest
= result
;
1347 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1349 dest
= bld
.vgrf(op
[0].type
, 1);
1351 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1353 if (bit_size
> 32) {
1354 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1355 } else if(bit_size
< 32) {
1356 /* When we convert the result to 32-bit we need to be careful and do
1357 * it as a signed conversion to get sign extension (for 32-bit true)
1359 const brw_reg_type src_type
=
1360 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1362 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1372 case nir_op_ine32
: {
1373 fs_reg dest
= result
;
1375 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1376 * type. So we convert both operands for the comparison.
1379 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1380 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1382 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1384 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1386 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1387 brw_cmod_for_nir_comparison(instr
->op
));
1389 if (bit_size
> 32) {
1390 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1391 } else if (bit_size
< 32) {
1392 /* When we convert the result to 32-bit we need to be careful and do
1393 * it as a signed conversion to get sign extension (for 32-bit true)
1395 const brw_reg_type src_type
=
1396 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1398 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1404 if (devinfo
->gen
>= 8) {
1405 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1407 if (inot_src_instr
!= NULL
&&
1408 (inot_src_instr
->op
== nir_op_ior
||
1409 inot_src_instr
->op
== nir_op_ixor
||
1410 inot_src_instr
->op
== nir_op_iand
) &&
1411 !inot_src_instr
->src
[0].abs
&&
1412 !inot_src_instr
->src
[0].negate
&&
1413 !inot_src_instr
->src
[1].abs
&&
1414 !inot_src_instr
->src
[1].negate
) {
1415 /* The sources of the source logical instruction are now the
1416 * sources of the instruction that will be generated.
1418 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1419 resolve_inot_sources(bld
, inot_src_instr
, op
);
1421 /* Smash all of the sources and destination to be signed. This
1422 * doesn't matter for the operation of the instruction, but cmod
1423 * propagation fails on unsigned sources with negation (due to
1424 * fs_inst::can_do_cmod returning false).
1427 brw_type_for_nir_type(devinfo
,
1428 (nir_alu_type
)(nir_type_int
|
1429 nir_dest_bit_size(instr
->dest
.dest
)));
1431 brw_type_for_nir_type(devinfo
,
1432 (nir_alu_type
)(nir_type_int
|
1433 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1435 brw_type_for_nir_type(devinfo
,
1436 (nir_alu_type
)(nir_type_int
|
1437 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1439 /* For XOR, only invert one of the sources. Arbitrarily choose
1442 op
[0].negate
= !op
[0].negate
;
1443 if (inot_src_instr
->op
!= nir_op_ixor
)
1444 op
[1].negate
= !op
[1].negate
;
1446 switch (inot_src_instr
->op
) {
1448 bld
.AND(result
, op
[0], op
[1]);
1452 bld
.OR(result
, op
[0], op
[1]);
1456 bld
.XOR(result
, op
[0], op
[1]);
1460 unreachable("impossible opcode");
1463 op
[0] = resolve_source_modifiers(op
[0]);
1465 bld
.NOT(result
, op
[0]);
1468 if (devinfo
->gen
>= 8) {
1469 resolve_inot_sources(bld
, instr
, op
);
1471 bld
.XOR(result
, op
[0], op
[1]);
1474 if (devinfo
->gen
>= 8) {
1475 resolve_inot_sources(bld
, instr
, op
);
1477 bld
.OR(result
, op
[0], op
[1]);
1480 if (devinfo
->gen
>= 8) {
1481 resolve_inot_sources(bld
, instr
, op
);
1483 bld
.AND(result
, op
[0], op
[1]);
1489 case nir_op_b32all_fequal2
:
1490 case nir_op_b32all_iequal2
:
1491 case nir_op_b32all_fequal3
:
1492 case nir_op_b32all_iequal3
:
1493 case nir_op_b32all_fequal4
:
1494 case nir_op_b32all_iequal4
:
1495 case nir_op_b32any_fnequal2
:
1496 case nir_op_b32any_inequal2
:
1497 case nir_op_b32any_fnequal3
:
1498 case nir_op_b32any_inequal3
:
1499 case nir_op_b32any_fnequal4
:
1500 case nir_op_b32any_inequal4
:
1501 unreachable("Lowered by nir_lower_alu_reductions");
1503 case nir_op_fnoise1_1
:
1504 case nir_op_fnoise1_2
:
1505 case nir_op_fnoise1_3
:
1506 case nir_op_fnoise1_4
:
1507 case nir_op_fnoise2_1
:
1508 case nir_op_fnoise2_2
:
1509 case nir_op_fnoise2_3
:
1510 case nir_op_fnoise2_4
:
1511 case nir_op_fnoise3_1
:
1512 case nir_op_fnoise3_2
:
1513 case nir_op_fnoise3_3
:
1514 case nir_op_fnoise3_4
:
1515 case nir_op_fnoise4_1
:
1516 case nir_op_fnoise4_2
:
1517 case nir_op_fnoise4_3
:
1518 case nir_op_fnoise4_4
:
1519 unreachable("not reached: should be handled by lower_noise");
1522 unreachable("not reached: should be handled by ldexp_to_arith()");
1525 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1526 inst
->saturate
= instr
->dest
.saturate
;
1530 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1531 inst
->saturate
= instr
->dest
.saturate
;
1535 case nir_op_f2b32
: {
1536 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1537 if (bit_size
== 64) {
1538 /* two-argument instructions can't take 64-bit immediates */
1542 if (instr
->op
== nir_op_f2b32
) {
1543 zero
= vgrf(glsl_type::double_type
);
1544 tmp
= vgrf(glsl_type::double_type
);
1545 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1547 zero
= vgrf(glsl_type::int64_t_type
);
1548 tmp
= vgrf(glsl_type::int64_t_type
);
1549 bld
.MOV(zero
, brw_imm_q(0));
1552 /* A SIMD16 execution needs to be split in two instructions, so use
1553 * a vgrf instead of the flag register as dst so instruction splitting
1556 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1557 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1560 if (bit_size
== 32) {
1561 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1563 assert(bit_size
== 16);
1564 zero
= instr
->op
== nir_op_f2b32
?
1565 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1567 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1573 inst
= bld
.RNDZ(result
, op
[0]);
1574 inst
->saturate
= instr
->dest
.saturate
;
1577 case nir_op_fceil
: {
1578 op
[0].negate
= !op
[0].negate
;
1579 fs_reg temp
= vgrf(glsl_type::float_type
);
1580 bld
.RNDD(temp
, op
[0]);
1582 inst
= bld
.MOV(result
, temp
);
1583 inst
->saturate
= instr
->dest
.saturate
;
1587 inst
= bld
.RNDD(result
, op
[0]);
1588 inst
->saturate
= instr
->dest
.saturate
;
1591 inst
= bld
.FRC(result
, op
[0]);
1592 inst
->saturate
= instr
->dest
.saturate
;
1594 case nir_op_fround_even
:
1595 inst
= bld
.RNDE(result
, op
[0]);
1596 inst
->saturate
= instr
->dest
.saturate
;
1599 case nir_op_fquantize2f16
: {
1600 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1601 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1602 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1604 /* The destination stride must be at least as big as the source stride. */
1605 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1608 /* Check for denormal */
1609 fs_reg abs_src0
= op
[0];
1610 abs_src0
.abs
= true;
1611 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1613 /* Get the appropriately signed zero */
1614 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1615 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1616 brw_imm_ud(0x80000000));
1617 /* Do the actual F32 -> F16 -> F32 conversion */
1618 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1619 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1620 /* Select that or zero based on normal status */
1621 inst
= bld
.SEL(result
, zero
, tmp32
);
1622 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1623 inst
->saturate
= instr
->dest
.saturate
;
1630 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1631 inst
->saturate
= instr
->dest
.saturate
;
1637 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1638 inst
->saturate
= instr
->dest
.saturate
;
1641 case nir_op_pack_snorm_2x16
:
1642 case nir_op_pack_snorm_4x8
:
1643 case nir_op_pack_unorm_2x16
:
1644 case nir_op_pack_unorm_4x8
:
1645 case nir_op_unpack_snorm_2x16
:
1646 case nir_op_unpack_snorm_4x8
:
1647 case nir_op_unpack_unorm_2x16
:
1648 case nir_op_unpack_unorm_4x8
:
1649 case nir_op_unpack_half_2x16
:
1650 case nir_op_pack_half_2x16
:
1651 unreachable("not reached: should be handled by lower_packing_builtins");
1653 case nir_op_unpack_half_2x16_split_x_flush_to_zero
:
1654 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1656 case nir_op_unpack_half_2x16_split_x
:
1657 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1658 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1659 inst
->saturate
= instr
->dest
.saturate
;
1662 case nir_op_unpack_half_2x16_split_y_flush_to_zero
:
1663 assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
& execution_mode
);
1665 case nir_op_unpack_half_2x16_split_y
:
1666 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1667 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1668 inst
->saturate
= instr
->dest
.saturate
;
1671 case nir_op_pack_64_2x32_split
:
1672 case nir_op_pack_32_2x16_split
:
1673 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1676 case nir_op_unpack_64_2x32_split_x
:
1677 case nir_op_unpack_64_2x32_split_y
: {
1678 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1679 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1681 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1685 case nir_op_unpack_32_2x16_split_x
:
1686 case nir_op_unpack_32_2x16_split_y
: {
1687 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1688 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1690 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1695 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1696 inst
->saturate
= instr
->dest
.saturate
;
1699 case nir_op_bitfield_reverse
:
1700 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1701 bld
.BFREV(result
, op
[0]);
1704 case nir_op_bit_count
:
1705 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1706 bld
.CBIT(result
, op
[0]);
1709 case nir_op_ufind_msb
: {
1710 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1711 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1715 case nir_op_ifind_msb
: {
1716 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1718 if (devinfo
->gen
< 7) {
1719 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1721 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1723 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1724 * count from the LSB side. If FBH didn't return an error
1725 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1726 * count into an LSB count.
1728 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1730 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1731 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1732 inst
->src
[0].negate
= true;
1737 case nir_op_find_lsb
:
1738 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1740 if (devinfo
->gen
< 7) {
1741 fs_reg temp
= vgrf(glsl_type::int_type
);
1743 /* (x & -x) generates a value that consists of only the LSB of x.
1744 * For all powers of 2, findMSB(y) == findLSB(y).
1746 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1747 fs_reg negated_src
= src
;
1749 /* One must be negated, and the other must be non-negated. It
1750 * doesn't matter which is which.
1752 negated_src
.negate
= true;
1755 bld
.AND(temp
, src
, negated_src
);
1756 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1758 bld
.FBL(result
, op
[0]);
1762 case nir_op_ubitfield_extract
:
1763 case nir_op_ibitfield_extract
:
1764 unreachable("should have been lowered");
1767 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1768 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1771 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1772 bld
.BFI1(result
, op
[0], op
[1]);
1775 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1776 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1779 case nir_op_bitfield_insert
:
1780 unreachable("not reached: should have been lowered");
1783 bld
.SHL(result
, op
[0], op
[1]);
1786 bld
.ASR(result
, op
[0], op
[1]);
1789 bld
.SHR(result
, op
[0], op
[1]);
1793 bld
.ROL(result
, op
[0], op
[1]);
1796 bld
.ROR(result
, op
[0], op
[1]);
1799 case nir_op_pack_half_2x16_split
:
1800 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1804 if (nir_has_any_rounding_mode_enabled(execution_mode
)) {
1806 brw_rnd_mode_from_execution_mode(execution_mode
);
1807 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1811 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1812 inst
->saturate
= instr
->dest
.saturate
;
1816 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1817 inst
->saturate
= instr
->dest
.saturate
;
1820 case nir_op_b32csel
:
1821 if (optimize_frontfacing_ternary(instr
, result
))
1824 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1825 inst
= bld
.SEL(result
, op
[1], op
[2]);
1826 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1829 case nir_op_extract_u8
:
1830 case nir_op_extract_i8
: {
1831 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1836 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1837 * Use two instructions and a word or DWord intermediate integer type.
1839 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1840 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1842 if (instr
->op
== nir_op_extract_i8
) {
1843 /* If we need to sign extend, extract to a word first */
1844 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1845 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1846 bld
.MOV(result
, w_temp
);
1847 } else if (byte
& 1) {
1848 /* Extract the high byte from the word containing the desired byte
1852 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1855 /* Otherwise use an AND with 0xff and a word type */
1857 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1861 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1862 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1867 case nir_op_extract_u16
:
1868 case nir_op_extract_i16
: {
1869 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1870 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1871 bld
.MOV(result
, subscript(op
[0], type
, word
));
1876 unreachable("unhandled instruction");
1879 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1880 * to sign extend the low bit to 0/~0
1882 if (devinfo
->gen
<= 5 &&
1883 !result
.is_null() &&
1884 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1885 fs_reg masked
= vgrf(glsl_type::int_type
);
1886 bld
.AND(masked
, result
, brw_imm_d(1));
1887 masked
.negate
= true;
1888 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1893 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1894 nir_load_const_instr
*instr
)
1896 const brw_reg_type reg_type
=
1897 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1898 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1900 switch (instr
->def
.bit_size
) {
1902 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1903 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1907 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1908 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1912 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1913 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1917 assert(devinfo
->gen
>= 7);
1918 if (devinfo
->gen
== 7) {
1919 /* We don't get 64-bit integer types until gen8 */
1920 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1921 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1922 setup_imm_df(bld
, instr
->value
[i
].f64
));
1925 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1926 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1931 unreachable("Invalid bit size");
1934 nir_ssa_values
[instr
->def
.index
] = reg
;
1938 fs_visitor::get_nir_src(const nir_src
&src
)
1942 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1943 const brw_reg_type reg_type
=
1944 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1945 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1947 reg
= nir_ssa_values
[src
.ssa
->index
];
1950 /* We don't handle indirects on locals */
1951 assert(src
.reg
.indirect
== NULL
);
1952 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1953 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1956 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1957 /* The only 64-bit type available on gen7 is DF, so use that. */
1958 reg
.type
= BRW_REGISTER_TYPE_DF
;
1960 /* To avoid floating-point denorm flushing problems, set the type by
1961 * default to an integer type - instructions that need floating point
1962 * semantics will set this to F if they need to
1964 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1965 BRW_REGISTER_TYPE_D
);
1972 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1974 * This function should not be called on any value which may be 64 bits.
1975 * We could theoretically support 64-bit on gen8+ but we choose not to
1976 * because it wouldn't work in general (no gen7 support) and there are
1977 * enough restrictions in 64-bit immediates that you can't take the return
1978 * value and treat it the same as the result of get_nir_src().
1981 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1983 assert(nir_src_bit_size(src
) == 32);
1984 return nir_src_is_const(src
) ?
1985 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1989 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1992 const brw_reg_type reg_type
=
1993 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1994 dest
.ssa
.bit_size
== 8 ?
1995 BRW_REGISTER_TYPE_D
:
1996 BRW_REGISTER_TYPE_F
);
1997 nir_ssa_values
[dest
.ssa
.index
] =
1998 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1999 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
2000 return nir_ssa_values
[dest
.ssa
.index
];
2002 /* We don't handle indirects on locals */
2003 assert(dest
.reg
.indirect
== NULL
);
2004 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
2005 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
2010 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
2013 for (unsigned i
= 0; i
< 4; i
++) {
2014 if (!((wr_mask
>> i
) & 1))
2017 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
2018 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
2019 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
2020 if (new_inst
->src
[j
].file
== VGRF
)
2021 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
2028 emit_pixel_interpolater_send(const fs_builder
&bld
,
2033 glsl_interp_mode interpolation
)
2035 struct brw_wm_prog_data
*wm_prog_data
=
2036 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
2038 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
2039 /* 2 floats per slot returned */
2040 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
2041 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
2043 wm_prog_data
->pulls_bary
= true;
2049 * Computes 1 << x, given a D/UD register containing some value x.
2052 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
2054 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
2056 fs_reg result
= bld
.vgrf(x
.type
, 1);
2057 fs_reg one
= bld
.vgrf(x
.type
, 1);
2059 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
2060 bld
.SHL(result
, one
, x
);
2065 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2067 assert(stage
== MESA_SHADER_GEOMETRY
);
2069 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2071 if (gs_compile
->control_data_header_size_bits
== 0)
2074 /* We can only do EndPrimitive() functionality when the control data
2075 * consists of cut bits. Fortunately, the only time it isn't is when the
2076 * output type is points, in which case EndPrimitive() is a no-op.
2078 if (gs_prog_data
->control_data_format
!=
2079 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2083 /* Cut bits use one bit per vertex. */
2084 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2086 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2087 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2089 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2090 * vertex n, 0 otherwise. So all we need to do here is mark bit
2091 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2092 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2093 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2095 * Note that if EndPrimitive() is called before emitting any vertices, this
2096 * will cause us to set bit 31 of the control_data_bits register to 1.
2097 * That's fine because:
2099 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2100 * output, so the hardware will ignore cut bit 31.
2102 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2103 * last vertex, so setting cut bit 31 has no effect (since the primitive
2104 * is automatically ended when the GS terminates).
2106 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2107 * control_data_bits register to 0 when the first vertex is emitted.
2110 const fs_builder abld
= bld
.annotate("end primitive");
2112 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2113 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2114 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2115 fs_reg mask
= intexp2(abld
, prev_count
);
2116 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2117 * attention to the lower 5 bits of its second source argument, so on this
2118 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2119 * ((vertex_count - 1) % 32).
2121 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2125 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2127 assert(stage
== MESA_SHADER_GEOMETRY
);
2128 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2130 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2132 const fs_builder abld
= bld
.annotate("emit control data bits");
2133 const fs_builder fwa_bld
= bld
.exec_all();
2135 /* We use a single UD register to accumulate control data bits (32 bits
2136 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2139 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2140 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2141 * use the Channel Mask phase to enable/disable which DWord within that
2142 * group to write. (Remember, different SIMD8 channels may have emitted
2143 * different numbers of vertices, so we may need per-slot offsets.)
2145 * Channel masking presents an annoying problem: we may have to replicate
2146 * the data up to 4 times:
2148 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2150 * To avoid penalizing shaders that emit a small number of vertices, we
2151 * can avoid these sometimes: if the size of the control data header is
2152 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2153 * land in the same 128-bit group, so we can skip per-slot offsets.
2155 * Similarly, if the control data header is <= 32 bits, there is only one
2156 * DWord, so we can skip channel masks.
2158 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2160 fs_reg channel_mask
, per_slot_offset
;
2162 if (gs_compile
->control_data_header_size_bits
> 32) {
2163 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2164 channel_mask
= vgrf(glsl_type::uint_type
);
2167 if (gs_compile
->control_data_header_size_bits
> 128) {
2168 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2169 per_slot_offset
= vgrf(glsl_type::uint_type
);
2172 /* Figure out which DWord we're trying to write to using the formula:
2174 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2176 * Since bits_per_vertex is a power of two, and is known at compile
2177 * time, this can be optimized to:
2179 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2181 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2182 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2183 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2184 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2185 unsigned log2_bits_per_vertex
=
2186 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2187 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2189 if (per_slot_offset
.file
!= BAD_FILE
) {
2190 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2191 * the appropriate OWord within the control data header.
2193 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2196 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2197 * write to the appropriate DWORD within the OWORD.
2199 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2200 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2201 channel_mask
= intexp2(fwa_bld
, channel
);
2202 /* Then the channel masks need to be in bits 23:16. */
2203 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2206 /* Store the control data bits in the message payload and send it. */
2208 if (channel_mask
.file
!= BAD_FILE
)
2209 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2210 if (per_slot_offset
.file
!= BAD_FILE
)
2213 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2214 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2216 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2217 if (per_slot_offset
.file
!= BAD_FILE
)
2218 sources
[i
++] = per_slot_offset
;
2219 if (channel_mask
.file
!= BAD_FILE
)
2220 sources
[i
++] = channel_mask
;
2222 sources
[i
++] = this->control_data_bits
;
2225 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2226 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2228 /* We need to increment Global Offset by 256-bits to make room for
2229 * Broadwell's extra "Vertex Count" payload at the beginning of the
2230 * URB entry. Since this is an OWord message, Global Offset is counted
2231 * in 128-bit units, so we must set it to 2.
2233 if (gs_prog_data
->static_vertex_count
== -1)
2238 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2241 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2243 /* Note: we are calling this *before* increasing vertex_count, so
2244 * this->vertex_count == vertex_count - 1 in the formula above.
2247 /* Stream mode uses 2 bits per vertex */
2248 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2250 /* Must be a valid stream */
2251 assert(stream_id
< MAX_VERTEX_STREAMS
);
2253 /* Control data bits are initialized to 0 so we don't have to set any
2254 * bits when sending vertices to stream 0.
2259 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2261 /* reg::sid = stream_id */
2262 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2263 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2265 /* reg:shift_count = 2 * (vertex_count - 1) */
2266 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2267 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2269 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2270 * attention to the lower 5 bits of its second source argument, so on this
2271 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2272 * stream_id << ((2 * (vertex_count - 1)) % 32).
2274 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2275 abld
.SHL(mask
, sid
, shift_count
);
2276 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2280 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2283 assert(stage
== MESA_SHADER_GEOMETRY
);
2285 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2287 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2288 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2290 /* Haswell and later hardware ignores the "Render Stream Select" bits
2291 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2292 * and instead sends all primitives down the pipeline for rasterization.
2293 * If the SOL stage is enabled, "Render Stream Select" is honored and
2294 * primitives bound to non-zero streams are discarded after stream output.
2296 * Since the only purpose of primives sent to non-zero streams is to
2297 * be recorded by transform feedback, we can simply discard all geometry
2298 * bound to these streams when transform feedback is disabled.
2300 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2303 /* If we're outputting 32 control data bits or less, then we can wait
2304 * until the shader is over to output them all. Otherwise we need to
2305 * output them as we go. Now is the time to do it, since we're about to
2306 * output the vertex_count'th vertex, so it's guaranteed that the
2307 * control data bits associated with the (vertex_count - 1)th vertex are
2310 if (gs_compile
->control_data_header_size_bits
> 32) {
2311 const fs_builder abld
=
2312 bld
.annotate("emit vertex: emit control data bits");
2314 /* Only emit control data bits if we've finished accumulating a batch
2315 * of 32 bits. This is the case when:
2317 * (vertex_count * bits_per_vertex) % 32 == 0
2319 * (in other words, when the last 5 bits of vertex_count *
2320 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2321 * integer n (which is always the case, since bits_per_vertex is
2322 * always 1 or 2), this is equivalent to requiring that the last 5-n
2323 * bits of vertex_count are 0:
2325 * vertex_count & (2^(5-n) - 1) == 0
2327 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2330 * vertex_count & (32 / bits_per_vertex - 1) == 0
2332 * TODO: If vertex_count is an immediate, we could do some of this math
2333 * at compile time...
2336 abld
.AND(bld
.null_reg_d(), vertex_count
,
2337 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2338 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2340 abld
.IF(BRW_PREDICATE_NORMAL
);
2341 /* If vertex_count is 0, then no control data bits have been
2342 * accumulated yet, so we can skip emitting them.
2344 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2345 BRW_CONDITIONAL_NEQ
);
2346 abld
.IF(BRW_PREDICATE_NORMAL
);
2347 emit_gs_control_data_bits(vertex_count
);
2348 abld
.emit(BRW_OPCODE_ENDIF
);
2350 /* Reset control_data_bits to 0 so we can start accumulating a new
2353 * Note: in the case where vertex_count == 0, this neutralizes the
2354 * effect of any call to EndPrimitive() that the shader may have
2355 * made before outputting its first vertex.
2357 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2358 inst
->force_writemask_all
= true;
2359 abld
.emit(BRW_OPCODE_ENDIF
);
2362 emit_urb_writes(vertex_count
);
2364 /* In stream mode we have to set control data bits for all vertices
2365 * unless we have disabled control data bits completely (which we do
2366 * do for GL_POINTS outputs that don't use streams).
2368 if (gs_compile
->control_data_header_size_bits
> 0 &&
2369 gs_prog_data
->control_data_format
==
2370 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2371 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2376 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2377 const nir_src
&vertex_src
,
2378 unsigned base_offset
,
2379 const nir_src
&offset_src
,
2380 unsigned num_components
,
2381 unsigned first_component
)
2383 assert(type_sz(dst
.type
) == 4);
2384 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2385 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2387 /* TODO: figure out push input layout for invocations == 1 */
2388 if (gs_prog_data
->invocations
== 1 &&
2389 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2390 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2391 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2392 nir_src_as_uint(vertex_src
) * push_reg_count
;
2393 for (unsigned i
= 0; i
< num_components
; i
++) {
2394 bld
.MOV(offset(dst
, bld
, i
),
2395 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2400 /* Resort to the pull model. Ensure the VUE handles are provided. */
2401 assert(gs_prog_data
->base
.include_vue_handles
);
2403 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2404 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2406 if (gs_prog_data
->invocations
== 1) {
2407 if (nir_src_is_const(vertex_src
)) {
2408 /* The vertex index is constant; just select the proper URB handle. */
2410 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2411 BRW_REGISTER_TYPE_UD
);
2413 /* The vertex index is non-constant. We need to use indirect
2414 * addressing to fetch the proper URB handle.
2416 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2417 * indicating that channel <n> should read the handle from
2418 * DWord <n>. We convert that to bytes by multiplying by 4.
2420 * Next, we convert the vertex index to bytes by multiplying
2421 * by 32 (shifting by 5), and add the two together. This is
2422 * the final indirect byte offset.
2424 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2425 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2426 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2427 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2429 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2430 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2431 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2432 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2433 /* Convert vertex_index to bytes (multiply by 32) */
2434 bld
.SHL(vertex_offset_bytes
,
2435 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2437 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2439 /* Use first_icp_handle as the base offset. There is one register
2440 * of URB handles per vertex, so inform the register allocator that
2441 * we might read up to nir->info.gs.vertices_in registers.
2443 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2444 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2445 fs_reg(icp_offset_bytes
),
2446 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2449 assert(gs_prog_data
->invocations
> 1);
2451 if (nir_src_is_const(vertex_src
)) {
2452 unsigned vertex
= nir_src_as_uint(vertex_src
);
2453 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2455 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2456 BRW_REGISTER_TYPE_UD
));
2458 /* The vertex index is non-constant. We need to use indirect
2459 * addressing to fetch the proper URB handle.
2462 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2464 /* Convert vertex_index to bytes (multiply by 4) */
2465 bld
.SHL(icp_offset_bytes
,
2466 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2469 /* Use first_icp_handle as the base offset. There is one DWord
2470 * of URB handles per vertex, so inform the register allocator that
2471 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2473 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2474 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2475 fs_reg(icp_offset_bytes
),
2476 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2482 fs_reg indirect_offset
= get_nir_src(offset_src
);
2484 if (nir_src_is_const(offset_src
)) {
2485 /* Constant indexing - use global offset. */
2486 if (first_component
!= 0) {
2487 unsigned read_components
= num_components
+ first_component
;
2488 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2489 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2490 inst
->size_written
= read_components
*
2491 tmp
.component_size(inst
->exec_size
);
2492 for (unsigned i
= 0; i
< num_components
; i
++) {
2493 bld
.MOV(offset(dst
, bld
, i
),
2494 offset(tmp
, bld
, i
+ first_component
));
2497 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2498 inst
->size_written
= num_components
*
2499 dst
.component_size(inst
->exec_size
);
2501 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2504 /* Indirect indexing - use per-slot offsets as well. */
2505 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2506 unsigned read_components
= num_components
+ first_component
;
2507 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2508 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2509 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2510 if (first_component
!= 0) {
2511 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2513 inst
->size_written
= read_components
*
2514 tmp
.component_size(inst
->exec_size
);
2515 for (unsigned i
= 0; i
< num_components
; i
++) {
2516 bld
.MOV(offset(dst
, bld
, i
),
2517 offset(tmp
, bld
, i
+ first_component
));
2520 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2521 inst
->size_written
= num_components
*
2522 dst
.component_size(inst
->exec_size
);
2524 inst
->offset
= base_offset
;
2530 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2532 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2534 if (nir_src_is_const(*offset_src
)) {
2535 /* The only constant offset we should find is 0. brw_nir.c's
2536 * add_const_offset_to_base() will fold other constant offsets
2537 * into instr->const_index[0].
2539 assert(nir_src_as_uint(*offset_src
) == 0);
2543 return get_nir_src(*offset_src
);
2547 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2548 nir_intrinsic_instr
*instr
)
2550 assert(stage
== MESA_SHADER_VERTEX
);
2553 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2554 dest
= get_nir_dest(instr
->dest
);
2556 switch (instr
->intrinsic
) {
2557 case nir_intrinsic_load_vertex_id
:
2558 case nir_intrinsic_load_base_vertex
:
2559 unreachable("should be lowered by nir_lower_system_values()");
2561 case nir_intrinsic_load_input
: {
2562 assert(nir_dest_bit_size(instr
->dest
) == 32);
2563 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2564 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2565 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2567 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2568 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2572 case nir_intrinsic_load_vertex_id_zero_base
:
2573 case nir_intrinsic_load_instance_id
:
2574 case nir_intrinsic_load_base_instance
:
2575 case nir_intrinsic_load_draw_id
:
2576 case nir_intrinsic_load_first_vertex
:
2577 case nir_intrinsic_load_is_indexed_draw
:
2578 unreachable("lowered by brw_nir_lower_vs_inputs");
2581 nir_emit_intrinsic(bld
, instr
);
2587 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2588 nir_intrinsic_instr
*instr
)
2590 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2591 const nir_src
&vertex_src
= instr
->src
[0];
2592 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2595 if (nir_src_is_const(vertex_src
)) {
2596 /* Emit a MOV to resolve <0,1,0> regioning. */
2597 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2598 unsigned vertex
= nir_src_as_uint(vertex_src
);
2600 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2601 BRW_REGISTER_TYPE_UD
));
2602 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2603 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2604 /* For the common case of only 1 instance, an array index of
2605 * gl_InvocationID means reading g1. Skip all the indirect work.
2607 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2609 /* The vertex index is non-constant. We need to use indirect
2610 * addressing to fetch the proper URB handle.
2612 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2614 /* Each ICP handle is a single DWord (4 bytes) */
2615 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2616 bld
.SHL(vertex_offset_bytes
,
2617 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2620 /* Start at g1. We might read up to 4 registers. */
2621 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2622 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2623 brw_imm_ud(4 * REG_SIZE
));
2630 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2631 nir_intrinsic_instr
*instr
)
2633 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2634 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2635 const nir_src
&vertex_src
= instr
->src
[0];
2637 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2639 if (nir_src_is_const(vertex_src
)) {
2640 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2641 nir_src_as_uint(vertex_src
), 0),
2642 BRW_REGISTER_TYPE_UD
));
2645 /* The vertex index is non-constant. We need to use indirect
2646 * addressing to fetch the proper URB handle.
2648 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2649 * indicating that channel <n> should read the handle from
2650 * DWord <n>. We convert that to bytes by multiplying by 4.
2652 * Next, we convert the vertex index to bytes by multiplying
2653 * by 32 (shifting by 5), and add the two together. This is
2654 * the final indirect byte offset.
2656 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2657 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2658 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2659 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2660 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2662 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2663 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2664 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2665 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2666 /* Convert vertex_index to bytes (multiply by 32) */
2667 bld
.SHL(vertex_offset_bytes
,
2668 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2670 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2672 /* Use first_icp_handle as the base offset. There is one register
2673 * of URB handles per vertex, so inform the register allocator that
2674 * we might read up to nir->info.gs.vertices_in registers.
2676 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2677 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2678 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2684 fs_visitor::get_tcs_output_urb_handle()
2686 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2688 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2689 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2691 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2692 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2697 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2698 nir_intrinsic_instr
*instr
)
2700 assert(stage
== MESA_SHADER_TESS_CTRL
);
2701 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2702 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2703 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2706 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2709 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2710 dst
= get_nir_dest(instr
->dest
);
2712 switch (instr
->intrinsic
) {
2713 case nir_intrinsic_load_primitive_id
:
2714 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2715 : brw_vec1_grf(0, 1)));
2717 case nir_intrinsic_load_invocation_id
:
2718 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2720 case nir_intrinsic_load_patch_vertices_in
:
2721 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2722 brw_imm_d(tcs_key
->input_vertices
));
2725 case nir_intrinsic_barrier
: {
2726 if (tcs_prog_data
->instances
== 1)
2729 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2730 fs_reg m0_2
= component(m0
, 2);
2732 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2734 /* Zero the message header */
2735 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2737 if (devinfo
->gen
< 11) {
2738 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2739 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2740 brw_imm_ud(INTEL_MASK(16, 13)));
2742 /* Shift it up to bits 27:24. */
2743 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2745 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2746 brw_imm_ud(INTEL_MASK(30, 24)));
2749 /* Set the Barrier Count and the enable bit */
2750 if (devinfo
->gen
< 11) {
2751 chanbld
.OR(m0_2
, m0_2
,
2752 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2754 chanbld
.OR(m0_2
, m0_2
,
2755 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2758 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2762 case nir_intrinsic_load_input
:
2763 unreachable("nir_lower_io should never give us these.");
2766 case nir_intrinsic_load_per_vertex_input
: {
2767 assert(nir_dest_bit_size(instr
->dest
) == 32);
2768 fs_reg indirect_offset
= get_indirect_offset(instr
);
2769 unsigned imm_offset
= instr
->const_index
[0];
2773 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2774 : get_tcs_single_patch_icp_handle(bld
, instr
);
2776 /* We can only read two double components with each URB read, so
2777 * we send two read messages in that case, each one loading up to
2778 * two double components.
2780 unsigned num_components
= instr
->num_components
;
2781 unsigned first_component
= nir_intrinsic_component(instr
);
2783 if (indirect_offset
.file
== BAD_FILE
) {
2784 /* Constant indexing - use global offset. */
2785 if (first_component
!= 0) {
2786 unsigned read_components
= num_components
+ first_component
;
2787 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2788 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2789 for (unsigned i
= 0; i
< num_components
; i
++) {
2790 bld
.MOV(offset(dst
, bld
, i
),
2791 offset(tmp
, bld
, i
+ first_component
));
2794 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2796 inst
->offset
= imm_offset
;
2799 /* Indirect indexing - use per-slot offsets as well. */
2800 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2801 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2802 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2803 if (first_component
!= 0) {
2804 unsigned read_components
= num_components
+ first_component
;
2805 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2806 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2808 for (unsigned i
= 0; i
< num_components
; i
++) {
2809 bld
.MOV(offset(dst
, bld
, i
),
2810 offset(tmp
, bld
, i
+ first_component
));
2813 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2816 inst
->offset
= imm_offset
;
2819 inst
->size_written
= (num_components
+ first_component
) *
2820 inst
->dst
.component_size(inst
->exec_size
);
2822 /* Copy the temporary to the destination to deal with writemasking.
2824 * Also attempt to deal with gl_PointSize being in the .w component.
2826 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2827 assert(type_sz(dst
.type
) == 4);
2828 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2829 inst
->size_written
= 4 * REG_SIZE
;
2830 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2835 case nir_intrinsic_load_output
:
2836 case nir_intrinsic_load_per_vertex_output
: {
2837 assert(nir_dest_bit_size(instr
->dest
) == 32);
2838 fs_reg indirect_offset
= get_indirect_offset(instr
);
2839 unsigned imm_offset
= instr
->const_index
[0];
2840 unsigned first_component
= nir_intrinsic_component(instr
);
2842 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2845 if (indirect_offset
.file
== BAD_FILE
) {
2846 /* This MOV replicates the output handle to all enabled channels
2847 * is SINGLE_PATCH mode.
2849 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2850 bld
.MOV(patch_handle
, output_handles
);
2853 if (first_component
!= 0) {
2854 unsigned read_components
=
2855 instr
->num_components
+ first_component
;
2856 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2857 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2859 inst
->size_written
= read_components
* REG_SIZE
;
2860 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2861 bld
.MOV(offset(dst
, bld
, i
),
2862 offset(tmp
, bld
, i
+ first_component
));
2865 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2867 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2869 inst
->offset
= imm_offset
;
2873 /* Indirect indexing - use per-slot offsets as well. */
2874 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2875 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2876 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2877 if (first_component
!= 0) {
2878 unsigned read_components
=
2879 instr
->num_components
+ first_component
;
2880 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2881 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2883 inst
->size_written
= read_components
* REG_SIZE
;
2884 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2885 bld
.MOV(offset(dst
, bld
, i
),
2886 offset(tmp
, bld
, i
+ first_component
));
2889 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2891 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2893 inst
->offset
= imm_offset
;
2899 case nir_intrinsic_store_output
:
2900 case nir_intrinsic_store_per_vertex_output
: {
2901 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2902 fs_reg value
= get_nir_src(instr
->src
[0]);
2903 fs_reg indirect_offset
= get_indirect_offset(instr
);
2904 unsigned imm_offset
= instr
->const_index
[0];
2905 unsigned mask
= instr
->const_index
[1];
2906 unsigned header_regs
= 0;
2907 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2910 srcs
[header_regs
++] = output_handles
;
2912 if (indirect_offset
.file
!= BAD_FILE
) {
2913 srcs
[header_regs
++] = indirect_offset
;
2919 unsigned num_components
= util_last_bit(mask
);
2922 /* We can only pack two 64-bit components in a single message, so send
2923 * 2 messages if we have more components
2925 unsigned first_component
= nir_intrinsic_component(instr
);
2926 mask
= mask
<< first_component
;
2928 if (mask
!= WRITEMASK_XYZW
) {
2929 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2930 opcode
= indirect_offset
.file
!= BAD_FILE
?
2931 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2932 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2934 opcode
= indirect_offset
.file
!= BAD_FILE
?
2935 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2936 SHADER_OPCODE_URB_WRITE_SIMD8
;
2939 for (unsigned i
= 0; i
< num_components
; i
++) {
2940 if (!(mask
& (1 << (i
+ first_component
))))
2943 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2946 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2948 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2949 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2951 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2952 inst
->offset
= imm_offset
;
2958 nir_emit_intrinsic(bld
, instr
);
2964 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2965 nir_intrinsic_instr
*instr
)
2967 assert(stage
== MESA_SHADER_TESS_EVAL
);
2968 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2971 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2972 dest
= get_nir_dest(instr
->dest
);
2974 switch (instr
->intrinsic
) {
2975 case nir_intrinsic_load_primitive_id
:
2976 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2978 case nir_intrinsic_load_tess_coord
:
2979 /* gl_TessCoord is part of the payload in g1-3 */
2980 for (unsigned i
= 0; i
< 3; i
++) {
2981 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2985 case nir_intrinsic_load_input
:
2986 case nir_intrinsic_load_per_vertex_input
: {
2987 assert(nir_dest_bit_size(instr
->dest
) == 32);
2988 fs_reg indirect_offset
= get_indirect_offset(instr
);
2989 unsigned imm_offset
= instr
->const_index
[0];
2990 unsigned first_component
= nir_intrinsic_component(instr
);
2993 if (indirect_offset
.file
== BAD_FILE
) {
2994 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2995 * which is 16 registers (since each holds 2 vec4 slots).
2997 const unsigned max_push_slots
= 32;
2998 if (imm_offset
< max_push_slots
) {
2999 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3000 for (int i
= 0; i
< instr
->num_components
; i
++) {
3001 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
3002 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3005 tes_prog_data
->base
.urb_read_length
=
3006 MAX2(tes_prog_data
->base
.urb_read_length
,
3007 (imm_offset
/ 2) + 1);
3009 /* Replicate the patch handle to all enabled channels */
3010 const fs_reg srcs
[] = {
3011 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3013 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3014 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3016 if (first_component
!= 0) {
3017 unsigned read_components
=
3018 instr
->num_components
+ first_component
;
3019 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3020 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3022 inst
->size_written
= read_components
* REG_SIZE
;
3023 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3024 bld
.MOV(offset(dest
, bld
, i
),
3025 offset(tmp
, bld
, i
+ first_component
));
3028 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3030 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3033 inst
->offset
= imm_offset
;
3036 /* Indirect indexing - use per-slot offsets as well. */
3038 /* We can only read two double components with each URB read, so
3039 * we send two read messages in that case, each one loading up to
3040 * two double components.
3042 unsigned num_components
= instr
->num_components
;
3043 const fs_reg srcs
[] = {
3044 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3047 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3048 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3050 if (first_component
!= 0) {
3051 unsigned read_components
=
3052 num_components
+ first_component
;
3053 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3054 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3056 for (unsigned i
= 0; i
< num_components
; i
++) {
3057 bld
.MOV(offset(dest
, bld
, i
),
3058 offset(tmp
, bld
, i
+ first_component
));
3061 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3065 inst
->offset
= imm_offset
;
3066 inst
->size_written
= (num_components
+ first_component
) *
3067 inst
->dst
.component_size(inst
->exec_size
);
3072 nir_emit_intrinsic(bld
, instr
);
3078 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3079 nir_intrinsic_instr
*instr
)
3081 assert(stage
== MESA_SHADER_GEOMETRY
);
3082 fs_reg indirect_offset
;
3085 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3086 dest
= get_nir_dest(instr
->dest
);
3088 switch (instr
->intrinsic
) {
3089 case nir_intrinsic_load_primitive_id
:
3090 assert(stage
== MESA_SHADER_GEOMETRY
);
3091 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3092 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3093 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3096 case nir_intrinsic_load_input
:
3097 unreachable("load_input intrinsics are invalid for the GS stage");
3099 case nir_intrinsic_load_per_vertex_input
:
3100 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3101 instr
->src
[1], instr
->num_components
,
3102 nir_intrinsic_component(instr
));
3105 case nir_intrinsic_emit_vertex_with_counter
:
3106 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3109 case nir_intrinsic_end_primitive_with_counter
:
3110 emit_gs_end_primitive(instr
->src
[0]);
3113 case nir_intrinsic_set_vertex_count
:
3114 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3117 case nir_intrinsic_load_invocation_id
: {
3118 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3119 assert(val
.file
!= BAD_FILE
);
3120 dest
.type
= val
.type
;
3126 nir_emit_intrinsic(bld
, instr
);
3132 * Fetch the current render target layer index.
3135 fetch_render_target_array_index(const fs_builder
&bld
)
3137 if (bld
.shader
->devinfo
->gen
>= 6) {
3138 /* The render target array index is provided in the thread payload as
3139 * bits 26:16 of r0.0.
3141 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3142 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3146 /* Pre-SNB we only ever render into the first layer of the framebuffer
3147 * since layered rendering is not implemented.
3149 return brw_imm_ud(0);
3154 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3155 * framebuffer at the current fragment coordinates and sample index.
3158 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3161 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3163 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3164 const brw_wm_prog_key
*wm_key
=
3165 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3166 assert(!wm_key
->coherent_fb_fetch
);
3167 const struct brw_wm_prog_data
*wm_prog_data
=
3168 brw_wm_prog_data(stage_prog_data
);
3170 /* Calculate the surface index relative to the start of the texture binding
3171 * table block, since that's what the texturing messages expect.
3173 const unsigned surface
= target
+
3174 wm_prog_data
->binding_table
.render_target_read_start
-
3175 wm_prog_data
->base
.binding_table
.texture_start
;
3177 /* Calculate the fragment coordinates. */
3178 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3179 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3180 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3181 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3183 /* Calculate the sample index and MCS payload when multisampling. Luckily
3184 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3185 * shouldn't be necessary to recompile based on whether the framebuffer is
3188 if (wm_key
->multisample_fbo
&&
3189 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3190 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3192 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3193 const fs_reg mcs
= wm_key
->multisample_fbo
?
3194 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3196 /* Use either a normal or a CMS texel fetch message depending on whether
3197 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3198 * message just in case the framebuffer uses 16x multisampling, it should
3199 * be equivalent to the normal CMS fetch for lower multisampling modes.
3201 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3202 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3203 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3205 /* Emit the instruction. */
3206 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3207 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3208 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3209 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3210 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3211 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3212 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3213 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3214 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3216 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3217 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3223 * Actual coherent framebuffer read implemented using the native render target
3224 * read message. Requires SKL+.
3227 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3229 assert(bld
.shader
->devinfo
->gen
>= 9);
3230 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3231 inst
->target
= target
;
3232 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3238 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3240 if (n
&& regs
[0].file
!= BAD_FILE
) {
3244 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3246 for (unsigned i
= 0; i
< n
; i
++)
3254 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3256 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3257 const brw_wm_prog_key
*const key
=
3258 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3259 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3260 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3262 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3263 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3265 else if (l
== FRAG_RESULT_COLOR
)
3266 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3267 MAX2(key
->nr_color_regions
, 1));
3269 else if (l
== FRAG_RESULT_DEPTH
)
3270 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3272 else if (l
== FRAG_RESULT_STENCIL
)
3273 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3275 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3276 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3278 else if (l
>= FRAG_RESULT_DATA0
&&
3279 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3280 return alloc_temporary(v
->bld
, 4,
3281 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3284 unreachable("Invalid location");
3287 /* Annoyingly, we get the barycentrics into the shader in a layout that's
3288 * optimized for PLN but it doesn't work nearly as well as one would like for
3289 * manual interpolation.
3292 shuffle_from_pln_layout(const fs_builder
&bld
, fs_reg dest
, fs_reg pln_data
)
3294 dest
.type
= BRW_REGISTER_TYPE_F
;
3295 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3296 const fs_reg dest_u
= offset(dest
, bld
, 0);
3297 const fs_reg dest_v
= offset(dest
, bld
, 1);
3299 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3300 const fs_builder gbld
= bld
.group(8, g
);
3301 gbld
.MOV(horiz_offset(dest_u
, g
* 8),
3302 byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
));
3303 gbld
.MOV(horiz_offset(dest_v
, g
* 8),
3304 byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
));
3309 shuffle_to_pln_layout(const fs_builder
&bld
, fs_reg pln_data
, fs_reg src
)
3311 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3312 src
.type
= BRW_REGISTER_TYPE_F
;
3313 const fs_reg src_u
= offset(src
, bld
, 0);
3314 const fs_reg src_v
= offset(src
, bld
, 1);
3316 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3317 const fs_builder gbld
= bld
.group(8, g
);
3318 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
),
3319 horiz_offset(src_u
, g
* 8));
3320 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
),
3321 horiz_offset(src_v
, g
* 8));
3326 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3327 nir_intrinsic_instr
*instr
)
3329 assert(stage
== MESA_SHADER_FRAGMENT
);
3332 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3333 dest
= get_nir_dest(instr
->dest
);
3335 switch (instr
->intrinsic
) {
3336 case nir_intrinsic_load_front_face
:
3337 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3338 *emit_frontfacing_interpolation());
3341 case nir_intrinsic_load_sample_pos
: {
3342 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3343 assert(sample_pos
.file
!= BAD_FILE
);
3344 dest
.type
= sample_pos
.type
;
3345 bld
.MOV(dest
, sample_pos
);
3346 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3350 case nir_intrinsic_load_layer_id
:
3351 dest
.type
= BRW_REGISTER_TYPE_UD
;
3352 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3355 case nir_intrinsic_is_helper_invocation
: {
3356 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3357 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3358 * consideration demoted invocations. That information is stored in
3361 dest
.type
= BRW_REGISTER_TYPE_UD
;
3363 bld
.MOV(dest
, brw_imm_ud(0));
3365 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3366 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3367 mov
->predicate_inverse
= true;
3368 mov
->flag_subreg
= 1;
3372 case nir_intrinsic_load_helper_invocation
:
3373 case nir_intrinsic_load_sample_mask_in
:
3374 case nir_intrinsic_load_sample_id
: {
3375 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3376 fs_reg val
= nir_system_values
[sv
];
3377 assert(val
.file
!= BAD_FILE
);
3378 dest
.type
= val
.type
;
3383 case nir_intrinsic_store_output
: {
3384 const fs_reg src
= get_nir_src(instr
->src
[0]);
3385 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3386 const unsigned location
= nir_intrinsic_base(instr
) +
3387 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3388 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3391 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3392 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3393 offset(src
, bld
, j
));
3398 case nir_intrinsic_load_output
: {
3399 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3400 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3401 assert(l
>= FRAG_RESULT_DATA0
);
3402 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3403 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3404 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3406 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3407 emit_coherent_fb_read(bld
, tmp
, target
);
3409 emit_non_coherent_fb_read(bld
, tmp
, target
);
3411 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3412 bld
.MOV(offset(dest
, bld
, j
),
3413 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3419 case nir_intrinsic_demote
:
3420 case nir_intrinsic_discard
:
3421 case nir_intrinsic_demote_if
:
3422 case nir_intrinsic_discard_if
: {
3423 /* We track our discarded pixels in f0.1. By predicating on it, we can
3424 * update just the flag bits that aren't yet discarded. If there's no
3425 * condition, we emit a CMP of g0 != g0, so all currently executing
3426 * channels will get turned off.
3428 fs_inst
*cmp
= NULL
;
3429 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3430 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3431 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3434 alu
->op
!= nir_op_bcsel
&&
3435 alu
->op
!= nir_op_inot
) {
3436 /* Re-emit the instruction that generated the Boolean value, but
3437 * do not store it. Since this instruction will be conditional,
3438 * other instructions that want to use the real Boolean value may
3439 * get garbage. This was a problem for piglit's fs-discard-exit-2
3442 * Ideally we'd detect that the instruction cannot have a
3443 * conditional modifier before emitting the instructions. Alas,
3444 * that is nigh impossible. Instead, we're going to assume the
3445 * instruction (or last instruction) generated can have a
3446 * conditional modifier. If it cannot, fallback to the old-style
3447 * compare, and hope dead code elimination will clean up the
3448 * extra instructions generated.
3450 nir_emit_alu(bld
, alu
, false);
3452 cmp
= (fs_inst
*) instructions
.get_tail();
3453 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3454 if (cmp
->can_do_cmod())
3455 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3459 /* The old sequence that would have been generated is,
3460 * basically, bool_result == false. This is equivalent to
3461 * !bool_result, so negate the old modifier.
3463 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3468 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3469 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3472 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3473 BRW_REGISTER_TYPE_UW
));
3474 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3477 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3478 cmp
->flag_subreg
= 1;
3480 if (devinfo
->gen
>= 6) {
3481 /* Due to the way we implement discard, the jump will only happen
3482 * when the whole quad is discarded. So we can do this even for
3483 * demote as it won't break its uniformity promises.
3485 emit_discard_jump();
3488 limit_dispatch_width(16, "Fragment discard/demote not implemented in SIMD32 mode.");
3492 case nir_intrinsic_load_input
: {
3493 /* load_input is only used for flat inputs */
3494 assert(nir_dest_bit_size(instr
->dest
) == 32);
3495 unsigned base
= nir_intrinsic_base(instr
);
3496 unsigned comp
= nir_intrinsic_component(instr
);
3497 unsigned num_components
= instr
->num_components
;
3499 /* Special case fields in the VUE header */
3500 if (base
== VARYING_SLOT_LAYER
)
3502 else if (base
== VARYING_SLOT_VIEWPORT
)
3505 for (unsigned int i
= 0; i
< num_components
; i
++) {
3506 bld
.MOV(offset(dest
, bld
, i
),
3507 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3512 case nir_intrinsic_load_fs_input_interp_deltas
: {
3513 assert(stage
== MESA_SHADER_FRAGMENT
);
3514 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3515 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3516 nir_intrinsic_component(instr
));
3517 dest
.type
= BRW_REGISTER_TYPE_F
;
3518 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3519 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3520 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3524 case nir_intrinsic_load_barycentric_pixel
:
3525 case nir_intrinsic_load_barycentric_centroid
:
3526 case nir_intrinsic_load_barycentric_sample
: {
3527 /* Use the delta_xy values computed from the payload */
3528 const glsl_interp_mode interp_mode
=
3529 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3530 enum brw_barycentric_mode bary
=
3531 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3533 shuffle_from_pln_layout(bld
, dest
, this->delta_xy
[bary
]);
3537 case nir_intrinsic_load_barycentric_at_sample
: {
3538 const glsl_interp_mode interpolation
=
3539 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3541 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3542 if (nir_src_is_const(instr
->src
[0])) {
3543 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3545 emit_pixel_interpolater_send(bld
,
3546 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3549 brw_imm_ud(msg_data
),
3552 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3553 BRW_REGISTER_TYPE_UD
);
3555 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3556 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3557 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3558 bld
.exec_all().group(1, 0)
3559 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3560 emit_pixel_interpolater_send(bld
,
3561 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3567 /* Make a loop that sends a message to the pixel interpolater
3568 * for the sample number in each live channel. If there are
3569 * multiple channels with the same sample number then these
3570 * will be handled simultaneously with a single interation of
3573 bld
.emit(BRW_OPCODE_DO
);
3575 /* Get the next live sample number into sample_id_reg */
3576 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3578 /* Set the flag register so that we can perform the send
3579 * message on all channels that have the same sample number
3581 bld
.CMP(bld
.null_reg_ud(),
3582 sample_src
, sample_id
,
3583 BRW_CONDITIONAL_EQ
);
3584 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3585 bld
.exec_all().group(1, 0)
3586 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3588 emit_pixel_interpolater_send(bld
,
3589 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3592 component(msg_data
, 0),
3594 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3596 /* Continue the loop if there are any live channels left */
3597 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3599 bld
.emit(BRW_OPCODE_WHILE
));
3602 shuffle_from_pln_layout(bld
, dest
, tmp
);
3606 case nir_intrinsic_load_barycentric_at_offset
: {
3607 const glsl_interp_mode interpolation
=
3608 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3610 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3612 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3614 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3615 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3616 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3618 emit_pixel_interpolater_send(bld
,
3619 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3622 brw_imm_ud(off_x
| (off_y
<< 4)),
3625 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3626 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3627 BRW_REGISTER_TYPE_F
);
3628 for (int i
= 0; i
< 2; i
++) {
3629 fs_reg temp
= vgrf(glsl_type::float_type
);
3630 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3631 fs_reg itemp
= vgrf(glsl_type::int_type
);
3633 bld
.MOV(itemp
, temp
);
3635 /* Clamp the upper end of the range to +7/16.
3636 * ARB_gpu_shader5 requires that we support a maximum offset
3637 * of +0.5, which isn't representable in a S0.4 value -- if
3638 * we didn't clamp it, we'd end up with -8/16, which is the
3639 * opposite of what the shader author wanted.
3641 * This is legal due to ARB_gpu_shader5's quantization
3644 * "Not all values of <offset> may be supported; x and y
3645 * offsets may be rounded to fixed-point values with the
3646 * number of fraction bits given by the
3647 * implementation-dependent constant
3648 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3650 set_condmod(BRW_CONDITIONAL_L
,
3651 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3654 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3655 emit_pixel_interpolater_send(bld
,
3662 shuffle_from_pln_layout(bld
, dest
, tmp
);
3666 case nir_intrinsic_load_frag_coord
:
3667 emit_fragcoord_interpolation(dest
);
3670 case nir_intrinsic_load_interpolated_input
: {
3671 assert(instr
->src
[0].ssa
&&
3672 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3673 nir_intrinsic_instr
*bary_intrinsic
=
3674 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3675 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3676 enum glsl_interp_mode interp_mode
=
3677 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3680 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3681 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3682 /* Use the result of the PI message. Because the load_barycentric
3683 * intrinsics return a regular vec2 and we need it in PLN layout, we
3684 * have to do a translation. Fortunately, copy-prop cleans this up
3687 dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3688 shuffle_to_pln_layout(bld
, dst_xy
, get_nir_src(instr
->src
[0]));
3690 /* Use the delta_xy values computed from the payload */
3691 enum brw_barycentric_mode bary
=
3692 brw_barycentric_mode(interp_mode
, bary_intrin
);
3694 dst_xy
= this->delta_xy
[bary
];
3697 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3699 component(interp_reg(nir_intrinsic_base(instr
),
3700 nir_intrinsic_component(instr
) + i
), 0);
3701 interp
.type
= BRW_REGISTER_TYPE_F
;
3702 dest
.type
= BRW_REGISTER_TYPE_F
;
3704 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3705 fs_reg tmp
= vgrf(glsl_type::float_type
);
3706 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3707 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3709 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3716 nir_emit_intrinsic(bld
, instr
);
3722 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3723 nir_intrinsic_instr
*instr
)
3725 assert(stage
== MESA_SHADER_COMPUTE
);
3726 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3729 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3730 dest
= get_nir_dest(instr
->dest
);
3732 switch (instr
->intrinsic
) {
3733 case nir_intrinsic_barrier
:
3735 cs_prog_data
->uses_barrier
= true;
3738 case nir_intrinsic_load_subgroup_id
:
3739 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3742 case nir_intrinsic_load_local_invocation_id
:
3743 case nir_intrinsic_load_work_group_id
: {
3744 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3745 fs_reg val
= nir_system_values
[sv
];
3746 assert(val
.file
!= BAD_FILE
);
3747 dest
.type
= val
.type
;
3748 for (unsigned i
= 0; i
< 3; i
++)
3749 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3753 case nir_intrinsic_load_num_work_groups
: {
3754 const unsigned surface
=
3755 cs_prog_data
->binding_table
.work_groups_start
;
3757 cs_prog_data
->uses_num_work_groups
= true;
3759 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3760 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3761 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3762 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3764 /* Read the 3 GLuint components of gl_NumWorkGroups */
3765 for (unsigned i
= 0; i
< 3; i
++) {
3766 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3767 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3768 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3773 case nir_intrinsic_shared_atomic_add
:
3774 case nir_intrinsic_shared_atomic_imin
:
3775 case nir_intrinsic_shared_atomic_umin
:
3776 case nir_intrinsic_shared_atomic_imax
:
3777 case nir_intrinsic_shared_atomic_umax
:
3778 case nir_intrinsic_shared_atomic_and
:
3779 case nir_intrinsic_shared_atomic_or
:
3780 case nir_intrinsic_shared_atomic_xor
:
3781 case nir_intrinsic_shared_atomic_exchange
:
3782 case nir_intrinsic_shared_atomic_comp_swap
:
3783 nir_emit_shared_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3785 case nir_intrinsic_shared_atomic_fmin
:
3786 case nir_intrinsic_shared_atomic_fmax
:
3787 case nir_intrinsic_shared_atomic_fcomp_swap
:
3788 nir_emit_shared_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
3791 case nir_intrinsic_load_shared
: {
3792 assert(devinfo
->gen
>= 7);
3793 assert(stage
== MESA_SHADER_COMPUTE
);
3795 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3796 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3797 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3798 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3799 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3801 /* Make dest unsigned because that's what the temporary will be */
3802 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3804 /* Read the vector */
3805 if (nir_intrinsic_align(instr
) >= 4) {
3806 assert(nir_dest_bit_size(instr
->dest
) == 32);
3807 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3809 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3810 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3811 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3813 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3814 assert(nir_dest_num_components(instr
->dest
) == 1);
3815 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3817 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3818 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3819 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3820 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3825 case nir_intrinsic_store_shared
: {
3826 assert(devinfo
->gen
>= 7);
3827 assert(stage
== MESA_SHADER_COMPUTE
);
3829 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3830 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3831 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3832 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3833 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3835 fs_reg data
= get_nir_src(instr
->src
[0]);
3836 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3838 assert(nir_intrinsic_write_mask(instr
) ==
3839 (1u << instr
->num_components
) - 1);
3840 if (nir_intrinsic_align(instr
) >= 4) {
3841 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3842 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3843 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3844 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3845 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3846 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3848 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3849 assert(nir_src_num_components(instr
->src
[0]) == 1);
3850 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3852 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3853 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3855 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3856 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3862 nir_emit_intrinsic(bld
, instr
);
3868 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3869 nir_op op
, brw_reg_type type
)
3871 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3872 switch (type_sz(type
)) {
3874 if (type
== BRW_REGISTER_TYPE_UB
) {
3875 return brw_imm_uw(value
.u8
);
3877 assert(type
== BRW_REGISTER_TYPE_B
);
3878 return brw_imm_w(value
.i8
);
3881 return retype(brw_imm_uw(value
.u16
), type
);
3883 return retype(brw_imm_ud(value
.u32
), type
);
3885 if (type
== BRW_REGISTER_TYPE_DF
)
3886 return setup_imm_df(bld
, value
.f64
);
3888 return retype(brw_imm_u64(value
.u64
), type
);
3890 unreachable("Invalid type size");
3895 brw_op_for_nir_reduction_op(nir_op op
)
3898 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3899 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3900 case nir_op_imul
: return BRW_OPCODE_MUL
;
3901 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3902 case nir_op_imin
: return BRW_OPCODE_SEL
;
3903 case nir_op_umin
: return BRW_OPCODE_SEL
;
3904 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3905 case nir_op_imax
: return BRW_OPCODE_SEL
;
3906 case nir_op_umax
: return BRW_OPCODE_SEL
;
3907 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3908 case nir_op_iand
: return BRW_OPCODE_AND
;
3909 case nir_op_ior
: return BRW_OPCODE_OR
;
3910 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3912 unreachable("Invalid reduction operation");
3916 static brw_conditional_mod
3917 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3920 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3921 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3922 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3923 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3924 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3925 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3926 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3927 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3928 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3929 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3930 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3931 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3932 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3934 unreachable("Invalid reduction operation");
3939 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3940 nir_intrinsic_instr
*instr
)
3942 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3944 if (stage_prog_data
->binding_table
.image_start
> 0) {
3945 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3946 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3948 bld
.ADD(image
, image
,
3949 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3953 return bld
.emit_uniformize(image
);
3957 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3958 nir_intrinsic_instr
*instr
)
3960 /* SSBO stores are weird in that their index is in src[1] */
3961 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3964 if (nir_src_is_const(instr
->src
[src
])) {
3965 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3966 nir_src_as_uint(instr
->src
[src
]);
3967 surf_index
= brw_imm_ud(index
);
3969 surf_index
= vgrf(glsl_type::uint_type
);
3970 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3971 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3974 return bld
.emit_uniformize(surf_index
);
3978 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3980 switch (nir_intrinsic_image_dim(instr
)) {
3981 case GLSL_SAMPLER_DIM_1D
:
3982 return 1 + nir_intrinsic_image_array(instr
);
3983 case GLSL_SAMPLER_DIM_2D
:
3984 case GLSL_SAMPLER_DIM_RECT
:
3985 return 2 + nir_intrinsic_image_array(instr
);
3986 case GLSL_SAMPLER_DIM_3D
:
3987 case GLSL_SAMPLER_DIM_CUBE
:
3989 case GLSL_SAMPLER_DIM_BUF
:
3991 case GLSL_SAMPLER_DIM_MS
:
3992 return 2 + nir_intrinsic_image_array(instr
);
3994 unreachable("Invalid image dimension");
3999 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4002 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4003 dest
= get_nir_dest(instr
->dest
);
4005 switch (instr
->intrinsic
) {
4006 case nir_intrinsic_image_load
:
4007 case nir_intrinsic_image_store
:
4008 case nir_intrinsic_image_atomic_add
:
4009 case nir_intrinsic_image_atomic_imin
:
4010 case nir_intrinsic_image_atomic_umin
:
4011 case nir_intrinsic_image_atomic_imax
:
4012 case nir_intrinsic_image_atomic_umax
:
4013 case nir_intrinsic_image_atomic_and
:
4014 case nir_intrinsic_image_atomic_or
:
4015 case nir_intrinsic_image_atomic_xor
:
4016 case nir_intrinsic_image_atomic_exchange
:
4017 case nir_intrinsic_image_atomic_comp_swap
:
4018 case nir_intrinsic_bindless_image_load
:
4019 case nir_intrinsic_bindless_image_store
:
4020 case nir_intrinsic_bindless_image_atomic_add
:
4021 case nir_intrinsic_bindless_image_atomic_imin
:
4022 case nir_intrinsic_bindless_image_atomic_umin
:
4023 case nir_intrinsic_bindless_image_atomic_imax
:
4024 case nir_intrinsic_bindless_image_atomic_umax
:
4025 case nir_intrinsic_bindless_image_atomic_and
:
4026 case nir_intrinsic_bindless_image_atomic_or
:
4027 case nir_intrinsic_bindless_image_atomic_xor
:
4028 case nir_intrinsic_bindless_image_atomic_exchange
:
4029 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4030 if (stage
== MESA_SHADER_FRAGMENT
&&
4031 instr
->intrinsic
!= nir_intrinsic_image_load
)
4032 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4034 /* Get some metadata from the image intrinsic. */
4035 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4037 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4039 switch (instr
->intrinsic
) {
4040 case nir_intrinsic_image_load
:
4041 case nir_intrinsic_image_store
:
4042 case nir_intrinsic_image_atomic_add
:
4043 case nir_intrinsic_image_atomic_imin
:
4044 case nir_intrinsic_image_atomic_umin
:
4045 case nir_intrinsic_image_atomic_imax
:
4046 case nir_intrinsic_image_atomic_umax
:
4047 case nir_intrinsic_image_atomic_and
:
4048 case nir_intrinsic_image_atomic_or
:
4049 case nir_intrinsic_image_atomic_xor
:
4050 case nir_intrinsic_image_atomic_exchange
:
4051 case nir_intrinsic_image_atomic_comp_swap
:
4052 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4053 get_nir_image_intrinsic_image(bld
, instr
);
4058 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4059 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4063 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4064 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4065 brw_imm_ud(image_intrinsic_coord_components(instr
));
4067 /* Emit an image load, store or atomic op. */
4068 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4069 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4070 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4072 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4073 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4074 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4075 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4076 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4077 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4078 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4079 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4080 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4082 unsigned num_srcs
= info
->num_srcs
;
4083 int op
= brw_aop_for_nir_intrinsic(instr
);
4084 if (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
) {
4085 assert(num_srcs
== 4);
4089 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4093 data
= get_nir_src(instr
->src
[3]);
4094 if (num_srcs
>= 5) {
4095 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4096 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4097 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4100 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4102 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4103 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4108 case nir_intrinsic_image_size
:
4109 case nir_intrinsic_bindless_image_size
: {
4110 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4111 * into will handle the binding table index for us in the geneerator.
4112 * Incidentally, this means that we can handle bindless with exactly the
4115 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4116 BRW_REGISTER_TYPE_UD
);
4117 image
= bld
.emit_uniformize(image
);
4119 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4120 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4121 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4123 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4124 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4125 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4126 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4128 /* Since the image size is always uniform, we can just emit a SIMD8
4129 * query instruction and splat the result out.
4131 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4133 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4134 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4135 tmp
, srcs
, ARRAY_SIZE(srcs
));
4136 inst
->size_written
= 4 * REG_SIZE
;
4138 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4139 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4140 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4141 offset(retype(dest
, tmp
.type
), bld
, c
),
4142 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4144 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4145 component(offset(tmp
, ubld
, c
), 0));
4151 case nir_intrinsic_image_load_raw_intel
: {
4152 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4153 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4154 get_nir_image_intrinsic_image(bld
, instr
);
4155 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4156 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4157 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4160 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4161 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4162 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4166 case nir_intrinsic_image_store_raw_intel
: {
4167 if (stage
== MESA_SHADER_FRAGMENT
)
4168 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4170 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4171 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4172 get_nir_image_intrinsic_image(bld
, instr
);
4173 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4174 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4175 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4176 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4178 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4179 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4183 case nir_intrinsic_group_memory_barrier
:
4184 case nir_intrinsic_memory_barrier_shared
:
4185 case nir_intrinsic_memory_barrier_atomic_counter
:
4186 case nir_intrinsic_memory_barrier_buffer
:
4187 case nir_intrinsic_memory_barrier_image
:
4188 case nir_intrinsic_memory_barrier
: {
4189 bool l3_fence
, slm_fence
;
4190 if (devinfo
->gen
>= 11) {
4191 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4192 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4193 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4194 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4196 /* Prior to gen11, we only have one kind of fence. */
4201 /* Be conservative in Gen11+ and always stall in a fence. Since there
4202 * are two different fences, and shader might want to synchronize
4205 * TODO: Improve NIR so that scope and visibility information for the
4206 * barriers is available here to make a better decision.
4208 * TODO: When emitting more than one fence, it might help emit all
4209 * the fences first and then generate the stall moves.
4211 const bool stall
= devinfo
->gen
>= 11;
4213 const fs_builder ubld
= bld
.group(8, 0);
4214 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4217 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4218 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4219 /* bti */ brw_imm_ud(0))
4220 ->size_written
= 2 * REG_SIZE
;
4224 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4225 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4226 brw_imm_ud(GEN7_BTI_SLM
))
4227 ->size_written
= 2 * REG_SIZE
;
4233 case nir_intrinsic_shader_clock
: {
4234 /* We cannot do anything if there is an event, so ignore it for now */
4235 const fs_reg shader_clock
= get_timestamp(bld
);
4236 const fs_reg srcs
[] = { component(shader_clock
, 0),
4237 component(shader_clock
, 1) };
4238 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4242 case nir_intrinsic_image_samples
:
4243 /* The driver does not support multi-sampled images. */
4244 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4247 case nir_intrinsic_load_uniform
: {
4248 /* Offsets are in bytes but they should always aligned to
4251 assert(instr
->const_index
[0] % 4 == 0 ||
4252 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4254 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4256 if (nir_src_is_const(instr
->src
[0])) {
4257 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4258 assert(load_offset
% type_sz(dest
.type
) == 0);
4259 /* For 16-bit types we add the module of the const_index[0]
4260 * offset to access to not 32-bit aligned element
4262 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4264 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4265 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4268 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4269 BRW_REGISTER_TYPE_UD
);
4271 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4272 * go past the end of the uniform. In order to keep the n'th
4273 * component from running past, we subtract off the size of all but
4274 * one component of the vector.
4276 assert(instr
->const_index
[1] >=
4277 instr
->num_components
* (int) type_sz(dest
.type
));
4278 unsigned read_size
= instr
->const_index
[1] -
4279 (instr
->num_components
- 1) * type_sz(dest
.type
);
4281 bool supports_64bit_indirects
=
4282 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4284 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4285 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4286 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4287 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4288 indirect
, brw_imm_ud(read_size
));
4291 const unsigned num_mov_indirects
=
4292 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4293 /* We read a little bit less per MOV INDIRECT, as they are now
4294 * 32-bits ones instead of 64-bit. Fix read_size then.
4296 const unsigned read_size_32bit
= read_size
-
4297 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4298 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4299 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4300 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4301 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4302 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4303 indirect
, brw_imm_ud(read_size_32bit
));
4311 case nir_intrinsic_load_ubo
: {
4313 if (nir_src_is_const(instr
->src
[0])) {
4314 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4315 nir_src_as_uint(instr
->src
[0]);
4316 surf_index
= brw_imm_ud(index
);
4318 /* The block index is not a constant. Evaluate the index expression
4319 * per-channel and add the base UBO index; we have to select a value
4320 * from any live channel.
4322 surf_index
= vgrf(glsl_type::uint_type
);
4323 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4324 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4325 surf_index
= bld
.emit_uniformize(surf_index
);
4328 if (!nir_src_is_const(instr
->src
[1])) {
4329 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4330 BRW_REGISTER_TYPE_UD
);
4332 for (int i
= 0; i
< instr
->num_components
; i
++)
4333 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4334 base_offset
, i
* type_sz(dest
.type
));
4336 prog_data
->has_ubo_pull
= true;
4338 /* Even if we are loading doubles, a pull constant load will load
4339 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4340 * need to load a full dvec4 we will have to emit 2 loads. This is
4341 * similar to demote_pull_constants(), except that in that case we
4342 * see individual accesses to each component of the vector and then
4343 * we let CSE deal with duplicate loads. Here we see a vector access
4344 * and we have to split it if necessary.
4346 const unsigned type_size
= type_sz(dest
.type
);
4347 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4349 /* See if we've selected this as a push constant candidate */
4350 if (nir_src_is_const(instr
->src
[0])) {
4351 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4352 const unsigned offset_256b
= load_offset
/ 32;
4355 for (int i
= 0; i
< 4; i
++) {
4356 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4357 if (range
->block
== ubo_block
&&
4358 offset_256b
>= range
->start
&&
4359 offset_256b
< range
->start
+ range
->length
) {
4361 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4362 push_reg
.offset
= load_offset
- 32 * range
->start
;
4367 if (push_reg
.file
!= BAD_FILE
) {
4368 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4369 bld
.MOV(offset(dest
, bld
, i
),
4370 byte_offset(push_reg
, i
* type_size
));
4376 prog_data
->has_ubo_pull
= true;
4378 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4379 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4380 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4382 for (unsigned c
= 0; c
< instr
->num_components
;) {
4383 const unsigned base
= load_offset
+ c
* type_size
;
4384 /* Number of usable components in the next block-aligned load. */
4385 const unsigned count
= MIN2(instr
->num_components
- c
,
4386 (block_sz
- base
% block_sz
) / type_size
);
4388 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4389 packed_consts
, surf_index
,
4390 brw_imm_ud(base
& ~(block_sz
- 1)));
4392 const fs_reg consts
=
4393 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4396 for (unsigned d
= 0; d
< count
; d
++)
4397 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4405 case nir_intrinsic_load_global
: {
4406 assert(devinfo
->gen
>= 8);
4408 if (nir_intrinsic_align(instr
) >= 4) {
4409 assert(nir_dest_bit_size(instr
->dest
) == 32);
4410 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4412 get_nir_src(instr
->src
[0]), /* Address */
4413 fs_reg(), /* No source data */
4414 brw_imm_ud(instr
->num_components
));
4415 inst
->size_written
= instr
->num_components
*
4416 inst
->dst
.component_size(inst
->exec_size
);
4418 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4419 assert(bit_size
<= 32);
4420 assert(nir_dest_num_components(instr
->dest
) == 1);
4421 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4422 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4424 get_nir_src(instr
->src
[0]), /* Address */
4425 fs_reg(), /* No source data */
4426 brw_imm_ud(bit_size
));
4427 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4432 case nir_intrinsic_store_global
:
4433 assert(devinfo
->gen
>= 8);
4435 if (stage
== MESA_SHADER_FRAGMENT
)
4436 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4438 if (nir_intrinsic_align(instr
) >= 4) {
4439 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4440 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4442 get_nir_src(instr
->src
[1]), /* Address */
4443 get_nir_src(instr
->src
[0]), /* Data */
4444 brw_imm_ud(instr
->num_components
));
4446 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4447 assert(bit_size
<= 32);
4448 assert(nir_src_num_components(instr
->src
[0]) == 1);
4449 brw_reg_type data_type
=
4450 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4451 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4452 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4453 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4455 get_nir_src(instr
->src
[1]), /* Address */
4457 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4461 case nir_intrinsic_global_atomic_add
:
4462 case nir_intrinsic_global_atomic_imin
:
4463 case nir_intrinsic_global_atomic_umin
:
4464 case nir_intrinsic_global_atomic_imax
:
4465 case nir_intrinsic_global_atomic_umax
:
4466 case nir_intrinsic_global_atomic_and
:
4467 case nir_intrinsic_global_atomic_or
:
4468 case nir_intrinsic_global_atomic_xor
:
4469 case nir_intrinsic_global_atomic_exchange
:
4470 case nir_intrinsic_global_atomic_comp_swap
:
4471 nir_emit_global_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4473 case nir_intrinsic_global_atomic_fmin
:
4474 case nir_intrinsic_global_atomic_fmax
:
4475 case nir_intrinsic_global_atomic_fcomp_swap
:
4476 nir_emit_global_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4479 case nir_intrinsic_load_ssbo
: {
4480 assert(devinfo
->gen
>= 7);
4482 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4483 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4484 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4485 get_nir_ssbo_intrinsic_index(bld
, instr
);
4486 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4487 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4489 /* Make dest unsigned because that's what the temporary will be */
4490 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4492 /* Read the vector */
4493 if (nir_intrinsic_align(instr
) >= 4) {
4494 assert(nir_dest_bit_size(instr
->dest
) == 32);
4495 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4497 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4498 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4499 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4501 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4502 assert(nir_dest_num_components(instr
->dest
) == 1);
4503 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4505 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4506 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4507 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4508 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4513 case nir_intrinsic_store_ssbo
: {
4514 assert(devinfo
->gen
>= 7);
4516 if (stage
== MESA_SHADER_FRAGMENT
)
4517 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4519 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4520 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4521 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4522 get_nir_ssbo_intrinsic_index(bld
, instr
);
4523 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4524 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4526 fs_reg data
= get_nir_src(instr
->src
[0]);
4527 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4529 assert(nir_intrinsic_write_mask(instr
) ==
4530 (1u << instr
->num_components
) - 1);
4531 if (nir_intrinsic_align(instr
) >= 4) {
4532 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4533 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4534 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4535 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4536 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4537 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4539 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4540 assert(nir_src_num_components(instr
->src
[0]) == 1);
4541 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4543 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4544 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4546 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4547 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4552 case nir_intrinsic_store_output
: {
4553 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4554 fs_reg src
= get_nir_src(instr
->src
[0]);
4556 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4557 unsigned num_components
= instr
->num_components
;
4558 unsigned first_component
= nir_intrinsic_component(instr
);
4560 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4561 4 * store_offset
), src
.type
);
4562 for (unsigned j
= 0; j
< num_components
; j
++) {
4563 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4564 offset(src
, bld
, j
));
4569 case nir_intrinsic_ssbo_atomic_add
:
4570 case nir_intrinsic_ssbo_atomic_imin
:
4571 case nir_intrinsic_ssbo_atomic_umin
:
4572 case nir_intrinsic_ssbo_atomic_imax
:
4573 case nir_intrinsic_ssbo_atomic_umax
:
4574 case nir_intrinsic_ssbo_atomic_and
:
4575 case nir_intrinsic_ssbo_atomic_or
:
4576 case nir_intrinsic_ssbo_atomic_xor
:
4577 case nir_intrinsic_ssbo_atomic_exchange
:
4578 case nir_intrinsic_ssbo_atomic_comp_swap
:
4579 nir_emit_ssbo_atomic(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4581 case nir_intrinsic_ssbo_atomic_fmin
:
4582 case nir_intrinsic_ssbo_atomic_fmax
:
4583 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4584 nir_emit_ssbo_atomic_float(bld
, brw_aop_for_nir_intrinsic(instr
), instr
);
4587 case nir_intrinsic_get_buffer_size
: {
4588 assert(nir_src_num_components(instr
->src
[0]) == 1);
4589 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4590 nir_src_as_uint(instr
->src
[0]) : 0;
4592 /* A resinfo's sampler message is used to get the buffer size. The
4593 * SIMD8's writeback message consists of four registers and SIMD16's
4594 * writeback message consists of 8 destination registers (two per each
4595 * component). Because we are only interested on the first channel of
4596 * the first returned component, where resinfo returns the buffer size
4597 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4598 * the dispatch width.
4600 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4601 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4602 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4605 ubld
.MOV(src_payload
, brw_imm_d(0));
4607 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4608 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4609 src_payload
, brw_imm_ud(index
));
4610 inst
->header_size
= 0;
4612 inst
->size_written
= 4 * REG_SIZE
;
4614 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4616 * "Out-of-bounds checking is always performed at a DWord granularity. If
4617 * any part of the DWord is out-of-bounds then the whole DWord is
4618 * considered out-of-bounds."
4620 * This implies that types with size smaller than 4-bytes need to be
4621 * padded if they don't complete the last dword of the buffer. But as we
4622 * need to maintain the original size we need to reverse the padding
4623 * calculation to return the correct size to know the number of elements
4624 * of an unsized array. As we stored in the last two bits of the surface
4625 * size the needed padding for the buffer, we calculate here the
4626 * original buffer_size reversing the surface_size calculation:
4628 * surface_size = isl_align(buffer_size, 4) +
4629 * (isl_align(buffer_size) - buffer_size)
4631 * buffer_size = surface_size & ~3 - surface_size & 3
4634 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4635 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4636 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4638 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4639 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4640 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4642 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4646 case nir_intrinsic_load_subgroup_size
:
4647 /* This should only happen for fragment shaders because every other case
4648 * is lowered in NIR so we can optimize on it.
4650 assert(stage
== MESA_SHADER_FRAGMENT
);
4651 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4654 case nir_intrinsic_load_subgroup_invocation
:
4655 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4656 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4659 case nir_intrinsic_load_subgroup_eq_mask
:
4660 case nir_intrinsic_load_subgroup_ge_mask
:
4661 case nir_intrinsic_load_subgroup_gt_mask
:
4662 case nir_intrinsic_load_subgroup_le_mask
:
4663 case nir_intrinsic_load_subgroup_lt_mask
:
4664 unreachable("not reached");
4666 case nir_intrinsic_vote_any
: {
4667 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4669 /* The any/all predicates do not consider channel enables. To prevent
4670 * dead channels from affecting the result, we initialize the flag with
4671 * with the identity value for the logical operation.
4673 if (dispatch_width
== 32) {
4674 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4675 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4678 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4680 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4682 /* For some reason, the any/all predicates don't work properly with
4683 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4684 * doesn't read the correct subset of the flag register and you end up
4685 * getting garbage in the second half. Work around this by using a pair
4686 * of 1-wide MOVs and scattering the result.
4688 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4689 ubld
.MOV(res1
, brw_imm_d(0));
4690 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4691 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4692 BRW_PREDICATE_ALIGN1_ANY32H
,
4693 ubld
.MOV(res1
, brw_imm_d(-1)));
4695 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4698 case nir_intrinsic_vote_all
: {
4699 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4701 /* The any/all predicates do not consider channel enables. To prevent
4702 * dead channels from affecting the result, we initialize the flag with
4703 * with the identity value for the logical operation.
4705 if (dispatch_width
== 32) {
4706 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4707 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4708 brw_imm_ud(0xffffffff));
4710 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4712 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4714 /* For some reason, the any/all predicates don't work properly with
4715 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4716 * doesn't read the correct subset of the flag register and you end up
4717 * getting garbage in the second half. Work around this by using a pair
4718 * of 1-wide MOVs and scattering the result.
4720 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4721 ubld
.MOV(res1
, brw_imm_d(0));
4722 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4723 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4724 BRW_PREDICATE_ALIGN1_ALL32H
,
4725 ubld
.MOV(res1
, brw_imm_d(-1)));
4727 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4730 case nir_intrinsic_vote_feq
:
4731 case nir_intrinsic_vote_ieq
: {
4732 fs_reg value
= get_nir_src(instr
->src
[0]);
4733 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4734 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4735 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4736 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4739 fs_reg uniformized
= bld
.emit_uniformize(value
);
4740 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4742 /* The any/all predicates do not consider channel enables. To prevent
4743 * dead channels from affecting the result, we initialize the flag with
4744 * with the identity value for the logical operation.
4746 if (dispatch_width
== 32) {
4747 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4748 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4749 brw_imm_ud(0xffffffff));
4751 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4753 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4755 /* For some reason, the any/all predicates don't work properly with
4756 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4757 * doesn't read the correct subset of the flag register and you end up
4758 * getting garbage in the second half. Work around this by using a pair
4759 * of 1-wide MOVs and scattering the result.
4761 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4762 ubld
.MOV(res1
, brw_imm_d(0));
4763 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4764 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4765 BRW_PREDICATE_ALIGN1_ALL32H
,
4766 ubld
.MOV(res1
, brw_imm_d(-1)));
4768 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4772 case nir_intrinsic_ballot
: {
4773 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4774 BRW_REGISTER_TYPE_UD
);
4775 struct brw_reg flag
= brw_flag_reg(0, 0);
4776 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4777 * as f0.0. This is a problem for fragment programs as we currently use
4778 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4779 * programs yet so this isn't a problem. When we do, something will
4782 if (dispatch_width
== 32)
4783 flag
.type
= BRW_REGISTER_TYPE_UD
;
4785 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4786 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4788 if (instr
->dest
.ssa
.bit_size
> 32) {
4789 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4791 dest
.type
= BRW_REGISTER_TYPE_UD
;
4793 bld
.MOV(dest
, flag
);
4797 case nir_intrinsic_read_invocation
: {
4798 const fs_reg value
= get_nir_src(instr
->src
[0]);
4799 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4800 fs_reg tmp
= bld
.vgrf(value
.type
);
4802 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4803 bld
.emit_uniformize(invocation
));
4805 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4809 case nir_intrinsic_read_first_invocation
: {
4810 const fs_reg value
= get_nir_src(instr
->src
[0]);
4811 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4815 case nir_intrinsic_shuffle
: {
4816 const fs_reg value
= get_nir_src(instr
->src
[0]);
4817 const fs_reg index
= get_nir_src(instr
->src
[1]);
4819 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4823 case nir_intrinsic_first_invocation
: {
4824 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4825 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4826 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4827 fs_reg(component(tmp
, 0)));
4831 case nir_intrinsic_quad_broadcast
: {
4832 const fs_reg value
= get_nir_src(instr
->src
[0]);
4833 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4835 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4836 value
, brw_imm_ud(index
), brw_imm_ud(4));
4840 case nir_intrinsic_quad_swap_horizontal
: {
4841 const fs_reg value
= get_nir_src(instr
->src
[0]);
4842 const fs_reg tmp
= bld
.vgrf(value
.type
);
4843 if (devinfo
->gen
<= 7) {
4844 /* The hardware doesn't seem to support these crazy regions with
4845 * compressed instructions on gen7 and earlier so we fall back to
4846 * using quad swizzles. Fortunately, we don't support 64-bit
4847 * anything in Vulkan on gen7.
4849 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4850 const fs_builder ubld
= bld
.exec_all();
4851 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4852 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
4853 bld
.MOV(retype(dest
, value
.type
), tmp
);
4855 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4857 const fs_reg src_left
= horiz_stride(value
, 2);
4858 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4859 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4860 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4862 ubld
.MOV(tmp_left
, src_right
);
4863 ubld
.MOV(tmp_right
, src_left
);
4866 bld
.MOV(retype(dest
, value
.type
), tmp
);
4870 case nir_intrinsic_quad_swap_vertical
: {
4871 const fs_reg value
= get_nir_src(instr
->src
[0]);
4872 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4873 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4874 const fs_reg tmp
= bld
.vgrf(value
.type
);
4875 const fs_builder ubld
= bld
.exec_all();
4876 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4877 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4878 bld
.MOV(retype(dest
, value
.type
), tmp
);
4880 /* For larger data types, we have to either emit dispatch_width many
4881 * MOVs or else fall back to doing indirects.
4883 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4884 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4886 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4891 case nir_intrinsic_quad_swap_diagonal
: {
4892 const fs_reg value
= get_nir_src(instr
->src
[0]);
4893 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4894 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4895 const fs_reg tmp
= bld
.vgrf(value
.type
);
4896 const fs_builder ubld
= bld
.exec_all();
4897 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4898 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4899 bld
.MOV(retype(dest
, value
.type
), tmp
);
4901 /* For larger data types, we have to either emit dispatch_width many
4902 * MOVs or else fall back to doing indirects.
4904 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4905 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4907 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4912 case nir_intrinsic_reduce
: {
4913 fs_reg src
= get_nir_src(instr
->src
[0]);
4914 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4915 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4916 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4917 cluster_size
= dispatch_width
;
4919 /* Figure out the source type */
4920 src
.type
= brw_type_for_nir_type(devinfo
,
4921 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4922 nir_src_bit_size(instr
->src
[0])));
4924 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4925 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4926 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4928 /* Set up a register for all of our scratching around and initialize it
4929 * to reduction operation's identity value.
4931 fs_reg scan
= bld
.vgrf(src
.type
);
4932 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4934 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4936 dest
.type
= src
.type
;
4937 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4938 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4939 * the distance between clusters is at least 2 GRFs. In this case,
4940 * we don't need the weird striding of the CLUSTER_BROADCAST
4941 * instruction and can just do regular MOVs.
4943 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4944 const unsigned groups
=
4945 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4946 const unsigned group_size
= dispatch_width
/ groups
;
4947 for (unsigned i
= 0; i
< groups
; i
++) {
4948 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4949 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4950 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4951 component(scan
, comp
));
4954 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4955 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4960 case nir_intrinsic_inclusive_scan
:
4961 case nir_intrinsic_exclusive_scan
: {
4962 fs_reg src
= get_nir_src(instr
->src
[0]);
4963 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4965 /* Figure out the source type */
4966 src
.type
= brw_type_for_nir_type(devinfo
,
4967 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4968 nir_src_bit_size(instr
->src
[0])));
4970 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4971 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4972 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4974 /* Set up a register for all of our scratching around and initialize it
4975 * to reduction operation's identity value.
4977 fs_reg scan
= bld
.vgrf(src
.type
);
4978 const fs_builder allbld
= bld
.exec_all();
4979 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4981 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4982 /* Exclusive scan is a bit harder because we have to do an annoying
4983 * shift of the contents before we can begin. To make things worse,
4984 * we can't do this with a normal stride; we have to use indirects.
4986 fs_reg shifted
= bld
.vgrf(src
.type
);
4987 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4988 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4990 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4991 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4995 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4997 bld
.MOV(retype(dest
, src
.type
), scan
);
5001 case nir_intrinsic_begin_invocation_interlock
: {
5002 const fs_builder ubld
= bld
.group(8, 0);
5003 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5005 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
5006 ->size_written
= 2 * REG_SIZE
;
5010 case nir_intrinsic_end_invocation_interlock
: {
5011 /* For endInvocationInterlock(), we need to insert a memory fence which
5012 * stalls in the shader until the memory transactions prior to that
5013 * fence are complete. This ensures that the shader does not end before
5014 * any writes from its critical section have landed. Otherwise, you can
5015 * end up with a case where the next invocation on that pixel properly
5016 * stalls for previous FS invocation on its pixel to complete but
5017 * doesn't actually wait for the dataport memory transactions from that
5018 * thread to land before submitting its own.
5020 const fs_builder ubld
= bld
.group(8, 0);
5021 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5022 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
5023 brw_vec8_grf(0, 0), brw_imm_ud(1), brw_imm_ud(0))
5024 ->size_written
= 2 * REG_SIZE
;
5029 unreachable("unknown intrinsic");
5034 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5035 int op
, nir_intrinsic_instr
*instr
)
5037 if (stage
== MESA_SHADER_FRAGMENT
)
5038 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5040 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5041 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5042 * appear to exist. However, if you look at Vol 2a, there are no message
5043 * descriptors provided for Qword atomic ops except for A64 messages.
5045 assert(nir_dest_bit_size(instr
->dest
) == 32);
5048 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5049 dest
= get_nir_dest(instr
->dest
);
5051 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5052 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5053 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5054 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5055 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5058 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5059 data
= get_nir_src(instr
->src
[2]);
5061 if (op
== BRW_AOP_CMPWR
) {
5062 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5063 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5064 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5067 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5069 /* Emit the actual atomic operation */
5071 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5072 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5076 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5077 int op
, nir_intrinsic_instr
*instr
)
5079 if (stage
== MESA_SHADER_FRAGMENT
)
5080 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5083 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5084 dest
= get_nir_dest(instr
->dest
);
5086 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5087 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5088 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5089 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5090 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5092 fs_reg data
= get_nir_src(instr
->src
[2]);
5093 if (op
== BRW_AOP_FCMPWR
) {
5094 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5095 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5096 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5099 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5101 /* Emit the actual atomic operation */
5103 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5104 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5108 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5109 int op
, nir_intrinsic_instr
*instr
)
5112 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5113 dest
= get_nir_dest(instr
->dest
);
5115 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5116 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5117 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5118 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5121 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5122 data
= get_nir_src(instr
->src
[1]);
5123 if (op
== BRW_AOP_CMPWR
) {
5124 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5125 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5126 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5129 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5131 /* Get the offset */
5132 if (nir_src_is_const(instr
->src
[0])) {
5133 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5134 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5136 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5137 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5138 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5139 brw_imm_ud(instr
->const_index
[0]));
5142 /* Emit the actual atomic operation operation */
5144 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5145 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5149 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5150 int op
, nir_intrinsic_instr
*instr
)
5153 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5154 dest
= get_nir_dest(instr
->dest
);
5156 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5157 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5158 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5159 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5161 fs_reg data
= get_nir_src(instr
->src
[1]);
5162 if (op
== BRW_AOP_FCMPWR
) {
5163 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5164 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5165 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5168 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5170 /* Get the offset */
5171 if (nir_src_is_const(instr
->src
[0])) {
5172 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5173 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5175 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5176 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5177 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5178 brw_imm_ud(instr
->const_index
[0]));
5181 /* Emit the actual atomic operation operation */
5183 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5184 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5188 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5189 int op
, nir_intrinsic_instr
*instr
)
5191 if (stage
== MESA_SHADER_FRAGMENT
)
5192 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5195 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5196 dest
= get_nir_dest(instr
->dest
);
5198 fs_reg addr
= get_nir_src(instr
->src
[0]);
5201 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5202 data
= get_nir_src(instr
->src
[1]);
5204 if (op
== BRW_AOP_CMPWR
) {
5205 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5206 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5207 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5211 if (nir_dest_bit_size(instr
->dest
) == 64) {
5212 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5213 dest
, addr
, data
, brw_imm_ud(op
));
5215 assert(nir_dest_bit_size(instr
->dest
) == 32);
5216 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5217 dest
, addr
, data
, brw_imm_ud(op
));
5222 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5223 int op
, nir_intrinsic_instr
*instr
)
5225 if (stage
== MESA_SHADER_FRAGMENT
)
5226 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5228 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5229 fs_reg dest
= get_nir_dest(instr
->dest
);
5231 fs_reg addr
= get_nir_src(instr
->src
[0]);
5233 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5234 fs_reg data
= get_nir_src(instr
->src
[1]);
5236 if (op
== BRW_AOP_FCMPWR
) {
5237 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5238 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5239 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5243 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5244 dest
, addr
, data
, brw_imm_ud(op
));
5248 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5250 unsigned texture
= instr
->texture_index
;
5251 unsigned sampler
= instr
->sampler_index
;
5253 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5255 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5256 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5258 int lod_components
= 0;
5260 /* The hardware requires a LOD for buffer textures */
5261 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5262 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5264 uint32_t header_bits
= 0;
5265 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5266 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5267 switch (instr
->src
[i
].src_type
) {
5268 case nir_tex_src_bias
:
5269 srcs
[TEX_LOGICAL_SRC_LOD
] =
5270 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5272 case nir_tex_src_comparator
:
5273 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5275 case nir_tex_src_coord
:
5276 switch (instr
->op
) {
5278 case nir_texop_txf_ms
:
5279 case nir_texop_txf_ms_mcs
:
5280 case nir_texop_samples_identical
:
5281 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5284 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5288 case nir_tex_src_ddx
:
5289 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5290 lod_components
= nir_tex_instr_src_size(instr
, i
);
5292 case nir_tex_src_ddy
:
5293 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5295 case nir_tex_src_lod
:
5296 switch (instr
->op
) {
5298 srcs
[TEX_LOGICAL_SRC_LOD
] =
5299 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5302 srcs
[TEX_LOGICAL_SRC_LOD
] =
5303 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5306 srcs
[TEX_LOGICAL_SRC_LOD
] =
5307 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5311 case nir_tex_src_min_lod
:
5312 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5313 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5315 case nir_tex_src_ms_index
:
5316 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5319 case nir_tex_src_offset
: {
5320 uint32_t offset_bits
= 0;
5321 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5322 header_bits
|= offset_bits
;
5324 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5325 retype(src
, BRW_REGISTER_TYPE_D
);
5330 case nir_tex_src_projector
:
5331 unreachable("should be lowered");
5333 case nir_tex_src_texture_offset
: {
5334 /* Emit code to evaluate the actual indexing expression */
5335 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5336 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5337 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5341 case nir_tex_src_sampler_offset
: {
5342 /* Emit code to evaluate the actual indexing expression */
5343 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5344 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5345 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5349 case nir_tex_src_texture_handle
:
5350 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5351 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5352 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5355 case nir_tex_src_sampler_handle
:
5356 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5357 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5358 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5361 case nir_tex_src_ms_mcs
:
5362 assert(instr
->op
== nir_texop_txf_ms
);
5363 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5366 case nir_tex_src_plane
: {
5367 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5368 const uint32_t texture_index
=
5369 instr
->texture_index
+
5370 stage_prog_data
->binding_table
.plane_start
[plane
] -
5371 stage_prog_data
->binding_table
.texture_start
;
5373 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5378 unreachable("unknown texture source");
5382 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5383 (instr
->op
== nir_texop_txf_ms
||
5384 instr
->op
== nir_texop_samples_identical
)) {
5385 if (devinfo
->gen
>= 7 &&
5386 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5387 srcs
[TEX_LOGICAL_SRC_MCS
] =
5388 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5389 instr
->coord_components
,
5390 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5391 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5393 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5397 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5398 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5401 switch (instr
->op
) {
5403 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5406 opcode
= FS_OPCODE_TXB_LOGICAL
;
5409 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5412 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5415 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5417 case nir_texop_txf_ms
:
5418 if ((key_tex
->msaa_16
& (1 << sampler
)))
5419 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5421 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5423 case nir_texop_txf_ms_mcs
:
5424 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5426 case nir_texop_query_levels
:
5428 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5431 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5434 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5435 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5437 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5439 case nir_texop_texture_samples
:
5440 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5442 case nir_texop_samples_identical
: {
5443 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5445 /* If mcs is an immediate value, it means there is no MCS. In that case
5446 * just return false.
5448 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5449 bld
.MOV(dst
, brw_imm_ud(0u));
5450 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5451 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5452 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5453 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5454 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5456 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5457 BRW_CONDITIONAL_EQ
);
5462 unreachable("unknown texture opcode");
5465 if (instr
->op
== nir_texop_tg4
) {
5466 if (instr
->component
== 1 &&
5467 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5468 /* gather4 sampler is broken for green channel on RG32F --
5469 * we must ask for blue instead.
5471 header_bits
|= 2 << 16;
5473 header_bits
|= instr
->component
<< 16;
5477 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5478 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5479 inst
->offset
= header_bits
;
5481 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5482 if (devinfo
->gen
>= 9 &&
5483 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5484 unsigned write_mask
= instr
->dest
.is_ssa
?
5485 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5486 (1 << dest_size
) - 1;
5487 assert(write_mask
!= 0); /* dead code should have been eliminated */
5488 inst
->size_written
= util_last_bit(write_mask
) *
5489 inst
->dst
.component_size(inst
->exec_size
);
5491 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5494 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5495 inst
->shadow_compare
= true;
5497 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5498 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5501 for (unsigned i
= 0; i
< dest_size
; i
++)
5502 nir_dest
[i
] = offset(dst
, bld
, i
);
5504 if (instr
->op
== nir_texop_query_levels
) {
5505 /* # levels is in .w */
5506 nir_dest
[0] = offset(dst
, bld
, 3);
5507 } else if (instr
->op
== nir_texop_txs
&&
5508 dest_size
>= 3 && devinfo
->gen
< 7) {
5509 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5510 fs_reg depth
= offset(dst
, bld
, 2);
5511 nir_dest
[2] = vgrf(glsl_type::int_type
);
5512 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5515 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5519 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5521 switch (instr
->type
) {
5522 case nir_jump_break
:
5523 bld
.emit(BRW_OPCODE_BREAK
);
5525 case nir_jump_continue
:
5526 bld
.emit(BRW_OPCODE_CONTINUE
);
5528 case nir_jump_return
:
5530 unreachable("unknown jump");
5535 * This helper takes a source register and un/shuffles it into the destination
5538 * If source type size is smaller than destination type size the operation
5539 * needed is a component shuffle. The opposite case would be an unshuffle. If
5540 * source/destination type size is equal a shuffle is done that would be
5541 * equivalent to a simple MOV.
5543 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5544 * components .xyz 16-bit vector on SIMD8 would be.
5546 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5547 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5549 * This helper will return the following 2 32-bit components with the 16-bit
5552 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5553 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5555 * For unshuffle, the example would be the opposite, a 64-bit type source
5556 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5559 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5560 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5561 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5562 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5564 * The returned result would be the following 4 32-bit components unshuffled:
5566 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5567 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5568 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5569 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5571 * - Source and destination register must not be overlapped.
5572 * - components units are measured in terms of the smaller type between
5573 * source and destination because we are un/shuffling the smaller
5574 * components from/into the bigger ones.
5575 * - first_component parameter allows skipping source components.
5578 shuffle_src_to_dst(const fs_builder
&bld
,
5581 uint32_t first_component
,
5582 uint32_t components
)
5584 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5585 assert(!regions_overlap(dst
,
5586 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5587 offset(src
, bld
, first_component
),
5588 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5589 for (unsigned i
= 0; i
< components
; i
++) {
5590 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5591 offset(src
, bld
, i
+ first_component
));
5593 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5594 /* Source is shuffled into destination */
5595 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5596 assert(!regions_overlap(dst
,
5597 type_sz(dst
.type
) * bld
.dispatch_width() *
5598 DIV_ROUND_UP(components
, size_ratio
),
5599 offset(src
, bld
, first_component
),
5600 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5602 brw_reg_type shuffle_type
=
5603 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5604 BRW_REGISTER_TYPE_D
);
5605 for (unsigned i
= 0; i
< components
; i
++) {
5606 fs_reg shuffle_component_i
=
5607 subscript(offset(dst
, bld
, i
/ size_ratio
),
5608 shuffle_type
, i
% size_ratio
);
5609 bld
.MOV(shuffle_component_i
,
5610 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5613 /* Source is unshuffled into destination */
5614 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5615 assert(!regions_overlap(dst
,
5616 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5617 offset(src
, bld
, first_component
/ size_ratio
),
5618 type_sz(src
.type
) * bld
.dispatch_width() *
5619 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5622 brw_reg_type shuffle_type
=
5623 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5624 BRW_REGISTER_TYPE_D
);
5625 for (unsigned i
= 0; i
< components
; i
++) {
5626 fs_reg shuffle_component_i
=
5627 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5628 shuffle_type
, (first_component
+ i
) % size_ratio
);
5629 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5630 shuffle_component_i
);
5636 shuffle_from_32bit_read(const fs_builder
&bld
,
5639 uint32_t first_component
,
5640 uint32_t components
)
5642 assert(type_sz(src
.type
) == 4);
5644 /* This function takes components in units of the destination type while
5645 * shuffle_src_to_dst takes components in units of the smallest type
5647 if (type_sz(dst
.type
) > 4) {
5648 assert(type_sz(dst
.type
) == 8);
5649 first_component
*= 2;
5653 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5657 setup_imm_df(const fs_builder
&bld
, double v
)
5659 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5660 assert(devinfo
->gen
>= 7);
5662 if (devinfo
->gen
>= 8)
5663 return brw_imm_df(v
);
5665 /* gen7.5 does not support DF immediates straighforward but the DIM
5666 * instruction allows to set the 64-bit immediate value.
5668 if (devinfo
->is_haswell
) {
5669 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5670 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5671 ubld
.DIM(dst
, brw_imm_df(v
));
5672 return component(dst
, 0);
5675 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5676 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5677 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5679 * Alternatively, we could also produce a normal VGRF (without stride 0)
5680 * by writing to all the channels in the VGRF, however, that would hit the
5681 * gen7 bug where we have to split writes that span more than 1 register
5682 * into instructions with a width of 4 (otherwise the write to the second
5683 * register written runs into an execmask hardware bug) which isn't very
5696 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5697 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5698 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5699 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5701 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5705 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5707 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5708 bld
.MOV(tmp
, brw_imm_w(v
));
5713 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5715 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5716 bld
.MOV(tmp
, brw_imm_uw(v
));