2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 nir_foreach_variable(var
, &nir
->outputs
) {
57 const unsigned vec4s
=
58 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
59 : type_size_vec4(var
->type
);
60 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
);
61 for (unsigned i
= 0; i
< vec4s
; i
++) {
62 if (outputs
[var
->data
.driver_location
+ i
].file
== BAD_FILE
)
63 outputs
[var
->data
.driver_location
+ i
] = offset(reg
, bld
, 4 * i
);
69 fs_visitor::nir_setup_uniforms()
71 if (dispatch_width
!= min_dispatch_width
)
74 uniforms
= nir
->num_uniforms
/ 4;
78 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
82 nir_foreach_instr(instr
, block
) {
83 if (instr
->type
!= nir_instr_type_intrinsic
)
86 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
87 switch (intrin
->intrinsic
) {
88 case nir_intrinsic_load_vertex_id
:
89 unreachable("should be lowered by lower_vertex_id().");
91 case nir_intrinsic_load_vertex_id_zero_base
:
92 assert(v
->stage
== MESA_SHADER_VERTEX
);
93 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
94 if (reg
->file
== BAD_FILE
)
95 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
98 case nir_intrinsic_load_base_vertex
:
99 assert(v
->stage
== MESA_SHADER_VERTEX
);
100 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
101 if (reg
->file
== BAD_FILE
)
102 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
105 case nir_intrinsic_load_instance_id
:
106 assert(v
->stage
== MESA_SHADER_VERTEX
);
107 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
108 if (reg
->file
== BAD_FILE
)
109 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
112 case nir_intrinsic_load_base_instance
:
113 assert(v
->stage
== MESA_SHADER_VERTEX
);
114 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
115 if (reg
->file
== BAD_FILE
)
116 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
119 case nir_intrinsic_load_draw_id
:
120 assert(v
->stage
== MESA_SHADER_VERTEX
);
121 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
122 if (reg
->file
== BAD_FILE
)
123 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
126 case nir_intrinsic_load_invocation_id
:
127 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
129 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
130 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
131 if (reg
->file
== BAD_FILE
) {
132 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
133 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
134 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
135 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
140 case nir_intrinsic_load_sample_pos
:
141 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
142 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
143 if (reg
->file
== BAD_FILE
)
144 *reg
= *v
->emit_samplepos_setup();
147 case nir_intrinsic_load_sample_id
:
148 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_sampleid_setup();
154 case nir_intrinsic_load_sample_mask_in
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 assert(v
->devinfo
->gen
>= 7);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_samplemaskin_setup();
162 case nir_intrinsic_load_work_group_id
:
163 assert(v
->stage
== MESA_SHADER_COMPUTE
);
164 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
165 if (reg
->file
== BAD_FILE
)
166 *reg
= *v
->emit_cs_work_group_id_setup();
169 case nir_intrinsic_load_helper_invocation
:
170 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
171 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
172 if (reg
->file
== BAD_FILE
) {
173 const fs_builder abld
=
174 v
->bld
.annotate("gl_HelperInvocation", NULL
);
176 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
177 * pixel mask is in g1.7 of the thread payload.
179 * We move the per-channel pixel enable bit to the low bit of each
180 * channel by shifting the byte containing the pixel mask by the
181 * vector immediate 0x76543210UV.
183 * The region of <1,8,0> reads only 1 byte (the pixel masks for
184 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
185 * masks for 2 and 3) in SIMD16.
187 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
189 stride(byte_offset(retype(brw_vec1_grf(1, 0),
190 BRW_REGISTER_TYPE_UB
), 28),
192 brw_imm_v(0x76543210));
194 /* A set bit in the pixel mask means the channel is enabled, but
195 * that is the opposite of gl_HelperInvocation so we need to invert
198 * The negate source-modifier bit of logical instructions on Gen8+
199 * performs 1's complement negation, so we can use that instead of
202 fs_reg inverted
= negate(shifted
);
203 if (v
->devinfo
->gen
< 8) {
204 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
205 abld
.NOT(inverted
, shifted
);
208 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
209 * with 1 and negating.
211 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
212 abld
.AND(anded
, inverted
, brw_imm_uw(1));
214 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
215 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
229 fs_visitor::nir_emit_system_values()
231 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
232 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
233 nir_system_values
[i
] = fs_reg();
236 nir_foreach_function(function
, nir
) {
237 assert(strcmp(function
->name
, "main") == 0);
238 assert(function
->impl
);
239 nir_foreach_block(block
, function
->impl
) {
240 emit_system_values_block(block
, this);
246 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
248 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
249 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
250 nir_locals
[i
] = fs_reg();
253 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
254 unsigned array_elems
=
255 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
256 unsigned size
= array_elems
* reg
->num_components
;
257 const brw_reg_type reg_type
=
258 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
259 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
262 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
265 nir_emit_cf_list(&impl
->body
);
269 fs_visitor::nir_emit_cf_list(exec_list
*list
)
271 exec_list_validate(list
);
272 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
273 switch (node
->type
) {
275 nir_emit_if(nir_cf_node_as_if(node
));
278 case nir_cf_node_loop
:
279 nir_emit_loop(nir_cf_node_as_loop(node
));
282 case nir_cf_node_block
:
283 nir_emit_block(nir_cf_node_as_block(node
));
287 unreachable("Invalid CFG node block");
293 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
295 /* first, put the condition into f0 */
296 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
297 retype(get_nir_src(if_stmt
->condition
),
298 BRW_REGISTER_TYPE_D
));
299 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
301 bld
.IF(BRW_PREDICATE_NORMAL
);
303 nir_emit_cf_list(&if_stmt
->then_list
);
305 /* note: if the else is empty, dead CF elimination will remove it */
306 bld
.emit(BRW_OPCODE_ELSE
);
308 nir_emit_cf_list(&if_stmt
->else_list
);
310 bld
.emit(BRW_OPCODE_ENDIF
);
314 fs_visitor::nir_emit_loop(nir_loop
*loop
)
316 bld
.emit(BRW_OPCODE_DO
);
318 nir_emit_cf_list(&loop
->body
);
320 bld
.emit(BRW_OPCODE_WHILE
);
324 fs_visitor::nir_emit_block(nir_block
*block
)
326 nir_foreach_instr(instr
, block
) {
327 nir_emit_instr(instr
);
332 fs_visitor::nir_emit_instr(nir_instr
*instr
)
334 const fs_builder abld
= bld
.annotate(NULL
, instr
);
336 switch (instr
->type
) {
337 case nir_instr_type_alu
:
338 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
341 case nir_instr_type_intrinsic
:
343 case MESA_SHADER_VERTEX
:
344 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
346 case MESA_SHADER_TESS_CTRL
:
347 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
349 case MESA_SHADER_TESS_EVAL
:
350 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
352 case MESA_SHADER_GEOMETRY
:
353 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
355 case MESA_SHADER_FRAGMENT
:
356 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
358 case MESA_SHADER_COMPUTE
:
359 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
362 unreachable("unsupported shader stage");
366 case nir_instr_type_tex
:
367 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
370 case nir_instr_type_load_const
:
371 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
374 case nir_instr_type_ssa_undef
:
375 /* We create a new VGRF for undefs on every use (by handling
376 * them in get_nir_src()), rather than for each definition.
377 * This helps register coalescing eliminate MOVs from undef.
381 case nir_instr_type_jump
:
382 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
386 unreachable("unknown instruction type");
391 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
395 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
396 const fs_reg
&result
)
398 if (!instr
->src
[0].src
.is_ssa
||
399 !instr
->src
[0].src
.ssa
->parent_instr
)
402 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
405 nir_alu_instr
*src0
=
406 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
408 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
409 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
412 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
413 assert(element
!= NULL
);
415 /* Element type to extract.*/
416 const brw_reg_type type
= brw_int_type(
417 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
418 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
420 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
421 op0
.type
= brw_type_for_nir_type(devinfo
,
422 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
423 nir_src_bit_size(src0
->src
[0].src
)));
424 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
426 set_saturate(instr
->dest
.saturate
,
427 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
432 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
433 const fs_reg
&result
)
435 if (!instr
->src
[0].src
.is_ssa
||
436 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
439 nir_intrinsic_instr
*src0
=
440 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
442 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
445 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
446 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
449 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
450 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
453 fs_reg tmp
= vgrf(glsl_type::int_type
);
455 if (devinfo
->gen
>= 6) {
456 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
457 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
459 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
461 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
462 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
464 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
466 * This negation looks like it's safe in practice, because bits 0:4 will
467 * surely be TRIANGLES
470 if (value1
->f32
[0] == -1.0f
) {
474 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
475 g0
, brw_imm_uw(0x3f80));
477 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
478 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
480 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
482 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
483 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
485 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
487 * This negation looks like it's safe in practice, because bits 0:4 will
488 * surely be TRIANGLES
491 if (value1
->f32
[0] == -1.0f
) {
495 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
497 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
503 emit_find_msb_using_lzd(const fs_builder
&bld
,
504 const fs_reg
&result
,
512 /* LZD of an absolute value source almost always does the right
513 * thing. There are two problem values:
515 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
516 * 0. However, findMSB(int(0x80000000)) == 30.
518 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
519 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
521 * For a value of zero or negative one, -1 will be returned.
523 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
524 * findMSB(-(1<<x)) should return x-1.
526 * For all negative number cases, including 0x80000000 and
527 * 0xffffffff, the correct value is obtained from LZD if instead of
528 * negating the (already negative) value the logical-not is used. A
529 * conditonal logical-not can be achieved in two instructions.
531 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
533 bld
.ASR(temp
, src
, brw_imm_d(31));
534 bld
.XOR(temp
, temp
, src
);
537 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
538 retype(temp
, BRW_REGISTER_TYPE_UD
));
540 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
541 * from the LSB side. Subtract the result from 31 to convert the MSB
542 * count into an LSB count. If no bits are set, LZD will return 32.
543 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
545 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
546 inst
->src
[0].negate
= true;
550 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
552 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
555 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
556 result
.type
= brw_type_for_nir_type(devinfo
,
557 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
558 nir_dest_bit_size(instr
->dest
.dest
)));
561 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
562 op
[i
] = get_nir_src(instr
->src
[i
].src
);
563 op
[i
].type
= brw_type_for_nir_type(devinfo
,
564 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
565 nir_src_bit_size(instr
->src
[i
].src
)));
566 op
[i
].abs
= instr
->src
[i
].abs
;
567 op
[i
].negate
= instr
->src
[i
].negate
;
570 /* We get a bunch of mov's out of the from_ssa pass and they may still
571 * be vectorized. We'll handle them as a special-case. We'll also
572 * handle vecN here because it's basically the same thing.
580 fs_reg temp
= result
;
581 bool need_extra_copy
= false;
582 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
583 if (!instr
->src
[i
].src
.is_ssa
&&
584 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
585 need_extra_copy
= true;
586 temp
= bld
.vgrf(result
.type
, 4);
591 for (unsigned i
= 0; i
< 4; i
++) {
592 if (!(instr
->dest
.write_mask
& (1 << i
)))
595 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
596 inst
= bld
.MOV(offset(temp
, bld
, i
),
597 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
599 inst
= bld
.MOV(offset(temp
, bld
, i
),
600 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
602 inst
->saturate
= instr
->dest
.saturate
;
605 /* In this case the source and destination registers were the same,
606 * so we need to insert an extra set of moves in order to deal with
609 if (need_extra_copy
) {
610 for (unsigned i
= 0; i
< 4; i
++) {
611 if (!(instr
->dest
.write_mask
& (1 << i
)))
614 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
623 /* At this point, we have dealt with any instruction that operates on
624 * more than a single channel. Therefore, we can just adjust the source
625 * and destination registers for that channel and emit the instruction.
627 unsigned channel
= 0;
628 if (nir_op_infos
[instr
->op
].output_size
== 0) {
629 /* Since NIR is doing the scalarizing for us, we should only ever see
630 * vectorized operations with a single channel.
632 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
633 channel
= ffs(instr
->dest
.write_mask
) - 1;
635 result
= offset(result
, bld
, channel
);
638 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
639 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
640 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
646 if (optimize_extract_to_float(instr
, result
))
648 inst
= bld
.MOV(result
, op
[0]);
649 inst
->saturate
= instr
->dest
.saturate
;
655 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
657 * "When source or destination is 64b (...), regioning in Align1
658 * must follow these rules:
660 * 1. Source and destination horizontal stride must be aligned to
664 * This means that 32-bit to 64-bit conversions need to have the 32-bit
665 * data elements aligned to 64-bit. This restriction does not apply to
668 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
669 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
670 (devinfo
->is_cherryview
|| devinfo
->is_broxton
)) {
671 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
672 tmp
= subscript(tmp
, op
[0].type
, 0);
673 inst
= bld
.MOV(tmp
, op
[0]);
674 inst
= bld
.MOV(result
, tmp
);
675 inst
->saturate
= instr
->dest
.saturate
;
688 inst
= bld
.MOV(result
, op
[0]);
689 inst
->saturate
= instr
->dest
.saturate
;
694 /* Straightforward since the source can be assumed to be
697 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
698 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
700 } else if (type_sz(op
[0].type
) < 8) {
701 /* AND(val, 0x80000000) gives the sign bit.
703 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
706 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
708 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
709 op
[0].type
= BRW_REGISTER_TYPE_UD
;
710 result
.type
= BRW_REGISTER_TYPE_UD
;
711 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
713 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
714 inst
->predicate
= BRW_PREDICATE_NORMAL
;
715 if (instr
->dest
.saturate
) {
716 inst
= bld
.MOV(result
, result
);
717 inst
->saturate
= true;
720 /* For doubles we do the same but we need to consider:
722 * - 2-src instructions can't operate with 64-bit immediates
723 * - The sign is encoded in the high 32-bit of each DF
724 * - CMP with DF requires special handling in SIMD16
725 * - We need to produce a DF result.
728 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
729 * a register and compare with that.
731 fs_reg tmp
= vgrf(glsl_type::double_type
);
732 bld
.MOV(tmp
, setup_imm_df(bld
, 0.0));
734 /* A direct DF CMP using the flag register (null dst) won't work in
735 * SIMD16 because the CMP will be split in two by lower_simd_width,
736 * resulting in two CMP instructions with the same dst (NULL),
737 * leading to dead code elimination of the first one. In SIMD8,
738 * however, there is no need to split the CMP and we can save some
741 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
742 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
744 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
745 * so we store the result of the comparison in a vgrf instead and
746 * then we generate a UD comparison from that that won't have to
747 * be split by lower_simd_width. This is what NIR does to handle
748 * double comparisons in the general case.
750 if (bld
.dispatch_width() == 16 ) {
751 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
752 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
753 bld
.CMP(bld
.null_reg_ud(),
754 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
757 /* Get the high 32-bit of each double component where the sign is */
758 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
759 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
761 /* Get the sign bit */
762 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
764 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
765 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
766 inst
->predicate
= BRW_PREDICATE_NORMAL
;
768 /* Convert from 32-bit float to 64-bit double */
769 result
.type
= BRW_REGISTER_TYPE_DF
;
770 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
772 if (instr
->dest
.saturate
) {
773 inst
= bld
.MOV(result
, result
);
774 inst
->saturate
= true;
781 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
782 * -> non-negative val generates 0x00000000.
783 * Predicated OR sets 1 if val is positive.
785 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
786 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
787 bld
.ASR(result
, op
[0], brw_imm_d(31));
788 inst
= bld
.OR(result
, result
, brw_imm_d(1));
789 inst
->predicate
= BRW_PREDICATE_NORMAL
;
793 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
794 inst
->saturate
= instr
->dest
.saturate
;
798 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
799 inst
->saturate
= instr
->dest
.saturate
;
803 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
804 inst
->saturate
= instr
->dest
.saturate
;
808 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
809 inst
->saturate
= instr
->dest
.saturate
;
813 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
814 inst
->saturate
= instr
->dest
.saturate
;
818 if (fs_key
->high_quality_derivatives
) {
819 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
821 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
823 inst
->saturate
= instr
->dest
.saturate
;
825 case nir_op_fddx_fine
:
826 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
827 inst
->saturate
= instr
->dest
.saturate
;
829 case nir_op_fddx_coarse
:
830 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
831 inst
->saturate
= instr
->dest
.saturate
;
834 if (fs_key
->high_quality_derivatives
) {
835 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
837 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
839 inst
->saturate
= instr
->dest
.saturate
;
841 case nir_op_fddy_fine
:
842 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
843 inst
->saturate
= instr
->dest
.saturate
;
845 case nir_op_fddy_coarse
:
846 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
847 inst
->saturate
= instr
->dest
.saturate
;
852 inst
= bld
.ADD(result
, op
[0], op
[1]);
853 inst
->saturate
= instr
->dest
.saturate
;
857 inst
= bld
.MUL(result
, op
[0], op
[1]);
858 inst
->saturate
= instr
->dest
.saturate
;
862 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
863 bld
.MUL(result
, op
[0], op
[1]);
866 case nir_op_imul_high
:
867 case nir_op_umul_high
:
868 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
869 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
874 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
875 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
878 case nir_op_uadd_carry
:
879 unreachable("Should have been lowered by carry_to_arith().");
881 case nir_op_usub_borrow
:
882 unreachable("Should have been lowered by borrow_to_arith().");
886 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
887 * appears that our hardware just does the right thing for signed
890 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
891 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
895 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
896 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
898 /* Math instructions don't support conditional mod */
899 inst
= bld
.MOV(bld
.null_reg_d(), result
);
900 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
902 /* Now, we need to determine if signs of the sources are different.
903 * When we XOR the sources, the top bit is 0 if they are the same and 1
904 * if they are different. We can then use a conditional modifier to
905 * turn that into a predicate. This leads us to an XOR.l instruction.
907 * Technically, according to the PRM, you're not allowed to use .l on a
908 * XOR instruction. However, emperical experiments and Curro's reading
909 * of the simulator source both indicate that it's safe.
911 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
912 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
913 inst
->predicate
= BRW_PREDICATE_NORMAL
;
914 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
916 /* If the result of the initial remainder operation is non-zero and the
917 * two sources have different signs, add in a copy of op[1] to get the
918 * final integer modulus value.
920 inst
= bld
.ADD(result
, result
, op
[1]);
921 inst
->predicate
= BRW_PREDICATE_NORMAL
;
929 fs_reg dest
= result
;
930 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
931 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
933 brw_conditional_mod cond
;
936 cond
= BRW_CONDITIONAL_L
;
939 cond
= BRW_CONDITIONAL_GE
;
942 cond
= BRW_CONDITIONAL_Z
;
945 cond
= BRW_CONDITIONAL_NZ
;
948 unreachable("bad opcode");
950 bld
.CMP(dest
, op
[0], op
[1], cond
);
951 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
952 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
963 fs_reg dest
= result
;
964 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
965 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
968 brw_conditional_mod cond
;
972 cond
= BRW_CONDITIONAL_L
;
976 cond
= BRW_CONDITIONAL_GE
;
979 cond
= BRW_CONDITIONAL_Z
;
982 cond
= BRW_CONDITIONAL_NZ
;
985 unreachable("bad opcode");
987 bld
.CMP(dest
, op
[0], op
[1], cond
);
988 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
989 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
995 if (devinfo
->gen
>= 8) {
996 op
[0] = resolve_source_modifiers(op
[0]);
998 bld
.NOT(result
, op
[0]);
1001 if (devinfo
->gen
>= 8) {
1002 op
[0] = resolve_source_modifiers(op
[0]);
1003 op
[1] = resolve_source_modifiers(op
[1]);
1005 bld
.XOR(result
, op
[0], op
[1]);
1008 if (devinfo
->gen
>= 8) {
1009 op
[0] = resolve_source_modifiers(op
[0]);
1010 op
[1] = resolve_source_modifiers(op
[1]);
1012 bld
.OR(result
, op
[0], op
[1]);
1015 if (devinfo
->gen
>= 8) {
1016 op
[0] = resolve_source_modifiers(op
[0]);
1017 op
[1] = resolve_source_modifiers(op
[1]);
1019 bld
.AND(result
, op
[0], op
[1]);
1025 case nir_op_ball_fequal2
:
1026 case nir_op_ball_iequal2
:
1027 case nir_op_ball_fequal3
:
1028 case nir_op_ball_iequal3
:
1029 case nir_op_ball_fequal4
:
1030 case nir_op_ball_iequal4
:
1031 case nir_op_bany_fnequal2
:
1032 case nir_op_bany_inequal2
:
1033 case nir_op_bany_fnequal3
:
1034 case nir_op_bany_inequal3
:
1035 case nir_op_bany_fnequal4
:
1036 case nir_op_bany_inequal4
:
1037 unreachable("Lowered by nir_lower_alu_reductions");
1039 case nir_op_fnoise1_1
:
1040 case nir_op_fnoise1_2
:
1041 case nir_op_fnoise1_3
:
1042 case nir_op_fnoise1_4
:
1043 case nir_op_fnoise2_1
:
1044 case nir_op_fnoise2_2
:
1045 case nir_op_fnoise2_3
:
1046 case nir_op_fnoise2_4
:
1047 case nir_op_fnoise3_1
:
1048 case nir_op_fnoise3_2
:
1049 case nir_op_fnoise3_3
:
1050 case nir_op_fnoise3_4
:
1051 case nir_op_fnoise4_1
:
1052 case nir_op_fnoise4_2
:
1053 case nir_op_fnoise4_3
:
1054 case nir_op_fnoise4_4
:
1055 unreachable("not reached: should be handled by lower_noise");
1058 unreachable("not reached: should be handled by ldexp_to_arith()");
1061 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1062 inst
->saturate
= instr
->dest
.saturate
;
1066 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1067 inst
->saturate
= instr
->dest
.saturate
;
1072 bld
.MOV(result
, negate(op
[0]));
1077 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1078 /* two-argument instructions can't take 64-bit immediates */
1082 if (instr
->op
== nir_op_f2b
) {
1083 zero
= vgrf(glsl_type::double_type
);
1084 tmp
= vgrf(glsl_type::double_type
);
1086 zero
= vgrf(glsl_type::int64_t_type
);
1087 tmp
= vgrf(glsl_type::int64_t_type
);
1090 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1091 /* A SIMD16 execution needs to be split in two instructions, so use
1092 * a vgrf instead of the flag register as dst so instruction splitting
1095 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1096 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1098 if (instr
->op
== nir_op_f2b
) {
1099 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1101 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1107 inst
= bld
.RNDZ(result
, op
[0]);
1108 inst
->saturate
= instr
->dest
.saturate
;
1111 case nir_op_fceil
: {
1112 op
[0].negate
= !op
[0].negate
;
1113 fs_reg temp
= vgrf(glsl_type::float_type
);
1114 bld
.RNDD(temp
, op
[0]);
1116 inst
= bld
.MOV(result
, temp
);
1117 inst
->saturate
= instr
->dest
.saturate
;
1121 inst
= bld
.RNDD(result
, op
[0]);
1122 inst
->saturate
= instr
->dest
.saturate
;
1125 inst
= bld
.FRC(result
, op
[0]);
1126 inst
->saturate
= instr
->dest
.saturate
;
1128 case nir_op_fround_even
:
1129 inst
= bld
.RNDE(result
, op
[0]);
1130 inst
->saturate
= instr
->dest
.saturate
;
1133 case nir_op_fquantize2f16
: {
1134 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1135 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1136 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1138 /* The destination stride must be at least as big as the source stride. */
1139 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1142 /* Check for denormal */
1143 fs_reg abs_src0
= op
[0];
1144 abs_src0
.abs
= true;
1145 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1147 /* Get the appropriately signed zero */
1148 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1149 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1150 brw_imm_ud(0x80000000));
1151 /* Do the actual F32 -> F16 -> F32 conversion */
1152 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1153 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1154 /* Select that or zero based on normal status */
1155 inst
= bld
.SEL(result
, zero
, tmp32
);
1156 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1157 inst
->saturate
= instr
->dest
.saturate
;
1164 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1165 inst
->saturate
= instr
->dest
.saturate
;
1171 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1172 inst
->saturate
= instr
->dest
.saturate
;
1175 case nir_op_pack_snorm_2x16
:
1176 case nir_op_pack_snorm_4x8
:
1177 case nir_op_pack_unorm_2x16
:
1178 case nir_op_pack_unorm_4x8
:
1179 case nir_op_unpack_snorm_2x16
:
1180 case nir_op_unpack_snorm_4x8
:
1181 case nir_op_unpack_unorm_2x16
:
1182 case nir_op_unpack_unorm_4x8
:
1183 case nir_op_unpack_half_2x16
:
1184 case nir_op_pack_half_2x16
:
1185 unreachable("not reached: should be handled by lower_packing_builtins");
1187 case nir_op_unpack_half_2x16_split_x
:
1188 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1189 inst
->saturate
= instr
->dest
.saturate
;
1191 case nir_op_unpack_half_2x16_split_y
:
1192 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1193 inst
->saturate
= instr
->dest
.saturate
;
1196 case nir_op_pack_64_2x32_split
:
1197 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1200 case nir_op_unpack_64_2x32_split_x
:
1201 case nir_op_unpack_64_2x32_split_y
: {
1202 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1203 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1205 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1210 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1211 inst
->saturate
= instr
->dest
.saturate
;
1214 case nir_op_bitfield_reverse
:
1215 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1216 bld
.BFREV(result
, op
[0]);
1219 case nir_op_bit_count
:
1220 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1221 bld
.CBIT(result
, op
[0]);
1224 case nir_op_ufind_msb
: {
1225 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1226 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1230 case nir_op_ifind_msb
: {
1231 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1233 if (devinfo
->gen
< 7) {
1234 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1236 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1238 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1239 * count from the LSB side. If FBH didn't return an error
1240 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1241 * count into an LSB count.
1243 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1245 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1246 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1247 inst
->src
[0].negate
= true;
1252 case nir_op_find_lsb
:
1253 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1255 if (devinfo
->gen
< 7) {
1256 fs_reg temp
= vgrf(glsl_type::int_type
);
1258 /* (x & -x) generates a value that consists of only the LSB of x.
1259 * For all powers of 2, findMSB(y) == findLSB(y).
1261 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1262 fs_reg negated_src
= src
;
1264 /* One must be negated, and the other must be non-negated. It
1265 * doesn't matter which is which.
1267 negated_src
.negate
= true;
1270 bld
.AND(temp
, src
, negated_src
);
1271 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1273 bld
.FBL(result
, op
[0]);
1277 case nir_op_ubitfield_extract
:
1278 case nir_op_ibitfield_extract
:
1279 unreachable("should have been lowered");
1282 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1283 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1286 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1287 bld
.BFI1(result
, op
[0], op
[1]);
1290 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1291 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1294 case nir_op_bitfield_insert
:
1295 unreachable("not reached: should have been lowered");
1298 bld
.SHL(result
, op
[0], op
[1]);
1301 bld
.ASR(result
, op
[0], op
[1]);
1304 bld
.SHR(result
, op
[0], op
[1]);
1307 case nir_op_pack_half_2x16_split
:
1308 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1312 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1313 inst
->saturate
= instr
->dest
.saturate
;
1317 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1318 inst
->saturate
= instr
->dest
.saturate
;
1322 if (optimize_frontfacing_ternary(instr
, result
))
1325 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1326 inst
= bld
.SEL(result
, op
[1], op
[2]);
1327 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1330 case nir_op_extract_u8
:
1331 case nir_op_extract_i8
: {
1332 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1333 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1334 assert(byte
!= NULL
);
1335 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1339 case nir_op_extract_u16
:
1340 case nir_op_extract_i16
: {
1341 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1342 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1343 assert(word
!= NULL
);
1344 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1349 unreachable("unhandled instruction");
1352 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1353 * to sign extend the low bit to 0/~0
1355 if (devinfo
->gen
<= 5 &&
1356 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1357 fs_reg masked
= vgrf(glsl_type::int_type
);
1358 bld
.AND(masked
, result
, brw_imm_d(1));
1359 masked
.negate
= true;
1360 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1365 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1366 nir_load_const_instr
*instr
)
1368 const brw_reg_type reg_type
=
1369 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1370 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1372 switch (instr
->def
.bit_size
) {
1374 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1375 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1379 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1380 bld
.MOV(offset(reg
, bld
, i
),
1381 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1385 unreachable("Invalid bit size");
1388 nir_ssa_values
[instr
->def
.index
] = reg
;
1392 fs_visitor::get_nir_src(const nir_src
&src
)
1396 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1397 const brw_reg_type reg_type
= src
.ssa
->bit_size
== 32 ?
1398 BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1399 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1401 reg
= nir_ssa_values
[src
.ssa
->index
];
1404 /* We don't handle indirects on locals */
1405 assert(src
.reg
.indirect
== NULL
);
1406 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1407 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1410 /* to avoid floating-point denorm flushing problems, set the type by
1411 * default to D - instructions that need floating point semantics will set
1412 * this to F if they need to
1414 return retype(reg
, BRW_REGISTER_TYPE_D
);
1418 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1421 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1423 nir_const_value
*val
= nir_src_as_const_value(src
);
1424 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1428 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1431 const brw_reg_type reg_type
=
1432 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1433 nir_ssa_values
[dest
.ssa
.index
] =
1434 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1435 return nir_ssa_values
[dest
.ssa
.index
];
1437 /* We don't handle indirects on locals */
1438 assert(dest
.reg
.indirect
== NULL
);
1439 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1440 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1445 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1447 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1448 BRW_REGISTER_TYPE_UD
);
1450 unsigned indirect_max
= 0;
1452 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1453 tail
= tail
->child
) {
1454 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1455 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1456 const unsigned size
= glsl_get_length(tail
->type
);
1457 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1458 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1459 image
= offset(image
, bld
, base
* element_size
);
1461 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1462 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1464 /* Accessing an invalid surface index with the dataport can result
1465 * in a hang. According to the spec "if the index used to
1466 * select an individual element is negative or greater than or
1467 * equal to the size of the array, the results of the operation
1468 * are undefined but may not lead to termination" -- which is one
1469 * of the possible outcomes of the hang. Clamp the index to
1470 * prevent access outside of the array bounds.
1472 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1473 BRW_REGISTER_TYPE_UD
),
1474 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1476 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1478 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1479 if (indirect
.file
== BAD_FILE
) {
1482 bld
.ADD(indirect
, indirect
, tmp
);
1487 if (indirect
.file
== BAD_FILE
) {
1490 /* Emit a pile of MOVs to load the uniform into a temporary. The
1491 * dead-code elimination pass will get rid of what we don't use.
1493 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1494 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1495 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1496 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1497 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1504 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1507 for (unsigned i
= 0; i
< 4; i
++) {
1508 if (!((wr_mask
>> i
) & 1))
1511 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1512 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1513 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1514 if (new_inst
->src
[j
].file
== VGRF
)
1515 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1522 * Get the matching channel register datatype for an image intrinsic of the
1523 * specified GLSL image type.
1526 get_image_base_type(const glsl_type
*type
)
1528 switch ((glsl_base_type
)type
->sampled_type
) {
1529 case GLSL_TYPE_UINT
:
1530 return BRW_REGISTER_TYPE_UD
;
1532 return BRW_REGISTER_TYPE_D
;
1533 case GLSL_TYPE_FLOAT
:
1534 return BRW_REGISTER_TYPE_F
;
1536 unreachable("Not reached.");
1541 * Get the appropriate atomic op for an image atomic intrinsic.
1544 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1547 case nir_intrinsic_image_atomic_add
:
1549 case nir_intrinsic_image_atomic_min
:
1550 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1551 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1552 case nir_intrinsic_image_atomic_max
:
1553 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1554 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1555 case nir_intrinsic_image_atomic_and
:
1557 case nir_intrinsic_image_atomic_or
:
1559 case nir_intrinsic_image_atomic_xor
:
1561 case nir_intrinsic_image_atomic_exchange
:
1563 case nir_intrinsic_image_atomic_comp_swap
:
1564 return BRW_AOP_CMPWR
;
1566 unreachable("Not reachable.");
1571 emit_pixel_interpolater_send(const fs_builder
&bld
,
1576 glsl_interp_mode interpolation
)
1578 struct brw_wm_prog_data
*wm_prog_data
=
1579 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1584 if (src
.file
== BAD_FILE
) {
1586 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1590 mlen
= 2 * bld
.dispatch_width() / 8;
1593 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1595 /* 2 floats per slot returned */
1596 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1597 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1599 wm_prog_data
->pulls_bary
= true;
1605 * Computes 1 << x, given a D/UD register containing some value x.
1608 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1610 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1612 fs_reg result
= bld
.vgrf(x
.type
, 1);
1613 fs_reg one
= bld
.vgrf(x
.type
, 1);
1615 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1616 bld
.SHL(result
, one
, x
);
1621 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1623 assert(stage
== MESA_SHADER_GEOMETRY
);
1625 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1627 if (gs_compile
->control_data_header_size_bits
== 0)
1630 /* We can only do EndPrimitive() functionality when the control data
1631 * consists of cut bits. Fortunately, the only time it isn't is when the
1632 * output type is points, in which case EndPrimitive() is a no-op.
1634 if (gs_prog_data
->control_data_format
!=
1635 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1639 /* Cut bits use one bit per vertex. */
1640 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1642 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1643 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1645 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1646 * vertex n, 0 otherwise. So all we need to do here is mark bit
1647 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1648 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1649 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1651 * Note that if EndPrimitive() is called before emitting any vertices, this
1652 * will cause us to set bit 31 of the control_data_bits register to 1.
1653 * That's fine because:
1655 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1656 * output, so the hardware will ignore cut bit 31.
1658 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1659 * last vertex, so setting cut bit 31 has no effect (since the primitive
1660 * is automatically ended when the GS terminates).
1662 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1663 * control_data_bits register to 0 when the first vertex is emitted.
1666 const fs_builder abld
= bld
.annotate("end primitive");
1668 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1669 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1670 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1671 fs_reg mask
= intexp2(abld
, prev_count
);
1672 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1673 * attention to the lower 5 bits of its second source argument, so on this
1674 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1675 * ((vertex_count - 1) % 32).
1677 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1681 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1683 assert(stage
== MESA_SHADER_GEOMETRY
);
1684 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1686 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1688 const fs_builder abld
= bld
.annotate("emit control data bits");
1689 const fs_builder fwa_bld
= bld
.exec_all();
1691 /* We use a single UD register to accumulate control data bits (32 bits
1692 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1695 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1696 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1697 * use the Channel Mask phase to enable/disable which DWord within that
1698 * group to write. (Remember, different SIMD8 channels may have emitted
1699 * different numbers of vertices, so we may need per-slot offsets.)
1701 * Channel masking presents an annoying problem: we may have to replicate
1702 * the data up to 4 times:
1704 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1706 * To avoid penalizing shaders that emit a small number of vertices, we
1707 * can avoid these sometimes: if the size of the control data header is
1708 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1709 * land in the same 128-bit group, so we can skip per-slot offsets.
1711 * Similarly, if the control data header is <= 32 bits, there is only one
1712 * DWord, so we can skip channel masks.
1714 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1716 fs_reg channel_mask
, per_slot_offset
;
1718 if (gs_compile
->control_data_header_size_bits
> 32) {
1719 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1720 channel_mask
= vgrf(glsl_type::uint_type
);
1723 if (gs_compile
->control_data_header_size_bits
> 128) {
1724 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1725 per_slot_offset
= vgrf(glsl_type::uint_type
);
1728 /* Figure out which DWord we're trying to write to using the formula:
1730 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1732 * Since bits_per_vertex is a power of two, and is known at compile
1733 * time, this can be optimized to:
1735 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1737 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1738 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1739 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1740 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1741 unsigned log2_bits_per_vertex
=
1742 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1743 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1745 if (per_slot_offset
.file
!= BAD_FILE
) {
1746 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1747 * the appropriate OWord within the control data header.
1749 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1752 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1753 * write to the appropriate DWORD within the OWORD.
1755 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1756 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1757 channel_mask
= intexp2(fwa_bld
, channel
);
1758 /* Then the channel masks need to be in bits 23:16. */
1759 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1762 /* Store the control data bits in the message payload and send it. */
1764 if (channel_mask
.file
!= BAD_FILE
)
1765 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1766 if (per_slot_offset
.file
!= BAD_FILE
)
1769 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1770 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1772 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1773 if (per_slot_offset
.file
!= BAD_FILE
)
1774 sources
[i
++] = per_slot_offset
;
1775 if (channel_mask
.file
!= BAD_FILE
)
1776 sources
[i
++] = channel_mask
;
1778 sources
[i
++] = this->control_data_bits
;
1781 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1782 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1784 /* We need to increment Global Offset by 256-bits to make room for
1785 * Broadwell's extra "Vertex Count" payload at the beginning of the
1786 * URB entry. Since this is an OWord message, Global Offset is counted
1787 * in 128-bit units, so we must set it to 2.
1789 if (gs_prog_data
->static_vertex_count
== -1)
1794 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1797 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1799 /* Note: we are calling this *before* increasing vertex_count, so
1800 * this->vertex_count == vertex_count - 1 in the formula above.
1803 /* Stream mode uses 2 bits per vertex */
1804 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1806 /* Must be a valid stream */
1807 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1809 /* Control data bits are initialized to 0 so we don't have to set any
1810 * bits when sending vertices to stream 0.
1815 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1817 /* reg::sid = stream_id */
1818 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1819 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1821 /* reg:shift_count = 2 * (vertex_count - 1) */
1822 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1823 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1825 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1826 * attention to the lower 5 bits of its second source argument, so on this
1827 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1828 * stream_id << ((2 * (vertex_count - 1)) % 32).
1830 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1831 abld
.SHL(mask
, sid
, shift_count
);
1832 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1836 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1839 assert(stage
== MESA_SHADER_GEOMETRY
);
1841 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1843 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1844 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1846 /* Haswell and later hardware ignores the "Render Stream Select" bits
1847 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1848 * and instead sends all primitives down the pipeline for rasterization.
1849 * If the SOL stage is enabled, "Render Stream Select" is honored and
1850 * primitives bound to non-zero streams are discarded after stream output.
1852 * Since the only purpose of primives sent to non-zero streams is to
1853 * be recorded by transform feedback, we can simply discard all geometry
1854 * bound to these streams when transform feedback is disabled.
1856 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1859 /* If we're outputting 32 control data bits or less, then we can wait
1860 * until the shader is over to output them all. Otherwise we need to
1861 * output them as we go. Now is the time to do it, since we're about to
1862 * output the vertex_count'th vertex, so it's guaranteed that the
1863 * control data bits associated with the (vertex_count - 1)th vertex are
1866 if (gs_compile
->control_data_header_size_bits
> 32) {
1867 const fs_builder abld
=
1868 bld
.annotate("emit vertex: emit control data bits");
1870 /* Only emit control data bits if we've finished accumulating a batch
1871 * of 32 bits. This is the case when:
1873 * (vertex_count * bits_per_vertex) % 32 == 0
1875 * (in other words, when the last 5 bits of vertex_count *
1876 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1877 * integer n (which is always the case, since bits_per_vertex is
1878 * always 1 or 2), this is equivalent to requiring that the last 5-n
1879 * bits of vertex_count are 0:
1881 * vertex_count & (2^(5-n) - 1) == 0
1883 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1886 * vertex_count & (32 / bits_per_vertex - 1) == 0
1888 * TODO: If vertex_count is an immediate, we could do some of this math
1889 * at compile time...
1892 abld
.AND(bld
.null_reg_d(), vertex_count
,
1893 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1894 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1896 abld
.IF(BRW_PREDICATE_NORMAL
);
1897 /* If vertex_count is 0, then no control data bits have been
1898 * accumulated yet, so we can skip emitting them.
1900 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1901 BRW_CONDITIONAL_NEQ
);
1902 abld
.IF(BRW_PREDICATE_NORMAL
);
1903 emit_gs_control_data_bits(vertex_count
);
1904 abld
.emit(BRW_OPCODE_ENDIF
);
1906 /* Reset control_data_bits to 0 so we can start accumulating a new
1909 * Note: in the case where vertex_count == 0, this neutralizes the
1910 * effect of any call to EndPrimitive() that the shader may have
1911 * made before outputting its first vertex.
1913 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1914 inst
->force_writemask_all
= true;
1915 abld
.emit(BRW_OPCODE_ENDIF
);
1918 emit_urb_writes(vertex_count
);
1920 /* In stream mode we have to set control data bits for all vertices
1921 * unless we have disabled control data bits completely (which we do
1922 * do for GL_POINTS outputs that don't use streams).
1924 if (gs_compile
->control_data_header_size_bits
> 0 &&
1925 gs_prog_data
->control_data_format
==
1926 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1927 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1932 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1933 const nir_src
&vertex_src
,
1934 unsigned base_offset
,
1935 const nir_src
&offset_src
,
1936 unsigned num_components
,
1937 unsigned first_component
)
1939 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1941 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1942 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1943 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1945 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1946 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1947 * gl_PointSize is available as a GS input, however, so it must be that.
1949 const bool is_point_size
= (base_offset
== 0);
1951 /* TODO: figure out push input layout for invocations == 1 */
1952 if (gs_prog_data
->invocations
== 1 &&
1953 offset_const
!= NULL
&& vertex_const
!= NULL
&&
1954 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1955 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1956 vertex_const
->u32
[0] * push_reg_count
;
1957 /* This input was pushed into registers. */
1958 if (is_point_size
) {
1959 /* gl_PointSize comes in .w */
1960 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1962 for (unsigned i
= 0; i
< num_components
; i
++) {
1963 bld
.MOV(offset(dst
, bld
, i
),
1964 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
1970 /* Resort to the pull model. Ensure the VUE handles are provided. */
1971 gs_prog_data
->base
.include_vue_handles
= true;
1973 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1974 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1976 if (gs_prog_data
->invocations
== 1) {
1978 /* The vertex index is constant; just select the proper URB handle. */
1980 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
1981 BRW_REGISTER_TYPE_UD
);
1983 /* The vertex index is non-constant. We need to use indirect
1984 * addressing to fetch the proper URB handle.
1986 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1987 * indicating that channel <n> should read the handle from
1988 * DWord <n>. We convert that to bytes by multiplying by 4.
1990 * Next, we convert the vertex index to bytes by multiplying
1991 * by 32 (shifting by 5), and add the two together. This is
1992 * the final indirect byte offset.
1994 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1995 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1996 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1997 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1999 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2000 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2001 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2002 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2003 /* Convert vertex_index to bytes (multiply by 32) */
2004 bld
.SHL(vertex_offset_bytes
,
2005 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2007 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2009 /* Use first_icp_handle as the base offset. There is one register
2010 * of URB handles per vertex, so inform the register allocator that
2011 * we might read up to nir->info.gs.vertices_in registers.
2013 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2014 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2015 fs_reg(icp_offset_bytes
),
2016 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2019 assert(gs_prog_data
->invocations
> 1);
2022 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2024 retype(brw_vec1_grf(first_icp_handle
+
2025 vertex_const
->i32
[0] / 8,
2026 vertex_const
->i32
[0] % 8),
2027 BRW_REGISTER_TYPE_UD
));
2029 /* The vertex index is non-constant. We need to use indirect
2030 * addressing to fetch the proper URB handle.
2033 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2035 /* Convert vertex_index to bytes (multiply by 4) */
2036 bld
.SHL(icp_offset_bytes
,
2037 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2040 /* Use first_icp_handle as the base offset. There is one DWord
2041 * of URB handles per vertex, so inform the register allocator that
2042 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2044 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2045 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2046 fs_reg(icp_offset_bytes
),
2047 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2054 fs_reg tmp_dst
= dst
;
2055 fs_reg indirect_offset
= get_nir_src(offset_src
);
2056 unsigned num_iterations
= 1;
2057 unsigned orig_num_components
= num_components
;
2059 if (type_sz(dst
.type
) == 8) {
2060 if (num_components
> 2) {
2064 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2066 first_component
= first_component
/ 2;
2069 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2071 /* Constant indexing - use global offset. */
2072 if (first_component
!= 0) {
2073 unsigned read_components
= num_components
+ first_component
;
2074 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2075 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2076 inst
->size_written
= read_components
*
2077 tmp
.component_size(inst
->exec_size
);
2078 for (unsigned i
= 0; i
< num_components
; i
++) {
2079 bld
.MOV(offset(tmp_dst
, bld
, i
),
2080 offset(tmp
, bld
, i
+ first_component
));
2083 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2085 inst
->size_written
= num_components
*
2086 tmp_dst
.component_size(inst
->exec_size
);
2088 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2091 /* Indirect indexing - use per-slot offsets as well. */
2092 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2093 unsigned read_components
= num_components
+ first_component
;
2094 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2095 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2096 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2097 if (first_component
!= 0) {
2098 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2100 inst
->size_written
= read_components
*
2101 tmp
.component_size(inst
->exec_size
);
2102 for (unsigned i
= 0; i
< num_components
; i
++) {
2103 bld
.MOV(offset(tmp_dst
, bld
, i
),
2104 offset(tmp
, bld
, i
+ first_component
));
2107 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2109 inst
->size_written
= num_components
*
2110 tmp_dst
.component_size(inst
->exec_size
);
2112 inst
->offset
= base_offset
;
2116 if (type_sz(dst
.type
) == 8) {
2117 shuffle_32bit_load_result_to_64bit_data(
2118 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2120 for (unsigned c
= 0; c
< num_components
; c
++)
2121 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2124 if (num_iterations
> 1) {
2125 num_components
= orig_num_components
- 2;
2129 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2130 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2131 indirect_offset
= new_indirect
;
2136 if (is_point_size
) {
2137 /* Read the whole VUE header (because of alignment) and read .w. */
2138 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2140 inst
->size_written
= 4 * REG_SIZE
;
2141 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2146 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2148 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2149 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2152 /* The only constant offset we should find is 0. brw_nir.c's
2153 * add_const_offset_to_base() will fold other constant offsets
2154 * into instr->const_index[0].
2156 assert(const_value
->u32
[0] == 0);
2160 return get_nir_src(*offset_src
);
2164 do_untyped_vector_read(const fs_builder
&bld
,
2166 const fs_reg surf_index
,
2167 const fs_reg offset_reg
,
2168 unsigned num_components
)
2170 if (type_sz(dest
.type
) == 4) {
2171 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2174 BRW_PREDICATE_NONE
);
2175 read_result
.type
= dest
.type
;
2176 for (unsigned i
= 0; i
< num_components
; i
++)
2177 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2178 } else if (type_sz(dest
.type
) == 8) {
2179 /* Reading a dvec, so we need to:
2181 * 1. Multiply num_components by 2, to account for the fact that we
2182 * need to read 64-bit components.
2183 * 2. Shuffle the result of the load to form valid 64-bit elements
2184 * 3. Emit a second load (for components z/w) if needed.
2186 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2187 bld
.MOV(read_offset
, offset_reg
);
2189 int iters
= num_components
<= 2 ? 1 : 2;
2191 /* Load the dvec, the first iteration loads components x/y, the second
2192 * iteration, if needed, loads components z/w
2194 for (int it
= 0; it
< iters
; it
++) {
2195 /* Compute number of components to read in this iteration */
2196 int iter_components
= MIN2(2, num_components
);
2197 num_components
-= iter_components
;
2199 /* Read. Since this message reads 32-bit components, we need to
2200 * read twice as many components.
2202 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2204 iter_components
* 2,
2205 BRW_PREDICATE_NONE
);
2207 /* Shuffle the 32-bit load result into valid 64-bit data */
2208 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2209 shuffle_32bit_load_result_to_64bit_data(
2210 bld
, packed_result
, read_result
, iter_components
);
2212 /* Move each component to its destination */
2213 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2214 for (int c
= 0; c
< iter_components
; c
++) {
2215 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2216 offset(packed_result
, bld
, c
));
2219 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2222 unreachable("Unsupported type");
2227 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2228 nir_intrinsic_instr
*instr
)
2230 assert(stage
== MESA_SHADER_VERTEX
);
2233 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2234 dest
= get_nir_dest(instr
->dest
);
2236 switch (instr
->intrinsic
) {
2237 case nir_intrinsic_load_vertex_id
:
2238 unreachable("should be lowered by lower_vertex_id()");
2240 case nir_intrinsic_load_vertex_id_zero_base
:
2241 case nir_intrinsic_load_base_vertex
:
2242 case nir_intrinsic_load_instance_id
:
2243 case nir_intrinsic_load_base_instance
:
2244 case nir_intrinsic_load_draw_id
: {
2245 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2246 fs_reg val
= nir_system_values
[sv
];
2247 assert(val
.file
!= BAD_FILE
);
2248 dest
.type
= val
.type
;
2253 case nir_intrinsic_load_input
: {
2254 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2255 unsigned first_component
= nir_intrinsic_component(instr
);
2256 unsigned num_components
= instr
->num_components
;
2257 enum brw_reg_type type
= dest
.type
;
2259 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2260 assert(const_offset
&& "Indirect input loads not allowed");
2261 src
= offset(src
, bld
, const_offset
->u32
[0]);
2263 for (unsigned j
= 0; j
< num_components
; j
++) {
2264 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2267 if (type
== BRW_REGISTER_TYPE_DF
) {
2268 /* Once the double vector is read, set again its original register
2269 * type to continue with normal execution.
2271 src
= retype(src
, type
);
2272 dest
= retype(dest
, type
);
2275 if (type_sz(src
.type
) == 8) {
2276 shuffle_32bit_load_result_to_64bit_data(bld
,
2278 retype(dest
, BRW_REGISTER_TYPE_F
),
2279 instr
->num_components
);
2285 nir_emit_intrinsic(bld
, instr
);
2291 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2292 nir_intrinsic_instr
*instr
)
2294 assert(stage
== MESA_SHADER_TESS_CTRL
);
2295 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2296 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2299 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2300 dst
= get_nir_dest(instr
->dest
);
2302 switch (instr
->intrinsic
) {
2303 case nir_intrinsic_load_primitive_id
:
2304 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2306 case nir_intrinsic_load_invocation_id
:
2307 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2309 case nir_intrinsic_load_patch_vertices_in
:
2310 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2311 brw_imm_d(tcs_key
->input_vertices
));
2314 case nir_intrinsic_barrier
: {
2315 if (tcs_prog_data
->instances
== 1)
2318 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2319 fs_reg m0_2
= component(m0
, 2);
2321 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2323 /* Zero the message header */
2324 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2326 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2327 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2328 brw_imm_ud(INTEL_MASK(16, 13)));
2330 /* Shift it up to bits 27:24. */
2331 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2333 /* Set the Barrier Count and the enable bit */
2334 chanbld
.OR(m0_2
, m0_2
,
2335 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2337 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2341 case nir_intrinsic_load_input
:
2342 unreachable("nir_lower_io should never give us these.");
2345 case nir_intrinsic_load_per_vertex_input
: {
2346 fs_reg indirect_offset
= get_indirect_offset(instr
);
2347 unsigned imm_offset
= instr
->const_index
[0];
2349 const nir_src
&vertex_src
= instr
->src
[0];
2350 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2357 /* Emit a MOV to resolve <0,1,0> regioning. */
2358 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2360 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2361 vertex_const
->i32
[0] & 7),
2362 BRW_REGISTER_TYPE_UD
));
2363 } else if (tcs_prog_data
->instances
== 1 &&
2364 vertex_src
.is_ssa
&&
2365 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2366 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2367 /* For the common case of only 1 instance, an array index of
2368 * gl_InvocationID means reading g1. Skip all the indirect work.
2370 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2372 /* The vertex index is non-constant. We need to use indirect
2373 * addressing to fetch the proper URB handle.
2375 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2377 /* Each ICP handle is a single DWord (4 bytes) */
2378 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2379 bld
.SHL(vertex_offset_bytes
,
2380 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2383 /* Start at g1. We might read up to 4 registers. */
2384 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2385 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2386 brw_imm_ud(4 * REG_SIZE
));
2389 /* We can only read two double components with each URB read, so
2390 * we send two read messages in that case, each one loading up to
2391 * two double components.
2393 unsigned num_iterations
= 1;
2394 unsigned num_components
= instr
->num_components
;
2395 unsigned first_component
= nir_intrinsic_component(instr
);
2396 fs_reg orig_dst
= dst
;
2397 if (type_sz(dst
.type
) == 8) {
2398 first_component
= first_component
/ 2;
2399 if (instr
->num_components
> 2) {
2404 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2408 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2409 if (indirect_offset
.file
== BAD_FILE
) {
2410 /* Constant indexing - use global offset. */
2411 if (first_component
!= 0) {
2412 unsigned read_components
= num_components
+ first_component
;
2413 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2414 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2415 for (unsigned i
= 0; i
< num_components
; i
++) {
2416 bld
.MOV(offset(dst
, bld
, i
),
2417 offset(tmp
, bld
, i
+ first_component
));
2420 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2422 inst
->offset
= imm_offset
;
2425 /* Indirect indexing - use per-slot offsets as well. */
2426 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2427 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2428 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2429 if (first_component
!= 0) {
2430 unsigned read_components
= num_components
+ first_component
;
2431 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2432 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2434 for (unsigned i
= 0; i
< num_components
; i
++) {
2435 bld
.MOV(offset(dst
, bld
, i
),
2436 offset(tmp
, bld
, i
+ first_component
));
2439 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2442 inst
->offset
= imm_offset
;
2445 inst
->size_written
= (num_components
+ first_component
) *
2446 inst
->dst
.component_size(inst
->exec_size
);
2448 /* If we are reading 64-bit data using 32-bit read messages we need
2449 * build proper 64-bit data elements by shuffling the low and high
2450 * 32-bit components around like we do for other things like UBOs
2453 if (type_sz(dst
.type
) == 8) {
2454 shuffle_32bit_load_result_to_64bit_data(
2455 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2457 for (unsigned c
= 0; c
< num_components
; c
++) {
2458 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2459 offset(dst
, bld
, c
));
2463 /* Copy the temporary to the destination to deal with writemasking.
2465 * Also attempt to deal with gl_PointSize being in the .w component.
2467 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2468 assert(type_sz(dst
.type
) < 8);
2469 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2470 inst
->size_written
= 4 * REG_SIZE
;
2471 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2474 /* If we are loading double data and we need a second read message
2475 * adjust the write offset
2477 if (num_iterations
> 1) {
2478 num_components
= instr
->num_components
- 2;
2485 case nir_intrinsic_load_output
:
2486 case nir_intrinsic_load_per_vertex_output
: {
2487 fs_reg indirect_offset
= get_indirect_offset(instr
);
2488 unsigned imm_offset
= instr
->const_index
[0];
2489 unsigned first_component
= nir_intrinsic_component(instr
);
2492 if (indirect_offset
.file
== BAD_FILE
) {
2493 /* Replicate the patch handle to all enabled channels */
2494 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2495 bld
.MOV(patch_handle
,
2496 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2499 if (first_component
!= 0) {
2500 unsigned read_components
=
2501 instr
->num_components
+ first_component
;
2502 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2503 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2505 inst
->size_written
= read_components
* REG_SIZE
;
2506 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2507 bld
.MOV(offset(dst
, bld
, i
),
2508 offset(tmp
, bld
, i
+ first_component
));
2511 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2513 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2515 inst
->offset
= imm_offset
;
2519 /* Indirect indexing - use per-slot offsets as well. */
2520 const fs_reg srcs
[] = {
2521 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2524 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2525 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2526 if (first_component
!= 0) {
2527 unsigned read_components
=
2528 instr
->num_components
+ first_component
;
2529 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2530 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2532 inst
->size_written
= read_components
* REG_SIZE
;
2533 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2534 bld
.MOV(offset(dst
, bld
, i
),
2535 offset(tmp
, bld
, i
+ first_component
));
2538 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2540 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2542 inst
->offset
= imm_offset
;
2548 case nir_intrinsic_store_output
:
2549 case nir_intrinsic_store_per_vertex_output
: {
2550 fs_reg value
= get_nir_src(instr
->src
[0]);
2551 bool is_64bit
= (instr
->src
[0].is_ssa
?
2552 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2553 fs_reg indirect_offset
= get_indirect_offset(instr
);
2554 unsigned imm_offset
= instr
->const_index
[0];
2555 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2556 unsigned mask
= instr
->const_index
[1];
2557 unsigned header_regs
= 0;
2559 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2561 if (indirect_offset
.file
!= BAD_FILE
) {
2562 srcs
[header_regs
++] = indirect_offset
;
2568 unsigned num_components
= util_last_bit(mask
);
2571 /* We can only pack two 64-bit components in a single message, so send
2572 * 2 messages if we have more components
2574 unsigned num_iterations
= 1;
2575 unsigned iter_components
= num_components
;
2576 unsigned first_component
= nir_intrinsic_component(instr
);
2578 first_component
= first_component
/ 2;
2579 if (instr
->num_components
> 2) {
2581 iter_components
= 2;
2585 /* 64-bit data needs to me shuffled before we can write it to the URB.
2586 * We will use this temporary to shuffle the components in each
2590 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2592 mask
= mask
<< first_component
;
2594 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2595 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2596 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2597 opcode
= indirect_offset
.file
!= BAD_FILE
?
2598 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2599 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2600 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2601 /* Expand the 64-bit mask to 32-bit channels. We only handle
2602 * two channels in each iteration, so we only care about X/Y.
2604 unsigned mask32
= 0;
2605 if (mask
& WRITEMASK_X
)
2606 mask32
|= WRITEMASK_XY
;
2607 if (mask
& WRITEMASK_Y
)
2608 mask32
|= WRITEMASK_ZW
;
2610 /* If the mask does not include any of the channels X or Y there
2611 * is nothing to do in this iteration. Move on to the next couple
2612 * of 64-bit channels.
2620 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2621 opcode
= indirect_offset
.file
!= BAD_FILE
?
2622 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2623 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2625 opcode
= indirect_offset
.file
!= BAD_FILE
?
2626 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2627 SHADER_OPCODE_URB_WRITE_SIMD8
;
2630 for (unsigned i
= 0; i
< iter_components
; i
++) {
2631 if (!(mask
& (1 << (i
+ first_component
))))
2635 srcs
[header_regs
+ i
+ first_component
] =
2636 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2638 /* We need to shuffle the 64-bit data to match the layout
2639 * expected by our 32-bit URB write messages. We use a temporary
2642 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2643 shuffle_64bit_data_for_32bit_write(bld
,
2644 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2645 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2648 /* Now copy the data to the destination */
2649 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2650 unsigned idx
= 2 * i
;
2651 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2652 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2653 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2654 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2655 offset(dest
, bld
, 1);
2660 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2661 (is_64bit
? 2 * first_component
: first_component
);
2663 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2664 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2666 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2667 inst
->offset
= imm_offset
;
2670 /* If this is a 64-bit attribute, select the next two 64-bit channels
2671 * to be handled in the next iteration.
2682 nir_emit_intrinsic(bld
, instr
);
2688 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2689 nir_intrinsic_instr
*instr
)
2691 assert(stage
== MESA_SHADER_TESS_EVAL
);
2692 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2695 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2696 dest
= get_nir_dest(instr
->dest
);
2698 switch (instr
->intrinsic
) {
2699 case nir_intrinsic_load_primitive_id
:
2700 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2702 case nir_intrinsic_load_tess_coord
:
2703 /* gl_TessCoord is part of the payload in g1-3 */
2704 for (unsigned i
= 0; i
< 3; i
++) {
2705 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2709 case nir_intrinsic_load_input
:
2710 case nir_intrinsic_load_per_vertex_input
: {
2711 fs_reg indirect_offset
= get_indirect_offset(instr
);
2712 unsigned imm_offset
= instr
->const_index
[0];
2713 unsigned first_component
= nir_intrinsic_component(instr
);
2715 if (type_sz(dest
.type
) == 8) {
2716 first_component
= first_component
/ 2;
2720 if (indirect_offset
.file
== BAD_FILE
) {
2721 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2722 * which is 16 registers (since each holds 2 vec4 slots).
2724 const unsigned max_push_slots
= 32;
2725 if (imm_offset
< max_push_slots
) {
2726 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2727 for (int i
= 0; i
< instr
->num_components
; i
++) {
2728 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2729 i
+ first_component
;
2730 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2732 tes_prog_data
->base
.urb_read_length
=
2733 MAX2(tes_prog_data
->base
.urb_read_length
,
2734 DIV_ROUND_UP(imm_offset
+ 1, 2));
2736 /* Replicate the patch handle to all enabled channels */
2737 const fs_reg srcs
[] = {
2738 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2740 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2741 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2743 if (first_component
!= 0) {
2744 unsigned read_components
=
2745 instr
->num_components
+ first_component
;
2746 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2747 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2749 inst
->size_written
= read_components
* REG_SIZE
;
2750 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2751 bld
.MOV(offset(dest
, bld
, i
),
2752 offset(tmp
, bld
, i
+ first_component
));
2755 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2757 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2760 inst
->offset
= imm_offset
;
2763 /* Indirect indexing - use per-slot offsets as well. */
2765 /* We can only read two double components with each URB read, so
2766 * we send two read messages in that case, each one loading up to
2767 * two double components.
2769 unsigned num_iterations
= 1;
2770 unsigned num_components
= instr
->num_components
;
2771 fs_reg orig_dest
= dest
;
2772 if (type_sz(dest
.type
) == 8) {
2773 if (instr
->num_components
> 2) {
2777 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2781 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2782 const fs_reg srcs
[] = {
2783 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2786 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2787 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2789 if (first_component
!= 0) {
2790 unsigned read_components
=
2791 num_components
+ first_component
;
2792 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2793 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2795 for (unsigned i
= 0; i
< num_components
; i
++) {
2796 bld
.MOV(offset(dest
, bld
, i
),
2797 offset(tmp
, bld
, i
+ first_component
));
2800 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2804 inst
->offset
= imm_offset
;
2805 inst
->size_written
= (num_components
+ first_component
) *
2806 inst
->dst
.component_size(inst
->exec_size
);
2808 /* If we are reading 64-bit data using 32-bit read messages we need
2809 * build proper 64-bit data elements by shuffling the low and high
2810 * 32-bit components around like we do for other things like UBOs
2813 if (type_sz(dest
.type
) == 8) {
2814 shuffle_32bit_load_result_to_64bit_data(
2815 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2817 for (unsigned c
= 0; c
< num_components
; c
++) {
2818 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2819 offset(dest
, bld
, c
));
2823 /* If we are loading double data and we need a second read message
2826 if (num_iterations
> 1) {
2827 num_components
= instr
->num_components
- 2;
2835 nir_emit_intrinsic(bld
, instr
);
2841 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2842 nir_intrinsic_instr
*instr
)
2844 assert(stage
== MESA_SHADER_GEOMETRY
);
2845 fs_reg indirect_offset
;
2848 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2849 dest
= get_nir_dest(instr
->dest
);
2851 switch (instr
->intrinsic
) {
2852 case nir_intrinsic_load_primitive_id
:
2853 assert(stage
== MESA_SHADER_GEOMETRY
);
2854 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2855 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2856 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2859 case nir_intrinsic_load_input
:
2860 unreachable("load_input intrinsics are invalid for the GS stage");
2862 case nir_intrinsic_load_per_vertex_input
:
2863 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2864 instr
->src
[1], instr
->num_components
,
2865 nir_intrinsic_component(instr
));
2868 case nir_intrinsic_emit_vertex_with_counter
:
2869 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2872 case nir_intrinsic_end_primitive_with_counter
:
2873 emit_gs_end_primitive(instr
->src
[0]);
2876 case nir_intrinsic_set_vertex_count
:
2877 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2880 case nir_intrinsic_load_invocation_id
: {
2881 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2882 assert(val
.file
!= BAD_FILE
);
2883 dest
.type
= val
.type
;
2889 nir_emit_intrinsic(bld
, instr
);
2895 * Fetch the current render target layer index.
2898 fetch_render_target_array_index(const fs_builder
&bld
)
2900 if (bld
.shader
->devinfo
->gen
>= 6) {
2901 /* The render target array index is provided in the thread payload as
2902 * bits 26:16 of r0.0.
2904 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2905 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2909 /* Pre-SNB we only ever render into the first layer of the framebuffer
2910 * since layered rendering is not implemented.
2912 return brw_imm_ud(0);
2917 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2918 * framebuffer at the current fragment coordinates and sample index.
2921 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2924 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2926 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2927 const brw_wm_prog_key
*wm_key
=
2928 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2929 assert(!wm_key
->coherent_fb_fetch
);
2930 const struct brw_wm_prog_data
*wm_prog_data
=
2931 brw_wm_prog_data(stage_prog_data
);
2933 /* Calculate the surface index relative to the start of the texture binding
2934 * table block, since that's what the texturing messages expect.
2936 const unsigned surface
= target
+
2937 wm_prog_data
->binding_table
.render_target_read_start
-
2938 wm_prog_data
->base
.binding_table
.texture_start
;
2940 brw_mark_surface_used(
2941 bld
.shader
->stage_prog_data
,
2942 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2944 /* Calculate the fragment coordinates. */
2945 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2946 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2947 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2948 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2950 /* Calculate the sample index and MCS payload when multisampling. Luckily
2951 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2952 * shouldn't be necessary to recompile based on whether the framebuffer is
2955 if (wm_key
->multisample_fbo
&&
2956 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2957 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2959 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2960 const fs_reg mcs
= wm_key
->multisample_fbo
?
2961 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2963 /* Use either a normal or a CMS texel fetch message depending on whether
2964 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2965 * message just in case the framebuffer uses 16x multisampling, it should
2966 * be equivalent to the normal CMS fetch for lower multisampling modes.
2968 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2969 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2970 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2972 /* Emit the instruction. */
2973 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
2975 brw_imm_ud(surface
), brw_imm_ud(0),
2976 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
2977 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
2979 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
2980 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2986 * Actual coherent framebuffer read implemented using the native render target
2987 * read message. Requires SKL+.
2990 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
2992 assert(bld
.shader
->devinfo
->gen
>= 9);
2993 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
2994 inst
->target
= target
;
2995 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3001 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3003 if (n
&& regs
[0].file
!= BAD_FILE
) {
3007 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3009 for (unsigned i
= 0; i
< n
; i
++)
3017 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3019 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3020 const brw_wm_prog_key
*const key
=
3021 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3022 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3023 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3025 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3026 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3028 else if (l
== FRAG_RESULT_COLOR
)
3029 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3030 MAX2(key
->nr_color_regions
, 1));
3032 else if (l
== FRAG_RESULT_DEPTH
)
3033 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3035 else if (l
== FRAG_RESULT_STENCIL
)
3036 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3038 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3039 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3041 else if (l
>= FRAG_RESULT_DATA0
&&
3042 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3043 return alloc_temporary(v
->bld
, 4,
3044 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3047 unreachable("Invalid location");
3051 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3052 nir_intrinsic_instr
*instr
)
3054 assert(stage
== MESA_SHADER_FRAGMENT
);
3057 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3058 dest
= get_nir_dest(instr
->dest
);
3060 switch (instr
->intrinsic
) {
3061 case nir_intrinsic_load_front_face
:
3062 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3063 *emit_frontfacing_interpolation());
3066 case nir_intrinsic_load_sample_pos
: {
3067 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3068 assert(sample_pos
.file
!= BAD_FILE
);
3069 dest
.type
= sample_pos
.type
;
3070 bld
.MOV(dest
, sample_pos
);
3071 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3075 case nir_intrinsic_load_layer_id
:
3076 dest
.type
= BRW_REGISTER_TYPE_UD
;
3077 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3080 case nir_intrinsic_load_helper_invocation
:
3081 case nir_intrinsic_load_sample_mask_in
:
3082 case nir_intrinsic_load_sample_id
: {
3083 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3084 fs_reg val
= nir_system_values
[sv
];
3085 assert(val
.file
!= BAD_FILE
);
3086 dest
.type
= val
.type
;
3091 case nir_intrinsic_store_output
: {
3092 const fs_reg src
= get_nir_src(instr
->src
[0]);
3093 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3094 assert(const_offset
&& "Indirect output stores not allowed");
3095 const unsigned location
= nir_intrinsic_base(instr
) +
3096 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3097 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3100 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3101 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3102 offset(src
, bld
, j
));
3107 case nir_intrinsic_load_output
: {
3108 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3109 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3110 assert(l
>= FRAG_RESULT_DATA0
);
3111 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3112 assert(const_offset
&& "Indirect output loads not allowed");
3113 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3114 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3116 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3117 emit_coherent_fb_read(bld
, tmp
, target
);
3119 emit_non_coherent_fb_read(bld
, tmp
, target
);
3121 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3122 bld
.MOV(offset(dest
, bld
, j
),
3123 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3129 case nir_intrinsic_discard
:
3130 case nir_intrinsic_discard_if
: {
3131 /* We track our discarded pixels in f0.1. By predicating on it, we can
3132 * update just the flag bits that aren't yet discarded. If there's no
3133 * condition, we emit a CMP of g0 != g0, so all currently executing
3134 * channels will get turned off.
3137 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3138 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3139 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3141 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3142 BRW_REGISTER_TYPE_UW
));
3143 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3145 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3146 cmp
->flag_subreg
= 1;
3148 if (devinfo
->gen
>= 6) {
3149 emit_discard_jump();
3154 case nir_intrinsic_load_input
: {
3155 /* load_input is only used for flat inputs */
3156 unsigned base
= nir_intrinsic_base(instr
);
3157 unsigned component
= nir_intrinsic_component(instr
);
3158 unsigned num_components
= instr
->num_components
;
3159 enum brw_reg_type type
= dest
.type
;
3161 /* Special case fields in the VUE header */
3162 if (base
== VARYING_SLOT_LAYER
)
3164 else if (base
== VARYING_SLOT_VIEWPORT
)
3167 if (nir_dest_bit_size(instr
->dest
) == 64) {
3168 /* const_index is in 32-bit type size units that could not be aligned
3169 * with DF. We need to read the double vector as if it was a float
3170 * vector of twice the number of components to fetch the right data.
3172 type
= BRW_REGISTER_TYPE_F
;
3173 num_components
*= 2;
3176 for (unsigned int i
= 0; i
< num_components
; i
++) {
3177 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3178 interp
= suboffset(interp
, 3);
3179 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3180 retype(fs_reg(interp
), type
));
3183 if (nir_dest_bit_size(instr
->dest
) == 64) {
3184 shuffle_32bit_load_result_to_64bit_data(bld
,
3187 instr
->num_components
);
3192 case nir_intrinsic_load_barycentric_pixel
:
3193 case nir_intrinsic_load_barycentric_centroid
:
3194 case nir_intrinsic_load_barycentric_sample
:
3195 /* Do nothing - load_interpolated_input handling will handle it later. */
3198 case nir_intrinsic_load_barycentric_at_sample
: {
3199 const glsl_interp_mode interpolation
=
3200 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3202 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3205 unsigned msg_data
= const_sample
->i32
[0] << 4;
3207 emit_pixel_interpolater_send(bld
,
3208 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3211 brw_imm_ud(msg_data
),
3214 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3215 BRW_REGISTER_TYPE_UD
);
3217 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3218 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3219 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3220 bld
.exec_all().group(1, 0)
3221 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3222 emit_pixel_interpolater_send(bld
,
3223 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3229 /* Make a loop that sends a message to the pixel interpolater
3230 * for the sample number in each live channel. If there are
3231 * multiple channels with the same sample number then these
3232 * will be handled simultaneously with a single interation of
3235 bld
.emit(BRW_OPCODE_DO
);
3237 /* Get the next live sample number into sample_id_reg */
3238 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3240 /* Set the flag register so that we can perform the send
3241 * message on all channels that have the same sample number
3243 bld
.CMP(bld
.null_reg_ud(),
3244 sample_src
, sample_id
,
3245 BRW_CONDITIONAL_EQ
);
3246 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3247 bld
.exec_all().group(1, 0)
3248 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3250 emit_pixel_interpolater_send(bld
,
3251 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3256 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3258 /* Continue the loop if there are any live channels left */
3259 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3261 bld
.emit(BRW_OPCODE_WHILE
));
3267 case nir_intrinsic_load_barycentric_at_offset
: {
3268 const glsl_interp_mode interpolation
=
3269 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3271 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3274 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3275 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3277 emit_pixel_interpolater_send(bld
,
3278 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3281 brw_imm_ud(off_x
| (off_y
<< 4)),
3284 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3285 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3286 BRW_REGISTER_TYPE_F
);
3287 for (int i
= 0; i
< 2; i
++) {
3288 fs_reg temp
= vgrf(glsl_type::float_type
);
3289 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3290 fs_reg itemp
= vgrf(glsl_type::int_type
);
3292 bld
.MOV(itemp
, temp
);
3294 /* Clamp the upper end of the range to +7/16.
3295 * ARB_gpu_shader5 requires that we support a maximum offset
3296 * of +0.5, which isn't representable in a S0.4 value -- if
3297 * we didn't clamp it, we'd end up with -8/16, which is the
3298 * opposite of what the shader author wanted.
3300 * This is legal due to ARB_gpu_shader5's quantization
3303 * "Not all values of <offset> may be supported; x and y
3304 * offsets may be rounded to fixed-point values with the
3305 * number of fraction bits given by the
3306 * implementation-dependent constant
3307 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3309 set_condmod(BRW_CONDITIONAL_L
,
3310 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3313 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3314 emit_pixel_interpolater_send(bld
,
3324 case nir_intrinsic_load_interpolated_input
: {
3325 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3326 emit_fragcoord_interpolation(dest
);
3330 assert(instr
->src
[0].ssa
&&
3331 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3332 nir_intrinsic_instr
*bary_intrinsic
=
3333 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3334 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3335 enum glsl_interp_mode interp_mode
=
3336 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3339 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3340 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3341 /* Use the result of the PI message */
3342 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3344 /* Use the delta_xy values computed from the payload */
3345 enum brw_barycentric_mode bary
=
3346 brw_barycentric_mode(interp_mode
, bary_intrin
);
3348 dst_xy
= this->delta_xy
[bary
];
3351 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3353 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3354 nir_intrinsic_component(instr
) + i
));
3355 interp
.type
= BRW_REGISTER_TYPE_F
;
3356 dest
.type
= BRW_REGISTER_TYPE_F
;
3358 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3359 fs_reg tmp
= vgrf(glsl_type::float_type
);
3360 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3361 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3363 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3370 nir_emit_intrinsic(bld
, instr
);
3376 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3377 nir_intrinsic_instr
*instr
)
3379 assert(stage
== MESA_SHADER_COMPUTE
);
3380 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3383 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3384 dest
= get_nir_dest(instr
->dest
);
3386 switch (instr
->intrinsic
) {
3387 case nir_intrinsic_barrier
:
3389 cs_prog_data
->uses_barrier
= true;
3392 case nir_intrinsic_load_local_invocation_id
:
3393 case nir_intrinsic_load_work_group_id
: {
3394 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3395 fs_reg val
= nir_system_values
[sv
];
3396 assert(val
.file
!= BAD_FILE
);
3397 dest
.type
= val
.type
;
3398 for (unsigned i
= 0; i
< 3; i
++)
3399 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3403 case nir_intrinsic_load_num_work_groups
: {
3404 const unsigned surface
=
3405 cs_prog_data
->binding_table
.work_groups_start
;
3407 cs_prog_data
->uses_num_work_groups
= true;
3409 fs_reg surf_index
= brw_imm_ud(surface
);
3410 brw_mark_surface_used(prog_data
, surface
);
3412 /* Read the 3 GLuint components of gl_NumWorkGroups */
3413 for (unsigned i
= 0; i
< 3; i
++) {
3414 fs_reg read_result
=
3415 emit_untyped_read(bld
, surf_index
,
3417 1 /* dims */, 1 /* size */,
3418 BRW_PREDICATE_NONE
);
3419 read_result
.type
= dest
.type
;
3420 bld
.MOV(dest
, read_result
);
3421 dest
= offset(dest
, bld
, 1);
3426 case nir_intrinsic_shared_atomic_add
:
3427 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3429 case nir_intrinsic_shared_atomic_imin
:
3430 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3432 case nir_intrinsic_shared_atomic_umin
:
3433 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3435 case nir_intrinsic_shared_atomic_imax
:
3436 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3438 case nir_intrinsic_shared_atomic_umax
:
3439 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3441 case nir_intrinsic_shared_atomic_and
:
3442 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3444 case nir_intrinsic_shared_atomic_or
:
3445 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3447 case nir_intrinsic_shared_atomic_xor
:
3448 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3450 case nir_intrinsic_shared_atomic_exchange
:
3451 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3453 case nir_intrinsic_shared_atomic_comp_swap
:
3454 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3457 case nir_intrinsic_load_shared
: {
3458 assert(devinfo
->gen
>= 7);
3460 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3462 /* Get the offset to read from */
3464 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3466 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3468 offset_reg
= vgrf(glsl_type::uint_type
);
3470 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3471 brw_imm_ud(instr
->const_index
[0]));
3474 /* Read the vector */
3475 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3476 instr
->num_components
);
3480 case nir_intrinsic_store_shared
: {
3481 assert(devinfo
->gen
>= 7);
3484 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3487 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3490 unsigned writemask
= instr
->const_index
[1];
3492 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3493 * since the untyped writes below operate in units of 32-bits, which
3494 * means that we need to write twice as many components each time.
3495 * Also, we have to suffle 64-bit data to be in the appropriate layout
3496 * expected by our 32-bit write messages.
3498 unsigned type_size
= 4;
3499 unsigned bit_size
= instr
->src
[0].is_ssa
?
3500 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3501 if (bit_size
== 64) {
3504 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3505 shuffle_64bit_data_for_32bit_write(
3507 retype(tmp
, BRW_REGISTER_TYPE_F
),
3508 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3509 instr
->num_components
);
3513 unsigned type_slots
= type_size
/ 4;
3515 /* Combine groups of consecutive enabled channels in one write
3516 * message. We use ffs to find the first enabled channel and then ffs on
3517 * the bit-inverse, down-shifted writemask to determine the length of
3518 * the block of enabled bits.
3521 unsigned first_component
= ffs(writemask
) - 1;
3522 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3524 /* We can't write more than 2 64-bit components at once. Limit the
3525 * length of the write to what we can do and let the next iteration
3529 length
= MIN2(2, length
);
3532 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3534 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3535 type_size
* first_component
);
3537 offset_reg
= vgrf(glsl_type::uint_type
);
3539 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3540 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3543 emit_untyped_write(bld
, surf_index
, offset_reg
,
3544 offset(val_reg
, bld
, first_component
* type_slots
),
3545 1 /* dims */, length
* type_slots
,
3546 BRW_PREDICATE_NONE
);
3548 /* Clear the bits in the writemask that we just wrote, then try
3549 * again to see if more channels are left.
3551 writemask
&= (15 << (first_component
+ length
));
3558 nir_emit_intrinsic(bld
, instr
);
3564 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3567 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3568 dest
= get_nir_dest(instr
->dest
);
3570 switch (instr
->intrinsic
) {
3571 case nir_intrinsic_atomic_counter_inc
:
3572 case nir_intrinsic_atomic_counter_dec
:
3573 case nir_intrinsic_atomic_counter_read
:
3574 case nir_intrinsic_atomic_counter_add
:
3575 case nir_intrinsic_atomic_counter_min
:
3576 case nir_intrinsic_atomic_counter_max
:
3577 case nir_intrinsic_atomic_counter_and
:
3578 case nir_intrinsic_atomic_counter_or
:
3579 case nir_intrinsic_atomic_counter_xor
:
3580 case nir_intrinsic_atomic_counter_exchange
:
3581 case nir_intrinsic_atomic_counter_comp_swap
: {
3582 if (stage
== MESA_SHADER_FRAGMENT
&&
3583 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3584 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3586 /* Get some metadata from the image intrinsic. */
3587 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3589 /* Get the arguments of the atomic intrinsic. */
3590 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3591 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3592 instr
->const_index
[0]);
3593 const fs_reg src0
= (info
->num_srcs
>= 2
3594 ? get_nir_src(instr
->src
[1]) : fs_reg());
3595 const fs_reg src1
= (info
->num_srcs
>= 3
3596 ? get_nir_src(instr
->src
[2]) : fs_reg());
3599 assert(info
->num_srcs
<= 3);
3601 /* Emit a surface read or atomic op. */
3602 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3603 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3605 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3607 get_atomic_counter_op(instr
->intrinsic
));
3610 /* Assign the result. */
3611 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3613 /* Mark the surface as used. */
3614 brw_mark_surface_used(stage_prog_data
, surface
);
3618 case nir_intrinsic_image_load
:
3619 case nir_intrinsic_image_store
:
3620 case nir_intrinsic_image_atomic_add
:
3621 case nir_intrinsic_image_atomic_min
:
3622 case nir_intrinsic_image_atomic_max
:
3623 case nir_intrinsic_image_atomic_and
:
3624 case nir_intrinsic_image_atomic_or
:
3625 case nir_intrinsic_image_atomic_xor
:
3626 case nir_intrinsic_image_atomic_exchange
:
3627 case nir_intrinsic_image_atomic_comp_swap
: {
3628 using namespace image_access
;
3630 if (stage
== MESA_SHADER_FRAGMENT
&&
3631 instr
->intrinsic
!= nir_intrinsic_image_load
)
3632 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3634 /* Get the referenced image variable and type. */
3635 const nir_variable
*var
= instr
->variables
[0]->var
;
3636 const glsl_type
*type
= var
->type
->without_array();
3637 const brw_reg_type base_type
= get_image_base_type(type
);
3639 /* Get some metadata from the image intrinsic. */
3640 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3641 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3642 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3643 const unsigned format
= var
->data
.image
.format
;
3645 /* Get the arguments of the image intrinsic. */
3646 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3647 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3648 BRW_REGISTER_TYPE_UD
);
3649 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3650 retype(get_nir_src(instr
->src
[2]), base_type
) :
3652 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3653 retype(get_nir_src(instr
->src
[3]), base_type
) :
3657 /* Emit an image load, store or atomic op. */
3658 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3659 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3661 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3662 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3663 var
->data
.image
.write_only
? GL_NONE
: format
);
3666 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3667 surf_dims
, arr_dims
, info
->dest_components
,
3668 get_image_atomic_op(instr
->intrinsic
, type
));
3670 /* Assign the result. */
3671 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3672 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3673 offset(tmp
, bld
, c
));
3677 case nir_intrinsic_memory_barrier_atomic_counter
:
3678 case nir_intrinsic_memory_barrier_buffer
:
3679 case nir_intrinsic_memory_barrier_image
:
3680 case nir_intrinsic_memory_barrier
: {
3681 const fs_builder ubld
= bld
.group(8, 0);
3682 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3683 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3684 ->size_written
= 2 * REG_SIZE
;
3688 case nir_intrinsic_group_memory_barrier
:
3689 case nir_intrinsic_memory_barrier_shared
:
3690 /* We treat these workgroup-level barriers as no-ops. This should be
3691 * safe at present and as long as:
3693 * - Memory access instructions are not subsequently reordered by the
3694 * compiler back-end.
3696 * - All threads from a given compute shader workgroup fit within a
3697 * single subslice and therefore talk to the same HDC shared unit
3698 * what supposedly guarantees ordering and coherency between threads
3699 * from the same workgroup. This may change in the future when we
3700 * start splitting workgroups across multiple subslices.
3702 * - The context is not in fault-and-stream mode, which could cause
3703 * memory transactions (including to SLM) prior to the barrier to be
3704 * replayed after the barrier if a pagefault occurs. This shouldn't
3705 * be a problem up to and including SKL because fault-and-stream is
3706 * not usable due to hardware issues, but that's likely to change in
3711 case nir_intrinsic_shader_clock
: {
3712 /* We cannot do anything if there is an event, so ignore it for now */
3713 const fs_reg shader_clock
= get_timestamp(bld
);
3714 const fs_reg srcs
[] = { component(shader_clock
, 0),
3715 component(shader_clock
, 1) };
3716 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3720 case nir_intrinsic_image_size
: {
3721 /* Get the referenced image variable and type. */
3722 const nir_variable
*var
= instr
->variables
[0]->var
;
3723 const glsl_type
*type
= var
->type
->without_array();
3725 /* Get the size of the image. */
3726 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3727 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3729 /* For 1DArray image types, the array index is stored in the Z component.
3730 * Fix this by swizzling the Z component to the Y component.
3732 const bool is_1d_array_image
=
3733 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3734 type
->sampler_array
;
3736 /* For CubeArray images, we should count the number of cubes instead
3737 * of the number of faces. Fix it by dividing the (Z component) by 6.
3739 const bool is_cube_array_image
=
3740 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3741 type
->sampler_array
;
3743 /* Copy all the components. */
3744 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3745 if ((int)c
>= type
->coordinate_components()) {
3746 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3748 } else if (c
== 1 && is_1d_array_image
) {
3749 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3750 offset(size
, bld
, 2));
3751 } else if (c
== 2 && is_cube_array_image
) {
3752 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3753 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3754 offset(size
, bld
, c
), brw_imm_d(6));
3756 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3757 offset(size
, bld
, c
));
3764 case nir_intrinsic_image_samples
:
3765 /* The driver does not support multi-sampled images. */
3766 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3769 case nir_intrinsic_load_uniform
: {
3770 /* Offsets are in bytes but they should always be multiples of 4 */
3771 assert(instr
->const_index
[0] % 4 == 0);
3773 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3775 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3777 /* Offsets are in bytes but they should always be multiples of 4 */
3778 assert(const_offset
->u32
[0] % 4 == 0);
3779 src
.offset
= const_offset
->u32
[0];
3781 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3782 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3785 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3786 BRW_REGISTER_TYPE_UD
);
3788 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3789 * go past the end of the uniform. In order to keep the n'th
3790 * component from running past, we subtract off the size of all but
3791 * one component of the vector.
3793 assert(instr
->const_index
[1] >=
3794 instr
->num_components
* (int) type_sz(dest
.type
));
3795 unsigned read_size
= instr
->const_index
[1] -
3796 (instr
->num_components
- 1) * type_sz(dest
.type
);
3798 bool supports_64bit_indirects
=
3799 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
;
3801 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3802 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3803 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3804 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3805 indirect
, brw_imm_ud(read_size
));
3808 const unsigned num_mov_indirects
=
3809 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3810 /* We read a little bit less per MOV INDIRECT, as they are now
3811 * 32-bits ones instead of 64-bit. Fix read_size then.
3813 const unsigned read_size_32bit
= read_size
-
3814 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3815 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3816 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3817 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3818 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3819 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3820 indirect
, brw_imm_ud(read_size_32bit
));
3828 case nir_intrinsic_load_ubo
: {
3829 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3833 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3834 const_index
->u32
[0];
3835 surf_index
= brw_imm_ud(index
);
3836 brw_mark_surface_used(prog_data
, index
);
3838 /* The block index is not a constant. Evaluate the index expression
3839 * per-channel and add the base UBO index; we have to select a value
3840 * from any live channel.
3842 surf_index
= vgrf(glsl_type::uint_type
);
3843 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3844 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3845 surf_index
= bld
.emit_uniformize(surf_index
);
3847 /* Assume this may touch any UBO. It would be nice to provide
3848 * a tighter bound, but the array information is already lowered away.
3850 brw_mark_surface_used(prog_data
,
3851 stage_prog_data
->binding_table
.ubo_start
+
3852 nir
->info
.num_ubos
- 1);
3855 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3856 if (const_offset
== NULL
) {
3857 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3858 BRW_REGISTER_TYPE_UD
);
3860 for (int i
= 0; i
< instr
->num_components
; i
++)
3861 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3862 base_offset
, i
* type_sz(dest
.type
));
3864 /* Even if we are loading doubles, a pull constant load will load
3865 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3866 * need to load a full dvec4 we will have to emit 2 loads. This is
3867 * similar to demote_pull_constants(), except that in that case we
3868 * see individual accesses to each component of the vector and then
3869 * we let CSE deal with duplicate loads. Here we see a vector access
3870 * and we have to split it if necessary.
3872 const unsigned type_size
= type_sz(dest
.type
);
3873 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3874 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3875 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3877 for (unsigned c
= 0; c
< instr
->num_components
;) {
3878 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3879 /* Number of usable components in the next block-aligned load. */
3880 const unsigned count
= MIN2(instr
->num_components
- c
,
3881 (block_sz
- base
% block_sz
) / type_size
);
3883 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3884 packed_consts
, surf_index
,
3885 brw_imm_ud(base
& ~(block_sz
- 1)));
3887 const fs_reg consts
=
3888 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3891 for (unsigned d
= 0; d
< count
; d
++)
3892 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3900 case nir_intrinsic_load_ssbo
: {
3901 assert(devinfo
->gen
>= 7);
3903 nir_const_value
*const_uniform_block
=
3904 nir_src_as_const_value(instr
->src
[0]);
3907 if (const_uniform_block
) {
3908 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3909 const_uniform_block
->u32
[0];
3910 surf_index
= brw_imm_ud(index
);
3911 brw_mark_surface_used(prog_data
, index
);
3913 surf_index
= vgrf(glsl_type::uint_type
);
3914 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3915 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3917 /* Assume this may touch any UBO. It would be nice to provide
3918 * a tighter bound, but the array information is already lowered away.
3920 brw_mark_surface_used(prog_data
,
3921 stage_prog_data
->binding_table
.ssbo_start
+
3922 nir
->info
.num_ssbos
- 1);
3926 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3928 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3930 offset_reg
= get_nir_src(instr
->src
[1]);
3933 /* Read the vector */
3934 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3935 instr
->num_components
);
3940 case nir_intrinsic_store_ssbo
: {
3941 assert(devinfo
->gen
>= 7);
3943 if (stage
== MESA_SHADER_FRAGMENT
)
3944 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3948 nir_const_value
*const_uniform_block
=
3949 nir_src_as_const_value(instr
->src
[1]);
3950 if (const_uniform_block
) {
3951 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3952 const_uniform_block
->u32
[0];
3953 surf_index
= brw_imm_ud(index
);
3954 brw_mark_surface_used(prog_data
, index
);
3956 surf_index
= vgrf(glsl_type::uint_type
);
3957 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3958 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3960 brw_mark_surface_used(prog_data
,
3961 stage_prog_data
->binding_table
.ssbo_start
+
3962 nir
->info
.num_ssbos
- 1);
3966 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3969 unsigned writemask
= instr
->const_index
[0];
3971 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3972 * since the untyped writes below operate in units of 32-bits, which
3973 * means that we need to write twice as many components each time.
3974 * Also, we have to suffle 64-bit data to be in the appropriate layout
3975 * expected by our 32-bit write messages.
3977 unsigned type_size
= 4;
3978 unsigned bit_size
= instr
->src
[0].is_ssa
?
3979 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3980 if (bit_size
== 64) {
3983 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3984 shuffle_64bit_data_for_32bit_write(bld
,
3985 retype(tmp
, BRW_REGISTER_TYPE_F
),
3986 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3987 instr
->num_components
);
3991 unsigned type_slots
= type_size
/ 4;
3993 /* Combine groups of consecutive enabled channels in one write
3994 * message. We use ffs to find the first enabled channel and then ffs on
3995 * the bit-inverse, down-shifted writemask to determine the length of
3996 * the block of enabled bits.
3999 unsigned first_component
= ffs(writemask
) - 1;
4000 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4002 /* We can't write more than 2 64-bit components at once. Limit the
4003 * length of the write to what we can do and let the next iteration
4007 length
= MIN2(2, length
);
4010 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4012 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4013 type_size
* first_component
);
4015 offset_reg
= vgrf(glsl_type::uint_type
);
4017 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4018 brw_imm_ud(type_size
* first_component
));
4022 emit_untyped_write(bld
, surf_index
, offset_reg
,
4023 offset(val_reg
, bld
, first_component
* type_slots
),
4024 1 /* dims */, length
* type_slots
,
4025 BRW_PREDICATE_NONE
);
4027 /* Clear the bits in the writemask that we just wrote, then try
4028 * again to see if more channels are left.
4030 writemask
&= (15 << (first_component
+ length
));
4035 case nir_intrinsic_store_output
: {
4036 fs_reg src
= get_nir_src(instr
->src
[0]);
4038 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4039 assert(const_offset
&& "Indirect output stores not allowed");
4040 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4041 4 * const_offset
->u32
[0]), src
.type
);
4043 unsigned num_components
= instr
->num_components
;
4044 unsigned first_component
= nir_intrinsic_component(instr
);
4045 unsigned bit_size
= instr
->src
[0].is_ssa
?
4046 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4047 if (bit_size
== 64) {
4049 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4050 BRW_REGISTER_TYPE_F
);
4051 shuffle_64bit_data_for_32bit_write(
4052 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4053 src
= retype(tmp
, src
.type
);
4054 num_components
*= 2;
4057 for (unsigned j
= 0; j
< num_components
; j
++) {
4058 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4059 offset(src
, bld
, j
));
4064 case nir_intrinsic_ssbo_atomic_add
:
4065 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4067 case nir_intrinsic_ssbo_atomic_imin
:
4068 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4070 case nir_intrinsic_ssbo_atomic_umin
:
4071 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4073 case nir_intrinsic_ssbo_atomic_imax
:
4074 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4076 case nir_intrinsic_ssbo_atomic_umax
:
4077 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4079 case nir_intrinsic_ssbo_atomic_and
:
4080 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4082 case nir_intrinsic_ssbo_atomic_or
:
4083 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4085 case nir_intrinsic_ssbo_atomic_xor
:
4086 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4088 case nir_intrinsic_ssbo_atomic_exchange
:
4089 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4091 case nir_intrinsic_ssbo_atomic_comp_swap
:
4092 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4095 case nir_intrinsic_get_buffer_size
: {
4096 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4097 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4099 /* A resinfo's sampler message is used to get the buffer size. The
4100 * SIMD8's writeback message consists of four registers and SIMD16's
4101 * writeback message consists of 8 destination registers (two per each
4102 * component). Because we are only interested on the first channel of
4103 * the first returned component, where resinfo returns the buffer size
4104 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4105 * the dispatch width.
4107 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4108 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4109 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4112 ubld
.MOV(src_payload
, brw_imm_d(0));
4114 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4115 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4116 src_payload
, brw_imm_ud(index
));
4117 inst
->header_size
= 0;
4119 inst
->size_written
= 4 * REG_SIZE
;
4121 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4122 brw_mark_surface_used(prog_data
, index
);
4126 case nir_intrinsic_load_channel_num
: {
4127 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4128 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4129 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4130 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4131 if (dispatch_width
> 8)
4132 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4133 if (dispatch_width
> 16) {
4134 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4135 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4142 unreachable("unknown intrinsic");
4147 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4148 int op
, nir_intrinsic_instr
*instr
)
4150 if (stage
== MESA_SHADER_FRAGMENT
)
4151 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4154 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4155 dest
= get_nir_dest(instr
->dest
);
4158 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4159 if (const_surface
) {
4160 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4161 const_surface
->u32
[0];
4162 surface
= brw_imm_ud(surf_index
);
4163 brw_mark_surface_used(prog_data
, surf_index
);
4165 surface
= vgrf(glsl_type::uint_type
);
4166 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4167 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4169 /* Assume this may touch any SSBO. This is the same we do for other
4170 * UBO/SSBO accesses with non-constant surface.
4172 brw_mark_surface_used(prog_data
,
4173 stage_prog_data
->binding_table
.ssbo_start
+
4174 nir
->info
.num_ssbos
- 1);
4177 fs_reg offset
= get_nir_src(instr
->src
[1]);
4178 fs_reg data1
= get_nir_src(instr
->src
[2]);
4180 if (op
== BRW_AOP_CMPWR
)
4181 data2
= get_nir_src(instr
->src
[3]);
4183 /* Emit the actual atomic operation */
4185 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4187 1 /* dims */, 1 /* rsize */,
4189 BRW_PREDICATE_NONE
);
4190 dest
.type
= atomic_result
.type
;
4191 bld
.MOV(dest
, atomic_result
);
4195 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4196 int op
, nir_intrinsic_instr
*instr
)
4199 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4200 dest
= get_nir_dest(instr
->dest
);
4202 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4204 fs_reg data1
= get_nir_src(instr
->src
[1]);
4206 if (op
== BRW_AOP_CMPWR
)
4207 data2
= get_nir_src(instr
->src
[2]);
4209 /* Get the offset */
4210 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4212 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4214 offset
= vgrf(glsl_type::uint_type
);
4216 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4217 brw_imm_ud(instr
->const_index
[0]));
4220 /* Emit the actual atomic operation operation */
4222 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4224 1 /* dims */, 1 /* rsize */,
4226 BRW_PREDICATE_NONE
);
4227 dest
.type
= atomic_result
.type
;
4228 bld
.MOV(dest
, atomic_result
);
4232 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4234 unsigned texture
= instr
->texture_index
;
4235 unsigned sampler
= instr
->sampler_index
;
4237 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4239 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4240 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4242 int lod_components
= 0;
4244 /* The hardware requires a LOD for buffer textures */
4245 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4246 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4248 uint32_t header_bits
= 0;
4249 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4250 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4251 switch (instr
->src
[i
].src_type
) {
4252 case nir_tex_src_bias
:
4253 srcs
[TEX_LOGICAL_SRC_LOD
] =
4254 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4256 case nir_tex_src_comparator
:
4257 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4259 case nir_tex_src_coord
:
4260 switch (instr
->op
) {
4262 case nir_texop_txf_ms
:
4263 case nir_texop_txf_ms_mcs
:
4264 case nir_texop_samples_identical
:
4265 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4268 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4272 case nir_tex_src_ddx
:
4273 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4274 lod_components
= nir_tex_instr_src_size(instr
, i
);
4276 case nir_tex_src_ddy
:
4277 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4279 case nir_tex_src_lod
:
4280 switch (instr
->op
) {
4282 srcs
[TEX_LOGICAL_SRC_LOD
] =
4283 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4286 srcs
[TEX_LOGICAL_SRC_LOD
] =
4287 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4290 srcs
[TEX_LOGICAL_SRC_LOD
] =
4291 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4295 case nir_tex_src_ms_index
:
4296 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4299 case nir_tex_src_offset
: {
4300 nir_const_value
*const_offset
=
4301 nir_src_as_const_value(instr
->src
[i
].src
);
4302 unsigned offset_bits
= 0;
4304 brw_texture_offset(const_offset
->i32
,
4305 nir_tex_instr_src_size(instr
, i
),
4307 header_bits
|= offset_bits
;
4309 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4310 retype(src
, BRW_REGISTER_TYPE_D
);
4315 case nir_tex_src_projector
:
4316 unreachable("should be lowered");
4318 case nir_tex_src_texture_offset
: {
4319 /* Figure out the highest possible texture index and mark it as used */
4320 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4321 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4322 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4324 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4326 brw_mark_surface_used(prog_data
, max_used
);
4328 /* Emit code to evaluate the actual indexing expression */
4329 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4330 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4331 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4335 case nir_tex_src_sampler_offset
: {
4336 /* Emit code to evaluate the actual indexing expression */
4337 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4338 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4339 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4343 case nir_tex_src_ms_mcs
:
4344 assert(instr
->op
== nir_texop_txf_ms
);
4345 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4348 case nir_tex_src_plane
: {
4349 nir_const_value
*const_plane
=
4350 nir_src_as_const_value(instr
->src
[i
].src
);
4351 const uint32_t plane
= const_plane
->u32
[0];
4352 const uint32_t texture_index
=
4353 instr
->texture_index
+
4354 stage_prog_data
->binding_table
.plane_start
[plane
] -
4355 stage_prog_data
->binding_table
.texture_start
;
4357 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4362 unreachable("unknown texture source");
4366 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4367 (instr
->op
== nir_texop_txf_ms
||
4368 instr
->op
== nir_texop_samples_identical
)) {
4369 if (devinfo
->gen
>= 7 &&
4370 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4371 srcs
[TEX_LOGICAL_SRC_MCS
] =
4372 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4373 instr
->coord_components
,
4374 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4376 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4380 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4381 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4384 switch (instr
->op
) {
4386 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4387 SHADER_OPCODE_TXL_LOGICAL
);
4390 opcode
= FS_OPCODE_TXB_LOGICAL
;
4393 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4396 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4399 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4401 case nir_texop_txf_ms
:
4402 if ((key_tex
->msaa_16
& (1 << sampler
)))
4403 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4405 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4407 case nir_texop_txf_ms_mcs
:
4408 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4410 case nir_texop_query_levels
:
4412 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4415 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4418 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4419 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4421 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4423 case nir_texop_texture_samples
:
4424 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4426 case nir_texop_samples_identical
: {
4427 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4429 /* If mcs is an immediate value, it means there is no MCS. In that case
4430 * just return false.
4432 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4433 bld
.MOV(dst
, brw_imm_ud(0u));
4434 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4435 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4436 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4437 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4438 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4440 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4441 BRW_CONDITIONAL_EQ
);
4446 unreachable("unknown texture opcode");
4449 /* TXS and TXL require a LOD but not everything we implement using those
4450 * two opcodes provides one. Provide a default LOD of 0.
4452 if ((opcode
== SHADER_OPCODE_TXS_LOGICAL
||
4453 opcode
== SHADER_OPCODE_TXL_LOGICAL
) &&
4454 srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
) {
4455 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4458 if (instr
->op
== nir_texop_tg4
) {
4459 if (instr
->component
== 1 &&
4460 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4461 /* gather4 sampler is broken for green channel on RG32F --
4462 * we must ask for blue instead.
4464 header_bits
|= 2 << 16;
4466 header_bits
|= instr
->component
<< 16;
4470 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4471 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4472 inst
->offset
= header_bits
;
4474 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4475 if (devinfo
->gen
>= 9 &&
4476 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4477 unsigned write_mask
= instr
->dest
.is_ssa
?
4478 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4479 (1 << dest_size
) - 1;
4480 assert(write_mask
!= 0); /* dead code should have been eliminated */
4481 inst
->size_written
= util_last_bit(write_mask
) *
4482 inst
->dst
.component_size(inst
->exec_size
);
4484 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4487 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4488 inst
->shadow_compare
= true;
4490 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4491 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4494 for (unsigned i
= 0; i
< dest_size
; i
++)
4495 nir_dest
[i
] = offset(dst
, bld
, i
);
4497 if (instr
->op
== nir_texop_query_levels
) {
4498 /* # levels is in .w */
4499 nir_dest
[0] = offset(dst
, bld
, 3);
4500 } else if (instr
->op
== nir_texop_txs
&&
4501 dest_size
>= 3 && devinfo
->gen
< 7) {
4502 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4503 fs_reg depth
= offset(dst
, bld
, 2);
4504 nir_dest
[2] = vgrf(glsl_type::int_type
);
4505 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4508 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4512 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4514 switch (instr
->type
) {
4515 case nir_jump_break
:
4516 bld
.emit(BRW_OPCODE_BREAK
);
4518 case nir_jump_continue
:
4519 bld
.emit(BRW_OPCODE_CONTINUE
);
4521 case nir_jump_return
:
4523 unreachable("unknown jump");
4528 * This helper takes the result of a load operation that reads 32-bit elements
4536 * and shuffles the data to get this:
4543 * Which is exactly what we want if the load is reading 64-bit components
4544 * like doubles, where x represents the low 32-bit of the x double component
4545 * and y represents the high 32-bit of the x double component (likewise with
4546 * z and w for double component y). The parameter @components represents
4547 * the number of 64-bit components present in @src. This would typically be
4548 * 2 at most, since we can only fit 2 double elements in the result of a
4551 * Notice that @dst and @src can be the same register.
4554 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4557 uint32_t components
)
4559 assert(type_sz(src
.type
) == 4);
4560 assert(type_sz(dst
.type
) == 8);
4562 /* A temporary that we will use to shuffle the 32-bit data of each
4563 * component in the vector into valid 64-bit data. We can't write directly
4564 * to dst because dst can be (and would usually be) the same as src
4565 * and in that case the first MOV in the loop below would overwrite the
4566 * data read in the second MOV.
4568 fs_reg tmp
= bld
.vgrf(dst
.type
);
4570 for (unsigned i
= 0; i
< components
; i
++) {
4571 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4573 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4574 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4576 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4581 * This helper does the inverse operation of
4582 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4584 * We need to do this when we are going to use untyped write messsages that
4585 * operate with 32-bit components in order to arrange our 64-bit data to be
4586 * in the expected layout.
4588 * Notice that callers of this function, unlike in the case of the inverse
4589 * operation, would typically need to call this with dst and src being
4590 * different registers, since they would otherwise corrupt the original
4591 * 64-bit data they are about to write. Because of this the function checks
4592 * that the src and dst regions involved in the operation do not overlap.
4595 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4598 uint32_t components
)
4600 assert(type_sz(src
.type
) == 8);
4601 assert(type_sz(dst
.type
) == 4);
4603 assert(!regions_overlap(
4604 dst
, 2 * components
* dst
.component_size(bld
.dispatch_width()),
4605 src
, components
* src
.component_size(bld
.dispatch_width())));
4607 for (unsigned i
= 0; i
< components
; i
++) {
4608 const fs_reg component_i
= offset(src
, bld
, i
);
4609 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4610 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4615 setup_imm_df(const fs_builder
&bld
, double v
)
4617 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4618 assert(devinfo
->gen
>= 7);
4620 if (devinfo
->gen
>= 8)
4621 return brw_imm_df(v
);
4623 /* gen7.5 does not support DF immediates straighforward but the DIM
4624 * instruction allows to set the 64-bit immediate value.
4626 if (devinfo
->is_haswell
) {
4627 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4628 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4629 ubld
.DIM(dst
, brw_imm_df(v
));
4630 return component(dst
, 0);
4633 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4634 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4635 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4637 * Alternatively, we could also produce a normal VGRF (without stride 0)
4638 * by writing to all the channels in the VGRF, however, that would hit the
4639 * gen7 bug where we have to split writes that span more than 1 register
4640 * into instructions with a width of 4 (otherwise the write to the second
4641 * register written runs into an execmask hardware bug) which isn't very
4654 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4655 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4656 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4657 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4659 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);