2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 nir_foreach_variable(var
, &nir
->outputs
) {
57 const unsigned vec4s
=
58 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
59 : type_size_vec4(var
->type
);
60 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
);
61 for (unsigned i
= 0; i
< vec4s
; i
++) {
62 if (outputs
[var
->data
.driver_location
+ i
].file
== BAD_FILE
)
63 outputs
[var
->data
.driver_location
+ i
] = offset(reg
, bld
, 4 * i
);
69 fs_visitor::nir_setup_uniforms()
71 if (dispatch_width
!= min_dispatch_width
)
74 uniforms
= nir
->num_uniforms
/ 4;
78 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
82 nir_foreach_instr(instr
, block
) {
83 if (instr
->type
!= nir_instr_type_intrinsic
)
86 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
87 switch (intrin
->intrinsic
) {
88 case nir_intrinsic_load_vertex_id
:
89 unreachable("should be lowered by lower_vertex_id().");
91 case nir_intrinsic_load_vertex_id_zero_base
:
92 case nir_intrinsic_load_base_vertex
:
93 case nir_intrinsic_load_instance_id
:
94 case nir_intrinsic_load_base_instance
:
95 case nir_intrinsic_load_draw_id
:
96 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
98 case nir_intrinsic_load_invocation_id
:
99 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
101 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
102 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
103 if (reg
->file
== BAD_FILE
) {
104 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
105 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
106 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
107 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
112 case nir_intrinsic_load_sample_pos
:
113 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
114 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
115 if (reg
->file
== BAD_FILE
)
116 *reg
= *v
->emit_samplepos_setup();
119 case nir_intrinsic_load_sample_id
:
120 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
121 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
122 if (reg
->file
== BAD_FILE
)
123 *reg
= *v
->emit_sampleid_setup();
126 case nir_intrinsic_load_sample_mask_in
:
127 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
128 assert(v
->devinfo
->gen
>= 7);
129 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
130 if (reg
->file
== BAD_FILE
)
131 *reg
= *v
->emit_samplemaskin_setup();
134 case nir_intrinsic_load_work_group_id
:
135 assert(v
->stage
== MESA_SHADER_COMPUTE
);
136 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
137 if (reg
->file
== BAD_FILE
)
138 *reg
= *v
->emit_cs_work_group_id_setup();
141 case nir_intrinsic_load_helper_invocation
:
142 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
143 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
144 if (reg
->file
== BAD_FILE
) {
145 const fs_builder abld
=
146 v
->bld
.annotate("gl_HelperInvocation", NULL
);
148 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
149 * pixel mask is in g1.7 of the thread payload.
151 * We move the per-channel pixel enable bit to the low bit of each
152 * channel by shifting the byte containing the pixel mask by the
153 * vector immediate 0x76543210UV.
155 * The region of <1,8,0> reads only 1 byte (the pixel masks for
156 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
157 * masks for 2 and 3) in SIMD16.
159 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
161 stride(byte_offset(retype(brw_vec1_grf(1, 0),
162 BRW_REGISTER_TYPE_UB
), 28),
164 brw_imm_v(0x76543210));
166 /* A set bit in the pixel mask means the channel is enabled, but
167 * that is the opposite of gl_HelperInvocation so we need to invert
170 * The negate source-modifier bit of logical instructions on Gen8+
171 * performs 1's complement negation, so we can use that instead of
174 fs_reg inverted
= negate(shifted
);
175 if (v
->devinfo
->gen
< 8) {
176 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
177 abld
.NOT(inverted
, shifted
);
180 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
181 * with 1 and negating.
183 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
184 abld
.AND(anded
, inverted
, brw_imm_uw(1));
186 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
187 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
201 fs_visitor::nir_emit_system_values()
203 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
204 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
205 nir_system_values
[i
] = fs_reg();
208 nir_foreach_function(function
, nir
) {
209 assert(strcmp(function
->name
, "main") == 0);
210 assert(function
->impl
);
211 nir_foreach_block(block
, function
->impl
) {
212 emit_system_values_block(block
, this);
218 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
220 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
221 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
222 nir_locals
[i
] = fs_reg();
225 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
226 unsigned array_elems
=
227 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
228 unsigned size
= array_elems
* reg
->num_components
;
229 const brw_reg_type reg_type
=
230 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
231 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
234 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
237 nir_emit_cf_list(&impl
->body
);
241 fs_visitor::nir_emit_cf_list(exec_list
*list
)
243 exec_list_validate(list
);
244 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
245 switch (node
->type
) {
247 nir_emit_if(nir_cf_node_as_if(node
));
250 case nir_cf_node_loop
:
251 nir_emit_loop(nir_cf_node_as_loop(node
));
254 case nir_cf_node_block
:
255 nir_emit_block(nir_cf_node_as_block(node
));
259 unreachable("Invalid CFG node block");
265 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
267 /* first, put the condition into f0 */
268 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
269 retype(get_nir_src(if_stmt
->condition
),
270 BRW_REGISTER_TYPE_D
));
271 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
273 bld
.IF(BRW_PREDICATE_NORMAL
);
275 nir_emit_cf_list(&if_stmt
->then_list
);
277 /* note: if the else is empty, dead CF elimination will remove it */
278 bld
.emit(BRW_OPCODE_ELSE
);
280 nir_emit_cf_list(&if_stmt
->else_list
);
282 bld
.emit(BRW_OPCODE_ENDIF
);
286 fs_visitor::nir_emit_loop(nir_loop
*loop
)
288 bld
.emit(BRW_OPCODE_DO
);
290 nir_emit_cf_list(&loop
->body
);
292 bld
.emit(BRW_OPCODE_WHILE
);
296 fs_visitor::nir_emit_block(nir_block
*block
)
298 nir_foreach_instr(instr
, block
) {
299 nir_emit_instr(instr
);
304 fs_visitor::nir_emit_instr(nir_instr
*instr
)
306 const fs_builder abld
= bld
.annotate(NULL
, instr
);
308 switch (instr
->type
) {
309 case nir_instr_type_alu
:
310 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
313 case nir_instr_type_intrinsic
:
315 case MESA_SHADER_VERTEX
:
316 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
318 case MESA_SHADER_TESS_CTRL
:
319 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
321 case MESA_SHADER_TESS_EVAL
:
322 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
324 case MESA_SHADER_GEOMETRY
:
325 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
327 case MESA_SHADER_FRAGMENT
:
328 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
330 case MESA_SHADER_COMPUTE
:
331 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
334 unreachable("unsupported shader stage");
338 case nir_instr_type_tex
:
339 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
342 case nir_instr_type_load_const
:
343 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
346 case nir_instr_type_ssa_undef
:
347 /* We create a new VGRF for undefs on every use (by handling
348 * them in get_nir_src()), rather than for each definition.
349 * This helps register coalescing eliminate MOVs from undef.
353 case nir_instr_type_jump
:
354 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
358 unreachable("unknown instruction type");
363 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
367 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
368 const fs_reg
&result
)
370 if (!instr
->src
[0].src
.is_ssa
||
371 !instr
->src
[0].src
.ssa
->parent_instr
)
374 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
377 nir_alu_instr
*src0
=
378 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
380 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
381 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
384 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
385 assert(element
!= NULL
);
387 /* Element type to extract.*/
388 const brw_reg_type type
= brw_int_type(
389 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
390 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
392 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
393 op0
.type
= brw_type_for_nir_type(devinfo
,
394 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
395 nir_src_bit_size(src0
->src
[0].src
)));
396 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
398 set_saturate(instr
->dest
.saturate
,
399 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
404 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
405 const fs_reg
&result
)
407 if (!instr
->src
[0].src
.is_ssa
||
408 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
411 nir_intrinsic_instr
*src0
=
412 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
414 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
417 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
418 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
421 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
422 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
425 fs_reg tmp
= vgrf(glsl_type::int_type
);
427 if (devinfo
->gen
>= 6) {
428 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
429 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
431 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
433 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
434 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
436 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
438 * This negation looks like it's safe in practice, because bits 0:4 will
439 * surely be TRIANGLES
442 if (value1
->f32
[0] == -1.0f
) {
446 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
447 g0
, brw_imm_uw(0x3f80));
449 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
450 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
452 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
454 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
455 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
457 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
459 * This negation looks like it's safe in practice, because bits 0:4 will
460 * surely be TRIANGLES
463 if (value1
->f32
[0] == -1.0f
) {
467 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
469 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
475 emit_find_msb_using_lzd(const fs_builder
&bld
,
476 const fs_reg
&result
,
484 /* LZD of an absolute value source almost always does the right
485 * thing. There are two problem values:
487 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
488 * 0. However, findMSB(int(0x80000000)) == 30.
490 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
491 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
493 * For a value of zero or negative one, -1 will be returned.
495 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
496 * findMSB(-(1<<x)) should return x-1.
498 * For all negative number cases, including 0x80000000 and
499 * 0xffffffff, the correct value is obtained from LZD if instead of
500 * negating the (already negative) value the logical-not is used. A
501 * conditonal logical-not can be achieved in two instructions.
503 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
505 bld
.ASR(temp
, src
, brw_imm_d(31));
506 bld
.XOR(temp
, temp
, src
);
509 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
510 retype(temp
, BRW_REGISTER_TYPE_UD
));
512 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
513 * from the LSB side. Subtract the result from 31 to convert the MSB
514 * count into an LSB count. If no bits are set, LZD will return 32.
515 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
517 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
518 inst
->src
[0].negate
= true;
522 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
524 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
527 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
528 result
.type
= brw_type_for_nir_type(devinfo
,
529 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
530 nir_dest_bit_size(instr
->dest
.dest
)));
533 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
534 op
[i
] = get_nir_src(instr
->src
[i
].src
);
535 op
[i
].type
= brw_type_for_nir_type(devinfo
,
536 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
537 nir_src_bit_size(instr
->src
[i
].src
)));
538 op
[i
].abs
= instr
->src
[i
].abs
;
539 op
[i
].negate
= instr
->src
[i
].negate
;
542 /* We get a bunch of mov's out of the from_ssa pass and they may still
543 * be vectorized. We'll handle them as a special-case. We'll also
544 * handle vecN here because it's basically the same thing.
552 fs_reg temp
= result
;
553 bool need_extra_copy
= false;
554 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
555 if (!instr
->src
[i
].src
.is_ssa
&&
556 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
557 need_extra_copy
= true;
558 temp
= bld
.vgrf(result
.type
, 4);
563 for (unsigned i
= 0; i
< 4; i
++) {
564 if (!(instr
->dest
.write_mask
& (1 << i
)))
567 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
568 inst
= bld
.MOV(offset(temp
, bld
, i
),
569 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
571 inst
= bld
.MOV(offset(temp
, bld
, i
),
572 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
574 inst
->saturate
= instr
->dest
.saturate
;
577 /* In this case the source and destination registers were the same,
578 * so we need to insert an extra set of moves in order to deal with
581 if (need_extra_copy
) {
582 for (unsigned i
= 0; i
< 4; i
++) {
583 if (!(instr
->dest
.write_mask
& (1 << i
)))
586 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
595 /* At this point, we have dealt with any instruction that operates on
596 * more than a single channel. Therefore, we can just adjust the source
597 * and destination registers for that channel and emit the instruction.
599 unsigned channel
= 0;
600 if (nir_op_infos
[instr
->op
].output_size
== 0) {
601 /* Since NIR is doing the scalarizing for us, we should only ever see
602 * vectorized operations with a single channel.
604 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
605 channel
= ffs(instr
->dest
.write_mask
) - 1;
607 result
= offset(result
, bld
, channel
);
610 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
611 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
612 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
618 if (optimize_extract_to_float(instr
, result
))
620 inst
= bld
.MOV(result
, op
[0]);
621 inst
->saturate
= instr
->dest
.saturate
;
627 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
629 * "When source or destination is 64b (...), regioning in Align1
630 * must follow these rules:
632 * 1. Source and destination horizontal stride must be aligned to
636 * This means that 32-bit to 64-bit conversions need to have the 32-bit
637 * data elements aligned to 64-bit. This restriction does not apply to
640 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
641 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
642 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
643 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
644 tmp
= subscript(tmp
, op
[0].type
, 0);
645 inst
= bld
.MOV(tmp
, op
[0]);
646 inst
= bld
.MOV(result
, tmp
);
647 inst
->saturate
= instr
->dest
.saturate
;
660 inst
= bld
.MOV(result
, op
[0]);
661 inst
->saturate
= instr
->dest
.saturate
;
666 /* Straightforward since the source can be assumed to be
669 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
670 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
672 } else if (type_sz(op
[0].type
) < 8) {
673 /* AND(val, 0x80000000) gives the sign bit.
675 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
678 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
680 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
681 op
[0].type
= BRW_REGISTER_TYPE_UD
;
682 result
.type
= BRW_REGISTER_TYPE_UD
;
683 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
685 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
686 inst
->predicate
= BRW_PREDICATE_NORMAL
;
687 if (instr
->dest
.saturate
) {
688 inst
= bld
.MOV(result
, result
);
689 inst
->saturate
= true;
692 /* For doubles we do the same but we need to consider:
694 * - 2-src instructions can't operate with 64-bit immediates
695 * - The sign is encoded in the high 32-bit of each DF
696 * - We need to produce a DF result.
699 fs_reg zero
= vgrf(glsl_type::double_type
);
700 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
701 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
703 bld
.MOV(result
, zero
);
705 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
706 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
707 brw_imm_ud(0x80000000u
));
709 set_predicate(BRW_PREDICATE_NORMAL
,
710 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
712 if (instr
->dest
.saturate
) {
713 inst
= bld
.MOV(result
, result
);
714 inst
->saturate
= true;
721 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
722 * -> non-negative val generates 0x00000000.
723 * Predicated OR sets 1 if val is positive.
725 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
726 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
727 bld
.ASR(result
, op
[0], brw_imm_d(31));
728 inst
= bld
.OR(result
, result
, brw_imm_d(1));
729 inst
->predicate
= BRW_PREDICATE_NORMAL
;
733 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
734 inst
->saturate
= instr
->dest
.saturate
;
738 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
739 inst
->saturate
= instr
->dest
.saturate
;
743 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
744 inst
->saturate
= instr
->dest
.saturate
;
748 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
749 inst
->saturate
= instr
->dest
.saturate
;
753 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
754 inst
->saturate
= instr
->dest
.saturate
;
758 if (fs_key
->high_quality_derivatives
) {
759 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
761 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
763 inst
->saturate
= instr
->dest
.saturate
;
765 case nir_op_fddx_fine
:
766 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
767 inst
->saturate
= instr
->dest
.saturate
;
769 case nir_op_fddx_coarse
:
770 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
771 inst
->saturate
= instr
->dest
.saturate
;
774 if (fs_key
->high_quality_derivatives
) {
775 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
777 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
779 inst
->saturate
= instr
->dest
.saturate
;
781 case nir_op_fddy_fine
:
782 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
783 inst
->saturate
= instr
->dest
.saturate
;
785 case nir_op_fddy_coarse
:
786 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
787 inst
->saturate
= instr
->dest
.saturate
;
792 inst
= bld
.ADD(result
, op
[0], op
[1]);
793 inst
->saturate
= instr
->dest
.saturate
;
797 inst
= bld
.MUL(result
, op
[0], op
[1]);
798 inst
->saturate
= instr
->dest
.saturate
;
802 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
803 bld
.MUL(result
, op
[0], op
[1]);
806 case nir_op_imul_high
:
807 case nir_op_umul_high
:
808 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
809 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
814 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
815 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
818 case nir_op_uadd_carry
:
819 unreachable("Should have been lowered by carry_to_arith().");
821 case nir_op_usub_borrow
:
822 unreachable("Should have been lowered by borrow_to_arith().");
826 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
827 * appears that our hardware just does the right thing for signed
830 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
831 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
835 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
836 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
838 /* Math instructions don't support conditional mod */
839 inst
= bld
.MOV(bld
.null_reg_d(), result
);
840 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
842 /* Now, we need to determine if signs of the sources are different.
843 * When we XOR the sources, the top bit is 0 if they are the same and 1
844 * if they are different. We can then use a conditional modifier to
845 * turn that into a predicate. This leads us to an XOR.l instruction.
847 * Technically, according to the PRM, you're not allowed to use .l on a
848 * XOR instruction. However, emperical experiments and Curro's reading
849 * of the simulator source both indicate that it's safe.
851 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
852 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
853 inst
->predicate
= BRW_PREDICATE_NORMAL
;
854 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
856 /* If the result of the initial remainder operation is non-zero and the
857 * two sources have different signs, add in a copy of op[1] to get the
858 * final integer modulus value.
860 inst
= bld
.ADD(result
, result
, op
[1]);
861 inst
->predicate
= BRW_PREDICATE_NORMAL
;
869 fs_reg dest
= result
;
870 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
871 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
873 brw_conditional_mod cond
;
876 cond
= BRW_CONDITIONAL_L
;
879 cond
= BRW_CONDITIONAL_GE
;
882 cond
= BRW_CONDITIONAL_Z
;
885 cond
= BRW_CONDITIONAL_NZ
;
888 unreachable("bad opcode");
890 bld
.CMP(dest
, op
[0], op
[1], cond
);
891 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
892 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
903 fs_reg dest
= result
;
904 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
905 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
908 brw_conditional_mod cond
;
912 cond
= BRW_CONDITIONAL_L
;
916 cond
= BRW_CONDITIONAL_GE
;
919 cond
= BRW_CONDITIONAL_Z
;
922 cond
= BRW_CONDITIONAL_NZ
;
925 unreachable("bad opcode");
927 bld
.CMP(dest
, op
[0], op
[1], cond
);
928 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
929 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
935 if (devinfo
->gen
>= 8) {
936 op
[0] = resolve_source_modifiers(op
[0]);
938 bld
.NOT(result
, op
[0]);
941 if (devinfo
->gen
>= 8) {
942 op
[0] = resolve_source_modifiers(op
[0]);
943 op
[1] = resolve_source_modifiers(op
[1]);
945 bld
.XOR(result
, op
[0], op
[1]);
948 if (devinfo
->gen
>= 8) {
949 op
[0] = resolve_source_modifiers(op
[0]);
950 op
[1] = resolve_source_modifiers(op
[1]);
952 bld
.OR(result
, op
[0], op
[1]);
955 if (devinfo
->gen
>= 8) {
956 op
[0] = resolve_source_modifiers(op
[0]);
957 op
[1] = resolve_source_modifiers(op
[1]);
959 bld
.AND(result
, op
[0], op
[1]);
965 case nir_op_ball_fequal2
:
966 case nir_op_ball_iequal2
:
967 case nir_op_ball_fequal3
:
968 case nir_op_ball_iequal3
:
969 case nir_op_ball_fequal4
:
970 case nir_op_ball_iequal4
:
971 case nir_op_bany_fnequal2
:
972 case nir_op_bany_inequal2
:
973 case nir_op_bany_fnequal3
:
974 case nir_op_bany_inequal3
:
975 case nir_op_bany_fnequal4
:
976 case nir_op_bany_inequal4
:
977 unreachable("Lowered by nir_lower_alu_reductions");
979 case nir_op_fnoise1_1
:
980 case nir_op_fnoise1_2
:
981 case nir_op_fnoise1_3
:
982 case nir_op_fnoise1_4
:
983 case nir_op_fnoise2_1
:
984 case nir_op_fnoise2_2
:
985 case nir_op_fnoise2_3
:
986 case nir_op_fnoise2_4
:
987 case nir_op_fnoise3_1
:
988 case nir_op_fnoise3_2
:
989 case nir_op_fnoise3_3
:
990 case nir_op_fnoise3_4
:
991 case nir_op_fnoise4_1
:
992 case nir_op_fnoise4_2
:
993 case nir_op_fnoise4_3
:
994 case nir_op_fnoise4_4
:
995 unreachable("not reached: should be handled by lower_noise");
998 unreachable("not reached: should be handled by ldexp_to_arith()");
1001 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1002 inst
->saturate
= instr
->dest
.saturate
;
1006 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1007 inst
->saturate
= instr
->dest
.saturate
;
1012 bld
.MOV(result
, negate(op
[0]));
1017 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1018 /* two-argument instructions can't take 64-bit immediates */
1022 if (instr
->op
== nir_op_f2b
) {
1023 zero
= vgrf(glsl_type::double_type
);
1024 tmp
= vgrf(glsl_type::double_type
);
1026 zero
= vgrf(glsl_type::int64_t_type
);
1027 tmp
= vgrf(glsl_type::int64_t_type
);
1030 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1031 /* A SIMD16 execution needs to be split in two instructions, so use
1032 * a vgrf instead of the flag register as dst so instruction splitting
1035 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1036 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1038 if (instr
->op
== nir_op_f2b
) {
1039 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1041 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1047 inst
= bld
.RNDZ(result
, op
[0]);
1048 inst
->saturate
= instr
->dest
.saturate
;
1051 case nir_op_fceil
: {
1052 op
[0].negate
= !op
[0].negate
;
1053 fs_reg temp
= vgrf(glsl_type::float_type
);
1054 bld
.RNDD(temp
, op
[0]);
1056 inst
= bld
.MOV(result
, temp
);
1057 inst
->saturate
= instr
->dest
.saturate
;
1061 inst
= bld
.RNDD(result
, op
[0]);
1062 inst
->saturate
= instr
->dest
.saturate
;
1065 inst
= bld
.FRC(result
, op
[0]);
1066 inst
->saturate
= instr
->dest
.saturate
;
1068 case nir_op_fround_even
:
1069 inst
= bld
.RNDE(result
, op
[0]);
1070 inst
->saturate
= instr
->dest
.saturate
;
1073 case nir_op_fquantize2f16
: {
1074 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1075 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1076 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1078 /* The destination stride must be at least as big as the source stride. */
1079 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1082 /* Check for denormal */
1083 fs_reg abs_src0
= op
[0];
1084 abs_src0
.abs
= true;
1085 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1087 /* Get the appropriately signed zero */
1088 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1089 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1090 brw_imm_ud(0x80000000));
1091 /* Do the actual F32 -> F16 -> F32 conversion */
1092 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1093 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1094 /* Select that or zero based on normal status */
1095 inst
= bld
.SEL(result
, zero
, tmp32
);
1096 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1097 inst
->saturate
= instr
->dest
.saturate
;
1104 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1105 inst
->saturate
= instr
->dest
.saturate
;
1111 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1112 inst
->saturate
= instr
->dest
.saturate
;
1115 case nir_op_pack_snorm_2x16
:
1116 case nir_op_pack_snorm_4x8
:
1117 case nir_op_pack_unorm_2x16
:
1118 case nir_op_pack_unorm_4x8
:
1119 case nir_op_unpack_snorm_2x16
:
1120 case nir_op_unpack_snorm_4x8
:
1121 case nir_op_unpack_unorm_2x16
:
1122 case nir_op_unpack_unorm_4x8
:
1123 case nir_op_unpack_half_2x16
:
1124 case nir_op_pack_half_2x16
:
1125 unreachable("not reached: should be handled by lower_packing_builtins");
1127 case nir_op_unpack_half_2x16_split_x
:
1128 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1129 inst
->saturate
= instr
->dest
.saturate
;
1131 case nir_op_unpack_half_2x16_split_y
:
1132 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1133 inst
->saturate
= instr
->dest
.saturate
;
1136 case nir_op_pack_64_2x32_split
:
1137 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1140 case nir_op_unpack_64_2x32_split_x
:
1141 case nir_op_unpack_64_2x32_split_y
: {
1142 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1143 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1145 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1150 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1151 inst
->saturate
= instr
->dest
.saturate
;
1154 case nir_op_bitfield_reverse
:
1155 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1156 bld
.BFREV(result
, op
[0]);
1159 case nir_op_bit_count
:
1160 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1161 bld
.CBIT(result
, op
[0]);
1164 case nir_op_ufind_msb
: {
1165 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1166 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1170 case nir_op_ifind_msb
: {
1171 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1173 if (devinfo
->gen
< 7) {
1174 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1176 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1178 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1179 * count from the LSB side. If FBH didn't return an error
1180 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1181 * count into an LSB count.
1183 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1185 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1186 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1187 inst
->src
[0].negate
= true;
1192 case nir_op_find_lsb
:
1193 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1195 if (devinfo
->gen
< 7) {
1196 fs_reg temp
= vgrf(glsl_type::int_type
);
1198 /* (x & -x) generates a value that consists of only the LSB of x.
1199 * For all powers of 2, findMSB(y) == findLSB(y).
1201 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1202 fs_reg negated_src
= src
;
1204 /* One must be negated, and the other must be non-negated. It
1205 * doesn't matter which is which.
1207 negated_src
.negate
= true;
1210 bld
.AND(temp
, src
, negated_src
);
1211 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1213 bld
.FBL(result
, op
[0]);
1217 case nir_op_ubitfield_extract
:
1218 case nir_op_ibitfield_extract
:
1219 unreachable("should have been lowered");
1222 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1223 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1226 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1227 bld
.BFI1(result
, op
[0], op
[1]);
1230 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1231 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1234 case nir_op_bitfield_insert
:
1235 unreachable("not reached: should have been lowered");
1240 fs_reg shift_count
= op
[1];
1242 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1243 if (op
[1].file
== VGRF
&&
1244 (result
.type
== BRW_REGISTER_TYPE_Q
||
1245 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1246 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1247 BRW_REGISTER_TYPE_UD
);
1248 shift_count
.stride
= 2;
1249 bld
.MOV(shift_count
, op
[1]);
1253 switch (instr
->op
) {
1255 bld
.SHL(result
, op
[0], shift_count
);
1258 bld
.ASR(result
, op
[0], shift_count
);
1261 bld
.SHR(result
, op
[0], shift_count
);
1264 unreachable("not reached");
1269 case nir_op_pack_half_2x16_split
:
1270 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1274 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1275 inst
->saturate
= instr
->dest
.saturate
;
1279 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1280 inst
->saturate
= instr
->dest
.saturate
;
1284 if (optimize_frontfacing_ternary(instr
, result
))
1287 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1288 inst
= bld
.SEL(result
, op
[1], op
[2]);
1289 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1292 case nir_op_extract_u8
:
1293 case nir_op_extract_i8
: {
1294 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1295 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1296 assert(byte
!= NULL
);
1297 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1301 case nir_op_extract_u16
:
1302 case nir_op_extract_i16
: {
1303 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1304 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1305 assert(word
!= NULL
);
1306 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1311 unreachable("unhandled instruction");
1314 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1315 * to sign extend the low bit to 0/~0
1317 if (devinfo
->gen
<= 5 &&
1318 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1319 fs_reg masked
= vgrf(glsl_type::int_type
);
1320 bld
.AND(masked
, result
, brw_imm_d(1));
1321 masked
.negate
= true;
1322 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1327 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1328 nir_load_const_instr
*instr
)
1330 const brw_reg_type reg_type
=
1331 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1332 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1334 switch (instr
->def
.bit_size
) {
1336 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1337 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1341 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1342 bld
.MOV(offset(reg
, bld
, i
),
1343 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1347 unreachable("Invalid bit size");
1350 nir_ssa_values
[instr
->def
.index
] = reg
;
1354 fs_visitor::get_nir_src(const nir_src
&src
)
1358 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1359 const brw_reg_type reg_type
= src
.ssa
->bit_size
== 32 ?
1360 BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1361 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1363 reg
= nir_ssa_values
[src
.ssa
->index
];
1366 /* We don't handle indirects on locals */
1367 assert(src
.reg
.indirect
== NULL
);
1368 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1369 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1372 /* to avoid floating-point denorm flushing problems, set the type by
1373 * default to D - instructions that need floating point semantics will set
1374 * this to F if they need to
1376 return retype(reg
, BRW_REGISTER_TYPE_D
);
1380 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1383 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1385 nir_const_value
*val
= nir_src_as_const_value(src
);
1386 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1390 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1393 const brw_reg_type reg_type
=
1394 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1395 nir_ssa_values
[dest
.ssa
.index
] =
1396 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1397 return nir_ssa_values
[dest
.ssa
.index
];
1399 /* We don't handle indirects on locals */
1400 assert(dest
.reg
.indirect
== NULL
);
1401 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1402 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1407 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1409 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1410 BRW_REGISTER_TYPE_UD
);
1412 unsigned indirect_max
= 0;
1414 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1415 tail
= tail
->child
) {
1416 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1417 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1418 const unsigned size
= glsl_get_length(tail
->type
);
1419 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1420 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1421 image
= offset(image
, bld
, base
* element_size
);
1423 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1424 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1426 /* Accessing an invalid surface index with the dataport can result
1427 * in a hang. According to the spec "if the index used to
1428 * select an individual element is negative or greater than or
1429 * equal to the size of the array, the results of the operation
1430 * are undefined but may not lead to termination" -- which is one
1431 * of the possible outcomes of the hang. Clamp the index to
1432 * prevent access outside of the array bounds.
1434 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1435 BRW_REGISTER_TYPE_UD
),
1436 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1438 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1440 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1441 if (indirect
.file
== BAD_FILE
) {
1444 bld
.ADD(indirect
, indirect
, tmp
);
1449 if (indirect
.file
== BAD_FILE
) {
1452 /* Emit a pile of MOVs to load the uniform into a temporary. The
1453 * dead-code elimination pass will get rid of what we don't use.
1455 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1456 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1457 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1458 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1459 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1466 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1469 for (unsigned i
= 0; i
< 4; i
++) {
1470 if (!((wr_mask
>> i
) & 1))
1473 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1474 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1475 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1476 if (new_inst
->src
[j
].file
== VGRF
)
1477 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1484 * Get the matching channel register datatype for an image intrinsic of the
1485 * specified GLSL image type.
1488 get_image_base_type(const glsl_type
*type
)
1490 switch ((glsl_base_type
)type
->sampled_type
) {
1491 case GLSL_TYPE_UINT
:
1492 return BRW_REGISTER_TYPE_UD
;
1494 return BRW_REGISTER_TYPE_D
;
1495 case GLSL_TYPE_FLOAT
:
1496 return BRW_REGISTER_TYPE_F
;
1498 unreachable("Not reached.");
1503 * Get the appropriate atomic op for an image atomic intrinsic.
1506 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1509 case nir_intrinsic_image_atomic_add
:
1511 case nir_intrinsic_image_atomic_min
:
1512 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1513 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1514 case nir_intrinsic_image_atomic_max
:
1515 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1516 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1517 case nir_intrinsic_image_atomic_and
:
1519 case nir_intrinsic_image_atomic_or
:
1521 case nir_intrinsic_image_atomic_xor
:
1523 case nir_intrinsic_image_atomic_exchange
:
1525 case nir_intrinsic_image_atomic_comp_swap
:
1526 return BRW_AOP_CMPWR
;
1528 unreachable("Not reachable.");
1533 emit_pixel_interpolater_send(const fs_builder
&bld
,
1538 glsl_interp_mode interpolation
)
1540 struct brw_wm_prog_data
*wm_prog_data
=
1541 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1546 if (src
.file
== BAD_FILE
) {
1548 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1552 mlen
= 2 * bld
.dispatch_width() / 8;
1555 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1557 /* 2 floats per slot returned */
1558 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1559 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1561 wm_prog_data
->pulls_bary
= true;
1567 * Computes 1 << x, given a D/UD register containing some value x.
1570 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1572 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1574 fs_reg result
= bld
.vgrf(x
.type
, 1);
1575 fs_reg one
= bld
.vgrf(x
.type
, 1);
1577 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1578 bld
.SHL(result
, one
, x
);
1583 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1585 assert(stage
== MESA_SHADER_GEOMETRY
);
1587 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1589 if (gs_compile
->control_data_header_size_bits
== 0)
1592 /* We can only do EndPrimitive() functionality when the control data
1593 * consists of cut bits. Fortunately, the only time it isn't is when the
1594 * output type is points, in which case EndPrimitive() is a no-op.
1596 if (gs_prog_data
->control_data_format
!=
1597 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1601 /* Cut bits use one bit per vertex. */
1602 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1604 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1605 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1607 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1608 * vertex n, 0 otherwise. So all we need to do here is mark bit
1609 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1610 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1611 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1613 * Note that if EndPrimitive() is called before emitting any vertices, this
1614 * will cause us to set bit 31 of the control_data_bits register to 1.
1615 * That's fine because:
1617 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1618 * output, so the hardware will ignore cut bit 31.
1620 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1621 * last vertex, so setting cut bit 31 has no effect (since the primitive
1622 * is automatically ended when the GS terminates).
1624 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1625 * control_data_bits register to 0 when the first vertex is emitted.
1628 const fs_builder abld
= bld
.annotate("end primitive");
1630 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1631 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1632 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1633 fs_reg mask
= intexp2(abld
, prev_count
);
1634 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1635 * attention to the lower 5 bits of its second source argument, so on this
1636 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1637 * ((vertex_count - 1) % 32).
1639 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1643 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1645 assert(stage
== MESA_SHADER_GEOMETRY
);
1646 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1648 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1650 const fs_builder abld
= bld
.annotate("emit control data bits");
1651 const fs_builder fwa_bld
= bld
.exec_all();
1653 /* We use a single UD register to accumulate control data bits (32 bits
1654 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1657 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1658 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1659 * use the Channel Mask phase to enable/disable which DWord within that
1660 * group to write. (Remember, different SIMD8 channels may have emitted
1661 * different numbers of vertices, so we may need per-slot offsets.)
1663 * Channel masking presents an annoying problem: we may have to replicate
1664 * the data up to 4 times:
1666 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1668 * To avoid penalizing shaders that emit a small number of vertices, we
1669 * can avoid these sometimes: if the size of the control data header is
1670 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1671 * land in the same 128-bit group, so we can skip per-slot offsets.
1673 * Similarly, if the control data header is <= 32 bits, there is only one
1674 * DWord, so we can skip channel masks.
1676 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1678 fs_reg channel_mask
, per_slot_offset
;
1680 if (gs_compile
->control_data_header_size_bits
> 32) {
1681 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1682 channel_mask
= vgrf(glsl_type::uint_type
);
1685 if (gs_compile
->control_data_header_size_bits
> 128) {
1686 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1687 per_slot_offset
= vgrf(glsl_type::uint_type
);
1690 /* Figure out which DWord we're trying to write to using the formula:
1692 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1694 * Since bits_per_vertex is a power of two, and is known at compile
1695 * time, this can be optimized to:
1697 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1699 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1700 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1701 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1702 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1703 unsigned log2_bits_per_vertex
=
1704 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1705 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1707 if (per_slot_offset
.file
!= BAD_FILE
) {
1708 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1709 * the appropriate OWord within the control data header.
1711 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1714 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1715 * write to the appropriate DWORD within the OWORD.
1717 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1718 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1719 channel_mask
= intexp2(fwa_bld
, channel
);
1720 /* Then the channel masks need to be in bits 23:16. */
1721 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1724 /* Store the control data bits in the message payload and send it. */
1726 if (channel_mask
.file
!= BAD_FILE
)
1727 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1728 if (per_slot_offset
.file
!= BAD_FILE
)
1731 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1732 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1734 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1735 if (per_slot_offset
.file
!= BAD_FILE
)
1736 sources
[i
++] = per_slot_offset
;
1737 if (channel_mask
.file
!= BAD_FILE
)
1738 sources
[i
++] = channel_mask
;
1740 sources
[i
++] = this->control_data_bits
;
1743 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1744 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1746 /* We need to increment Global Offset by 256-bits to make room for
1747 * Broadwell's extra "Vertex Count" payload at the beginning of the
1748 * URB entry. Since this is an OWord message, Global Offset is counted
1749 * in 128-bit units, so we must set it to 2.
1751 if (gs_prog_data
->static_vertex_count
== -1)
1756 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1759 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1761 /* Note: we are calling this *before* increasing vertex_count, so
1762 * this->vertex_count == vertex_count - 1 in the formula above.
1765 /* Stream mode uses 2 bits per vertex */
1766 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1768 /* Must be a valid stream */
1769 assert(stream_id
< MAX_VERTEX_STREAMS
);
1771 /* Control data bits are initialized to 0 so we don't have to set any
1772 * bits when sending vertices to stream 0.
1777 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1779 /* reg::sid = stream_id */
1780 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1781 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1783 /* reg:shift_count = 2 * (vertex_count - 1) */
1784 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1785 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1787 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1788 * attention to the lower 5 bits of its second source argument, so on this
1789 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1790 * stream_id << ((2 * (vertex_count - 1)) % 32).
1792 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1793 abld
.SHL(mask
, sid
, shift_count
);
1794 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1798 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1801 assert(stage
== MESA_SHADER_GEOMETRY
);
1803 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1805 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1806 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1808 /* Haswell and later hardware ignores the "Render Stream Select" bits
1809 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1810 * and instead sends all primitives down the pipeline for rasterization.
1811 * If the SOL stage is enabled, "Render Stream Select" is honored and
1812 * primitives bound to non-zero streams are discarded after stream output.
1814 * Since the only purpose of primives sent to non-zero streams is to
1815 * be recorded by transform feedback, we can simply discard all geometry
1816 * bound to these streams when transform feedback is disabled.
1818 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1821 /* If we're outputting 32 control data bits or less, then we can wait
1822 * until the shader is over to output them all. Otherwise we need to
1823 * output them as we go. Now is the time to do it, since we're about to
1824 * output the vertex_count'th vertex, so it's guaranteed that the
1825 * control data bits associated with the (vertex_count - 1)th vertex are
1828 if (gs_compile
->control_data_header_size_bits
> 32) {
1829 const fs_builder abld
=
1830 bld
.annotate("emit vertex: emit control data bits");
1832 /* Only emit control data bits if we've finished accumulating a batch
1833 * of 32 bits. This is the case when:
1835 * (vertex_count * bits_per_vertex) % 32 == 0
1837 * (in other words, when the last 5 bits of vertex_count *
1838 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1839 * integer n (which is always the case, since bits_per_vertex is
1840 * always 1 or 2), this is equivalent to requiring that the last 5-n
1841 * bits of vertex_count are 0:
1843 * vertex_count & (2^(5-n) - 1) == 0
1845 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1848 * vertex_count & (32 / bits_per_vertex - 1) == 0
1850 * TODO: If vertex_count is an immediate, we could do some of this math
1851 * at compile time...
1854 abld
.AND(bld
.null_reg_d(), vertex_count
,
1855 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1856 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1858 abld
.IF(BRW_PREDICATE_NORMAL
);
1859 /* If vertex_count is 0, then no control data bits have been
1860 * accumulated yet, so we can skip emitting them.
1862 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1863 BRW_CONDITIONAL_NEQ
);
1864 abld
.IF(BRW_PREDICATE_NORMAL
);
1865 emit_gs_control_data_bits(vertex_count
);
1866 abld
.emit(BRW_OPCODE_ENDIF
);
1868 /* Reset control_data_bits to 0 so we can start accumulating a new
1871 * Note: in the case where vertex_count == 0, this neutralizes the
1872 * effect of any call to EndPrimitive() that the shader may have
1873 * made before outputting its first vertex.
1875 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1876 inst
->force_writemask_all
= true;
1877 abld
.emit(BRW_OPCODE_ENDIF
);
1880 emit_urb_writes(vertex_count
);
1882 /* In stream mode we have to set control data bits for all vertices
1883 * unless we have disabled control data bits completely (which we do
1884 * do for GL_POINTS outputs that don't use streams).
1886 if (gs_compile
->control_data_header_size_bits
> 0 &&
1887 gs_prog_data
->control_data_format
==
1888 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1889 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1894 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1895 const nir_src
&vertex_src
,
1896 unsigned base_offset
,
1897 const nir_src
&offset_src
,
1898 unsigned num_components
,
1899 unsigned first_component
)
1901 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1903 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1904 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1905 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1907 /* TODO: figure out push input layout for invocations == 1 */
1908 /* TODO: make this work with 64-bit inputs */
1909 if (gs_prog_data
->invocations
== 1 &&
1910 type_sz(dst
.type
) <= 4 &&
1911 offset_const
!= NULL
&& vertex_const
!= NULL
&&
1912 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1913 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1914 vertex_const
->u32
[0] * push_reg_count
;
1915 for (unsigned i
= 0; i
< num_components
; i
++) {
1916 bld
.MOV(offset(dst
, bld
, i
),
1917 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
1922 /* Resort to the pull model. Ensure the VUE handles are provided. */
1923 assert(gs_prog_data
->base
.include_vue_handles
);
1925 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1926 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1928 if (gs_prog_data
->invocations
== 1) {
1930 /* The vertex index is constant; just select the proper URB handle. */
1932 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
1933 BRW_REGISTER_TYPE_UD
);
1935 /* The vertex index is non-constant. We need to use indirect
1936 * addressing to fetch the proper URB handle.
1938 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1939 * indicating that channel <n> should read the handle from
1940 * DWord <n>. We convert that to bytes by multiplying by 4.
1942 * Next, we convert the vertex index to bytes by multiplying
1943 * by 32 (shifting by 5), and add the two together. This is
1944 * the final indirect byte offset.
1946 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1947 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1948 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1949 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1951 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1952 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1953 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1954 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1955 /* Convert vertex_index to bytes (multiply by 32) */
1956 bld
.SHL(vertex_offset_bytes
,
1957 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1959 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1961 /* Use first_icp_handle as the base offset. There is one register
1962 * of URB handles per vertex, so inform the register allocator that
1963 * we might read up to nir->info.gs.vertices_in registers.
1965 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1966 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
1967 fs_reg(icp_offset_bytes
),
1968 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1971 assert(gs_prog_data
->invocations
> 1);
1974 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
1976 retype(brw_vec1_grf(first_icp_handle
+
1977 vertex_const
->i32
[0] / 8,
1978 vertex_const
->i32
[0] % 8),
1979 BRW_REGISTER_TYPE_UD
));
1981 /* The vertex index is non-constant. We need to use indirect
1982 * addressing to fetch the proper URB handle.
1985 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1987 /* Convert vertex_index to bytes (multiply by 4) */
1988 bld
.SHL(icp_offset_bytes
,
1989 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1992 /* Use first_icp_handle as the base offset. There is one DWord
1993 * of URB handles per vertex, so inform the register allocator that
1994 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
1996 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1997 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
1998 fs_reg(icp_offset_bytes
),
1999 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2006 fs_reg tmp_dst
= dst
;
2007 fs_reg indirect_offset
= get_nir_src(offset_src
);
2008 unsigned num_iterations
= 1;
2009 unsigned orig_num_components
= num_components
;
2011 if (type_sz(dst
.type
) == 8) {
2012 if (num_components
> 2) {
2016 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2018 first_component
= first_component
/ 2;
2021 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2023 /* Constant indexing - use global offset. */
2024 if (first_component
!= 0) {
2025 unsigned read_components
= num_components
+ first_component
;
2026 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2027 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2028 inst
->size_written
= read_components
*
2029 tmp
.component_size(inst
->exec_size
);
2030 for (unsigned i
= 0; i
< num_components
; i
++) {
2031 bld
.MOV(offset(tmp_dst
, bld
, i
),
2032 offset(tmp
, bld
, i
+ first_component
));
2035 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2037 inst
->size_written
= num_components
*
2038 tmp_dst
.component_size(inst
->exec_size
);
2040 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2043 /* Indirect indexing - use per-slot offsets as well. */
2044 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2045 unsigned read_components
= num_components
+ first_component
;
2046 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2047 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2048 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2049 if (first_component
!= 0) {
2050 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2052 inst
->size_written
= read_components
*
2053 tmp
.component_size(inst
->exec_size
);
2054 for (unsigned i
= 0; i
< num_components
; i
++) {
2055 bld
.MOV(offset(tmp_dst
, bld
, i
),
2056 offset(tmp
, bld
, i
+ first_component
));
2059 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2061 inst
->size_written
= num_components
*
2062 tmp_dst
.component_size(inst
->exec_size
);
2064 inst
->offset
= base_offset
;
2068 if (type_sz(dst
.type
) == 8) {
2069 shuffle_32bit_load_result_to_64bit_data(
2070 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2072 for (unsigned c
= 0; c
< num_components
; c
++)
2073 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2076 if (num_iterations
> 1) {
2077 num_components
= orig_num_components
- 2;
2081 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2082 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2083 indirect_offset
= new_indirect
;
2090 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2092 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2093 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2096 /* The only constant offset we should find is 0. brw_nir.c's
2097 * add_const_offset_to_base() will fold other constant offsets
2098 * into instr->const_index[0].
2100 assert(const_value
->u32
[0] == 0);
2104 return get_nir_src(*offset_src
);
2108 do_untyped_vector_read(const fs_builder
&bld
,
2110 const fs_reg surf_index
,
2111 const fs_reg offset_reg
,
2112 unsigned num_components
)
2114 if (type_sz(dest
.type
) == 4) {
2115 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2118 BRW_PREDICATE_NONE
);
2119 read_result
.type
= dest
.type
;
2120 for (unsigned i
= 0; i
< num_components
; i
++)
2121 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2122 } else if (type_sz(dest
.type
) == 8) {
2123 /* Reading a dvec, so we need to:
2125 * 1. Multiply num_components by 2, to account for the fact that we
2126 * need to read 64-bit components.
2127 * 2. Shuffle the result of the load to form valid 64-bit elements
2128 * 3. Emit a second load (for components z/w) if needed.
2130 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2131 bld
.MOV(read_offset
, offset_reg
);
2133 int iters
= num_components
<= 2 ? 1 : 2;
2135 /* Load the dvec, the first iteration loads components x/y, the second
2136 * iteration, if needed, loads components z/w
2138 for (int it
= 0; it
< iters
; it
++) {
2139 /* Compute number of components to read in this iteration */
2140 int iter_components
= MIN2(2, num_components
);
2141 num_components
-= iter_components
;
2143 /* Read. Since this message reads 32-bit components, we need to
2144 * read twice as many components.
2146 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2148 iter_components
* 2,
2149 BRW_PREDICATE_NONE
);
2151 /* Shuffle the 32-bit load result into valid 64-bit data */
2152 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2153 shuffle_32bit_load_result_to_64bit_data(
2154 bld
, packed_result
, read_result
, iter_components
);
2156 /* Move each component to its destination */
2157 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2158 for (int c
= 0; c
< iter_components
; c
++) {
2159 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2160 offset(packed_result
, bld
, c
));
2163 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2166 unreachable("Unsupported type");
2171 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2172 nir_intrinsic_instr
*instr
)
2174 assert(stage
== MESA_SHADER_VERTEX
);
2177 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2178 dest
= get_nir_dest(instr
->dest
);
2180 switch (instr
->intrinsic
) {
2181 case nir_intrinsic_load_vertex_id
:
2182 unreachable("should be lowered by lower_vertex_id()");
2184 case nir_intrinsic_load_vertex_id_zero_base
:
2185 case nir_intrinsic_load_base_vertex
:
2186 case nir_intrinsic_load_instance_id
:
2187 case nir_intrinsic_load_base_instance
:
2188 case nir_intrinsic_load_draw_id
: {
2189 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2190 fs_reg val
= nir_system_values
[sv
];
2191 assert(val
.file
!= BAD_FILE
);
2192 dest
.type
= val
.type
;
2197 case nir_intrinsic_load_input
: {
2198 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2199 unsigned first_component
= nir_intrinsic_component(instr
);
2200 unsigned num_components
= instr
->num_components
;
2201 enum brw_reg_type type
= dest
.type
;
2203 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2204 assert(const_offset
&& "Indirect input loads not allowed");
2205 src
= offset(src
, bld
, const_offset
->u32
[0]);
2207 for (unsigned j
= 0; j
< num_components
; j
++) {
2208 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2211 if (type
== BRW_REGISTER_TYPE_DF
) {
2212 /* Once the double vector is read, set again its original register
2213 * type to continue with normal execution.
2215 src
= retype(src
, type
);
2216 dest
= retype(dest
, type
);
2219 if (type_sz(src
.type
) == 8) {
2220 shuffle_32bit_load_result_to_64bit_data(bld
,
2222 retype(dest
, BRW_REGISTER_TYPE_F
),
2223 instr
->num_components
);
2229 nir_emit_intrinsic(bld
, instr
);
2235 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2236 nir_intrinsic_instr
*instr
)
2238 assert(stage
== MESA_SHADER_TESS_CTRL
);
2239 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2240 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2243 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2244 dst
= get_nir_dest(instr
->dest
);
2246 switch (instr
->intrinsic
) {
2247 case nir_intrinsic_load_primitive_id
:
2248 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2250 case nir_intrinsic_load_invocation_id
:
2251 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2253 case nir_intrinsic_load_patch_vertices_in
:
2254 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2255 brw_imm_d(tcs_key
->input_vertices
));
2258 case nir_intrinsic_barrier
: {
2259 if (tcs_prog_data
->instances
== 1)
2262 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2263 fs_reg m0_2
= component(m0
, 2);
2265 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2267 /* Zero the message header */
2268 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2270 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2271 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2272 brw_imm_ud(INTEL_MASK(16, 13)));
2274 /* Shift it up to bits 27:24. */
2275 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2277 /* Set the Barrier Count and the enable bit */
2278 chanbld
.OR(m0_2
, m0_2
,
2279 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2281 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2285 case nir_intrinsic_load_input
:
2286 unreachable("nir_lower_io should never give us these.");
2289 case nir_intrinsic_load_per_vertex_input
: {
2290 fs_reg indirect_offset
= get_indirect_offset(instr
);
2291 unsigned imm_offset
= instr
->const_index
[0];
2293 const nir_src
&vertex_src
= instr
->src
[0];
2294 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2301 /* Emit a MOV to resolve <0,1,0> regioning. */
2302 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2304 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2305 vertex_const
->i32
[0] & 7),
2306 BRW_REGISTER_TYPE_UD
));
2307 } else if (tcs_prog_data
->instances
== 1 &&
2308 vertex_src
.is_ssa
&&
2309 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2310 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2311 /* For the common case of only 1 instance, an array index of
2312 * gl_InvocationID means reading g1. Skip all the indirect work.
2314 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2316 /* The vertex index is non-constant. We need to use indirect
2317 * addressing to fetch the proper URB handle.
2319 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2321 /* Each ICP handle is a single DWord (4 bytes) */
2322 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2323 bld
.SHL(vertex_offset_bytes
,
2324 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2327 /* Start at g1. We might read up to 4 registers. */
2328 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2329 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2330 brw_imm_ud(4 * REG_SIZE
));
2333 /* We can only read two double components with each URB read, so
2334 * we send two read messages in that case, each one loading up to
2335 * two double components.
2337 unsigned num_iterations
= 1;
2338 unsigned num_components
= instr
->num_components
;
2339 unsigned first_component
= nir_intrinsic_component(instr
);
2340 fs_reg orig_dst
= dst
;
2341 if (type_sz(dst
.type
) == 8) {
2342 first_component
= first_component
/ 2;
2343 if (instr
->num_components
> 2) {
2348 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2352 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2353 if (indirect_offset
.file
== BAD_FILE
) {
2354 /* Constant indexing - use global offset. */
2355 if (first_component
!= 0) {
2356 unsigned read_components
= num_components
+ first_component
;
2357 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2358 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2359 for (unsigned i
= 0; i
< num_components
; i
++) {
2360 bld
.MOV(offset(dst
, bld
, i
),
2361 offset(tmp
, bld
, i
+ first_component
));
2364 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2366 inst
->offset
= imm_offset
;
2369 /* Indirect indexing - use per-slot offsets as well. */
2370 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2371 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2372 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2373 if (first_component
!= 0) {
2374 unsigned read_components
= num_components
+ first_component
;
2375 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2376 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2378 for (unsigned i
= 0; i
< num_components
; i
++) {
2379 bld
.MOV(offset(dst
, bld
, i
),
2380 offset(tmp
, bld
, i
+ first_component
));
2383 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2386 inst
->offset
= imm_offset
;
2389 inst
->size_written
= (num_components
+ first_component
) *
2390 inst
->dst
.component_size(inst
->exec_size
);
2392 /* If we are reading 64-bit data using 32-bit read messages we need
2393 * build proper 64-bit data elements by shuffling the low and high
2394 * 32-bit components around like we do for other things like UBOs
2397 if (type_sz(dst
.type
) == 8) {
2398 shuffle_32bit_load_result_to_64bit_data(
2399 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2401 for (unsigned c
= 0; c
< num_components
; c
++) {
2402 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2403 offset(dst
, bld
, c
));
2407 /* Copy the temporary to the destination to deal with writemasking.
2409 * Also attempt to deal with gl_PointSize being in the .w component.
2411 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2412 assert(type_sz(dst
.type
) < 8);
2413 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2414 inst
->size_written
= 4 * REG_SIZE
;
2415 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2418 /* If we are loading double data and we need a second read message
2419 * adjust the write offset
2421 if (num_iterations
> 1) {
2422 num_components
= instr
->num_components
- 2;
2429 case nir_intrinsic_load_output
:
2430 case nir_intrinsic_load_per_vertex_output
: {
2431 fs_reg indirect_offset
= get_indirect_offset(instr
);
2432 unsigned imm_offset
= instr
->const_index
[0];
2433 unsigned first_component
= nir_intrinsic_component(instr
);
2436 if (indirect_offset
.file
== BAD_FILE
) {
2437 /* Replicate the patch handle to all enabled channels */
2438 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2439 bld
.MOV(patch_handle
,
2440 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2443 if (first_component
!= 0) {
2444 unsigned read_components
=
2445 instr
->num_components
+ first_component
;
2446 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2447 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2449 inst
->size_written
= read_components
* REG_SIZE
;
2450 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2451 bld
.MOV(offset(dst
, bld
, i
),
2452 offset(tmp
, bld
, i
+ first_component
));
2455 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2457 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2459 inst
->offset
= imm_offset
;
2463 /* Indirect indexing - use per-slot offsets as well. */
2464 const fs_reg srcs
[] = {
2465 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2468 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2469 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2470 if (first_component
!= 0) {
2471 unsigned read_components
=
2472 instr
->num_components
+ first_component
;
2473 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2474 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2476 inst
->size_written
= read_components
* REG_SIZE
;
2477 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2478 bld
.MOV(offset(dst
, bld
, i
),
2479 offset(tmp
, bld
, i
+ first_component
));
2482 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2484 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2486 inst
->offset
= imm_offset
;
2492 case nir_intrinsic_store_output
:
2493 case nir_intrinsic_store_per_vertex_output
: {
2494 fs_reg value
= get_nir_src(instr
->src
[0]);
2495 bool is_64bit
= (instr
->src
[0].is_ssa
?
2496 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2497 fs_reg indirect_offset
= get_indirect_offset(instr
);
2498 unsigned imm_offset
= instr
->const_index
[0];
2499 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2500 unsigned mask
= instr
->const_index
[1];
2501 unsigned header_regs
= 0;
2503 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2505 if (indirect_offset
.file
!= BAD_FILE
) {
2506 srcs
[header_regs
++] = indirect_offset
;
2512 unsigned num_components
= util_last_bit(mask
);
2515 /* We can only pack two 64-bit components in a single message, so send
2516 * 2 messages if we have more components
2518 unsigned num_iterations
= 1;
2519 unsigned iter_components
= num_components
;
2520 unsigned first_component
= nir_intrinsic_component(instr
);
2522 first_component
= first_component
/ 2;
2523 if (instr
->num_components
> 2) {
2525 iter_components
= 2;
2529 /* 64-bit data needs to me shuffled before we can write it to the URB.
2530 * We will use this temporary to shuffle the components in each
2534 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2536 mask
= mask
<< first_component
;
2538 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2539 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2540 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2541 opcode
= indirect_offset
.file
!= BAD_FILE
?
2542 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2543 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2544 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2545 /* Expand the 64-bit mask to 32-bit channels. We only handle
2546 * two channels in each iteration, so we only care about X/Y.
2548 unsigned mask32
= 0;
2549 if (mask
& WRITEMASK_X
)
2550 mask32
|= WRITEMASK_XY
;
2551 if (mask
& WRITEMASK_Y
)
2552 mask32
|= WRITEMASK_ZW
;
2554 /* If the mask does not include any of the channels X or Y there
2555 * is nothing to do in this iteration. Move on to the next couple
2556 * of 64-bit channels.
2564 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2565 opcode
= indirect_offset
.file
!= BAD_FILE
?
2566 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2567 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2569 opcode
= indirect_offset
.file
!= BAD_FILE
?
2570 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2571 SHADER_OPCODE_URB_WRITE_SIMD8
;
2574 for (unsigned i
= 0; i
< iter_components
; i
++) {
2575 if (!(mask
& (1 << (i
+ first_component
))))
2579 srcs
[header_regs
+ i
+ first_component
] =
2580 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2582 /* We need to shuffle the 64-bit data to match the layout
2583 * expected by our 32-bit URB write messages. We use a temporary
2586 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2587 shuffle_64bit_data_for_32bit_write(bld
,
2588 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2589 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2592 /* Now copy the data to the destination */
2593 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2594 unsigned idx
= 2 * i
;
2595 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2596 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2597 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2598 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2599 offset(dest
, bld
, 1);
2604 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2605 (is_64bit
? 2 * first_component
: first_component
);
2607 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2608 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2610 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2611 inst
->offset
= imm_offset
;
2614 /* If this is a 64-bit attribute, select the next two 64-bit channels
2615 * to be handled in the next iteration.
2626 nir_emit_intrinsic(bld
, instr
);
2632 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2633 nir_intrinsic_instr
*instr
)
2635 assert(stage
== MESA_SHADER_TESS_EVAL
);
2636 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2639 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2640 dest
= get_nir_dest(instr
->dest
);
2642 switch (instr
->intrinsic
) {
2643 case nir_intrinsic_load_primitive_id
:
2644 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2646 case nir_intrinsic_load_tess_coord
:
2647 /* gl_TessCoord is part of the payload in g1-3 */
2648 for (unsigned i
= 0; i
< 3; i
++) {
2649 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2653 case nir_intrinsic_load_input
:
2654 case nir_intrinsic_load_per_vertex_input
: {
2655 fs_reg indirect_offset
= get_indirect_offset(instr
);
2656 unsigned imm_offset
= instr
->const_index
[0];
2657 unsigned first_component
= nir_intrinsic_component(instr
);
2659 if (type_sz(dest
.type
) == 8) {
2660 first_component
= first_component
/ 2;
2664 if (indirect_offset
.file
== BAD_FILE
) {
2665 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2666 * which is 16 registers (since each holds 2 vec4 slots).
2668 unsigned slot_count
= 1;
2669 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2672 const unsigned max_push_slots
= 32;
2673 if (imm_offset
+ slot_count
<= max_push_slots
) {
2674 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2675 for (int i
= 0; i
< instr
->num_components
; i
++) {
2676 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2677 i
+ first_component
;
2678 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2681 tes_prog_data
->base
.urb_read_length
=
2682 MAX2(tes_prog_data
->base
.urb_read_length
,
2683 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2685 /* Replicate the patch handle to all enabled channels */
2686 const fs_reg srcs
[] = {
2687 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2689 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2690 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2692 if (first_component
!= 0) {
2693 unsigned read_components
=
2694 instr
->num_components
+ first_component
;
2695 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2696 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2698 inst
->size_written
= read_components
* REG_SIZE
;
2699 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2700 bld
.MOV(offset(dest
, bld
, i
),
2701 offset(tmp
, bld
, i
+ first_component
));
2704 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2706 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2709 inst
->offset
= imm_offset
;
2712 /* Indirect indexing - use per-slot offsets as well. */
2714 /* We can only read two double components with each URB read, so
2715 * we send two read messages in that case, each one loading up to
2716 * two double components.
2718 unsigned num_iterations
= 1;
2719 unsigned num_components
= instr
->num_components
;
2720 fs_reg orig_dest
= dest
;
2721 if (type_sz(dest
.type
) == 8) {
2722 if (instr
->num_components
> 2) {
2726 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2730 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2731 const fs_reg srcs
[] = {
2732 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2735 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2736 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2738 if (first_component
!= 0) {
2739 unsigned read_components
=
2740 num_components
+ first_component
;
2741 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2742 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2744 for (unsigned i
= 0; i
< num_components
; i
++) {
2745 bld
.MOV(offset(dest
, bld
, i
),
2746 offset(tmp
, bld
, i
+ first_component
));
2749 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2753 inst
->offset
= imm_offset
;
2754 inst
->size_written
= (num_components
+ first_component
) *
2755 inst
->dst
.component_size(inst
->exec_size
);
2757 /* If we are reading 64-bit data using 32-bit read messages we need
2758 * build proper 64-bit data elements by shuffling the low and high
2759 * 32-bit components around like we do for other things like UBOs
2762 if (type_sz(dest
.type
) == 8) {
2763 shuffle_32bit_load_result_to_64bit_data(
2764 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2766 for (unsigned c
= 0; c
< num_components
; c
++) {
2767 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2768 offset(dest
, bld
, c
));
2772 /* If we are loading double data and we need a second read message
2775 if (num_iterations
> 1) {
2776 num_components
= instr
->num_components
- 2;
2784 nir_emit_intrinsic(bld
, instr
);
2790 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2791 nir_intrinsic_instr
*instr
)
2793 assert(stage
== MESA_SHADER_GEOMETRY
);
2794 fs_reg indirect_offset
;
2797 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2798 dest
= get_nir_dest(instr
->dest
);
2800 switch (instr
->intrinsic
) {
2801 case nir_intrinsic_load_primitive_id
:
2802 assert(stage
== MESA_SHADER_GEOMETRY
);
2803 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2804 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2805 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2808 case nir_intrinsic_load_input
:
2809 unreachable("load_input intrinsics are invalid for the GS stage");
2811 case nir_intrinsic_load_per_vertex_input
:
2812 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2813 instr
->src
[1], instr
->num_components
,
2814 nir_intrinsic_component(instr
));
2817 case nir_intrinsic_emit_vertex_with_counter
:
2818 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2821 case nir_intrinsic_end_primitive_with_counter
:
2822 emit_gs_end_primitive(instr
->src
[0]);
2825 case nir_intrinsic_set_vertex_count
:
2826 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2829 case nir_intrinsic_load_invocation_id
: {
2830 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2831 assert(val
.file
!= BAD_FILE
);
2832 dest
.type
= val
.type
;
2838 nir_emit_intrinsic(bld
, instr
);
2844 * Fetch the current render target layer index.
2847 fetch_render_target_array_index(const fs_builder
&bld
)
2849 if (bld
.shader
->devinfo
->gen
>= 6) {
2850 /* The render target array index is provided in the thread payload as
2851 * bits 26:16 of r0.0.
2853 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2854 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2858 /* Pre-SNB we only ever render into the first layer of the framebuffer
2859 * since layered rendering is not implemented.
2861 return brw_imm_ud(0);
2866 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2867 * framebuffer at the current fragment coordinates and sample index.
2870 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2873 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2875 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2876 const brw_wm_prog_key
*wm_key
=
2877 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2878 assert(!wm_key
->coherent_fb_fetch
);
2879 const struct brw_wm_prog_data
*wm_prog_data
=
2880 brw_wm_prog_data(stage_prog_data
);
2882 /* Calculate the surface index relative to the start of the texture binding
2883 * table block, since that's what the texturing messages expect.
2885 const unsigned surface
= target
+
2886 wm_prog_data
->binding_table
.render_target_read_start
-
2887 wm_prog_data
->base
.binding_table
.texture_start
;
2889 brw_mark_surface_used(
2890 bld
.shader
->stage_prog_data
,
2891 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2893 /* Calculate the fragment coordinates. */
2894 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2895 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2896 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2897 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2899 /* Calculate the sample index and MCS payload when multisampling. Luckily
2900 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2901 * shouldn't be necessary to recompile based on whether the framebuffer is
2904 if (wm_key
->multisample_fbo
&&
2905 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2906 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2908 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2909 const fs_reg mcs
= wm_key
->multisample_fbo
?
2910 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2912 /* Use either a normal or a CMS texel fetch message depending on whether
2913 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2914 * message just in case the framebuffer uses 16x multisampling, it should
2915 * be equivalent to the normal CMS fetch for lower multisampling modes.
2917 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
2918 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
2919 SHADER_OPCODE_TXF_CMS_LOGICAL
;
2921 /* Emit the instruction. */
2922 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
2924 brw_imm_ud(surface
), brw_imm_ud(0),
2925 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
2926 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
2928 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
2929 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2935 * Actual coherent framebuffer read implemented using the native render target
2936 * read message. Requires SKL+.
2939 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
2941 assert(bld
.shader
->devinfo
->gen
>= 9);
2942 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
2943 inst
->target
= target
;
2944 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
2950 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
2952 if (n
&& regs
[0].file
!= BAD_FILE
) {
2956 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
2958 for (unsigned i
= 0; i
< n
; i
++)
2966 alloc_frag_output(fs_visitor
*v
, unsigned location
)
2968 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
2969 const brw_wm_prog_key
*const key
=
2970 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
2971 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
2972 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
2974 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
2975 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
2977 else if (l
== FRAG_RESULT_COLOR
)
2978 return alloc_temporary(v
->bld
, 4, v
->outputs
,
2979 MAX2(key
->nr_color_regions
, 1));
2981 else if (l
== FRAG_RESULT_DEPTH
)
2982 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
2984 else if (l
== FRAG_RESULT_STENCIL
)
2985 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
2987 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
2988 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
2990 else if (l
>= FRAG_RESULT_DATA0
&&
2991 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
2992 return alloc_temporary(v
->bld
, 4,
2993 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
2996 unreachable("Invalid location");
3000 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3001 nir_intrinsic_instr
*instr
)
3003 assert(stage
== MESA_SHADER_FRAGMENT
);
3006 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3007 dest
= get_nir_dest(instr
->dest
);
3009 switch (instr
->intrinsic
) {
3010 case nir_intrinsic_load_front_face
:
3011 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3012 *emit_frontfacing_interpolation());
3015 case nir_intrinsic_load_sample_pos
: {
3016 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3017 assert(sample_pos
.file
!= BAD_FILE
);
3018 dest
.type
= sample_pos
.type
;
3019 bld
.MOV(dest
, sample_pos
);
3020 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3024 case nir_intrinsic_load_layer_id
:
3025 dest
.type
= BRW_REGISTER_TYPE_UD
;
3026 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3029 case nir_intrinsic_load_helper_invocation
:
3030 case nir_intrinsic_load_sample_mask_in
:
3031 case nir_intrinsic_load_sample_id
: {
3032 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3033 fs_reg val
= nir_system_values
[sv
];
3034 assert(val
.file
!= BAD_FILE
);
3035 dest
.type
= val
.type
;
3040 case nir_intrinsic_store_output
: {
3041 const fs_reg src
= get_nir_src(instr
->src
[0]);
3042 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3043 assert(const_offset
&& "Indirect output stores not allowed");
3044 const unsigned location
= nir_intrinsic_base(instr
) +
3045 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3046 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3049 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3050 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3051 offset(src
, bld
, j
));
3056 case nir_intrinsic_load_output
: {
3057 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3058 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3059 assert(l
>= FRAG_RESULT_DATA0
);
3060 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3061 assert(const_offset
&& "Indirect output loads not allowed");
3062 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3063 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3065 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3066 emit_coherent_fb_read(bld
, tmp
, target
);
3068 emit_non_coherent_fb_read(bld
, tmp
, target
);
3070 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3071 bld
.MOV(offset(dest
, bld
, j
),
3072 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3078 case nir_intrinsic_discard
:
3079 case nir_intrinsic_discard_if
: {
3080 /* We track our discarded pixels in f0.1. By predicating on it, we can
3081 * update just the flag bits that aren't yet discarded. If there's no
3082 * condition, we emit a CMP of g0 != g0, so all currently executing
3083 * channels will get turned off.
3086 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3087 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3088 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3090 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3091 BRW_REGISTER_TYPE_UW
));
3092 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3094 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3095 cmp
->flag_subreg
= 1;
3097 if (devinfo
->gen
>= 6) {
3098 emit_discard_jump();
3103 case nir_intrinsic_load_input
: {
3104 /* load_input is only used for flat inputs */
3105 unsigned base
= nir_intrinsic_base(instr
);
3106 unsigned component
= nir_intrinsic_component(instr
);
3107 unsigned num_components
= instr
->num_components
;
3108 enum brw_reg_type type
= dest
.type
;
3110 /* Special case fields in the VUE header */
3111 if (base
== VARYING_SLOT_LAYER
)
3113 else if (base
== VARYING_SLOT_VIEWPORT
)
3116 if (nir_dest_bit_size(instr
->dest
) == 64) {
3117 /* const_index is in 32-bit type size units that could not be aligned
3118 * with DF. We need to read the double vector as if it was a float
3119 * vector of twice the number of components to fetch the right data.
3121 type
= BRW_REGISTER_TYPE_F
;
3122 num_components
*= 2;
3125 for (unsigned int i
= 0; i
< num_components
; i
++) {
3126 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3127 interp
= suboffset(interp
, 3);
3128 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3129 retype(fs_reg(interp
), type
));
3132 if (nir_dest_bit_size(instr
->dest
) == 64) {
3133 shuffle_32bit_load_result_to_64bit_data(bld
,
3136 instr
->num_components
);
3141 case nir_intrinsic_load_barycentric_pixel
:
3142 case nir_intrinsic_load_barycentric_centroid
:
3143 case nir_intrinsic_load_barycentric_sample
:
3144 /* Do nothing - load_interpolated_input handling will handle it later. */
3147 case nir_intrinsic_load_barycentric_at_sample
: {
3148 const glsl_interp_mode interpolation
=
3149 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3151 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3154 unsigned msg_data
= const_sample
->i32
[0] << 4;
3156 emit_pixel_interpolater_send(bld
,
3157 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3160 brw_imm_ud(msg_data
),
3163 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3164 BRW_REGISTER_TYPE_UD
);
3166 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3167 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3168 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3169 bld
.exec_all().group(1, 0)
3170 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3171 emit_pixel_interpolater_send(bld
,
3172 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3178 /* Make a loop that sends a message to the pixel interpolater
3179 * for the sample number in each live channel. If there are
3180 * multiple channels with the same sample number then these
3181 * will be handled simultaneously with a single interation of
3184 bld
.emit(BRW_OPCODE_DO
);
3186 /* Get the next live sample number into sample_id_reg */
3187 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3189 /* Set the flag register so that we can perform the send
3190 * message on all channels that have the same sample number
3192 bld
.CMP(bld
.null_reg_ud(),
3193 sample_src
, sample_id
,
3194 BRW_CONDITIONAL_EQ
);
3195 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3196 bld
.exec_all().group(1, 0)
3197 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3199 emit_pixel_interpolater_send(bld
,
3200 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3205 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3207 /* Continue the loop if there are any live channels left */
3208 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3210 bld
.emit(BRW_OPCODE_WHILE
));
3216 case nir_intrinsic_load_barycentric_at_offset
: {
3217 const glsl_interp_mode interpolation
=
3218 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3220 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3223 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3224 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3226 emit_pixel_interpolater_send(bld
,
3227 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3230 brw_imm_ud(off_x
| (off_y
<< 4)),
3233 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3234 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3235 BRW_REGISTER_TYPE_F
);
3236 for (int i
= 0; i
< 2; i
++) {
3237 fs_reg temp
= vgrf(glsl_type::float_type
);
3238 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3239 fs_reg itemp
= vgrf(glsl_type::int_type
);
3241 bld
.MOV(itemp
, temp
);
3243 /* Clamp the upper end of the range to +7/16.
3244 * ARB_gpu_shader5 requires that we support a maximum offset
3245 * of +0.5, which isn't representable in a S0.4 value -- if
3246 * we didn't clamp it, we'd end up with -8/16, which is the
3247 * opposite of what the shader author wanted.
3249 * This is legal due to ARB_gpu_shader5's quantization
3252 * "Not all values of <offset> may be supported; x and y
3253 * offsets may be rounded to fixed-point values with the
3254 * number of fraction bits given by the
3255 * implementation-dependent constant
3256 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3258 set_condmod(BRW_CONDITIONAL_L
,
3259 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3262 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3263 emit_pixel_interpolater_send(bld
,
3273 case nir_intrinsic_load_interpolated_input
: {
3274 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3275 emit_fragcoord_interpolation(dest
);
3279 assert(instr
->src
[0].ssa
&&
3280 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3281 nir_intrinsic_instr
*bary_intrinsic
=
3282 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3283 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3284 enum glsl_interp_mode interp_mode
=
3285 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3288 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3289 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3290 /* Use the result of the PI message */
3291 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3293 /* Use the delta_xy values computed from the payload */
3294 enum brw_barycentric_mode bary
=
3295 brw_barycentric_mode(interp_mode
, bary_intrin
);
3297 dst_xy
= this->delta_xy
[bary
];
3300 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3302 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3303 nir_intrinsic_component(instr
) + i
));
3304 interp
.type
= BRW_REGISTER_TYPE_F
;
3305 dest
.type
= BRW_REGISTER_TYPE_F
;
3307 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3308 fs_reg tmp
= vgrf(glsl_type::float_type
);
3309 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3310 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3312 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3319 nir_emit_intrinsic(bld
, instr
);
3325 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3326 nir_intrinsic_instr
*instr
)
3328 assert(stage
== MESA_SHADER_COMPUTE
);
3329 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3332 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3333 dest
= get_nir_dest(instr
->dest
);
3335 switch (instr
->intrinsic
) {
3336 case nir_intrinsic_barrier
:
3338 cs_prog_data
->uses_barrier
= true;
3341 case nir_intrinsic_load_local_invocation_id
:
3342 case nir_intrinsic_load_work_group_id
: {
3343 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3344 fs_reg val
= nir_system_values
[sv
];
3345 assert(val
.file
!= BAD_FILE
);
3346 dest
.type
= val
.type
;
3347 for (unsigned i
= 0; i
< 3; i
++)
3348 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3352 case nir_intrinsic_load_num_work_groups
: {
3353 const unsigned surface
=
3354 cs_prog_data
->binding_table
.work_groups_start
;
3356 cs_prog_data
->uses_num_work_groups
= true;
3358 fs_reg surf_index
= brw_imm_ud(surface
);
3359 brw_mark_surface_used(prog_data
, surface
);
3361 /* Read the 3 GLuint components of gl_NumWorkGroups */
3362 for (unsigned i
= 0; i
< 3; i
++) {
3363 fs_reg read_result
=
3364 emit_untyped_read(bld
, surf_index
,
3366 1 /* dims */, 1 /* size */,
3367 BRW_PREDICATE_NONE
);
3368 read_result
.type
= dest
.type
;
3369 bld
.MOV(dest
, read_result
);
3370 dest
= offset(dest
, bld
, 1);
3375 case nir_intrinsic_shared_atomic_add
:
3376 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3378 case nir_intrinsic_shared_atomic_imin
:
3379 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3381 case nir_intrinsic_shared_atomic_umin
:
3382 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3384 case nir_intrinsic_shared_atomic_imax
:
3385 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3387 case nir_intrinsic_shared_atomic_umax
:
3388 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3390 case nir_intrinsic_shared_atomic_and
:
3391 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3393 case nir_intrinsic_shared_atomic_or
:
3394 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3396 case nir_intrinsic_shared_atomic_xor
:
3397 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3399 case nir_intrinsic_shared_atomic_exchange
:
3400 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3402 case nir_intrinsic_shared_atomic_comp_swap
:
3403 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3406 case nir_intrinsic_load_shared
: {
3407 assert(devinfo
->gen
>= 7);
3409 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3411 /* Get the offset to read from */
3413 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3415 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3417 offset_reg
= vgrf(glsl_type::uint_type
);
3419 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3420 brw_imm_ud(instr
->const_index
[0]));
3423 /* Read the vector */
3424 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3425 instr
->num_components
);
3429 case nir_intrinsic_store_shared
: {
3430 assert(devinfo
->gen
>= 7);
3433 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3436 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3439 unsigned writemask
= instr
->const_index
[1];
3441 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3442 * since the untyped writes below operate in units of 32-bits, which
3443 * means that we need to write twice as many components each time.
3444 * Also, we have to suffle 64-bit data to be in the appropriate layout
3445 * expected by our 32-bit write messages.
3447 unsigned type_size
= 4;
3448 unsigned bit_size
= instr
->src
[0].is_ssa
?
3449 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3450 if (bit_size
== 64) {
3453 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3454 shuffle_64bit_data_for_32bit_write(
3456 retype(tmp
, BRW_REGISTER_TYPE_F
),
3457 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3458 instr
->num_components
);
3462 unsigned type_slots
= type_size
/ 4;
3464 /* Combine groups of consecutive enabled channels in one write
3465 * message. We use ffs to find the first enabled channel and then ffs on
3466 * the bit-inverse, down-shifted writemask to determine the length of
3467 * the block of enabled bits.
3470 unsigned first_component
= ffs(writemask
) - 1;
3471 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3473 /* We can't write more than 2 64-bit components at once. Limit the
3474 * length of the write to what we can do and let the next iteration
3478 length
= MIN2(2, length
);
3481 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3483 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3484 type_size
* first_component
);
3486 offset_reg
= vgrf(glsl_type::uint_type
);
3488 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3489 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3492 emit_untyped_write(bld
, surf_index
, offset_reg
,
3493 offset(val_reg
, bld
, first_component
* type_slots
),
3494 1 /* dims */, length
* type_slots
,
3495 BRW_PREDICATE_NONE
);
3497 /* Clear the bits in the writemask that we just wrote, then try
3498 * again to see if more channels are left.
3500 writemask
&= (15 << (first_component
+ length
));
3507 nir_emit_intrinsic(bld
, instr
);
3513 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3516 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3517 dest
= get_nir_dest(instr
->dest
);
3519 switch (instr
->intrinsic
) {
3520 case nir_intrinsic_atomic_counter_inc
:
3521 case nir_intrinsic_atomic_counter_dec
:
3522 case nir_intrinsic_atomic_counter_read
:
3523 case nir_intrinsic_atomic_counter_add
:
3524 case nir_intrinsic_atomic_counter_min
:
3525 case nir_intrinsic_atomic_counter_max
:
3526 case nir_intrinsic_atomic_counter_and
:
3527 case nir_intrinsic_atomic_counter_or
:
3528 case nir_intrinsic_atomic_counter_xor
:
3529 case nir_intrinsic_atomic_counter_exchange
:
3530 case nir_intrinsic_atomic_counter_comp_swap
: {
3531 if (stage
== MESA_SHADER_FRAGMENT
&&
3532 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3533 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3535 /* Get some metadata from the image intrinsic. */
3536 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3538 /* Get the arguments of the atomic intrinsic. */
3539 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3540 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3541 instr
->const_index
[0]);
3542 const fs_reg src0
= (info
->num_srcs
>= 2
3543 ? get_nir_src(instr
->src
[1]) : fs_reg());
3544 const fs_reg src1
= (info
->num_srcs
>= 3
3545 ? get_nir_src(instr
->src
[2]) : fs_reg());
3548 assert(info
->num_srcs
<= 3);
3550 /* Emit a surface read or atomic op. */
3551 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3552 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3554 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3556 get_atomic_counter_op(instr
->intrinsic
));
3559 /* Assign the result. */
3560 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3562 /* Mark the surface as used. */
3563 brw_mark_surface_used(stage_prog_data
, surface
);
3567 case nir_intrinsic_image_load
:
3568 case nir_intrinsic_image_store
:
3569 case nir_intrinsic_image_atomic_add
:
3570 case nir_intrinsic_image_atomic_min
:
3571 case nir_intrinsic_image_atomic_max
:
3572 case nir_intrinsic_image_atomic_and
:
3573 case nir_intrinsic_image_atomic_or
:
3574 case nir_intrinsic_image_atomic_xor
:
3575 case nir_intrinsic_image_atomic_exchange
:
3576 case nir_intrinsic_image_atomic_comp_swap
: {
3577 using namespace image_access
;
3579 if (stage
== MESA_SHADER_FRAGMENT
&&
3580 instr
->intrinsic
!= nir_intrinsic_image_load
)
3581 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3583 /* Get the referenced image variable and type. */
3584 const nir_variable
*var
= instr
->variables
[0]->var
;
3585 const glsl_type
*type
= var
->type
->without_array();
3586 const brw_reg_type base_type
= get_image_base_type(type
);
3588 /* Get some metadata from the image intrinsic. */
3589 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3590 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3591 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3592 const unsigned format
= var
->data
.image
.format
;
3594 /* Get the arguments of the image intrinsic. */
3595 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3596 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3597 BRW_REGISTER_TYPE_UD
);
3598 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3599 retype(get_nir_src(instr
->src
[2]), base_type
) :
3601 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3602 retype(get_nir_src(instr
->src
[3]), base_type
) :
3606 /* Emit an image load, store or atomic op. */
3607 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3608 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3610 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3611 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3612 var
->data
.image
.write_only
? GL_NONE
: format
);
3615 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3616 surf_dims
, arr_dims
, info
->dest_components
,
3617 get_image_atomic_op(instr
->intrinsic
, type
));
3619 /* Assign the result. */
3620 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3621 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3622 offset(tmp
, bld
, c
));
3626 case nir_intrinsic_memory_barrier_atomic_counter
:
3627 case nir_intrinsic_memory_barrier_buffer
:
3628 case nir_intrinsic_memory_barrier_image
:
3629 case nir_intrinsic_memory_barrier
: {
3630 const fs_builder ubld
= bld
.group(8, 0);
3631 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3632 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3633 ->size_written
= 2 * REG_SIZE
;
3637 case nir_intrinsic_group_memory_barrier
:
3638 case nir_intrinsic_memory_barrier_shared
:
3639 /* We treat these workgroup-level barriers as no-ops. This should be
3640 * safe at present and as long as:
3642 * - Memory access instructions are not subsequently reordered by the
3643 * compiler back-end.
3645 * - All threads from a given compute shader workgroup fit within a
3646 * single subslice and therefore talk to the same HDC shared unit
3647 * what supposedly guarantees ordering and coherency between threads
3648 * from the same workgroup. This may change in the future when we
3649 * start splitting workgroups across multiple subslices.
3651 * - The context is not in fault-and-stream mode, which could cause
3652 * memory transactions (including to SLM) prior to the barrier to be
3653 * replayed after the barrier if a pagefault occurs. This shouldn't
3654 * be a problem up to and including SKL because fault-and-stream is
3655 * not usable due to hardware issues, but that's likely to change in
3660 case nir_intrinsic_shader_clock
: {
3661 /* We cannot do anything if there is an event, so ignore it for now */
3662 const fs_reg shader_clock
= get_timestamp(bld
);
3663 const fs_reg srcs
[] = { component(shader_clock
, 0),
3664 component(shader_clock
, 1) };
3665 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3669 case nir_intrinsic_image_size
: {
3670 /* Get the referenced image variable and type. */
3671 const nir_variable
*var
= instr
->variables
[0]->var
;
3672 const glsl_type
*type
= var
->type
->without_array();
3674 /* Get the size of the image. */
3675 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3676 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3678 /* For 1DArray image types, the array index is stored in the Z component.
3679 * Fix this by swizzling the Z component to the Y component.
3681 const bool is_1d_array_image
=
3682 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3683 type
->sampler_array
;
3685 /* For CubeArray images, we should count the number of cubes instead
3686 * of the number of faces. Fix it by dividing the (Z component) by 6.
3688 const bool is_cube_array_image
=
3689 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3690 type
->sampler_array
;
3692 /* Copy all the components. */
3693 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3694 if ((int)c
>= type
->coordinate_components()) {
3695 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3697 } else if (c
== 1 && is_1d_array_image
) {
3698 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3699 offset(size
, bld
, 2));
3700 } else if (c
== 2 && is_cube_array_image
) {
3701 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3702 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3703 offset(size
, bld
, c
), brw_imm_d(6));
3705 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3706 offset(size
, bld
, c
));
3713 case nir_intrinsic_image_samples
:
3714 /* The driver does not support multi-sampled images. */
3715 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3718 case nir_intrinsic_load_uniform
: {
3719 /* Offsets are in bytes but they should always be multiples of 4 */
3720 assert(instr
->const_index
[0] % 4 == 0);
3722 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3724 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3726 /* Offsets are in bytes but they should always be multiples of 4 */
3727 assert(const_offset
->u32
[0] % 4 == 0);
3728 src
.offset
= const_offset
->u32
[0];
3730 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3731 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3734 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3735 BRW_REGISTER_TYPE_UD
);
3737 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3738 * go past the end of the uniform. In order to keep the n'th
3739 * component from running past, we subtract off the size of all but
3740 * one component of the vector.
3742 assert(instr
->const_index
[1] >=
3743 instr
->num_components
* (int) type_sz(dest
.type
));
3744 unsigned read_size
= instr
->const_index
[1] -
3745 (instr
->num_components
- 1) * type_sz(dest
.type
);
3747 bool supports_64bit_indirects
=
3748 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3750 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3751 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3752 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3753 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3754 indirect
, brw_imm_ud(read_size
));
3757 const unsigned num_mov_indirects
=
3758 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3759 /* We read a little bit less per MOV INDIRECT, as they are now
3760 * 32-bits ones instead of 64-bit. Fix read_size then.
3762 const unsigned read_size_32bit
= read_size
-
3763 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3764 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3765 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3766 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3767 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3768 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3769 indirect
, brw_imm_ud(read_size_32bit
));
3777 case nir_intrinsic_load_ubo
: {
3778 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3782 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3783 const_index
->u32
[0];
3784 surf_index
= brw_imm_ud(index
);
3785 brw_mark_surface_used(prog_data
, index
);
3787 /* The block index is not a constant. Evaluate the index expression
3788 * per-channel and add the base UBO index; we have to select a value
3789 * from any live channel.
3791 surf_index
= vgrf(glsl_type::uint_type
);
3792 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3793 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3794 surf_index
= bld
.emit_uniformize(surf_index
);
3796 /* Assume this may touch any UBO. It would be nice to provide
3797 * a tighter bound, but the array information is already lowered away.
3799 brw_mark_surface_used(prog_data
,
3800 stage_prog_data
->binding_table
.ubo_start
+
3801 nir
->info
.num_ubos
- 1);
3804 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3805 if (const_offset
== NULL
) {
3806 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3807 BRW_REGISTER_TYPE_UD
);
3809 for (int i
= 0; i
< instr
->num_components
; i
++)
3810 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3811 base_offset
, i
* type_sz(dest
.type
));
3813 /* Even if we are loading doubles, a pull constant load will load
3814 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3815 * need to load a full dvec4 we will have to emit 2 loads. This is
3816 * similar to demote_pull_constants(), except that in that case we
3817 * see individual accesses to each component of the vector and then
3818 * we let CSE deal with duplicate loads. Here we see a vector access
3819 * and we have to split it if necessary.
3821 const unsigned type_size
= type_sz(dest
.type
);
3823 /* See if we've selected this as a push constant candidate */
3825 const unsigned ubo_block
= const_index
->u32
[0];
3826 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
3829 for (int i
= 0; i
< 4; i
++) {
3830 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3831 if (range
->block
== ubo_block
&&
3832 offset_256b
>= range
->start
&&
3833 offset_256b
< range
->start
+ range
->length
) {
3835 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3836 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
3841 if (push_reg
.file
!= BAD_FILE
) {
3842 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3843 bld
.MOV(offset(dest
, bld
, i
),
3844 byte_offset(push_reg
, i
* type_size
));
3850 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3851 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3852 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3854 for (unsigned c
= 0; c
< instr
->num_components
;) {
3855 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3856 /* Number of usable components in the next block-aligned load. */
3857 const unsigned count
= MIN2(instr
->num_components
- c
,
3858 (block_sz
- base
% block_sz
) / type_size
);
3860 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3861 packed_consts
, surf_index
,
3862 brw_imm_ud(base
& ~(block_sz
- 1)));
3864 const fs_reg consts
=
3865 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3868 for (unsigned d
= 0; d
< count
; d
++)
3869 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3877 case nir_intrinsic_load_ssbo
: {
3878 assert(devinfo
->gen
>= 7);
3880 nir_const_value
*const_uniform_block
=
3881 nir_src_as_const_value(instr
->src
[0]);
3884 if (const_uniform_block
) {
3885 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3886 const_uniform_block
->u32
[0];
3887 surf_index
= brw_imm_ud(index
);
3888 brw_mark_surface_used(prog_data
, index
);
3890 surf_index
= vgrf(glsl_type::uint_type
);
3891 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3892 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3894 /* Assume this may touch any UBO. It would be nice to provide
3895 * a tighter bound, but the array information is already lowered away.
3897 brw_mark_surface_used(prog_data
,
3898 stage_prog_data
->binding_table
.ssbo_start
+
3899 nir
->info
.num_ssbos
- 1);
3903 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3905 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3907 offset_reg
= get_nir_src(instr
->src
[1]);
3910 /* Read the vector */
3911 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3912 instr
->num_components
);
3917 case nir_intrinsic_store_ssbo
: {
3918 assert(devinfo
->gen
>= 7);
3920 if (stage
== MESA_SHADER_FRAGMENT
)
3921 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3925 nir_const_value
*const_uniform_block
=
3926 nir_src_as_const_value(instr
->src
[1]);
3927 if (const_uniform_block
) {
3928 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3929 const_uniform_block
->u32
[0];
3930 surf_index
= brw_imm_ud(index
);
3931 brw_mark_surface_used(prog_data
, index
);
3933 surf_index
= vgrf(glsl_type::uint_type
);
3934 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3935 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3937 brw_mark_surface_used(prog_data
,
3938 stage_prog_data
->binding_table
.ssbo_start
+
3939 nir
->info
.num_ssbos
- 1);
3943 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3946 unsigned writemask
= instr
->const_index
[0];
3948 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3949 * since the untyped writes below operate in units of 32-bits, which
3950 * means that we need to write twice as many components each time.
3951 * Also, we have to suffle 64-bit data to be in the appropriate layout
3952 * expected by our 32-bit write messages.
3954 unsigned type_size
= 4;
3955 unsigned bit_size
= instr
->src
[0].is_ssa
?
3956 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3957 if (bit_size
== 64) {
3960 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3961 shuffle_64bit_data_for_32bit_write(bld
,
3962 retype(tmp
, BRW_REGISTER_TYPE_F
),
3963 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3964 instr
->num_components
);
3968 unsigned type_slots
= type_size
/ 4;
3970 /* Combine groups of consecutive enabled channels in one write
3971 * message. We use ffs to find the first enabled channel and then ffs on
3972 * the bit-inverse, down-shifted writemask to determine the length of
3973 * the block of enabled bits.
3976 unsigned first_component
= ffs(writemask
) - 1;
3977 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3979 /* We can't write more than 2 64-bit components at once. Limit the
3980 * length of the write to what we can do and let the next iteration
3984 length
= MIN2(2, length
);
3987 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
3989 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
3990 type_size
* first_component
);
3992 offset_reg
= vgrf(glsl_type::uint_type
);
3994 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
3995 brw_imm_ud(type_size
* first_component
));
3999 emit_untyped_write(bld
, surf_index
, offset_reg
,
4000 offset(val_reg
, bld
, first_component
* type_slots
),
4001 1 /* dims */, length
* type_slots
,
4002 BRW_PREDICATE_NONE
);
4004 /* Clear the bits in the writemask that we just wrote, then try
4005 * again to see if more channels are left.
4007 writemask
&= (15 << (first_component
+ length
));
4012 case nir_intrinsic_store_output
: {
4013 fs_reg src
= get_nir_src(instr
->src
[0]);
4015 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4016 assert(const_offset
&& "Indirect output stores not allowed");
4017 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4018 4 * const_offset
->u32
[0]), src
.type
);
4020 unsigned num_components
= instr
->num_components
;
4021 unsigned first_component
= nir_intrinsic_component(instr
);
4022 unsigned bit_size
= instr
->src
[0].is_ssa
?
4023 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4024 if (bit_size
== 64) {
4026 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4027 BRW_REGISTER_TYPE_F
);
4028 shuffle_64bit_data_for_32bit_write(
4029 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4030 src
= retype(tmp
, src
.type
);
4031 num_components
*= 2;
4034 for (unsigned j
= 0; j
< num_components
; j
++) {
4035 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4036 offset(src
, bld
, j
));
4041 case nir_intrinsic_ssbo_atomic_add
:
4042 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4044 case nir_intrinsic_ssbo_atomic_imin
:
4045 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4047 case nir_intrinsic_ssbo_atomic_umin
:
4048 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4050 case nir_intrinsic_ssbo_atomic_imax
:
4051 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4053 case nir_intrinsic_ssbo_atomic_umax
:
4054 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4056 case nir_intrinsic_ssbo_atomic_and
:
4057 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4059 case nir_intrinsic_ssbo_atomic_or
:
4060 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4062 case nir_intrinsic_ssbo_atomic_xor
:
4063 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4065 case nir_intrinsic_ssbo_atomic_exchange
:
4066 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4068 case nir_intrinsic_ssbo_atomic_comp_swap
:
4069 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4072 case nir_intrinsic_get_buffer_size
: {
4073 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4074 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4076 /* A resinfo's sampler message is used to get the buffer size. The
4077 * SIMD8's writeback message consists of four registers and SIMD16's
4078 * writeback message consists of 8 destination registers (two per each
4079 * component). Because we are only interested on the first channel of
4080 * the first returned component, where resinfo returns the buffer size
4081 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4082 * the dispatch width.
4084 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4085 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4086 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4089 ubld
.MOV(src_payload
, brw_imm_d(0));
4091 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4092 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4093 src_payload
, brw_imm_ud(index
));
4094 inst
->header_size
= 0;
4096 inst
->size_written
= 4 * REG_SIZE
;
4098 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4099 brw_mark_surface_used(prog_data
, index
);
4103 case nir_intrinsic_load_subgroup_size
:
4104 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4107 case nir_intrinsic_load_subgroup_invocation
: {
4108 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4109 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4110 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4111 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4112 if (dispatch_width
> 8)
4113 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4114 if (dispatch_width
> 16) {
4115 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4116 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4122 case nir_intrinsic_load_subgroup_eq_mask
:
4123 case nir_intrinsic_load_subgroup_ge_mask
:
4124 case nir_intrinsic_load_subgroup_gt_mask
:
4125 case nir_intrinsic_load_subgroup_le_mask
:
4126 case nir_intrinsic_load_subgroup_lt_mask
:
4127 unreachable("not reached");
4129 case nir_intrinsic_vote_any
: {
4130 const fs_builder ubld
= bld
.exec_all();
4132 /* The any/all predicates do not consider channel enables. To prevent
4133 * dead channels from affecting the result, we initialize the flag with
4134 * with the identity value for the logical operation.
4136 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4137 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4138 bld
.MOV(dest
, brw_imm_d(-1));
4139 set_predicate(dispatch_width
== 8 ?
4140 BRW_PREDICATE_ALIGN1_ANY8H
:
4141 BRW_PREDICATE_ALIGN1_ANY16H
,
4142 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4145 case nir_intrinsic_vote_all
: {
4146 const fs_builder ubld
= bld
.exec_all();
4148 /* The any/all predicates do not consider channel enables. To prevent
4149 * dead channels from affecting the result, we initialize the flag with
4150 * with the identity value for the logical operation.
4152 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4153 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4154 bld
.MOV(dest
, brw_imm_d(-1));
4155 set_predicate(dispatch_width
== 8 ?
4156 BRW_PREDICATE_ALIGN1_ALL8H
:
4157 BRW_PREDICATE_ALIGN1_ALL16H
,
4158 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4161 case nir_intrinsic_vote_eq
: {
4162 fs_reg value
= get_nir_src(instr
->src
[0]);
4163 fs_reg uniformized
= bld
.emit_uniformize(value
);
4164 const fs_builder ubld
= bld
.exec_all();
4166 /* The any/all predicates do not consider channel enables. To prevent
4167 * dead channels from affecting the result, we initialize the flag with
4168 * with the identity value for the logical operation.
4170 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4171 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4172 bld
.MOV(dest
, brw_imm_d(-1));
4173 set_predicate(dispatch_width
== 8 ?
4174 BRW_PREDICATE_ALIGN1_ALL8H
:
4175 BRW_PREDICATE_ALIGN1_ALL16H
,
4176 bld
.SEL(dest
, dest
, brw_imm_d(0)));
4180 case nir_intrinsic_ballot
: {
4181 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4182 BRW_REGISTER_TYPE_UD
);
4183 const struct brw_reg flag
= retype(brw_flag_reg(0, 0),
4184 BRW_REGISTER_TYPE_UD
);
4186 bld
.exec_all().MOV(flag
, brw_imm_ud(0u));
4187 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4189 if (instr
->dest
.ssa
.bit_size
> 32) {
4190 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4192 dest
.type
= BRW_REGISTER_TYPE_UD
;
4194 bld
.MOV(dest
, flag
);
4198 case nir_intrinsic_read_invocation
: {
4199 const fs_reg value
= get_nir_src(instr
->src
[0]);
4200 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4201 fs_reg tmp
= bld
.vgrf(value
.type
);
4203 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4204 component(invocation
, 0));
4206 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4207 fs_reg(component(tmp
, 0)));
4211 case nir_intrinsic_read_first_invocation
: {
4212 const fs_reg value
= get_nir_src(instr
->src
[0]);
4213 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4214 bld
.emit_uniformize(value
));
4219 unreachable("unknown intrinsic");
4224 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4225 int op
, nir_intrinsic_instr
*instr
)
4227 if (stage
== MESA_SHADER_FRAGMENT
)
4228 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4231 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4232 dest
= get_nir_dest(instr
->dest
);
4235 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4236 if (const_surface
) {
4237 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4238 const_surface
->u32
[0];
4239 surface
= brw_imm_ud(surf_index
);
4240 brw_mark_surface_used(prog_data
, surf_index
);
4242 surface
= vgrf(glsl_type::uint_type
);
4243 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4244 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4246 /* Assume this may touch any SSBO. This is the same we do for other
4247 * UBO/SSBO accesses with non-constant surface.
4249 brw_mark_surface_used(prog_data
,
4250 stage_prog_data
->binding_table
.ssbo_start
+
4251 nir
->info
.num_ssbos
- 1);
4254 fs_reg offset
= get_nir_src(instr
->src
[1]);
4255 fs_reg data1
= get_nir_src(instr
->src
[2]);
4257 if (op
== BRW_AOP_CMPWR
)
4258 data2
= get_nir_src(instr
->src
[3]);
4260 /* Emit the actual atomic operation */
4262 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4264 1 /* dims */, 1 /* rsize */,
4266 BRW_PREDICATE_NONE
);
4267 dest
.type
= atomic_result
.type
;
4268 bld
.MOV(dest
, atomic_result
);
4272 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4273 int op
, nir_intrinsic_instr
*instr
)
4276 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4277 dest
= get_nir_dest(instr
->dest
);
4279 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4281 fs_reg data1
= get_nir_src(instr
->src
[1]);
4283 if (op
== BRW_AOP_CMPWR
)
4284 data2
= get_nir_src(instr
->src
[2]);
4286 /* Get the offset */
4287 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4289 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4291 offset
= vgrf(glsl_type::uint_type
);
4293 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4294 brw_imm_ud(instr
->const_index
[0]));
4297 /* Emit the actual atomic operation operation */
4299 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4301 1 /* dims */, 1 /* rsize */,
4303 BRW_PREDICATE_NONE
);
4304 dest
.type
= atomic_result
.type
;
4305 bld
.MOV(dest
, atomic_result
);
4309 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4311 unsigned texture
= instr
->texture_index
;
4312 unsigned sampler
= instr
->sampler_index
;
4314 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4316 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4317 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4319 int lod_components
= 0;
4321 /* The hardware requires a LOD for buffer textures */
4322 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4323 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4325 uint32_t header_bits
= 0;
4326 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4327 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4328 switch (instr
->src
[i
].src_type
) {
4329 case nir_tex_src_bias
:
4330 srcs
[TEX_LOGICAL_SRC_LOD
] =
4331 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4333 case nir_tex_src_comparator
:
4334 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4336 case nir_tex_src_coord
:
4337 switch (instr
->op
) {
4339 case nir_texop_txf_ms
:
4340 case nir_texop_txf_ms_mcs
:
4341 case nir_texop_samples_identical
:
4342 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4345 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4349 case nir_tex_src_ddx
:
4350 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4351 lod_components
= nir_tex_instr_src_size(instr
, i
);
4353 case nir_tex_src_ddy
:
4354 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4356 case nir_tex_src_lod
:
4357 switch (instr
->op
) {
4359 srcs
[TEX_LOGICAL_SRC_LOD
] =
4360 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4363 srcs
[TEX_LOGICAL_SRC_LOD
] =
4364 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4367 srcs
[TEX_LOGICAL_SRC_LOD
] =
4368 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4372 case nir_tex_src_ms_index
:
4373 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4376 case nir_tex_src_offset
: {
4377 nir_const_value
*const_offset
=
4378 nir_src_as_const_value(instr
->src
[i
].src
);
4379 unsigned offset_bits
= 0;
4381 brw_texture_offset(const_offset
->i32
,
4382 nir_tex_instr_src_size(instr
, i
),
4384 header_bits
|= offset_bits
;
4386 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4387 retype(src
, BRW_REGISTER_TYPE_D
);
4392 case nir_tex_src_projector
:
4393 unreachable("should be lowered");
4395 case nir_tex_src_texture_offset
: {
4396 /* Figure out the highest possible texture index and mark it as used */
4397 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4398 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4399 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4401 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4403 brw_mark_surface_used(prog_data
, max_used
);
4405 /* Emit code to evaluate the actual indexing expression */
4406 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4407 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4408 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4412 case nir_tex_src_sampler_offset
: {
4413 /* Emit code to evaluate the actual indexing expression */
4414 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4415 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4416 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4420 case nir_tex_src_ms_mcs
:
4421 assert(instr
->op
== nir_texop_txf_ms
);
4422 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4425 case nir_tex_src_plane
: {
4426 nir_const_value
*const_plane
=
4427 nir_src_as_const_value(instr
->src
[i
].src
);
4428 const uint32_t plane
= const_plane
->u32
[0];
4429 const uint32_t texture_index
=
4430 instr
->texture_index
+
4431 stage_prog_data
->binding_table
.plane_start
[plane
] -
4432 stage_prog_data
->binding_table
.texture_start
;
4434 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4439 unreachable("unknown texture source");
4443 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4444 (instr
->op
== nir_texop_txf_ms
||
4445 instr
->op
== nir_texop_samples_identical
)) {
4446 if (devinfo
->gen
>= 7 &&
4447 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4448 srcs
[TEX_LOGICAL_SRC_MCS
] =
4449 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4450 instr
->coord_components
,
4451 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4453 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4457 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4458 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4461 switch (instr
->op
) {
4463 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4464 SHADER_OPCODE_TXL_LOGICAL
);
4467 opcode
= FS_OPCODE_TXB_LOGICAL
;
4470 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4473 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4476 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4478 case nir_texop_txf_ms
:
4479 if ((key_tex
->msaa_16
& (1 << sampler
)))
4480 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4482 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4484 case nir_texop_txf_ms_mcs
:
4485 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4487 case nir_texop_query_levels
:
4489 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4492 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4495 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4496 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4498 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4500 case nir_texop_texture_samples
:
4501 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4503 case nir_texop_samples_identical
: {
4504 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4506 /* If mcs is an immediate value, it means there is no MCS. In that case
4507 * just return false.
4509 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4510 bld
.MOV(dst
, brw_imm_ud(0u));
4511 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4512 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4513 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4514 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4515 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4517 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4518 BRW_CONDITIONAL_EQ
);
4523 unreachable("unknown texture opcode");
4526 /* TXS and TXL require a LOD but not everything we implement using those
4527 * two opcodes provides one. Provide a default LOD of 0.
4529 if ((opcode
== SHADER_OPCODE_TXS_LOGICAL
||
4530 opcode
== SHADER_OPCODE_TXL_LOGICAL
) &&
4531 srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
) {
4532 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4535 if (instr
->op
== nir_texop_tg4
) {
4536 if (instr
->component
== 1 &&
4537 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4538 /* gather4 sampler is broken for green channel on RG32F --
4539 * we must ask for blue instead.
4541 header_bits
|= 2 << 16;
4543 header_bits
|= instr
->component
<< 16;
4547 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4548 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4549 inst
->offset
= header_bits
;
4551 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4552 if (devinfo
->gen
>= 9 &&
4553 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4554 unsigned write_mask
= instr
->dest
.is_ssa
?
4555 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4556 (1 << dest_size
) - 1;
4557 assert(write_mask
!= 0); /* dead code should have been eliminated */
4558 inst
->size_written
= util_last_bit(write_mask
) *
4559 inst
->dst
.component_size(inst
->exec_size
);
4561 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4564 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4565 inst
->shadow_compare
= true;
4567 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4568 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4571 for (unsigned i
= 0; i
< dest_size
; i
++)
4572 nir_dest
[i
] = offset(dst
, bld
, i
);
4574 if (instr
->op
== nir_texop_query_levels
) {
4575 /* # levels is in .w */
4576 nir_dest
[0] = offset(dst
, bld
, 3);
4577 } else if (instr
->op
== nir_texop_txs
&&
4578 dest_size
>= 3 && devinfo
->gen
< 7) {
4579 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4580 fs_reg depth
= offset(dst
, bld
, 2);
4581 nir_dest
[2] = vgrf(glsl_type::int_type
);
4582 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4585 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4589 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4591 switch (instr
->type
) {
4592 case nir_jump_break
:
4593 bld
.emit(BRW_OPCODE_BREAK
);
4595 case nir_jump_continue
:
4596 bld
.emit(BRW_OPCODE_CONTINUE
);
4598 case nir_jump_return
:
4600 unreachable("unknown jump");
4605 * This helper takes the result of a load operation that reads 32-bit elements
4613 * and shuffles the data to get this:
4620 * Which is exactly what we want if the load is reading 64-bit components
4621 * like doubles, where x represents the low 32-bit of the x double component
4622 * and y represents the high 32-bit of the x double component (likewise with
4623 * z and w for double component y). The parameter @components represents
4624 * the number of 64-bit components present in @src. This would typically be
4625 * 2 at most, since we can only fit 2 double elements in the result of a
4628 * Notice that @dst and @src can be the same register.
4631 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4634 uint32_t components
)
4636 assert(type_sz(src
.type
) == 4);
4637 assert(type_sz(dst
.type
) == 8);
4639 /* A temporary that we will use to shuffle the 32-bit data of each
4640 * component in the vector into valid 64-bit data. We can't write directly
4641 * to dst because dst can be (and would usually be) the same as src
4642 * and in that case the first MOV in the loop below would overwrite the
4643 * data read in the second MOV.
4645 fs_reg tmp
= bld
.vgrf(dst
.type
);
4647 for (unsigned i
= 0; i
< components
; i
++) {
4648 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4650 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4651 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4653 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4658 * This helper does the inverse operation of
4659 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4661 * We need to do this when we are going to use untyped write messsages that
4662 * operate with 32-bit components in order to arrange our 64-bit data to be
4663 * in the expected layout.
4665 * Notice that callers of this function, unlike in the case of the inverse
4666 * operation, would typically need to call this with dst and src being
4667 * different registers, since they would otherwise corrupt the original
4668 * 64-bit data they are about to write. Because of this the function checks
4669 * that the src and dst regions involved in the operation do not overlap.
4672 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4675 uint32_t components
)
4677 assert(type_sz(src
.type
) == 8);
4678 assert(type_sz(dst
.type
) == 4);
4680 assert(!regions_overlap(
4681 dst
, 2 * components
* dst
.component_size(bld
.dispatch_width()),
4682 src
, components
* src
.component_size(bld
.dispatch_width())));
4684 for (unsigned i
= 0; i
< components
; i
++) {
4685 const fs_reg component_i
= offset(src
, bld
, i
);
4686 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4687 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4692 setup_imm_df(const fs_builder
&bld
, double v
)
4694 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4695 assert(devinfo
->gen
>= 7);
4697 if (devinfo
->gen
>= 8)
4698 return brw_imm_df(v
);
4700 /* gen7.5 does not support DF immediates straighforward but the DIM
4701 * instruction allows to set the 64-bit immediate value.
4703 if (devinfo
->is_haswell
) {
4704 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4705 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4706 ubld
.DIM(dst
, brw_imm_df(v
));
4707 return component(dst
, 0);
4710 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4711 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4712 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4714 * Alternatively, we could also produce a normal VGRF (without stride 0)
4715 * by writing to all the channels in the VGRF, however, that would hit the
4716 * gen7 bug where we have to split writes that span more than 1 register
4717 * into instructions with a width of 4 (otherwise the write to the second
4718 * register written runs into an execmask hardware bug) which isn't very
4731 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4732 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4733 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4734 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4736 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);