2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "nir_search_helpers.h"
28 #include "util/u_math.h"
29 #include "util/bitscan.h"
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
47 fs_visitor::nir_setup_outputs()
49 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
52 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
54 /* Calculate the size of output registers in a separate pass, before
55 * allocating them. With ARB_enhanced_layouts, multiple output variables
56 * may occupy the same slot, but have different type sizes.
58 nir_foreach_variable(var
, &nir
->outputs
) {
59 const int loc
= var
->data
.driver_location
;
60 const unsigned var_vec4s
=
61 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
62 : type_size_vec4(var
->type
, true);
63 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
66 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
67 if (vec4s
[loc
] == 0) {
72 unsigned reg_size
= vec4s
[loc
];
74 /* Check if there are any ranges that start within this range and extend
75 * past it. If so, include them in this allocation.
77 for (unsigned i
= 1; i
< reg_size
; i
++)
78 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
80 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
81 for (unsigned i
= 0; i
< reg_size
; i
++)
82 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
89 fs_visitor::nir_setup_uniforms()
91 /* Only the first compile gets to set up uniforms. */
92 if (push_constant_loc
) {
93 assert(pull_constant_loc
);
97 uniforms
= nir
->num_uniforms
/ 4;
99 if (stage
== MESA_SHADER_COMPUTE
) {
100 /* Add a uniform for the thread local id. It must be the last uniform
103 assert(uniforms
== prog_data
->nr_params
);
104 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
105 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
106 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
111 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
115 nir_foreach_instr(instr
, block
) {
116 if (instr
->type
!= nir_instr_type_intrinsic
)
119 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
120 switch (intrin
->intrinsic
) {
121 case nir_intrinsic_load_vertex_id
:
122 case nir_intrinsic_load_base_vertex
:
123 unreachable("should be lowered by nir_lower_system_values().");
125 case nir_intrinsic_load_vertex_id_zero_base
:
126 case nir_intrinsic_load_is_indexed_draw
:
127 case nir_intrinsic_load_first_vertex
:
128 case nir_intrinsic_load_instance_id
:
129 case nir_intrinsic_load_base_instance
:
130 case nir_intrinsic_load_draw_id
:
131 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
133 case nir_intrinsic_load_invocation_id
:
134 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
136 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
137 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
138 if (reg
->file
== BAD_FILE
) {
139 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
140 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
141 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
142 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
147 case nir_intrinsic_load_sample_pos
:
148 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
149 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
150 if (reg
->file
== BAD_FILE
)
151 *reg
= *v
->emit_samplepos_setup();
154 case nir_intrinsic_load_sample_id
:
155 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
156 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
157 if (reg
->file
== BAD_FILE
)
158 *reg
= *v
->emit_sampleid_setup();
161 case nir_intrinsic_load_sample_mask_in
:
162 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
163 assert(v
->devinfo
->gen
>= 7);
164 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
165 if (reg
->file
== BAD_FILE
)
166 *reg
= *v
->emit_samplemaskin_setup();
169 case nir_intrinsic_load_work_group_id
:
170 assert(v
->stage
== MESA_SHADER_COMPUTE
);
171 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
172 if (reg
->file
== BAD_FILE
)
173 *reg
= *v
->emit_cs_work_group_id_setup();
176 case nir_intrinsic_load_helper_invocation
:
177 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
178 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
179 if (reg
->file
== BAD_FILE
) {
180 const fs_builder abld
=
181 v
->bld
.annotate("gl_HelperInvocation", NULL
);
183 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
184 * pixel mask is in g1.7 of the thread payload.
186 * We move the per-channel pixel enable bit to the low bit of each
187 * channel by shifting the byte containing the pixel mask by the
188 * vector immediate 0x76543210UV.
190 * The region of <1,8,0> reads only 1 byte (the pixel masks for
191 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
192 * masks for 2 and 3) in SIMD16.
194 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
196 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
197 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
198 hbld
.SHR(offset(shifted
, hbld
, i
),
199 stride(retype(brw_vec1_grf(1 + i
, 7),
200 BRW_REGISTER_TYPE_UB
),
202 brw_imm_v(0x76543210));
205 /* A set bit in the pixel mask means the channel is enabled, but
206 * that is the opposite of gl_HelperInvocation so we need to invert
209 * The negate source-modifier bit of logical instructions on Gen8+
210 * performs 1's complement negation, so we can use that instead of
213 fs_reg inverted
= negate(shifted
);
214 if (v
->devinfo
->gen
< 8) {
215 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
216 abld
.NOT(inverted
, shifted
);
219 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
220 * with 1 and negating.
222 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
223 abld
.AND(anded
, inverted
, brw_imm_uw(1));
225 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
226 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
240 fs_visitor::nir_emit_system_values()
242 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
243 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
244 nir_system_values
[i
] = fs_reg();
247 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
248 * never end up using it.
251 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
252 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
253 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
255 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
256 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
257 if (dispatch_width
> 8)
258 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
259 if (dispatch_width
> 16) {
260 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
261 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
265 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
266 nir_foreach_block(block
, impl
)
267 emit_system_values_block(block
, this);
271 * Returns a type based on a reference_type (word, float, half-float) and a
274 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
276 * @FIXME: 64-bit return types are always DF on integer types to maintain
277 * compability with uses of DF previously to the introduction of int64
281 brw_reg_type_from_bit_size(const unsigned bit_size
,
282 const brw_reg_type reference_type
)
284 switch(reference_type
) {
285 case BRW_REGISTER_TYPE_HF
:
286 case BRW_REGISTER_TYPE_F
:
287 case BRW_REGISTER_TYPE_DF
:
290 return BRW_REGISTER_TYPE_HF
;
292 return BRW_REGISTER_TYPE_F
;
294 return BRW_REGISTER_TYPE_DF
;
296 unreachable("Invalid bit size");
298 case BRW_REGISTER_TYPE_B
:
299 case BRW_REGISTER_TYPE_W
:
300 case BRW_REGISTER_TYPE_D
:
301 case BRW_REGISTER_TYPE_Q
:
304 return BRW_REGISTER_TYPE_B
;
306 return BRW_REGISTER_TYPE_W
;
308 return BRW_REGISTER_TYPE_D
;
310 return BRW_REGISTER_TYPE_Q
;
312 unreachable("Invalid bit size");
314 case BRW_REGISTER_TYPE_UB
:
315 case BRW_REGISTER_TYPE_UW
:
316 case BRW_REGISTER_TYPE_UD
:
317 case BRW_REGISTER_TYPE_UQ
:
320 return BRW_REGISTER_TYPE_UB
;
322 return BRW_REGISTER_TYPE_UW
;
324 return BRW_REGISTER_TYPE_UD
;
326 return BRW_REGISTER_TYPE_UQ
;
328 unreachable("Invalid bit size");
331 unreachable("Unknown type");
336 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
338 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
339 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
340 nir_locals
[i
] = fs_reg();
343 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
344 unsigned array_elems
=
345 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
346 unsigned size
= array_elems
* reg
->num_components
;
347 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
348 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
349 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
352 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
355 nir_emit_cf_list(&impl
->body
);
359 fs_visitor::nir_emit_cf_list(exec_list
*list
)
361 exec_list_validate(list
);
362 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
363 switch (node
->type
) {
365 nir_emit_if(nir_cf_node_as_if(node
));
368 case nir_cf_node_loop
:
369 nir_emit_loop(nir_cf_node_as_loop(node
));
372 case nir_cf_node_block
:
373 nir_emit_block(nir_cf_node_as_block(node
));
377 unreachable("Invalid CFG node block");
383 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
388 /* If the condition has the form !other_condition, use other_condition as
389 * the source, but invert the predicate on the if instruction.
391 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
392 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
393 assert(!cond
->src
[0].negate
);
394 assert(!cond
->src
[0].abs
);
397 cond_reg
= get_nir_src(cond
->src
[0].src
);
400 cond_reg
= get_nir_src(if_stmt
->condition
);
403 /* first, put the condition into f0 */
404 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
405 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
406 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
408 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
410 nir_emit_cf_list(&if_stmt
->then_list
);
412 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
413 bld
.emit(BRW_OPCODE_ELSE
);
414 nir_emit_cf_list(&if_stmt
->else_list
);
417 bld
.emit(BRW_OPCODE_ENDIF
);
419 if (devinfo
->gen
< 7)
420 limit_dispatch_width(16, "Non-uniform control flow unsupported "
425 fs_visitor::nir_emit_loop(nir_loop
*loop
)
427 bld
.emit(BRW_OPCODE_DO
);
429 nir_emit_cf_list(&loop
->body
);
431 bld
.emit(BRW_OPCODE_WHILE
);
433 if (devinfo
->gen
< 7)
434 limit_dispatch_width(16, "Non-uniform control flow unsupported "
439 fs_visitor::nir_emit_block(nir_block
*block
)
441 nir_foreach_instr(instr
, block
) {
442 nir_emit_instr(instr
);
447 fs_visitor::nir_emit_instr(nir_instr
*instr
)
449 const fs_builder abld
= bld
.annotate(NULL
, instr
);
451 switch (instr
->type
) {
452 case nir_instr_type_alu
:
453 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
456 case nir_instr_type_deref
:
457 unreachable("All derefs should've been lowered");
460 case nir_instr_type_intrinsic
:
462 case MESA_SHADER_VERTEX
:
463 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_TESS_CTRL
:
466 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_TESS_EVAL
:
469 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_GEOMETRY
:
472 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_FRAGMENT
:
475 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
477 case MESA_SHADER_COMPUTE
:
478 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
481 unreachable("unsupported shader stage");
485 case nir_instr_type_tex
:
486 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
489 case nir_instr_type_load_const
:
490 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
493 case nir_instr_type_ssa_undef
:
494 /* We create a new VGRF for undefs on every use (by handling
495 * them in get_nir_src()), rather than for each definition.
496 * This helps register coalescing eliminate MOVs from undef.
500 case nir_instr_type_jump
:
501 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
505 unreachable("unknown instruction type");
510 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
514 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
515 const fs_reg
&result
)
517 if (!instr
->src
[0].src
.is_ssa
||
518 !instr
->src
[0].src
.ssa
->parent_instr
)
521 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
524 nir_alu_instr
*src0
=
525 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
527 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
528 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
531 /* If either opcode has source modifiers, bail.
533 * TODO: We can potentially handle source modifiers if both of the opcodes
534 * we're combining are signed integers.
536 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
537 src0
->src
[0].abs
|| src0
->src
[0].negate
)
540 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
542 /* Element type to extract.*/
543 const brw_reg_type type
= brw_int_type(
544 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
545 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
547 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
548 op0
.type
= brw_type_for_nir_type(devinfo
,
549 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
550 nir_src_bit_size(src0
->src
[0].src
)));
551 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
553 set_saturate(instr
->dest
.saturate
,
554 bld
.MOV(result
, subscript(op0
, type
, element
)));
559 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
560 const fs_reg
&result
)
562 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
563 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
566 if (!nir_src_is_const(instr
->src
[1].src
) ||
567 !nir_src_is_const(instr
->src
[2].src
))
570 const float value1
= nir_src_as_float(instr
->src
[1].src
);
571 const float value2
= nir_src_as_float(instr
->src
[2].src
);
572 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
575 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
576 assert(value1
== -value2
);
578 fs_reg tmp
= vgrf(glsl_type::int_type
);
580 if (devinfo
->gen
>= 6) {
581 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
582 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
584 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
586 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
587 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
589 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
591 * This negation looks like it's safe in practice, because bits 0:4 will
592 * surely be TRIANGLES
595 if (value1
== -1.0f
) {
599 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
600 g0
, brw_imm_uw(0x3f80));
602 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
603 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
605 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
607 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
608 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
610 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
612 * This negation looks like it's safe in practice, because bits 0:4 will
613 * surely be TRIANGLES
616 if (value1
== -1.0f
) {
620 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
622 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
628 emit_find_msb_using_lzd(const fs_builder
&bld
,
629 const fs_reg
&result
,
637 /* LZD of an absolute value source almost always does the right
638 * thing. There are two problem values:
640 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
641 * 0. However, findMSB(int(0x80000000)) == 30.
643 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
644 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
646 * For a value of zero or negative one, -1 will be returned.
648 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
649 * findMSB(-(1<<x)) should return x-1.
651 * For all negative number cases, including 0x80000000 and
652 * 0xffffffff, the correct value is obtained from LZD if instead of
653 * negating the (already negative) value the logical-not is used. A
654 * conditonal logical-not can be achieved in two instructions.
656 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
658 bld
.ASR(temp
, src
, brw_imm_d(31));
659 bld
.XOR(temp
, temp
, src
);
662 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
663 retype(temp
, BRW_REGISTER_TYPE_UD
));
665 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
666 * from the LSB side. Subtract the result from 31 to convert the MSB
667 * count into an LSB count. If no bits are set, LZD will return 32.
668 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
670 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
671 inst
->src
[0].negate
= true;
675 brw_rnd_mode_from_nir_op (const nir_op op
) {
677 case nir_op_f2f16_rtz
:
678 return BRW_RND_MODE_RTZ
;
679 case nir_op_f2f16_rtne
:
680 return BRW_RND_MODE_RTNE
;
682 unreachable("Operation doesn't support rounding mode");
687 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
688 nir_alu_instr
*instr
,
693 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
695 result
.type
= brw_type_for_nir_type(devinfo
,
696 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
697 nir_dest_bit_size(instr
->dest
.dest
)));
699 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
700 op
[i
] = get_nir_src(instr
->src
[i
].src
);
701 op
[i
].type
= brw_type_for_nir_type(devinfo
,
702 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
703 nir_src_bit_size(instr
->src
[i
].src
)));
704 op
[i
].abs
= instr
->src
[i
].abs
;
705 op
[i
].negate
= instr
->src
[i
].negate
;
708 /* Move and vecN instrutions may still be vectored. Return the raw,
709 * vectored source and destination so that fs_visitor::nir_emit_alu can
710 * handle it. Other callers should not have to handle these kinds of
724 /* At this point, we have dealt with any instruction that operates on
725 * more than a single channel. Therefore, we can just adjust the source
726 * and destination registers for that channel and emit the instruction.
728 unsigned channel
= 0;
729 if (nir_op_infos
[instr
->op
].output_size
== 0) {
730 /* Since NIR is doing the scalarizing for us, we should only ever see
731 * vectorized operations with a single channel.
733 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
734 channel
= ffs(instr
->dest
.write_mask
) - 1;
736 result
= offset(result
, bld
, channel
);
739 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
740 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
741 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
748 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
751 for (unsigned i
= 0; i
< 2; i
++) {
752 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
754 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
755 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
756 /* The source of the inot is now the source of instr. */
757 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
759 assert(!op
[i
].negate
);
762 op
[i
] = resolve_source_modifiers(op
[i
]);
768 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
770 nir_alu_instr
*instr
)
772 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
775 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
777 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
780 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
781 * of valid size-changing combinations is a bit more complex.
783 * The source restriction is just because I was lazy about generating the
786 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
787 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
790 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
791 * this is float(1 + a).
795 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
797 /* Ignore the saturate modifier, if there is one. The result of the
798 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
800 bld
.ADD(result
, op
, brw_imm_d(1));
806 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
808 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
809 * the source of \c instr that is a \c nir_op_fsign.
812 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
813 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
817 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
818 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
820 if (instr
->op
!= nir_op_fsign
) {
821 const nir_alu_instr
*const fsign_instr
=
822 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
824 assert(!fsign_instr
->dest
.saturate
);
826 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
827 * fsign_src] has the other multiply source. This must be rearranged so
828 * that op[0] is the source of the fsign op[1] is the other multiply
834 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
836 const nir_alu_type t
=
837 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
838 nir_src_bit_size(fsign_instr
->src
[0].src
));
840 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
841 op
[0].abs
= fsign_instr
->src
[0].abs
;
842 op
[0].negate
= fsign_instr
->src
[0].negate
;
844 unsigned channel
= 0;
845 if (nir_op_infos
[instr
->op
].output_size
== 0) {
846 /* Since NIR is doing the scalarizing for us, we should only ever see
847 * vectorized operations with a single channel.
849 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
850 channel
= ffs(instr
->dest
.write_mask
) - 1;
853 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
855 assert(!instr
->dest
.saturate
);
859 /* Straightforward since the source can be assumed to be either strictly
860 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
862 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
864 if (instr
->op
== nir_op_fsign
) {
865 inst
= (op
[0].negate
)
866 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
867 : bld
.MOV(result
, brw_imm_f(1.0f
));
869 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
870 inst
= bld
.MOV(result
, op
[1]);
873 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
874 } else if (type_sz(op
[0].type
) == 2) {
875 /* AND(val, 0x8000) gives the sign bit.
877 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
879 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
880 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
882 op
[0].type
= BRW_REGISTER_TYPE_UW
;
883 result
.type
= BRW_REGISTER_TYPE_UW
;
884 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
886 if (instr
->op
== nir_op_fsign
)
887 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
889 /* Use XOR here to get the result sign correct. */
890 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
893 inst
->predicate
= BRW_PREDICATE_NORMAL
;
894 } else if (type_sz(op
[0].type
) == 4) {
895 /* AND(val, 0x80000000) gives the sign bit.
897 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
900 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
902 op
[0].type
= BRW_REGISTER_TYPE_UD
;
903 result
.type
= BRW_REGISTER_TYPE_UD
;
904 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
906 if (instr
->op
== nir_op_fsign
)
907 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
909 /* Use XOR here to get the result sign correct. */
910 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
913 inst
->predicate
= BRW_PREDICATE_NORMAL
;
915 /* For doubles we do the same but we need to consider:
917 * - 2-src instructions can't operate with 64-bit immediates
918 * - The sign is encoded in the high 32-bit of each DF
919 * - We need to produce a DF result.
922 fs_reg zero
= vgrf(glsl_type::double_type
);
923 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
924 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
926 bld
.MOV(result
, zero
);
928 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
929 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
930 brw_imm_ud(0x80000000u
));
932 if (instr
->op
== nir_op_fsign
) {
933 set_predicate(BRW_PREDICATE_NORMAL
,
934 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
936 /* This could be done better in some cases. If the scale is an
937 * immediate with the low 32-bits all 0, emitting a separate XOR and
938 * OR would allow an algebraic optimization to remove the OR. There
939 * are currently zero instances of fsign(double(x))*IMM in shader-db
940 * or any test suite, so it is hard to care at this time.
942 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
943 inst
= bld
.XOR(result_int64
, result_int64
,
944 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
950 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
952 * Checks the operands of a \c nir_op_fmul to determine whether or not
953 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
955 * \param instr The multiplication instruction
957 * \param fsign_src The source of \c instr that may or may not be a
961 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
963 assert(instr
->op
== nir_op_fmul
);
965 nir_alu_instr
*const fsign_instr
=
966 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
970 * 1. instr->src[fsign_src] must be a nir_op_fsign.
971 * 2. The nir_op_fsign can only be used by this multiplication.
972 * 3. The source that is the nir_op_fsign does not have source modifiers.
973 * \c emit_fsign only examines the source modifiers of the source of the
976 * The nir_op_fsign must also not have the saturate modifier, but steps
977 * have already been taken (in nir_opt_algebraic) to ensure that.
979 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
980 is_used_once(fsign_instr
) &&
981 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
985 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
987 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
991 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, true);
999 fs_reg temp
= result
;
1000 bool need_extra_copy
= false;
1001 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1002 if (!instr
->src
[i
].src
.is_ssa
&&
1003 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1004 need_extra_copy
= true;
1005 temp
= bld
.vgrf(result
.type
, 4);
1010 for (unsigned i
= 0; i
< 4; i
++) {
1011 if (!(instr
->dest
.write_mask
& (1 << i
)))
1014 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
1015 inst
= bld
.MOV(offset(temp
, bld
, i
),
1016 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1018 inst
= bld
.MOV(offset(temp
, bld
, i
),
1019 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1021 inst
->saturate
= instr
->dest
.saturate
;
1024 /* In this case the source and destination registers were the same,
1025 * so we need to insert an extra set of moves in order to deal with
1028 if (need_extra_copy
) {
1029 for (unsigned i
= 0; i
< 4; i
++) {
1030 if (!(instr
->dest
.write_mask
& (1 << i
)))
1033 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1041 if (optimize_extract_to_float(instr
, result
))
1043 inst
= bld
.MOV(result
, op
[0]);
1044 inst
->saturate
= instr
->dest
.saturate
;
1047 case nir_op_f2f16_rtne
:
1048 case nir_op_f2f16_rtz
:
1049 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1050 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
1053 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1054 * on the HW gen, it is a special hw opcode or just a MOV, and
1055 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1057 * But if we want to use that opcode, we need to provide support on
1058 * different optimizations and lowerings. As right now HF support is
1059 * only for gen8+, it will be better to use directly the MOV, and use
1060 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1062 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1063 inst
= bld
.MOV(result
, op
[0]);
1064 inst
->saturate
= instr
->dest
.saturate
;
1074 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1076 op
[0].type
= BRW_REGISTER_TYPE_D
;
1077 op
[0].negate
= !op
[0].negate
;
1101 if (result
.type
== BRW_REGISTER_TYPE_B
||
1102 result
.type
== BRW_REGISTER_TYPE_UB
||
1103 result
.type
== BRW_REGISTER_TYPE_HF
)
1104 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1106 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1107 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1108 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1109 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1111 inst
= bld
.MOV(result
, op
[0]);
1112 inst
->saturate
= instr
->dest
.saturate
;
1116 emit_fsign(bld
, instr
, result
, op
, 0);
1120 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1121 inst
->saturate
= instr
->dest
.saturate
;
1125 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1126 inst
->saturate
= instr
->dest
.saturate
;
1130 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1131 inst
->saturate
= instr
->dest
.saturate
;
1135 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1136 inst
->saturate
= instr
->dest
.saturate
;
1140 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1141 inst
->saturate
= instr
->dest
.saturate
;
1145 if (fs_key
->high_quality_derivatives
) {
1146 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1148 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1150 inst
->saturate
= instr
->dest
.saturate
;
1152 case nir_op_fddx_fine
:
1153 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1154 inst
->saturate
= instr
->dest
.saturate
;
1156 case nir_op_fddx_coarse
:
1157 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1158 inst
->saturate
= instr
->dest
.saturate
;
1161 if (fs_key
->high_quality_derivatives
) {
1162 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1164 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1166 inst
->saturate
= instr
->dest
.saturate
;
1168 case nir_op_fddy_fine
:
1169 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1170 inst
->saturate
= instr
->dest
.saturate
;
1172 case nir_op_fddy_coarse
:
1173 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1174 inst
->saturate
= instr
->dest
.saturate
;
1179 inst
= bld
.ADD(result
, op
[0], op
[1]);
1180 inst
->saturate
= instr
->dest
.saturate
;
1183 case nir_op_uadd_sat
:
1184 inst
= bld
.ADD(result
, op
[0], op
[1]);
1185 inst
->saturate
= true;
1189 for (unsigned i
= 0; i
< 2; i
++) {
1190 if (can_fuse_fmul_fsign(instr
, i
)) {
1191 emit_fsign(bld
, instr
, result
, op
, i
);
1196 inst
= bld
.MUL(result
, op
[0], op
[1]);
1197 inst
->saturate
= instr
->dest
.saturate
;
1200 case nir_op_imul_2x32_64
:
1201 case nir_op_umul_2x32_64
:
1202 bld
.MUL(result
, op
[0], op
[1]);
1206 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1207 bld
.MUL(result
, op
[0], op
[1]);
1210 case nir_op_imul_high
:
1211 case nir_op_umul_high
:
1212 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1213 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1218 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1219 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1222 case nir_op_uadd_carry
:
1223 unreachable("Should have been lowered by carry_to_arith().");
1225 case nir_op_usub_borrow
:
1226 unreachable("Should have been lowered by borrow_to_arith().");
1230 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1231 * appears that our hardware just does the right thing for signed
1234 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1235 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1239 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1240 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1242 /* Math instructions don't support conditional mod */
1243 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1244 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1246 /* Now, we need to determine if signs of the sources are different.
1247 * When we XOR the sources, the top bit is 0 if they are the same and 1
1248 * if they are different. We can then use a conditional modifier to
1249 * turn that into a predicate. This leads us to an XOR.l instruction.
1251 * Technically, according to the PRM, you're not allowed to use .l on a
1252 * XOR instruction. However, emperical experiments and Curro's reading
1253 * of the simulator source both indicate that it's safe.
1255 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1256 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1257 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1258 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1260 /* If the result of the initial remainder operation is non-zero and the
1261 * two sources have different signs, add in a copy of op[1] to get the
1262 * final integer modulus value.
1264 inst
= bld
.ADD(result
, result
, op
[1]);
1265 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1272 case nir_op_fne32
: {
1273 fs_reg dest
= result
;
1275 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1277 dest
= bld
.vgrf(op
[0].type
, 1);
1279 brw_conditional_mod cond
;
1280 switch (instr
->op
) {
1282 cond
= BRW_CONDITIONAL_L
;
1285 cond
= BRW_CONDITIONAL_GE
;
1288 cond
= BRW_CONDITIONAL_Z
;
1291 cond
= BRW_CONDITIONAL_NZ
;
1294 unreachable("bad opcode");
1297 bld
.CMP(dest
, op
[0], op
[1], cond
);
1299 if (bit_size
> 32) {
1300 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1301 } else if(bit_size
< 32) {
1302 /* When we convert the result to 32-bit we need to be careful and do
1303 * it as a signed conversion to get sign extension (for 32-bit true)
1305 const brw_reg_type src_type
=
1306 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1308 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1318 case nir_op_ine32
: {
1319 fs_reg dest
= result
;
1321 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1323 dest
= bld
.vgrf(op
[0].type
, 1);
1325 brw_conditional_mod cond
;
1326 switch (instr
->op
) {
1329 cond
= BRW_CONDITIONAL_L
;
1333 cond
= BRW_CONDITIONAL_GE
;
1336 cond
= BRW_CONDITIONAL_Z
;
1339 cond
= BRW_CONDITIONAL_NZ
;
1342 unreachable("bad opcode");
1344 bld
.CMP(dest
, op
[0], op
[1], cond
);
1346 if (bit_size
> 32) {
1347 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1348 } else if (bit_size
< 32) {
1349 /* When we convert the result to 32-bit we need to be careful and do
1350 * it as a signed conversion to get sign extension (for 32-bit true)
1352 const brw_reg_type src_type
=
1353 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1355 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1361 if (devinfo
->gen
>= 8) {
1362 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1364 if (inot_src_instr
!= NULL
&&
1365 (inot_src_instr
->op
== nir_op_ior
||
1366 inot_src_instr
->op
== nir_op_ixor
||
1367 inot_src_instr
->op
== nir_op_iand
) &&
1368 !inot_src_instr
->src
[0].abs
&&
1369 !inot_src_instr
->src
[0].negate
&&
1370 !inot_src_instr
->src
[1].abs
&&
1371 !inot_src_instr
->src
[1].negate
) {
1372 /* The sources of the source logical instruction are now the
1373 * sources of the instruction that will be generated.
1375 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1376 resolve_inot_sources(bld
, inot_src_instr
, op
);
1378 /* Smash all of the sources and destination to be signed. This
1379 * doesn't matter for the operation of the instruction, but cmod
1380 * propagation fails on unsigned sources with negation (due to
1381 * fs_inst::can_do_cmod returning false).
1384 brw_type_for_nir_type(devinfo
,
1385 (nir_alu_type
)(nir_type_int
|
1386 nir_dest_bit_size(instr
->dest
.dest
)));
1388 brw_type_for_nir_type(devinfo
,
1389 (nir_alu_type
)(nir_type_int
|
1390 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1392 brw_type_for_nir_type(devinfo
,
1393 (nir_alu_type
)(nir_type_int
|
1394 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1396 /* For XOR, only invert one of the sources. Arbitrarily choose
1399 op
[0].negate
= !op
[0].negate
;
1400 if (inot_src_instr
->op
!= nir_op_ixor
)
1401 op
[1].negate
= !op
[1].negate
;
1403 switch (inot_src_instr
->op
) {
1405 bld
.AND(result
, op
[0], op
[1]);
1409 bld
.OR(result
, op
[0], op
[1]);
1413 bld
.XOR(result
, op
[0], op
[1]);
1417 unreachable("impossible opcode");
1420 op
[0] = resolve_source_modifiers(op
[0]);
1422 bld
.NOT(result
, op
[0]);
1425 if (devinfo
->gen
>= 8) {
1426 resolve_inot_sources(bld
, instr
, op
);
1428 bld
.XOR(result
, op
[0], op
[1]);
1431 if (devinfo
->gen
>= 8) {
1432 resolve_inot_sources(bld
, instr
, op
);
1434 bld
.OR(result
, op
[0], op
[1]);
1437 if (devinfo
->gen
>= 8) {
1438 resolve_inot_sources(bld
, instr
, op
);
1440 bld
.AND(result
, op
[0], op
[1]);
1446 case nir_op_b32all_fequal2
:
1447 case nir_op_b32all_iequal2
:
1448 case nir_op_b32all_fequal3
:
1449 case nir_op_b32all_iequal3
:
1450 case nir_op_b32all_fequal4
:
1451 case nir_op_b32all_iequal4
:
1452 case nir_op_b32any_fnequal2
:
1453 case nir_op_b32any_inequal2
:
1454 case nir_op_b32any_fnequal3
:
1455 case nir_op_b32any_inequal3
:
1456 case nir_op_b32any_fnequal4
:
1457 case nir_op_b32any_inequal4
:
1458 unreachable("Lowered by nir_lower_alu_reductions");
1460 case nir_op_fnoise1_1
:
1461 case nir_op_fnoise1_2
:
1462 case nir_op_fnoise1_3
:
1463 case nir_op_fnoise1_4
:
1464 case nir_op_fnoise2_1
:
1465 case nir_op_fnoise2_2
:
1466 case nir_op_fnoise2_3
:
1467 case nir_op_fnoise2_4
:
1468 case nir_op_fnoise3_1
:
1469 case nir_op_fnoise3_2
:
1470 case nir_op_fnoise3_3
:
1471 case nir_op_fnoise3_4
:
1472 case nir_op_fnoise4_1
:
1473 case nir_op_fnoise4_2
:
1474 case nir_op_fnoise4_3
:
1475 case nir_op_fnoise4_4
:
1476 unreachable("not reached: should be handled by lower_noise");
1479 unreachable("not reached: should be handled by ldexp_to_arith()");
1482 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1483 inst
->saturate
= instr
->dest
.saturate
;
1487 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1488 inst
->saturate
= instr
->dest
.saturate
;
1492 case nir_op_f2b32
: {
1493 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1494 if (bit_size
== 64) {
1495 /* two-argument instructions can't take 64-bit immediates */
1499 if (instr
->op
== nir_op_f2b32
) {
1500 zero
= vgrf(glsl_type::double_type
);
1501 tmp
= vgrf(glsl_type::double_type
);
1502 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1504 zero
= vgrf(glsl_type::int64_t_type
);
1505 tmp
= vgrf(glsl_type::int64_t_type
);
1506 bld
.MOV(zero
, brw_imm_q(0));
1509 /* A SIMD16 execution needs to be split in two instructions, so use
1510 * a vgrf instead of the flag register as dst so instruction splitting
1513 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1514 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1517 if (bit_size
== 32) {
1518 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1520 assert(bit_size
== 16);
1521 zero
= instr
->op
== nir_op_f2b32
?
1522 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1524 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1530 inst
= bld
.RNDZ(result
, op
[0]);
1531 inst
->saturate
= instr
->dest
.saturate
;
1534 case nir_op_fceil
: {
1535 op
[0].negate
= !op
[0].negate
;
1536 fs_reg temp
= vgrf(glsl_type::float_type
);
1537 bld
.RNDD(temp
, op
[0]);
1539 inst
= bld
.MOV(result
, temp
);
1540 inst
->saturate
= instr
->dest
.saturate
;
1544 inst
= bld
.RNDD(result
, op
[0]);
1545 inst
->saturate
= instr
->dest
.saturate
;
1548 inst
= bld
.FRC(result
, op
[0]);
1549 inst
->saturate
= instr
->dest
.saturate
;
1551 case nir_op_fround_even
:
1552 inst
= bld
.RNDE(result
, op
[0]);
1553 inst
->saturate
= instr
->dest
.saturate
;
1556 case nir_op_fquantize2f16
: {
1557 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1558 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1559 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1561 /* The destination stride must be at least as big as the source stride. */
1562 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1565 /* Check for denormal */
1566 fs_reg abs_src0
= op
[0];
1567 abs_src0
.abs
= true;
1568 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1570 /* Get the appropriately signed zero */
1571 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1572 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1573 brw_imm_ud(0x80000000));
1574 /* Do the actual F32 -> F16 -> F32 conversion */
1575 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1576 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1577 /* Select that or zero based on normal status */
1578 inst
= bld
.SEL(result
, zero
, tmp32
);
1579 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1580 inst
->saturate
= instr
->dest
.saturate
;
1587 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1588 inst
->saturate
= instr
->dest
.saturate
;
1594 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1595 inst
->saturate
= instr
->dest
.saturate
;
1598 case nir_op_pack_snorm_2x16
:
1599 case nir_op_pack_snorm_4x8
:
1600 case nir_op_pack_unorm_2x16
:
1601 case nir_op_pack_unorm_4x8
:
1602 case nir_op_unpack_snorm_2x16
:
1603 case nir_op_unpack_snorm_4x8
:
1604 case nir_op_unpack_unorm_2x16
:
1605 case nir_op_unpack_unorm_4x8
:
1606 case nir_op_unpack_half_2x16
:
1607 case nir_op_pack_half_2x16
:
1608 unreachable("not reached: should be handled by lower_packing_builtins");
1610 case nir_op_unpack_half_2x16_split_x
:
1611 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1612 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1613 inst
->saturate
= instr
->dest
.saturate
;
1615 case nir_op_unpack_half_2x16_split_y
:
1616 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1617 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1618 inst
->saturate
= instr
->dest
.saturate
;
1621 case nir_op_pack_64_2x32_split
:
1622 case nir_op_pack_32_2x16_split
:
1623 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1626 case nir_op_unpack_64_2x32_split_x
:
1627 case nir_op_unpack_64_2x32_split_y
: {
1628 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1629 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1631 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1635 case nir_op_unpack_32_2x16_split_x
:
1636 case nir_op_unpack_32_2x16_split_y
: {
1637 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1638 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1640 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1645 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1646 inst
->saturate
= instr
->dest
.saturate
;
1649 case nir_op_bitfield_reverse
:
1650 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1651 bld
.BFREV(result
, op
[0]);
1654 case nir_op_bit_count
:
1655 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1656 bld
.CBIT(result
, op
[0]);
1659 case nir_op_ufind_msb
: {
1660 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1661 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1665 case nir_op_ifind_msb
: {
1666 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1668 if (devinfo
->gen
< 7) {
1669 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1671 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1673 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1674 * count from the LSB side. If FBH didn't return an error
1675 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1676 * count into an LSB count.
1678 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1680 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1681 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1682 inst
->src
[0].negate
= true;
1687 case nir_op_find_lsb
:
1688 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1690 if (devinfo
->gen
< 7) {
1691 fs_reg temp
= vgrf(glsl_type::int_type
);
1693 /* (x & -x) generates a value that consists of only the LSB of x.
1694 * For all powers of 2, findMSB(y) == findLSB(y).
1696 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1697 fs_reg negated_src
= src
;
1699 /* One must be negated, and the other must be non-negated. It
1700 * doesn't matter which is which.
1702 negated_src
.negate
= true;
1705 bld
.AND(temp
, src
, negated_src
);
1706 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1708 bld
.FBL(result
, op
[0]);
1712 case nir_op_ubitfield_extract
:
1713 case nir_op_ibitfield_extract
:
1714 unreachable("should have been lowered");
1717 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1718 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1721 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1722 bld
.BFI1(result
, op
[0], op
[1]);
1725 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1726 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1729 case nir_op_bitfield_insert
:
1730 unreachable("not reached: should have been lowered");
1733 bld
.SHL(result
, op
[0], op
[1]);
1736 bld
.ASR(result
, op
[0], op
[1]);
1739 bld
.SHR(result
, op
[0], op
[1]);
1742 case nir_op_pack_half_2x16_split
:
1743 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1747 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1748 inst
->saturate
= instr
->dest
.saturate
;
1752 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1753 inst
->saturate
= instr
->dest
.saturate
;
1756 case nir_op_b32csel
:
1757 if (optimize_frontfacing_ternary(instr
, result
))
1760 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1761 inst
= bld
.SEL(result
, op
[1], op
[2]);
1762 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1765 case nir_op_extract_u8
:
1766 case nir_op_extract_i8
: {
1767 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1772 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1773 * Use two instructions and a word or DWord intermediate integer type.
1775 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1776 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1778 if (instr
->op
== nir_op_extract_i8
) {
1779 /* If we need to sign extend, extract to a word first */
1780 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1781 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1782 bld
.MOV(result
, w_temp
);
1783 } else if (byte
& 1) {
1784 /* Extract the high byte from the word containing the desired byte
1788 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1791 /* Otherwise use an AND with 0xff and a word type */
1793 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1797 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1798 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1803 case nir_op_extract_u16
:
1804 case nir_op_extract_i16
: {
1805 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1806 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1807 bld
.MOV(result
, subscript(op
[0], type
, word
));
1812 unreachable("unhandled instruction");
1815 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1816 * to sign extend the low bit to 0/~0
1818 if (devinfo
->gen
<= 5 &&
1819 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1820 fs_reg masked
= vgrf(glsl_type::int_type
);
1821 bld
.AND(masked
, result
, brw_imm_d(1));
1822 masked
.negate
= true;
1823 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1828 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1829 nir_load_const_instr
*instr
)
1831 const brw_reg_type reg_type
=
1832 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1833 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1835 switch (instr
->def
.bit_size
) {
1837 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1838 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1842 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1843 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1847 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1848 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1852 assert(devinfo
->gen
>= 7);
1853 if (devinfo
->gen
== 7) {
1854 /* We don't get 64-bit integer types until gen8 */
1855 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1856 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1857 setup_imm_df(bld
, instr
->value
[i
].f64
));
1860 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1861 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1866 unreachable("Invalid bit size");
1869 nir_ssa_values
[instr
->def
.index
] = reg
;
1873 fs_visitor::get_nir_src(const nir_src
&src
)
1877 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1878 const brw_reg_type reg_type
=
1879 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1880 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1882 reg
= nir_ssa_values
[src
.ssa
->index
];
1885 /* We don't handle indirects on locals */
1886 assert(src
.reg
.indirect
== NULL
);
1887 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1888 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1891 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1892 /* The only 64-bit type available on gen7 is DF, so use that. */
1893 reg
.type
= BRW_REGISTER_TYPE_DF
;
1895 /* To avoid floating-point denorm flushing problems, set the type by
1896 * default to an integer type - instructions that need floating point
1897 * semantics will set this to F if they need to
1899 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1900 BRW_REGISTER_TYPE_D
);
1907 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1909 * This function should not be called on any value which may be 64 bits.
1910 * We could theoretically support 64-bit on gen8+ but we choose not to
1911 * because it wouldn't work in general (no gen7 support) and there are
1912 * enough restrictions in 64-bit immediates that you can't take the return
1913 * value and treat it the same as the result of get_nir_src().
1916 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1918 assert(nir_src_bit_size(src
) == 32);
1919 return nir_src_is_const(src
) ?
1920 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1924 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1927 const brw_reg_type reg_type
=
1928 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1929 dest
.ssa
.bit_size
== 8 ?
1930 BRW_REGISTER_TYPE_D
:
1931 BRW_REGISTER_TYPE_F
);
1932 nir_ssa_values
[dest
.ssa
.index
] =
1933 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1934 return nir_ssa_values
[dest
.ssa
.index
];
1936 /* We don't handle indirects on locals */
1937 assert(dest
.reg
.indirect
== NULL
);
1938 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1939 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1944 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1947 for (unsigned i
= 0; i
< 4; i
++) {
1948 if (!((wr_mask
>> i
) & 1))
1951 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1952 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1953 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1954 if (new_inst
->src
[j
].file
== VGRF
)
1955 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1962 emit_pixel_interpolater_send(const fs_builder
&bld
,
1967 glsl_interp_mode interpolation
)
1969 struct brw_wm_prog_data
*wm_prog_data
=
1970 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1972 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1973 /* 2 floats per slot returned */
1974 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1975 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1977 wm_prog_data
->pulls_bary
= true;
1983 * Computes 1 << x, given a D/UD register containing some value x.
1986 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1988 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1990 fs_reg result
= bld
.vgrf(x
.type
, 1);
1991 fs_reg one
= bld
.vgrf(x
.type
, 1);
1993 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1994 bld
.SHL(result
, one
, x
);
1999 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2001 assert(stage
== MESA_SHADER_GEOMETRY
);
2003 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2005 if (gs_compile
->control_data_header_size_bits
== 0)
2008 /* We can only do EndPrimitive() functionality when the control data
2009 * consists of cut bits. Fortunately, the only time it isn't is when the
2010 * output type is points, in which case EndPrimitive() is a no-op.
2012 if (gs_prog_data
->control_data_format
!=
2013 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2017 /* Cut bits use one bit per vertex. */
2018 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2020 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2021 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2023 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2024 * vertex n, 0 otherwise. So all we need to do here is mark bit
2025 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2026 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2027 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2029 * Note that if EndPrimitive() is called before emitting any vertices, this
2030 * will cause us to set bit 31 of the control_data_bits register to 1.
2031 * That's fine because:
2033 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2034 * output, so the hardware will ignore cut bit 31.
2036 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2037 * last vertex, so setting cut bit 31 has no effect (since the primitive
2038 * is automatically ended when the GS terminates).
2040 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2041 * control_data_bits register to 0 when the first vertex is emitted.
2044 const fs_builder abld
= bld
.annotate("end primitive");
2046 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2047 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2048 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2049 fs_reg mask
= intexp2(abld
, prev_count
);
2050 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2051 * attention to the lower 5 bits of its second source argument, so on this
2052 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2053 * ((vertex_count - 1) % 32).
2055 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2059 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2061 assert(stage
== MESA_SHADER_GEOMETRY
);
2062 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2064 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2066 const fs_builder abld
= bld
.annotate("emit control data bits");
2067 const fs_builder fwa_bld
= bld
.exec_all();
2069 /* We use a single UD register to accumulate control data bits (32 bits
2070 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2073 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2074 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2075 * use the Channel Mask phase to enable/disable which DWord within that
2076 * group to write. (Remember, different SIMD8 channels may have emitted
2077 * different numbers of vertices, so we may need per-slot offsets.)
2079 * Channel masking presents an annoying problem: we may have to replicate
2080 * the data up to 4 times:
2082 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2084 * To avoid penalizing shaders that emit a small number of vertices, we
2085 * can avoid these sometimes: if the size of the control data header is
2086 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2087 * land in the same 128-bit group, so we can skip per-slot offsets.
2089 * Similarly, if the control data header is <= 32 bits, there is only one
2090 * DWord, so we can skip channel masks.
2092 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2094 fs_reg channel_mask
, per_slot_offset
;
2096 if (gs_compile
->control_data_header_size_bits
> 32) {
2097 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2098 channel_mask
= vgrf(glsl_type::uint_type
);
2101 if (gs_compile
->control_data_header_size_bits
> 128) {
2102 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2103 per_slot_offset
= vgrf(glsl_type::uint_type
);
2106 /* Figure out which DWord we're trying to write to using the formula:
2108 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2110 * Since bits_per_vertex is a power of two, and is known at compile
2111 * time, this can be optimized to:
2113 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2115 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2116 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2117 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2118 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2119 unsigned log2_bits_per_vertex
=
2120 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2121 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2123 if (per_slot_offset
.file
!= BAD_FILE
) {
2124 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2125 * the appropriate OWord within the control data header.
2127 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2130 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2131 * write to the appropriate DWORD within the OWORD.
2133 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2134 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2135 channel_mask
= intexp2(fwa_bld
, channel
);
2136 /* Then the channel masks need to be in bits 23:16. */
2137 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2140 /* Store the control data bits in the message payload and send it. */
2142 if (channel_mask
.file
!= BAD_FILE
)
2143 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2144 if (per_slot_offset
.file
!= BAD_FILE
)
2147 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2148 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2150 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2151 if (per_slot_offset
.file
!= BAD_FILE
)
2152 sources
[i
++] = per_slot_offset
;
2153 if (channel_mask
.file
!= BAD_FILE
)
2154 sources
[i
++] = channel_mask
;
2156 sources
[i
++] = this->control_data_bits
;
2159 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2160 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2162 /* We need to increment Global Offset by 256-bits to make room for
2163 * Broadwell's extra "Vertex Count" payload at the beginning of the
2164 * URB entry. Since this is an OWord message, Global Offset is counted
2165 * in 128-bit units, so we must set it to 2.
2167 if (gs_prog_data
->static_vertex_count
== -1)
2172 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2175 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2177 /* Note: we are calling this *before* increasing vertex_count, so
2178 * this->vertex_count == vertex_count - 1 in the formula above.
2181 /* Stream mode uses 2 bits per vertex */
2182 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2184 /* Must be a valid stream */
2185 assert(stream_id
< MAX_VERTEX_STREAMS
);
2187 /* Control data bits are initialized to 0 so we don't have to set any
2188 * bits when sending vertices to stream 0.
2193 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2195 /* reg::sid = stream_id */
2196 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2197 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2199 /* reg:shift_count = 2 * (vertex_count - 1) */
2200 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2201 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2203 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2204 * attention to the lower 5 bits of its second source argument, so on this
2205 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2206 * stream_id << ((2 * (vertex_count - 1)) % 32).
2208 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2209 abld
.SHL(mask
, sid
, shift_count
);
2210 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2214 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2217 assert(stage
== MESA_SHADER_GEOMETRY
);
2219 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2221 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2222 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2224 /* Haswell and later hardware ignores the "Render Stream Select" bits
2225 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2226 * and instead sends all primitives down the pipeline for rasterization.
2227 * If the SOL stage is enabled, "Render Stream Select" is honored and
2228 * primitives bound to non-zero streams are discarded after stream output.
2230 * Since the only purpose of primives sent to non-zero streams is to
2231 * be recorded by transform feedback, we can simply discard all geometry
2232 * bound to these streams when transform feedback is disabled.
2234 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2237 /* If we're outputting 32 control data bits or less, then we can wait
2238 * until the shader is over to output them all. Otherwise we need to
2239 * output them as we go. Now is the time to do it, since we're about to
2240 * output the vertex_count'th vertex, so it's guaranteed that the
2241 * control data bits associated with the (vertex_count - 1)th vertex are
2244 if (gs_compile
->control_data_header_size_bits
> 32) {
2245 const fs_builder abld
=
2246 bld
.annotate("emit vertex: emit control data bits");
2248 /* Only emit control data bits if we've finished accumulating a batch
2249 * of 32 bits. This is the case when:
2251 * (vertex_count * bits_per_vertex) % 32 == 0
2253 * (in other words, when the last 5 bits of vertex_count *
2254 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2255 * integer n (which is always the case, since bits_per_vertex is
2256 * always 1 or 2), this is equivalent to requiring that the last 5-n
2257 * bits of vertex_count are 0:
2259 * vertex_count & (2^(5-n) - 1) == 0
2261 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2264 * vertex_count & (32 / bits_per_vertex - 1) == 0
2266 * TODO: If vertex_count is an immediate, we could do some of this math
2267 * at compile time...
2270 abld
.AND(bld
.null_reg_d(), vertex_count
,
2271 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2272 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2274 abld
.IF(BRW_PREDICATE_NORMAL
);
2275 /* If vertex_count is 0, then no control data bits have been
2276 * accumulated yet, so we can skip emitting them.
2278 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2279 BRW_CONDITIONAL_NEQ
);
2280 abld
.IF(BRW_PREDICATE_NORMAL
);
2281 emit_gs_control_data_bits(vertex_count
);
2282 abld
.emit(BRW_OPCODE_ENDIF
);
2284 /* Reset control_data_bits to 0 so we can start accumulating a new
2287 * Note: in the case where vertex_count == 0, this neutralizes the
2288 * effect of any call to EndPrimitive() that the shader may have
2289 * made before outputting its first vertex.
2291 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2292 inst
->force_writemask_all
= true;
2293 abld
.emit(BRW_OPCODE_ENDIF
);
2296 emit_urb_writes(vertex_count
);
2298 /* In stream mode we have to set control data bits for all vertices
2299 * unless we have disabled control data bits completely (which we do
2300 * do for GL_POINTS outputs that don't use streams).
2302 if (gs_compile
->control_data_header_size_bits
> 0 &&
2303 gs_prog_data
->control_data_format
==
2304 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2305 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2310 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2311 const nir_src
&vertex_src
,
2312 unsigned base_offset
,
2313 const nir_src
&offset_src
,
2314 unsigned num_components
,
2315 unsigned first_component
)
2317 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2318 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2320 /* TODO: figure out push input layout for invocations == 1 */
2321 /* TODO: make this work with 64-bit inputs */
2322 if (gs_prog_data
->invocations
== 1 &&
2323 type_sz(dst
.type
) <= 4 &&
2324 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2325 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2326 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2327 nir_src_as_uint(vertex_src
) * push_reg_count
;
2328 for (unsigned i
= 0; i
< num_components
; i
++) {
2329 bld
.MOV(offset(dst
, bld
, i
),
2330 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2335 /* Resort to the pull model. Ensure the VUE handles are provided. */
2336 assert(gs_prog_data
->base
.include_vue_handles
);
2338 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2339 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2341 if (gs_prog_data
->invocations
== 1) {
2342 if (nir_src_is_const(vertex_src
)) {
2343 /* The vertex index is constant; just select the proper URB handle. */
2345 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2346 BRW_REGISTER_TYPE_UD
);
2348 /* The vertex index is non-constant. We need to use indirect
2349 * addressing to fetch the proper URB handle.
2351 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2352 * indicating that channel <n> should read the handle from
2353 * DWord <n>. We convert that to bytes by multiplying by 4.
2355 * Next, we convert the vertex index to bytes by multiplying
2356 * by 32 (shifting by 5), and add the two together. This is
2357 * the final indirect byte offset.
2359 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2360 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2361 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2362 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2364 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2365 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2366 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2367 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2368 /* Convert vertex_index to bytes (multiply by 32) */
2369 bld
.SHL(vertex_offset_bytes
,
2370 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2372 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2374 /* Use first_icp_handle as the base offset. There is one register
2375 * of URB handles per vertex, so inform the register allocator that
2376 * we might read up to nir->info.gs.vertices_in registers.
2378 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2379 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2380 fs_reg(icp_offset_bytes
),
2381 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2384 assert(gs_prog_data
->invocations
> 1);
2386 if (nir_src_is_const(vertex_src
)) {
2387 unsigned vertex
= nir_src_as_uint(vertex_src
);
2388 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2390 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2391 BRW_REGISTER_TYPE_UD
));
2393 /* The vertex index is non-constant. We need to use indirect
2394 * addressing to fetch the proper URB handle.
2397 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2399 /* Convert vertex_index to bytes (multiply by 4) */
2400 bld
.SHL(icp_offset_bytes
,
2401 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2404 /* Use first_icp_handle as the base offset. There is one DWord
2405 * of URB handles per vertex, so inform the register allocator that
2406 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2408 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2409 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2410 fs_reg(icp_offset_bytes
),
2411 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2418 fs_reg tmp_dst
= dst
;
2419 fs_reg indirect_offset
= get_nir_src(offset_src
);
2420 unsigned num_iterations
= 1;
2421 unsigned orig_num_components
= num_components
;
2423 if (type_sz(dst
.type
) == 8) {
2424 if (num_components
> 2) {
2428 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2430 first_component
= first_component
/ 2;
2433 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2434 if (nir_src_is_const(offset_src
)) {
2435 /* Constant indexing - use global offset. */
2436 if (first_component
!= 0) {
2437 unsigned read_components
= num_components
+ first_component
;
2438 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2439 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2440 inst
->size_written
= read_components
*
2441 tmp
.component_size(inst
->exec_size
);
2442 for (unsigned i
= 0; i
< num_components
; i
++) {
2443 bld
.MOV(offset(tmp_dst
, bld
, i
),
2444 offset(tmp
, bld
, i
+ first_component
));
2447 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2449 inst
->size_written
= num_components
*
2450 tmp_dst
.component_size(inst
->exec_size
);
2452 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2455 /* Indirect indexing - use per-slot offsets as well. */
2456 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2457 unsigned read_components
= num_components
+ first_component
;
2458 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2459 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2460 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2461 if (first_component
!= 0) {
2462 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2464 inst
->size_written
= read_components
*
2465 tmp
.component_size(inst
->exec_size
);
2466 for (unsigned i
= 0; i
< num_components
; i
++) {
2467 bld
.MOV(offset(tmp_dst
, bld
, i
),
2468 offset(tmp
, bld
, i
+ first_component
));
2471 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2473 inst
->size_written
= num_components
*
2474 tmp_dst
.component_size(inst
->exec_size
);
2476 inst
->offset
= base_offset
;
2480 if (type_sz(dst
.type
) == 8) {
2481 shuffle_from_32bit_read(bld
,
2482 offset(dst
, bld
, iter
* 2),
2483 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2488 if (num_iterations
> 1) {
2489 num_components
= orig_num_components
- 2;
2490 if(nir_src_is_const(offset_src
)) {
2493 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2494 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2495 indirect_offset
= new_indirect
;
2502 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2504 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2506 if (nir_src_is_const(*offset_src
)) {
2507 /* The only constant offset we should find is 0. brw_nir.c's
2508 * add_const_offset_to_base() will fold other constant offsets
2509 * into instr->const_index[0].
2511 assert(nir_src_as_uint(*offset_src
) == 0);
2515 return get_nir_src(*offset_src
);
2519 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2520 nir_intrinsic_instr
*instr
)
2522 assert(stage
== MESA_SHADER_VERTEX
);
2525 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2526 dest
= get_nir_dest(instr
->dest
);
2528 switch (instr
->intrinsic
) {
2529 case nir_intrinsic_load_vertex_id
:
2530 case nir_intrinsic_load_base_vertex
:
2531 unreachable("should be lowered by nir_lower_system_values()");
2533 case nir_intrinsic_load_input
: {
2534 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2535 unsigned first_component
= nir_intrinsic_component(instr
);
2536 unsigned num_components
= instr
->num_components
;
2538 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2540 if (type_sz(dest
.type
) == 8)
2541 first_component
/= 2;
2543 /* For 16-bit support maybe a temporary will be needed to copy from
2546 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2547 first_component
, num_components
);
2551 case nir_intrinsic_load_vertex_id_zero_base
:
2552 case nir_intrinsic_load_instance_id
:
2553 case nir_intrinsic_load_base_instance
:
2554 case nir_intrinsic_load_draw_id
:
2555 case nir_intrinsic_load_first_vertex
:
2556 case nir_intrinsic_load_is_indexed_draw
:
2557 unreachable("lowered by brw_nir_lower_vs_inputs");
2560 nir_emit_intrinsic(bld
, instr
);
2566 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2567 nir_intrinsic_instr
*instr
)
2569 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2570 const nir_src
&vertex_src
= instr
->src
[0];
2571 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2574 if (nir_src_is_const(vertex_src
)) {
2575 /* Emit a MOV to resolve <0,1,0> regioning. */
2576 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2577 unsigned vertex
= nir_src_as_uint(vertex_src
);
2579 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2580 BRW_REGISTER_TYPE_UD
));
2581 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2582 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2583 /* For the common case of only 1 instance, an array index of
2584 * gl_InvocationID means reading g1. Skip all the indirect work.
2586 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2588 /* The vertex index is non-constant. We need to use indirect
2589 * addressing to fetch the proper URB handle.
2591 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2593 /* Each ICP handle is a single DWord (4 bytes) */
2594 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2595 bld
.SHL(vertex_offset_bytes
,
2596 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2599 /* Start at g1. We might read up to 4 registers. */
2600 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2601 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2602 brw_imm_ud(4 * REG_SIZE
));
2609 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2610 nir_intrinsic_instr
*instr
)
2612 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2613 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2614 const nir_src
&vertex_src
= instr
->src
[0];
2616 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2618 if (nir_src_is_const(vertex_src
)) {
2619 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2620 nir_src_as_uint(vertex_src
), 0),
2621 BRW_REGISTER_TYPE_UD
));
2624 /* The vertex index is non-constant. We need to use indirect
2625 * addressing to fetch the proper URB handle.
2627 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2628 * indicating that channel <n> should read the handle from
2629 * DWord <n>. We convert that to bytes by multiplying by 4.
2631 * Next, we convert the vertex index to bytes by multiplying
2632 * by 32 (shifting by 5), and add the two together. This is
2633 * the final indirect byte offset.
2635 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2636 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2637 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2638 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2639 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2641 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2642 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2643 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2644 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2645 /* Convert vertex_index to bytes (multiply by 32) */
2646 bld
.SHL(vertex_offset_bytes
,
2647 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2649 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2651 /* Use first_icp_handle as the base offset. There is one register
2652 * of URB handles per vertex, so inform the register allocator that
2653 * we might read up to nir->info.gs.vertices_in registers.
2655 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2656 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2657 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2663 fs_visitor::get_tcs_output_urb_handle()
2665 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2667 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2668 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2670 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2671 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2676 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2677 nir_intrinsic_instr
*instr
)
2679 assert(stage
== MESA_SHADER_TESS_CTRL
);
2680 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2681 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2682 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2685 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2688 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2689 dst
= get_nir_dest(instr
->dest
);
2691 switch (instr
->intrinsic
) {
2692 case nir_intrinsic_load_primitive_id
:
2693 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2694 : brw_vec1_grf(0, 1)));
2696 case nir_intrinsic_load_invocation_id
:
2697 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2699 case nir_intrinsic_load_patch_vertices_in
:
2700 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2701 brw_imm_d(tcs_key
->input_vertices
));
2704 case nir_intrinsic_barrier
: {
2705 if (tcs_prog_data
->instances
== 1)
2708 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2709 fs_reg m0_2
= component(m0
, 2);
2711 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2713 /* Zero the message header */
2714 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2716 if (devinfo
->gen
< 11) {
2717 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2718 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2719 brw_imm_ud(INTEL_MASK(16, 13)));
2721 /* Shift it up to bits 27:24. */
2722 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2724 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2725 brw_imm_ud(INTEL_MASK(30, 24)));
2728 /* Set the Barrier Count and the enable bit */
2729 if (devinfo
->gen
< 11) {
2730 chanbld
.OR(m0_2
, m0_2
,
2731 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2733 chanbld
.OR(m0_2
, m0_2
,
2734 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2737 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2741 case nir_intrinsic_load_input
:
2742 unreachable("nir_lower_io should never give us these.");
2745 case nir_intrinsic_load_per_vertex_input
: {
2746 fs_reg indirect_offset
= get_indirect_offset(instr
);
2747 unsigned imm_offset
= instr
->const_index
[0];
2751 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2752 : get_tcs_single_patch_icp_handle(bld
, instr
);
2754 /* We can only read two double components with each URB read, so
2755 * we send two read messages in that case, each one loading up to
2756 * two double components.
2758 unsigned num_iterations
= 1;
2759 unsigned num_components
= instr
->num_components
;
2760 unsigned first_component
= nir_intrinsic_component(instr
);
2761 fs_reg orig_dst
= dst
;
2762 if (type_sz(dst
.type
) == 8) {
2763 first_component
= first_component
/ 2;
2764 if (instr
->num_components
> 2) {
2769 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2773 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2774 if (indirect_offset
.file
== BAD_FILE
) {
2775 /* Constant indexing - use global offset. */
2776 if (first_component
!= 0) {
2777 unsigned read_components
= num_components
+ first_component
;
2778 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2779 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2780 for (unsigned i
= 0; i
< num_components
; i
++) {
2781 bld
.MOV(offset(dst
, bld
, i
),
2782 offset(tmp
, bld
, i
+ first_component
));
2785 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2787 inst
->offset
= imm_offset
;
2790 /* Indirect indexing - use per-slot offsets as well. */
2791 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2792 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2793 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2794 if (first_component
!= 0) {
2795 unsigned read_components
= num_components
+ first_component
;
2796 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2797 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2799 for (unsigned i
= 0; i
< num_components
; i
++) {
2800 bld
.MOV(offset(dst
, bld
, i
),
2801 offset(tmp
, bld
, i
+ first_component
));
2804 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2807 inst
->offset
= imm_offset
;
2810 inst
->size_written
= (num_components
+ first_component
) *
2811 inst
->dst
.component_size(inst
->exec_size
);
2813 /* If we are reading 64-bit data using 32-bit read messages we need
2814 * build proper 64-bit data elements by shuffling the low and high
2815 * 32-bit components around like we do for other things like UBOs
2818 if (type_sz(dst
.type
) == 8) {
2819 shuffle_from_32bit_read(bld
,
2820 offset(orig_dst
, bld
, iter
* 2),
2821 retype(dst
, BRW_REGISTER_TYPE_D
),
2825 /* Copy the temporary to the destination to deal with writemasking.
2827 * Also attempt to deal with gl_PointSize being in the .w component.
2829 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2830 assert(type_sz(dst
.type
) < 8);
2831 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2832 inst
->size_written
= 4 * REG_SIZE
;
2833 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2836 /* If we are loading double data and we need a second read message
2837 * adjust the write offset
2839 if (num_iterations
> 1) {
2840 num_components
= instr
->num_components
- 2;
2847 case nir_intrinsic_load_output
:
2848 case nir_intrinsic_load_per_vertex_output
: {
2849 fs_reg indirect_offset
= get_indirect_offset(instr
);
2850 unsigned imm_offset
= instr
->const_index
[0];
2851 unsigned first_component
= nir_intrinsic_component(instr
);
2853 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2856 if (indirect_offset
.file
== BAD_FILE
) {
2857 /* This MOV replicates the output handle to all enabled channels
2858 * is SINGLE_PATCH mode.
2860 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2861 bld
.MOV(patch_handle
, output_handles
);
2864 if (first_component
!= 0) {
2865 unsigned read_components
=
2866 instr
->num_components
+ first_component
;
2867 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2868 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2870 inst
->size_written
= read_components
* REG_SIZE
;
2871 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2872 bld
.MOV(offset(dst
, bld
, i
),
2873 offset(tmp
, bld
, i
+ first_component
));
2876 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2878 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2880 inst
->offset
= imm_offset
;
2884 /* Indirect indexing - use per-slot offsets as well. */
2885 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2886 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2887 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2888 if (first_component
!= 0) {
2889 unsigned read_components
=
2890 instr
->num_components
+ first_component
;
2891 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2892 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2894 inst
->size_written
= read_components
* REG_SIZE
;
2895 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2896 bld
.MOV(offset(dst
, bld
, i
),
2897 offset(tmp
, bld
, i
+ first_component
));
2900 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2902 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2904 inst
->offset
= imm_offset
;
2910 case nir_intrinsic_store_output
:
2911 case nir_intrinsic_store_per_vertex_output
: {
2912 fs_reg value
= get_nir_src(instr
->src
[0]);
2913 bool is_64bit
= (instr
->src
[0].is_ssa
?
2914 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2915 fs_reg indirect_offset
= get_indirect_offset(instr
);
2916 unsigned imm_offset
= instr
->const_index
[0];
2917 unsigned mask
= instr
->const_index
[1];
2918 unsigned header_regs
= 0;
2919 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2922 srcs
[header_regs
++] = output_handles
;
2924 if (indirect_offset
.file
!= BAD_FILE
) {
2925 srcs
[header_regs
++] = indirect_offset
;
2931 unsigned num_components
= util_last_bit(mask
);
2934 /* We can only pack two 64-bit components in a single message, so send
2935 * 2 messages if we have more components
2937 unsigned num_iterations
= 1;
2938 unsigned iter_components
= num_components
;
2939 unsigned first_component
= nir_intrinsic_component(instr
);
2941 first_component
= first_component
/ 2;
2942 if (instr
->num_components
> 2) {
2944 iter_components
= 2;
2948 mask
= mask
<< first_component
;
2950 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2951 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2952 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2953 opcode
= indirect_offset
.file
!= BAD_FILE
?
2954 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2955 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2956 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2957 /* Expand the 64-bit mask to 32-bit channels. We only handle
2958 * two channels in each iteration, so we only care about X/Y.
2960 unsigned mask32
= 0;
2961 if (mask
& WRITEMASK_X
)
2962 mask32
|= WRITEMASK_XY
;
2963 if (mask
& WRITEMASK_Y
)
2964 mask32
|= WRITEMASK_ZW
;
2966 /* If the mask does not include any of the channels X or Y there
2967 * is nothing to do in this iteration. Move on to the next couple
2968 * of 64-bit channels.
2976 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2977 opcode
= indirect_offset
.file
!= BAD_FILE
?
2978 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2979 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2981 opcode
= indirect_offset
.file
!= BAD_FILE
?
2982 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2983 SHADER_OPCODE_URB_WRITE_SIMD8
;
2986 for (unsigned i
= 0; i
< iter_components
; i
++) {
2987 if (!(mask
& (1 << (i
+ first_component
))))
2991 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2993 /* We need to shuffle the 64-bit data to match the layout
2994 * expected by our 32-bit URB write messages. We use a temporary
2997 unsigned channel
= iter
* 2 + i
;
2998 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
3000 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
3001 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
3002 offset(dest
, bld
, 1);
3007 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
3008 (is_64bit
? 2 * first_component
: first_component
);
3010 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
3011 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
3013 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
3014 inst
->offset
= imm_offset
;
3017 /* If this is a 64-bit attribute, select the next two 64-bit channels
3018 * to be handled in the next iteration.
3029 nir_emit_intrinsic(bld
, instr
);
3035 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
3036 nir_intrinsic_instr
*instr
)
3038 assert(stage
== MESA_SHADER_TESS_EVAL
);
3039 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
3042 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3043 dest
= get_nir_dest(instr
->dest
);
3045 switch (instr
->intrinsic
) {
3046 case nir_intrinsic_load_primitive_id
:
3047 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
3049 case nir_intrinsic_load_tess_coord
:
3050 /* gl_TessCoord is part of the payload in g1-3 */
3051 for (unsigned i
= 0; i
< 3; i
++) {
3052 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
3056 case nir_intrinsic_load_input
:
3057 case nir_intrinsic_load_per_vertex_input
: {
3058 fs_reg indirect_offset
= get_indirect_offset(instr
);
3059 unsigned imm_offset
= instr
->const_index
[0];
3060 unsigned first_component
= nir_intrinsic_component(instr
);
3062 if (type_sz(dest
.type
) == 8) {
3063 first_component
= first_component
/ 2;
3067 if (indirect_offset
.file
== BAD_FILE
) {
3068 /* Arbitrarily only push up to 32 vec4 slots worth of data,
3069 * which is 16 registers (since each holds 2 vec4 slots).
3071 unsigned slot_count
= 1;
3072 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
3075 const unsigned max_push_slots
= 32;
3076 if (imm_offset
+ slot_count
<= max_push_slots
) {
3077 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
3078 for (int i
= 0; i
< instr
->num_components
; i
++) {
3079 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
3080 i
+ first_component
;
3081 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
3084 tes_prog_data
->base
.urb_read_length
=
3085 MAX2(tes_prog_data
->base
.urb_read_length
,
3086 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
3088 /* Replicate the patch handle to all enabled channels */
3089 const fs_reg srcs
[] = {
3090 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3092 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3093 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3095 if (first_component
!= 0) {
3096 unsigned read_components
=
3097 instr
->num_components
+ first_component
;
3098 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3099 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3101 inst
->size_written
= read_components
* REG_SIZE
;
3102 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3103 bld
.MOV(offset(dest
, bld
, i
),
3104 offset(tmp
, bld
, i
+ first_component
));
3107 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3109 inst
->size_written
= instr
->num_components
* REG_SIZE
;
3112 inst
->offset
= imm_offset
;
3115 /* Indirect indexing - use per-slot offsets as well. */
3117 /* We can only read two double components with each URB read, so
3118 * we send two read messages in that case, each one loading up to
3119 * two double components.
3121 unsigned num_iterations
= 1;
3122 unsigned num_components
= instr
->num_components
;
3123 fs_reg orig_dest
= dest
;
3124 if (type_sz(dest
.type
) == 8) {
3125 if (instr
->num_components
> 2) {
3129 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3133 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3134 const fs_reg srcs
[] = {
3135 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3138 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3139 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3141 if (first_component
!= 0) {
3142 unsigned read_components
=
3143 num_components
+ first_component
;
3144 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3145 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3147 for (unsigned i
= 0; i
< num_components
; i
++) {
3148 bld
.MOV(offset(dest
, bld
, i
),
3149 offset(tmp
, bld
, i
+ first_component
));
3152 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3156 inst
->offset
= imm_offset
;
3157 inst
->size_written
= (num_components
+ first_component
) *
3158 inst
->dst
.component_size(inst
->exec_size
);
3160 /* If we are reading 64-bit data using 32-bit read messages we need
3161 * build proper 64-bit data elements by shuffling the low and high
3162 * 32-bit components around like we do for other things like UBOs
3165 if (type_sz(dest
.type
) == 8) {
3166 shuffle_from_32bit_read(bld
,
3167 offset(orig_dest
, bld
, iter
* 2),
3168 retype(dest
, BRW_REGISTER_TYPE_D
),
3172 /* If we are loading double data and we need a second read message
3175 if (num_iterations
> 1) {
3176 num_components
= instr
->num_components
- 2;
3184 nir_emit_intrinsic(bld
, instr
);
3190 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3191 nir_intrinsic_instr
*instr
)
3193 assert(stage
== MESA_SHADER_GEOMETRY
);
3194 fs_reg indirect_offset
;
3197 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3198 dest
= get_nir_dest(instr
->dest
);
3200 switch (instr
->intrinsic
) {
3201 case nir_intrinsic_load_primitive_id
:
3202 assert(stage
== MESA_SHADER_GEOMETRY
);
3203 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3204 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3205 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3208 case nir_intrinsic_load_input
:
3209 unreachable("load_input intrinsics are invalid for the GS stage");
3211 case nir_intrinsic_load_per_vertex_input
:
3212 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3213 instr
->src
[1], instr
->num_components
,
3214 nir_intrinsic_component(instr
));
3217 case nir_intrinsic_emit_vertex_with_counter
:
3218 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3221 case nir_intrinsic_end_primitive_with_counter
:
3222 emit_gs_end_primitive(instr
->src
[0]);
3225 case nir_intrinsic_set_vertex_count
:
3226 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3229 case nir_intrinsic_load_invocation_id
: {
3230 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3231 assert(val
.file
!= BAD_FILE
);
3232 dest
.type
= val
.type
;
3238 nir_emit_intrinsic(bld
, instr
);
3244 * Fetch the current render target layer index.
3247 fetch_render_target_array_index(const fs_builder
&bld
)
3249 if (bld
.shader
->devinfo
->gen
>= 6) {
3250 /* The render target array index is provided in the thread payload as
3251 * bits 26:16 of r0.0.
3253 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3254 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3258 /* Pre-SNB we only ever render into the first layer of the framebuffer
3259 * since layered rendering is not implemented.
3261 return brw_imm_ud(0);
3266 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3267 * framebuffer at the current fragment coordinates and sample index.
3270 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3273 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3275 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3276 const brw_wm_prog_key
*wm_key
=
3277 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3278 assert(!wm_key
->coherent_fb_fetch
);
3279 const struct brw_wm_prog_data
*wm_prog_data
=
3280 brw_wm_prog_data(stage_prog_data
);
3282 /* Calculate the surface index relative to the start of the texture binding
3283 * table block, since that's what the texturing messages expect.
3285 const unsigned surface
= target
+
3286 wm_prog_data
->binding_table
.render_target_read_start
-
3287 wm_prog_data
->base
.binding_table
.texture_start
;
3289 /* Calculate the fragment coordinates. */
3290 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3291 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3292 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3293 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3295 /* Calculate the sample index and MCS payload when multisampling. Luckily
3296 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3297 * shouldn't be necessary to recompile based on whether the framebuffer is
3300 if (wm_key
->multisample_fbo
&&
3301 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3302 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3304 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3305 const fs_reg mcs
= wm_key
->multisample_fbo
?
3306 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3308 /* Use either a normal or a CMS texel fetch message depending on whether
3309 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3310 * message just in case the framebuffer uses 16x multisampling, it should
3311 * be equivalent to the normal CMS fetch for lower multisampling modes.
3313 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3314 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3315 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3317 /* Emit the instruction. */
3318 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3319 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3320 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3321 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3322 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3323 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3324 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3325 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3326 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3328 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3329 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3335 * Actual coherent framebuffer read implemented using the native render target
3336 * read message. Requires SKL+.
3339 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3341 assert(bld
.shader
->devinfo
->gen
>= 9);
3342 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3343 inst
->target
= target
;
3344 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3350 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3352 if (n
&& regs
[0].file
!= BAD_FILE
) {
3356 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3358 for (unsigned i
= 0; i
< n
; i
++)
3366 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3368 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3369 const brw_wm_prog_key
*const key
=
3370 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3371 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3372 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3374 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3375 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3377 else if (l
== FRAG_RESULT_COLOR
)
3378 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3379 MAX2(key
->nr_color_regions
, 1));
3381 else if (l
== FRAG_RESULT_DEPTH
)
3382 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3384 else if (l
== FRAG_RESULT_STENCIL
)
3385 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3387 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3388 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3390 else if (l
>= FRAG_RESULT_DATA0
&&
3391 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3392 return alloc_temporary(v
->bld
, 4,
3393 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3396 unreachable("Invalid location");
3400 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3401 nir_intrinsic_instr
*instr
)
3403 assert(stage
== MESA_SHADER_FRAGMENT
);
3406 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3407 dest
= get_nir_dest(instr
->dest
);
3409 switch (instr
->intrinsic
) {
3410 case nir_intrinsic_load_front_face
:
3411 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3412 *emit_frontfacing_interpolation());
3415 case nir_intrinsic_load_sample_pos
: {
3416 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3417 assert(sample_pos
.file
!= BAD_FILE
);
3418 dest
.type
= sample_pos
.type
;
3419 bld
.MOV(dest
, sample_pos
);
3420 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3424 case nir_intrinsic_load_layer_id
:
3425 dest
.type
= BRW_REGISTER_TYPE_UD
;
3426 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3429 case nir_intrinsic_load_helper_invocation
:
3430 case nir_intrinsic_load_sample_mask_in
:
3431 case nir_intrinsic_load_sample_id
: {
3432 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3433 fs_reg val
= nir_system_values
[sv
];
3434 assert(val
.file
!= BAD_FILE
);
3435 dest
.type
= val
.type
;
3440 case nir_intrinsic_store_output
: {
3441 const fs_reg src
= get_nir_src(instr
->src
[0]);
3442 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3443 const unsigned location
= nir_intrinsic_base(instr
) +
3444 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3445 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3448 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3449 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3450 offset(src
, bld
, j
));
3455 case nir_intrinsic_load_output
: {
3456 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3457 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3458 assert(l
>= FRAG_RESULT_DATA0
);
3459 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3460 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3461 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3463 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3464 emit_coherent_fb_read(bld
, tmp
, target
);
3466 emit_non_coherent_fb_read(bld
, tmp
, target
);
3468 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3469 bld
.MOV(offset(dest
, bld
, j
),
3470 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3476 case nir_intrinsic_discard
:
3477 case nir_intrinsic_discard_if
: {
3478 /* We track our discarded pixels in f0.1. By predicating on it, we can
3479 * update just the flag bits that aren't yet discarded. If there's no
3480 * condition, we emit a CMP of g0 != g0, so all currently executing
3481 * channels will get turned off.
3484 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3485 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3486 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3488 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3489 BRW_REGISTER_TYPE_UW
));
3490 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3492 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3493 cmp
->flag_subreg
= 1;
3495 if (devinfo
->gen
>= 6) {
3496 emit_discard_jump();
3499 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3503 case nir_intrinsic_load_input
: {
3504 /* load_input is only used for flat inputs */
3505 unsigned base
= nir_intrinsic_base(instr
);
3506 unsigned comp
= nir_intrinsic_component(instr
);
3507 unsigned num_components
= instr
->num_components
;
3508 fs_reg orig_dest
= dest
;
3509 enum brw_reg_type type
= dest
.type
;
3511 /* Special case fields in the VUE header */
3512 if (base
== VARYING_SLOT_LAYER
)
3514 else if (base
== VARYING_SLOT_VIEWPORT
)
3517 if (nir_dest_bit_size(instr
->dest
) == 64) {
3518 /* const_index is in 32-bit type size units that could not be aligned
3519 * with DF. We need to read the double vector as if it was a float
3520 * vector of twice the number of components to fetch the right data.
3522 type
= BRW_REGISTER_TYPE_F
;
3523 num_components
*= 2;
3524 dest
= bld
.vgrf(type
, num_components
);
3527 for (unsigned int i
= 0; i
< num_components
; i
++) {
3528 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3529 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3532 if (nir_dest_bit_size(instr
->dest
) == 64) {
3533 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3534 instr
->num_components
);
3539 case nir_intrinsic_load_barycentric_pixel
:
3540 case nir_intrinsic_load_barycentric_centroid
:
3541 case nir_intrinsic_load_barycentric_sample
:
3542 /* Do nothing - load_interpolated_input handling will handle it later. */
3545 case nir_intrinsic_load_barycentric_at_sample
: {
3546 const glsl_interp_mode interpolation
=
3547 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3549 if (nir_src_is_const(instr
->src
[0])) {
3550 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3552 emit_pixel_interpolater_send(bld
,
3553 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3556 brw_imm_ud(msg_data
),
3559 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3560 BRW_REGISTER_TYPE_UD
);
3562 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3563 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3564 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3565 bld
.exec_all().group(1, 0)
3566 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3567 emit_pixel_interpolater_send(bld
,
3568 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3574 /* Make a loop that sends a message to the pixel interpolater
3575 * for the sample number in each live channel. If there are
3576 * multiple channels with the same sample number then these
3577 * will be handled simultaneously with a single interation of
3580 bld
.emit(BRW_OPCODE_DO
);
3582 /* Get the next live sample number into sample_id_reg */
3583 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3585 /* Set the flag register so that we can perform the send
3586 * message on all channels that have the same sample number
3588 bld
.CMP(bld
.null_reg_ud(),
3589 sample_src
, sample_id
,
3590 BRW_CONDITIONAL_EQ
);
3591 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3592 bld
.exec_all().group(1, 0)
3593 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3595 emit_pixel_interpolater_send(bld
,
3596 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3599 component(msg_data
, 0),
3601 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3603 /* Continue the loop if there are any live channels left */
3604 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3606 bld
.emit(BRW_OPCODE_WHILE
));
3612 case nir_intrinsic_load_barycentric_at_offset
: {
3613 const glsl_interp_mode interpolation
=
3614 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3616 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3619 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3620 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3621 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3623 emit_pixel_interpolater_send(bld
,
3624 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3627 brw_imm_ud(off_x
| (off_y
<< 4)),
3630 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3631 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3632 BRW_REGISTER_TYPE_F
);
3633 for (int i
= 0; i
< 2; i
++) {
3634 fs_reg temp
= vgrf(glsl_type::float_type
);
3635 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3636 fs_reg itemp
= vgrf(glsl_type::int_type
);
3638 bld
.MOV(itemp
, temp
);
3640 /* Clamp the upper end of the range to +7/16.
3641 * ARB_gpu_shader5 requires that we support a maximum offset
3642 * of +0.5, which isn't representable in a S0.4 value -- if
3643 * we didn't clamp it, we'd end up with -8/16, which is the
3644 * opposite of what the shader author wanted.
3646 * This is legal due to ARB_gpu_shader5's quantization
3649 * "Not all values of <offset> may be supported; x and y
3650 * offsets may be rounded to fixed-point values with the
3651 * number of fraction bits given by the
3652 * implementation-dependent constant
3653 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3655 set_condmod(BRW_CONDITIONAL_L
,
3656 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3659 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3660 emit_pixel_interpolater_send(bld
,
3670 case nir_intrinsic_load_interpolated_input
: {
3671 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3672 emit_fragcoord_interpolation(dest
);
3676 assert(instr
->src
[0].ssa
&&
3677 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3678 nir_intrinsic_instr
*bary_intrinsic
=
3679 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3680 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3681 enum glsl_interp_mode interp_mode
=
3682 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3685 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3686 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3687 /* Use the result of the PI message */
3688 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3690 /* Use the delta_xy values computed from the payload */
3691 enum brw_barycentric_mode bary
=
3692 brw_barycentric_mode(interp_mode
, bary_intrin
);
3694 dst_xy
= this->delta_xy
[bary
];
3697 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3699 interp_reg(nir_intrinsic_base(instr
),
3700 nir_intrinsic_component(instr
) + i
);
3701 interp
.type
= BRW_REGISTER_TYPE_F
;
3702 dest
.type
= BRW_REGISTER_TYPE_F
;
3704 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3705 fs_reg tmp
= vgrf(glsl_type::float_type
);
3706 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3707 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3709 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3716 nir_emit_intrinsic(bld
, instr
);
3722 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3724 if (nir_src_is_const(instr
->src
[src
])) {
3725 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3728 else if (add_val
== -1)
3736 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3737 nir_intrinsic_instr
*instr
)
3739 assert(stage
== MESA_SHADER_COMPUTE
);
3740 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3743 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3744 dest
= get_nir_dest(instr
->dest
);
3746 switch (instr
->intrinsic
) {
3747 case nir_intrinsic_barrier
:
3749 cs_prog_data
->uses_barrier
= true;
3752 case nir_intrinsic_load_subgroup_id
:
3753 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3756 case nir_intrinsic_load_local_invocation_id
:
3757 case nir_intrinsic_load_work_group_id
: {
3758 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3759 fs_reg val
= nir_system_values
[sv
];
3760 assert(val
.file
!= BAD_FILE
);
3761 dest
.type
= val
.type
;
3762 for (unsigned i
= 0; i
< 3; i
++)
3763 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3767 case nir_intrinsic_load_num_work_groups
: {
3768 const unsigned surface
=
3769 cs_prog_data
->binding_table
.work_groups_start
;
3771 cs_prog_data
->uses_num_work_groups
= true;
3773 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3774 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3775 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3776 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3778 /* Read the 3 GLuint components of gl_NumWorkGroups */
3779 for (unsigned i
= 0; i
< 3; i
++) {
3780 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3781 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3782 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3787 case nir_intrinsic_shared_atomic_add
:
3788 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3790 case nir_intrinsic_shared_atomic_imin
:
3791 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3793 case nir_intrinsic_shared_atomic_umin
:
3794 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3796 case nir_intrinsic_shared_atomic_imax
:
3797 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3799 case nir_intrinsic_shared_atomic_umax
:
3800 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3802 case nir_intrinsic_shared_atomic_and
:
3803 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3805 case nir_intrinsic_shared_atomic_or
:
3806 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3808 case nir_intrinsic_shared_atomic_xor
:
3809 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3811 case nir_intrinsic_shared_atomic_exchange
:
3812 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3814 case nir_intrinsic_shared_atomic_comp_swap
:
3815 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3817 case nir_intrinsic_shared_atomic_fmin
:
3818 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3820 case nir_intrinsic_shared_atomic_fmax
:
3821 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3823 case nir_intrinsic_shared_atomic_fcomp_swap
:
3824 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3827 case nir_intrinsic_load_shared
: {
3828 assert(devinfo
->gen
>= 7);
3829 assert(stage
== MESA_SHADER_COMPUTE
);
3831 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3832 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3833 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3834 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3835 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3837 /* Make dest unsigned because that's what the temporary will be */
3838 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3840 /* Read the vector */
3841 if (nir_intrinsic_align(instr
) >= 4) {
3842 assert(nir_dest_bit_size(instr
->dest
) == 32);
3843 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3845 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3846 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3847 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3849 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3850 assert(nir_dest_num_components(instr
->dest
) == 1);
3851 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3853 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3854 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3855 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3856 bld
.MOV(dest
, read_result
);
3861 case nir_intrinsic_store_shared
: {
3862 assert(devinfo
->gen
>= 7);
3863 assert(stage
== MESA_SHADER_COMPUTE
);
3865 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3866 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3867 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3868 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3869 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3871 fs_reg data
= get_nir_src(instr
->src
[0]);
3872 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3874 assert(nir_intrinsic_write_mask(instr
) ==
3875 (1u << instr
->num_components
) - 1);
3876 if (nir_intrinsic_align(instr
) >= 4) {
3877 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3878 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3879 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3880 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3881 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3882 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3884 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3885 assert(nir_src_num_components(instr
->src
[0]) == 1);
3886 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3888 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3889 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3891 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3892 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3898 nir_emit_intrinsic(bld
, instr
);
3904 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3905 nir_op op
, brw_reg_type type
)
3907 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3908 switch (type_sz(type
)) {
3910 assert(type
!= BRW_REGISTER_TYPE_HF
);
3911 return retype(brw_imm_uw(value
.u16
), type
);
3913 return retype(brw_imm_ud(value
.u32
), type
);
3915 if (type
== BRW_REGISTER_TYPE_DF
)
3916 return setup_imm_df(bld
, value
.f64
);
3918 return retype(brw_imm_u64(value
.u64
), type
);
3920 unreachable("Invalid type size");
3925 brw_op_for_nir_reduction_op(nir_op op
)
3928 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3929 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3930 case nir_op_imul
: return BRW_OPCODE_MUL
;
3931 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3932 case nir_op_imin
: return BRW_OPCODE_SEL
;
3933 case nir_op_umin
: return BRW_OPCODE_SEL
;
3934 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3935 case nir_op_imax
: return BRW_OPCODE_SEL
;
3936 case nir_op_umax
: return BRW_OPCODE_SEL
;
3937 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3938 case nir_op_iand
: return BRW_OPCODE_AND
;
3939 case nir_op_ior
: return BRW_OPCODE_OR
;
3940 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3942 unreachable("Invalid reduction operation");
3946 static brw_conditional_mod
3947 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3950 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3951 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3952 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3953 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3954 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3955 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3956 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3957 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3958 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3959 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3960 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3961 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3962 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3964 unreachable("Invalid reduction operation");
3969 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3970 nir_intrinsic_instr
*instr
)
3972 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3974 if (stage_prog_data
->binding_table
.image_start
> 0) {
3975 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3976 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3978 bld
.ADD(image
, image
,
3979 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3983 return bld
.emit_uniformize(image
);
3987 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3988 nir_intrinsic_instr
*instr
)
3990 /* SSBO stores are weird in that their index is in src[1] */
3991 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3994 if (nir_src_is_const(instr
->src
[src
])) {
3995 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3996 nir_src_as_uint(instr
->src
[src
]);
3997 surf_index
= brw_imm_ud(index
);
3999 surf_index
= vgrf(glsl_type::uint_type
);
4000 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
4001 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4004 return bld
.emit_uniformize(surf_index
);
4008 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
4010 switch (nir_intrinsic_image_dim(instr
)) {
4011 case GLSL_SAMPLER_DIM_1D
:
4012 return 1 + nir_intrinsic_image_array(instr
);
4013 case GLSL_SAMPLER_DIM_2D
:
4014 case GLSL_SAMPLER_DIM_RECT
:
4015 return 2 + nir_intrinsic_image_array(instr
);
4016 case GLSL_SAMPLER_DIM_3D
:
4017 case GLSL_SAMPLER_DIM_CUBE
:
4019 case GLSL_SAMPLER_DIM_BUF
:
4021 case GLSL_SAMPLER_DIM_MS
:
4022 return 2 + nir_intrinsic_image_array(instr
);
4024 unreachable("Invalid image dimension");
4029 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
4032 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4033 dest
= get_nir_dest(instr
->dest
);
4035 switch (instr
->intrinsic
) {
4036 case nir_intrinsic_image_load
:
4037 case nir_intrinsic_image_store
:
4038 case nir_intrinsic_image_atomic_add
:
4039 case nir_intrinsic_image_atomic_min
:
4040 case nir_intrinsic_image_atomic_max
:
4041 case nir_intrinsic_image_atomic_and
:
4042 case nir_intrinsic_image_atomic_or
:
4043 case nir_intrinsic_image_atomic_xor
:
4044 case nir_intrinsic_image_atomic_exchange
:
4045 case nir_intrinsic_image_atomic_comp_swap
:
4046 case nir_intrinsic_bindless_image_load
:
4047 case nir_intrinsic_bindless_image_store
:
4048 case nir_intrinsic_bindless_image_atomic_add
:
4049 case nir_intrinsic_bindless_image_atomic_min
:
4050 case nir_intrinsic_bindless_image_atomic_max
:
4051 case nir_intrinsic_bindless_image_atomic_and
:
4052 case nir_intrinsic_bindless_image_atomic_or
:
4053 case nir_intrinsic_bindless_image_atomic_xor
:
4054 case nir_intrinsic_bindless_image_atomic_exchange
:
4055 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
4056 if (stage
== MESA_SHADER_FRAGMENT
&&
4057 instr
->intrinsic
!= nir_intrinsic_image_load
)
4058 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4060 /* Get some metadata from the image intrinsic. */
4061 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4062 const GLenum format
= nir_intrinsic_format(instr
);
4064 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4066 switch (instr
->intrinsic
) {
4067 case nir_intrinsic_image_load
:
4068 case nir_intrinsic_image_store
:
4069 case nir_intrinsic_image_atomic_add
:
4070 case nir_intrinsic_image_atomic_min
:
4071 case nir_intrinsic_image_atomic_max
:
4072 case nir_intrinsic_image_atomic_and
:
4073 case nir_intrinsic_image_atomic_or
:
4074 case nir_intrinsic_image_atomic_xor
:
4075 case nir_intrinsic_image_atomic_exchange
:
4076 case nir_intrinsic_image_atomic_comp_swap
:
4077 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4078 get_nir_image_intrinsic_image(bld
, instr
);
4083 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4084 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4088 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4089 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4090 brw_imm_ud(image_intrinsic_coord_components(instr
));
4092 /* Emit an image load, store or atomic op. */
4093 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4094 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4095 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4097 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4098 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4099 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4100 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4101 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4102 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4103 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4104 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4105 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4108 unsigned num_srcs
= info
->num_srcs
;
4110 switch (instr
->intrinsic
) {
4111 case nir_intrinsic_image_atomic_add
:
4112 case nir_intrinsic_bindless_image_atomic_add
:
4113 assert(num_srcs
== 4);
4115 op
= get_op_for_atomic_add(instr
, 3);
4117 if (op
!= BRW_AOP_ADD
)
4120 case nir_intrinsic_image_atomic_min
:
4121 case nir_intrinsic_bindless_image_atomic_min
:
4122 assert(format
== GL_R32UI
|| format
== GL_R32I
);
4123 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
4125 case nir_intrinsic_image_atomic_max
:
4126 case nir_intrinsic_bindless_image_atomic_max
:
4127 assert(format
== GL_R32UI
|| format
== GL_R32I
);
4128 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
4130 case nir_intrinsic_image_atomic_and
:
4131 case nir_intrinsic_bindless_image_atomic_and
:
4134 case nir_intrinsic_image_atomic_or
:
4135 case nir_intrinsic_bindless_image_atomic_or
:
4138 case nir_intrinsic_image_atomic_xor
:
4139 case nir_intrinsic_bindless_image_atomic_xor
:
4142 case nir_intrinsic_image_atomic_exchange
:
4143 case nir_intrinsic_bindless_image_atomic_exchange
:
4146 case nir_intrinsic_image_atomic_comp_swap
:
4147 case nir_intrinsic_bindless_image_atomic_comp_swap
:
4151 unreachable("Not reachable.");
4154 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4158 data
= get_nir_src(instr
->src
[3]);
4159 if (num_srcs
>= 5) {
4160 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4161 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4162 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4165 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4167 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4168 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4173 case nir_intrinsic_image_size
:
4174 case nir_intrinsic_bindless_image_size
: {
4175 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4176 * into will handle the binding table index for us in the geneerator.
4177 * Incidentally, this means that we can handle bindless with exactly the
4180 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4181 BRW_REGISTER_TYPE_UD
);
4182 image
= bld
.emit_uniformize(image
);
4184 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4185 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4186 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4188 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4189 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4190 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4191 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4193 /* Since the image size is always uniform, we can just emit a SIMD8
4194 * query instruction and splat the result out.
4196 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4198 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4199 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4200 tmp
, srcs
, ARRAY_SIZE(srcs
));
4201 inst
->size_written
= 4 * REG_SIZE
;
4203 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4204 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4205 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4206 offset(retype(dest
, tmp
.type
), bld
, c
),
4207 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4209 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4210 component(offset(tmp
, ubld
, c
), 0));
4216 case nir_intrinsic_image_load_raw_intel
: {
4217 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4218 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4219 get_nir_image_intrinsic_image(bld
, instr
);
4220 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4221 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4222 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4225 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4226 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4227 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4231 case nir_intrinsic_image_store_raw_intel
: {
4232 if (stage
== MESA_SHADER_FRAGMENT
)
4233 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4235 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4236 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4237 get_nir_image_intrinsic_image(bld
, instr
);
4238 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4239 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4240 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4241 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4243 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4244 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4248 case nir_intrinsic_group_memory_barrier
:
4249 case nir_intrinsic_memory_barrier_shared
:
4250 case nir_intrinsic_memory_barrier_atomic_counter
:
4251 case nir_intrinsic_memory_barrier_buffer
:
4252 case nir_intrinsic_memory_barrier_image
:
4253 case nir_intrinsic_memory_barrier
: {
4254 const fs_builder ubld
= bld
.group(8, 0);
4255 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4256 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
4257 ->size_written
= 2 * REG_SIZE
;
4261 case nir_intrinsic_shader_clock
: {
4262 /* We cannot do anything if there is an event, so ignore it for now */
4263 const fs_reg shader_clock
= get_timestamp(bld
);
4264 const fs_reg srcs
[] = { component(shader_clock
, 0),
4265 component(shader_clock
, 1) };
4266 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4270 case nir_intrinsic_image_samples
:
4271 /* The driver does not support multi-sampled images. */
4272 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4275 case nir_intrinsic_load_uniform
: {
4276 /* Offsets are in bytes but they should always aligned to
4279 assert(instr
->const_index
[0] % 4 == 0 ||
4280 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4282 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4284 if (nir_src_is_const(instr
->src
[0])) {
4285 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4286 assert(load_offset
% type_sz(dest
.type
) == 0);
4287 /* For 16-bit types we add the module of the const_index[0]
4288 * offset to access to not 32-bit aligned element
4290 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4292 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4293 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4296 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4297 BRW_REGISTER_TYPE_UD
);
4299 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4300 * go past the end of the uniform. In order to keep the n'th
4301 * component from running past, we subtract off the size of all but
4302 * one component of the vector.
4304 assert(instr
->const_index
[1] >=
4305 instr
->num_components
* (int) type_sz(dest
.type
));
4306 unsigned read_size
= instr
->const_index
[1] -
4307 (instr
->num_components
- 1) * type_sz(dest
.type
);
4309 bool supports_64bit_indirects
=
4310 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4312 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4313 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4314 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4315 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4316 indirect
, brw_imm_ud(read_size
));
4319 const unsigned num_mov_indirects
=
4320 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4321 /* We read a little bit less per MOV INDIRECT, as they are now
4322 * 32-bits ones instead of 64-bit. Fix read_size then.
4324 const unsigned read_size_32bit
= read_size
-
4325 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4326 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4327 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4328 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4329 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4330 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4331 indirect
, brw_imm_ud(read_size_32bit
));
4339 case nir_intrinsic_load_ubo
: {
4341 if (nir_src_is_const(instr
->src
[0])) {
4342 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4343 nir_src_as_uint(instr
->src
[0]);
4344 surf_index
= brw_imm_ud(index
);
4346 /* The block index is not a constant. Evaluate the index expression
4347 * per-channel and add the base UBO index; we have to select a value
4348 * from any live channel.
4350 surf_index
= vgrf(glsl_type::uint_type
);
4351 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4352 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4353 surf_index
= bld
.emit_uniformize(surf_index
);
4356 if (!nir_src_is_const(instr
->src
[1])) {
4357 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4358 BRW_REGISTER_TYPE_UD
);
4360 for (int i
= 0; i
< instr
->num_components
; i
++)
4361 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4362 base_offset
, i
* type_sz(dest
.type
));
4364 /* Even if we are loading doubles, a pull constant load will load
4365 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4366 * need to load a full dvec4 we will have to emit 2 loads. This is
4367 * similar to demote_pull_constants(), except that in that case we
4368 * see individual accesses to each component of the vector and then
4369 * we let CSE deal with duplicate loads. Here we see a vector access
4370 * and we have to split it if necessary.
4372 const unsigned type_size
= type_sz(dest
.type
);
4373 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4375 /* See if we've selected this as a push constant candidate */
4376 if (nir_src_is_const(instr
->src
[0])) {
4377 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4378 const unsigned offset_256b
= load_offset
/ 32;
4381 for (int i
= 0; i
< 4; i
++) {
4382 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4383 if (range
->block
== ubo_block
&&
4384 offset_256b
>= range
->start
&&
4385 offset_256b
< range
->start
+ range
->length
) {
4387 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4388 push_reg
.offset
= load_offset
- 32 * range
->start
;
4393 if (push_reg
.file
!= BAD_FILE
) {
4394 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4395 bld
.MOV(offset(dest
, bld
, i
),
4396 byte_offset(push_reg
, i
* type_size
));
4402 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4403 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4404 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4406 for (unsigned c
= 0; c
< instr
->num_components
;) {
4407 const unsigned base
= load_offset
+ c
* type_size
;
4408 /* Number of usable components in the next block-aligned load. */
4409 const unsigned count
= MIN2(instr
->num_components
- c
,
4410 (block_sz
- base
% block_sz
) / type_size
);
4412 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4413 packed_consts
, surf_index
,
4414 brw_imm_ud(base
& ~(block_sz
- 1)));
4416 const fs_reg consts
=
4417 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4420 for (unsigned d
= 0; d
< count
; d
++)
4421 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4429 case nir_intrinsic_load_global
: {
4430 assert(devinfo
->gen
>= 8);
4432 if (nir_intrinsic_align(instr
) >= 4) {
4433 assert(nir_dest_bit_size(instr
->dest
) == 32);
4434 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4436 get_nir_src(instr
->src
[0]), /* Address */
4437 fs_reg(), /* No source data */
4438 brw_imm_ud(instr
->num_components
));
4439 inst
->size_written
= instr
->num_components
*
4440 inst
->dst
.component_size(inst
->exec_size
);
4442 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4443 assert(bit_size
<= 32);
4444 assert(nir_dest_num_components(instr
->dest
) == 1);
4445 brw_reg_type data_type
=
4446 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4447 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4448 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4450 get_nir_src(instr
->src
[0]), /* Address */
4451 fs_reg(), /* No source data */
4452 brw_imm_ud(bit_size
));
4453 bld
.MOV(retype(dest
, data_type
), tmp
);
4458 case nir_intrinsic_store_global
:
4459 assert(devinfo
->gen
>= 8);
4461 if (stage
== MESA_SHADER_FRAGMENT
)
4462 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4464 if (nir_intrinsic_align(instr
) >= 4) {
4465 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4466 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4468 get_nir_src(instr
->src
[1]), /* Address */
4469 get_nir_src(instr
->src
[0]), /* Data */
4470 brw_imm_ud(instr
->num_components
));
4472 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4473 assert(bit_size
<= 32);
4474 assert(nir_src_num_components(instr
->src
[0]) == 1);
4475 brw_reg_type data_type
=
4476 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4477 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4478 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4479 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4481 get_nir_src(instr
->src
[1]), /* Address */
4483 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4487 case nir_intrinsic_global_atomic_add
:
4488 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4490 case nir_intrinsic_global_atomic_imin
:
4491 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4493 case nir_intrinsic_global_atomic_umin
:
4494 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4496 case nir_intrinsic_global_atomic_imax
:
4497 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4499 case nir_intrinsic_global_atomic_umax
:
4500 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4502 case nir_intrinsic_global_atomic_and
:
4503 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4505 case nir_intrinsic_global_atomic_or
:
4506 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4508 case nir_intrinsic_global_atomic_xor
:
4509 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4511 case nir_intrinsic_global_atomic_exchange
:
4512 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4514 case nir_intrinsic_global_atomic_comp_swap
:
4515 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4517 case nir_intrinsic_global_atomic_fmin
:
4518 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4520 case nir_intrinsic_global_atomic_fmax
:
4521 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4523 case nir_intrinsic_global_atomic_fcomp_swap
:
4524 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4527 case nir_intrinsic_load_ssbo
: {
4528 assert(devinfo
->gen
>= 7);
4530 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4531 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4532 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4533 get_nir_ssbo_intrinsic_index(bld
, instr
);
4534 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4535 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4537 /* Make dest unsigned because that's what the temporary will be */
4538 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4540 /* Read the vector */
4541 if (nir_intrinsic_align(instr
) >= 4) {
4542 assert(nir_dest_bit_size(instr
->dest
) == 32);
4543 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4545 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4546 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4547 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4549 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4550 assert(nir_dest_num_components(instr
->dest
) == 1);
4551 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4553 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4554 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4555 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4556 bld
.MOV(dest
, read_result
);
4561 case nir_intrinsic_store_ssbo
: {
4562 assert(devinfo
->gen
>= 7);
4564 if (stage
== MESA_SHADER_FRAGMENT
)
4565 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4567 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4568 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4569 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4570 get_nir_ssbo_intrinsic_index(bld
, instr
);
4571 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4572 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4574 fs_reg data
= get_nir_src(instr
->src
[0]);
4575 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4577 assert(nir_intrinsic_write_mask(instr
) ==
4578 (1u << instr
->num_components
) - 1);
4579 if (nir_intrinsic_align(instr
) >= 4) {
4580 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4581 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4582 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4583 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4584 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4585 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4587 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4588 assert(nir_src_num_components(instr
->src
[0]) == 1);
4589 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4591 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4592 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4594 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4595 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4600 case nir_intrinsic_store_output
: {
4601 fs_reg src
= get_nir_src(instr
->src
[0]);
4603 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4604 unsigned num_components
= instr
->num_components
;
4605 unsigned first_component
= nir_intrinsic_component(instr
);
4606 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4607 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4608 num_components
*= 2;
4611 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4612 4 * store_offset
), src
.type
);
4613 for (unsigned j
= 0; j
< num_components
; j
++) {
4614 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4615 offset(src
, bld
, j
));
4620 case nir_intrinsic_ssbo_atomic_add
:
4621 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4623 case nir_intrinsic_ssbo_atomic_imin
:
4624 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4626 case nir_intrinsic_ssbo_atomic_umin
:
4627 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4629 case nir_intrinsic_ssbo_atomic_imax
:
4630 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4632 case nir_intrinsic_ssbo_atomic_umax
:
4633 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4635 case nir_intrinsic_ssbo_atomic_and
:
4636 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4638 case nir_intrinsic_ssbo_atomic_or
:
4639 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4641 case nir_intrinsic_ssbo_atomic_xor
:
4642 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4644 case nir_intrinsic_ssbo_atomic_exchange
:
4645 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4647 case nir_intrinsic_ssbo_atomic_comp_swap
:
4648 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4650 case nir_intrinsic_ssbo_atomic_fmin
:
4651 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4653 case nir_intrinsic_ssbo_atomic_fmax
:
4654 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4656 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4657 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4660 case nir_intrinsic_get_buffer_size
: {
4661 assert(nir_src_num_components(instr
->src
[0]) == 1);
4662 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4663 nir_src_as_uint(instr
->src
[0]) : 0;
4665 /* A resinfo's sampler message is used to get the buffer size. The
4666 * SIMD8's writeback message consists of four registers and SIMD16's
4667 * writeback message consists of 8 destination registers (two per each
4668 * component). Because we are only interested on the first channel of
4669 * the first returned component, where resinfo returns the buffer size
4670 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4671 * the dispatch width.
4673 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4674 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4675 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4678 ubld
.MOV(src_payload
, brw_imm_d(0));
4680 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4681 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4682 src_payload
, brw_imm_ud(index
));
4683 inst
->header_size
= 0;
4685 inst
->size_written
= 4 * REG_SIZE
;
4687 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4689 * "Out-of-bounds checking is always performed at a DWord granularity. If
4690 * any part of the DWord is out-of-bounds then the whole DWord is
4691 * considered out-of-bounds."
4693 * This implies that types with size smaller than 4-bytes need to be
4694 * padded if they don't complete the last dword of the buffer. But as we
4695 * need to maintain the original size we need to reverse the padding
4696 * calculation to return the correct size to know the number of elements
4697 * of an unsized array. As we stored in the last two bits of the surface
4698 * size the needed padding for the buffer, we calculate here the
4699 * original buffer_size reversing the surface_size calculation:
4701 * surface_size = isl_align(buffer_size, 4) +
4702 * (isl_align(buffer_size) - buffer_size)
4704 * buffer_size = surface_size & ~3 - surface_size & 3
4707 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4708 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4709 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4711 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4712 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4713 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4715 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4719 case nir_intrinsic_load_subgroup_invocation
:
4720 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4721 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4724 case nir_intrinsic_load_subgroup_eq_mask
:
4725 case nir_intrinsic_load_subgroup_ge_mask
:
4726 case nir_intrinsic_load_subgroup_gt_mask
:
4727 case nir_intrinsic_load_subgroup_le_mask
:
4728 case nir_intrinsic_load_subgroup_lt_mask
:
4729 unreachable("not reached");
4731 case nir_intrinsic_vote_any
: {
4732 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4734 /* The any/all predicates do not consider channel enables. To prevent
4735 * dead channels from affecting the result, we initialize the flag with
4736 * with the identity value for the logical operation.
4738 if (dispatch_width
== 32) {
4739 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4740 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4743 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4745 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4747 /* For some reason, the any/all predicates don't work properly with
4748 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4749 * doesn't read the correct subset of the flag register and you end up
4750 * getting garbage in the second half. Work around this by using a pair
4751 * of 1-wide MOVs and scattering the result.
4753 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4754 ubld
.MOV(res1
, brw_imm_d(0));
4755 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4756 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4757 BRW_PREDICATE_ALIGN1_ANY32H
,
4758 ubld
.MOV(res1
, brw_imm_d(-1)));
4760 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4763 case nir_intrinsic_vote_all
: {
4764 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4766 /* The any/all predicates do not consider channel enables. To prevent
4767 * dead channels from affecting the result, we initialize the flag with
4768 * with the identity value for the logical operation.
4770 if (dispatch_width
== 32) {
4771 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4772 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4773 brw_imm_ud(0xffffffff));
4775 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4777 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4779 /* For some reason, the any/all predicates don't work properly with
4780 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4781 * doesn't read the correct subset of the flag register and you end up
4782 * getting garbage in the second half. Work around this by using a pair
4783 * of 1-wide MOVs and scattering the result.
4785 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4786 ubld
.MOV(res1
, brw_imm_d(0));
4787 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4788 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4789 BRW_PREDICATE_ALIGN1_ALL32H
,
4790 ubld
.MOV(res1
, brw_imm_d(-1)));
4792 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4795 case nir_intrinsic_vote_feq
:
4796 case nir_intrinsic_vote_ieq
: {
4797 fs_reg value
= get_nir_src(instr
->src
[0]);
4798 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4799 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4800 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4801 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4804 fs_reg uniformized
= bld
.emit_uniformize(value
);
4805 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4807 /* The any/all predicates do not consider channel enables. To prevent
4808 * dead channels from affecting the result, we initialize the flag with
4809 * with the identity value for the logical operation.
4811 if (dispatch_width
== 32) {
4812 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4813 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4814 brw_imm_ud(0xffffffff));
4816 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4818 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4820 /* For some reason, the any/all predicates don't work properly with
4821 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4822 * doesn't read the correct subset of the flag register and you end up
4823 * getting garbage in the second half. Work around this by using a pair
4824 * of 1-wide MOVs and scattering the result.
4826 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4827 ubld
.MOV(res1
, brw_imm_d(0));
4828 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4829 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4830 BRW_PREDICATE_ALIGN1_ALL32H
,
4831 ubld
.MOV(res1
, brw_imm_d(-1)));
4833 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4837 case nir_intrinsic_ballot
: {
4838 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4839 BRW_REGISTER_TYPE_UD
);
4840 struct brw_reg flag
= brw_flag_reg(0, 0);
4841 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4842 * as f0.0. This is a problem for fragment programs as we currently use
4843 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4844 * programs yet so this isn't a problem. When we do, something will
4847 if (dispatch_width
== 32)
4848 flag
.type
= BRW_REGISTER_TYPE_UD
;
4850 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4851 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4853 if (instr
->dest
.ssa
.bit_size
> 32) {
4854 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4856 dest
.type
= BRW_REGISTER_TYPE_UD
;
4858 bld
.MOV(dest
, flag
);
4862 case nir_intrinsic_read_invocation
: {
4863 const fs_reg value
= get_nir_src(instr
->src
[0]);
4864 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4865 fs_reg tmp
= bld
.vgrf(value
.type
);
4867 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4868 bld
.emit_uniformize(invocation
));
4870 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4874 case nir_intrinsic_read_first_invocation
: {
4875 const fs_reg value
= get_nir_src(instr
->src
[0]);
4876 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4880 case nir_intrinsic_shuffle
: {
4881 const fs_reg value
= get_nir_src(instr
->src
[0]);
4882 const fs_reg index
= get_nir_src(instr
->src
[1]);
4884 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4888 case nir_intrinsic_first_invocation
: {
4889 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4890 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4891 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4892 fs_reg(component(tmp
, 0)));
4896 case nir_intrinsic_quad_broadcast
: {
4897 const fs_reg value
= get_nir_src(instr
->src
[0]);
4898 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4900 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4901 value
, brw_imm_ud(index
), brw_imm_ud(4));
4905 case nir_intrinsic_quad_swap_horizontal
: {
4906 const fs_reg value
= get_nir_src(instr
->src
[0]);
4907 const fs_reg tmp
= bld
.vgrf(value
.type
);
4908 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4910 const fs_reg src_left
= horiz_stride(value
, 2);
4911 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4912 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4913 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4915 ubld
.MOV(tmp_left
, src_right
);
4916 ubld
.MOV(tmp_right
, src_left
);
4918 bld
.MOV(retype(dest
, value
.type
), tmp
);
4922 case nir_intrinsic_quad_swap_vertical
: {
4923 const fs_reg value
= get_nir_src(instr
->src
[0]);
4924 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4925 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4926 const fs_reg tmp
= bld
.vgrf(value
.type
);
4927 const fs_builder ubld
= bld
.exec_all();
4928 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4929 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4930 bld
.MOV(retype(dest
, value
.type
), tmp
);
4932 /* For larger data types, we have to either emit dispatch_width many
4933 * MOVs or else fall back to doing indirects.
4935 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4936 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4938 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4943 case nir_intrinsic_quad_swap_diagonal
: {
4944 const fs_reg value
= get_nir_src(instr
->src
[0]);
4945 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4946 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4947 const fs_reg tmp
= bld
.vgrf(value
.type
);
4948 const fs_builder ubld
= bld
.exec_all();
4949 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4950 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4951 bld
.MOV(retype(dest
, value
.type
), tmp
);
4953 /* For larger data types, we have to either emit dispatch_width many
4954 * MOVs or else fall back to doing indirects.
4956 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4957 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4959 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4964 case nir_intrinsic_reduce
: {
4965 fs_reg src
= get_nir_src(instr
->src
[0]);
4966 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4967 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4968 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4969 cluster_size
= dispatch_width
;
4971 /* Figure out the source type */
4972 src
.type
= brw_type_for_nir_type(devinfo
,
4973 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4974 nir_src_bit_size(instr
->src
[0])));
4976 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4977 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4978 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4980 /* Set up a register for all of our scratching around and initialize it
4981 * to reduction operation's identity value.
4983 fs_reg scan
= bld
.vgrf(src
.type
);
4984 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4986 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4988 dest
.type
= src
.type
;
4989 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4990 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4991 * the distance between clusters is at least 2 GRFs. In this case,
4992 * we don't need the weird striding of the CLUSTER_BROADCAST
4993 * instruction and can just do regular MOVs.
4995 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4996 const unsigned groups
=
4997 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4998 const unsigned group_size
= dispatch_width
/ groups
;
4999 for (unsigned i
= 0; i
< groups
; i
++) {
5000 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5001 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5002 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5003 component(scan
, comp
));
5006 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5007 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5012 case nir_intrinsic_inclusive_scan
:
5013 case nir_intrinsic_exclusive_scan
: {
5014 fs_reg src
= get_nir_src(instr
->src
[0]);
5015 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5017 /* Figure out the source type */
5018 src
.type
= brw_type_for_nir_type(devinfo
,
5019 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5020 nir_src_bit_size(instr
->src
[0])));
5022 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5023 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5024 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5026 /* Set up a register for all of our scratching around and initialize it
5027 * to reduction operation's identity value.
5029 fs_reg scan
= bld
.vgrf(src
.type
);
5030 const fs_builder allbld
= bld
.exec_all();
5031 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5033 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5034 /* Exclusive scan is a bit harder because we have to do an annoying
5035 * shift of the contents before we can begin. To make things worse,
5036 * we can't do this with a normal stride; we have to use indirects.
5038 fs_reg shifted
= bld
.vgrf(src
.type
);
5039 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5040 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5042 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5043 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5047 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5049 bld
.MOV(retype(dest
, src
.type
), scan
);
5053 case nir_intrinsic_begin_invocation_interlock
: {
5054 const fs_builder ubld
= bld
.group(8, 0);
5055 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5057 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
5063 case nir_intrinsic_end_invocation_interlock
: {
5064 /* We don't need to do anything here */
5069 unreachable("unknown intrinsic");
5074 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5075 int op
, nir_intrinsic_instr
*instr
)
5077 if (stage
== MESA_SHADER_FRAGMENT
)
5078 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5080 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5081 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5082 * appear to exist. However, if you look at Vol 2a, there are no message
5083 * descriptors provided for Qword atomic ops except for A64 messages.
5085 assert(nir_dest_bit_size(instr
->dest
) == 32);
5088 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5089 dest
= get_nir_dest(instr
->dest
);
5091 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5092 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5093 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5094 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5095 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5098 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5099 data
= get_nir_src(instr
->src
[2]);
5101 if (op
== BRW_AOP_CMPWR
) {
5102 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5103 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5104 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5107 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5109 /* Emit the actual atomic operation */
5111 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5112 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5116 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5117 int op
, nir_intrinsic_instr
*instr
)
5119 if (stage
== MESA_SHADER_FRAGMENT
)
5120 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5123 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5124 dest
= get_nir_dest(instr
->dest
);
5126 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5127 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5128 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5129 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5130 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5132 fs_reg data
= get_nir_src(instr
->src
[2]);
5133 if (op
== BRW_AOP_FCMPWR
) {
5134 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5135 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5136 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5139 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5141 /* Emit the actual atomic operation */
5143 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5144 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5148 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5149 int op
, nir_intrinsic_instr
*instr
)
5152 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5153 dest
= get_nir_dest(instr
->dest
);
5155 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5156 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5157 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5158 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5161 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5162 data
= get_nir_src(instr
->src
[1]);
5163 if (op
== BRW_AOP_CMPWR
) {
5164 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5165 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5166 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5169 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5171 /* Get the offset */
5172 if (nir_src_is_const(instr
->src
[0])) {
5173 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5174 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5176 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5177 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5178 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5179 brw_imm_ud(instr
->const_index
[0]));
5182 /* Emit the actual atomic operation operation */
5184 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5185 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5189 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5190 int op
, nir_intrinsic_instr
*instr
)
5193 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5194 dest
= get_nir_dest(instr
->dest
);
5196 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5197 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5198 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5199 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5201 fs_reg data
= get_nir_src(instr
->src
[1]);
5202 if (op
== BRW_AOP_FCMPWR
) {
5203 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5204 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5205 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5208 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5210 /* Get the offset */
5211 if (nir_src_is_const(instr
->src
[0])) {
5212 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5213 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5215 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5216 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5217 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5218 brw_imm_ud(instr
->const_index
[0]));
5221 /* Emit the actual atomic operation operation */
5223 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5224 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5228 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5229 int op
, nir_intrinsic_instr
*instr
)
5231 if (stage
== MESA_SHADER_FRAGMENT
)
5232 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5235 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5236 dest
= get_nir_dest(instr
->dest
);
5238 fs_reg addr
= get_nir_src(instr
->src
[0]);
5241 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5242 data
= get_nir_src(instr
->src
[1]);
5244 if (op
== BRW_AOP_CMPWR
) {
5245 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5246 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5247 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5251 if (nir_dest_bit_size(instr
->dest
) == 64) {
5252 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5253 dest
, addr
, data
, brw_imm_ud(op
));
5255 assert(nir_dest_bit_size(instr
->dest
) == 32);
5256 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5257 dest
, addr
, data
, brw_imm_ud(op
));
5262 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5263 int op
, nir_intrinsic_instr
*instr
)
5265 if (stage
== MESA_SHADER_FRAGMENT
)
5266 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5268 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5269 fs_reg dest
= get_nir_dest(instr
->dest
);
5271 fs_reg addr
= get_nir_src(instr
->src
[0]);
5273 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5274 fs_reg data
= get_nir_src(instr
->src
[1]);
5276 if (op
== BRW_AOP_FCMPWR
) {
5277 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5278 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5279 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5283 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5284 dest
, addr
, data
, brw_imm_ud(op
));
5288 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5290 unsigned texture
= instr
->texture_index
;
5291 unsigned sampler
= instr
->sampler_index
;
5293 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5295 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5296 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5298 int lod_components
= 0;
5300 /* The hardware requires a LOD for buffer textures */
5301 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5302 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5304 uint32_t header_bits
= 0;
5305 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5306 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5307 switch (instr
->src
[i
].src_type
) {
5308 case nir_tex_src_bias
:
5309 srcs
[TEX_LOGICAL_SRC_LOD
] =
5310 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5312 case nir_tex_src_comparator
:
5313 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5315 case nir_tex_src_coord
:
5316 switch (instr
->op
) {
5318 case nir_texop_txf_ms
:
5319 case nir_texop_txf_ms_mcs
:
5320 case nir_texop_samples_identical
:
5321 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5324 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5328 case nir_tex_src_ddx
:
5329 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5330 lod_components
= nir_tex_instr_src_size(instr
, i
);
5332 case nir_tex_src_ddy
:
5333 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5335 case nir_tex_src_lod
:
5336 switch (instr
->op
) {
5338 srcs
[TEX_LOGICAL_SRC_LOD
] =
5339 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5342 srcs
[TEX_LOGICAL_SRC_LOD
] =
5343 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5346 srcs
[TEX_LOGICAL_SRC_LOD
] =
5347 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5351 case nir_tex_src_min_lod
:
5352 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5353 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5355 case nir_tex_src_ms_index
:
5356 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5359 case nir_tex_src_offset
: {
5360 uint32_t offset_bits
= 0;
5361 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5362 header_bits
|= offset_bits
;
5364 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5365 retype(src
, BRW_REGISTER_TYPE_D
);
5370 case nir_tex_src_projector
:
5371 unreachable("should be lowered");
5373 case nir_tex_src_texture_offset
: {
5374 /* Emit code to evaluate the actual indexing expression */
5375 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5376 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5377 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5381 case nir_tex_src_sampler_offset
: {
5382 /* Emit code to evaluate the actual indexing expression */
5383 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5384 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5385 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5389 case nir_tex_src_texture_handle
:
5390 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5391 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5392 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5395 case nir_tex_src_sampler_handle
:
5396 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5397 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5398 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5401 case nir_tex_src_ms_mcs
:
5402 assert(instr
->op
== nir_texop_txf_ms
);
5403 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5406 case nir_tex_src_plane
: {
5407 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5408 const uint32_t texture_index
=
5409 instr
->texture_index
+
5410 stage_prog_data
->binding_table
.plane_start
[plane
] -
5411 stage_prog_data
->binding_table
.texture_start
;
5413 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5418 unreachable("unknown texture source");
5422 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5423 (instr
->op
== nir_texop_txf_ms
||
5424 instr
->op
== nir_texop_samples_identical
)) {
5425 if (devinfo
->gen
>= 7 &&
5426 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5427 srcs
[TEX_LOGICAL_SRC_MCS
] =
5428 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5429 instr
->coord_components
,
5430 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5431 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5433 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5437 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5438 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5441 switch (instr
->op
) {
5443 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5446 opcode
= FS_OPCODE_TXB_LOGICAL
;
5449 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5452 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5455 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5457 case nir_texop_txf_ms
:
5458 if ((key_tex
->msaa_16
& (1 << sampler
)))
5459 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5461 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5463 case nir_texop_txf_ms_mcs
:
5464 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5466 case nir_texop_query_levels
:
5468 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5471 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5474 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5475 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5477 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5479 case nir_texop_texture_samples
:
5480 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5482 case nir_texop_samples_identical
: {
5483 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5485 /* If mcs is an immediate value, it means there is no MCS. In that case
5486 * just return false.
5488 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5489 bld
.MOV(dst
, brw_imm_ud(0u));
5490 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5491 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5492 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5493 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5494 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5496 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5497 BRW_CONDITIONAL_EQ
);
5502 unreachable("unknown texture opcode");
5505 if (instr
->op
== nir_texop_tg4
) {
5506 if (instr
->component
== 1 &&
5507 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5508 /* gather4 sampler is broken for green channel on RG32F --
5509 * we must ask for blue instead.
5511 header_bits
|= 2 << 16;
5513 header_bits
|= instr
->component
<< 16;
5517 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5518 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5519 inst
->offset
= header_bits
;
5521 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5522 if (devinfo
->gen
>= 9 &&
5523 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5524 unsigned write_mask
= instr
->dest
.is_ssa
?
5525 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5526 (1 << dest_size
) - 1;
5527 assert(write_mask
!= 0); /* dead code should have been eliminated */
5528 inst
->size_written
= util_last_bit(write_mask
) *
5529 inst
->dst
.component_size(inst
->exec_size
);
5531 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5534 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5535 inst
->shadow_compare
= true;
5537 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5538 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5541 for (unsigned i
= 0; i
< dest_size
; i
++)
5542 nir_dest
[i
] = offset(dst
, bld
, i
);
5544 if (instr
->op
== nir_texop_query_levels
) {
5545 /* # levels is in .w */
5546 nir_dest
[0] = offset(dst
, bld
, 3);
5547 } else if (instr
->op
== nir_texop_txs
&&
5548 dest_size
>= 3 && devinfo
->gen
< 7) {
5549 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5550 fs_reg depth
= offset(dst
, bld
, 2);
5551 nir_dest
[2] = vgrf(glsl_type::int_type
);
5552 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5555 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5559 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5561 switch (instr
->type
) {
5562 case nir_jump_break
:
5563 bld
.emit(BRW_OPCODE_BREAK
);
5565 case nir_jump_continue
:
5566 bld
.emit(BRW_OPCODE_CONTINUE
);
5568 case nir_jump_return
:
5570 unreachable("unknown jump");
5575 * This helper takes a source register and un/shuffles it into the destination
5578 * If source type size is smaller than destination type size the operation
5579 * needed is a component shuffle. The opposite case would be an unshuffle. If
5580 * source/destination type size is equal a shuffle is done that would be
5581 * equivalent to a simple MOV.
5583 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5584 * components .xyz 16-bit vector on SIMD8 would be.
5586 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5587 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5589 * This helper will return the following 2 32-bit components with the 16-bit
5592 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5593 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5595 * For unshuffle, the example would be the opposite, a 64-bit type source
5596 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5599 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5600 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5601 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5602 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5604 * The returned result would be the following 4 32-bit components unshuffled:
5606 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5607 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5608 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5609 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5611 * - Source and destination register must not be overlapped.
5612 * - components units are measured in terms of the smaller type between
5613 * source and destination because we are un/shuffling the smaller
5614 * components from/into the bigger ones.
5615 * - first_component parameter allows skipping source components.
5618 shuffle_src_to_dst(const fs_builder
&bld
,
5621 uint32_t first_component
,
5622 uint32_t components
)
5624 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5625 assert(!regions_overlap(dst
,
5626 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5627 offset(src
, bld
, first_component
),
5628 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5629 for (unsigned i
= 0; i
< components
; i
++) {
5630 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5631 offset(src
, bld
, i
+ first_component
));
5633 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5634 /* Source is shuffled into destination */
5635 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5636 assert(!regions_overlap(dst
,
5637 type_sz(dst
.type
) * bld
.dispatch_width() *
5638 DIV_ROUND_UP(components
, size_ratio
),
5639 offset(src
, bld
, first_component
),
5640 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5642 brw_reg_type shuffle_type
=
5643 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5644 BRW_REGISTER_TYPE_D
);
5645 for (unsigned i
= 0; i
< components
; i
++) {
5646 fs_reg shuffle_component_i
=
5647 subscript(offset(dst
, bld
, i
/ size_ratio
),
5648 shuffle_type
, i
% size_ratio
);
5649 bld
.MOV(shuffle_component_i
,
5650 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5653 /* Source is unshuffled into destination */
5654 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5655 assert(!regions_overlap(dst
,
5656 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5657 offset(src
, bld
, first_component
/ size_ratio
),
5658 type_sz(src
.type
) * bld
.dispatch_width() *
5659 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5662 brw_reg_type shuffle_type
=
5663 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5664 BRW_REGISTER_TYPE_D
);
5665 for (unsigned i
= 0; i
< components
; i
++) {
5666 fs_reg shuffle_component_i
=
5667 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5668 shuffle_type
, (first_component
+ i
) % size_ratio
);
5669 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5670 shuffle_component_i
);
5676 shuffle_from_32bit_read(const fs_builder
&bld
,
5679 uint32_t first_component
,
5680 uint32_t components
)
5682 assert(type_sz(src
.type
) == 4);
5684 /* This function takes components in units of the destination type while
5685 * shuffle_src_to_dst takes components in units of the smallest type
5687 if (type_sz(dst
.type
) > 4) {
5688 assert(type_sz(dst
.type
) == 8);
5689 first_component
*= 2;
5693 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5697 shuffle_for_32bit_write(const fs_builder
&bld
,
5699 uint32_t first_component
,
5700 uint32_t components
)
5702 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5703 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5704 /* This function takes components in units of the source type while
5705 * shuffle_src_to_dst takes components in units of the smallest type
5707 if (type_sz(src
.type
) > 4) {
5708 assert(type_sz(src
.type
) == 8);
5709 first_component
*= 2;
5713 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5719 setup_imm_df(const fs_builder
&bld
, double v
)
5721 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5722 assert(devinfo
->gen
>= 7);
5724 if (devinfo
->gen
>= 8)
5725 return brw_imm_df(v
);
5727 /* gen7.5 does not support DF immediates straighforward but the DIM
5728 * instruction allows to set the 64-bit immediate value.
5730 if (devinfo
->is_haswell
) {
5731 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5732 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5733 ubld
.DIM(dst
, brw_imm_df(v
));
5734 return component(dst
, 0);
5737 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5738 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5739 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5741 * Alternatively, we could also produce a normal VGRF (without stride 0)
5742 * by writing to all the channels in the VGRF, however, that would hit the
5743 * gen7 bug where we have to split writes that span more than 1 register
5744 * into instructions with a width of 4 (otherwise the write to the second
5745 * register written runs into an execmask hardware bug) which isn't very
5758 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5759 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5760 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5761 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5763 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5767 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5769 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5770 bld
.MOV(tmp
, brw_imm_w(v
));
5775 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5777 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5778 bld
.MOV(tmp
, brw_imm_uw(v
));