2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "util/u_math.h"
28 #include "util/bitscan.h"
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
46 fs_visitor::nir_setup_outputs()
48 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
51 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
53 /* Calculate the size of output registers in a separate pass, before
54 * allocating them. With ARB_enhanced_layouts, multiple output variables
55 * may occupy the same slot, but have different type sizes.
57 nir_foreach_variable(var
, &nir
->outputs
) {
58 const int loc
= var
->data
.driver_location
;
59 const unsigned var_vec4s
=
60 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
61 : type_size_vec4(var
->type
);
62 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
65 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
66 if (vec4s
[loc
] == 0) {
71 unsigned reg_size
= vec4s
[loc
];
73 /* Check if there are any ranges that start within this range and extend
74 * past it. If so, include them in this allocation.
76 for (unsigned i
= 1; i
< reg_size
; i
++)
77 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
79 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
80 for (unsigned i
= 0; i
< reg_size
; i
++)
81 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
88 fs_visitor::nir_setup_uniforms()
90 /* Only the first compile gets to set up uniforms. */
91 if (push_constant_loc
) {
92 assert(pull_constant_loc
);
96 uniforms
= nir
->num_uniforms
/ 4;
98 if (stage
== MESA_SHADER_COMPUTE
) {
99 /* Add a uniform for the thread local id. It must be the last uniform
102 assert(uniforms
== prog_data
->nr_params
);
103 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
104 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
105 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
110 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
114 nir_foreach_instr(instr
, block
) {
115 if (instr
->type
!= nir_instr_type_intrinsic
)
118 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
119 switch (intrin
->intrinsic
) {
120 case nir_intrinsic_load_vertex_id
:
121 case nir_intrinsic_load_base_vertex
:
122 unreachable("should be lowered by nir_lower_system_values().");
124 case nir_intrinsic_load_vertex_id_zero_base
:
125 case nir_intrinsic_load_is_indexed_draw
:
126 case nir_intrinsic_load_first_vertex
:
127 case nir_intrinsic_load_instance_id
:
128 case nir_intrinsic_load_base_instance
:
129 case nir_intrinsic_load_draw_id
:
130 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
132 case nir_intrinsic_load_invocation_id
:
133 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
135 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
136 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
137 if (reg
->file
== BAD_FILE
) {
138 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
139 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
140 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
141 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
146 case nir_intrinsic_load_sample_pos
:
147 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
148 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
149 if (reg
->file
== BAD_FILE
)
150 *reg
= *v
->emit_samplepos_setup();
153 case nir_intrinsic_load_sample_id
:
154 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_sampleid_setup();
160 case nir_intrinsic_load_sample_mask_in
:
161 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
162 assert(v
->devinfo
->gen
>= 7);
163 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
164 if (reg
->file
== BAD_FILE
)
165 *reg
= *v
->emit_samplemaskin_setup();
168 case nir_intrinsic_load_work_group_id
:
169 assert(v
->stage
== MESA_SHADER_COMPUTE
);
170 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
171 if (reg
->file
== BAD_FILE
)
172 *reg
= *v
->emit_cs_work_group_id_setup();
175 case nir_intrinsic_load_helper_invocation
:
176 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
177 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
178 if (reg
->file
== BAD_FILE
) {
179 const fs_builder abld
=
180 v
->bld
.annotate("gl_HelperInvocation", NULL
);
182 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
183 * pixel mask is in g1.7 of the thread payload.
185 * We move the per-channel pixel enable bit to the low bit of each
186 * channel by shifting the byte containing the pixel mask by the
187 * vector immediate 0x76543210UV.
189 * The region of <1,8,0> reads only 1 byte (the pixel masks for
190 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
191 * masks for 2 and 3) in SIMD16.
193 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
195 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
196 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
197 hbld
.SHR(offset(shifted
, hbld
, i
),
198 stride(retype(brw_vec1_grf(1 + i
, 7),
199 BRW_REGISTER_TYPE_UB
),
201 brw_imm_v(0x76543210));
204 /* A set bit in the pixel mask means the channel is enabled, but
205 * that is the opposite of gl_HelperInvocation so we need to invert
208 * The negate source-modifier bit of logical instructions on Gen8+
209 * performs 1's complement negation, so we can use that instead of
212 fs_reg inverted
= negate(shifted
);
213 if (v
->devinfo
->gen
< 8) {
214 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
215 abld
.NOT(inverted
, shifted
);
218 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
219 * with 1 and negating.
221 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
222 abld
.AND(anded
, inverted
, brw_imm_uw(1));
224 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
225 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
239 fs_visitor::nir_emit_system_values()
241 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
242 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
243 nir_system_values
[i
] = fs_reg();
246 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
247 * never end up using it.
250 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
251 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
252 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
254 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
255 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
256 if (dispatch_width
> 8)
257 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
258 if (dispatch_width
> 16) {
259 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
260 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
264 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
265 nir_foreach_block(block
, impl
)
266 emit_system_values_block(block
, this);
270 * Returns a type based on a reference_type (word, float, half-float) and a
273 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
275 * @FIXME: 64-bit return types are always DF on integer types to maintain
276 * compability with uses of DF previously to the introduction of int64
280 brw_reg_type_from_bit_size(const unsigned bit_size
,
281 const brw_reg_type reference_type
)
283 switch(reference_type
) {
284 case BRW_REGISTER_TYPE_HF
:
285 case BRW_REGISTER_TYPE_F
:
286 case BRW_REGISTER_TYPE_DF
:
289 return BRW_REGISTER_TYPE_HF
;
291 return BRW_REGISTER_TYPE_F
;
293 return BRW_REGISTER_TYPE_DF
;
295 unreachable("Invalid bit size");
297 case BRW_REGISTER_TYPE_B
:
298 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_D
:
300 case BRW_REGISTER_TYPE_Q
:
303 return BRW_REGISTER_TYPE_B
;
305 return BRW_REGISTER_TYPE_W
;
307 return BRW_REGISTER_TYPE_D
;
309 return BRW_REGISTER_TYPE_Q
;
311 unreachable("Invalid bit size");
313 case BRW_REGISTER_TYPE_UB
:
314 case BRW_REGISTER_TYPE_UW
:
315 case BRW_REGISTER_TYPE_UD
:
316 case BRW_REGISTER_TYPE_UQ
:
319 return BRW_REGISTER_TYPE_UB
;
321 return BRW_REGISTER_TYPE_UW
;
323 return BRW_REGISTER_TYPE_UD
;
325 return BRW_REGISTER_TYPE_UQ
;
327 unreachable("Invalid bit size");
330 unreachable("Unknown type");
335 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
337 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
338 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
339 nir_locals
[i
] = fs_reg();
342 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
343 unsigned array_elems
=
344 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
345 unsigned size
= array_elems
* reg
->num_components
;
346 const brw_reg_type reg_type
=
347 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
348 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
351 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
354 nir_emit_cf_list(&impl
->body
);
358 fs_visitor::nir_emit_cf_list(exec_list
*list
)
360 exec_list_validate(list
);
361 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
362 switch (node
->type
) {
364 nir_emit_if(nir_cf_node_as_if(node
));
367 case nir_cf_node_loop
:
368 nir_emit_loop(nir_cf_node_as_loop(node
));
371 case nir_cf_node_block
:
372 nir_emit_block(nir_cf_node_as_block(node
));
376 unreachable("Invalid CFG node block");
382 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
384 /* first, put the condition into f0 */
385 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
386 retype(get_nir_src(if_stmt
->condition
),
387 BRW_REGISTER_TYPE_D
));
388 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
390 bld
.IF(BRW_PREDICATE_NORMAL
);
392 nir_emit_cf_list(&if_stmt
->then_list
);
394 /* note: if the else is empty, dead CF elimination will remove it */
395 bld
.emit(BRW_OPCODE_ELSE
);
397 nir_emit_cf_list(&if_stmt
->else_list
);
399 bld
.emit(BRW_OPCODE_ENDIF
);
401 if (devinfo
->gen
< 7)
402 limit_dispatch_width(16, "Non-uniform control flow unsupported "
407 fs_visitor::nir_emit_loop(nir_loop
*loop
)
409 bld
.emit(BRW_OPCODE_DO
);
411 nir_emit_cf_list(&loop
->body
);
413 bld
.emit(BRW_OPCODE_WHILE
);
415 if (devinfo
->gen
< 7)
416 limit_dispatch_width(16, "Non-uniform control flow unsupported "
421 fs_visitor::nir_emit_block(nir_block
*block
)
423 nir_foreach_instr(instr
, block
) {
424 nir_emit_instr(instr
);
429 fs_visitor::nir_emit_instr(nir_instr
*instr
)
431 const fs_builder abld
= bld
.annotate(NULL
, instr
);
433 switch (instr
->type
) {
434 case nir_instr_type_alu
:
435 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
438 case nir_instr_type_deref
:
439 /* Derefs can exist for images but they do nothing */
442 case nir_instr_type_intrinsic
:
444 case MESA_SHADER_VERTEX
:
445 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
447 case MESA_SHADER_TESS_CTRL
:
448 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
450 case MESA_SHADER_TESS_EVAL
:
451 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
453 case MESA_SHADER_GEOMETRY
:
454 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_FRAGMENT
:
457 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
459 case MESA_SHADER_COMPUTE
:
460 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
463 unreachable("unsupported shader stage");
467 case nir_instr_type_tex
:
468 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
471 case nir_instr_type_load_const
:
472 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
475 case nir_instr_type_ssa_undef
:
476 /* We create a new VGRF for undefs on every use (by handling
477 * them in get_nir_src()), rather than for each definition.
478 * This helps register coalescing eliminate MOVs from undef.
482 case nir_instr_type_jump
:
483 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
487 unreachable("unknown instruction type");
492 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
496 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
497 const fs_reg
&result
)
499 if (!instr
->src
[0].src
.is_ssa
||
500 !instr
->src
[0].src
.ssa
->parent_instr
)
503 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
506 nir_alu_instr
*src0
=
507 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
509 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
510 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
513 /* If either opcode has source modifiers, bail.
515 * TODO: We can potentially handle source modifiers if both of the opcodes
516 * we're combining are signed integers.
518 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
519 src0
->src
[0].abs
|| src0
->src
[0].negate
)
522 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
524 /* Element type to extract.*/
525 const brw_reg_type type
= brw_int_type(
526 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
527 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
529 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
530 op0
.type
= brw_type_for_nir_type(devinfo
,
531 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
532 nir_src_bit_size(src0
->src
[0].src
)));
533 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
535 set_saturate(instr
->dest
.saturate
,
536 bld
.MOV(result
, subscript(op0
, type
, element
)));
541 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
542 const fs_reg
&result
)
544 if (!instr
->src
[0].src
.is_ssa
||
545 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
548 nir_intrinsic_instr
*src0
=
549 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
551 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
554 if (!nir_src_is_const(instr
->src
[1].src
) ||
555 !nir_src_is_const(instr
->src
[2].src
))
558 const float value1
= nir_src_as_float(instr
->src
[1].src
);
559 const float value2
= nir_src_as_float(instr
->src
[2].src
);
560 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
563 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
564 assert(value1
== -value2
);
566 fs_reg tmp
= vgrf(glsl_type::int_type
);
568 if (devinfo
->gen
>= 6) {
569 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
570 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
572 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
574 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
575 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
577 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
579 * This negation looks like it's safe in practice, because bits 0:4 will
580 * surely be TRIANGLES
583 if (value1
== -1.0f
) {
587 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
588 g0
, brw_imm_uw(0x3f80));
590 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
591 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
593 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
595 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
596 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
598 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
600 * This negation looks like it's safe in practice, because bits 0:4 will
601 * surely be TRIANGLES
604 if (value1
== -1.0f
) {
608 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
610 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
616 emit_find_msb_using_lzd(const fs_builder
&bld
,
617 const fs_reg
&result
,
625 /* LZD of an absolute value source almost always does the right
626 * thing. There are two problem values:
628 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
629 * 0. However, findMSB(int(0x80000000)) == 30.
631 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
632 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
634 * For a value of zero or negative one, -1 will be returned.
636 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
637 * findMSB(-(1<<x)) should return x-1.
639 * For all negative number cases, including 0x80000000 and
640 * 0xffffffff, the correct value is obtained from LZD if instead of
641 * negating the (already negative) value the logical-not is used. A
642 * conditonal logical-not can be achieved in two instructions.
644 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
646 bld
.ASR(temp
, src
, brw_imm_d(31));
647 bld
.XOR(temp
, temp
, src
);
650 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
651 retype(temp
, BRW_REGISTER_TYPE_UD
));
653 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
654 * from the LSB side. Subtract the result from 31 to convert the MSB
655 * count into an LSB count. If no bits are set, LZD will return 32.
656 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
658 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
659 inst
->src
[0].negate
= true;
663 brw_rnd_mode_from_nir_op (const nir_op op
) {
665 case nir_op_f2f16_rtz
:
666 return BRW_RND_MODE_RTZ
;
667 case nir_op_f2f16_rtne
:
668 return BRW_RND_MODE_RTNE
;
670 unreachable("Operation doesn't support rounding mode");
675 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
676 nir_alu_instr
*instr
,
681 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
683 result
.type
= brw_type_for_nir_type(devinfo
,
684 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
685 nir_dest_bit_size(instr
->dest
.dest
)));
687 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
688 op
[i
] = get_nir_src(instr
->src
[i
].src
);
689 op
[i
].type
= brw_type_for_nir_type(devinfo
,
690 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
691 nir_src_bit_size(instr
->src
[i
].src
)));
692 op
[i
].abs
= instr
->src
[i
].abs
;
693 op
[i
].negate
= instr
->src
[i
].negate
;
696 /* Move and vecN instrutions may still be vectored. Return the raw,
697 * vectored source and destination so that fs_visitor::nir_emit_alu can
698 * handle it. Other callers should not have to handle these kinds of
712 /* At this point, we have dealt with any instruction that operates on
713 * more than a single channel. Therefore, we can just adjust the source
714 * and destination registers for that channel and emit the instruction.
716 unsigned channel
= 0;
717 if (nir_op_infos
[instr
->op
].output_size
== 0) {
718 /* Since NIR is doing the scalarizing for us, we should only ever see
719 * vectorized operations with a single channel.
721 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
722 channel
= ffs(instr
->dest
.write_mask
) - 1;
724 result
= offset(result
, bld
, channel
);
727 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
728 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
729 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
736 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
739 for (unsigned i
= 0; i
< 2; i
++) {
740 nir_alu_instr
*const inot_instr
=
741 nir_src_as_alu_instr(&instr
->src
[i
].src
);
743 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
744 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
745 /* The source of the inot is now the source of instr. */
746 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
748 assert(!op
[i
].negate
);
751 op
[i
] = resolve_source_modifiers(op
[i
]);
757 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
759 nir_alu_instr
*instr
)
761 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
764 nir_alu_instr
*const inot_instr
= nir_src_as_alu_instr(&instr
->src
[0].src
);
766 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
769 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
770 * of valid size-changing combinations is a bit more complex.
772 * The source restriction is just because I was lazy about generating the
775 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
776 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
779 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
780 * this is float(1 + a).
784 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
786 bld
.ADD(result
, op
, brw_imm_d(1));
787 assert(!instr
->dest
.saturate
);
793 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
795 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
799 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, true);
807 fs_reg temp
= result
;
808 bool need_extra_copy
= false;
809 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
810 if (!instr
->src
[i
].src
.is_ssa
&&
811 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
812 need_extra_copy
= true;
813 temp
= bld
.vgrf(result
.type
, 4);
818 for (unsigned i
= 0; i
< 4; i
++) {
819 if (!(instr
->dest
.write_mask
& (1 << i
)))
822 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
823 inst
= bld
.MOV(offset(temp
, bld
, i
),
824 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
826 inst
= bld
.MOV(offset(temp
, bld
, i
),
827 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
829 inst
->saturate
= instr
->dest
.saturate
;
832 /* In this case the source and destination registers were the same,
833 * so we need to insert an extra set of moves in order to deal with
836 if (need_extra_copy
) {
837 for (unsigned i
= 0; i
< 4; i
++) {
838 if (!(instr
->dest
.write_mask
& (1 << i
)))
841 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
849 if (optimize_extract_to_float(instr
, result
))
851 inst
= bld
.MOV(result
, op
[0]);
852 inst
->saturate
= instr
->dest
.saturate
;
855 case nir_op_f2f16_rtne
:
856 case nir_op_f2f16_rtz
:
857 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
858 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
861 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
862 * on the HW gen, it is a special hw opcode or just a MOV, and
863 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
865 * But if we want to use that opcode, we need to provide support on
866 * different optimizations and lowerings. As right now HF support is
867 * only for gen8+, it will be better to use directly the MOV, and use
868 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
872 inst
= bld
.MOV(result
, op
[0]);
873 inst
->saturate
= instr
->dest
.saturate
;
883 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
885 op
[0].type
= BRW_REGISTER_TYPE_D
;
886 op
[0].negate
= !op
[0].negate
;
908 inst
= bld
.MOV(result
, op
[0]);
909 inst
->saturate
= instr
->dest
.saturate
;
913 assert(!instr
->dest
.saturate
);
915 /* Straightforward since the source can be assumed to be either
916 * strictly >= 0 or strictly <= 0 depending on the setting of the
919 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
921 inst
= (op
[0].negate
)
922 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
923 : bld
.MOV(result
, brw_imm_f(1.0f
));
925 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
926 } else if (type_sz(op
[0].type
) < 8) {
927 /* AND(val, 0x80000000) gives the sign bit.
929 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
932 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
934 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
935 op
[0].type
= BRW_REGISTER_TYPE_UD
;
936 result
.type
= BRW_REGISTER_TYPE_UD
;
937 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
939 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
940 inst
->predicate
= BRW_PREDICATE_NORMAL
;
942 /* For doubles we do the same but we need to consider:
944 * - 2-src instructions can't operate with 64-bit immediates
945 * - The sign is encoded in the high 32-bit of each DF
946 * - We need to produce a DF result.
949 fs_reg zero
= vgrf(glsl_type::double_type
);
950 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
951 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
953 bld
.MOV(result
, zero
);
955 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
956 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
957 brw_imm_ud(0x80000000u
));
959 set_predicate(BRW_PREDICATE_NORMAL
,
960 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
966 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
967 inst
->saturate
= instr
->dest
.saturate
;
971 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
972 inst
->saturate
= instr
->dest
.saturate
;
976 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
977 inst
->saturate
= instr
->dest
.saturate
;
981 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
982 inst
->saturate
= instr
->dest
.saturate
;
986 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
987 inst
->saturate
= instr
->dest
.saturate
;
991 if (fs_key
->high_quality_derivatives
) {
992 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
994 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
996 inst
->saturate
= instr
->dest
.saturate
;
998 case nir_op_fddx_fine
:
999 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1000 inst
->saturate
= instr
->dest
.saturate
;
1002 case nir_op_fddx_coarse
:
1003 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1004 inst
->saturate
= instr
->dest
.saturate
;
1007 if (fs_key
->high_quality_derivatives
) {
1008 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1010 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1012 inst
->saturate
= instr
->dest
.saturate
;
1014 case nir_op_fddy_fine
:
1015 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1016 inst
->saturate
= instr
->dest
.saturate
;
1018 case nir_op_fddy_coarse
:
1019 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1020 inst
->saturate
= instr
->dest
.saturate
;
1025 inst
= bld
.ADD(result
, op
[0], op
[1]);
1026 inst
->saturate
= instr
->dest
.saturate
;
1029 case nir_op_uadd_sat
:
1030 inst
= bld
.ADD(result
, op
[0], op
[1]);
1031 inst
->saturate
= true;
1035 inst
= bld
.MUL(result
, op
[0], op
[1]);
1036 inst
->saturate
= instr
->dest
.saturate
;
1040 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1041 bld
.MUL(result
, op
[0], op
[1]);
1044 case nir_op_imul_high
:
1045 case nir_op_umul_high
:
1046 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1047 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1052 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1053 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1056 case nir_op_uadd_carry
:
1057 unreachable("Should have been lowered by carry_to_arith().");
1059 case nir_op_usub_borrow
:
1060 unreachable("Should have been lowered by borrow_to_arith().");
1064 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1065 * appears that our hardware just does the right thing for signed
1068 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1069 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1073 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1074 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1076 /* Math instructions don't support conditional mod */
1077 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1078 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1080 /* Now, we need to determine if signs of the sources are different.
1081 * When we XOR the sources, the top bit is 0 if they are the same and 1
1082 * if they are different. We can then use a conditional modifier to
1083 * turn that into a predicate. This leads us to an XOR.l instruction.
1085 * Technically, according to the PRM, you're not allowed to use .l on a
1086 * XOR instruction. However, emperical experiments and Curro's reading
1087 * of the simulator source both indicate that it's safe.
1089 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1090 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1091 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1092 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1094 /* If the result of the initial remainder operation is non-zero and the
1095 * two sources have different signs, add in a copy of op[1] to get the
1096 * final integer modulus value.
1098 inst
= bld
.ADD(result
, result
, op
[1]);
1099 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1106 case nir_op_fne32
: {
1107 fs_reg dest
= result
;
1109 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1111 dest
= bld
.vgrf(op
[0].type
, 1);
1113 brw_conditional_mod cond
;
1114 switch (instr
->op
) {
1116 cond
= BRW_CONDITIONAL_L
;
1119 cond
= BRW_CONDITIONAL_GE
;
1122 cond
= BRW_CONDITIONAL_Z
;
1125 cond
= BRW_CONDITIONAL_NZ
;
1128 unreachable("bad opcode");
1131 bld
.CMP(dest
, op
[0], op
[1], cond
);
1133 if (bit_size
> 32) {
1134 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1135 } else if(bit_size
< 32) {
1136 /* When we convert the result to 32-bit we need to be careful and do
1137 * it as a signed conversion to get sign extension (for 32-bit true)
1139 const brw_reg_type src_type
=
1140 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1142 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1152 case nir_op_ine32
: {
1153 fs_reg dest
= result
;
1155 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1157 dest
= bld
.vgrf(op
[0].type
, 1);
1159 brw_conditional_mod cond
;
1160 switch (instr
->op
) {
1163 cond
= BRW_CONDITIONAL_L
;
1167 cond
= BRW_CONDITIONAL_GE
;
1170 cond
= BRW_CONDITIONAL_Z
;
1173 cond
= BRW_CONDITIONAL_NZ
;
1176 unreachable("bad opcode");
1178 bld
.CMP(dest
, op
[0], op
[1], cond
);
1180 if (bit_size
> 32) {
1181 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1182 } else if (bit_size
< 32) {
1183 /* When we convert the result to 32-bit we need to be careful and do
1184 * it as a signed conversion to get sign extension (for 32-bit true)
1186 const brw_reg_type src_type
=
1187 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1189 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1195 if (devinfo
->gen
>= 8) {
1196 nir_alu_instr
*const inot_src_instr
=
1197 nir_src_as_alu_instr(&instr
->src
[0].src
);
1199 if (inot_src_instr
!= NULL
&&
1200 (inot_src_instr
->op
== nir_op_ior
||
1201 inot_src_instr
->op
== nir_op_ixor
||
1202 inot_src_instr
->op
== nir_op_iand
) &&
1203 !inot_src_instr
->src
[0].abs
&&
1204 !inot_src_instr
->src
[0].negate
&&
1205 !inot_src_instr
->src
[1].abs
&&
1206 !inot_src_instr
->src
[1].negate
) {
1207 /* The sources of the source logical instruction are now the
1208 * sources of the instruction that will be generated.
1210 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1211 resolve_inot_sources(bld
, inot_src_instr
, op
);
1213 /* Smash all of the sources and destination to be signed. This
1214 * doesn't matter for the operation of the instruction, but cmod
1215 * propagation fails on unsigned sources with negation (due to
1216 * fs_inst::can_do_cmod returning false).
1219 brw_type_for_nir_type(devinfo
,
1220 (nir_alu_type
)(nir_type_int
|
1221 nir_dest_bit_size(instr
->dest
.dest
)));
1223 brw_type_for_nir_type(devinfo
,
1224 (nir_alu_type
)(nir_type_int
|
1225 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1227 brw_type_for_nir_type(devinfo
,
1228 (nir_alu_type
)(nir_type_int
|
1229 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1231 /* For XOR, only invert one of the sources. Arbitrarily choose
1234 op
[0].negate
= !op
[0].negate
;
1235 if (inot_src_instr
->op
!= nir_op_ixor
)
1236 op
[1].negate
= !op
[1].negate
;
1238 switch (inot_src_instr
->op
) {
1240 bld
.AND(result
, op
[0], op
[1]);
1244 bld
.OR(result
, op
[0], op
[1]);
1248 bld
.XOR(result
, op
[0], op
[1]);
1252 unreachable("impossible opcode");
1255 op
[0] = resolve_source_modifiers(op
[0]);
1257 bld
.NOT(result
, op
[0]);
1260 if (devinfo
->gen
>= 8) {
1261 resolve_inot_sources(bld
, instr
, op
);
1263 bld
.XOR(result
, op
[0], op
[1]);
1266 if (devinfo
->gen
>= 8) {
1267 resolve_inot_sources(bld
, instr
, op
);
1269 bld
.OR(result
, op
[0], op
[1]);
1272 if (devinfo
->gen
>= 8) {
1273 resolve_inot_sources(bld
, instr
, op
);
1275 bld
.AND(result
, op
[0], op
[1]);
1281 case nir_op_b32all_fequal2
:
1282 case nir_op_b32all_iequal2
:
1283 case nir_op_b32all_fequal3
:
1284 case nir_op_b32all_iequal3
:
1285 case nir_op_b32all_fequal4
:
1286 case nir_op_b32all_iequal4
:
1287 case nir_op_b32any_fnequal2
:
1288 case nir_op_b32any_inequal2
:
1289 case nir_op_b32any_fnequal3
:
1290 case nir_op_b32any_inequal3
:
1291 case nir_op_b32any_fnequal4
:
1292 case nir_op_b32any_inequal4
:
1293 unreachable("Lowered by nir_lower_alu_reductions");
1295 case nir_op_fnoise1_1
:
1296 case nir_op_fnoise1_2
:
1297 case nir_op_fnoise1_3
:
1298 case nir_op_fnoise1_4
:
1299 case nir_op_fnoise2_1
:
1300 case nir_op_fnoise2_2
:
1301 case nir_op_fnoise2_3
:
1302 case nir_op_fnoise2_4
:
1303 case nir_op_fnoise3_1
:
1304 case nir_op_fnoise3_2
:
1305 case nir_op_fnoise3_3
:
1306 case nir_op_fnoise3_4
:
1307 case nir_op_fnoise4_1
:
1308 case nir_op_fnoise4_2
:
1309 case nir_op_fnoise4_3
:
1310 case nir_op_fnoise4_4
:
1311 unreachable("not reached: should be handled by lower_noise");
1314 unreachable("not reached: should be handled by ldexp_to_arith()");
1317 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1318 inst
->saturate
= instr
->dest
.saturate
;
1322 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1323 inst
->saturate
= instr
->dest
.saturate
;
1327 case nir_op_f2b32
: {
1328 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1329 if (bit_size
== 64) {
1330 /* two-argument instructions can't take 64-bit immediates */
1334 if (instr
->op
== nir_op_f2b32
) {
1335 zero
= vgrf(glsl_type::double_type
);
1336 tmp
= vgrf(glsl_type::double_type
);
1337 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1339 zero
= vgrf(glsl_type::int64_t_type
);
1340 tmp
= vgrf(glsl_type::int64_t_type
);
1341 bld
.MOV(zero
, brw_imm_q(0));
1344 /* A SIMD16 execution needs to be split in two instructions, so use
1345 * a vgrf instead of the flag register as dst so instruction splitting
1348 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1349 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1352 if (bit_size
== 32) {
1353 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1355 assert(bit_size
== 16);
1356 zero
= instr
->op
== nir_op_f2b32
?
1357 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1359 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1365 inst
= bld
.RNDZ(result
, op
[0]);
1366 inst
->saturate
= instr
->dest
.saturate
;
1369 case nir_op_fceil
: {
1370 op
[0].negate
= !op
[0].negate
;
1371 fs_reg temp
= vgrf(glsl_type::float_type
);
1372 bld
.RNDD(temp
, op
[0]);
1374 inst
= bld
.MOV(result
, temp
);
1375 inst
->saturate
= instr
->dest
.saturate
;
1379 inst
= bld
.RNDD(result
, op
[0]);
1380 inst
->saturate
= instr
->dest
.saturate
;
1383 inst
= bld
.FRC(result
, op
[0]);
1384 inst
->saturate
= instr
->dest
.saturate
;
1386 case nir_op_fround_even
:
1387 inst
= bld
.RNDE(result
, op
[0]);
1388 inst
->saturate
= instr
->dest
.saturate
;
1391 case nir_op_fquantize2f16
: {
1392 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1393 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1394 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1396 /* The destination stride must be at least as big as the source stride. */
1397 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1400 /* Check for denormal */
1401 fs_reg abs_src0
= op
[0];
1402 abs_src0
.abs
= true;
1403 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1405 /* Get the appropriately signed zero */
1406 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1407 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1408 brw_imm_ud(0x80000000));
1409 /* Do the actual F32 -> F16 -> F32 conversion */
1410 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1411 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1412 /* Select that or zero based on normal status */
1413 inst
= bld
.SEL(result
, zero
, tmp32
);
1414 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1415 inst
->saturate
= instr
->dest
.saturate
;
1422 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1423 inst
->saturate
= instr
->dest
.saturate
;
1429 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1430 inst
->saturate
= instr
->dest
.saturate
;
1433 case nir_op_pack_snorm_2x16
:
1434 case nir_op_pack_snorm_4x8
:
1435 case nir_op_pack_unorm_2x16
:
1436 case nir_op_pack_unorm_4x8
:
1437 case nir_op_unpack_snorm_2x16
:
1438 case nir_op_unpack_snorm_4x8
:
1439 case nir_op_unpack_unorm_2x16
:
1440 case nir_op_unpack_unorm_4x8
:
1441 case nir_op_unpack_half_2x16
:
1442 case nir_op_pack_half_2x16
:
1443 unreachable("not reached: should be handled by lower_packing_builtins");
1445 case nir_op_unpack_half_2x16_split_x
:
1446 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1447 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1448 inst
->saturate
= instr
->dest
.saturate
;
1450 case nir_op_unpack_half_2x16_split_y
:
1451 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1452 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1453 inst
->saturate
= instr
->dest
.saturate
;
1456 case nir_op_pack_64_2x32_split
:
1457 case nir_op_pack_32_2x16_split
:
1458 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1461 case nir_op_unpack_64_2x32_split_x
:
1462 case nir_op_unpack_64_2x32_split_y
: {
1463 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1464 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1466 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1470 case nir_op_unpack_32_2x16_split_x
:
1471 case nir_op_unpack_32_2x16_split_y
: {
1472 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1473 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1475 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1480 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1481 inst
->saturate
= instr
->dest
.saturate
;
1484 case nir_op_bitfield_reverse
:
1485 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1486 bld
.BFREV(result
, op
[0]);
1489 case nir_op_bit_count
:
1490 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1491 bld
.CBIT(result
, op
[0]);
1494 case nir_op_ufind_msb
: {
1495 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1496 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1500 case nir_op_ifind_msb
: {
1501 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1503 if (devinfo
->gen
< 7) {
1504 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1506 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1508 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1509 * count from the LSB side. If FBH didn't return an error
1510 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1511 * count into an LSB count.
1513 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1515 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1516 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1517 inst
->src
[0].negate
= true;
1522 case nir_op_find_lsb
:
1523 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1525 if (devinfo
->gen
< 7) {
1526 fs_reg temp
= vgrf(glsl_type::int_type
);
1528 /* (x & -x) generates a value that consists of only the LSB of x.
1529 * For all powers of 2, findMSB(y) == findLSB(y).
1531 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1532 fs_reg negated_src
= src
;
1534 /* One must be negated, and the other must be non-negated. It
1535 * doesn't matter which is which.
1537 negated_src
.negate
= true;
1540 bld
.AND(temp
, src
, negated_src
);
1541 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1543 bld
.FBL(result
, op
[0]);
1547 case nir_op_ubitfield_extract
:
1548 case nir_op_ibitfield_extract
:
1549 unreachable("should have been lowered");
1552 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1553 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1556 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1557 bld
.BFI1(result
, op
[0], op
[1]);
1560 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1561 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1564 case nir_op_bitfield_insert
:
1565 unreachable("not reached: should have been lowered");
1568 bld
.SHL(result
, op
[0], op
[1]);
1571 bld
.ASR(result
, op
[0], op
[1]);
1574 bld
.SHR(result
, op
[0], op
[1]);
1577 case nir_op_pack_half_2x16_split
:
1578 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1582 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1583 inst
->saturate
= instr
->dest
.saturate
;
1587 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1588 inst
->saturate
= instr
->dest
.saturate
;
1591 case nir_op_b32csel
:
1592 if (optimize_frontfacing_ternary(instr
, result
))
1595 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1596 inst
= bld
.SEL(result
, op
[1], op
[2]);
1597 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1600 case nir_op_extract_u8
:
1601 case nir_op_extract_i8
: {
1602 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1607 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1608 * Use two instructions and a word or DWord intermediate integer type.
1610 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1611 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i8
);
1613 if (instr
->op
== nir_op_extract_i8
) {
1614 /* If we need to sign extend, extract to a word first */
1615 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1616 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1617 bld
.MOV(result
, w_temp
);
1619 /* Otherwise use an AND with 0xff and a word type */
1620 bld
.AND(result
, subscript(op
[0], type
, byte
/ 2), brw_imm_uw(0xff));
1623 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1624 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1629 case nir_op_extract_u16
:
1630 case nir_op_extract_i16
: {
1631 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1632 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1633 bld
.MOV(result
, subscript(op
[0], type
, word
));
1638 unreachable("unhandled instruction");
1641 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1642 * to sign extend the low bit to 0/~0
1644 if (devinfo
->gen
<= 5 &&
1645 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1646 fs_reg masked
= vgrf(glsl_type::int_type
);
1647 bld
.AND(masked
, result
, brw_imm_d(1));
1648 masked
.negate
= true;
1649 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1654 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1655 nir_load_const_instr
*instr
)
1657 const brw_reg_type reg_type
=
1658 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1659 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1661 switch (instr
->def
.bit_size
) {
1663 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1664 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
.i8
[i
]));
1668 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1669 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
.i16
[i
]));
1673 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1674 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1678 assert(devinfo
->gen
>= 7);
1679 if (devinfo
->gen
== 7) {
1680 /* We don't get 64-bit integer types until gen8 */
1681 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1682 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1683 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1686 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1687 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
.i64
[i
]));
1692 unreachable("Invalid bit size");
1695 nir_ssa_values
[instr
->def
.index
] = reg
;
1699 fs_visitor::get_nir_src(const nir_src
&src
)
1703 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1704 const brw_reg_type reg_type
=
1705 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1706 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1708 reg
= nir_ssa_values
[src
.ssa
->index
];
1711 /* We don't handle indirects on locals */
1712 assert(src
.reg
.indirect
== NULL
);
1713 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1714 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1717 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1718 /* The only 64-bit type available on gen7 is DF, so use that. */
1719 reg
.type
= BRW_REGISTER_TYPE_DF
;
1721 /* To avoid floating-point denorm flushing problems, set the type by
1722 * default to an integer type - instructions that need floating point
1723 * semantics will set this to F if they need to
1725 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1726 BRW_REGISTER_TYPE_D
);
1733 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1735 * This function should not be called on any value which may be 64 bits.
1736 * We could theoretically support 64-bit on gen8+ but we choose not to
1737 * because it wouldn't work in general (no gen7 support) and there are
1738 * enough restrictions in 64-bit immediates that you can't take the return
1739 * value and treat it the same as the result of get_nir_src().
1742 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1744 assert(nir_src_bit_size(src
) == 32);
1745 return nir_src_is_const(src
) ?
1746 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1750 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1753 const brw_reg_type reg_type
=
1754 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1755 dest
.ssa
.bit_size
== 8 ?
1756 BRW_REGISTER_TYPE_D
:
1757 BRW_REGISTER_TYPE_F
);
1758 nir_ssa_values
[dest
.ssa
.index
] =
1759 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1760 return nir_ssa_values
[dest
.ssa
.index
];
1762 /* We don't handle indirects on locals */
1763 assert(dest
.reg
.indirect
== NULL
);
1764 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1765 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1770 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1773 for (unsigned i
= 0; i
< 4; i
++) {
1774 if (!((wr_mask
>> i
) & 1))
1777 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1778 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1779 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1780 if (new_inst
->src
[j
].file
== VGRF
)
1781 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1788 emit_pixel_interpolater_send(const fs_builder
&bld
,
1793 glsl_interp_mode interpolation
)
1795 struct brw_wm_prog_data
*wm_prog_data
=
1796 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1798 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1799 /* 2 floats per slot returned */
1800 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1801 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1803 wm_prog_data
->pulls_bary
= true;
1809 * Computes 1 << x, given a D/UD register containing some value x.
1812 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1814 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1816 fs_reg result
= bld
.vgrf(x
.type
, 1);
1817 fs_reg one
= bld
.vgrf(x
.type
, 1);
1819 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1820 bld
.SHL(result
, one
, x
);
1825 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1827 assert(stage
== MESA_SHADER_GEOMETRY
);
1829 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1831 if (gs_compile
->control_data_header_size_bits
== 0)
1834 /* We can only do EndPrimitive() functionality when the control data
1835 * consists of cut bits. Fortunately, the only time it isn't is when the
1836 * output type is points, in which case EndPrimitive() is a no-op.
1838 if (gs_prog_data
->control_data_format
!=
1839 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1843 /* Cut bits use one bit per vertex. */
1844 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1846 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1847 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1849 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1850 * vertex n, 0 otherwise. So all we need to do here is mark bit
1851 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1852 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1853 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1855 * Note that if EndPrimitive() is called before emitting any vertices, this
1856 * will cause us to set bit 31 of the control_data_bits register to 1.
1857 * That's fine because:
1859 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1860 * output, so the hardware will ignore cut bit 31.
1862 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1863 * last vertex, so setting cut bit 31 has no effect (since the primitive
1864 * is automatically ended when the GS terminates).
1866 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1867 * control_data_bits register to 0 when the first vertex is emitted.
1870 const fs_builder abld
= bld
.annotate("end primitive");
1872 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1873 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1874 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1875 fs_reg mask
= intexp2(abld
, prev_count
);
1876 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1877 * attention to the lower 5 bits of its second source argument, so on this
1878 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1879 * ((vertex_count - 1) % 32).
1881 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1885 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1887 assert(stage
== MESA_SHADER_GEOMETRY
);
1888 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1890 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1892 const fs_builder abld
= bld
.annotate("emit control data bits");
1893 const fs_builder fwa_bld
= bld
.exec_all();
1895 /* We use a single UD register to accumulate control data bits (32 bits
1896 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1899 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1900 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1901 * use the Channel Mask phase to enable/disable which DWord within that
1902 * group to write. (Remember, different SIMD8 channels may have emitted
1903 * different numbers of vertices, so we may need per-slot offsets.)
1905 * Channel masking presents an annoying problem: we may have to replicate
1906 * the data up to 4 times:
1908 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1910 * To avoid penalizing shaders that emit a small number of vertices, we
1911 * can avoid these sometimes: if the size of the control data header is
1912 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1913 * land in the same 128-bit group, so we can skip per-slot offsets.
1915 * Similarly, if the control data header is <= 32 bits, there is only one
1916 * DWord, so we can skip channel masks.
1918 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1920 fs_reg channel_mask
, per_slot_offset
;
1922 if (gs_compile
->control_data_header_size_bits
> 32) {
1923 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1924 channel_mask
= vgrf(glsl_type::uint_type
);
1927 if (gs_compile
->control_data_header_size_bits
> 128) {
1928 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1929 per_slot_offset
= vgrf(glsl_type::uint_type
);
1932 /* Figure out which DWord we're trying to write to using the formula:
1934 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1936 * Since bits_per_vertex is a power of two, and is known at compile
1937 * time, this can be optimized to:
1939 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1941 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1942 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1943 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1944 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1945 unsigned log2_bits_per_vertex
=
1946 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1947 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1949 if (per_slot_offset
.file
!= BAD_FILE
) {
1950 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1951 * the appropriate OWord within the control data header.
1953 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1956 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1957 * write to the appropriate DWORD within the OWORD.
1959 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1960 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1961 channel_mask
= intexp2(fwa_bld
, channel
);
1962 /* Then the channel masks need to be in bits 23:16. */
1963 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1966 /* Store the control data bits in the message payload and send it. */
1968 if (channel_mask
.file
!= BAD_FILE
)
1969 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1970 if (per_slot_offset
.file
!= BAD_FILE
)
1973 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1974 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1976 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1977 if (per_slot_offset
.file
!= BAD_FILE
)
1978 sources
[i
++] = per_slot_offset
;
1979 if (channel_mask
.file
!= BAD_FILE
)
1980 sources
[i
++] = channel_mask
;
1982 sources
[i
++] = this->control_data_bits
;
1985 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1986 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1988 /* We need to increment Global Offset by 256-bits to make room for
1989 * Broadwell's extra "Vertex Count" payload at the beginning of the
1990 * URB entry. Since this is an OWord message, Global Offset is counted
1991 * in 128-bit units, so we must set it to 2.
1993 if (gs_prog_data
->static_vertex_count
== -1)
1998 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2001 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2003 /* Note: we are calling this *before* increasing vertex_count, so
2004 * this->vertex_count == vertex_count - 1 in the formula above.
2007 /* Stream mode uses 2 bits per vertex */
2008 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2010 /* Must be a valid stream */
2011 assert(stream_id
< MAX_VERTEX_STREAMS
);
2013 /* Control data bits are initialized to 0 so we don't have to set any
2014 * bits when sending vertices to stream 0.
2019 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2021 /* reg::sid = stream_id */
2022 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2023 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2025 /* reg:shift_count = 2 * (vertex_count - 1) */
2026 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2027 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2029 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2030 * attention to the lower 5 bits of its second source argument, so on this
2031 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2032 * stream_id << ((2 * (vertex_count - 1)) % 32).
2034 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2035 abld
.SHL(mask
, sid
, shift_count
);
2036 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2040 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2043 assert(stage
== MESA_SHADER_GEOMETRY
);
2045 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2047 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2048 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2050 /* Haswell and later hardware ignores the "Render Stream Select" bits
2051 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2052 * and instead sends all primitives down the pipeline for rasterization.
2053 * If the SOL stage is enabled, "Render Stream Select" is honored and
2054 * primitives bound to non-zero streams are discarded after stream output.
2056 * Since the only purpose of primives sent to non-zero streams is to
2057 * be recorded by transform feedback, we can simply discard all geometry
2058 * bound to these streams when transform feedback is disabled.
2060 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2063 /* If we're outputting 32 control data bits or less, then we can wait
2064 * until the shader is over to output them all. Otherwise we need to
2065 * output them as we go. Now is the time to do it, since we're about to
2066 * output the vertex_count'th vertex, so it's guaranteed that the
2067 * control data bits associated with the (vertex_count - 1)th vertex are
2070 if (gs_compile
->control_data_header_size_bits
> 32) {
2071 const fs_builder abld
=
2072 bld
.annotate("emit vertex: emit control data bits");
2074 /* Only emit control data bits if we've finished accumulating a batch
2075 * of 32 bits. This is the case when:
2077 * (vertex_count * bits_per_vertex) % 32 == 0
2079 * (in other words, when the last 5 bits of vertex_count *
2080 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2081 * integer n (which is always the case, since bits_per_vertex is
2082 * always 1 or 2), this is equivalent to requiring that the last 5-n
2083 * bits of vertex_count are 0:
2085 * vertex_count & (2^(5-n) - 1) == 0
2087 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2090 * vertex_count & (32 / bits_per_vertex - 1) == 0
2092 * TODO: If vertex_count is an immediate, we could do some of this math
2093 * at compile time...
2096 abld
.AND(bld
.null_reg_d(), vertex_count
,
2097 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2098 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2100 abld
.IF(BRW_PREDICATE_NORMAL
);
2101 /* If vertex_count is 0, then no control data bits have been
2102 * accumulated yet, so we can skip emitting them.
2104 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2105 BRW_CONDITIONAL_NEQ
);
2106 abld
.IF(BRW_PREDICATE_NORMAL
);
2107 emit_gs_control_data_bits(vertex_count
);
2108 abld
.emit(BRW_OPCODE_ENDIF
);
2110 /* Reset control_data_bits to 0 so we can start accumulating a new
2113 * Note: in the case where vertex_count == 0, this neutralizes the
2114 * effect of any call to EndPrimitive() that the shader may have
2115 * made before outputting its first vertex.
2117 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2118 inst
->force_writemask_all
= true;
2119 abld
.emit(BRW_OPCODE_ENDIF
);
2122 emit_urb_writes(vertex_count
);
2124 /* In stream mode we have to set control data bits for all vertices
2125 * unless we have disabled control data bits completely (which we do
2126 * do for GL_POINTS outputs that don't use streams).
2128 if (gs_compile
->control_data_header_size_bits
> 0 &&
2129 gs_prog_data
->control_data_format
==
2130 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2131 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2136 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2137 const nir_src
&vertex_src
,
2138 unsigned base_offset
,
2139 const nir_src
&offset_src
,
2140 unsigned num_components
,
2141 unsigned first_component
)
2143 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2144 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2146 /* TODO: figure out push input layout for invocations == 1 */
2147 /* TODO: make this work with 64-bit inputs */
2148 if (gs_prog_data
->invocations
== 1 &&
2149 type_sz(dst
.type
) <= 4 &&
2150 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2151 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2152 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2153 nir_src_as_uint(vertex_src
) * push_reg_count
;
2154 for (unsigned i
= 0; i
< num_components
; i
++) {
2155 bld
.MOV(offset(dst
, bld
, i
),
2156 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2161 /* Resort to the pull model. Ensure the VUE handles are provided. */
2162 assert(gs_prog_data
->base
.include_vue_handles
);
2164 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2165 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2167 if (gs_prog_data
->invocations
== 1) {
2168 if (nir_src_is_const(vertex_src
)) {
2169 /* The vertex index is constant; just select the proper URB handle. */
2171 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2172 BRW_REGISTER_TYPE_UD
);
2174 /* The vertex index is non-constant. We need to use indirect
2175 * addressing to fetch the proper URB handle.
2177 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2178 * indicating that channel <n> should read the handle from
2179 * DWord <n>. We convert that to bytes by multiplying by 4.
2181 * Next, we convert the vertex index to bytes by multiplying
2182 * by 32 (shifting by 5), and add the two together. This is
2183 * the final indirect byte offset.
2185 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2186 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2187 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2188 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2190 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2191 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2192 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2193 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2194 /* Convert vertex_index to bytes (multiply by 32) */
2195 bld
.SHL(vertex_offset_bytes
,
2196 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2198 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2200 /* Use first_icp_handle as the base offset. There is one register
2201 * of URB handles per vertex, so inform the register allocator that
2202 * we might read up to nir->info.gs.vertices_in registers.
2204 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2205 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2206 fs_reg(icp_offset_bytes
),
2207 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2210 assert(gs_prog_data
->invocations
> 1);
2212 if (nir_src_is_const(vertex_src
)) {
2213 unsigned vertex
= nir_src_as_uint(vertex_src
);
2214 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2216 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2217 BRW_REGISTER_TYPE_UD
));
2219 /* The vertex index is non-constant. We need to use indirect
2220 * addressing to fetch the proper URB handle.
2223 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2225 /* Convert vertex_index to bytes (multiply by 4) */
2226 bld
.SHL(icp_offset_bytes
,
2227 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2230 /* Use first_icp_handle as the base offset. There is one DWord
2231 * of URB handles per vertex, so inform the register allocator that
2232 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2234 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2235 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2236 fs_reg(icp_offset_bytes
),
2237 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2244 fs_reg tmp_dst
= dst
;
2245 fs_reg indirect_offset
= get_nir_src(offset_src
);
2246 unsigned num_iterations
= 1;
2247 unsigned orig_num_components
= num_components
;
2249 if (type_sz(dst
.type
) == 8) {
2250 if (num_components
> 2) {
2254 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2256 first_component
= first_component
/ 2;
2259 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2260 if (nir_src_is_const(offset_src
)) {
2261 /* Constant indexing - use global offset. */
2262 if (first_component
!= 0) {
2263 unsigned read_components
= num_components
+ first_component
;
2264 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2265 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2266 inst
->size_written
= read_components
*
2267 tmp
.component_size(inst
->exec_size
);
2268 for (unsigned i
= 0; i
< num_components
; i
++) {
2269 bld
.MOV(offset(tmp_dst
, bld
, i
),
2270 offset(tmp
, bld
, i
+ first_component
));
2273 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2275 inst
->size_written
= num_components
*
2276 tmp_dst
.component_size(inst
->exec_size
);
2278 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2281 /* Indirect indexing - use per-slot offsets as well. */
2282 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2283 unsigned read_components
= num_components
+ first_component
;
2284 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2285 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2286 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2287 if (first_component
!= 0) {
2288 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2290 inst
->size_written
= read_components
*
2291 tmp
.component_size(inst
->exec_size
);
2292 for (unsigned i
= 0; i
< num_components
; i
++) {
2293 bld
.MOV(offset(tmp_dst
, bld
, i
),
2294 offset(tmp
, bld
, i
+ first_component
));
2297 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2299 inst
->size_written
= num_components
*
2300 tmp_dst
.component_size(inst
->exec_size
);
2302 inst
->offset
= base_offset
;
2306 if (type_sz(dst
.type
) == 8) {
2307 shuffle_from_32bit_read(bld
,
2308 offset(dst
, bld
, iter
* 2),
2309 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2314 if (num_iterations
> 1) {
2315 num_components
= orig_num_components
- 2;
2316 if(nir_src_is_const(offset_src
)) {
2319 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2320 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2321 indirect_offset
= new_indirect
;
2328 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2330 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2332 if (nir_src_is_const(*offset_src
)) {
2333 /* The only constant offset we should find is 0. brw_nir.c's
2334 * add_const_offset_to_base() will fold other constant offsets
2335 * into instr->const_index[0].
2337 assert(nir_src_as_uint(*offset_src
) == 0);
2341 return get_nir_src(*offset_src
);
2345 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2346 nir_intrinsic_instr
*instr
)
2348 assert(stage
== MESA_SHADER_VERTEX
);
2351 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2352 dest
= get_nir_dest(instr
->dest
);
2354 switch (instr
->intrinsic
) {
2355 case nir_intrinsic_load_vertex_id
:
2356 case nir_intrinsic_load_base_vertex
:
2357 unreachable("should be lowered by nir_lower_system_values()");
2359 case nir_intrinsic_load_input
: {
2360 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2361 unsigned first_component
= nir_intrinsic_component(instr
);
2362 unsigned num_components
= instr
->num_components
;
2364 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2366 if (type_sz(dest
.type
) == 8)
2367 first_component
/= 2;
2369 /* For 16-bit support maybe a temporary will be needed to copy from
2372 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2373 first_component
, num_components
);
2377 case nir_intrinsic_load_vertex_id_zero_base
:
2378 case nir_intrinsic_load_instance_id
:
2379 case nir_intrinsic_load_base_instance
:
2380 case nir_intrinsic_load_draw_id
:
2381 case nir_intrinsic_load_first_vertex
:
2382 case nir_intrinsic_load_is_indexed_draw
:
2383 unreachable("lowered by brw_nir_lower_vs_inputs");
2386 nir_emit_intrinsic(bld
, instr
);
2392 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2393 nir_intrinsic_instr
*instr
)
2395 assert(stage
== MESA_SHADER_TESS_CTRL
);
2396 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2397 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2400 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2401 dst
= get_nir_dest(instr
->dest
);
2403 switch (instr
->intrinsic
) {
2404 case nir_intrinsic_load_primitive_id
:
2405 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2407 case nir_intrinsic_load_invocation_id
:
2408 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2410 case nir_intrinsic_load_patch_vertices_in
:
2411 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2412 brw_imm_d(tcs_key
->input_vertices
));
2415 case nir_intrinsic_barrier
: {
2416 if (tcs_prog_data
->instances
== 1)
2419 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2420 fs_reg m0_2
= component(m0
, 2);
2422 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2424 /* Zero the message header */
2425 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2427 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2428 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2429 brw_imm_ud(INTEL_MASK(16, 13)));
2431 /* Shift it up to bits 27:24. */
2432 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2434 /* Set the Barrier Count and the enable bit */
2435 chanbld
.OR(m0_2
, m0_2
,
2436 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2438 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2442 case nir_intrinsic_load_input
:
2443 unreachable("nir_lower_io should never give us these.");
2446 case nir_intrinsic_load_per_vertex_input
: {
2447 fs_reg indirect_offset
= get_indirect_offset(instr
);
2448 unsigned imm_offset
= instr
->const_index
[0];
2450 const nir_src
&vertex_src
= instr
->src
[0];
2456 if (nir_src_is_const(vertex_src
)) {
2457 /* Emit a MOV to resolve <0,1,0> regioning. */
2458 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2459 unsigned vertex
= nir_src_as_uint(vertex_src
);
2461 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2462 BRW_REGISTER_TYPE_UD
));
2463 } else if (tcs_prog_data
->instances
== 1 &&
2464 vertex_src
.is_ssa
&&
2465 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2466 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2467 /* For the common case of only 1 instance, an array index of
2468 * gl_InvocationID means reading g1. Skip all the indirect work.
2470 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2472 /* The vertex index is non-constant. We need to use indirect
2473 * addressing to fetch the proper URB handle.
2475 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2477 /* Each ICP handle is a single DWord (4 bytes) */
2478 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2479 bld
.SHL(vertex_offset_bytes
,
2480 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2483 /* Start at g1. We might read up to 4 registers. */
2484 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2485 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2486 brw_imm_ud(4 * REG_SIZE
));
2489 /* We can only read two double components with each URB read, so
2490 * we send two read messages in that case, each one loading up to
2491 * two double components.
2493 unsigned num_iterations
= 1;
2494 unsigned num_components
= instr
->num_components
;
2495 unsigned first_component
= nir_intrinsic_component(instr
);
2496 fs_reg orig_dst
= dst
;
2497 if (type_sz(dst
.type
) == 8) {
2498 first_component
= first_component
/ 2;
2499 if (instr
->num_components
> 2) {
2504 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2508 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2509 if (indirect_offset
.file
== BAD_FILE
) {
2510 /* Constant indexing - use global offset. */
2511 if (first_component
!= 0) {
2512 unsigned read_components
= num_components
+ first_component
;
2513 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2514 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2515 for (unsigned i
= 0; i
< num_components
; i
++) {
2516 bld
.MOV(offset(dst
, bld
, i
),
2517 offset(tmp
, bld
, i
+ first_component
));
2520 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2522 inst
->offset
= imm_offset
;
2525 /* Indirect indexing - use per-slot offsets as well. */
2526 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2527 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2528 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2529 if (first_component
!= 0) {
2530 unsigned read_components
= num_components
+ first_component
;
2531 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2532 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2534 for (unsigned i
= 0; i
< num_components
; i
++) {
2535 bld
.MOV(offset(dst
, bld
, i
),
2536 offset(tmp
, bld
, i
+ first_component
));
2539 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2542 inst
->offset
= imm_offset
;
2545 inst
->size_written
= (num_components
+ first_component
) *
2546 inst
->dst
.component_size(inst
->exec_size
);
2548 /* If we are reading 64-bit data using 32-bit read messages we need
2549 * build proper 64-bit data elements by shuffling the low and high
2550 * 32-bit components around like we do for other things like UBOs
2553 if (type_sz(dst
.type
) == 8) {
2554 shuffle_from_32bit_read(bld
,
2555 offset(orig_dst
, bld
, iter
* 2),
2556 retype(dst
, BRW_REGISTER_TYPE_D
),
2560 /* Copy the temporary to the destination to deal with writemasking.
2562 * Also attempt to deal with gl_PointSize being in the .w component.
2564 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2565 assert(type_sz(dst
.type
) < 8);
2566 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2567 inst
->size_written
= 4 * REG_SIZE
;
2568 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2571 /* If we are loading double data and we need a second read message
2572 * adjust the write offset
2574 if (num_iterations
> 1) {
2575 num_components
= instr
->num_components
- 2;
2582 case nir_intrinsic_load_output
:
2583 case nir_intrinsic_load_per_vertex_output
: {
2584 fs_reg indirect_offset
= get_indirect_offset(instr
);
2585 unsigned imm_offset
= instr
->const_index
[0];
2586 unsigned first_component
= nir_intrinsic_component(instr
);
2589 if (indirect_offset
.file
== BAD_FILE
) {
2590 /* Replicate the patch handle to all enabled channels */
2591 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2592 bld
.MOV(patch_handle
,
2593 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2596 if (first_component
!= 0) {
2597 unsigned read_components
=
2598 instr
->num_components
+ first_component
;
2599 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2600 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2602 inst
->size_written
= read_components
* REG_SIZE
;
2603 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2604 bld
.MOV(offset(dst
, bld
, i
),
2605 offset(tmp
, bld
, i
+ first_component
));
2608 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2610 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2612 inst
->offset
= imm_offset
;
2616 /* Indirect indexing - use per-slot offsets as well. */
2617 const fs_reg srcs
[] = {
2618 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2621 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2622 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2623 if (first_component
!= 0) {
2624 unsigned read_components
=
2625 instr
->num_components
+ first_component
;
2626 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2627 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2629 inst
->size_written
= read_components
* REG_SIZE
;
2630 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2631 bld
.MOV(offset(dst
, bld
, i
),
2632 offset(tmp
, bld
, i
+ first_component
));
2635 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2637 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2639 inst
->offset
= imm_offset
;
2645 case nir_intrinsic_store_output
:
2646 case nir_intrinsic_store_per_vertex_output
: {
2647 fs_reg value
= get_nir_src(instr
->src
[0]);
2648 bool is_64bit
= (instr
->src
[0].is_ssa
?
2649 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2650 fs_reg indirect_offset
= get_indirect_offset(instr
);
2651 unsigned imm_offset
= instr
->const_index
[0];
2652 unsigned mask
= instr
->const_index
[1];
2653 unsigned header_regs
= 0;
2655 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2657 if (indirect_offset
.file
!= BAD_FILE
) {
2658 srcs
[header_regs
++] = indirect_offset
;
2664 unsigned num_components
= util_last_bit(mask
);
2667 /* We can only pack two 64-bit components in a single message, so send
2668 * 2 messages if we have more components
2670 unsigned num_iterations
= 1;
2671 unsigned iter_components
= num_components
;
2672 unsigned first_component
= nir_intrinsic_component(instr
);
2674 first_component
= first_component
/ 2;
2675 if (instr
->num_components
> 2) {
2677 iter_components
= 2;
2681 mask
= mask
<< first_component
;
2683 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2684 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2685 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2686 opcode
= indirect_offset
.file
!= BAD_FILE
?
2687 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2688 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2689 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2690 /* Expand the 64-bit mask to 32-bit channels. We only handle
2691 * two channels in each iteration, so we only care about X/Y.
2693 unsigned mask32
= 0;
2694 if (mask
& WRITEMASK_X
)
2695 mask32
|= WRITEMASK_XY
;
2696 if (mask
& WRITEMASK_Y
)
2697 mask32
|= WRITEMASK_ZW
;
2699 /* If the mask does not include any of the channels X or Y there
2700 * is nothing to do in this iteration. Move on to the next couple
2701 * of 64-bit channels.
2709 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2710 opcode
= indirect_offset
.file
!= BAD_FILE
?
2711 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2712 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2714 opcode
= indirect_offset
.file
!= BAD_FILE
?
2715 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2716 SHADER_OPCODE_URB_WRITE_SIMD8
;
2719 for (unsigned i
= 0; i
< iter_components
; i
++) {
2720 if (!(mask
& (1 << (i
+ first_component
))))
2724 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2726 /* We need to shuffle the 64-bit data to match the layout
2727 * expected by our 32-bit URB write messages. We use a temporary
2730 unsigned channel
= iter
* 2 + i
;
2731 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2733 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2734 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2735 offset(dest
, bld
, 1);
2740 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2741 (is_64bit
? 2 * first_component
: first_component
);
2743 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2744 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2746 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2747 inst
->offset
= imm_offset
;
2750 /* If this is a 64-bit attribute, select the next two 64-bit channels
2751 * to be handled in the next iteration.
2762 nir_emit_intrinsic(bld
, instr
);
2768 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2769 nir_intrinsic_instr
*instr
)
2771 assert(stage
== MESA_SHADER_TESS_EVAL
);
2772 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2775 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2776 dest
= get_nir_dest(instr
->dest
);
2778 switch (instr
->intrinsic
) {
2779 case nir_intrinsic_load_primitive_id
:
2780 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2782 case nir_intrinsic_load_tess_coord
:
2783 /* gl_TessCoord is part of the payload in g1-3 */
2784 for (unsigned i
= 0; i
< 3; i
++) {
2785 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2789 case nir_intrinsic_load_input
:
2790 case nir_intrinsic_load_per_vertex_input
: {
2791 fs_reg indirect_offset
= get_indirect_offset(instr
);
2792 unsigned imm_offset
= instr
->const_index
[0];
2793 unsigned first_component
= nir_intrinsic_component(instr
);
2795 if (type_sz(dest
.type
) == 8) {
2796 first_component
= first_component
/ 2;
2800 if (indirect_offset
.file
== BAD_FILE
) {
2801 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2802 * which is 16 registers (since each holds 2 vec4 slots).
2804 unsigned slot_count
= 1;
2805 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2808 const unsigned max_push_slots
= 32;
2809 if (imm_offset
+ slot_count
<= max_push_slots
) {
2810 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2811 for (int i
= 0; i
< instr
->num_components
; i
++) {
2812 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2813 i
+ first_component
;
2814 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2817 tes_prog_data
->base
.urb_read_length
=
2818 MAX2(tes_prog_data
->base
.urb_read_length
,
2819 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2821 /* Replicate the patch handle to all enabled channels */
2822 const fs_reg srcs
[] = {
2823 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2825 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2826 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2828 if (first_component
!= 0) {
2829 unsigned read_components
=
2830 instr
->num_components
+ first_component
;
2831 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2832 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2834 inst
->size_written
= read_components
* REG_SIZE
;
2835 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2836 bld
.MOV(offset(dest
, bld
, i
),
2837 offset(tmp
, bld
, i
+ first_component
));
2840 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2842 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2845 inst
->offset
= imm_offset
;
2848 /* Indirect indexing - use per-slot offsets as well. */
2850 /* We can only read two double components with each URB read, so
2851 * we send two read messages in that case, each one loading up to
2852 * two double components.
2854 unsigned num_iterations
= 1;
2855 unsigned num_components
= instr
->num_components
;
2856 fs_reg orig_dest
= dest
;
2857 if (type_sz(dest
.type
) == 8) {
2858 if (instr
->num_components
> 2) {
2862 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2866 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2867 const fs_reg srcs
[] = {
2868 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2871 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2872 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2874 if (first_component
!= 0) {
2875 unsigned read_components
=
2876 num_components
+ first_component
;
2877 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2878 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2880 for (unsigned i
= 0; i
< num_components
; i
++) {
2881 bld
.MOV(offset(dest
, bld
, i
),
2882 offset(tmp
, bld
, i
+ first_component
));
2885 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2889 inst
->offset
= imm_offset
;
2890 inst
->size_written
= (num_components
+ first_component
) *
2891 inst
->dst
.component_size(inst
->exec_size
);
2893 /* If we are reading 64-bit data using 32-bit read messages we need
2894 * build proper 64-bit data elements by shuffling the low and high
2895 * 32-bit components around like we do for other things like UBOs
2898 if (type_sz(dest
.type
) == 8) {
2899 shuffle_from_32bit_read(bld
,
2900 offset(orig_dest
, bld
, iter
* 2),
2901 retype(dest
, BRW_REGISTER_TYPE_D
),
2905 /* If we are loading double data and we need a second read message
2908 if (num_iterations
> 1) {
2909 num_components
= instr
->num_components
- 2;
2917 nir_emit_intrinsic(bld
, instr
);
2923 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2924 nir_intrinsic_instr
*instr
)
2926 assert(stage
== MESA_SHADER_GEOMETRY
);
2927 fs_reg indirect_offset
;
2930 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2931 dest
= get_nir_dest(instr
->dest
);
2933 switch (instr
->intrinsic
) {
2934 case nir_intrinsic_load_primitive_id
:
2935 assert(stage
== MESA_SHADER_GEOMETRY
);
2936 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2937 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2938 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2941 case nir_intrinsic_load_input
:
2942 unreachable("load_input intrinsics are invalid for the GS stage");
2944 case nir_intrinsic_load_per_vertex_input
:
2945 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2946 instr
->src
[1], instr
->num_components
,
2947 nir_intrinsic_component(instr
));
2950 case nir_intrinsic_emit_vertex_with_counter
:
2951 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2954 case nir_intrinsic_end_primitive_with_counter
:
2955 emit_gs_end_primitive(instr
->src
[0]);
2958 case nir_intrinsic_set_vertex_count
:
2959 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2962 case nir_intrinsic_load_invocation_id
: {
2963 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2964 assert(val
.file
!= BAD_FILE
);
2965 dest
.type
= val
.type
;
2971 nir_emit_intrinsic(bld
, instr
);
2977 * Fetch the current render target layer index.
2980 fetch_render_target_array_index(const fs_builder
&bld
)
2982 if (bld
.shader
->devinfo
->gen
>= 6) {
2983 /* The render target array index is provided in the thread payload as
2984 * bits 26:16 of r0.0.
2986 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2987 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2991 /* Pre-SNB we only ever render into the first layer of the framebuffer
2992 * since layered rendering is not implemented.
2994 return brw_imm_ud(0);
2999 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3000 * framebuffer at the current fragment coordinates and sample index.
3003 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3006 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3008 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3009 const brw_wm_prog_key
*wm_key
=
3010 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3011 assert(!wm_key
->coherent_fb_fetch
);
3012 const struct brw_wm_prog_data
*wm_prog_data
=
3013 brw_wm_prog_data(stage_prog_data
);
3015 /* Calculate the surface index relative to the start of the texture binding
3016 * table block, since that's what the texturing messages expect.
3018 const unsigned surface
= target
+
3019 wm_prog_data
->binding_table
.render_target_read_start
-
3020 wm_prog_data
->base
.binding_table
.texture_start
;
3022 /* Calculate the fragment coordinates. */
3023 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3024 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3025 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3026 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3028 /* Calculate the sample index and MCS payload when multisampling. Luckily
3029 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3030 * shouldn't be necessary to recompile based on whether the framebuffer is
3033 if (wm_key
->multisample_fbo
&&
3034 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3035 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3037 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3038 const fs_reg mcs
= wm_key
->multisample_fbo
?
3039 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3041 /* Use either a normal or a CMS texel fetch message depending on whether
3042 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3043 * message just in case the framebuffer uses 16x multisampling, it should
3044 * be equivalent to the normal CMS fetch for lower multisampling modes.
3046 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3047 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3048 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3050 /* Emit the instruction. */
3051 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3052 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3053 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3054 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3055 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3056 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3057 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3058 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3059 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3061 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3062 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3068 * Actual coherent framebuffer read implemented using the native render target
3069 * read message. Requires SKL+.
3072 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3074 assert(bld
.shader
->devinfo
->gen
>= 9);
3075 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3076 inst
->target
= target
;
3077 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3083 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3085 if (n
&& regs
[0].file
!= BAD_FILE
) {
3089 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3091 for (unsigned i
= 0; i
< n
; i
++)
3099 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3101 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3102 const brw_wm_prog_key
*const key
=
3103 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3104 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3105 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3107 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3108 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3110 else if (l
== FRAG_RESULT_COLOR
)
3111 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3112 MAX2(key
->nr_color_regions
, 1));
3114 else if (l
== FRAG_RESULT_DEPTH
)
3115 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3117 else if (l
== FRAG_RESULT_STENCIL
)
3118 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3120 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3121 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3123 else if (l
>= FRAG_RESULT_DATA0
&&
3124 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3125 return alloc_temporary(v
->bld
, 4,
3126 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3129 unreachable("Invalid location");
3133 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3134 nir_intrinsic_instr
*instr
)
3136 assert(stage
== MESA_SHADER_FRAGMENT
);
3139 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3140 dest
= get_nir_dest(instr
->dest
);
3142 switch (instr
->intrinsic
) {
3143 case nir_intrinsic_load_front_face
:
3144 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3145 *emit_frontfacing_interpolation());
3148 case nir_intrinsic_load_sample_pos
: {
3149 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3150 assert(sample_pos
.file
!= BAD_FILE
);
3151 dest
.type
= sample_pos
.type
;
3152 bld
.MOV(dest
, sample_pos
);
3153 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3157 case nir_intrinsic_load_layer_id
:
3158 dest
.type
= BRW_REGISTER_TYPE_UD
;
3159 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3162 case nir_intrinsic_load_helper_invocation
:
3163 case nir_intrinsic_load_sample_mask_in
:
3164 case nir_intrinsic_load_sample_id
: {
3165 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3166 fs_reg val
= nir_system_values
[sv
];
3167 assert(val
.file
!= BAD_FILE
);
3168 dest
.type
= val
.type
;
3173 case nir_intrinsic_store_output
: {
3174 const fs_reg src
= get_nir_src(instr
->src
[0]);
3175 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3176 const unsigned location
= nir_intrinsic_base(instr
) +
3177 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3178 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3181 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3182 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3183 offset(src
, bld
, j
));
3188 case nir_intrinsic_load_output
: {
3189 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3190 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3191 assert(l
>= FRAG_RESULT_DATA0
);
3192 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3193 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3194 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3196 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3197 emit_coherent_fb_read(bld
, tmp
, target
);
3199 emit_non_coherent_fb_read(bld
, tmp
, target
);
3201 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3202 bld
.MOV(offset(dest
, bld
, j
),
3203 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3209 case nir_intrinsic_discard
:
3210 case nir_intrinsic_discard_if
: {
3211 /* We track our discarded pixels in f0.1. By predicating on it, we can
3212 * update just the flag bits that aren't yet discarded. If there's no
3213 * condition, we emit a CMP of g0 != g0, so all currently executing
3214 * channels will get turned off.
3217 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3218 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3219 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3221 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3222 BRW_REGISTER_TYPE_UW
));
3223 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3225 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3226 cmp
->flag_subreg
= 1;
3228 if (devinfo
->gen
>= 6) {
3229 emit_discard_jump();
3232 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3236 case nir_intrinsic_load_input
: {
3237 /* load_input is only used for flat inputs */
3238 unsigned base
= nir_intrinsic_base(instr
);
3239 unsigned comp
= nir_intrinsic_component(instr
);
3240 unsigned num_components
= instr
->num_components
;
3241 fs_reg orig_dest
= dest
;
3242 enum brw_reg_type type
= dest
.type
;
3244 /* Special case fields in the VUE header */
3245 if (base
== VARYING_SLOT_LAYER
)
3247 else if (base
== VARYING_SLOT_VIEWPORT
)
3250 if (nir_dest_bit_size(instr
->dest
) == 64) {
3251 /* const_index is in 32-bit type size units that could not be aligned
3252 * with DF. We need to read the double vector as if it was a float
3253 * vector of twice the number of components to fetch the right data.
3255 type
= BRW_REGISTER_TYPE_F
;
3256 num_components
*= 2;
3257 dest
= bld
.vgrf(type
, num_components
);
3260 for (unsigned int i
= 0; i
< num_components
; i
++) {
3261 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3262 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3265 if (nir_dest_bit_size(instr
->dest
) == 64) {
3266 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3267 instr
->num_components
);
3272 case nir_intrinsic_load_barycentric_pixel
:
3273 case nir_intrinsic_load_barycentric_centroid
:
3274 case nir_intrinsic_load_barycentric_sample
:
3275 /* Do nothing - load_interpolated_input handling will handle it later. */
3278 case nir_intrinsic_load_barycentric_at_sample
: {
3279 const glsl_interp_mode interpolation
=
3280 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3282 if (nir_src_is_const(instr
->src
[0])) {
3283 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3285 emit_pixel_interpolater_send(bld
,
3286 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3289 brw_imm_ud(msg_data
),
3292 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3293 BRW_REGISTER_TYPE_UD
);
3295 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3296 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3297 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3298 bld
.exec_all().group(1, 0)
3299 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3300 emit_pixel_interpolater_send(bld
,
3301 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3307 /* Make a loop that sends a message to the pixel interpolater
3308 * for the sample number in each live channel. If there are
3309 * multiple channels with the same sample number then these
3310 * will be handled simultaneously with a single interation of
3313 bld
.emit(BRW_OPCODE_DO
);
3315 /* Get the next live sample number into sample_id_reg */
3316 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3318 /* Set the flag register so that we can perform the send
3319 * message on all channels that have the same sample number
3321 bld
.CMP(bld
.null_reg_ud(),
3322 sample_src
, sample_id
,
3323 BRW_CONDITIONAL_EQ
);
3324 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3325 bld
.exec_all().group(1, 0)
3326 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3328 emit_pixel_interpolater_send(bld
,
3329 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3332 component(msg_data
, 0),
3334 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3336 /* Continue the loop if there are any live channels left */
3337 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3339 bld
.emit(BRW_OPCODE_WHILE
));
3345 case nir_intrinsic_load_barycentric_at_offset
: {
3346 const glsl_interp_mode interpolation
=
3347 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3349 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3352 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3353 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3354 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3356 emit_pixel_interpolater_send(bld
,
3357 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3360 brw_imm_ud(off_x
| (off_y
<< 4)),
3363 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3364 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3365 BRW_REGISTER_TYPE_F
);
3366 for (int i
= 0; i
< 2; i
++) {
3367 fs_reg temp
= vgrf(glsl_type::float_type
);
3368 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3369 fs_reg itemp
= vgrf(glsl_type::int_type
);
3371 bld
.MOV(itemp
, temp
);
3373 /* Clamp the upper end of the range to +7/16.
3374 * ARB_gpu_shader5 requires that we support a maximum offset
3375 * of +0.5, which isn't representable in a S0.4 value -- if
3376 * we didn't clamp it, we'd end up with -8/16, which is the
3377 * opposite of what the shader author wanted.
3379 * This is legal due to ARB_gpu_shader5's quantization
3382 * "Not all values of <offset> may be supported; x and y
3383 * offsets may be rounded to fixed-point values with the
3384 * number of fraction bits given by the
3385 * implementation-dependent constant
3386 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3388 set_condmod(BRW_CONDITIONAL_L
,
3389 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3392 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3393 emit_pixel_interpolater_send(bld
,
3403 case nir_intrinsic_load_interpolated_input
: {
3404 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3405 emit_fragcoord_interpolation(dest
);
3409 assert(instr
->src
[0].ssa
&&
3410 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3411 nir_intrinsic_instr
*bary_intrinsic
=
3412 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3413 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3414 enum glsl_interp_mode interp_mode
=
3415 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3418 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3419 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3420 /* Use the result of the PI message */
3421 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3423 /* Use the delta_xy values computed from the payload */
3424 enum brw_barycentric_mode bary
=
3425 brw_barycentric_mode(interp_mode
, bary_intrin
);
3427 dst_xy
= this->delta_xy
[bary
];
3430 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3432 component(interp_reg(nir_intrinsic_base(instr
),
3433 nir_intrinsic_component(instr
) + i
), 0);
3434 interp
.type
= BRW_REGISTER_TYPE_F
;
3435 dest
.type
= BRW_REGISTER_TYPE_F
;
3437 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3438 fs_reg tmp
= vgrf(glsl_type::float_type
);
3439 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3440 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3442 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3449 nir_emit_intrinsic(bld
, instr
);
3455 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3457 if (nir_src_is_const(instr
->src
[src
])) {
3458 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3461 else if (add_val
== -1)
3469 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3470 nir_intrinsic_instr
*instr
)
3472 assert(stage
== MESA_SHADER_COMPUTE
);
3473 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3476 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3477 dest
= get_nir_dest(instr
->dest
);
3479 switch (instr
->intrinsic
) {
3480 case nir_intrinsic_barrier
:
3482 cs_prog_data
->uses_barrier
= true;
3485 case nir_intrinsic_load_subgroup_id
:
3486 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3489 case nir_intrinsic_load_local_invocation_id
:
3490 case nir_intrinsic_load_work_group_id
: {
3491 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3492 fs_reg val
= nir_system_values
[sv
];
3493 assert(val
.file
!= BAD_FILE
);
3494 dest
.type
= val
.type
;
3495 for (unsigned i
= 0; i
< 3; i
++)
3496 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3500 case nir_intrinsic_load_num_work_groups
: {
3501 const unsigned surface
=
3502 cs_prog_data
->binding_table
.work_groups_start
;
3504 cs_prog_data
->uses_num_work_groups
= true;
3506 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3507 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3508 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3509 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3511 /* Read the 3 GLuint components of gl_NumWorkGroups */
3512 for (unsigned i
= 0; i
< 3; i
++) {
3513 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3514 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3515 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3520 case nir_intrinsic_shared_atomic_add
:
3521 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3523 case nir_intrinsic_shared_atomic_imin
:
3524 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3526 case nir_intrinsic_shared_atomic_umin
:
3527 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3529 case nir_intrinsic_shared_atomic_imax
:
3530 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3532 case nir_intrinsic_shared_atomic_umax
:
3533 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3535 case nir_intrinsic_shared_atomic_and
:
3536 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3538 case nir_intrinsic_shared_atomic_or
:
3539 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3541 case nir_intrinsic_shared_atomic_xor
:
3542 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3544 case nir_intrinsic_shared_atomic_exchange
:
3545 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3547 case nir_intrinsic_shared_atomic_comp_swap
:
3548 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3550 case nir_intrinsic_shared_atomic_fmin
:
3551 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3553 case nir_intrinsic_shared_atomic_fmax
:
3554 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3556 case nir_intrinsic_shared_atomic_fcomp_swap
:
3557 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3560 case nir_intrinsic_load_shared
: {
3561 assert(devinfo
->gen
>= 7);
3562 assert(stage
== MESA_SHADER_COMPUTE
);
3564 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3565 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3566 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3567 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3568 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3570 /* Make dest unsigned because that's what the temporary will be */
3571 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3573 /* Read the vector */
3574 if (nir_intrinsic_align(instr
) >= 4) {
3575 assert(nir_dest_bit_size(instr
->dest
) == 32);
3576 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3578 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3579 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3580 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3582 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3583 assert(nir_dest_num_components(instr
->dest
) == 1);
3584 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3586 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3587 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3588 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3589 bld
.MOV(dest
, read_result
);
3594 case nir_intrinsic_store_shared
: {
3595 assert(devinfo
->gen
>= 7);
3596 assert(stage
== MESA_SHADER_COMPUTE
);
3598 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3599 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3600 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3601 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3602 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3604 fs_reg data
= get_nir_src(instr
->src
[0]);
3605 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3607 assert(nir_intrinsic_write_mask(instr
) ==
3608 (1u << instr
->num_components
) - 1);
3609 if (nir_intrinsic_align(instr
) >= 4) {
3610 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3611 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3612 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3613 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3614 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3615 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3617 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3618 assert(nir_src_num_components(instr
->src
[0]) == 1);
3619 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3621 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3622 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3624 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3625 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3631 nir_emit_intrinsic(bld
, instr
);
3637 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3638 nir_op op
, brw_reg_type type
)
3640 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3641 switch (type_sz(type
)) {
3643 assert(type
!= BRW_REGISTER_TYPE_HF
);
3644 return retype(brw_imm_uw(value
.u16
[0]), type
);
3646 return retype(brw_imm_ud(value
.u32
[0]), type
);
3648 if (type
== BRW_REGISTER_TYPE_DF
)
3649 return setup_imm_df(bld
, value
.f64
[0]);
3651 return retype(brw_imm_u64(value
.u64
[0]), type
);
3653 unreachable("Invalid type size");
3658 brw_op_for_nir_reduction_op(nir_op op
)
3661 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3662 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3663 case nir_op_imul
: return BRW_OPCODE_MUL
;
3664 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3665 case nir_op_imin
: return BRW_OPCODE_SEL
;
3666 case nir_op_umin
: return BRW_OPCODE_SEL
;
3667 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3668 case nir_op_imax
: return BRW_OPCODE_SEL
;
3669 case nir_op_umax
: return BRW_OPCODE_SEL
;
3670 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3671 case nir_op_iand
: return BRW_OPCODE_AND
;
3672 case nir_op_ior
: return BRW_OPCODE_OR
;
3673 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3675 unreachable("Invalid reduction operation");
3679 static brw_conditional_mod
3680 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3683 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3684 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3685 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3686 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3687 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3688 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3689 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3690 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3691 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3692 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3693 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3694 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3695 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3697 unreachable("Invalid reduction operation");
3702 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3703 nir_intrinsic_instr
*instr
)
3705 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3707 if (stage_prog_data
->binding_table
.image_start
> 0) {
3708 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3709 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3711 bld
.ADD(image
, image
,
3712 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3716 return bld
.emit_uniformize(image
);
3720 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3721 nir_intrinsic_instr
*instr
)
3723 /* SSBO stores are weird in that their index is in src[1] */
3724 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3727 if (nir_src_is_const(instr
->src
[src
])) {
3728 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3729 nir_src_as_uint(instr
->src
[src
]);
3730 surf_index
= brw_imm_ud(index
);
3732 surf_index
= vgrf(glsl_type::uint_type
);
3733 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3734 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3737 return bld
.emit_uniformize(surf_index
);
3741 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3743 switch (nir_intrinsic_image_dim(instr
)) {
3744 case GLSL_SAMPLER_DIM_1D
:
3745 return 1 + nir_intrinsic_image_array(instr
);
3746 case GLSL_SAMPLER_DIM_2D
:
3747 case GLSL_SAMPLER_DIM_RECT
:
3748 return 2 + nir_intrinsic_image_array(instr
);
3749 case GLSL_SAMPLER_DIM_3D
:
3750 case GLSL_SAMPLER_DIM_CUBE
:
3752 case GLSL_SAMPLER_DIM_BUF
:
3754 case GLSL_SAMPLER_DIM_MS
:
3755 return 2 + nir_intrinsic_image_array(instr
);
3757 unreachable("Invalid image dimension");
3762 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3765 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3766 dest
= get_nir_dest(instr
->dest
);
3768 switch (instr
->intrinsic
) {
3769 case nir_intrinsic_image_load
:
3770 case nir_intrinsic_image_store
:
3771 case nir_intrinsic_image_atomic_add
:
3772 case nir_intrinsic_image_atomic_min
:
3773 case nir_intrinsic_image_atomic_max
:
3774 case nir_intrinsic_image_atomic_and
:
3775 case nir_intrinsic_image_atomic_or
:
3776 case nir_intrinsic_image_atomic_xor
:
3777 case nir_intrinsic_image_atomic_exchange
:
3778 case nir_intrinsic_image_atomic_comp_swap
: {
3779 if (stage
== MESA_SHADER_FRAGMENT
&&
3780 instr
->intrinsic
!= nir_intrinsic_image_load
)
3781 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3783 /* Get some metadata from the image intrinsic. */
3784 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3785 const GLenum format
= nir_intrinsic_format(instr
);
3787 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3788 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3789 get_nir_image_intrinsic_image(bld
, instr
);
3790 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3791 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
3792 brw_imm_ud(image_intrinsic_coord_components(instr
));
3794 /* Emit an image load, store or atomic op. */
3795 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3796 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3798 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
3799 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3800 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3801 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3802 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3803 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
3804 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
3805 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3808 unsigned num_srcs
= info
->num_srcs
;
3810 switch (instr
->intrinsic
) {
3811 case nir_intrinsic_image_atomic_add
:
3812 assert(num_srcs
== 4);
3814 op
= get_op_for_atomic_add(instr
, 3);
3816 if (op
!= BRW_AOP_ADD
)
3819 case nir_intrinsic_image_atomic_min
:
3820 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3821 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3823 case nir_intrinsic_image_atomic_max
:
3824 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3825 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3827 case nir_intrinsic_image_atomic_and
:
3830 case nir_intrinsic_image_atomic_or
:
3833 case nir_intrinsic_image_atomic_xor
:
3836 case nir_intrinsic_image_atomic_exchange
:
3839 case nir_intrinsic_image_atomic_comp_swap
:
3843 unreachable("Not reachable.");
3846 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
3850 data
= get_nir_src(instr
->src
[3]);
3851 if (num_srcs
>= 5) {
3852 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
3853 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
3854 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
3857 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3859 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
3860 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3865 case nir_intrinsic_image_size
: {
3866 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3867 * into will handle the binding table index for us in the geneerator.
3869 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3870 BRW_REGISTER_TYPE_UD
);
3871 image
= bld
.emit_uniformize(image
);
3873 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3874 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
3875 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
3876 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
3877 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
3879 /* Since the image size is always uniform, we can just emit a SIMD8
3880 * query instruction and splat the result out.
3882 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3884 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3885 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
3886 tmp
, srcs
, ARRAY_SIZE(srcs
));
3887 inst
->size_written
= 4 * REG_SIZE
;
3889 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3890 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3891 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3892 offset(retype(dest
, tmp
.type
), bld
, c
),
3893 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3895 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3896 component(offset(tmp
, ubld
, c
), 0));
3902 case nir_intrinsic_image_load_raw_intel
: {
3903 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3904 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3905 get_nir_image_intrinsic_image(bld
, instr
);
3906 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3907 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3908 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3911 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3912 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3913 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3917 case nir_intrinsic_image_store_raw_intel
: {
3918 if (stage
== MESA_SHADER_FRAGMENT
)
3919 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3921 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3922 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3923 get_nir_image_intrinsic_image(bld
, instr
);
3924 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3925 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
3926 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3927 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3929 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3930 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3934 case nir_intrinsic_group_memory_barrier
:
3935 case nir_intrinsic_memory_barrier_shared
:
3936 case nir_intrinsic_memory_barrier_atomic_counter
:
3937 case nir_intrinsic_memory_barrier_buffer
:
3938 case nir_intrinsic_memory_barrier_image
:
3939 case nir_intrinsic_memory_barrier
: {
3940 const fs_builder ubld
= bld
.group(8, 0);
3941 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3942 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3943 ->size_written
= 2 * REG_SIZE
;
3947 case nir_intrinsic_shader_clock
: {
3948 /* We cannot do anything if there is an event, so ignore it for now */
3949 const fs_reg shader_clock
= get_timestamp(bld
);
3950 const fs_reg srcs
[] = { component(shader_clock
, 0),
3951 component(shader_clock
, 1) };
3952 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3956 case nir_intrinsic_image_samples
:
3957 /* The driver does not support multi-sampled images. */
3958 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3961 case nir_intrinsic_load_uniform
: {
3962 /* Offsets are in bytes but they should always aligned to
3965 assert(instr
->const_index
[0] % 4 == 0 ||
3966 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
3968 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3970 if (nir_src_is_const(instr
->src
[0])) {
3971 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3972 assert(load_offset
% type_sz(dest
.type
) == 0);
3973 /* For 16-bit types we add the module of the const_index[0]
3974 * offset to access to not 32-bit aligned element
3976 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
3978 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3979 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3982 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3983 BRW_REGISTER_TYPE_UD
);
3985 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3986 * go past the end of the uniform. In order to keep the n'th
3987 * component from running past, we subtract off the size of all but
3988 * one component of the vector.
3990 assert(instr
->const_index
[1] >=
3991 instr
->num_components
* (int) type_sz(dest
.type
));
3992 unsigned read_size
= instr
->const_index
[1] -
3993 (instr
->num_components
- 1) * type_sz(dest
.type
);
3995 bool supports_64bit_indirects
=
3996 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3998 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3999 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4000 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4001 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4002 indirect
, brw_imm_ud(read_size
));
4005 const unsigned num_mov_indirects
=
4006 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4007 /* We read a little bit less per MOV INDIRECT, as they are now
4008 * 32-bits ones instead of 64-bit. Fix read_size then.
4010 const unsigned read_size_32bit
= read_size
-
4011 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4012 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4013 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4014 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4015 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4016 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4017 indirect
, brw_imm_ud(read_size_32bit
));
4025 case nir_intrinsic_load_ubo
: {
4027 if (nir_src_is_const(instr
->src
[0])) {
4028 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4029 nir_src_as_uint(instr
->src
[0]);
4030 surf_index
= brw_imm_ud(index
);
4032 /* The block index is not a constant. Evaluate the index expression
4033 * per-channel and add the base UBO index; we have to select a value
4034 * from any live channel.
4036 surf_index
= vgrf(glsl_type::uint_type
);
4037 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4038 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4039 surf_index
= bld
.emit_uniformize(surf_index
);
4042 if (!nir_src_is_const(instr
->src
[1])) {
4043 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4044 BRW_REGISTER_TYPE_UD
);
4046 for (int i
= 0; i
< instr
->num_components
; i
++)
4047 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4048 base_offset
, i
* type_sz(dest
.type
));
4050 /* Even if we are loading doubles, a pull constant load will load
4051 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4052 * need to load a full dvec4 we will have to emit 2 loads. This is
4053 * similar to demote_pull_constants(), except that in that case we
4054 * see individual accesses to each component of the vector and then
4055 * we let CSE deal with duplicate loads. Here we see a vector access
4056 * and we have to split it if necessary.
4058 const unsigned type_size
= type_sz(dest
.type
);
4059 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4061 /* See if we've selected this as a push constant candidate */
4062 if (nir_src_is_const(instr
->src
[0])) {
4063 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4064 const unsigned offset_256b
= load_offset
/ 32;
4067 for (int i
= 0; i
< 4; i
++) {
4068 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4069 if (range
->block
== ubo_block
&&
4070 offset_256b
>= range
->start
&&
4071 offset_256b
< range
->start
+ range
->length
) {
4073 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4074 push_reg
.offset
= load_offset
- 32 * range
->start
;
4079 if (push_reg
.file
!= BAD_FILE
) {
4080 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4081 bld
.MOV(offset(dest
, bld
, i
),
4082 byte_offset(push_reg
, i
* type_size
));
4088 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4089 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4090 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4092 for (unsigned c
= 0; c
< instr
->num_components
;) {
4093 const unsigned base
= load_offset
+ c
* type_size
;
4094 /* Number of usable components in the next block-aligned load. */
4095 const unsigned count
= MIN2(instr
->num_components
- c
,
4096 (block_sz
- base
% block_sz
) / type_size
);
4098 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4099 packed_consts
, surf_index
,
4100 brw_imm_ud(base
& ~(block_sz
- 1)));
4102 const fs_reg consts
=
4103 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4106 for (unsigned d
= 0; d
< count
; d
++)
4107 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4115 case nir_intrinsic_load_global
: {
4116 assert(devinfo
->gen
>= 8);
4118 if (nir_intrinsic_align(instr
) >= 4) {
4119 assert(nir_dest_bit_size(instr
->dest
) == 32);
4120 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4122 get_nir_src(instr
->src
[0]), /* Address */
4123 fs_reg(), /* No source data */
4124 brw_imm_ud(instr
->num_components
));
4125 inst
->size_written
= instr
->num_components
*
4126 inst
->dst
.component_size(inst
->exec_size
);
4128 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4129 assert(bit_size
<= 32);
4130 assert(nir_dest_num_components(instr
->dest
) == 1);
4131 brw_reg_type data_type
=
4132 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4133 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4134 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4136 get_nir_src(instr
->src
[0]), /* Address */
4137 fs_reg(), /* No source data */
4138 brw_imm_ud(bit_size
));
4139 bld
.MOV(retype(dest
, data_type
), tmp
);
4144 case nir_intrinsic_store_global
:
4145 assert(devinfo
->gen
>= 8);
4147 if (stage
== MESA_SHADER_FRAGMENT
)
4148 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4150 if (nir_intrinsic_align(instr
) >= 4) {
4151 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4152 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4154 get_nir_src(instr
->src
[1]), /* Address */
4155 get_nir_src(instr
->src
[0]), /* Data */
4156 brw_imm_ud(instr
->num_components
));
4158 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4159 assert(bit_size
<= 32);
4160 assert(nir_src_num_components(instr
->src
[0]) == 1);
4161 brw_reg_type data_type
=
4162 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4163 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4164 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4165 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4167 get_nir_src(instr
->src
[1]), /* Address */
4169 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4173 case nir_intrinsic_global_atomic_add
:
4174 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4176 case nir_intrinsic_global_atomic_imin
:
4177 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4179 case nir_intrinsic_global_atomic_umin
:
4180 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4182 case nir_intrinsic_global_atomic_imax
:
4183 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4185 case nir_intrinsic_global_atomic_umax
:
4186 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4188 case nir_intrinsic_global_atomic_and
:
4189 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4191 case nir_intrinsic_global_atomic_or
:
4192 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4194 case nir_intrinsic_global_atomic_xor
:
4195 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4197 case nir_intrinsic_global_atomic_exchange
:
4198 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4200 case nir_intrinsic_global_atomic_comp_swap
:
4201 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4203 case nir_intrinsic_global_atomic_fmin
:
4204 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4206 case nir_intrinsic_global_atomic_fmax
:
4207 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4209 case nir_intrinsic_global_atomic_fcomp_swap
:
4210 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4213 case nir_intrinsic_load_ssbo
: {
4214 assert(devinfo
->gen
>= 7);
4216 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4217 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4218 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4219 get_nir_ssbo_intrinsic_index(bld
, instr
);
4220 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4221 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4223 /* Make dest unsigned because that's what the temporary will be */
4224 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4226 /* Read the vector */
4227 if (nir_intrinsic_align(instr
) >= 4) {
4228 assert(nir_dest_bit_size(instr
->dest
) == 32);
4229 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4231 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4232 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4233 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4235 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4236 assert(nir_dest_num_components(instr
->dest
) == 1);
4237 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4239 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4240 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4241 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4242 bld
.MOV(dest
, read_result
);
4247 case nir_intrinsic_store_ssbo
: {
4248 assert(devinfo
->gen
>= 7);
4250 if (stage
== MESA_SHADER_FRAGMENT
)
4251 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4253 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4254 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4255 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4256 get_nir_ssbo_intrinsic_index(bld
, instr
);
4257 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4258 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4260 fs_reg data
= get_nir_src(instr
->src
[0]);
4261 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4263 assert(nir_intrinsic_write_mask(instr
) ==
4264 (1u << instr
->num_components
) - 1);
4265 if (nir_intrinsic_align(instr
) >= 4) {
4266 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4267 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4268 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4269 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4270 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4271 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4273 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4274 assert(nir_src_num_components(instr
->src
[0]) == 1);
4275 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4277 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4278 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4280 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4281 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4286 case nir_intrinsic_store_output
: {
4287 fs_reg src
= get_nir_src(instr
->src
[0]);
4289 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4290 unsigned num_components
= instr
->num_components
;
4291 unsigned first_component
= nir_intrinsic_component(instr
);
4292 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4293 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4294 num_components
*= 2;
4297 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4298 4 * store_offset
), src
.type
);
4299 for (unsigned j
= 0; j
< num_components
; j
++) {
4300 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4301 offset(src
, bld
, j
));
4306 case nir_intrinsic_ssbo_atomic_add
:
4307 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4309 case nir_intrinsic_ssbo_atomic_imin
:
4310 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4312 case nir_intrinsic_ssbo_atomic_umin
:
4313 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4315 case nir_intrinsic_ssbo_atomic_imax
:
4316 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4318 case nir_intrinsic_ssbo_atomic_umax
:
4319 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4321 case nir_intrinsic_ssbo_atomic_and
:
4322 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4324 case nir_intrinsic_ssbo_atomic_or
:
4325 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4327 case nir_intrinsic_ssbo_atomic_xor
:
4328 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4330 case nir_intrinsic_ssbo_atomic_exchange
:
4331 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4333 case nir_intrinsic_ssbo_atomic_comp_swap
:
4334 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4336 case nir_intrinsic_ssbo_atomic_fmin
:
4337 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4339 case nir_intrinsic_ssbo_atomic_fmax
:
4340 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4342 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4343 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4346 case nir_intrinsic_get_buffer_size
: {
4347 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4348 nir_src_as_uint(instr
->src
[0]) : 0;
4350 /* A resinfo's sampler message is used to get the buffer size. The
4351 * SIMD8's writeback message consists of four registers and SIMD16's
4352 * writeback message consists of 8 destination registers (two per each
4353 * component). Because we are only interested on the first channel of
4354 * the first returned component, where resinfo returns the buffer size
4355 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4356 * the dispatch width.
4358 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4359 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4360 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4363 ubld
.MOV(src_payload
, brw_imm_d(0));
4365 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4366 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4367 src_payload
, brw_imm_ud(index
));
4368 inst
->header_size
= 0;
4370 inst
->size_written
= 4 * REG_SIZE
;
4372 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4374 * "Out-of-bounds checking is always performed at a DWord granularity. If
4375 * any part of the DWord is out-of-bounds then the whole DWord is
4376 * considered out-of-bounds."
4378 * This implies that types with size smaller than 4-bytes need to be
4379 * padded if they don't complete the last dword of the buffer. But as we
4380 * need to maintain the original size we need to reverse the padding
4381 * calculation to return the correct size to know the number of elements
4382 * of an unsized array. As we stored in the last two bits of the surface
4383 * size the needed padding for the buffer, we calculate here the
4384 * original buffer_size reversing the surface_size calculation:
4386 * surface_size = isl_align(buffer_size, 4) +
4387 * (isl_align(buffer_size) - buffer_size)
4389 * buffer_size = surface_size & ~3 - surface_size & 3
4392 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4393 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4394 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4396 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4397 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4398 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4400 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4404 case nir_intrinsic_load_subgroup_invocation
:
4405 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4406 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4409 case nir_intrinsic_load_subgroup_eq_mask
:
4410 case nir_intrinsic_load_subgroup_ge_mask
:
4411 case nir_intrinsic_load_subgroup_gt_mask
:
4412 case nir_intrinsic_load_subgroup_le_mask
:
4413 case nir_intrinsic_load_subgroup_lt_mask
:
4414 unreachable("not reached");
4416 case nir_intrinsic_vote_any
: {
4417 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4419 /* The any/all predicates do not consider channel enables. To prevent
4420 * dead channels from affecting the result, we initialize the flag with
4421 * with the identity value for the logical operation.
4423 if (dispatch_width
== 32) {
4424 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4425 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4428 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4430 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4432 /* For some reason, the any/all predicates don't work properly with
4433 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4434 * doesn't read the correct subset of the flag register and you end up
4435 * getting garbage in the second half. Work around this by using a pair
4436 * of 1-wide MOVs and scattering the result.
4438 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4439 ubld
.MOV(res1
, brw_imm_d(0));
4440 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4441 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4442 BRW_PREDICATE_ALIGN1_ANY32H
,
4443 ubld
.MOV(res1
, brw_imm_d(-1)));
4445 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4448 case nir_intrinsic_vote_all
: {
4449 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4451 /* The any/all predicates do not consider channel enables. To prevent
4452 * dead channels from affecting the result, we initialize the flag with
4453 * with the identity value for the logical operation.
4455 if (dispatch_width
== 32) {
4456 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4457 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4458 brw_imm_ud(0xffffffff));
4460 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4462 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4464 /* For some reason, the any/all predicates don't work properly with
4465 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4466 * doesn't read the correct subset of the flag register and you end up
4467 * getting garbage in the second half. Work around this by using a pair
4468 * of 1-wide MOVs and scattering the result.
4470 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4471 ubld
.MOV(res1
, brw_imm_d(0));
4472 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4473 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4474 BRW_PREDICATE_ALIGN1_ALL32H
,
4475 ubld
.MOV(res1
, brw_imm_d(-1)));
4477 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4480 case nir_intrinsic_vote_feq
:
4481 case nir_intrinsic_vote_ieq
: {
4482 fs_reg value
= get_nir_src(instr
->src
[0]);
4483 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4484 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4485 value
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4488 fs_reg uniformized
= bld
.emit_uniformize(value
);
4489 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4491 /* The any/all predicates do not consider channel enables. To prevent
4492 * dead channels from affecting the result, we initialize the flag with
4493 * with the identity value for the logical operation.
4495 if (dispatch_width
== 32) {
4496 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4497 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4498 brw_imm_ud(0xffffffff));
4500 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4502 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4504 /* For some reason, the any/all predicates don't work properly with
4505 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4506 * doesn't read the correct subset of the flag register and you end up
4507 * getting garbage in the second half. Work around this by using a pair
4508 * of 1-wide MOVs and scattering the result.
4510 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4511 ubld
.MOV(res1
, brw_imm_d(0));
4512 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4513 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4514 BRW_PREDICATE_ALIGN1_ALL32H
,
4515 ubld
.MOV(res1
, brw_imm_d(-1)));
4517 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4521 case nir_intrinsic_ballot
: {
4522 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4523 BRW_REGISTER_TYPE_UD
);
4524 struct brw_reg flag
= brw_flag_reg(0, 0);
4525 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4526 * as f0.0. This is a problem for fragment programs as we currently use
4527 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4528 * programs yet so this isn't a problem. When we do, something will
4531 if (dispatch_width
== 32)
4532 flag
.type
= BRW_REGISTER_TYPE_UD
;
4534 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4535 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4537 if (instr
->dest
.ssa
.bit_size
> 32) {
4538 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4540 dest
.type
= BRW_REGISTER_TYPE_UD
;
4542 bld
.MOV(dest
, flag
);
4546 case nir_intrinsic_read_invocation
: {
4547 const fs_reg value
= get_nir_src(instr
->src
[0]);
4548 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4549 fs_reg tmp
= bld
.vgrf(value
.type
);
4551 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4552 bld
.emit_uniformize(invocation
));
4554 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4558 case nir_intrinsic_read_first_invocation
: {
4559 const fs_reg value
= get_nir_src(instr
->src
[0]);
4560 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4564 case nir_intrinsic_shuffle
: {
4565 const fs_reg value
= get_nir_src(instr
->src
[0]);
4566 const fs_reg index
= get_nir_src(instr
->src
[1]);
4568 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4572 case nir_intrinsic_first_invocation
: {
4573 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4574 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4575 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4576 fs_reg(component(tmp
, 0)));
4580 case nir_intrinsic_quad_broadcast
: {
4581 const fs_reg value
= get_nir_src(instr
->src
[0]);
4582 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4584 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4585 value
, brw_imm_ud(index
), brw_imm_ud(4));
4589 case nir_intrinsic_quad_swap_horizontal
: {
4590 const fs_reg value
= get_nir_src(instr
->src
[0]);
4591 const fs_reg tmp
= bld
.vgrf(value
.type
);
4592 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4594 const fs_reg src_left
= horiz_stride(value
, 2);
4595 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4596 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4597 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4599 ubld
.MOV(tmp_left
, src_right
);
4600 ubld
.MOV(tmp_right
, src_left
);
4602 bld
.MOV(retype(dest
, value
.type
), tmp
);
4606 case nir_intrinsic_quad_swap_vertical
: {
4607 const fs_reg value
= get_nir_src(instr
->src
[0]);
4608 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4609 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4610 const fs_reg tmp
= bld
.vgrf(value
.type
);
4611 const fs_builder ubld
= bld
.exec_all();
4612 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4613 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4614 bld
.MOV(retype(dest
, value
.type
), tmp
);
4616 /* For larger data types, we have to either emit dispatch_width many
4617 * MOVs or else fall back to doing indirects.
4619 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4620 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4622 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4627 case nir_intrinsic_quad_swap_diagonal
: {
4628 const fs_reg value
= get_nir_src(instr
->src
[0]);
4629 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4630 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4631 const fs_reg tmp
= bld
.vgrf(value
.type
);
4632 const fs_builder ubld
= bld
.exec_all();
4633 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4634 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4635 bld
.MOV(retype(dest
, value
.type
), tmp
);
4637 /* For larger data types, we have to either emit dispatch_width many
4638 * MOVs or else fall back to doing indirects.
4640 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4641 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4643 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4648 case nir_intrinsic_reduce
: {
4649 fs_reg src
= get_nir_src(instr
->src
[0]);
4650 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4651 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4652 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4653 cluster_size
= dispatch_width
;
4655 /* Figure out the source type */
4656 src
.type
= brw_type_for_nir_type(devinfo
,
4657 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4658 nir_src_bit_size(instr
->src
[0])));
4660 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4661 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4662 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4664 /* Set up a register for all of our scratching around and initialize it
4665 * to reduction operation's identity value.
4667 fs_reg scan
= bld
.vgrf(src
.type
);
4668 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4670 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4672 dest
.type
= src
.type
;
4673 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4674 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4675 * the distance between clusters is at least 2 GRFs. In this case,
4676 * we don't need the weird striding of the CLUSTER_BROADCAST
4677 * instruction and can just do regular MOVs.
4679 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4680 const unsigned groups
=
4681 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4682 const unsigned group_size
= dispatch_width
/ groups
;
4683 for (unsigned i
= 0; i
< groups
; i
++) {
4684 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4685 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4686 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4687 component(scan
, comp
));
4690 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4691 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4696 case nir_intrinsic_inclusive_scan
:
4697 case nir_intrinsic_exclusive_scan
: {
4698 fs_reg src
= get_nir_src(instr
->src
[0]);
4699 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4701 /* Figure out the source type */
4702 src
.type
= brw_type_for_nir_type(devinfo
,
4703 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4704 nir_src_bit_size(instr
->src
[0])));
4706 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4707 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4708 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4710 /* Set up a register for all of our scratching around and initialize it
4711 * to reduction operation's identity value.
4713 fs_reg scan
= bld
.vgrf(src
.type
);
4714 const fs_builder allbld
= bld
.exec_all();
4715 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4717 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4718 /* Exclusive scan is a bit harder because we have to do an annoying
4719 * shift of the contents before we can begin. To make things worse,
4720 * we can't do this with a normal stride; we have to use indirects.
4722 fs_reg shifted
= bld
.vgrf(src
.type
);
4723 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4724 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4726 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4727 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4731 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4733 bld
.MOV(retype(dest
, src
.type
), scan
);
4737 case nir_intrinsic_begin_invocation_interlock
: {
4738 const fs_builder ubld
= bld
.group(8, 0);
4739 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4741 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4747 case nir_intrinsic_end_invocation_interlock
: {
4748 /* We don't need to do anything here */
4753 unreachable("unknown intrinsic");
4758 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4759 int op
, nir_intrinsic_instr
*instr
)
4761 if (stage
== MESA_SHADER_FRAGMENT
)
4762 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4765 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4766 dest
= get_nir_dest(instr
->dest
);
4768 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4769 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4770 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4771 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4772 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4775 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4776 data
= get_nir_src(instr
->src
[2]);
4778 if (op
== BRW_AOP_CMPWR
) {
4779 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4780 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4781 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4784 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4786 /* Emit the actual atomic operation */
4788 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4789 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4793 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4794 int op
, nir_intrinsic_instr
*instr
)
4796 if (stage
== MESA_SHADER_FRAGMENT
)
4797 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4800 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4801 dest
= get_nir_dest(instr
->dest
);
4803 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4804 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4805 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4806 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4807 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4809 fs_reg data
= get_nir_src(instr
->src
[2]);
4810 if (op
== BRW_AOP_FCMPWR
) {
4811 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4812 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4813 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4816 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4818 /* Emit the actual atomic operation */
4820 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4821 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4825 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4826 int op
, nir_intrinsic_instr
*instr
)
4829 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4830 dest
= get_nir_dest(instr
->dest
);
4832 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4833 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4834 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4835 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4838 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4839 data
= get_nir_src(instr
->src
[1]);
4840 if (op
== BRW_AOP_CMPWR
) {
4841 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4842 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4843 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4846 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4848 /* Get the offset */
4849 if (nir_src_is_const(instr
->src
[0])) {
4850 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4851 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4853 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4854 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4855 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4856 brw_imm_ud(instr
->const_index
[0]));
4859 /* Emit the actual atomic operation operation */
4861 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4862 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4866 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4867 int op
, nir_intrinsic_instr
*instr
)
4870 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4871 dest
= get_nir_dest(instr
->dest
);
4873 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4874 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4875 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4876 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4878 fs_reg data
= get_nir_src(instr
->src
[1]);
4879 if (op
== BRW_AOP_FCMPWR
) {
4880 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4881 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4882 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4885 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4887 /* Get the offset */
4888 if (nir_src_is_const(instr
->src
[0])) {
4889 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4890 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4892 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4893 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4894 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4895 brw_imm_ud(instr
->const_index
[0]));
4898 /* Emit the actual atomic operation operation */
4900 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4901 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4905 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
4906 int op
, nir_intrinsic_instr
*instr
)
4908 if (stage
== MESA_SHADER_FRAGMENT
)
4909 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4912 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4913 dest
= get_nir_dest(instr
->dest
);
4915 fs_reg addr
= get_nir_src(instr
->src
[0]);
4918 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4919 data
= get_nir_src(instr
->src
[1]);
4921 if (op
== BRW_AOP_CMPWR
) {
4922 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4923 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4924 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4928 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4929 dest
, addr
, data
, brw_imm_ud(op
));
4933 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
4934 int op
, nir_intrinsic_instr
*instr
)
4936 if (stage
== MESA_SHADER_FRAGMENT
)
4937 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4939 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
4940 fs_reg dest
= get_nir_dest(instr
->dest
);
4942 fs_reg addr
= get_nir_src(instr
->src
[0]);
4944 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
4945 fs_reg data
= get_nir_src(instr
->src
[1]);
4947 if (op
== BRW_AOP_FCMPWR
) {
4948 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4949 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4950 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4954 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4955 dest
, addr
, data
, brw_imm_ud(op
));
4959 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4961 unsigned texture
= instr
->texture_index
;
4962 unsigned sampler
= instr
->sampler_index
;
4964 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4966 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4967 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4969 int lod_components
= 0;
4971 /* The hardware requires a LOD for buffer textures */
4972 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4973 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4975 uint32_t header_bits
= 0;
4976 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4977 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4978 switch (instr
->src
[i
].src_type
) {
4979 case nir_tex_src_bias
:
4980 srcs
[TEX_LOGICAL_SRC_LOD
] =
4981 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4983 case nir_tex_src_comparator
:
4984 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4986 case nir_tex_src_coord
:
4987 switch (instr
->op
) {
4989 case nir_texop_txf_ms
:
4990 case nir_texop_txf_ms_mcs
:
4991 case nir_texop_samples_identical
:
4992 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4995 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4999 case nir_tex_src_ddx
:
5000 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5001 lod_components
= nir_tex_instr_src_size(instr
, i
);
5003 case nir_tex_src_ddy
:
5004 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5006 case nir_tex_src_lod
:
5007 switch (instr
->op
) {
5009 srcs
[TEX_LOGICAL_SRC_LOD
] =
5010 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5013 srcs
[TEX_LOGICAL_SRC_LOD
] =
5014 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5017 srcs
[TEX_LOGICAL_SRC_LOD
] =
5018 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5022 case nir_tex_src_min_lod
:
5023 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5024 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5026 case nir_tex_src_ms_index
:
5027 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5030 case nir_tex_src_offset
: {
5031 nir_const_value
*const_offset
=
5032 nir_src_as_const_value(instr
->src
[i
].src
);
5033 assert(nir_src_bit_size(instr
->src
[i
].src
) == 32);
5034 unsigned offset_bits
= 0;
5036 brw_texture_offset(const_offset
->i32
,
5037 nir_tex_instr_src_size(instr
, i
),
5039 header_bits
|= offset_bits
;
5041 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5042 retype(src
, BRW_REGISTER_TYPE_D
);
5047 case nir_tex_src_projector
:
5048 unreachable("should be lowered");
5050 case nir_tex_src_texture_offset
: {
5051 /* Emit code to evaluate the actual indexing expression */
5052 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5053 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5054 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5058 case nir_tex_src_sampler_offset
: {
5059 /* Emit code to evaluate the actual indexing expression */
5060 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5061 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5062 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5066 case nir_tex_src_ms_mcs
:
5067 assert(instr
->op
== nir_texop_txf_ms
);
5068 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5071 case nir_tex_src_plane
: {
5072 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5073 const uint32_t texture_index
=
5074 instr
->texture_index
+
5075 stage_prog_data
->binding_table
.plane_start
[plane
] -
5076 stage_prog_data
->binding_table
.texture_start
;
5078 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5083 unreachable("unknown texture source");
5087 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5088 (instr
->op
== nir_texop_txf_ms
||
5089 instr
->op
== nir_texop_samples_identical
)) {
5090 if (devinfo
->gen
>= 7 &&
5091 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5092 srcs
[TEX_LOGICAL_SRC_MCS
] =
5093 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5094 instr
->coord_components
,
5095 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5097 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5101 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5102 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5105 switch (instr
->op
) {
5107 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
5108 SHADER_OPCODE_TXL_LOGICAL
);
5111 opcode
= FS_OPCODE_TXB_LOGICAL
;
5114 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5117 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5120 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5122 case nir_texop_txf_ms
:
5123 if ((key_tex
->msaa_16
& (1 << sampler
)))
5124 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5126 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5128 case nir_texop_txf_ms_mcs
:
5129 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5131 case nir_texop_query_levels
:
5133 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5136 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5139 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5140 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5142 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5144 case nir_texop_texture_samples
:
5145 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5147 case nir_texop_samples_identical
: {
5148 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5150 /* If mcs is an immediate value, it means there is no MCS. In that case
5151 * just return false.
5153 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5154 bld
.MOV(dst
, brw_imm_ud(0u));
5155 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5156 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5157 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5158 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5159 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5161 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5162 BRW_CONDITIONAL_EQ
);
5167 unreachable("unknown texture opcode");
5170 if (instr
->op
== nir_texop_tg4
) {
5171 if (instr
->component
== 1 &&
5172 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5173 /* gather4 sampler is broken for green channel on RG32F --
5174 * we must ask for blue instead.
5176 header_bits
|= 2 << 16;
5178 header_bits
|= instr
->component
<< 16;
5182 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5183 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5184 inst
->offset
= header_bits
;
5186 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5187 if (devinfo
->gen
>= 9 &&
5188 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5189 unsigned write_mask
= instr
->dest
.is_ssa
?
5190 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5191 (1 << dest_size
) - 1;
5192 assert(write_mask
!= 0); /* dead code should have been eliminated */
5193 inst
->size_written
= util_last_bit(write_mask
) *
5194 inst
->dst
.component_size(inst
->exec_size
);
5196 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5199 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5200 inst
->shadow_compare
= true;
5202 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5203 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5206 for (unsigned i
= 0; i
< dest_size
; i
++)
5207 nir_dest
[i
] = offset(dst
, bld
, i
);
5209 if (instr
->op
== nir_texop_query_levels
) {
5210 /* # levels is in .w */
5211 nir_dest
[0] = offset(dst
, bld
, 3);
5212 } else if (instr
->op
== nir_texop_txs
&&
5213 dest_size
>= 3 && devinfo
->gen
< 7) {
5214 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5215 fs_reg depth
= offset(dst
, bld
, 2);
5216 nir_dest
[2] = vgrf(glsl_type::int_type
);
5217 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5220 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5224 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5226 switch (instr
->type
) {
5227 case nir_jump_break
:
5228 bld
.emit(BRW_OPCODE_BREAK
);
5230 case nir_jump_continue
:
5231 bld
.emit(BRW_OPCODE_CONTINUE
);
5233 case nir_jump_return
:
5235 unreachable("unknown jump");
5240 * This helper takes a source register and un/shuffles it into the destination
5243 * If source type size is smaller than destination type size the operation
5244 * needed is a component shuffle. The opposite case would be an unshuffle. If
5245 * source/destination type size is equal a shuffle is done that would be
5246 * equivalent to a simple MOV.
5248 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5249 * components .xyz 16-bit vector on SIMD8 would be.
5251 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5252 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5254 * This helper will return the following 2 32-bit components with the 16-bit
5257 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5258 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5260 * For unshuffle, the example would be the opposite, a 64-bit type source
5261 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5264 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5265 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5266 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5267 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5269 * The returned result would be the following 4 32-bit components unshuffled:
5271 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5272 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5273 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5274 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5276 * - Source and destination register must not be overlapped.
5277 * - components units are measured in terms of the smaller type between
5278 * source and destination because we are un/shuffling the smaller
5279 * components from/into the bigger ones.
5280 * - first_component parameter allows skipping source components.
5283 shuffle_src_to_dst(const fs_builder
&bld
,
5286 uint32_t first_component
,
5287 uint32_t components
)
5289 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5290 assert(!regions_overlap(dst
,
5291 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5292 offset(src
, bld
, first_component
),
5293 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5294 for (unsigned i
= 0; i
< components
; i
++) {
5295 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5296 offset(src
, bld
, i
+ first_component
));
5298 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5299 /* Source is shuffled into destination */
5300 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5301 assert(!regions_overlap(dst
,
5302 type_sz(dst
.type
) * bld
.dispatch_width() *
5303 DIV_ROUND_UP(components
, size_ratio
),
5304 offset(src
, bld
, first_component
),
5305 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5307 brw_reg_type shuffle_type
=
5308 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5309 BRW_REGISTER_TYPE_D
);
5310 for (unsigned i
= 0; i
< components
; i
++) {
5311 fs_reg shuffle_component_i
=
5312 subscript(offset(dst
, bld
, i
/ size_ratio
),
5313 shuffle_type
, i
% size_ratio
);
5314 bld
.MOV(shuffle_component_i
,
5315 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5318 /* Source is unshuffled into destination */
5319 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5320 assert(!regions_overlap(dst
,
5321 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5322 offset(src
, bld
, first_component
/ size_ratio
),
5323 type_sz(src
.type
) * bld
.dispatch_width() *
5324 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5327 brw_reg_type shuffle_type
=
5328 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5329 BRW_REGISTER_TYPE_D
);
5330 for (unsigned i
= 0; i
< components
; i
++) {
5331 fs_reg shuffle_component_i
=
5332 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5333 shuffle_type
, (first_component
+ i
) % size_ratio
);
5334 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5335 shuffle_component_i
);
5341 shuffle_from_32bit_read(const fs_builder
&bld
,
5344 uint32_t first_component
,
5345 uint32_t components
)
5347 assert(type_sz(src
.type
) == 4);
5349 /* This function takes components in units of the destination type while
5350 * shuffle_src_to_dst takes components in units of the smallest type
5352 if (type_sz(dst
.type
) > 4) {
5353 assert(type_sz(dst
.type
) == 8);
5354 first_component
*= 2;
5358 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5362 shuffle_for_32bit_write(const fs_builder
&bld
,
5364 uint32_t first_component
,
5365 uint32_t components
)
5367 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5368 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5369 /* This function takes components in units of the source type while
5370 * shuffle_src_to_dst takes components in units of the smallest type
5372 if (type_sz(src
.type
) > 4) {
5373 assert(type_sz(src
.type
) == 8);
5374 first_component
*= 2;
5378 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5384 setup_imm_df(const fs_builder
&bld
, double v
)
5386 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5387 assert(devinfo
->gen
>= 7);
5389 if (devinfo
->gen
>= 8)
5390 return brw_imm_df(v
);
5392 /* gen7.5 does not support DF immediates straighforward but the DIM
5393 * instruction allows to set the 64-bit immediate value.
5395 if (devinfo
->is_haswell
) {
5396 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5397 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5398 ubld
.DIM(dst
, brw_imm_df(v
));
5399 return component(dst
, 0);
5402 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5403 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5404 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5406 * Alternatively, we could also produce a normal VGRF (without stride 0)
5407 * by writing to all the channels in the VGRF, however, that would hit the
5408 * gen7 bug where we have to split writes that span more than 1 register
5409 * into instructions with a width of 4 (otherwise the write to the second
5410 * register written runs into an execmask hardware bug) which isn't very
5423 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5424 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5425 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5426 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5428 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5432 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5434 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5435 bld
.MOV(tmp
, brw_imm_w(v
));
5440 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5442 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5443 bld
.MOV(tmp
, brw_imm_uw(v
));