2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
30 using namespace brw::surface_access
;
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 /* get the main function and emit it */
43 nir_foreach_function(function
, nir
) {
44 assert(strcmp(function
->name
, "main") == 0);
45 assert(function
->impl
);
46 nir_emit_impl(function
->impl
);
51 fs_visitor::nir_setup_outputs()
53 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
56 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
58 /* Calculate the size of output registers in a separate pass, before
59 * allocating them. With ARB_enhanced_layouts, multiple output variables
60 * may occupy the same slot, but have different type sizes.
62 nir_foreach_variable(var
, &nir
->outputs
) {
63 const int loc
= var
->data
.driver_location
;
64 const unsigned var_vec4s
=
65 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
66 : type_size_vec4(var
->type
);
67 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
70 nir_foreach_variable(var
, &nir
->outputs
) {
71 const int loc
= var
->data
.driver_location
;
72 if (outputs
[loc
].file
== BAD_FILE
) {
73 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
[loc
]);
74 for (unsigned i
= 0; i
< vec4s
[loc
]; i
++) {
75 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
82 fs_visitor::nir_setup_uniforms()
84 /* Only the first compile gets to set up uniforms. */
85 if (push_constant_loc
) {
86 assert(pull_constant_loc
);
90 uniforms
= nir
->num_uniforms
/ 4;
92 if (stage
== MESA_SHADER_COMPUTE
) {
93 /* Add a uniform for the thread local id. It must be the last uniform
96 assert(uniforms
== prog_data
->nr_params
);
97 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
98 *param
= BRW_PARAM_BUILTIN_THREAD_LOCAL_ID
;
99 thread_local_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
104 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
108 nir_foreach_instr(instr
, block
) {
109 if (instr
->type
!= nir_instr_type_intrinsic
)
112 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
113 switch (intrin
->intrinsic
) {
114 case nir_intrinsic_load_vertex_id
:
115 unreachable("should be lowered by lower_vertex_id().");
117 case nir_intrinsic_load_vertex_id_zero_base
:
118 case nir_intrinsic_load_base_vertex
:
119 case nir_intrinsic_load_instance_id
:
120 case nir_intrinsic_load_base_instance
:
121 case nir_intrinsic_load_draw_id
:
122 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
124 case nir_intrinsic_load_invocation_id
:
125 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
127 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
128 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
129 if (reg
->file
== BAD_FILE
) {
130 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
131 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
132 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
133 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
138 case nir_intrinsic_load_sample_pos
:
139 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
140 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
141 if (reg
->file
== BAD_FILE
)
142 *reg
= *v
->emit_samplepos_setup();
145 case nir_intrinsic_load_sample_id
:
146 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
147 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
148 if (reg
->file
== BAD_FILE
)
149 *reg
= *v
->emit_sampleid_setup();
152 case nir_intrinsic_load_sample_mask_in
:
153 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
154 assert(v
->devinfo
->gen
>= 7);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_samplemaskin_setup();
160 case nir_intrinsic_load_work_group_id
:
161 assert(v
->stage
== MESA_SHADER_COMPUTE
);
162 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
163 if (reg
->file
== BAD_FILE
)
164 *reg
= *v
->emit_cs_work_group_id_setup();
167 case nir_intrinsic_load_helper_invocation
:
168 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
169 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
170 if (reg
->file
== BAD_FILE
) {
171 const fs_builder abld
=
172 v
->bld
.annotate("gl_HelperInvocation", NULL
);
174 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
175 * pixel mask is in g1.7 of the thread payload.
177 * We move the per-channel pixel enable bit to the low bit of each
178 * channel by shifting the byte containing the pixel mask by the
179 * vector immediate 0x76543210UV.
181 * The region of <1,8,0> reads only 1 byte (the pixel masks for
182 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
183 * masks for 2 and 3) in SIMD16.
185 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
187 stride(byte_offset(retype(brw_vec1_grf(1, 0),
188 BRW_REGISTER_TYPE_UB
), 28),
190 brw_imm_v(0x76543210));
192 /* A set bit in the pixel mask means the channel is enabled, but
193 * that is the opposite of gl_HelperInvocation so we need to invert
196 * The negate source-modifier bit of logical instructions on Gen8+
197 * performs 1's complement negation, so we can use that instead of
200 fs_reg inverted
= negate(shifted
);
201 if (v
->devinfo
->gen
< 8) {
202 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
203 abld
.NOT(inverted
, shifted
);
206 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
207 * with 1 and negating.
209 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
210 abld
.AND(anded
, inverted
, brw_imm_uw(1));
212 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
213 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
227 fs_visitor::nir_emit_system_values()
229 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
230 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
231 nir_system_values
[i
] = fs_reg();
234 nir_foreach_function(function
, nir
) {
235 assert(strcmp(function
->name
, "main") == 0);
236 assert(function
->impl
);
237 nir_foreach_block(block
, function
->impl
) {
238 emit_system_values_block(block
, this);
244 * Returns a type based on a reference_type (word, float, half-float) and a
247 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
249 * @FIXME: 64-bit return types are always DF on integer types to maintain
250 * compability with uses of DF previously to the introduction of int64
254 brw_reg_type_from_bit_size(const unsigned bit_size
,
255 const brw_reg_type reference_type
)
257 switch(reference_type
) {
258 case BRW_REGISTER_TYPE_HF
:
259 case BRW_REGISTER_TYPE_F
:
260 case BRW_REGISTER_TYPE_DF
:
263 return BRW_REGISTER_TYPE_HF
;
265 return BRW_REGISTER_TYPE_F
;
267 return BRW_REGISTER_TYPE_DF
;
269 unreachable("Invalid bit size");
271 case BRW_REGISTER_TYPE_W
:
272 case BRW_REGISTER_TYPE_D
:
273 case BRW_REGISTER_TYPE_Q
:
276 return BRW_REGISTER_TYPE_W
;
278 return BRW_REGISTER_TYPE_D
;
280 return BRW_REGISTER_TYPE_DF
;
282 unreachable("Invalid bit size");
284 case BRW_REGISTER_TYPE_UW
:
285 case BRW_REGISTER_TYPE_UD
:
286 case BRW_REGISTER_TYPE_UQ
:
289 return BRW_REGISTER_TYPE_UW
;
291 return BRW_REGISTER_TYPE_UD
;
293 return BRW_REGISTER_TYPE_DF
;
295 unreachable("Invalid bit size");
298 unreachable("Unknown type");
303 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
305 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
306 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
307 nir_locals
[i
] = fs_reg();
310 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
311 unsigned array_elems
=
312 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
313 unsigned size
= array_elems
* reg
->num_components
;
314 const brw_reg_type reg_type
=
315 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
316 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
319 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
322 nir_emit_cf_list(&impl
->body
);
326 fs_visitor::nir_emit_cf_list(exec_list
*list
)
328 exec_list_validate(list
);
329 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
330 switch (node
->type
) {
332 nir_emit_if(nir_cf_node_as_if(node
));
335 case nir_cf_node_loop
:
336 nir_emit_loop(nir_cf_node_as_loop(node
));
339 case nir_cf_node_block
:
340 nir_emit_block(nir_cf_node_as_block(node
));
344 unreachable("Invalid CFG node block");
350 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
352 /* first, put the condition into f0 */
353 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
354 retype(get_nir_src(if_stmt
->condition
),
355 BRW_REGISTER_TYPE_D
));
356 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
358 bld
.IF(BRW_PREDICATE_NORMAL
);
360 nir_emit_cf_list(&if_stmt
->then_list
);
362 /* note: if the else is empty, dead CF elimination will remove it */
363 bld
.emit(BRW_OPCODE_ELSE
);
365 nir_emit_cf_list(&if_stmt
->else_list
);
367 bld
.emit(BRW_OPCODE_ENDIF
);
371 fs_visitor::nir_emit_loop(nir_loop
*loop
)
373 bld
.emit(BRW_OPCODE_DO
);
375 nir_emit_cf_list(&loop
->body
);
377 bld
.emit(BRW_OPCODE_WHILE
);
381 fs_visitor::nir_emit_block(nir_block
*block
)
383 nir_foreach_instr(instr
, block
) {
384 nir_emit_instr(instr
);
389 fs_visitor::nir_emit_instr(nir_instr
*instr
)
391 const fs_builder abld
= bld
.annotate(NULL
, instr
);
393 switch (instr
->type
) {
394 case nir_instr_type_alu
:
395 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
398 case nir_instr_type_intrinsic
:
400 case MESA_SHADER_VERTEX
:
401 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
403 case MESA_SHADER_TESS_CTRL
:
404 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
406 case MESA_SHADER_TESS_EVAL
:
407 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
409 case MESA_SHADER_GEOMETRY
:
410 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
412 case MESA_SHADER_FRAGMENT
:
413 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
415 case MESA_SHADER_COMPUTE
:
416 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
419 unreachable("unsupported shader stage");
423 case nir_instr_type_tex
:
424 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
427 case nir_instr_type_load_const
:
428 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
431 case nir_instr_type_ssa_undef
:
432 /* We create a new VGRF for undefs on every use (by handling
433 * them in get_nir_src()), rather than for each definition.
434 * This helps register coalescing eliminate MOVs from undef.
438 case nir_instr_type_jump
:
439 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
443 unreachable("unknown instruction type");
448 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
452 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
453 const fs_reg
&result
)
455 if (!instr
->src
[0].src
.is_ssa
||
456 !instr
->src
[0].src
.ssa
->parent_instr
)
459 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
462 nir_alu_instr
*src0
=
463 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
465 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
466 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
469 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
470 assert(element
!= NULL
);
472 /* Element type to extract.*/
473 const brw_reg_type type
= brw_int_type(
474 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
475 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
477 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
478 op0
.type
= brw_type_for_nir_type(devinfo
,
479 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
480 nir_src_bit_size(src0
->src
[0].src
)));
481 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
483 set_saturate(instr
->dest
.saturate
,
484 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
489 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
490 const fs_reg
&result
)
492 if (!instr
->src
[0].src
.is_ssa
||
493 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
496 nir_intrinsic_instr
*src0
=
497 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
499 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
502 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
503 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
506 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
507 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
510 fs_reg tmp
= vgrf(glsl_type::int_type
);
512 if (devinfo
->gen
>= 6) {
513 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
514 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
516 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
518 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
519 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
521 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
523 * This negation looks like it's safe in practice, because bits 0:4 will
524 * surely be TRIANGLES
527 if (value1
->f32
[0] == -1.0f
) {
531 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
532 g0
, brw_imm_uw(0x3f80));
534 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
535 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
537 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
539 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
540 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
542 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
544 * This negation looks like it's safe in practice, because bits 0:4 will
545 * surely be TRIANGLES
548 if (value1
->f32
[0] == -1.0f
) {
552 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
554 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
560 emit_find_msb_using_lzd(const fs_builder
&bld
,
561 const fs_reg
&result
,
569 /* LZD of an absolute value source almost always does the right
570 * thing. There are two problem values:
572 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
573 * 0. However, findMSB(int(0x80000000)) == 30.
575 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
576 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
578 * For a value of zero or negative one, -1 will be returned.
580 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
581 * findMSB(-(1<<x)) should return x-1.
583 * For all negative number cases, including 0x80000000 and
584 * 0xffffffff, the correct value is obtained from LZD if instead of
585 * negating the (already negative) value the logical-not is used. A
586 * conditonal logical-not can be achieved in two instructions.
588 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
590 bld
.ASR(temp
, src
, brw_imm_d(31));
591 bld
.XOR(temp
, temp
, src
);
594 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
595 retype(temp
, BRW_REGISTER_TYPE_UD
));
597 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
598 * from the LSB side. Subtract the result from 31 to convert the MSB
599 * count into an LSB count. If no bits are set, LZD will return 32.
600 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
602 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
603 inst
->src
[0].negate
= true;
607 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
609 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
612 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
613 result
.type
= brw_type_for_nir_type(devinfo
,
614 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
615 nir_dest_bit_size(instr
->dest
.dest
)));
618 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
619 op
[i
] = get_nir_src(instr
->src
[i
].src
);
620 op
[i
].type
= brw_type_for_nir_type(devinfo
,
621 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
622 nir_src_bit_size(instr
->src
[i
].src
)));
623 op
[i
].abs
= instr
->src
[i
].abs
;
624 op
[i
].negate
= instr
->src
[i
].negate
;
627 /* We get a bunch of mov's out of the from_ssa pass and they may still
628 * be vectorized. We'll handle them as a special-case. We'll also
629 * handle vecN here because it's basically the same thing.
637 fs_reg temp
= result
;
638 bool need_extra_copy
= false;
639 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
640 if (!instr
->src
[i
].src
.is_ssa
&&
641 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
642 need_extra_copy
= true;
643 temp
= bld
.vgrf(result
.type
, 4);
648 for (unsigned i
= 0; i
< 4; i
++) {
649 if (!(instr
->dest
.write_mask
& (1 << i
)))
652 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
653 inst
= bld
.MOV(offset(temp
, bld
, i
),
654 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
656 inst
= bld
.MOV(offset(temp
, bld
, i
),
657 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
659 inst
->saturate
= instr
->dest
.saturate
;
662 /* In this case the source and destination registers were the same,
663 * so we need to insert an extra set of moves in order to deal with
666 if (need_extra_copy
) {
667 for (unsigned i
= 0; i
< 4; i
++) {
668 if (!(instr
->dest
.write_mask
& (1 << i
)))
671 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
680 /* At this point, we have dealt with any instruction that operates on
681 * more than a single channel. Therefore, we can just adjust the source
682 * and destination registers for that channel and emit the instruction.
684 unsigned channel
= 0;
685 if (nir_op_infos
[instr
->op
].output_size
== 0) {
686 /* Since NIR is doing the scalarizing for us, we should only ever see
687 * vectorized operations with a single channel.
689 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
690 channel
= ffs(instr
->dest
.write_mask
) - 1;
692 result
= offset(result
, bld
, channel
);
695 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
696 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
697 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
703 if (optimize_extract_to_float(instr
, result
))
705 inst
= bld
.MOV(result
, op
[0]);
706 inst
->saturate
= instr
->dest
.saturate
;
712 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
714 * "When source or destination is 64b (...), regioning in Align1
715 * must follow these rules:
717 * 1. Source and destination horizontal stride must be aligned to
721 * This means that 32-bit to 64-bit conversions need to have the 32-bit
722 * data elements aligned to 64-bit. This restriction does not apply to
725 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
726 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
727 (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
))) {
728 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
729 tmp
= subscript(tmp
, op
[0].type
, 0);
730 inst
= bld
.MOV(tmp
, op
[0]);
731 inst
= bld
.MOV(result
, tmp
);
732 inst
->saturate
= instr
->dest
.saturate
;
745 inst
= bld
.MOV(result
, op
[0]);
746 inst
->saturate
= instr
->dest
.saturate
;
751 /* Straightforward since the source can be assumed to be
754 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
755 set_predicate(BRW_PREDICATE_NORMAL
, bld
.MOV(result
, brw_imm_f(1.0f
)));
757 } else if (type_sz(op
[0].type
) < 8) {
758 /* AND(val, 0x80000000) gives the sign bit.
760 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
763 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
765 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
766 op
[0].type
= BRW_REGISTER_TYPE_UD
;
767 result
.type
= BRW_REGISTER_TYPE_UD
;
768 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
770 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
771 inst
->predicate
= BRW_PREDICATE_NORMAL
;
772 if (instr
->dest
.saturate
) {
773 inst
= bld
.MOV(result
, result
);
774 inst
->saturate
= true;
777 /* For doubles we do the same but we need to consider:
779 * - 2-src instructions can't operate with 64-bit immediates
780 * - The sign is encoded in the high 32-bit of each DF
781 * - We need to produce a DF result.
784 fs_reg zero
= vgrf(glsl_type::double_type
);
785 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
786 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
788 bld
.MOV(result
, zero
);
790 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
791 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
792 brw_imm_ud(0x80000000u
));
794 set_predicate(BRW_PREDICATE_NORMAL
,
795 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
797 if (instr
->dest
.saturate
) {
798 inst
= bld
.MOV(result
, result
);
799 inst
->saturate
= true;
806 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
807 * -> non-negative val generates 0x00000000.
808 * Predicated OR sets 1 if val is positive.
810 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
811 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
812 bld
.ASR(result
, op
[0], brw_imm_d(31));
813 inst
= bld
.OR(result
, result
, brw_imm_d(1));
814 inst
->predicate
= BRW_PREDICATE_NORMAL
;
818 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
819 inst
->saturate
= instr
->dest
.saturate
;
823 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
824 inst
->saturate
= instr
->dest
.saturate
;
828 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
829 inst
->saturate
= instr
->dest
.saturate
;
833 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
834 inst
->saturate
= instr
->dest
.saturate
;
838 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
839 inst
->saturate
= instr
->dest
.saturate
;
843 if (fs_key
->high_quality_derivatives
) {
844 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
846 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
848 inst
->saturate
= instr
->dest
.saturate
;
850 case nir_op_fddx_fine
:
851 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
852 inst
->saturate
= instr
->dest
.saturate
;
854 case nir_op_fddx_coarse
:
855 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
856 inst
->saturate
= instr
->dest
.saturate
;
859 if (fs_key
->high_quality_derivatives
) {
860 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
862 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
864 inst
->saturate
= instr
->dest
.saturate
;
866 case nir_op_fddy_fine
:
867 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
868 inst
->saturate
= instr
->dest
.saturate
;
870 case nir_op_fddy_coarse
:
871 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
872 inst
->saturate
= instr
->dest
.saturate
;
877 inst
= bld
.ADD(result
, op
[0], op
[1]);
878 inst
->saturate
= instr
->dest
.saturate
;
882 inst
= bld
.MUL(result
, op
[0], op
[1]);
883 inst
->saturate
= instr
->dest
.saturate
;
887 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
888 bld
.MUL(result
, op
[0], op
[1]);
891 case nir_op_imul_high
:
892 case nir_op_umul_high
:
893 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
894 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
899 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
900 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
903 case nir_op_uadd_carry
:
904 unreachable("Should have been lowered by carry_to_arith().");
906 case nir_op_usub_borrow
:
907 unreachable("Should have been lowered by borrow_to_arith().");
911 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
912 * appears that our hardware just does the right thing for signed
915 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
916 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
920 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
921 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
923 /* Math instructions don't support conditional mod */
924 inst
= bld
.MOV(bld
.null_reg_d(), result
);
925 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
927 /* Now, we need to determine if signs of the sources are different.
928 * When we XOR the sources, the top bit is 0 if they are the same and 1
929 * if they are different. We can then use a conditional modifier to
930 * turn that into a predicate. This leads us to an XOR.l instruction.
932 * Technically, according to the PRM, you're not allowed to use .l on a
933 * XOR instruction. However, emperical experiments and Curro's reading
934 * of the simulator source both indicate that it's safe.
936 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
937 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
938 inst
->predicate
= BRW_PREDICATE_NORMAL
;
939 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
941 /* If the result of the initial remainder operation is non-zero and the
942 * two sources have different signs, add in a copy of op[1] to get the
943 * final integer modulus value.
945 inst
= bld
.ADD(result
, result
, op
[1]);
946 inst
->predicate
= BRW_PREDICATE_NORMAL
;
954 fs_reg dest
= result
;
955 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
956 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
958 brw_conditional_mod cond
;
961 cond
= BRW_CONDITIONAL_L
;
964 cond
= BRW_CONDITIONAL_GE
;
967 cond
= BRW_CONDITIONAL_Z
;
970 cond
= BRW_CONDITIONAL_NZ
;
973 unreachable("bad opcode");
975 bld
.CMP(dest
, op
[0], op
[1], cond
);
976 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
977 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
988 fs_reg dest
= result
;
989 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
990 dest
= bld
.vgrf(BRW_REGISTER_TYPE_UQ
, 1);
993 brw_conditional_mod cond
;
997 cond
= BRW_CONDITIONAL_L
;
1001 cond
= BRW_CONDITIONAL_GE
;
1004 cond
= BRW_CONDITIONAL_Z
;
1007 cond
= BRW_CONDITIONAL_NZ
;
1010 unreachable("bad opcode");
1012 bld
.CMP(dest
, op
[0], op
[1], cond
);
1013 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1014 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1020 if (devinfo
->gen
>= 8) {
1021 op
[0] = resolve_source_modifiers(op
[0]);
1023 bld
.NOT(result
, op
[0]);
1026 if (devinfo
->gen
>= 8) {
1027 op
[0] = resolve_source_modifiers(op
[0]);
1028 op
[1] = resolve_source_modifiers(op
[1]);
1030 bld
.XOR(result
, op
[0], op
[1]);
1033 if (devinfo
->gen
>= 8) {
1034 op
[0] = resolve_source_modifiers(op
[0]);
1035 op
[1] = resolve_source_modifiers(op
[1]);
1037 bld
.OR(result
, op
[0], op
[1]);
1040 if (devinfo
->gen
>= 8) {
1041 op
[0] = resolve_source_modifiers(op
[0]);
1042 op
[1] = resolve_source_modifiers(op
[1]);
1044 bld
.AND(result
, op
[0], op
[1]);
1050 case nir_op_ball_fequal2
:
1051 case nir_op_ball_iequal2
:
1052 case nir_op_ball_fequal3
:
1053 case nir_op_ball_iequal3
:
1054 case nir_op_ball_fequal4
:
1055 case nir_op_ball_iequal4
:
1056 case nir_op_bany_fnequal2
:
1057 case nir_op_bany_inequal2
:
1058 case nir_op_bany_fnequal3
:
1059 case nir_op_bany_inequal3
:
1060 case nir_op_bany_fnequal4
:
1061 case nir_op_bany_inequal4
:
1062 unreachable("Lowered by nir_lower_alu_reductions");
1064 case nir_op_fnoise1_1
:
1065 case nir_op_fnoise1_2
:
1066 case nir_op_fnoise1_3
:
1067 case nir_op_fnoise1_4
:
1068 case nir_op_fnoise2_1
:
1069 case nir_op_fnoise2_2
:
1070 case nir_op_fnoise2_3
:
1071 case nir_op_fnoise2_4
:
1072 case nir_op_fnoise3_1
:
1073 case nir_op_fnoise3_2
:
1074 case nir_op_fnoise3_3
:
1075 case nir_op_fnoise3_4
:
1076 case nir_op_fnoise4_1
:
1077 case nir_op_fnoise4_2
:
1078 case nir_op_fnoise4_3
:
1079 case nir_op_fnoise4_4
:
1080 unreachable("not reached: should be handled by lower_noise");
1083 unreachable("not reached: should be handled by ldexp_to_arith()");
1086 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1087 inst
->saturate
= instr
->dest
.saturate
;
1091 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1092 inst
->saturate
= instr
->dest
.saturate
;
1097 bld
.MOV(result
, negate(op
[0]));
1102 if (nir_src_bit_size(instr
->src
[0].src
) == 64) {
1103 /* two-argument instructions can't take 64-bit immediates */
1107 if (instr
->op
== nir_op_f2b
) {
1108 zero
= vgrf(glsl_type::double_type
);
1109 tmp
= vgrf(glsl_type::double_type
);
1111 zero
= vgrf(glsl_type::int64_t_type
);
1112 tmp
= vgrf(glsl_type::int64_t_type
);
1115 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1116 /* A SIMD16 execution needs to be split in two instructions, so use
1117 * a vgrf instead of the flag register as dst so instruction splitting
1120 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1121 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1123 if (instr
->op
== nir_op_f2b
) {
1124 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1126 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1132 inst
= bld
.RNDZ(result
, op
[0]);
1133 inst
->saturate
= instr
->dest
.saturate
;
1136 case nir_op_fceil
: {
1137 op
[0].negate
= !op
[0].negate
;
1138 fs_reg temp
= vgrf(glsl_type::float_type
);
1139 bld
.RNDD(temp
, op
[0]);
1141 inst
= bld
.MOV(result
, temp
);
1142 inst
->saturate
= instr
->dest
.saturate
;
1146 inst
= bld
.RNDD(result
, op
[0]);
1147 inst
->saturate
= instr
->dest
.saturate
;
1150 inst
= bld
.FRC(result
, op
[0]);
1151 inst
->saturate
= instr
->dest
.saturate
;
1153 case nir_op_fround_even
:
1154 inst
= bld
.RNDE(result
, op
[0]);
1155 inst
->saturate
= instr
->dest
.saturate
;
1158 case nir_op_fquantize2f16
: {
1159 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1160 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1161 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1163 /* The destination stride must be at least as big as the source stride. */
1164 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1167 /* Check for denormal */
1168 fs_reg abs_src0
= op
[0];
1169 abs_src0
.abs
= true;
1170 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1172 /* Get the appropriately signed zero */
1173 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1174 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1175 brw_imm_ud(0x80000000));
1176 /* Do the actual F32 -> F16 -> F32 conversion */
1177 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1178 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1179 /* Select that or zero based on normal status */
1180 inst
= bld
.SEL(result
, zero
, tmp32
);
1181 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1182 inst
->saturate
= instr
->dest
.saturate
;
1189 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1190 inst
->saturate
= instr
->dest
.saturate
;
1196 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1197 inst
->saturate
= instr
->dest
.saturate
;
1200 case nir_op_pack_snorm_2x16
:
1201 case nir_op_pack_snorm_4x8
:
1202 case nir_op_pack_unorm_2x16
:
1203 case nir_op_pack_unorm_4x8
:
1204 case nir_op_unpack_snorm_2x16
:
1205 case nir_op_unpack_snorm_4x8
:
1206 case nir_op_unpack_unorm_2x16
:
1207 case nir_op_unpack_unorm_4x8
:
1208 case nir_op_unpack_half_2x16
:
1209 case nir_op_pack_half_2x16
:
1210 unreachable("not reached: should be handled by lower_packing_builtins");
1212 case nir_op_unpack_half_2x16_split_x
:
1213 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1214 inst
->saturate
= instr
->dest
.saturate
;
1216 case nir_op_unpack_half_2x16_split_y
:
1217 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1218 inst
->saturate
= instr
->dest
.saturate
;
1221 case nir_op_pack_64_2x32_split
:
1222 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1225 case nir_op_unpack_64_2x32_split_x
:
1226 case nir_op_unpack_64_2x32_split_y
: {
1227 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1228 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1230 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1235 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1236 inst
->saturate
= instr
->dest
.saturate
;
1239 case nir_op_bitfield_reverse
:
1240 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1241 bld
.BFREV(result
, op
[0]);
1244 case nir_op_bit_count
:
1245 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1246 bld
.CBIT(result
, op
[0]);
1249 case nir_op_ufind_msb
: {
1250 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1251 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1255 case nir_op_ifind_msb
: {
1256 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1258 if (devinfo
->gen
< 7) {
1259 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1261 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1263 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1264 * count from the LSB side. If FBH didn't return an error
1265 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1266 * count into an LSB count.
1268 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1270 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1271 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1272 inst
->src
[0].negate
= true;
1277 case nir_op_find_lsb
:
1278 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1280 if (devinfo
->gen
< 7) {
1281 fs_reg temp
= vgrf(glsl_type::int_type
);
1283 /* (x & -x) generates a value that consists of only the LSB of x.
1284 * For all powers of 2, findMSB(y) == findLSB(y).
1286 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1287 fs_reg negated_src
= src
;
1289 /* One must be negated, and the other must be non-negated. It
1290 * doesn't matter which is which.
1292 negated_src
.negate
= true;
1295 bld
.AND(temp
, src
, negated_src
);
1296 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1298 bld
.FBL(result
, op
[0]);
1302 case nir_op_ubitfield_extract
:
1303 case nir_op_ibitfield_extract
:
1304 unreachable("should have been lowered");
1307 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1308 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1311 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1312 bld
.BFI1(result
, op
[0], op
[1]);
1315 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1316 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1319 case nir_op_bitfield_insert
:
1320 unreachable("not reached: should have been lowered");
1325 fs_reg shift_count
= op
[1];
1327 if (devinfo
->is_cherryview
|| gen_device_info_is_9lp(devinfo
)) {
1328 if (op
[1].file
== VGRF
&&
1329 (result
.type
== BRW_REGISTER_TYPE_Q
||
1330 result
.type
== BRW_REGISTER_TYPE_UQ
)) {
1331 shift_count
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 4),
1332 BRW_REGISTER_TYPE_UD
);
1333 shift_count
.stride
= 2;
1334 bld
.MOV(shift_count
, op
[1]);
1338 switch (instr
->op
) {
1340 bld
.SHL(result
, op
[0], shift_count
);
1343 bld
.ASR(result
, op
[0], shift_count
);
1346 bld
.SHR(result
, op
[0], shift_count
);
1349 unreachable("not reached");
1354 case nir_op_pack_half_2x16_split
:
1355 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1359 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1360 inst
->saturate
= instr
->dest
.saturate
;
1364 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1365 inst
->saturate
= instr
->dest
.saturate
;
1369 if (optimize_frontfacing_ternary(instr
, result
))
1372 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1373 inst
= bld
.SEL(result
, op
[1], op
[2]);
1374 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1377 case nir_op_extract_u8
:
1378 case nir_op_extract_i8
: {
1379 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1380 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1381 assert(byte
!= NULL
);
1382 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1386 case nir_op_extract_u16
:
1387 case nir_op_extract_i16
: {
1388 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1389 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1390 assert(word
!= NULL
);
1391 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1396 unreachable("unhandled instruction");
1399 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1400 * to sign extend the low bit to 0/~0
1402 if (devinfo
->gen
<= 5 &&
1403 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1404 fs_reg masked
= vgrf(glsl_type::int_type
);
1405 bld
.AND(masked
, result
, brw_imm_d(1));
1406 masked
.negate
= true;
1407 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1412 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1413 nir_load_const_instr
*instr
)
1415 const brw_reg_type reg_type
=
1416 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1417 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1419 switch (instr
->def
.bit_size
) {
1421 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1422 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1426 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1427 bld
.MOV(offset(reg
, bld
, i
),
1428 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1432 unreachable("Invalid bit size");
1435 nir_ssa_values
[instr
->def
.index
] = reg
;
1439 fs_visitor::get_nir_src(const nir_src
&src
)
1443 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1444 const brw_reg_type reg_type
=
1445 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1446 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1448 reg
= nir_ssa_values
[src
.ssa
->index
];
1451 /* We don't handle indirects on locals */
1452 assert(src
.reg
.indirect
== NULL
);
1453 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1454 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1457 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1458 /* The only 64-bit type available on gen7 is DF, so use that. */
1459 reg
.type
= BRW_REGISTER_TYPE_DF
;
1461 /* To avoid floating-point denorm flushing problems, set the type by
1462 * default to an integer type - instructions that need floating point
1463 * semantics will set this to F if they need to
1465 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1466 BRW_REGISTER_TYPE_D
);
1473 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1475 * This function should not be called on any value which may be 64 bits.
1476 * We could theoretically support 64-bit on gen8+ but we choose not to
1477 * because it wouldn't work in general (no gen7 support) and there are
1478 * enough restrictions in 64-bit immediates that you can't take the return
1479 * value and treat it the same as the result of get_nir_src().
1482 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1484 nir_const_value
*val
= nir_src_as_const_value(src
);
1485 assert(nir_src_bit_size(src
) == 32);
1486 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1490 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1493 const brw_reg_type reg_type
=
1494 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
, BRW_REGISTER_TYPE_F
);
1495 nir_ssa_values
[dest
.ssa
.index
] =
1496 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1497 return nir_ssa_values
[dest
.ssa
.index
];
1499 /* We don't handle indirects on locals */
1500 assert(dest
.reg
.indirect
== NULL
);
1501 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1502 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1507 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1509 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1510 BRW_REGISTER_TYPE_UD
);
1512 unsigned indirect_max
= 0;
1514 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1515 tail
= tail
->child
) {
1516 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1517 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1518 const unsigned size
= glsl_get_length(tail
->type
);
1519 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1520 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1521 image
= offset(image
, bld
, base
* element_size
);
1523 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1524 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1526 /* Accessing an invalid surface index with the dataport can result
1527 * in a hang. According to the spec "if the index used to
1528 * select an individual element is negative or greater than or
1529 * equal to the size of the array, the results of the operation
1530 * are undefined but may not lead to termination" -- which is one
1531 * of the possible outcomes of the hang. Clamp the index to
1532 * prevent access outside of the array bounds.
1534 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1535 BRW_REGISTER_TYPE_UD
),
1536 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1538 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1540 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1541 if (indirect
.file
== BAD_FILE
) {
1544 bld
.ADD(indirect
, indirect
, tmp
);
1549 if (indirect
.file
== BAD_FILE
) {
1552 /* Emit a pile of MOVs to load the uniform into a temporary. The
1553 * dead-code elimination pass will get rid of what we don't use.
1555 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1556 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1557 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1558 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1559 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1566 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1569 for (unsigned i
= 0; i
< 4; i
++) {
1570 if (!((wr_mask
>> i
) & 1))
1573 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1574 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1575 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1576 if (new_inst
->src
[j
].file
== VGRF
)
1577 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1584 * Get the matching channel register datatype for an image intrinsic of the
1585 * specified GLSL image type.
1588 get_image_base_type(const glsl_type
*type
)
1590 switch ((glsl_base_type
)type
->sampled_type
) {
1591 case GLSL_TYPE_UINT
:
1592 return BRW_REGISTER_TYPE_UD
;
1594 return BRW_REGISTER_TYPE_D
;
1595 case GLSL_TYPE_FLOAT
:
1596 return BRW_REGISTER_TYPE_F
;
1598 unreachable("Not reached.");
1603 * Get the appropriate atomic op for an image atomic intrinsic.
1606 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1609 case nir_intrinsic_image_atomic_add
:
1611 case nir_intrinsic_image_atomic_min
:
1612 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1613 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1614 case nir_intrinsic_image_atomic_max
:
1615 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1616 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1617 case nir_intrinsic_image_atomic_and
:
1619 case nir_intrinsic_image_atomic_or
:
1621 case nir_intrinsic_image_atomic_xor
:
1623 case nir_intrinsic_image_atomic_exchange
:
1625 case nir_intrinsic_image_atomic_comp_swap
:
1626 return BRW_AOP_CMPWR
;
1628 unreachable("Not reachable.");
1633 emit_pixel_interpolater_send(const fs_builder
&bld
,
1638 glsl_interp_mode interpolation
)
1640 struct brw_wm_prog_data
*wm_prog_data
=
1641 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1646 if (src
.file
== BAD_FILE
) {
1648 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1652 mlen
= 2 * bld
.dispatch_width() / 8;
1655 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1657 /* 2 floats per slot returned */
1658 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1659 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1661 wm_prog_data
->pulls_bary
= true;
1667 * Computes 1 << x, given a D/UD register containing some value x.
1670 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1672 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1674 fs_reg result
= bld
.vgrf(x
.type
, 1);
1675 fs_reg one
= bld
.vgrf(x
.type
, 1);
1677 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1678 bld
.SHL(result
, one
, x
);
1683 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1685 assert(stage
== MESA_SHADER_GEOMETRY
);
1687 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1689 if (gs_compile
->control_data_header_size_bits
== 0)
1692 /* We can only do EndPrimitive() functionality when the control data
1693 * consists of cut bits. Fortunately, the only time it isn't is when the
1694 * output type is points, in which case EndPrimitive() is a no-op.
1696 if (gs_prog_data
->control_data_format
!=
1697 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1701 /* Cut bits use one bit per vertex. */
1702 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1704 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1705 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1707 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1708 * vertex n, 0 otherwise. So all we need to do here is mark bit
1709 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1710 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1711 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1713 * Note that if EndPrimitive() is called before emitting any vertices, this
1714 * will cause us to set bit 31 of the control_data_bits register to 1.
1715 * That's fine because:
1717 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1718 * output, so the hardware will ignore cut bit 31.
1720 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1721 * last vertex, so setting cut bit 31 has no effect (since the primitive
1722 * is automatically ended when the GS terminates).
1724 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1725 * control_data_bits register to 0 when the first vertex is emitted.
1728 const fs_builder abld
= bld
.annotate("end primitive");
1730 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1731 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1732 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1733 fs_reg mask
= intexp2(abld
, prev_count
);
1734 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1735 * attention to the lower 5 bits of its second source argument, so on this
1736 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1737 * ((vertex_count - 1) % 32).
1739 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1743 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1745 assert(stage
== MESA_SHADER_GEOMETRY
);
1746 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1748 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1750 const fs_builder abld
= bld
.annotate("emit control data bits");
1751 const fs_builder fwa_bld
= bld
.exec_all();
1753 /* We use a single UD register to accumulate control data bits (32 bits
1754 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1757 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1758 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1759 * use the Channel Mask phase to enable/disable which DWord within that
1760 * group to write. (Remember, different SIMD8 channels may have emitted
1761 * different numbers of vertices, so we may need per-slot offsets.)
1763 * Channel masking presents an annoying problem: we may have to replicate
1764 * the data up to 4 times:
1766 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1768 * To avoid penalizing shaders that emit a small number of vertices, we
1769 * can avoid these sometimes: if the size of the control data header is
1770 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1771 * land in the same 128-bit group, so we can skip per-slot offsets.
1773 * Similarly, if the control data header is <= 32 bits, there is only one
1774 * DWord, so we can skip channel masks.
1776 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1778 fs_reg channel_mask
, per_slot_offset
;
1780 if (gs_compile
->control_data_header_size_bits
> 32) {
1781 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1782 channel_mask
= vgrf(glsl_type::uint_type
);
1785 if (gs_compile
->control_data_header_size_bits
> 128) {
1786 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1787 per_slot_offset
= vgrf(glsl_type::uint_type
);
1790 /* Figure out which DWord we're trying to write to using the formula:
1792 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1794 * Since bits_per_vertex is a power of two, and is known at compile
1795 * time, this can be optimized to:
1797 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1799 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1800 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1801 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1802 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1803 unsigned log2_bits_per_vertex
=
1804 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1805 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1807 if (per_slot_offset
.file
!= BAD_FILE
) {
1808 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1809 * the appropriate OWord within the control data header.
1811 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1814 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1815 * write to the appropriate DWORD within the OWORD.
1817 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1818 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1819 channel_mask
= intexp2(fwa_bld
, channel
);
1820 /* Then the channel masks need to be in bits 23:16. */
1821 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1824 /* Store the control data bits in the message payload and send it. */
1826 if (channel_mask
.file
!= BAD_FILE
)
1827 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1828 if (per_slot_offset
.file
!= BAD_FILE
)
1831 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1832 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1834 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1835 if (per_slot_offset
.file
!= BAD_FILE
)
1836 sources
[i
++] = per_slot_offset
;
1837 if (channel_mask
.file
!= BAD_FILE
)
1838 sources
[i
++] = channel_mask
;
1840 sources
[i
++] = this->control_data_bits
;
1843 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1844 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1846 /* We need to increment Global Offset by 256-bits to make room for
1847 * Broadwell's extra "Vertex Count" payload at the beginning of the
1848 * URB entry. Since this is an OWord message, Global Offset is counted
1849 * in 128-bit units, so we must set it to 2.
1851 if (gs_prog_data
->static_vertex_count
== -1)
1856 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1859 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1861 /* Note: we are calling this *before* increasing vertex_count, so
1862 * this->vertex_count == vertex_count - 1 in the formula above.
1865 /* Stream mode uses 2 bits per vertex */
1866 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1868 /* Must be a valid stream */
1869 assert(stream_id
< MAX_VERTEX_STREAMS
);
1871 /* Control data bits are initialized to 0 so we don't have to set any
1872 * bits when sending vertices to stream 0.
1877 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1879 /* reg::sid = stream_id */
1880 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1881 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1883 /* reg:shift_count = 2 * (vertex_count - 1) */
1884 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1885 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1887 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1888 * attention to the lower 5 bits of its second source argument, so on this
1889 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1890 * stream_id << ((2 * (vertex_count - 1)) % 32).
1892 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1893 abld
.SHL(mask
, sid
, shift_count
);
1894 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1898 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1901 assert(stage
== MESA_SHADER_GEOMETRY
);
1903 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1905 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1906 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1908 /* Haswell and later hardware ignores the "Render Stream Select" bits
1909 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1910 * and instead sends all primitives down the pipeline for rasterization.
1911 * If the SOL stage is enabled, "Render Stream Select" is honored and
1912 * primitives bound to non-zero streams are discarded after stream output.
1914 * Since the only purpose of primives sent to non-zero streams is to
1915 * be recorded by transform feedback, we can simply discard all geometry
1916 * bound to these streams when transform feedback is disabled.
1918 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1921 /* If we're outputting 32 control data bits or less, then we can wait
1922 * until the shader is over to output them all. Otherwise we need to
1923 * output them as we go. Now is the time to do it, since we're about to
1924 * output the vertex_count'th vertex, so it's guaranteed that the
1925 * control data bits associated with the (vertex_count - 1)th vertex are
1928 if (gs_compile
->control_data_header_size_bits
> 32) {
1929 const fs_builder abld
=
1930 bld
.annotate("emit vertex: emit control data bits");
1932 /* Only emit control data bits if we've finished accumulating a batch
1933 * of 32 bits. This is the case when:
1935 * (vertex_count * bits_per_vertex) % 32 == 0
1937 * (in other words, when the last 5 bits of vertex_count *
1938 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1939 * integer n (which is always the case, since bits_per_vertex is
1940 * always 1 or 2), this is equivalent to requiring that the last 5-n
1941 * bits of vertex_count are 0:
1943 * vertex_count & (2^(5-n) - 1) == 0
1945 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1948 * vertex_count & (32 / bits_per_vertex - 1) == 0
1950 * TODO: If vertex_count is an immediate, we could do some of this math
1951 * at compile time...
1954 abld
.AND(bld
.null_reg_d(), vertex_count
,
1955 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1956 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1958 abld
.IF(BRW_PREDICATE_NORMAL
);
1959 /* If vertex_count is 0, then no control data bits have been
1960 * accumulated yet, so we can skip emitting them.
1962 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1963 BRW_CONDITIONAL_NEQ
);
1964 abld
.IF(BRW_PREDICATE_NORMAL
);
1965 emit_gs_control_data_bits(vertex_count
);
1966 abld
.emit(BRW_OPCODE_ENDIF
);
1968 /* Reset control_data_bits to 0 so we can start accumulating a new
1971 * Note: in the case where vertex_count == 0, this neutralizes the
1972 * effect of any call to EndPrimitive() that the shader may have
1973 * made before outputting its first vertex.
1975 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1976 inst
->force_writemask_all
= true;
1977 abld
.emit(BRW_OPCODE_ENDIF
);
1980 emit_urb_writes(vertex_count
);
1982 /* In stream mode we have to set control data bits for all vertices
1983 * unless we have disabled control data bits completely (which we do
1984 * do for GL_POINTS outputs that don't use streams).
1986 if (gs_compile
->control_data_header_size_bits
> 0 &&
1987 gs_prog_data
->control_data_format
==
1988 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1989 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1994 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1995 const nir_src
&vertex_src
,
1996 unsigned base_offset
,
1997 const nir_src
&offset_src
,
1998 unsigned num_components
,
1999 unsigned first_component
)
2001 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2003 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2004 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2005 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2007 /* TODO: figure out push input layout for invocations == 1 */
2008 /* TODO: make this work with 64-bit inputs */
2009 if (gs_prog_data
->invocations
== 1 &&
2010 type_sz(dst
.type
) <= 4 &&
2011 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2012 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2013 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2014 vertex_const
->u32
[0] * push_reg_count
;
2015 for (unsigned i
= 0; i
< num_components
; i
++) {
2016 bld
.MOV(offset(dst
, bld
, i
),
2017 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2022 /* Resort to the pull model. Ensure the VUE handles are provided. */
2023 assert(gs_prog_data
->base
.include_vue_handles
);
2025 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2026 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2028 if (gs_prog_data
->invocations
== 1) {
2030 /* The vertex index is constant; just select the proper URB handle. */
2032 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2033 BRW_REGISTER_TYPE_UD
);
2035 /* The vertex index is non-constant. We need to use indirect
2036 * addressing to fetch the proper URB handle.
2038 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2039 * indicating that channel <n> should read the handle from
2040 * DWord <n>. We convert that to bytes by multiplying by 4.
2042 * Next, we convert the vertex index to bytes by multiplying
2043 * by 32 (shifting by 5), and add the two together. This is
2044 * the final indirect byte offset.
2046 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2047 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2048 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2049 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2051 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2052 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2053 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2054 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2055 /* Convert vertex_index to bytes (multiply by 32) */
2056 bld
.SHL(vertex_offset_bytes
,
2057 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2059 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2061 /* Use first_icp_handle as the base offset. There is one register
2062 * of URB handles per vertex, so inform the register allocator that
2063 * we might read up to nir->info.gs.vertices_in registers.
2065 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2066 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2067 fs_reg(icp_offset_bytes
),
2068 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2071 assert(gs_prog_data
->invocations
> 1);
2074 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2076 retype(brw_vec1_grf(first_icp_handle
+
2077 vertex_const
->i32
[0] / 8,
2078 vertex_const
->i32
[0] % 8),
2079 BRW_REGISTER_TYPE_UD
));
2081 /* The vertex index is non-constant. We need to use indirect
2082 * addressing to fetch the proper URB handle.
2085 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2087 /* Convert vertex_index to bytes (multiply by 4) */
2088 bld
.SHL(icp_offset_bytes
,
2089 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2092 /* Use first_icp_handle as the base offset. There is one DWord
2093 * of URB handles per vertex, so inform the register allocator that
2094 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2096 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2097 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2098 fs_reg(icp_offset_bytes
),
2099 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2106 fs_reg tmp_dst
= dst
;
2107 fs_reg indirect_offset
= get_nir_src(offset_src
);
2108 unsigned num_iterations
= 1;
2109 unsigned orig_num_components
= num_components
;
2111 if (type_sz(dst
.type
) == 8) {
2112 if (num_components
> 2) {
2116 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2118 first_component
= first_component
/ 2;
2121 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2123 /* Constant indexing - use global offset. */
2124 if (first_component
!= 0) {
2125 unsigned read_components
= num_components
+ first_component
;
2126 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2127 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2128 inst
->size_written
= read_components
*
2129 tmp
.component_size(inst
->exec_size
);
2130 for (unsigned i
= 0; i
< num_components
; i
++) {
2131 bld
.MOV(offset(tmp_dst
, bld
, i
),
2132 offset(tmp
, bld
, i
+ first_component
));
2135 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2137 inst
->size_written
= num_components
*
2138 tmp_dst
.component_size(inst
->exec_size
);
2140 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2143 /* Indirect indexing - use per-slot offsets as well. */
2144 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2145 unsigned read_components
= num_components
+ first_component
;
2146 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2147 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2148 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2149 if (first_component
!= 0) {
2150 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2152 inst
->size_written
= read_components
*
2153 tmp
.component_size(inst
->exec_size
);
2154 for (unsigned i
= 0; i
< num_components
; i
++) {
2155 bld
.MOV(offset(tmp_dst
, bld
, i
),
2156 offset(tmp
, bld
, i
+ first_component
));
2159 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2161 inst
->size_written
= num_components
*
2162 tmp_dst
.component_size(inst
->exec_size
);
2164 inst
->offset
= base_offset
;
2168 if (type_sz(dst
.type
) == 8) {
2169 shuffle_32bit_load_result_to_64bit_data(
2170 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2172 for (unsigned c
= 0; c
< num_components
; c
++)
2173 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2176 if (num_iterations
> 1) {
2177 num_components
= orig_num_components
- 2;
2181 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2182 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2183 indirect_offset
= new_indirect
;
2190 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2192 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2193 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2196 /* The only constant offset we should find is 0. brw_nir.c's
2197 * add_const_offset_to_base() will fold other constant offsets
2198 * into instr->const_index[0].
2200 assert(const_value
->u32
[0] == 0);
2204 return get_nir_src(*offset_src
);
2208 do_untyped_vector_read(const fs_builder
&bld
,
2210 const fs_reg surf_index
,
2211 const fs_reg offset_reg
,
2212 unsigned num_components
)
2214 if (type_sz(dest
.type
) == 4) {
2215 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2218 BRW_PREDICATE_NONE
);
2219 read_result
.type
= dest
.type
;
2220 for (unsigned i
= 0; i
< num_components
; i
++)
2221 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2222 } else if (type_sz(dest
.type
) == 8) {
2223 /* Reading a dvec, so we need to:
2225 * 1. Multiply num_components by 2, to account for the fact that we
2226 * need to read 64-bit components.
2227 * 2. Shuffle the result of the load to form valid 64-bit elements
2228 * 3. Emit a second load (for components z/w) if needed.
2230 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2231 bld
.MOV(read_offset
, offset_reg
);
2233 int iters
= num_components
<= 2 ? 1 : 2;
2235 /* Load the dvec, the first iteration loads components x/y, the second
2236 * iteration, if needed, loads components z/w
2238 for (int it
= 0; it
< iters
; it
++) {
2239 /* Compute number of components to read in this iteration */
2240 int iter_components
= MIN2(2, num_components
);
2241 num_components
-= iter_components
;
2243 /* Read. Since this message reads 32-bit components, we need to
2244 * read twice as many components.
2246 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2248 iter_components
* 2,
2249 BRW_PREDICATE_NONE
);
2251 /* Shuffle the 32-bit load result into valid 64-bit data */
2252 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2253 shuffle_32bit_load_result_to_64bit_data(
2254 bld
, packed_result
, read_result
, iter_components
);
2256 /* Move each component to its destination */
2257 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2258 for (int c
= 0; c
< iter_components
; c
++) {
2259 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2260 offset(packed_result
, bld
, c
));
2263 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2266 unreachable("Unsupported type");
2271 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2272 nir_intrinsic_instr
*instr
)
2274 assert(stage
== MESA_SHADER_VERTEX
);
2277 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2278 dest
= get_nir_dest(instr
->dest
);
2280 switch (instr
->intrinsic
) {
2281 case nir_intrinsic_load_vertex_id
:
2282 unreachable("should be lowered by lower_vertex_id()");
2284 case nir_intrinsic_load_vertex_id_zero_base
:
2285 case nir_intrinsic_load_base_vertex
:
2286 case nir_intrinsic_load_instance_id
:
2287 case nir_intrinsic_load_base_instance
:
2288 case nir_intrinsic_load_draw_id
: {
2289 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2290 fs_reg val
= nir_system_values
[sv
];
2291 assert(val
.file
!= BAD_FILE
);
2292 dest
.type
= val
.type
;
2297 case nir_intrinsic_load_input
: {
2298 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2299 unsigned first_component
= nir_intrinsic_component(instr
);
2300 unsigned num_components
= instr
->num_components
;
2301 enum brw_reg_type type
= dest
.type
;
2303 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2304 assert(const_offset
&& "Indirect input loads not allowed");
2305 src
= offset(src
, bld
, const_offset
->u32
[0]);
2307 for (unsigned j
= 0; j
< num_components
; j
++) {
2308 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2311 if (type
== BRW_REGISTER_TYPE_DF
) {
2312 /* Once the double vector is read, set again its original register
2313 * type to continue with normal execution.
2315 src
= retype(src
, type
);
2316 dest
= retype(dest
, type
);
2319 if (type_sz(src
.type
) == 8) {
2320 shuffle_32bit_load_result_to_64bit_data(bld
,
2322 retype(dest
, BRW_REGISTER_TYPE_F
),
2323 instr
->num_components
);
2329 nir_emit_intrinsic(bld
, instr
);
2335 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2336 nir_intrinsic_instr
*instr
)
2338 assert(stage
== MESA_SHADER_TESS_CTRL
);
2339 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2340 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2343 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2344 dst
= get_nir_dest(instr
->dest
);
2346 switch (instr
->intrinsic
) {
2347 case nir_intrinsic_load_primitive_id
:
2348 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2350 case nir_intrinsic_load_invocation_id
:
2351 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2353 case nir_intrinsic_load_patch_vertices_in
:
2354 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2355 brw_imm_d(tcs_key
->input_vertices
));
2358 case nir_intrinsic_barrier
: {
2359 if (tcs_prog_data
->instances
== 1)
2362 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2363 fs_reg m0_2
= component(m0
, 2);
2365 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2367 /* Zero the message header */
2368 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2370 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2371 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2372 brw_imm_ud(INTEL_MASK(16, 13)));
2374 /* Shift it up to bits 27:24. */
2375 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2377 /* Set the Barrier Count and the enable bit */
2378 chanbld
.OR(m0_2
, m0_2
,
2379 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2381 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2385 case nir_intrinsic_load_input
:
2386 unreachable("nir_lower_io should never give us these.");
2389 case nir_intrinsic_load_per_vertex_input
: {
2390 fs_reg indirect_offset
= get_indirect_offset(instr
);
2391 unsigned imm_offset
= instr
->const_index
[0];
2393 const nir_src
&vertex_src
= instr
->src
[0];
2394 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2401 /* Emit a MOV to resolve <0,1,0> regioning. */
2402 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2404 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2405 vertex_const
->i32
[0] & 7),
2406 BRW_REGISTER_TYPE_UD
));
2407 } else if (tcs_prog_data
->instances
== 1 &&
2408 vertex_src
.is_ssa
&&
2409 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2410 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2411 /* For the common case of only 1 instance, an array index of
2412 * gl_InvocationID means reading g1. Skip all the indirect work.
2414 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2416 /* The vertex index is non-constant. We need to use indirect
2417 * addressing to fetch the proper URB handle.
2419 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2421 /* Each ICP handle is a single DWord (4 bytes) */
2422 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2423 bld
.SHL(vertex_offset_bytes
,
2424 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2427 /* Start at g1. We might read up to 4 registers. */
2428 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2429 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2430 brw_imm_ud(4 * REG_SIZE
));
2433 /* We can only read two double components with each URB read, so
2434 * we send two read messages in that case, each one loading up to
2435 * two double components.
2437 unsigned num_iterations
= 1;
2438 unsigned num_components
= instr
->num_components
;
2439 unsigned first_component
= nir_intrinsic_component(instr
);
2440 fs_reg orig_dst
= dst
;
2441 if (type_sz(dst
.type
) == 8) {
2442 first_component
= first_component
/ 2;
2443 if (instr
->num_components
> 2) {
2448 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2452 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2453 if (indirect_offset
.file
== BAD_FILE
) {
2454 /* Constant indexing - use global offset. */
2455 if (first_component
!= 0) {
2456 unsigned read_components
= num_components
+ first_component
;
2457 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2458 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2459 for (unsigned i
= 0; i
< num_components
; i
++) {
2460 bld
.MOV(offset(dst
, bld
, i
),
2461 offset(tmp
, bld
, i
+ first_component
));
2464 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2466 inst
->offset
= imm_offset
;
2469 /* Indirect indexing - use per-slot offsets as well. */
2470 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2471 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2472 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2473 if (first_component
!= 0) {
2474 unsigned read_components
= num_components
+ first_component
;
2475 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2476 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2478 for (unsigned i
= 0; i
< num_components
; i
++) {
2479 bld
.MOV(offset(dst
, bld
, i
),
2480 offset(tmp
, bld
, i
+ first_component
));
2483 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2486 inst
->offset
= imm_offset
;
2489 inst
->size_written
= (num_components
+ first_component
) *
2490 inst
->dst
.component_size(inst
->exec_size
);
2492 /* If we are reading 64-bit data using 32-bit read messages we need
2493 * build proper 64-bit data elements by shuffling the low and high
2494 * 32-bit components around like we do for other things like UBOs
2497 if (type_sz(dst
.type
) == 8) {
2498 shuffle_32bit_load_result_to_64bit_data(
2499 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2501 for (unsigned c
= 0; c
< num_components
; c
++) {
2502 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2503 offset(dst
, bld
, c
));
2507 /* Copy the temporary to the destination to deal with writemasking.
2509 * Also attempt to deal with gl_PointSize being in the .w component.
2511 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2512 assert(type_sz(dst
.type
) < 8);
2513 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2514 inst
->size_written
= 4 * REG_SIZE
;
2515 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2518 /* If we are loading double data and we need a second read message
2519 * adjust the write offset
2521 if (num_iterations
> 1) {
2522 num_components
= instr
->num_components
- 2;
2529 case nir_intrinsic_load_output
:
2530 case nir_intrinsic_load_per_vertex_output
: {
2531 fs_reg indirect_offset
= get_indirect_offset(instr
);
2532 unsigned imm_offset
= instr
->const_index
[0];
2533 unsigned first_component
= nir_intrinsic_component(instr
);
2536 if (indirect_offset
.file
== BAD_FILE
) {
2537 /* Replicate the patch handle to all enabled channels */
2538 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2539 bld
.MOV(patch_handle
,
2540 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2543 if (first_component
!= 0) {
2544 unsigned read_components
=
2545 instr
->num_components
+ first_component
;
2546 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2547 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2549 inst
->size_written
= read_components
* REG_SIZE
;
2550 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2551 bld
.MOV(offset(dst
, bld
, i
),
2552 offset(tmp
, bld
, i
+ first_component
));
2555 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2557 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2559 inst
->offset
= imm_offset
;
2563 /* Indirect indexing - use per-slot offsets as well. */
2564 const fs_reg srcs
[] = {
2565 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2568 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2569 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2570 if (first_component
!= 0) {
2571 unsigned read_components
=
2572 instr
->num_components
+ first_component
;
2573 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2574 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2576 inst
->size_written
= read_components
* REG_SIZE
;
2577 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2578 bld
.MOV(offset(dst
, bld
, i
),
2579 offset(tmp
, bld
, i
+ first_component
));
2582 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2584 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2586 inst
->offset
= imm_offset
;
2592 case nir_intrinsic_store_output
:
2593 case nir_intrinsic_store_per_vertex_output
: {
2594 fs_reg value
= get_nir_src(instr
->src
[0]);
2595 bool is_64bit
= (instr
->src
[0].is_ssa
?
2596 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2597 fs_reg indirect_offset
= get_indirect_offset(instr
);
2598 unsigned imm_offset
= instr
->const_index
[0];
2599 unsigned mask
= instr
->const_index
[1];
2600 unsigned header_regs
= 0;
2602 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2604 if (indirect_offset
.file
!= BAD_FILE
) {
2605 srcs
[header_regs
++] = indirect_offset
;
2611 unsigned num_components
= util_last_bit(mask
);
2614 /* We can only pack two 64-bit components in a single message, so send
2615 * 2 messages if we have more components
2617 unsigned num_iterations
= 1;
2618 unsigned iter_components
= num_components
;
2619 unsigned first_component
= nir_intrinsic_component(instr
);
2621 first_component
= first_component
/ 2;
2622 if (instr
->num_components
> 2) {
2624 iter_components
= 2;
2628 mask
= mask
<< first_component
;
2630 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2631 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2632 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2633 opcode
= indirect_offset
.file
!= BAD_FILE
?
2634 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2635 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2636 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2637 /* Expand the 64-bit mask to 32-bit channels. We only handle
2638 * two channels in each iteration, so we only care about X/Y.
2640 unsigned mask32
= 0;
2641 if (mask
& WRITEMASK_X
)
2642 mask32
|= WRITEMASK_XY
;
2643 if (mask
& WRITEMASK_Y
)
2644 mask32
|= WRITEMASK_ZW
;
2646 /* If the mask does not include any of the channels X or Y there
2647 * is nothing to do in this iteration. Move on to the next couple
2648 * of 64-bit channels.
2656 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2657 opcode
= indirect_offset
.file
!= BAD_FILE
?
2658 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2659 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2661 opcode
= indirect_offset
.file
!= BAD_FILE
?
2662 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2663 SHADER_OPCODE_URB_WRITE_SIMD8
;
2666 for (unsigned i
= 0; i
< iter_components
; i
++) {
2667 if (!(mask
& (1 << (i
+ first_component
))))
2671 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2673 /* We need to shuffle the 64-bit data to match the layout
2674 * expected by our 32-bit URB write messages. We use a temporary
2677 unsigned channel
= iter
* 2 + i
;
2678 fs_reg dest
= shuffle_64bit_data_for_32bit_write(bld
,
2679 offset(value
, bld
, channel
), 1);
2681 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2682 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2683 offset(dest
, bld
, 1);
2688 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2689 (is_64bit
? 2 * first_component
: first_component
);
2691 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2692 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2694 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2695 inst
->offset
= imm_offset
;
2698 /* If this is a 64-bit attribute, select the next two 64-bit channels
2699 * to be handled in the next iteration.
2710 nir_emit_intrinsic(bld
, instr
);
2716 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2717 nir_intrinsic_instr
*instr
)
2719 assert(stage
== MESA_SHADER_TESS_EVAL
);
2720 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2723 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2724 dest
= get_nir_dest(instr
->dest
);
2726 switch (instr
->intrinsic
) {
2727 case nir_intrinsic_load_primitive_id
:
2728 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2730 case nir_intrinsic_load_tess_coord
:
2731 /* gl_TessCoord is part of the payload in g1-3 */
2732 for (unsigned i
= 0; i
< 3; i
++) {
2733 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2737 case nir_intrinsic_load_input
:
2738 case nir_intrinsic_load_per_vertex_input
: {
2739 fs_reg indirect_offset
= get_indirect_offset(instr
);
2740 unsigned imm_offset
= instr
->const_index
[0];
2741 unsigned first_component
= nir_intrinsic_component(instr
);
2743 if (type_sz(dest
.type
) == 8) {
2744 first_component
= first_component
/ 2;
2748 if (indirect_offset
.file
== BAD_FILE
) {
2749 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2750 * which is 16 registers (since each holds 2 vec4 slots).
2752 unsigned slot_count
= 1;
2753 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2756 const unsigned max_push_slots
= 32;
2757 if (imm_offset
+ slot_count
<= max_push_slots
) {
2758 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2759 for (int i
= 0; i
< instr
->num_components
; i
++) {
2760 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2761 i
+ first_component
;
2762 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2765 tes_prog_data
->base
.urb_read_length
=
2766 MAX2(tes_prog_data
->base
.urb_read_length
,
2767 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2769 /* Replicate the patch handle to all enabled channels */
2770 const fs_reg srcs
[] = {
2771 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2773 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2774 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2776 if (first_component
!= 0) {
2777 unsigned read_components
=
2778 instr
->num_components
+ first_component
;
2779 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2780 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2782 inst
->size_written
= read_components
* REG_SIZE
;
2783 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2784 bld
.MOV(offset(dest
, bld
, i
),
2785 offset(tmp
, bld
, i
+ first_component
));
2788 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2790 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2793 inst
->offset
= imm_offset
;
2796 /* Indirect indexing - use per-slot offsets as well. */
2798 /* We can only read two double components with each URB read, so
2799 * we send two read messages in that case, each one loading up to
2800 * two double components.
2802 unsigned num_iterations
= 1;
2803 unsigned num_components
= instr
->num_components
;
2804 fs_reg orig_dest
= dest
;
2805 if (type_sz(dest
.type
) == 8) {
2806 if (instr
->num_components
> 2) {
2810 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2814 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2815 const fs_reg srcs
[] = {
2816 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2819 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2820 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2822 if (first_component
!= 0) {
2823 unsigned read_components
=
2824 num_components
+ first_component
;
2825 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2826 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2828 for (unsigned i
= 0; i
< num_components
; i
++) {
2829 bld
.MOV(offset(dest
, bld
, i
),
2830 offset(tmp
, bld
, i
+ first_component
));
2833 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2837 inst
->offset
= imm_offset
;
2838 inst
->size_written
= (num_components
+ first_component
) *
2839 inst
->dst
.component_size(inst
->exec_size
);
2841 /* If we are reading 64-bit data using 32-bit read messages we need
2842 * build proper 64-bit data elements by shuffling the low and high
2843 * 32-bit components around like we do for other things like UBOs
2846 if (type_sz(dest
.type
) == 8) {
2847 shuffle_32bit_load_result_to_64bit_data(
2848 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2850 for (unsigned c
= 0; c
< num_components
; c
++) {
2851 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2852 offset(dest
, bld
, c
));
2856 /* If we are loading double data and we need a second read message
2859 if (num_iterations
> 1) {
2860 num_components
= instr
->num_components
- 2;
2868 nir_emit_intrinsic(bld
, instr
);
2874 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2875 nir_intrinsic_instr
*instr
)
2877 assert(stage
== MESA_SHADER_GEOMETRY
);
2878 fs_reg indirect_offset
;
2881 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2882 dest
= get_nir_dest(instr
->dest
);
2884 switch (instr
->intrinsic
) {
2885 case nir_intrinsic_load_primitive_id
:
2886 assert(stage
== MESA_SHADER_GEOMETRY
);
2887 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2888 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2889 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2892 case nir_intrinsic_load_input
:
2893 unreachable("load_input intrinsics are invalid for the GS stage");
2895 case nir_intrinsic_load_per_vertex_input
:
2896 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2897 instr
->src
[1], instr
->num_components
,
2898 nir_intrinsic_component(instr
));
2901 case nir_intrinsic_emit_vertex_with_counter
:
2902 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2905 case nir_intrinsic_end_primitive_with_counter
:
2906 emit_gs_end_primitive(instr
->src
[0]);
2909 case nir_intrinsic_set_vertex_count
:
2910 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2913 case nir_intrinsic_load_invocation_id
: {
2914 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2915 assert(val
.file
!= BAD_FILE
);
2916 dest
.type
= val
.type
;
2922 nir_emit_intrinsic(bld
, instr
);
2928 * Fetch the current render target layer index.
2931 fetch_render_target_array_index(const fs_builder
&bld
)
2933 if (bld
.shader
->devinfo
->gen
>= 6) {
2934 /* The render target array index is provided in the thread payload as
2935 * bits 26:16 of r0.0.
2937 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2938 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2942 /* Pre-SNB we only ever render into the first layer of the framebuffer
2943 * since layered rendering is not implemented.
2945 return brw_imm_ud(0);
2950 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2951 * framebuffer at the current fragment coordinates and sample index.
2954 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2957 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2959 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2960 const brw_wm_prog_key
*wm_key
=
2961 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2962 assert(!wm_key
->coherent_fb_fetch
);
2963 const struct brw_wm_prog_data
*wm_prog_data
=
2964 brw_wm_prog_data(stage_prog_data
);
2966 /* Calculate the surface index relative to the start of the texture binding
2967 * table block, since that's what the texturing messages expect.
2969 const unsigned surface
= target
+
2970 wm_prog_data
->binding_table
.render_target_read_start
-
2971 wm_prog_data
->base
.binding_table
.texture_start
;
2973 brw_mark_surface_used(
2974 bld
.shader
->stage_prog_data
,
2975 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2977 /* Calculate the fragment coordinates. */
2978 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2979 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2980 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2981 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
2983 /* Calculate the sample index and MCS payload when multisampling. Luckily
2984 * the MCS fetch message behaves deterministically for UMS surfaces, so it
2985 * shouldn't be necessary to recompile based on whether the framebuffer is
2988 if (wm_key
->multisample_fbo
&&
2989 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
2990 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
2992 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
2993 const fs_reg mcs
= wm_key
->multisample_fbo
?
2994 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
2996 /* Use either a normal or a CMS texel fetch message depending on whether
2997 * the framebuffer is single or multisample. On SKL+ use the wide CMS
2998 * message just in case the framebuffer uses 16x multisampling, it should
2999 * be equivalent to the normal CMS fetch for lower multisampling modes.
3001 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3002 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3003 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3005 /* Emit the instruction. */
3006 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3008 brw_imm_ud(surface
), brw_imm_ud(0),
3009 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3010 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3012 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3013 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3019 * Actual coherent framebuffer read implemented using the native render target
3020 * read message. Requires SKL+.
3023 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3025 assert(bld
.shader
->devinfo
->gen
>= 9);
3026 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3027 inst
->target
= target
;
3028 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3034 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3036 if (n
&& regs
[0].file
!= BAD_FILE
) {
3040 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3042 for (unsigned i
= 0; i
< n
; i
++)
3050 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3052 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3053 const brw_wm_prog_key
*const key
=
3054 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3055 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3056 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3058 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3059 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3061 else if (l
== FRAG_RESULT_COLOR
)
3062 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3063 MAX2(key
->nr_color_regions
, 1));
3065 else if (l
== FRAG_RESULT_DEPTH
)
3066 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3068 else if (l
== FRAG_RESULT_STENCIL
)
3069 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3071 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3072 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3074 else if (l
>= FRAG_RESULT_DATA0
&&
3075 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3076 return alloc_temporary(v
->bld
, 4,
3077 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3080 unreachable("Invalid location");
3084 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3085 nir_intrinsic_instr
*instr
)
3087 assert(stage
== MESA_SHADER_FRAGMENT
);
3090 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3091 dest
= get_nir_dest(instr
->dest
);
3093 switch (instr
->intrinsic
) {
3094 case nir_intrinsic_load_front_face
:
3095 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3096 *emit_frontfacing_interpolation());
3099 case nir_intrinsic_load_sample_pos
: {
3100 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3101 assert(sample_pos
.file
!= BAD_FILE
);
3102 dest
.type
= sample_pos
.type
;
3103 bld
.MOV(dest
, sample_pos
);
3104 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3108 case nir_intrinsic_load_layer_id
:
3109 dest
.type
= BRW_REGISTER_TYPE_UD
;
3110 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3113 case nir_intrinsic_load_helper_invocation
:
3114 case nir_intrinsic_load_sample_mask_in
:
3115 case nir_intrinsic_load_sample_id
: {
3116 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3117 fs_reg val
= nir_system_values
[sv
];
3118 assert(val
.file
!= BAD_FILE
);
3119 dest
.type
= val
.type
;
3124 case nir_intrinsic_store_output
: {
3125 const fs_reg src
= get_nir_src(instr
->src
[0]);
3126 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3127 assert(const_offset
&& "Indirect output stores not allowed");
3128 const unsigned location
= nir_intrinsic_base(instr
) +
3129 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3130 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3133 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3134 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3135 offset(src
, bld
, j
));
3140 case nir_intrinsic_load_output
: {
3141 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3142 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3143 assert(l
>= FRAG_RESULT_DATA0
);
3144 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3145 assert(const_offset
&& "Indirect output loads not allowed");
3146 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3147 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3149 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3150 emit_coherent_fb_read(bld
, tmp
, target
);
3152 emit_non_coherent_fb_read(bld
, tmp
, target
);
3154 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3155 bld
.MOV(offset(dest
, bld
, j
),
3156 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3162 case nir_intrinsic_discard
:
3163 case nir_intrinsic_discard_if
: {
3164 /* We track our discarded pixels in f0.1. By predicating on it, we can
3165 * update just the flag bits that aren't yet discarded. If there's no
3166 * condition, we emit a CMP of g0 != g0, so all currently executing
3167 * channels will get turned off.
3170 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3171 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3172 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3174 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3175 BRW_REGISTER_TYPE_UW
));
3176 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3178 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3179 cmp
->flag_subreg
= 1;
3181 if (devinfo
->gen
>= 6) {
3182 emit_discard_jump();
3187 case nir_intrinsic_load_input
: {
3188 /* load_input is only used for flat inputs */
3189 unsigned base
= nir_intrinsic_base(instr
);
3190 unsigned component
= nir_intrinsic_component(instr
);
3191 unsigned num_components
= instr
->num_components
;
3192 enum brw_reg_type type
= dest
.type
;
3194 /* Special case fields in the VUE header */
3195 if (base
== VARYING_SLOT_LAYER
)
3197 else if (base
== VARYING_SLOT_VIEWPORT
)
3200 if (nir_dest_bit_size(instr
->dest
) == 64) {
3201 /* const_index is in 32-bit type size units that could not be aligned
3202 * with DF. We need to read the double vector as if it was a float
3203 * vector of twice the number of components to fetch the right data.
3205 type
= BRW_REGISTER_TYPE_F
;
3206 num_components
*= 2;
3209 for (unsigned int i
= 0; i
< num_components
; i
++) {
3210 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3211 interp
= suboffset(interp
, 3);
3212 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3213 retype(fs_reg(interp
), type
));
3216 if (nir_dest_bit_size(instr
->dest
) == 64) {
3217 shuffle_32bit_load_result_to_64bit_data(bld
,
3220 instr
->num_components
);
3225 case nir_intrinsic_load_barycentric_pixel
:
3226 case nir_intrinsic_load_barycentric_centroid
:
3227 case nir_intrinsic_load_barycentric_sample
:
3228 /* Do nothing - load_interpolated_input handling will handle it later. */
3231 case nir_intrinsic_load_barycentric_at_sample
: {
3232 const glsl_interp_mode interpolation
=
3233 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3235 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3238 unsigned msg_data
= const_sample
->i32
[0] << 4;
3240 emit_pixel_interpolater_send(bld
,
3241 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3244 brw_imm_ud(msg_data
),
3247 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3248 BRW_REGISTER_TYPE_UD
);
3250 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3251 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3252 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3253 bld
.exec_all().group(1, 0)
3254 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3255 emit_pixel_interpolater_send(bld
,
3256 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3262 /* Make a loop that sends a message to the pixel interpolater
3263 * for the sample number in each live channel. If there are
3264 * multiple channels with the same sample number then these
3265 * will be handled simultaneously with a single interation of
3268 bld
.emit(BRW_OPCODE_DO
);
3270 /* Get the next live sample number into sample_id_reg */
3271 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3273 /* Set the flag register so that we can perform the send
3274 * message on all channels that have the same sample number
3276 bld
.CMP(bld
.null_reg_ud(),
3277 sample_src
, sample_id
,
3278 BRW_CONDITIONAL_EQ
);
3279 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3280 bld
.exec_all().group(1, 0)
3281 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3283 emit_pixel_interpolater_send(bld
,
3284 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3289 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3291 /* Continue the loop if there are any live channels left */
3292 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3294 bld
.emit(BRW_OPCODE_WHILE
));
3300 case nir_intrinsic_load_barycentric_at_offset
: {
3301 const glsl_interp_mode interpolation
=
3302 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3304 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3307 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3308 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3310 emit_pixel_interpolater_send(bld
,
3311 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3314 brw_imm_ud(off_x
| (off_y
<< 4)),
3317 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3318 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3319 BRW_REGISTER_TYPE_F
);
3320 for (int i
= 0; i
< 2; i
++) {
3321 fs_reg temp
= vgrf(glsl_type::float_type
);
3322 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3323 fs_reg itemp
= vgrf(glsl_type::int_type
);
3325 bld
.MOV(itemp
, temp
);
3327 /* Clamp the upper end of the range to +7/16.
3328 * ARB_gpu_shader5 requires that we support a maximum offset
3329 * of +0.5, which isn't representable in a S0.4 value -- if
3330 * we didn't clamp it, we'd end up with -8/16, which is the
3331 * opposite of what the shader author wanted.
3333 * This is legal due to ARB_gpu_shader5's quantization
3336 * "Not all values of <offset> may be supported; x and y
3337 * offsets may be rounded to fixed-point values with the
3338 * number of fraction bits given by the
3339 * implementation-dependent constant
3340 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3342 set_condmod(BRW_CONDITIONAL_L
,
3343 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3346 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3347 emit_pixel_interpolater_send(bld
,
3357 case nir_intrinsic_load_interpolated_input
: {
3358 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3359 emit_fragcoord_interpolation(dest
);
3363 assert(instr
->src
[0].ssa
&&
3364 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3365 nir_intrinsic_instr
*bary_intrinsic
=
3366 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3367 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3368 enum glsl_interp_mode interp_mode
=
3369 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3372 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3373 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3374 /* Use the result of the PI message */
3375 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3377 /* Use the delta_xy values computed from the payload */
3378 enum brw_barycentric_mode bary
=
3379 brw_barycentric_mode(interp_mode
, bary_intrin
);
3381 dst_xy
= this->delta_xy
[bary
];
3384 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3386 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3387 nir_intrinsic_component(instr
) + i
));
3388 interp
.type
= BRW_REGISTER_TYPE_F
;
3389 dest
.type
= BRW_REGISTER_TYPE_F
;
3391 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3392 fs_reg tmp
= vgrf(glsl_type::float_type
);
3393 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3394 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3396 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3403 nir_emit_intrinsic(bld
, instr
);
3409 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3410 nir_intrinsic_instr
*instr
)
3412 assert(stage
== MESA_SHADER_COMPUTE
);
3413 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3416 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3417 dest
= get_nir_dest(instr
->dest
);
3419 switch (instr
->intrinsic
) {
3420 case nir_intrinsic_barrier
:
3422 cs_prog_data
->uses_barrier
= true;
3425 case nir_intrinsic_load_intel_thread_local_id
:
3426 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), thread_local_id
);
3429 case nir_intrinsic_load_local_invocation_id
:
3430 case nir_intrinsic_load_work_group_id
: {
3431 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3432 fs_reg val
= nir_system_values
[sv
];
3433 assert(val
.file
!= BAD_FILE
);
3434 dest
.type
= val
.type
;
3435 for (unsigned i
= 0; i
< 3; i
++)
3436 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3440 case nir_intrinsic_load_num_work_groups
: {
3441 const unsigned surface
=
3442 cs_prog_data
->binding_table
.work_groups_start
;
3444 cs_prog_data
->uses_num_work_groups
= true;
3446 fs_reg surf_index
= brw_imm_ud(surface
);
3447 brw_mark_surface_used(prog_data
, surface
);
3449 /* Read the 3 GLuint components of gl_NumWorkGroups */
3450 for (unsigned i
= 0; i
< 3; i
++) {
3451 fs_reg read_result
=
3452 emit_untyped_read(bld
, surf_index
,
3454 1 /* dims */, 1 /* size */,
3455 BRW_PREDICATE_NONE
);
3456 read_result
.type
= dest
.type
;
3457 bld
.MOV(dest
, read_result
);
3458 dest
= offset(dest
, bld
, 1);
3463 case nir_intrinsic_shared_atomic_add
:
3464 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3466 case nir_intrinsic_shared_atomic_imin
:
3467 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3469 case nir_intrinsic_shared_atomic_umin
:
3470 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3472 case nir_intrinsic_shared_atomic_imax
:
3473 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3475 case nir_intrinsic_shared_atomic_umax
:
3476 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3478 case nir_intrinsic_shared_atomic_and
:
3479 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3481 case nir_intrinsic_shared_atomic_or
:
3482 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3484 case nir_intrinsic_shared_atomic_xor
:
3485 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3487 case nir_intrinsic_shared_atomic_exchange
:
3488 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3490 case nir_intrinsic_shared_atomic_comp_swap
:
3491 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3494 case nir_intrinsic_load_shared
: {
3495 assert(devinfo
->gen
>= 7);
3497 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3499 /* Get the offset to read from */
3501 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3503 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3505 offset_reg
= vgrf(glsl_type::uint_type
);
3507 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3508 brw_imm_ud(instr
->const_index
[0]));
3511 /* Read the vector */
3512 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3513 instr
->num_components
);
3517 case nir_intrinsic_store_shared
: {
3518 assert(devinfo
->gen
>= 7);
3521 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3524 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3527 unsigned writemask
= instr
->const_index
[1];
3529 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3530 * since the untyped writes below operate in units of 32-bits, which
3531 * means that we need to write twice as many components each time.
3532 * Also, we have to suffle 64-bit data to be in the appropriate layout
3533 * expected by our 32-bit write messages.
3535 unsigned type_size
= 4;
3536 if (nir_src_bit_size(instr
->src
[0]) == 64) {
3538 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
3539 val_reg
, instr
->num_components
);
3542 unsigned type_slots
= type_size
/ 4;
3544 /* Combine groups of consecutive enabled channels in one write
3545 * message. We use ffs to find the first enabled channel and then ffs on
3546 * the bit-inverse, down-shifted writemask to determine the length of
3547 * the block of enabled bits.
3550 unsigned first_component
= ffs(writemask
) - 1;
3551 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3553 /* We can't write more than 2 64-bit components at once. Limit the
3554 * length of the write to what we can do and let the next iteration
3558 length
= MIN2(2, length
);
3561 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3563 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3564 type_size
* first_component
);
3566 offset_reg
= vgrf(glsl_type::uint_type
);
3568 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3569 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3572 emit_untyped_write(bld
, surf_index
, offset_reg
,
3573 offset(val_reg
, bld
, first_component
* type_slots
),
3574 1 /* dims */, length
* type_slots
,
3575 BRW_PREDICATE_NONE
);
3577 /* Clear the bits in the writemask that we just wrote, then try
3578 * again to see if more channels are left.
3580 writemask
&= (15 << (first_component
+ length
));
3587 nir_emit_intrinsic(bld
, instr
);
3593 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3596 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3597 dest
= get_nir_dest(instr
->dest
);
3599 switch (instr
->intrinsic
) {
3600 case nir_intrinsic_atomic_counter_inc
:
3601 case nir_intrinsic_atomic_counter_dec
:
3602 case nir_intrinsic_atomic_counter_read
:
3603 case nir_intrinsic_atomic_counter_add
:
3604 case nir_intrinsic_atomic_counter_min
:
3605 case nir_intrinsic_atomic_counter_max
:
3606 case nir_intrinsic_atomic_counter_and
:
3607 case nir_intrinsic_atomic_counter_or
:
3608 case nir_intrinsic_atomic_counter_xor
:
3609 case nir_intrinsic_atomic_counter_exchange
:
3610 case nir_intrinsic_atomic_counter_comp_swap
: {
3611 if (stage
== MESA_SHADER_FRAGMENT
&&
3612 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3613 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3615 /* Get some metadata from the image intrinsic. */
3616 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3618 /* Get the arguments of the atomic intrinsic. */
3619 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3620 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3621 instr
->const_index
[0]);
3622 const fs_reg src0
= (info
->num_srcs
>= 2
3623 ? get_nir_src(instr
->src
[1]) : fs_reg());
3624 const fs_reg src1
= (info
->num_srcs
>= 3
3625 ? get_nir_src(instr
->src
[2]) : fs_reg());
3628 assert(info
->num_srcs
<= 3);
3630 /* Emit a surface read or atomic op. */
3631 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3632 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3634 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3636 get_atomic_counter_op(instr
->intrinsic
));
3639 /* Assign the result. */
3640 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3642 /* Mark the surface as used. */
3643 brw_mark_surface_used(stage_prog_data
, surface
);
3647 case nir_intrinsic_image_load
:
3648 case nir_intrinsic_image_store
:
3649 case nir_intrinsic_image_atomic_add
:
3650 case nir_intrinsic_image_atomic_min
:
3651 case nir_intrinsic_image_atomic_max
:
3652 case nir_intrinsic_image_atomic_and
:
3653 case nir_intrinsic_image_atomic_or
:
3654 case nir_intrinsic_image_atomic_xor
:
3655 case nir_intrinsic_image_atomic_exchange
:
3656 case nir_intrinsic_image_atomic_comp_swap
: {
3657 using namespace image_access
;
3659 if (stage
== MESA_SHADER_FRAGMENT
&&
3660 instr
->intrinsic
!= nir_intrinsic_image_load
)
3661 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3663 /* Get the referenced image variable and type. */
3664 const nir_variable
*var
= instr
->variables
[0]->var
;
3665 const glsl_type
*type
= var
->type
->without_array();
3666 const brw_reg_type base_type
= get_image_base_type(type
);
3668 /* Get some metadata from the image intrinsic. */
3669 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3670 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3671 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3672 const unsigned format
= var
->data
.image
.format
;
3674 /* Get the arguments of the image intrinsic. */
3675 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3676 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3677 BRW_REGISTER_TYPE_UD
);
3678 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3679 retype(get_nir_src(instr
->src
[2]), base_type
) :
3681 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3682 retype(get_nir_src(instr
->src
[3]), base_type
) :
3686 /* Emit an image load, store or atomic op. */
3687 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3688 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3690 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3691 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3692 var
->data
.image
.write_only
? GL_NONE
: format
);
3695 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3696 surf_dims
, arr_dims
, info
->dest_components
,
3697 get_image_atomic_op(instr
->intrinsic
, type
));
3699 /* Assign the result. */
3700 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3701 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3702 offset(tmp
, bld
, c
));
3706 case nir_intrinsic_memory_barrier_atomic_counter
:
3707 case nir_intrinsic_memory_barrier_buffer
:
3708 case nir_intrinsic_memory_barrier_image
:
3709 case nir_intrinsic_memory_barrier
: {
3710 const fs_builder ubld
= bld
.group(8, 0);
3711 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3712 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3713 ->size_written
= 2 * REG_SIZE
;
3717 case nir_intrinsic_group_memory_barrier
:
3718 case nir_intrinsic_memory_barrier_shared
:
3719 /* We treat these workgroup-level barriers as no-ops. This should be
3720 * safe at present and as long as:
3722 * - Memory access instructions are not subsequently reordered by the
3723 * compiler back-end.
3725 * - All threads from a given compute shader workgroup fit within a
3726 * single subslice and therefore talk to the same HDC shared unit
3727 * what supposedly guarantees ordering and coherency between threads
3728 * from the same workgroup. This may change in the future when we
3729 * start splitting workgroups across multiple subslices.
3731 * - The context is not in fault-and-stream mode, which could cause
3732 * memory transactions (including to SLM) prior to the barrier to be
3733 * replayed after the barrier if a pagefault occurs. This shouldn't
3734 * be a problem up to and including SKL because fault-and-stream is
3735 * not usable due to hardware issues, but that's likely to change in
3740 case nir_intrinsic_shader_clock
: {
3741 /* We cannot do anything if there is an event, so ignore it for now */
3742 const fs_reg shader_clock
= get_timestamp(bld
);
3743 const fs_reg srcs
[] = { component(shader_clock
, 0),
3744 component(shader_clock
, 1) };
3745 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3749 case nir_intrinsic_image_size
: {
3750 /* Get the referenced image variable and type. */
3751 const nir_variable
*var
= instr
->variables
[0]->var
;
3752 const glsl_type
*type
= var
->type
->without_array();
3754 /* Get the size of the image. */
3755 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3756 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3758 /* For 1DArray image types, the array index is stored in the Z component.
3759 * Fix this by swizzling the Z component to the Y component.
3761 const bool is_1d_array_image
=
3762 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3763 type
->sampler_array
;
3765 /* For CubeArray images, we should count the number of cubes instead
3766 * of the number of faces. Fix it by dividing the (Z component) by 6.
3768 const bool is_cube_array_image
=
3769 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3770 type
->sampler_array
;
3772 /* Copy all the components. */
3773 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3774 if ((int)c
>= type
->coordinate_components()) {
3775 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3777 } else if (c
== 1 && is_1d_array_image
) {
3778 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3779 offset(size
, bld
, 2));
3780 } else if (c
== 2 && is_cube_array_image
) {
3781 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3782 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3783 offset(size
, bld
, c
), brw_imm_d(6));
3785 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3786 offset(size
, bld
, c
));
3793 case nir_intrinsic_image_samples
:
3794 /* The driver does not support multi-sampled images. */
3795 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3798 case nir_intrinsic_load_uniform
: {
3799 /* Offsets are in bytes but they should always be multiples of 4 */
3800 assert(instr
->const_index
[0] % 4 == 0);
3802 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3804 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3806 /* Offsets are in bytes but they should always be multiples of 4 */
3807 assert(const_offset
->u32
[0] % 4 == 0);
3808 src
.offset
= const_offset
->u32
[0];
3810 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3811 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3814 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3815 BRW_REGISTER_TYPE_UD
);
3817 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3818 * go past the end of the uniform. In order to keep the n'th
3819 * component from running past, we subtract off the size of all but
3820 * one component of the vector.
3822 assert(instr
->const_index
[1] >=
3823 instr
->num_components
* (int) type_sz(dest
.type
));
3824 unsigned read_size
= instr
->const_index
[1] -
3825 (instr
->num_components
- 1) * type_sz(dest
.type
);
3827 bool supports_64bit_indirects
=
3828 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
3830 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
3831 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3832 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3833 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3834 indirect
, brw_imm_ud(read_size
));
3837 const unsigned num_mov_indirects
=
3838 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
3839 /* We read a little bit less per MOV INDIRECT, as they are now
3840 * 32-bits ones instead of 64-bit. Fix read_size then.
3842 const unsigned read_size_32bit
= read_size
-
3843 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
3844 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3845 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
3846 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3847 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3848 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
3849 indirect
, brw_imm_ud(read_size_32bit
));
3857 case nir_intrinsic_load_ubo
: {
3858 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3862 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3863 const_index
->u32
[0];
3864 surf_index
= brw_imm_ud(index
);
3865 brw_mark_surface_used(prog_data
, index
);
3867 /* The block index is not a constant. Evaluate the index expression
3868 * per-channel and add the base UBO index; we have to select a value
3869 * from any live channel.
3871 surf_index
= vgrf(glsl_type::uint_type
);
3872 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3873 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3874 surf_index
= bld
.emit_uniformize(surf_index
);
3876 /* Assume this may touch any UBO. It would be nice to provide
3877 * a tighter bound, but the array information is already lowered away.
3879 brw_mark_surface_used(prog_data
,
3880 stage_prog_data
->binding_table
.ubo_start
+
3881 nir
->info
.num_ubos
- 1);
3884 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3885 if (const_offset
== NULL
) {
3886 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3887 BRW_REGISTER_TYPE_UD
);
3889 for (int i
= 0; i
< instr
->num_components
; i
++)
3890 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3891 base_offset
, i
* type_sz(dest
.type
));
3893 /* Even if we are loading doubles, a pull constant load will load
3894 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3895 * need to load a full dvec4 we will have to emit 2 loads. This is
3896 * similar to demote_pull_constants(), except that in that case we
3897 * see individual accesses to each component of the vector and then
3898 * we let CSE deal with duplicate loads. Here we see a vector access
3899 * and we have to split it if necessary.
3901 const unsigned type_size
= type_sz(dest
.type
);
3903 /* See if we've selected this as a push constant candidate */
3905 const unsigned ubo_block
= const_index
->u32
[0];
3906 const unsigned offset_256b
= const_offset
->u32
[0] / 32;
3909 for (int i
= 0; i
< 4; i
++) {
3910 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
3911 if (range
->block
== ubo_block
&&
3912 offset_256b
>= range
->start
&&
3913 offset_256b
< range
->start
+ range
->length
) {
3915 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
3916 push_reg
.offset
= const_offset
->u32
[0] - 32 * range
->start
;
3921 if (push_reg
.file
!= BAD_FILE
) {
3922 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3923 bld
.MOV(offset(dest
, bld
, i
),
3924 byte_offset(push_reg
, i
* type_size
));
3930 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3931 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3932 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3934 for (unsigned c
= 0; c
< instr
->num_components
;) {
3935 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3936 /* Number of usable components in the next block-aligned load. */
3937 const unsigned count
= MIN2(instr
->num_components
- c
,
3938 (block_sz
- base
% block_sz
) / type_size
);
3940 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3941 packed_consts
, surf_index
,
3942 brw_imm_ud(base
& ~(block_sz
- 1)));
3944 const fs_reg consts
=
3945 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3948 for (unsigned d
= 0; d
< count
; d
++)
3949 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3957 case nir_intrinsic_load_ssbo
: {
3958 assert(devinfo
->gen
>= 7);
3960 nir_const_value
*const_uniform_block
=
3961 nir_src_as_const_value(instr
->src
[0]);
3964 if (const_uniform_block
) {
3965 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3966 const_uniform_block
->u32
[0];
3967 surf_index
= brw_imm_ud(index
);
3968 brw_mark_surface_used(prog_data
, index
);
3970 surf_index
= vgrf(glsl_type::uint_type
);
3971 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3972 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3974 /* Assume this may touch any UBO. It would be nice to provide
3975 * a tighter bound, but the array information is already lowered away.
3977 brw_mark_surface_used(prog_data
,
3978 stage_prog_data
->binding_table
.ssbo_start
+
3979 nir
->info
.num_ssbos
- 1);
3983 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3985 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3987 offset_reg
= get_nir_src(instr
->src
[1]);
3990 /* Read the vector */
3991 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3992 instr
->num_components
);
3997 case nir_intrinsic_store_ssbo
: {
3998 assert(devinfo
->gen
>= 7);
4000 if (stage
== MESA_SHADER_FRAGMENT
)
4001 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4005 nir_const_value
*const_uniform_block
=
4006 nir_src_as_const_value(instr
->src
[1]);
4007 if (const_uniform_block
) {
4008 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4009 const_uniform_block
->u32
[0];
4010 surf_index
= brw_imm_ud(index
);
4011 brw_mark_surface_used(prog_data
, index
);
4013 surf_index
= vgrf(glsl_type::uint_type
);
4014 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4015 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4017 brw_mark_surface_used(prog_data
,
4018 stage_prog_data
->binding_table
.ssbo_start
+
4019 nir
->info
.num_ssbos
- 1);
4023 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4026 unsigned writemask
= instr
->const_index
[0];
4028 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4029 * since the untyped writes below operate in units of 32-bits, which
4030 * means that we need to write twice as many components each time.
4031 * Also, we have to suffle 64-bit data to be in the appropriate layout
4032 * expected by our 32-bit write messages.
4034 unsigned type_size
= 4;
4035 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4037 val_reg
= shuffle_64bit_data_for_32bit_write(bld
,
4038 val_reg
, instr
->num_components
);
4041 unsigned type_slots
= type_size
/ 4;
4043 /* Combine groups of consecutive enabled channels in one write
4044 * message. We use ffs to find the first enabled channel and then ffs on
4045 * the bit-inverse, down-shifted writemask to determine the length of
4046 * the block of enabled bits.
4049 unsigned first_component
= ffs(writemask
) - 1;
4050 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4052 /* We can't write more than 2 64-bit components at once. Limit the
4053 * length of the write to what we can do and let the next iteration
4057 length
= MIN2(2, length
);
4060 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4062 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4063 type_size
* first_component
);
4065 offset_reg
= vgrf(glsl_type::uint_type
);
4067 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4068 brw_imm_ud(type_size
* first_component
));
4072 emit_untyped_write(bld
, surf_index
, offset_reg
,
4073 offset(val_reg
, bld
, first_component
* type_slots
),
4074 1 /* dims */, length
* type_slots
,
4075 BRW_PREDICATE_NONE
);
4077 /* Clear the bits in the writemask that we just wrote, then try
4078 * again to see if more channels are left.
4080 writemask
&= (15 << (first_component
+ length
));
4085 case nir_intrinsic_store_output
: {
4086 fs_reg src
= get_nir_src(instr
->src
[0]);
4088 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4089 assert(const_offset
&& "Indirect output stores not allowed");
4091 unsigned num_components
= instr
->num_components
;
4092 unsigned first_component
= nir_intrinsic_component(instr
);
4093 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4094 src
= shuffle_64bit_data_for_32bit_write(bld
, src
, num_components
);
4095 num_components
*= 2;
4098 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4099 4 * const_offset
->u32
[0]), src
.type
);
4100 for (unsigned j
= 0; j
< num_components
; j
++) {
4101 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4102 offset(src
, bld
, j
));
4107 case nir_intrinsic_ssbo_atomic_add
:
4108 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4110 case nir_intrinsic_ssbo_atomic_imin
:
4111 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4113 case nir_intrinsic_ssbo_atomic_umin
:
4114 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4116 case nir_intrinsic_ssbo_atomic_imax
:
4117 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4119 case nir_intrinsic_ssbo_atomic_umax
:
4120 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4122 case nir_intrinsic_ssbo_atomic_and
:
4123 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4125 case nir_intrinsic_ssbo_atomic_or
:
4126 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4128 case nir_intrinsic_ssbo_atomic_xor
:
4129 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4131 case nir_intrinsic_ssbo_atomic_exchange
:
4132 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4134 case nir_intrinsic_ssbo_atomic_comp_swap
:
4135 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4138 case nir_intrinsic_get_buffer_size
: {
4139 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4140 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4142 /* A resinfo's sampler message is used to get the buffer size. The
4143 * SIMD8's writeback message consists of four registers and SIMD16's
4144 * writeback message consists of 8 destination registers (two per each
4145 * component). Because we are only interested on the first channel of
4146 * the first returned component, where resinfo returns the buffer size
4147 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4148 * the dispatch width.
4150 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4151 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4152 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4155 ubld
.MOV(src_payload
, brw_imm_d(0));
4157 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4158 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4159 src_payload
, brw_imm_ud(index
));
4160 inst
->header_size
= 0;
4162 inst
->size_written
= 4 * REG_SIZE
;
4164 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4165 brw_mark_surface_used(prog_data
, index
);
4169 case nir_intrinsic_load_subgroup_size
:
4170 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4173 case nir_intrinsic_load_subgroup_invocation
: {
4174 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4175 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4176 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4177 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4178 if (dispatch_width
> 8)
4179 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4180 if (dispatch_width
> 16) {
4181 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4182 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4188 case nir_intrinsic_load_subgroup_eq_mask
:
4189 case nir_intrinsic_load_subgroup_ge_mask
:
4190 case nir_intrinsic_load_subgroup_gt_mask
:
4191 case nir_intrinsic_load_subgroup_le_mask
:
4192 case nir_intrinsic_load_subgroup_lt_mask
:
4193 unreachable("not reached");
4195 case nir_intrinsic_vote_any
: {
4196 const fs_builder ubld
= bld
.exec_all();
4198 /* The any/all predicates do not consider channel enables. To prevent
4199 * dead channels from affecting the result, we initialize the flag with
4200 * with the identity value for the logical operation.
4202 if (dispatch_width
== 32) {
4203 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4204 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4207 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4209 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4211 /* For some reason, the any/all predicates don't work properly with
4212 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4213 * doesn't read the correct subset of the flag register and you end up
4214 * getting garbage in the second half. Work around this by using a pair
4215 * of 1-wide MOVs and scattering the result.
4217 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4218 ubld
.MOV(res1
, brw_imm_d(0));
4219 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4220 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4221 BRW_PREDICATE_ALIGN1_ANY32H
,
4222 ubld
.MOV(res1
, brw_imm_d(-1)));
4224 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4227 case nir_intrinsic_vote_all
: {
4228 const fs_builder ubld
= bld
.exec_all();
4230 /* The any/all predicates do not consider channel enables. To prevent
4231 * dead channels from affecting the result, we initialize the flag with
4232 * with the identity value for the logical operation.
4234 if (dispatch_width
== 32) {
4235 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4236 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4237 brw_imm_ud(0xffffffff));
4239 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4241 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4243 /* For some reason, the any/all predicates don't work properly with
4244 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4245 * doesn't read the correct subset of the flag register and you end up
4246 * getting garbage in the second half. Work around this by using a pair
4247 * of 1-wide MOVs and scattering the result.
4249 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4250 ubld
.MOV(res1
, brw_imm_d(0));
4251 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4252 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4253 BRW_PREDICATE_ALIGN1_ALL32H
,
4254 ubld
.MOV(res1
, brw_imm_d(-1)));
4256 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4259 case nir_intrinsic_vote_eq
: {
4260 fs_reg value
= get_nir_src(instr
->src
[0]);
4261 fs_reg uniformized
= bld
.emit_uniformize(value
);
4262 const fs_builder ubld
= bld
.exec_all();
4264 /* The any/all predicates do not consider channel enables. To prevent
4265 * dead channels from affecting the result, we initialize the flag with
4266 * with the identity value for the logical operation.
4268 if (dispatch_width
== 32) {
4269 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4270 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4271 brw_imm_ud(0xffffffff));
4273 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4275 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4277 /* For some reason, the any/all predicates don't work properly with
4278 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4279 * doesn't read the correct subset of the flag register and you end up
4280 * getting garbage in the second half. Work around this by using a pair
4281 * of 1-wide MOVs and scattering the result.
4283 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4284 ubld
.MOV(res1
, brw_imm_d(0));
4285 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4286 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4287 BRW_PREDICATE_ALIGN1_ALL32H
,
4288 ubld
.MOV(res1
, brw_imm_d(-1)));
4290 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4294 case nir_intrinsic_ballot
: {
4295 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4296 BRW_REGISTER_TYPE_UD
);
4297 struct brw_reg flag
= brw_flag_reg(0, 0);
4298 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4299 * as f0.0. This is a problem for fragment programs as we currently use
4300 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4301 * programs yet so this isn't a problem. When we do, something will
4304 if (dispatch_width
== 32)
4305 flag
.type
= BRW_REGISTER_TYPE_UD
;
4307 bld
.exec_all().MOV(flag
, brw_imm_ud(0u));
4308 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4310 if (instr
->dest
.ssa
.bit_size
> 32) {
4311 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4313 dest
.type
= BRW_REGISTER_TYPE_UD
;
4315 bld
.MOV(dest
, flag
);
4319 case nir_intrinsic_read_invocation
: {
4320 const fs_reg value
= get_nir_src(instr
->src
[0]);
4321 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4322 fs_reg tmp
= bld
.vgrf(value
.type
);
4324 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4325 bld
.emit_uniformize(invocation
));
4327 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4331 case nir_intrinsic_read_first_invocation
: {
4332 const fs_reg value
= get_nir_src(instr
->src
[0]);
4333 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4338 unreachable("unknown intrinsic");
4343 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4344 int op
, nir_intrinsic_instr
*instr
)
4346 if (stage
== MESA_SHADER_FRAGMENT
)
4347 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4350 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4351 dest
= get_nir_dest(instr
->dest
);
4354 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4355 if (const_surface
) {
4356 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4357 const_surface
->u32
[0];
4358 surface
= brw_imm_ud(surf_index
);
4359 brw_mark_surface_used(prog_data
, surf_index
);
4361 surface
= vgrf(glsl_type::uint_type
);
4362 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4363 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4365 /* Assume this may touch any SSBO. This is the same we do for other
4366 * UBO/SSBO accesses with non-constant surface.
4368 brw_mark_surface_used(prog_data
,
4369 stage_prog_data
->binding_table
.ssbo_start
+
4370 nir
->info
.num_ssbos
- 1);
4373 fs_reg offset
= get_nir_src(instr
->src
[1]);
4374 fs_reg data1
= get_nir_src(instr
->src
[2]);
4376 if (op
== BRW_AOP_CMPWR
)
4377 data2
= get_nir_src(instr
->src
[3]);
4379 /* Emit the actual atomic operation */
4381 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4383 1 /* dims */, 1 /* rsize */,
4385 BRW_PREDICATE_NONE
);
4386 dest
.type
= atomic_result
.type
;
4387 bld
.MOV(dest
, atomic_result
);
4391 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4392 int op
, nir_intrinsic_instr
*instr
)
4395 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4396 dest
= get_nir_dest(instr
->dest
);
4398 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4400 fs_reg data1
= get_nir_src(instr
->src
[1]);
4402 if (op
== BRW_AOP_CMPWR
)
4403 data2
= get_nir_src(instr
->src
[2]);
4405 /* Get the offset */
4406 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4408 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4410 offset
= vgrf(glsl_type::uint_type
);
4412 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4413 brw_imm_ud(instr
->const_index
[0]));
4416 /* Emit the actual atomic operation operation */
4418 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4420 1 /* dims */, 1 /* rsize */,
4422 BRW_PREDICATE_NONE
);
4423 dest
.type
= atomic_result
.type
;
4424 bld
.MOV(dest
, atomic_result
);
4428 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4430 unsigned texture
= instr
->texture_index
;
4431 unsigned sampler
= instr
->sampler_index
;
4433 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4435 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4436 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4438 int lod_components
= 0;
4440 /* The hardware requires a LOD for buffer textures */
4441 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4442 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4444 uint32_t header_bits
= 0;
4445 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4446 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4447 switch (instr
->src
[i
].src_type
) {
4448 case nir_tex_src_bias
:
4449 srcs
[TEX_LOGICAL_SRC_LOD
] =
4450 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4452 case nir_tex_src_comparator
:
4453 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4455 case nir_tex_src_coord
:
4456 switch (instr
->op
) {
4458 case nir_texop_txf_ms
:
4459 case nir_texop_txf_ms_mcs
:
4460 case nir_texop_samples_identical
:
4461 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4464 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4468 case nir_tex_src_ddx
:
4469 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4470 lod_components
= nir_tex_instr_src_size(instr
, i
);
4472 case nir_tex_src_ddy
:
4473 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4475 case nir_tex_src_lod
:
4476 switch (instr
->op
) {
4478 srcs
[TEX_LOGICAL_SRC_LOD
] =
4479 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4482 srcs
[TEX_LOGICAL_SRC_LOD
] =
4483 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4486 srcs
[TEX_LOGICAL_SRC_LOD
] =
4487 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4491 case nir_tex_src_ms_index
:
4492 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4495 case nir_tex_src_offset
: {
4496 nir_const_value
*const_offset
=
4497 nir_src_as_const_value(instr
->src
[i
].src
);
4498 unsigned offset_bits
= 0;
4500 brw_texture_offset(const_offset
->i32
,
4501 nir_tex_instr_src_size(instr
, i
),
4503 header_bits
|= offset_bits
;
4505 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4506 retype(src
, BRW_REGISTER_TYPE_D
);
4511 case nir_tex_src_projector
:
4512 unreachable("should be lowered");
4514 case nir_tex_src_texture_offset
: {
4515 /* Figure out the highest possible texture index and mark it as used */
4516 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4517 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4518 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4520 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4522 brw_mark_surface_used(prog_data
, max_used
);
4524 /* Emit code to evaluate the actual indexing expression */
4525 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4526 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4527 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4531 case nir_tex_src_sampler_offset
: {
4532 /* Emit code to evaluate the actual indexing expression */
4533 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4534 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4535 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4539 case nir_tex_src_ms_mcs
:
4540 assert(instr
->op
== nir_texop_txf_ms
);
4541 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4544 case nir_tex_src_plane
: {
4545 nir_const_value
*const_plane
=
4546 nir_src_as_const_value(instr
->src
[i
].src
);
4547 const uint32_t plane
= const_plane
->u32
[0];
4548 const uint32_t texture_index
=
4549 instr
->texture_index
+
4550 stage_prog_data
->binding_table
.plane_start
[plane
] -
4551 stage_prog_data
->binding_table
.texture_start
;
4553 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4558 unreachable("unknown texture source");
4562 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4563 (instr
->op
== nir_texop_txf_ms
||
4564 instr
->op
== nir_texop_samples_identical
)) {
4565 if (devinfo
->gen
>= 7 &&
4566 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4567 srcs
[TEX_LOGICAL_SRC_MCS
] =
4568 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4569 instr
->coord_components
,
4570 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4572 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4576 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4577 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4580 switch (instr
->op
) {
4582 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4583 SHADER_OPCODE_TXL_LOGICAL
);
4586 opcode
= FS_OPCODE_TXB_LOGICAL
;
4589 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4592 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4595 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4597 case nir_texop_txf_ms
:
4598 if ((key_tex
->msaa_16
& (1 << sampler
)))
4599 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4601 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4603 case nir_texop_txf_ms_mcs
:
4604 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4606 case nir_texop_query_levels
:
4608 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4611 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4614 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4615 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4617 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4619 case nir_texop_texture_samples
:
4620 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4622 case nir_texop_samples_identical
: {
4623 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4625 /* If mcs is an immediate value, it means there is no MCS. In that case
4626 * just return false.
4628 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4629 bld
.MOV(dst
, brw_imm_ud(0u));
4630 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4631 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4632 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4633 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4634 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4636 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4637 BRW_CONDITIONAL_EQ
);
4642 unreachable("unknown texture opcode");
4645 if (instr
->op
== nir_texop_tg4
) {
4646 if (instr
->component
== 1 &&
4647 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4648 /* gather4 sampler is broken for green channel on RG32F --
4649 * we must ask for blue instead.
4651 header_bits
|= 2 << 16;
4653 header_bits
|= instr
->component
<< 16;
4657 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
4658 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4659 inst
->offset
= header_bits
;
4661 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4662 if (devinfo
->gen
>= 9 &&
4663 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4664 unsigned write_mask
= instr
->dest
.is_ssa
?
4665 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4666 (1 << dest_size
) - 1;
4667 assert(write_mask
!= 0); /* dead code should have been eliminated */
4668 inst
->size_written
= util_last_bit(write_mask
) *
4669 inst
->dst
.component_size(inst
->exec_size
);
4671 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4674 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4675 inst
->shadow_compare
= true;
4677 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4678 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4681 for (unsigned i
= 0; i
< dest_size
; i
++)
4682 nir_dest
[i
] = offset(dst
, bld
, i
);
4684 if (instr
->op
== nir_texop_query_levels
) {
4685 /* # levels is in .w */
4686 nir_dest
[0] = offset(dst
, bld
, 3);
4687 } else if (instr
->op
== nir_texop_txs
&&
4688 dest_size
>= 3 && devinfo
->gen
< 7) {
4689 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4690 fs_reg depth
= offset(dst
, bld
, 2);
4691 nir_dest
[2] = vgrf(glsl_type::int_type
);
4692 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4695 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4699 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4701 switch (instr
->type
) {
4702 case nir_jump_break
:
4703 bld
.emit(BRW_OPCODE_BREAK
);
4705 case nir_jump_continue
:
4706 bld
.emit(BRW_OPCODE_CONTINUE
);
4708 case nir_jump_return
:
4710 unreachable("unknown jump");
4715 * This helper takes the result of a load operation that reads 32-bit elements
4723 * and shuffles the data to get this:
4730 * Which is exactly what we want if the load is reading 64-bit components
4731 * like doubles, where x represents the low 32-bit of the x double component
4732 * and y represents the high 32-bit of the x double component (likewise with
4733 * z and w for double component y). The parameter @components represents
4734 * the number of 64-bit components present in @src. This would typically be
4735 * 2 at most, since we can only fit 2 double elements in the result of a
4738 * Notice that @dst and @src can be the same register.
4741 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4744 uint32_t components
)
4746 assert(type_sz(src
.type
) == 4);
4747 assert(type_sz(dst
.type
) == 8);
4749 /* A temporary that we will use to shuffle the 32-bit data of each
4750 * component in the vector into valid 64-bit data. We can't write directly
4751 * to dst because dst can be (and would usually be) the same as src
4752 * and in that case the first MOV in the loop below would overwrite the
4753 * data read in the second MOV.
4755 fs_reg tmp
= bld
.vgrf(dst
.type
);
4757 for (unsigned i
= 0; i
< components
; i
++) {
4758 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4760 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4761 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4763 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4768 * This helper does the inverse operation of
4769 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4771 * We need to do this when we are going to use untyped write messsages that
4772 * operate with 32-bit components in order to arrange our 64-bit data to be
4773 * in the expected layout.
4775 * Notice that callers of this function, unlike in the case of the inverse
4776 * operation, would typically need to call this with dst and src being
4777 * different registers, since they would otherwise corrupt the original
4778 * 64-bit data they are about to write. Because of this the function checks
4779 * that the src and dst regions involved in the operation do not overlap.
4782 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4784 uint32_t components
)
4786 assert(type_sz(src
.type
) == 8);
4788 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 2 * components
);
4790 for (unsigned i
= 0; i
< components
; i
++) {
4791 const fs_reg component_i
= offset(src
, bld
, i
);
4792 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4793 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4800 setup_imm_df(const fs_builder
&bld
, double v
)
4802 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4803 assert(devinfo
->gen
>= 7);
4805 if (devinfo
->gen
>= 8)
4806 return brw_imm_df(v
);
4808 /* gen7.5 does not support DF immediates straighforward but the DIM
4809 * instruction allows to set the 64-bit immediate value.
4811 if (devinfo
->is_haswell
) {
4812 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4813 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4814 ubld
.DIM(dst
, brw_imm_df(v
));
4815 return component(dst
, 0);
4818 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4819 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4820 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4822 * Alternatively, we could also produce a normal VGRF (without stride 0)
4823 * by writing to all the channels in the VGRF, however, that would hit the
4824 * gen7 bug where we have to split writes that span more than 1 register
4825 * into instructions with a width of 4 (otherwise the write to the second
4826 * register written runs into an execmask hardware bug) which isn't very
4839 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4840 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4841 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4842 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4844 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);