2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
27 #include "util/u_math.h"
28 #include "util/bitscan.h"
33 fs_visitor::emit_nir_code()
35 /* emit the arrays used for inputs and outputs - load/store intrinsics will
36 * be converted to reads/writes of these arrays
40 nir_emit_system_values();
42 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
46 fs_visitor::nir_setup_outputs()
48 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
51 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
53 /* Calculate the size of output registers in a separate pass, before
54 * allocating them. With ARB_enhanced_layouts, multiple output variables
55 * may occupy the same slot, but have different type sizes.
57 nir_foreach_variable(var
, &nir
->outputs
) {
58 const int loc
= var
->data
.driver_location
;
59 const unsigned var_vec4s
=
60 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
61 : type_size_vec4(var
->type
, true);
62 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
65 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
66 if (vec4s
[loc
] == 0) {
71 unsigned reg_size
= vec4s
[loc
];
73 /* Check if there are any ranges that start within this range and extend
74 * past it. If so, include them in this allocation.
76 for (unsigned i
= 1; i
< reg_size
; i
++)
77 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
79 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
80 for (unsigned i
= 0; i
< reg_size
; i
++)
81 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
88 fs_visitor::nir_setup_uniforms()
90 /* Only the first compile gets to set up uniforms. */
91 if (push_constant_loc
) {
92 assert(pull_constant_loc
);
96 uniforms
= nir
->num_uniforms
/ 4;
98 if (stage
== MESA_SHADER_COMPUTE
) {
99 /* Add a uniform for the thread local id. It must be the last uniform
102 assert(uniforms
== prog_data
->nr_params
);
103 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
104 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
105 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
110 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
114 nir_foreach_instr(instr
, block
) {
115 if (instr
->type
!= nir_instr_type_intrinsic
)
118 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
119 switch (intrin
->intrinsic
) {
120 case nir_intrinsic_load_vertex_id
:
121 case nir_intrinsic_load_base_vertex
:
122 unreachable("should be lowered by nir_lower_system_values().");
124 case nir_intrinsic_load_vertex_id_zero_base
:
125 case nir_intrinsic_load_is_indexed_draw
:
126 case nir_intrinsic_load_first_vertex
:
127 case nir_intrinsic_load_instance_id
:
128 case nir_intrinsic_load_base_instance
:
129 case nir_intrinsic_load_draw_id
:
130 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
132 case nir_intrinsic_load_invocation_id
:
133 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
135 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
136 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
137 if (reg
->file
== BAD_FILE
) {
138 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
139 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
140 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
141 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
146 case nir_intrinsic_load_sample_pos
:
147 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
148 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
149 if (reg
->file
== BAD_FILE
)
150 *reg
= *v
->emit_samplepos_setup();
153 case nir_intrinsic_load_sample_id
:
154 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
155 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
156 if (reg
->file
== BAD_FILE
)
157 *reg
= *v
->emit_sampleid_setup();
160 case nir_intrinsic_load_sample_mask_in
:
161 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
162 assert(v
->devinfo
->gen
>= 7);
163 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
164 if (reg
->file
== BAD_FILE
)
165 *reg
= *v
->emit_samplemaskin_setup();
168 case nir_intrinsic_load_work_group_id
:
169 assert(v
->stage
== MESA_SHADER_COMPUTE
);
170 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
171 if (reg
->file
== BAD_FILE
)
172 *reg
= *v
->emit_cs_work_group_id_setup();
175 case nir_intrinsic_load_helper_invocation
:
176 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
177 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
178 if (reg
->file
== BAD_FILE
) {
179 const fs_builder abld
=
180 v
->bld
.annotate("gl_HelperInvocation", NULL
);
182 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
183 * pixel mask is in g1.7 of the thread payload.
185 * We move the per-channel pixel enable bit to the low bit of each
186 * channel by shifting the byte containing the pixel mask by the
187 * vector immediate 0x76543210UV.
189 * The region of <1,8,0> reads only 1 byte (the pixel masks for
190 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
191 * masks for 2 and 3) in SIMD16.
193 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
195 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
196 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
197 hbld
.SHR(offset(shifted
, hbld
, i
),
198 stride(retype(brw_vec1_grf(1 + i
, 7),
199 BRW_REGISTER_TYPE_UB
),
201 brw_imm_v(0x76543210));
204 /* A set bit in the pixel mask means the channel is enabled, but
205 * that is the opposite of gl_HelperInvocation so we need to invert
208 * The negate source-modifier bit of logical instructions on Gen8+
209 * performs 1's complement negation, so we can use that instead of
212 fs_reg inverted
= negate(shifted
);
213 if (v
->devinfo
->gen
< 8) {
214 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
215 abld
.NOT(inverted
, shifted
);
218 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
219 * with 1 and negating.
221 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
222 abld
.AND(anded
, inverted
, brw_imm_uw(1));
224 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
225 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
239 fs_visitor::nir_emit_system_values()
241 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
242 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
243 nir_system_values
[i
] = fs_reg();
246 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
247 * never end up using it.
250 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
251 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
252 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
254 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
255 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
256 if (dispatch_width
> 8)
257 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
258 if (dispatch_width
> 16) {
259 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
260 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
264 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
265 nir_foreach_block(block
, impl
)
266 emit_system_values_block(block
, this);
270 * Returns a type based on a reference_type (word, float, half-float) and a
273 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
275 * @FIXME: 64-bit return types are always DF on integer types to maintain
276 * compability with uses of DF previously to the introduction of int64
280 brw_reg_type_from_bit_size(const unsigned bit_size
,
281 const brw_reg_type reference_type
)
283 switch(reference_type
) {
284 case BRW_REGISTER_TYPE_HF
:
285 case BRW_REGISTER_TYPE_F
:
286 case BRW_REGISTER_TYPE_DF
:
289 return BRW_REGISTER_TYPE_HF
;
291 return BRW_REGISTER_TYPE_F
;
293 return BRW_REGISTER_TYPE_DF
;
295 unreachable("Invalid bit size");
297 case BRW_REGISTER_TYPE_B
:
298 case BRW_REGISTER_TYPE_W
:
299 case BRW_REGISTER_TYPE_D
:
300 case BRW_REGISTER_TYPE_Q
:
303 return BRW_REGISTER_TYPE_B
;
305 return BRW_REGISTER_TYPE_W
;
307 return BRW_REGISTER_TYPE_D
;
309 return BRW_REGISTER_TYPE_Q
;
311 unreachable("Invalid bit size");
313 case BRW_REGISTER_TYPE_UB
:
314 case BRW_REGISTER_TYPE_UW
:
315 case BRW_REGISTER_TYPE_UD
:
316 case BRW_REGISTER_TYPE_UQ
:
319 return BRW_REGISTER_TYPE_UB
;
321 return BRW_REGISTER_TYPE_UW
;
323 return BRW_REGISTER_TYPE_UD
;
325 return BRW_REGISTER_TYPE_UQ
;
327 unreachable("Invalid bit size");
330 unreachable("Unknown type");
335 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
337 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
338 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
339 nir_locals
[i
] = fs_reg();
342 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
343 unsigned array_elems
=
344 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
345 unsigned size
= array_elems
* reg
->num_components
;
346 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
347 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
348 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
351 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
354 nir_emit_cf_list(&impl
->body
);
358 fs_visitor::nir_emit_cf_list(exec_list
*list
)
360 exec_list_validate(list
);
361 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
362 switch (node
->type
) {
364 nir_emit_if(nir_cf_node_as_if(node
));
367 case nir_cf_node_loop
:
368 nir_emit_loop(nir_cf_node_as_loop(node
));
371 case nir_cf_node_block
:
372 nir_emit_block(nir_cf_node_as_block(node
));
376 unreachable("Invalid CFG node block");
382 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
387 /* If the condition has the form !other_condition, use other_condition as
388 * the source, but invert the predicate on the if instruction.
390 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
391 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
392 assert(!cond
->src
[0].negate
);
393 assert(!cond
->src
[0].abs
);
396 cond_reg
= get_nir_src(cond
->src
[0].src
);
399 cond_reg
= get_nir_src(if_stmt
->condition
);
402 /* first, put the condition into f0 */
403 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
404 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
405 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
407 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
409 nir_emit_cf_list(&if_stmt
->then_list
);
411 /* note: if the else is empty, dead CF elimination will remove it */
412 bld
.emit(BRW_OPCODE_ELSE
);
414 nir_emit_cf_list(&if_stmt
->else_list
);
416 bld
.emit(BRW_OPCODE_ENDIF
);
418 if (devinfo
->gen
< 7)
419 limit_dispatch_width(16, "Non-uniform control flow unsupported "
424 fs_visitor::nir_emit_loop(nir_loop
*loop
)
426 bld
.emit(BRW_OPCODE_DO
);
428 nir_emit_cf_list(&loop
->body
);
430 bld
.emit(BRW_OPCODE_WHILE
);
432 if (devinfo
->gen
< 7)
433 limit_dispatch_width(16, "Non-uniform control flow unsupported "
438 fs_visitor::nir_emit_block(nir_block
*block
)
440 nir_foreach_instr(instr
, block
) {
441 nir_emit_instr(instr
);
446 fs_visitor::nir_emit_instr(nir_instr
*instr
)
448 const fs_builder abld
= bld
.annotate(NULL
, instr
);
450 switch (instr
->type
) {
451 case nir_instr_type_alu
:
452 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
455 case nir_instr_type_deref
:
456 /* Derefs can exist for images but they do nothing */
459 case nir_instr_type_intrinsic
:
461 case MESA_SHADER_VERTEX
:
462 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
464 case MESA_SHADER_TESS_CTRL
:
465 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
467 case MESA_SHADER_TESS_EVAL
:
468 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
470 case MESA_SHADER_GEOMETRY
:
471 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
473 case MESA_SHADER_FRAGMENT
:
474 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
476 case MESA_SHADER_COMPUTE
:
477 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
480 unreachable("unsupported shader stage");
484 case nir_instr_type_tex
:
485 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
488 case nir_instr_type_load_const
:
489 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
492 case nir_instr_type_ssa_undef
:
493 /* We create a new VGRF for undefs on every use (by handling
494 * them in get_nir_src()), rather than for each definition.
495 * This helps register coalescing eliminate MOVs from undef.
499 case nir_instr_type_jump
:
500 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
504 unreachable("unknown instruction type");
509 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
513 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
514 const fs_reg
&result
)
516 if (!instr
->src
[0].src
.is_ssa
||
517 !instr
->src
[0].src
.ssa
->parent_instr
)
520 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
523 nir_alu_instr
*src0
=
524 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
526 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
527 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
530 /* If either opcode has source modifiers, bail.
532 * TODO: We can potentially handle source modifiers if both of the opcodes
533 * we're combining are signed integers.
535 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
536 src0
->src
[0].abs
|| src0
->src
[0].negate
)
539 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
541 /* Element type to extract.*/
542 const brw_reg_type type
= brw_int_type(
543 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
544 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
546 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
547 op0
.type
= brw_type_for_nir_type(devinfo
,
548 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
549 nir_src_bit_size(src0
->src
[0].src
)));
550 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
552 set_saturate(instr
->dest
.saturate
,
553 bld
.MOV(result
, subscript(op0
, type
, element
)));
558 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
559 const fs_reg
&result
)
561 if (!instr
->src
[0].src
.is_ssa
||
562 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
565 nir_intrinsic_instr
*src0
=
566 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
568 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
571 if (!nir_src_is_const(instr
->src
[1].src
) ||
572 !nir_src_is_const(instr
->src
[2].src
))
575 const float value1
= nir_src_as_float(instr
->src
[1].src
);
576 const float value2
= nir_src_as_float(instr
->src
[2].src
);
577 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
580 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
581 assert(value1
== -value2
);
583 fs_reg tmp
= vgrf(glsl_type::int_type
);
585 if (devinfo
->gen
>= 6) {
586 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
587 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
589 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
591 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
592 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
594 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
596 * This negation looks like it's safe in practice, because bits 0:4 will
597 * surely be TRIANGLES
600 if (value1
== -1.0f
) {
604 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
605 g0
, brw_imm_uw(0x3f80));
607 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
608 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
610 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
612 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
613 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
615 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
617 * This negation looks like it's safe in practice, because bits 0:4 will
618 * surely be TRIANGLES
621 if (value1
== -1.0f
) {
625 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
627 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
633 emit_find_msb_using_lzd(const fs_builder
&bld
,
634 const fs_reg
&result
,
642 /* LZD of an absolute value source almost always does the right
643 * thing. There are two problem values:
645 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
646 * 0. However, findMSB(int(0x80000000)) == 30.
648 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
649 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
651 * For a value of zero or negative one, -1 will be returned.
653 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
654 * findMSB(-(1<<x)) should return x-1.
656 * For all negative number cases, including 0x80000000 and
657 * 0xffffffff, the correct value is obtained from LZD if instead of
658 * negating the (already negative) value the logical-not is used. A
659 * conditonal logical-not can be achieved in two instructions.
661 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
663 bld
.ASR(temp
, src
, brw_imm_d(31));
664 bld
.XOR(temp
, temp
, src
);
667 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
668 retype(temp
, BRW_REGISTER_TYPE_UD
));
670 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
671 * from the LSB side. Subtract the result from 31 to convert the MSB
672 * count into an LSB count. If no bits are set, LZD will return 32.
673 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
675 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
676 inst
->src
[0].negate
= true;
680 brw_rnd_mode_from_nir_op (const nir_op op
) {
682 case nir_op_f2f16_rtz
:
683 return BRW_RND_MODE_RTZ
;
684 case nir_op_f2f16_rtne
:
685 return BRW_RND_MODE_RTNE
;
687 unreachable("Operation doesn't support rounding mode");
692 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
693 nir_alu_instr
*instr
,
698 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
700 result
.type
= brw_type_for_nir_type(devinfo
,
701 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
702 nir_dest_bit_size(instr
->dest
.dest
)));
704 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
705 op
[i
] = get_nir_src(instr
->src
[i
].src
);
706 op
[i
].type
= brw_type_for_nir_type(devinfo
,
707 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
708 nir_src_bit_size(instr
->src
[i
].src
)));
709 op
[i
].abs
= instr
->src
[i
].abs
;
710 op
[i
].negate
= instr
->src
[i
].negate
;
713 /* Move and vecN instrutions may still be vectored. Return the raw,
714 * vectored source and destination so that fs_visitor::nir_emit_alu can
715 * handle it. Other callers should not have to handle these kinds of
729 /* At this point, we have dealt with any instruction that operates on
730 * more than a single channel. Therefore, we can just adjust the source
731 * and destination registers for that channel and emit the instruction.
733 unsigned channel
= 0;
734 if (nir_op_infos
[instr
->op
].output_size
== 0) {
735 /* Since NIR is doing the scalarizing for us, we should only ever see
736 * vectorized operations with a single channel.
738 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
739 channel
= ffs(instr
->dest
.write_mask
) - 1;
741 result
= offset(result
, bld
, channel
);
744 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
745 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
746 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
753 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
756 for (unsigned i
= 0; i
< 2; i
++) {
757 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
759 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
760 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
761 /* The source of the inot is now the source of instr. */
762 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
764 assert(!op
[i
].negate
);
767 op
[i
] = resolve_source_modifiers(op
[i
]);
773 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
775 nir_alu_instr
*instr
)
777 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
780 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
782 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
785 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
786 * of valid size-changing combinations is a bit more complex.
788 * The source restriction is just because I was lazy about generating the
791 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
792 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
795 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
796 * this is float(1 + a).
800 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
802 /* Ignore the saturate modifier, if there is one. The result of the
803 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
805 bld
.ADD(result
, op
, brw_imm_d(1));
811 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
813 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
817 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, true);
825 fs_reg temp
= result
;
826 bool need_extra_copy
= false;
827 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
828 if (!instr
->src
[i
].src
.is_ssa
&&
829 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
830 need_extra_copy
= true;
831 temp
= bld
.vgrf(result
.type
, 4);
836 for (unsigned i
= 0; i
< 4; i
++) {
837 if (!(instr
->dest
.write_mask
& (1 << i
)))
840 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
841 inst
= bld
.MOV(offset(temp
, bld
, i
),
842 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
844 inst
= bld
.MOV(offset(temp
, bld
, i
),
845 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
847 inst
->saturate
= instr
->dest
.saturate
;
850 /* In this case the source and destination registers were the same,
851 * so we need to insert an extra set of moves in order to deal with
854 if (need_extra_copy
) {
855 for (unsigned i
= 0; i
< 4; i
++) {
856 if (!(instr
->dest
.write_mask
& (1 << i
)))
859 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
867 if (optimize_extract_to_float(instr
, result
))
869 inst
= bld
.MOV(result
, op
[0]);
870 inst
->saturate
= instr
->dest
.saturate
;
873 case nir_op_f2f16_rtne
:
874 case nir_op_f2f16_rtz
:
875 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
876 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
879 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
880 * on the HW gen, it is a special hw opcode or just a MOV, and
881 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
883 * But if we want to use that opcode, we need to provide support on
884 * different optimizations and lowerings. As right now HF support is
885 * only for gen8+, it will be better to use directly the MOV, and use
886 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
888 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
889 inst
= bld
.MOV(result
, op
[0]);
890 inst
->saturate
= instr
->dest
.saturate
;
900 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
902 op
[0].type
= BRW_REGISTER_TYPE_D
;
903 op
[0].negate
= !op
[0].negate
;
927 if (result
.type
== BRW_REGISTER_TYPE_B
||
928 result
.type
== BRW_REGISTER_TYPE_UB
||
929 result
.type
== BRW_REGISTER_TYPE_HF
)
930 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
932 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
933 op
[0].type
== BRW_REGISTER_TYPE_UB
||
934 op
[0].type
== BRW_REGISTER_TYPE_HF
)
935 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
937 inst
= bld
.MOV(result
, op
[0]);
938 inst
->saturate
= instr
->dest
.saturate
;
942 assert(!instr
->dest
.saturate
);
944 /* Straightforward since the source can be assumed to be either
945 * strictly >= 0 or strictly <= 0 depending on the setting of the
948 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
950 inst
= (op
[0].negate
)
951 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
952 : bld
.MOV(result
, brw_imm_f(1.0f
));
954 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
955 } else if (type_sz(op
[0].type
) == 2) {
956 /* AND(val, 0x8000) gives the sign bit.
958 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
960 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
961 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
963 op
[0].type
= BRW_REGISTER_TYPE_UW
;
964 result
.type
= BRW_REGISTER_TYPE_UW
;
965 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
967 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
968 inst
->predicate
= BRW_PREDICATE_NORMAL
;
969 } else if (type_sz(op
[0].type
) == 4) {
970 /* AND(val, 0x80000000) gives the sign bit.
972 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
975 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
977 op
[0].type
= BRW_REGISTER_TYPE_UD
;
978 result
.type
= BRW_REGISTER_TYPE_UD
;
979 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
981 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
982 inst
->predicate
= BRW_PREDICATE_NORMAL
;
984 /* For doubles we do the same but we need to consider:
986 * - 2-src instructions can't operate with 64-bit immediates
987 * - The sign is encoded in the high 32-bit of each DF
988 * - We need to produce a DF result.
990 assert(type_sz(op
[0].type
) == 8);
992 fs_reg zero
= vgrf(glsl_type::double_type
);
993 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
994 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
996 bld
.MOV(result
, zero
);
998 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
999 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
1000 brw_imm_ud(0x80000000u
));
1002 set_predicate(BRW_PREDICATE_NORMAL
,
1003 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
1009 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1010 inst
->saturate
= instr
->dest
.saturate
;
1014 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1015 inst
->saturate
= instr
->dest
.saturate
;
1019 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1020 inst
->saturate
= instr
->dest
.saturate
;
1024 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1025 inst
->saturate
= instr
->dest
.saturate
;
1029 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1030 inst
->saturate
= instr
->dest
.saturate
;
1034 if (fs_key
->high_quality_derivatives
) {
1035 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1037 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1039 inst
->saturate
= instr
->dest
.saturate
;
1041 case nir_op_fddx_fine
:
1042 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1043 inst
->saturate
= instr
->dest
.saturate
;
1045 case nir_op_fddx_coarse
:
1046 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1047 inst
->saturate
= instr
->dest
.saturate
;
1050 if (fs_key
->high_quality_derivatives
) {
1051 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1053 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1055 inst
->saturate
= instr
->dest
.saturate
;
1057 case nir_op_fddy_fine
:
1058 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1059 inst
->saturate
= instr
->dest
.saturate
;
1061 case nir_op_fddy_coarse
:
1062 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1063 inst
->saturate
= instr
->dest
.saturate
;
1068 inst
= bld
.ADD(result
, op
[0], op
[1]);
1069 inst
->saturate
= instr
->dest
.saturate
;
1072 case nir_op_uadd_sat
:
1073 inst
= bld
.ADD(result
, op
[0], op
[1]);
1074 inst
->saturate
= true;
1078 inst
= bld
.MUL(result
, op
[0], op
[1]);
1079 inst
->saturate
= instr
->dest
.saturate
;
1082 case nir_op_imul_2x32_64
:
1083 case nir_op_umul_2x32_64
:
1084 bld
.MUL(result
, op
[0], op
[1]);
1088 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1089 bld
.MUL(result
, op
[0], op
[1]);
1092 case nir_op_imul_high
:
1093 case nir_op_umul_high
:
1094 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1095 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1100 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1101 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1104 case nir_op_uadd_carry
:
1105 unreachable("Should have been lowered by carry_to_arith().");
1107 case nir_op_usub_borrow
:
1108 unreachable("Should have been lowered by borrow_to_arith().");
1112 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1113 * appears that our hardware just does the right thing for signed
1116 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1117 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1121 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1122 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1124 /* Math instructions don't support conditional mod */
1125 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1126 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1128 /* Now, we need to determine if signs of the sources are different.
1129 * When we XOR the sources, the top bit is 0 if they are the same and 1
1130 * if they are different. We can then use a conditional modifier to
1131 * turn that into a predicate. This leads us to an XOR.l instruction.
1133 * Technically, according to the PRM, you're not allowed to use .l on a
1134 * XOR instruction. However, emperical experiments and Curro's reading
1135 * of the simulator source both indicate that it's safe.
1137 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1138 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1139 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1140 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1142 /* If the result of the initial remainder operation is non-zero and the
1143 * two sources have different signs, add in a copy of op[1] to get the
1144 * final integer modulus value.
1146 inst
= bld
.ADD(result
, result
, op
[1]);
1147 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1154 case nir_op_fne32
: {
1155 fs_reg dest
= result
;
1157 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1159 dest
= bld
.vgrf(op
[0].type
, 1);
1161 brw_conditional_mod cond
;
1162 switch (instr
->op
) {
1164 cond
= BRW_CONDITIONAL_L
;
1167 cond
= BRW_CONDITIONAL_GE
;
1170 cond
= BRW_CONDITIONAL_Z
;
1173 cond
= BRW_CONDITIONAL_NZ
;
1176 unreachable("bad opcode");
1179 bld
.CMP(dest
, op
[0], op
[1], cond
);
1181 if (bit_size
> 32) {
1182 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1183 } else if(bit_size
< 32) {
1184 /* When we convert the result to 32-bit we need to be careful and do
1185 * it as a signed conversion to get sign extension (for 32-bit true)
1187 const brw_reg_type src_type
=
1188 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1190 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1200 case nir_op_ine32
: {
1201 fs_reg dest
= result
;
1203 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1205 dest
= bld
.vgrf(op
[0].type
, 1);
1207 brw_conditional_mod cond
;
1208 switch (instr
->op
) {
1211 cond
= BRW_CONDITIONAL_L
;
1215 cond
= BRW_CONDITIONAL_GE
;
1218 cond
= BRW_CONDITIONAL_Z
;
1221 cond
= BRW_CONDITIONAL_NZ
;
1224 unreachable("bad opcode");
1226 bld
.CMP(dest
, op
[0], op
[1], cond
);
1228 if (bit_size
> 32) {
1229 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1230 } else if (bit_size
< 32) {
1231 /* When we convert the result to 32-bit we need to be careful and do
1232 * it as a signed conversion to get sign extension (for 32-bit true)
1234 const brw_reg_type src_type
=
1235 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1237 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1243 if (devinfo
->gen
>= 8) {
1244 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1246 if (inot_src_instr
!= NULL
&&
1247 (inot_src_instr
->op
== nir_op_ior
||
1248 inot_src_instr
->op
== nir_op_ixor
||
1249 inot_src_instr
->op
== nir_op_iand
) &&
1250 !inot_src_instr
->src
[0].abs
&&
1251 !inot_src_instr
->src
[0].negate
&&
1252 !inot_src_instr
->src
[1].abs
&&
1253 !inot_src_instr
->src
[1].negate
) {
1254 /* The sources of the source logical instruction are now the
1255 * sources of the instruction that will be generated.
1257 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1258 resolve_inot_sources(bld
, inot_src_instr
, op
);
1260 /* Smash all of the sources and destination to be signed. This
1261 * doesn't matter for the operation of the instruction, but cmod
1262 * propagation fails on unsigned sources with negation (due to
1263 * fs_inst::can_do_cmod returning false).
1266 brw_type_for_nir_type(devinfo
,
1267 (nir_alu_type
)(nir_type_int
|
1268 nir_dest_bit_size(instr
->dest
.dest
)));
1270 brw_type_for_nir_type(devinfo
,
1271 (nir_alu_type
)(nir_type_int
|
1272 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1274 brw_type_for_nir_type(devinfo
,
1275 (nir_alu_type
)(nir_type_int
|
1276 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1278 /* For XOR, only invert one of the sources. Arbitrarily choose
1281 op
[0].negate
= !op
[0].negate
;
1282 if (inot_src_instr
->op
!= nir_op_ixor
)
1283 op
[1].negate
= !op
[1].negate
;
1285 switch (inot_src_instr
->op
) {
1287 bld
.AND(result
, op
[0], op
[1]);
1291 bld
.OR(result
, op
[0], op
[1]);
1295 bld
.XOR(result
, op
[0], op
[1]);
1299 unreachable("impossible opcode");
1302 op
[0] = resolve_source_modifiers(op
[0]);
1304 bld
.NOT(result
, op
[0]);
1307 if (devinfo
->gen
>= 8) {
1308 resolve_inot_sources(bld
, instr
, op
);
1310 bld
.XOR(result
, op
[0], op
[1]);
1313 if (devinfo
->gen
>= 8) {
1314 resolve_inot_sources(bld
, instr
, op
);
1316 bld
.OR(result
, op
[0], op
[1]);
1319 if (devinfo
->gen
>= 8) {
1320 resolve_inot_sources(bld
, instr
, op
);
1322 bld
.AND(result
, op
[0], op
[1]);
1328 case nir_op_b32all_fequal2
:
1329 case nir_op_b32all_iequal2
:
1330 case nir_op_b32all_fequal3
:
1331 case nir_op_b32all_iequal3
:
1332 case nir_op_b32all_fequal4
:
1333 case nir_op_b32all_iequal4
:
1334 case nir_op_b32any_fnequal2
:
1335 case nir_op_b32any_inequal2
:
1336 case nir_op_b32any_fnequal3
:
1337 case nir_op_b32any_inequal3
:
1338 case nir_op_b32any_fnequal4
:
1339 case nir_op_b32any_inequal4
:
1340 unreachable("Lowered by nir_lower_alu_reductions");
1342 case nir_op_fnoise1_1
:
1343 case nir_op_fnoise1_2
:
1344 case nir_op_fnoise1_3
:
1345 case nir_op_fnoise1_4
:
1346 case nir_op_fnoise2_1
:
1347 case nir_op_fnoise2_2
:
1348 case nir_op_fnoise2_3
:
1349 case nir_op_fnoise2_4
:
1350 case nir_op_fnoise3_1
:
1351 case nir_op_fnoise3_2
:
1352 case nir_op_fnoise3_3
:
1353 case nir_op_fnoise3_4
:
1354 case nir_op_fnoise4_1
:
1355 case nir_op_fnoise4_2
:
1356 case nir_op_fnoise4_3
:
1357 case nir_op_fnoise4_4
:
1358 unreachable("not reached: should be handled by lower_noise");
1361 unreachable("not reached: should be handled by ldexp_to_arith()");
1364 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1365 inst
->saturate
= instr
->dest
.saturate
;
1369 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1370 inst
->saturate
= instr
->dest
.saturate
;
1374 case nir_op_f2b32
: {
1375 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1376 if (bit_size
== 64) {
1377 /* two-argument instructions can't take 64-bit immediates */
1381 if (instr
->op
== nir_op_f2b32
) {
1382 zero
= vgrf(glsl_type::double_type
);
1383 tmp
= vgrf(glsl_type::double_type
);
1384 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1386 zero
= vgrf(glsl_type::int64_t_type
);
1387 tmp
= vgrf(glsl_type::int64_t_type
);
1388 bld
.MOV(zero
, brw_imm_q(0));
1391 /* A SIMD16 execution needs to be split in two instructions, so use
1392 * a vgrf instead of the flag register as dst so instruction splitting
1395 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1396 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1399 if (bit_size
== 32) {
1400 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1402 assert(bit_size
== 16);
1403 zero
= instr
->op
== nir_op_f2b32
?
1404 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1406 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1412 inst
= bld
.RNDZ(result
, op
[0]);
1413 inst
->saturate
= instr
->dest
.saturate
;
1416 case nir_op_fceil
: {
1417 op
[0].negate
= !op
[0].negate
;
1418 fs_reg temp
= vgrf(glsl_type::float_type
);
1419 bld
.RNDD(temp
, op
[0]);
1421 inst
= bld
.MOV(result
, temp
);
1422 inst
->saturate
= instr
->dest
.saturate
;
1426 inst
= bld
.RNDD(result
, op
[0]);
1427 inst
->saturate
= instr
->dest
.saturate
;
1430 inst
= bld
.FRC(result
, op
[0]);
1431 inst
->saturate
= instr
->dest
.saturate
;
1433 case nir_op_fround_even
:
1434 inst
= bld
.RNDE(result
, op
[0]);
1435 inst
->saturate
= instr
->dest
.saturate
;
1438 case nir_op_fquantize2f16
: {
1439 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1440 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1441 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1443 /* The destination stride must be at least as big as the source stride. */
1444 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1447 /* Check for denormal */
1448 fs_reg abs_src0
= op
[0];
1449 abs_src0
.abs
= true;
1450 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1452 /* Get the appropriately signed zero */
1453 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1454 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1455 brw_imm_ud(0x80000000));
1456 /* Do the actual F32 -> F16 -> F32 conversion */
1457 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1458 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1459 /* Select that or zero based on normal status */
1460 inst
= bld
.SEL(result
, zero
, tmp32
);
1461 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1462 inst
->saturate
= instr
->dest
.saturate
;
1469 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1470 inst
->saturate
= instr
->dest
.saturate
;
1476 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1477 inst
->saturate
= instr
->dest
.saturate
;
1480 case nir_op_pack_snorm_2x16
:
1481 case nir_op_pack_snorm_4x8
:
1482 case nir_op_pack_unorm_2x16
:
1483 case nir_op_pack_unorm_4x8
:
1484 case nir_op_unpack_snorm_2x16
:
1485 case nir_op_unpack_snorm_4x8
:
1486 case nir_op_unpack_unorm_2x16
:
1487 case nir_op_unpack_unorm_4x8
:
1488 case nir_op_unpack_half_2x16
:
1489 case nir_op_pack_half_2x16
:
1490 unreachable("not reached: should be handled by lower_packing_builtins");
1492 case nir_op_unpack_half_2x16_split_x
:
1493 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1494 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1495 inst
->saturate
= instr
->dest
.saturate
;
1497 case nir_op_unpack_half_2x16_split_y
:
1498 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1499 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1500 inst
->saturate
= instr
->dest
.saturate
;
1503 case nir_op_pack_64_2x32_split
:
1504 case nir_op_pack_32_2x16_split
:
1505 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1508 case nir_op_unpack_64_2x32_split_x
:
1509 case nir_op_unpack_64_2x32_split_y
: {
1510 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1511 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1513 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1517 case nir_op_unpack_32_2x16_split_x
:
1518 case nir_op_unpack_32_2x16_split_y
: {
1519 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1520 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1522 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1527 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1528 inst
->saturate
= instr
->dest
.saturate
;
1531 case nir_op_bitfield_reverse
:
1532 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1533 bld
.BFREV(result
, op
[0]);
1536 case nir_op_bit_count
:
1537 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1538 bld
.CBIT(result
, op
[0]);
1541 case nir_op_ufind_msb
: {
1542 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1543 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1547 case nir_op_ifind_msb
: {
1548 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1550 if (devinfo
->gen
< 7) {
1551 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1553 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1555 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1556 * count from the LSB side. If FBH didn't return an error
1557 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1558 * count into an LSB count.
1560 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1562 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1563 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1564 inst
->src
[0].negate
= true;
1569 case nir_op_find_lsb
:
1570 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1572 if (devinfo
->gen
< 7) {
1573 fs_reg temp
= vgrf(glsl_type::int_type
);
1575 /* (x & -x) generates a value that consists of only the LSB of x.
1576 * For all powers of 2, findMSB(y) == findLSB(y).
1578 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1579 fs_reg negated_src
= src
;
1581 /* One must be negated, and the other must be non-negated. It
1582 * doesn't matter which is which.
1584 negated_src
.negate
= true;
1587 bld
.AND(temp
, src
, negated_src
);
1588 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1590 bld
.FBL(result
, op
[0]);
1594 case nir_op_ubitfield_extract
:
1595 case nir_op_ibitfield_extract
:
1596 unreachable("should have been lowered");
1599 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1600 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1603 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1604 bld
.BFI1(result
, op
[0], op
[1]);
1607 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1608 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1611 case nir_op_bitfield_insert
:
1612 unreachable("not reached: should have been lowered");
1615 bld
.SHL(result
, op
[0], op
[1]);
1618 bld
.ASR(result
, op
[0], op
[1]);
1621 bld
.SHR(result
, op
[0], op
[1]);
1624 case nir_op_pack_half_2x16_split
:
1625 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1629 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1630 inst
->saturate
= instr
->dest
.saturate
;
1634 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1635 inst
->saturate
= instr
->dest
.saturate
;
1638 case nir_op_b32csel
:
1639 if (optimize_frontfacing_ternary(instr
, result
))
1642 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1643 inst
= bld
.SEL(result
, op
[1], op
[2]);
1644 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1647 case nir_op_extract_u8
:
1648 case nir_op_extract_i8
: {
1649 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1654 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1655 * Use two instructions and a word or DWord intermediate integer type.
1657 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1658 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1660 if (instr
->op
== nir_op_extract_i8
) {
1661 /* If we need to sign extend, extract to a word first */
1662 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1663 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1664 bld
.MOV(result
, w_temp
);
1665 } else if (byte
& 1) {
1666 /* Extract the high byte from the word containing the desired byte
1670 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1673 /* Otherwise use an AND with 0xff and a word type */
1675 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1679 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1680 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1685 case nir_op_extract_u16
:
1686 case nir_op_extract_i16
: {
1687 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1688 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1689 bld
.MOV(result
, subscript(op
[0], type
, word
));
1694 unreachable("unhandled instruction");
1697 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1698 * to sign extend the low bit to 0/~0
1700 if (devinfo
->gen
<= 5 &&
1701 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1702 fs_reg masked
= vgrf(glsl_type::int_type
);
1703 bld
.AND(masked
, result
, brw_imm_d(1));
1704 masked
.negate
= true;
1705 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1710 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1711 nir_load_const_instr
*instr
)
1713 const brw_reg_type reg_type
=
1714 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1715 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1717 switch (instr
->def
.bit_size
) {
1719 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1720 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1724 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1725 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1729 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1730 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1734 assert(devinfo
->gen
>= 7);
1735 if (devinfo
->gen
== 7) {
1736 /* We don't get 64-bit integer types until gen8 */
1737 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1738 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1739 setup_imm_df(bld
, instr
->value
[i
].f64
));
1742 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1743 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1748 unreachable("Invalid bit size");
1751 nir_ssa_values
[instr
->def
.index
] = reg
;
1755 fs_visitor::get_nir_src(const nir_src
&src
)
1759 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1760 const brw_reg_type reg_type
=
1761 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1762 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1764 reg
= nir_ssa_values
[src
.ssa
->index
];
1767 /* We don't handle indirects on locals */
1768 assert(src
.reg
.indirect
== NULL
);
1769 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1770 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1773 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1774 /* The only 64-bit type available on gen7 is DF, so use that. */
1775 reg
.type
= BRW_REGISTER_TYPE_DF
;
1777 /* To avoid floating-point denorm flushing problems, set the type by
1778 * default to an integer type - instructions that need floating point
1779 * semantics will set this to F if they need to
1781 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1782 BRW_REGISTER_TYPE_D
);
1789 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1791 * This function should not be called on any value which may be 64 bits.
1792 * We could theoretically support 64-bit on gen8+ but we choose not to
1793 * because it wouldn't work in general (no gen7 support) and there are
1794 * enough restrictions in 64-bit immediates that you can't take the return
1795 * value and treat it the same as the result of get_nir_src().
1798 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1800 assert(nir_src_bit_size(src
) == 32);
1801 return nir_src_is_const(src
) ?
1802 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1806 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1809 const brw_reg_type reg_type
=
1810 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1811 dest
.ssa
.bit_size
== 8 ?
1812 BRW_REGISTER_TYPE_D
:
1813 BRW_REGISTER_TYPE_F
);
1814 nir_ssa_values
[dest
.ssa
.index
] =
1815 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1816 return nir_ssa_values
[dest
.ssa
.index
];
1818 /* We don't handle indirects on locals */
1819 assert(dest
.reg
.indirect
== NULL
);
1820 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1821 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1826 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1829 for (unsigned i
= 0; i
< 4; i
++) {
1830 if (!((wr_mask
>> i
) & 1))
1833 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1834 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1835 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1836 if (new_inst
->src
[j
].file
== VGRF
)
1837 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1844 emit_pixel_interpolater_send(const fs_builder
&bld
,
1849 glsl_interp_mode interpolation
)
1851 struct brw_wm_prog_data
*wm_prog_data
=
1852 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1854 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1855 /* 2 floats per slot returned */
1856 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1857 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1859 wm_prog_data
->pulls_bary
= true;
1865 * Computes 1 << x, given a D/UD register containing some value x.
1868 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1870 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1872 fs_reg result
= bld
.vgrf(x
.type
, 1);
1873 fs_reg one
= bld
.vgrf(x
.type
, 1);
1875 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1876 bld
.SHL(result
, one
, x
);
1881 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1883 assert(stage
== MESA_SHADER_GEOMETRY
);
1885 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1887 if (gs_compile
->control_data_header_size_bits
== 0)
1890 /* We can only do EndPrimitive() functionality when the control data
1891 * consists of cut bits. Fortunately, the only time it isn't is when the
1892 * output type is points, in which case EndPrimitive() is a no-op.
1894 if (gs_prog_data
->control_data_format
!=
1895 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1899 /* Cut bits use one bit per vertex. */
1900 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1902 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1903 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1905 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1906 * vertex n, 0 otherwise. So all we need to do here is mark bit
1907 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1908 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1909 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1911 * Note that if EndPrimitive() is called before emitting any vertices, this
1912 * will cause us to set bit 31 of the control_data_bits register to 1.
1913 * That's fine because:
1915 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1916 * output, so the hardware will ignore cut bit 31.
1918 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1919 * last vertex, so setting cut bit 31 has no effect (since the primitive
1920 * is automatically ended when the GS terminates).
1922 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1923 * control_data_bits register to 0 when the first vertex is emitted.
1926 const fs_builder abld
= bld
.annotate("end primitive");
1928 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1929 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1930 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1931 fs_reg mask
= intexp2(abld
, prev_count
);
1932 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1933 * attention to the lower 5 bits of its second source argument, so on this
1934 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1935 * ((vertex_count - 1) % 32).
1937 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1941 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1943 assert(stage
== MESA_SHADER_GEOMETRY
);
1944 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1946 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1948 const fs_builder abld
= bld
.annotate("emit control data bits");
1949 const fs_builder fwa_bld
= bld
.exec_all();
1951 /* We use a single UD register to accumulate control data bits (32 bits
1952 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1955 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1956 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1957 * use the Channel Mask phase to enable/disable which DWord within that
1958 * group to write. (Remember, different SIMD8 channels may have emitted
1959 * different numbers of vertices, so we may need per-slot offsets.)
1961 * Channel masking presents an annoying problem: we may have to replicate
1962 * the data up to 4 times:
1964 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1966 * To avoid penalizing shaders that emit a small number of vertices, we
1967 * can avoid these sometimes: if the size of the control data header is
1968 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1969 * land in the same 128-bit group, so we can skip per-slot offsets.
1971 * Similarly, if the control data header is <= 32 bits, there is only one
1972 * DWord, so we can skip channel masks.
1974 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1976 fs_reg channel_mask
, per_slot_offset
;
1978 if (gs_compile
->control_data_header_size_bits
> 32) {
1979 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1980 channel_mask
= vgrf(glsl_type::uint_type
);
1983 if (gs_compile
->control_data_header_size_bits
> 128) {
1984 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1985 per_slot_offset
= vgrf(glsl_type::uint_type
);
1988 /* Figure out which DWord we're trying to write to using the formula:
1990 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1992 * Since bits_per_vertex is a power of two, and is known at compile
1993 * time, this can be optimized to:
1995 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1997 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1998 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1999 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2000 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2001 unsigned log2_bits_per_vertex
=
2002 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2003 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2005 if (per_slot_offset
.file
!= BAD_FILE
) {
2006 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2007 * the appropriate OWord within the control data header.
2009 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2012 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2013 * write to the appropriate DWORD within the OWORD.
2015 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2016 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2017 channel_mask
= intexp2(fwa_bld
, channel
);
2018 /* Then the channel masks need to be in bits 23:16. */
2019 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2022 /* Store the control data bits in the message payload and send it. */
2024 if (channel_mask
.file
!= BAD_FILE
)
2025 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2026 if (per_slot_offset
.file
!= BAD_FILE
)
2029 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2030 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2032 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2033 if (per_slot_offset
.file
!= BAD_FILE
)
2034 sources
[i
++] = per_slot_offset
;
2035 if (channel_mask
.file
!= BAD_FILE
)
2036 sources
[i
++] = channel_mask
;
2038 sources
[i
++] = this->control_data_bits
;
2041 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2042 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2044 /* We need to increment Global Offset by 256-bits to make room for
2045 * Broadwell's extra "Vertex Count" payload at the beginning of the
2046 * URB entry. Since this is an OWord message, Global Offset is counted
2047 * in 128-bit units, so we must set it to 2.
2049 if (gs_prog_data
->static_vertex_count
== -1)
2054 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2057 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2059 /* Note: we are calling this *before* increasing vertex_count, so
2060 * this->vertex_count == vertex_count - 1 in the formula above.
2063 /* Stream mode uses 2 bits per vertex */
2064 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2066 /* Must be a valid stream */
2067 assert(stream_id
< MAX_VERTEX_STREAMS
);
2069 /* Control data bits are initialized to 0 so we don't have to set any
2070 * bits when sending vertices to stream 0.
2075 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2077 /* reg::sid = stream_id */
2078 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2079 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2081 /* reg:shift_count = 2 * (vertex_count - 1) */
2082 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2083 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2085 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2086 * attention to the lower 5 bits of its second source argument, so on this
2087 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2088 * stream_id << ((2 * (vertex_count - 1)) % 32).
2090 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2091 abld
.SHL(mask
, sid
, shift_count
);
2092 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2096 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2099 assert(stage
== MESA_SHADER_GEOMETRY
);
2101 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2103 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2104 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2106 /* Haswell and later hardware ignores the "Render Stream Select" bits
2107 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2108 * and instead sends all primitives down the pipeline for rasterization.
2109 * If the SOL stage is enabled, "Render Stream Select" is honored and
2110 * primitives bound to non-zero streams are discarded after stream output.
2112 * Since the only purpose of primives sent to non-zero streams is to
2113 * be recorded by transform feedback, we can simply discard all geometry
2114 * bound to these streams when transform feedback is disabled.
2116 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2119 /* If we're outputting 32 control data bits or less, then we can wait
2120 * until the shader is over to output them all. Otherwise we need to
2121 * output them as we go. Now is the time to do it, since we're about to
2122 * output the vertex_count'th vertex, so it's guaranteed that the
2123 * control data bits associated with the (vertex_count - 1)th vertex are
2126 if (gs_compile
->control_data_header_size_bits
> 32) {
2127 const fs_builder abld
=
2128 bld
.annotate("emit vertex: emit control data bits");
2130 /* Only emit control data bits if we've finished accumulating a batch
2131 * of 32 bits. This is the case when:
2133 * (vertex_count * bits_per_vertex) % 32 == 0
2135 * (in other words, when the last 5 bits of vertex_count *
2136 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2137 * integer n (which is always the case, since bits_per_vertex is
2138 * always 1 or 2), this is equivalent to requiring that the last 5-n
2139 * bits of vertex_count are 0:
2141 * vertex_count & (2^(5-n) - 1) == 0
2143 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2146 * vertex_count & (32 / bits_per_vertex - 1) == 0
2148 * TODO: If vertex_count is an immediate, we could do some of this math
2149 * at compile time...
2152 abld
.AND(bld
.null_reg_d(), vertex_count
,
2153 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2154 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2156 abld
.IF(BRW_PREDICATE_NORMAL
);
2157 /* If vertex_count is 0, then no control data bits have been
2158 * accumulated yet, so we can skip emitting them.
2160 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2161 BRW_CONDITIONAL_NEQ
);
2162 abld
.IF(BRW_PREDICATE_NORMAL
);
2163 emit_gs_control_data_bits(vertex_count
);
2164 abld
.emit(BRW_OPCODE_ENDIF
);
2166 /* Reset control_data_bits to 0 so we can start accumulating a new
2169 * Note: in the case where vertex_count == 0, this neutralizes the
2170 * effect of any call to EndPrimitive() that the shader may have
2171 * made before outputting its first vertex.
2173 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2174 inst
->force_writemask_all
= true;
2175 abld
.emit(BRW_OPCODE_ENDIF
);
2178 emit_urb_writes(vertex_count
);
2180 /* In stream mode we have to set control data bits for all vertices
2181 * unless we have disabled control data bits completely (which we do
2182 * do for GL_POINTS outputs that don't use streams).
2184 if (gs_compile
->control_data_header_size_bits
> 0 &&
2185 gs_prog_data
->control_data_format
==
2186 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2187 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2192 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2193 const nir_src
&vertex_src
,
2194 unsigned base_offset
,
2195 const nir_src
&offset_src
,
2196 unsigned num_components
,
2197 unsigned first_component
)
2199 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2200 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2202 /* TODO: figure out push input layout for invocations == 1 */
2203 /* TODO: make this work with 64-bit inputs */
2204 if (gs_prog_data
->invocations
== 1 &&
2205 type_sz(dst
.type
) <= 4 &&
2206 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2207 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2208 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2209 nir_src_as_uint(vertex_src
) * push_reg_count
;
2210 for (unsigned i
= 0; i
< num_components
; i
++) {
2211 bld
.MOV(offset(dst
, bld
, i
),
2212 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2217 /* Resort to the pull model. Ensure the VUE handles are provided. */
2218 assert(gs_prog_data
->base
.include_vue_handles
);
2220 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2221 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2223 if (gs_prog_data
->invocations
== 1) {
2224 if (nir_src_is_const(vertex_src
)) {
2225 /* The vertex index is constant; just select the proper URB handle. */
2227 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2228 BRW_REGISTER_TYPE_UD
);
2230 /* The vertex index is non-constant. We need to use indirect
2231 * addressing to fetch the proper URB handle.
2233 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2234 * indicating that channel <n> should read the handle from
2235 * DWord <n>. We convert that to bytes by multiplying by 4.
2237 * Next, we convert the vertex index to bytes by multiplying
2238 * by 32 (shifting by 5), and add the two together. This is
2239 * the final indirect byte offset.
2241 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2242 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2243 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2244 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2246 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2247 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2248 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2249 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2250 /* Convert vertex_index to bytes (multiply by 32) */
2251 bld
.SHL(vertex_offset_bytes
,
2252 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2254 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2256 /* Use first_icp_handle as the base offset. There is one register
2257 * of URB handles per vertex, so inform the register allocator that
2258 * we might read up to nir->info.gs.vertices_in registers.
2260 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2261 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2262 fs_reg(icp_offset_bytes
),
2263 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2266 assert(gs_prog_data
->invocations
> 1);
2268 if (nir_src_is_const(vertex_src
)) {
2269 unsigned vertex
= nir_src_as_uint(vertex_src
);
2270 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2272 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2273 BRW_REGISTER_TYPE_UD
));
2275 /* The vertex index is non-constant. We need to use indirect
2276 * addressing to fetch the proper URB handle.
2279 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2281 /* Convert vertex_index to bytes (multiply by 4) */
2282 bld
.SHL(icp_offset_bytes
,
2283 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2286 /* Use first_icp_handle as the base offset. There is one DWord
2287 * of URB handles per vertex, so inform the register allocator that
2288 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2290 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2291 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2292 fs_reg(icp_offset_bytes
),
2293 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2300 fs_reg tmp_dst
= dst
;
2301 fs_reg indirect_offset
= get_nir_src(offset_src
);
2302 unsigned num_iterations
= 1;
2303 unsigned orig_num_components
= num_components
;
2305 if (type_sz(dst
.type
) == 8) {
2306 if (num_components
> 2) {
2310 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2312 first_component
= first_component
/ 2;
2315 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2316 if (nir_src_is_const(offset_src
)) {
2317 /* Constant indexing - use global offset. */
2318 if (first_component
!= 0) {
2319 unsigned read_components
= num_components
+ first_component
;
2320 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2321 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2322 inst
->size_written
= read_components
*
2323 tmp
.component_size(inst
->exec_size
);
2324 for (unsigned i
= 0; i
< num_components
; i
++) {
2325 bld
.MOV(offset(tmp_dst
, bld
, i
),
2326 offset(tmp
, bld
, i
+ first_component
));
2329 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2331 inst
->size_written
= num_components
*
2332 tmp_dst
.component_size(inst
->exec_size
);
2334 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2337 /* Indirect indexing - use per-slot offsets as well. */
2338 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2339 unsigned read_components
= num_components
+ first_component
;
2340 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2341 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2342 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2343 if (first_component
!= 0) {
2344 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2346 inst
->size_written
= read_components
*
2347 tmp
.component_size(inst
->exec_size
);
2348 for (unsigned i
= 0; i
< num_components
; i
++) {
2349 bld
.MOV(offset(tmp_dst
, bld
, i
),
2350 offset(tmp
, bld
, i
+ first_component
));
2353 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2355 inst
->size_written
= num_components
*
2356 tmp_dst
.component_size(inst
->exec_size
);
2358 inst
->offset
= base_offset
;
2362 if (type_sz(dst
.type
) == 8) {
2363 shuffle_from_32bit_read(bld
,
2364 offset(dst
, bld
, iter
* 2),
2365 retype(tmp_dst
, BRW_REGISTER_TYPE_D
),
2370 if (num_iterations
> 1) {
2371 num_components
= orig_num_components
- 2;
2372 if(nir_src_is_const(offset_src
)) {
2375 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2376 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2377 indirect_offset
= new_indirect
;
2384 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2386 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2388 if (nir_src_is_const(*offset_src
)) {
2389 /* The only constant offset we should find is 0. brw_nir.c's
2390 * add_const_offset_to_base() will fold other constant offsets
2391 * into instr->const_index[0].
2393 assert(nir_src_as_uint(*offset_src
) == 0);
2397 return get_nir_src(*offset_src
);
2401 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2402 nir_intrinsic_instr
*instr
)
2404 assert(stage
== MESA_SHADER_VERTEX
);
2407 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2408 dest
= get_nir_dest(instr
->dest
);
2410 switch (instr
->intrinsic
) {
2411 case nir_intrinsic_load_vertex_id
:
2412 case nir_intrinsic_load_base_vertex
:
2413 unreachable("should be lowered by nir_lower_system_values()");
2415 case nir_intrinsic_load_input
: {
2416 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2417 unsigned first_component
= nir_intrinsic_component(instr
);
2418 unsigned num_components
= instr
->num_components
;
2420 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2422 if (type_sz(dest
.type
) == 8)
2423 first_component
/= 2;
2425 /* For 16-bit support maybe a temporary will be needed to copy from
2428 shuffle_from_32bit_read(bld
, dest
, retype(src
, BRW_REGISTER_TYPE_D
),
2429 first_component
, num_components
);
2433 case nir_intrinsic_load_vertex_id_zero_base
:
2434 case nir_intrinsic_load_instance_id
:
2435 case nir_intrinsic_load_base_instance
:
2436 case nir_intrinsic_load_draw_id
:
2437 case nir_intrinsic_load_first_vertex
:
2438 case nir_intrinsic_load_is_indexed_draw
:
2439 unreachable("lowered by brw_nir_lower_vs_inputs");
2442 nir_emit_intrinsic(bld
, instr
);
2448 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2449 nir_intrinsic_instr
*instr
)
2451 assert(stage
== MESA_SHADER_TESS_CTRL
);
2452 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2453 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2456 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2457 dst
= get_nir_dest(instr
->dest
);
2459 switch (instr
->intrinsic
) {
2460 case nir_intrinsic_load_primitive_id
:
2461 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2463 case nir_intrinsic_load_invocation_id
:
2464 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2466 case nir_intrinsic_load_patch_vertices_in
:
2467 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2468 brw_imm_d(tcs_key
->input_vertices
));
2471 case nir_intrinsic_barrier
: {
2472 if (tcs_prog_data
->instances
== 1)
2475 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2476 fs_reg m0_2
= component(m0
, 2);
2478 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2480 /* Zero the message header */
2481 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2483 if (devinfo
->gen
< 11) {
2484 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2485 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2486 brw_imm_ud(INTEL_MASK(16, 13)));
2488 /* Shift it up to bits 27:24. */
2489 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2491 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2492 brw_imm_ud(INTEL_MASK(30, 24)));
2495 /* Set the Barrier Count and the enable bit */
2496 if (devinfo
->gen
< 11) {
2497 chanbld
.OR(m0_2
, m0_2
,
2498 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2500 chanbld
.OR(m0_2
, m0_2
,
2501 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2504 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2508 case nir_intrinsic_load_input
:
2509 unreachable("nir_lower_io should never give us these.");
2512 case nir_intrinsic_load_per_vertex_input
: {
2513 fs_reg indirect_offset
= get_indirect_offset(instr
);
2514 unsigned imm_offset
= instr
->const_index
[0];
2516 const nir_src
&vertex_src
= instr
->src
[0];
2522 if (nir_src_is_const(vertex_src
)) {
2523 /* Emit a MOV to resolve <0,1,0> regioning. */
2524 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2525 unsigned vertex
= nir_src_as_uint(vertex_src
);
2527 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2528 BRW_REGISTER_TYPE_UD
));
2529 } else if (tcs_prog_data
->instances
== 1 &&
2530 vertex_src
.is_ssa
&&
2531 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2532 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2533 /* For the common case of only 1 instance, an array index of
2534 * gl_InvocationID means reading g1. Skip all the indirect work.
2536 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2538 /* The vertex index is non-constant. We need to use indirect
2539 * addressing to fetch the proper URB handle.
2541 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2543 /* Each ICP handle is a single DWord (4 bytes) */
2544 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2545 bld
.SHL(vertex_offset_bytes
,
2546 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2549 /* Start at g1. We might read up to 4 registers. */
2550 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2551 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2552 brw_imm_ud(4 * REG_SIZE
));
2555 /* We can only read two double components with each URB read, so
2556 * we send two read messages in that case, each one loading up to
2557 * two double components.
2559 unsigned num_iterations
= 1;
2560 unsigned num_components
= instr
->num_components
;
2561 unsigned first_component
= nir_intrinsic_component(instr
);
2562 fs_reg orig_dst
= dst
;
2563 if (type_sz(dst
.type
) == 8) {
2564 first_component
= first_component
/ 2;
2565 if (instr
->num_components
> 2) {
2570 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2574 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2575 if (indirect_offset
.file
== BAD_FILE
) {
2576 /* Constant indexing - use global offset. */
2577 if (first_component
!= 0) {
2578 unsigned read_components
= num_components
+ first_component
;
2579 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2580 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2581 for (unsigned i
= 0; i
< num_components
; i
++) {
2582 bld
.MOV(offset(dst
, bld
, i
),
2583 offset(tmp
, bld
, i
+ first_component
));
2586 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2588 inst
->offset
= imm_offset
;
2591 /* Indirect indexing - use per-slot offsets as well. */
2592 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2593 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2594 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2595 if (first_component
!= 0) {
2596 unsigned read_components
= num_components
+ first_component
;
2597 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2598 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2600 for (unsigned i
= 0; i
< num_components
; i
++) {
2601 bld
.MOV(offset(dst
, bld
, i
),
2602 offset(tmp
, bld
, i
+ first_component
));
2605 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2608 inst
->offset
= imm_offset
;
2611 inst
->size_written
= (num_components
+ first_component
) *
2612 inst
->dst
.component_size(inst
->exec_size
);
2614 /* If we are reading 64-bit data using 32-bit read messages we need
2615 * build proper 64-bit data elements by shuffling the low and high
2616 * 32-bit components around like we do for other things like UBOs
2619 if (type_sz(dst
.type
) == 8) {
2620 shuffle_from_32bit_read(bld
,
2621 offset(orig_dst
, bld
, iter
* 2),
2622 retype(dst
, BRW_REGISTER_TYPE_D
),
2626 /* Copy the temporary to the destination to deal with writemasking.
2628 * Also attempt to deal with gl_PointSize being in the .w component.
2630 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2631 assert(type_sz(dst
.type
) < 8);
2632 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2633 inst
->size_written
= 4 * REG_SIZE
;
2634 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2637 /* If we are loading double data and we need a second read message
2638 * adjust the write offset
2640 if (num_iterations
> 1) {
2641 num_components
= instr
->num_components
- 2;
2648 case nir_intrinsic_load_output
:
2649 case nir_intrinsic_load_per_vertex_output
: {
2650 fs_reg indirect_offset
= get_indirect_offset(instr
);
2651 unsigned imm_offset
= instr
->const_index
[0];
2652 unsigned first_component
= nir_intrinsic_component(instr
);
2655 if (indirect_offset
.file
== BAD_FILE
) {
2656 /* Replicate the patch handle to all enabled channels */
2657 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2658 bld
.MOV(patch_handle
,
2659 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2662 if (first_component
!= 0) {
2663 unsigned read_components
=
2664 instr
->num_components
+ first_component
;
2665 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2666 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2668 inst
->size_written
= read_components
* REG_SIZE
;
2669 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2670 bld
.MOV(offset(dst
, bld
, i
),
2671 offset(tmp
, bld
, i
+ first_component
));
2674 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2676 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2678 inst
->offset
= imm_offset
;
2682 /* Indirect indexing - use per-slot offsets as well. */
2683 const fs_reg srcs
[] = {
2684 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2687 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2688 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2689 if (first_component
!= 0) {
2690 unsigned read_components
=
2691 instr
->num_components
+ first_component
;
2692 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2693 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2695 inst
->size_written
= read_components
* REG_SIZE
;
2696 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2697 bld
.MOV(offset(dst
, bld
, i
),
2698 offset(tmp
, bld
, i
+ first_component
));
2701 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2703 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2705 inst
->offset
= imm_offset
;
2711 case nir_intrinsic_store_output
:
2712 case nir_intrinsic_store_per_vertex_output
: {
2713 fs_reg value
= get_nir_src(instr
->src
[0]);
2714 bool is_64bit
= (instr
->src
[0].is_ssa
?
2715 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2716 fs_reg indirect_offset
= get_indirect_offset(instr
);
2717 unsigned imm_offset
= instr
->const_index
[0];
2718 unsigned mask
= instr
->const_index
[1];
2719 unsigned header_regs
= 0;
2721 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2723 if (indirect_offset
.file
!= BAD_FILE
) {
2724 srcs
[header_regs
++] = indirect_offset
;
2730 unsigned num_components
= util_last_bit(mask
);
2733 /* We can only pack two 64-bit components in a single message, so send
2734 * 2 messages if we have more components
2736 unsigned num_iterations
= 1;
2737 unsigned iter_components
= num_components
;
2738 unsigned first_component
= nir_intrinsic_component(instr
);
2740 first_component
= first_component
/ 2;
2741 if (instr
->num_components
> 2) {
2743 iter_components
= 2;
2747 mask
= mask
<< first_component
;
2749 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2750 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2751 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2752 opcode
= indirect_offset
.file
!= BAD_FILE
?
2753 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2754 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2755 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2756 /* Expand the 64-bit mask to 32-bit channels. We only handle
2757 * two channels in each iteration, so we only care about X/Y.
2759 unsigned mask32
= 0;
2760 if (mask
& WRITEMASK_X
)
2761 mask32
|= WRITEMASK_XY
;
2762 if (mask
& WRITEMASK_Y
)
2763 mask32
|= WRITEMASK_ZW
;
2765 /* If the mask does not include any of the channels X or Y there
2766 * is nothing to do in this iteration. Move on to the next couple
2767 * of 64-bit channels.
2775 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2776 opcode
= indirect_offset
.file
!= BAD_FILE
?
2777 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2778 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2780 opcode
= indirect_offset
.file
!= BAD_FILE
?
2781 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2782 SHADER_OPCODE_URB_WRITE_SIMD8
;
2785 for (unsigned i
= 0; i
< iter_components
; i
++) {
2786 if (!(mask
& (1 << (i
+ first_component
))))
2790 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2792 /* We need to shuffle the 64-bit data to match the layout
2793 * expected by our 32-bit URB write messages. We use a temporary
2796 unsigned channel
= iter
* 2 + i
;
2797 fs_reg dest
= shuffle_for_32bit_write(bld
, value
, channel
, 1);
2799 srcs
[header_regs
+ (i
+ first_component
) * 2] = dest
;
2800 srcs
[header_regs
+ (i
+ first_component
) * 2 + 1] =
2801 offset(dest
, bld
, 1);
2806 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2807 (is_64bit
? 2 * first_component
: first_component
);
2809 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2810 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2812 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2813 inst
->offset
= imm_offset
;
2816 /* If this is a 64-bit attribute, select the next two 64-bit channels
2817 * to be handled in the next iteration.
2828 nir_emit_intrinsic(bld
, instr
);
2834 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2835 nir_intrinsic_instr
*instr
)
2837 assert(stage
== MESA_SHADER_TESS_EVAL
);
2838 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2841 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2842 dest
= get_nir_dest(instr
->dest
);
2844 switch (instr
->intrinsic
) {
2845 case nir_intrinsic_load_primitive_id
:
2846 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2848 case nir_intrinsic_load_tess_coord
:
2849 /* gl_TessCoord is part of the payload in g1-3 */
2850 for (unsigned i
= 0; i
< 3; i
++) {
2851 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2855 case nir_intrinsic_load_input
:
2856 case nir_intrinsic_load_per_vertex_input
: {
2857 fs_reg indirect_offset
= get_indirect_offset(instr
);
2858 unsigned imm_offset
= instr
->const_index
[0];
2859 unsigned first_component
= nir_intrinsic_component(instr
);
2861 if (type_sz(dest
.type
) == 8) {
2862 first_component
= first_component
/ 2;
2866 if (indirect_offset
.file
== BAD_FILE
) {
2867 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2868 * which is 16 registers (since each holds 2 vec4 slots).
2870 unsigned slot_count
= 1;
2871 if (type_sz(dest
.type
) == 8 && instr
->num_components
> 2)
2874 const unsigned max_push_slots
= 32;
2875 if (imm_offset
+ slot_count
<= max_push_slots
) {
2876 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2877 for (int i
= 0; i
< instr
->num_components
; i
++) {
2878 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2879 i
+ first_component
;
2880 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2883 tes_prog_data
->base
.urb_read_length
=
2884 MAX2(tes_prog_data
->base
.urb_read_length
,
2885 DIV_ROUND_UP(imm_offset
+ slot_count
, 2));
2887 /* Replicate the patch handle to all enabled channels */
2888 const fs_reg srcs
[] = {
2889 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2891 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2892 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2894 if (first_component
!= 0) {
2895 unsigned read_components
=
2896 instr
->num_components
+ first_component
;
2897 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2898 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2900 inst
->size_written
= read_components
* REG_SIZE
;
2901 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2902 bld
.MOV(offset(dest
, bld
, i
),
2903 offset(tmp
, bld
, i
+ first_component
));
2906 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2908 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2911 inst
->offset
= imm_offset
;
2914 /* Indirect indexing - use per-slot offsets as well. */
2916 /* We can only read two double components with each URB read, so
2917 * we send two read messages in that case, each one loading up to
2918 * two double components.
2920 unsigned num_iterations
= 1;
2921 unsigned num_components
= instr
->num_components
;
2922 fs_reg orig_dest
= dest
;
2923 if (type_sz(dest
.type
) == 8) {
2924 if (instr
->num_components
> 2) {
2928 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2932 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2933 const fs_reg srcs
[] = {
2934 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2937 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2938 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2940 if (first_component
!= 0) {
2941 unsigned read_components
=
2942 num_components
+ first_component
;
2943 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2944 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2946 for (unsigned i
= 0; i
< num_components
; i
++) {
2947 bld
.MOV(offset(dest
, bld
, i
),
2948 offset(tmp
, bld
, i
+ first_component
));
2951 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2955 inst
->offset
= imm_offset
;
2956 inst
->size_written
= (num_components
+ first_component
) *
2957 inst
->dst
.component_size(inst
->exec_size
);
2959 /* If we are reading 64-bit data using 32-bit read messages we need
2960 * build proper 64-bit data elements by shuffling the low and high
2961 * 32-bit components around like we do for other things like UBOs
2964 if (type_sz(dest
.type
) == 8) {
2965 shuffle_from_32bit_read(bld
,
2966 offset(orig_dest
, bld
, iter
* 2),
2967 retype(dest
, BRW_REGISTER_TYPE_D
),
2971 /* If we are loading double data and we need a second read message
2974 if (num_iterations
> 1) {
2975 num_components
= instr
->num_components
- 2;
2983 nir_emit_intrinsic(bld
, instr
);
2989 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2990 nir_intrinsic_instr
*instr
)
2992 assert(stage
== MESA_SHADER_GEOMETRY
);
2993 fs_reg indirect_offset
;
2996 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2997 dest
= get_nir_dest(instr
->dest
);
2999 switch (instr
->intrinsic
) {
3000 case nir_intrinsic_load_primitive_id
:
3001 assert(stage
== MESA_SHADER_GEOMETRY
);
3002 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3003 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3004 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3007 case nir_intrinsic_load_input
:
3008 unreachable("load_input intrinsics are invalid for the GS stage");
3010 case nir_intrinsic_load_per_vertex_input
:
3011 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3012 instr
->src
[1], instr
->num_components
,
3013 nir_intrinsic_component(instr
));
3016 case nir_intrinsic_emit_vertex_with_counter
:
3017 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3020 case nir_intrinsic_end_primitive_with_counter
:
3021 emit_gs_end_primitive(instr
->src
[0]);
3024 case nir_intrinsic_set_vertex_count
:
3025 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3028 case nir_intrinsic_load_invocation_id
: {
3029 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3030 assert(val
.file
!= BAD_FILE
);
3031 dest
.type
= val
.type
;
3037 nir_emit_intrinsic(bld
, instr
);
3043 * Fetch the current render target layer index.
3046 fetch_render_target_array_index(const fs_builder
&bld
)
3048 if (bld
.shader
->devinfo
->gen
>= 6) {
3049 /* The render target array index is provided in the thread payload as
3050 * bits 26:16 of r0.0.
3052 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3053 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3057 /* Pre-SNB we only ever render into the first layer of the framebuffer
3058 * since layered rendering is not implemented.
3060 return brw_imm_ud(0);
3065 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3066 * framebuffer at the current fragment coordinates and sample index.
3069 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3072 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3074 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3075 const brw_wm_prog_key
*wm_key
=
3076 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3077 assert(!wm_key
->coherent_fb_fetch
);
3078 const struct brw_wm_prog_data
*wm_prog_data
=
3079 brw_wm_prog_data(stage_prog_data
);
3081 /* Calculate the surface index relative to the start of the texture binding
3082 * table block, since that's what the texturing messages expect.
3084 const unsigned surface
= target
+
3085 wm_prog_data
->binding_table
.render_target_read_start
-
3086 wm_prog_data
->base
.binding_table
.texture_start
;
3088 /* Calculate the fragment coordinates. */
3089 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3090 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3091 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3092 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3094 /* Calculate the sample index and MCS payload when multisampling. Luckily
3095 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3096 * shouldn't be necessary to recompile based on whether the framebuffer is
3099 if (wm_key
->multisample_fbo
&&
3100 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3101 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3103 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3104 const fs_reg mcs
= wm_key
->multisample_fbo
?
3105 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3107 /* Use either a normal or a CMS texel fetch message depending on whether
3108 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3109 * message just in case the framebuffer uses 16x multisampling, it should
3110 * be equivalent to the normal CMS fetch for lower multisampling modes.
3112 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3113 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3114 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3116 /* Emit the instruction. */
3117 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3118 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3119 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3120 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3121 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3122 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3123 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3124 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3125 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3127 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3128 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3134 * Actual coherent framebuffer read implemented using the native render target
3135 * read message. Requires SKL+.
3138 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3140 assert(bld
.shader
->devinfo
->gen
>= 9);
3141 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3142 inst
->target
= target
;
3143 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3149 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3151 if (n
&& regs
[0].file
!= BAD_FILE
) {
3155 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3157 for (unsigned i
= 0; i
< n
; i
++)
3165 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3167 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3168 const brw_wm_prog_key
*const key
=
3169 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3170 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3171 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3173 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3174 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3176 else if (l
== FRAG_RESULT_COLOR
)
3177 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3178 MAX2(key
->nr_color_regions
, 1));
3180 else if (l
== FRAG_RESULT_DEPTH
)
3181 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3183 else if (l
== FRAG_RESULT_STENCIL
)
3184 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3186 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3187 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3189 else if (l
>= FRAG_RESULT_DATA0
&&
3190 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3191 return alloc_temporary(v
->bld
, 4,
3192 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3195 unreachable("Invalid location");
3199 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3200 nir_intrinsic_instr
*instr
)
3202 assert(stage
== MESA_SHADER_FRAGMENT
);
3205 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3206 dest
= get_nir_dest(instr
->dest
);
3208 switch (instr
->intrinsic
) {
3209 case nir_intrinsic_load_front_face
:
3210 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3211 *emit_frontfacing_interpolation());
3214 case nir_intrinsic_load_sample_pos
: {
3215 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3216 assert(sample_pos
.file
!= BAD_FILE
);
3217 dest
.type
= sample_pos
.type
;
3218 bld
.MOV(dest
, sample_pos
);
3219 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3223 case nir_intrinsic_load_layer_id
:
3224 dest
.type
= BRW_REGISTER_TYPE_UD
;
3225 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3228 case nir_intrinsic_load_helper_invocation
:
3229 case nir_intrinsic_load_sample_mask_in
:
3230 case nir_intrinsic_load_sample_id
: {
3231 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3232 fs_reg val
= nir_system_values
[sv
];
3233 assert(val
.file
!= BAD_FILE
);
3234 dest
.type
= val
.type
;
3239 case nir_intrinsic_store_output
: {
3240 const fs_reg src
= get_nir_src(instr
->src
[0]);
3241 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3242 const unsigned location
= nir_intrinsic_base(instr
) +
3243 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3244 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3247 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3248 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3249 offset(src
, bld
, j
));
3254 case nir_intrinsic_load_output
: {
3255 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3256 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3257 assert(l
>= FRAG_RESULT_DATA0
);
3258 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3259 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3260 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3262 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3263 emit_coherent_fb_read(bld
, tmp
, target
);
3265 emit_non_coherent_fb_read(bld
, tmp
, target
);
3267 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3268 bld
.MOV(offset(dest
, bld
, j
),
3269 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3275 case nir_intrinsic_discard
:
3276 case nir_intrinsic_discard_if
: {
3277 /* We track our discarded pixels in f0.1. By predicating on it, we can
3278 * update just the flag bits that aren't yet discarded. If there's no
3279 * condition, we emit a CMP of g0 != g0, so all currently executing
3280 * channels will get turned off.
3283 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3284 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3285 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3287 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3288 BRW_REGISTER_TYPE_UW
));
3289 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3291 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3292 cmp
->flag_subreg
= 1;
3294 if (devinfo
->gen
>= 6) {
3295 emit_discard_jump();
3298 limit_dispatch_width(16, "Fragment discard not implemented in SIMD32 mode.");
3302 case nir_intrinsic_load_input
: {
3303 /* load_input is only used for flat inputs */
3304 unsigned base
= nir_intrinsic_base(instr
);
3305 unsigned comp
= nir_intrinsic_component(instr
);
3306 unsigned num_components
= instr
->num_components
;
3307 fs_reg orig_dest
= dest
;
3308 enum brw_reg_type type
= dest
.type
;
3310 /* Special case fields in the VUE header */
3311 if (base
== VARYING_SLOT_LAYER
)
3313 else if (base
== VARYING_SLOT_VIEWPORT
)
3316 if (nir_dest_bit_size(instr
->dest
) == 64) {
3317 /* const_index is in 32-bit type size units that could not be aligned
3318 * with DF. We need to read the double vector as if it was a float
3319 * vector of twice the number of components to fetch the right data.
3321 type
= BRW_REGISTER_TYPE_F
;
3322 num_components
*= 2;
3323 dest
= bld
.vgrf(type
, num_components
);
3326 for (unsigned int i
= 0; i
< num_components
; i
++) {
3327 bld
.MOV(offset(retype(dest
, type
), bld
, i
),
3328 retype(component(interp_reg(base
, comp
+ i
), 3), type
));
3331 if (nir_dest_bit_size(instr
->dest
) == 64) {
3332 shuffle_from_32bit_read(bld
, orig_dest
, dest
, 0,
3333 instr
->num_components
);
3338 case nir_intrinsic_load_barycentric_pixel
:
3339 case nir_intrinsic_load_barycentric_centroid
:
3340 case nir_intrinsic_load_barycentric_sample
:
3341 /* Do nothing - load_interpolated_input handling will handle it later. */
3344 case nir_intrinsic_load_barycentric_at_sample
: {
3345 const glsl_interp_mode interpolation
=
3346 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3348 if (nir_src_is_const(instr
->src
[0])) {
3349 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3351 emit_pixel_interpolater_send(bld
,
3352 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3355 brw_imm_ud(msg_data
),
3358 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3359 BRW_REGISTER_TYPE_UD
);
3361 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3362 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3363 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3364 bld
.exec_all().group(1, 0)
3365 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3366 emit_pixel_interpolater_send(bld
,
3367 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3373 /* Make a loop that sends a message to the pixel interpolater
3374 * for the sample number in each live channel. If there are
3375 * multiple channels with the same sample number then these
3376 * will be handled simultaneously with a single interation of
3379 bld
.emit(BRW_OPCODE_DO
);
3381 /* Get the next live sample number into sample_id_reg */
3382 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3384 /* Set the flag register so that we can perform the send
3385 * message on all channels that have the same sample number
3387 bld
.CMP(bld
.null_reg_ud(),
3388 sample_src
, sample_id
,
3389 BRW_CONDITIONAL_EQ
);
3390 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3391 bld
.exec_all().group(1, 0)
3392 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3394 emit_pixel_interpolater_send(bld
,
3395 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3398 component(msg_data
, 0),
3400 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3402 /* Continue the loop if there are any live channels left */
3403 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3405 bld
.emit(BRW_OPCODE_WHILE
));
3411 case nir_intrinsic_load_barycentric_at_offset
: {
3412 const glsl_interp_mode interpolation
=
3413 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3415 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3418 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3419 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3420 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3422 emit_pixel_interpolater_send(bld
,
3423 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3426 brw_imm_ud(off_x
| (off_y
<< 4)),
3429 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3430 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3431 BRW_REGISTER_TYPE_F
);
3432 for (int i
= 0; i
< 2; i
++) {
3433 fs_reg temp
= vgrf(glsl_type::float_type
);
3434 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3435 fs_reg itemp
= vgrf(glsl_type::int_type
);
3437 bld
.MOV(itemp
, temp
);
3439 /* Clamp the upper end of the range to +7/16.
3440 * ARB_gpu_shader5 requires that we support a maximum offset
3441 * of +0.5, which isn't representable in a S0.4 value -- if
3442 * we didn't clamp it, we'd end up with -8/16, which is the
3443 * opposite of what the shader author wanted.
3445 * This is legal due to ARB_gpu_shader5's quantization
3448 * "Not all values of <offset> may be supported; x and y
3449 * offsets may be rounded to fixed-point values with the
3450 * number of fraction bits given by the
3451 * implementation-dependent constant
3452 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3454 set_condmod(BRW_CONDITIONAL_L
,
3455 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3458 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3459 emit_pixel_interpolater_send(bld
,
3469 case nir_intrinsic_load_interpolated_input
: {
3470 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3471 emit_fragcoord_interpolation(dest
);
3475 assert(instr
->src
[0].ssa
&&
3476 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3477 nir_intrinsic_instr
*bary_intrinsic
=
3478 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3479 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3480 enum glsl_interp_mode interp_mode
=
3481 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3484 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3485 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3486 /* Use the result of the PI message */
3487 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3489 /* Use the delta_xy values computed from the payload */
3490 enum brw_barycentric_mode bary
=
3491 brw_barycentric_mode(interp_mode
, bary_intrin
);
3493 dst_xy
= this->delta_xy
[bary
];
3496 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3498 component(interp_reg(nir_intrinsic_base(instr
),
3499 nir_intrinsic_component(instr
) + i
), 0);
3500 interp
.type
= BRW_REGISTER_TYPE_F
;
3501 dest
.type
= BRW_REGISTER_TYPE_F
;
3503 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3504 fs_reg tmp
= vgrf(glsl_type::float_type
);
3505 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3506 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3508 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3515 nir_emit_intrinsic(bld
, instr
);
3521 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3523 if (nir_src_is_const(instr
->src
[src
])) {
3524 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3527 else if (add_val
== -1)
3535 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3536 nir_intrinsic_instr
*instr
)
3538 assert(stage
== MESA_SHADER_COMPUTE
);
3539 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3542 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3543 dest
= get_nir_dest(instr
->dest
);
3545 switch (instr
->intrinsic
) {
3546 case nir_intrinsic_barrier
:
3548 cs_prog_data
->uses_barrier
= true;
3551 case nir_intrinsic_load_subgroup_id
:
3552 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3555 case nir_intrinsic_load_local_invocation_id
:
3556 case nir_intrinsic_load_work_group_id
: {
3557 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3558 fs_reg val
= nir_system_values
[sv
];
3559 assert(val
.file
!= BAD_FILE
);
3560 dest
.type
= val
.type
;
3561 for (unsigned i
= 0; i
< 3; i
++)
3562 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3566 case nir_intrinsic_load_num_work_groups
: {
3567 const unsigned surface
=
3568 cs_prog_data
->binding_table
.work_groups_start
;
3570 cs_prog_data
->uses_num_work_groups
= true;
3572 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3573 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3574 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3575 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3577 /* Read the 3 GLuint components of gl_NumWorkGroups */
3578 for (unsigned i
= 0; i
< 3; i
++) {
3579 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3580 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3581 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3586 case nir_intrinsic_shared_atomic_add
:
3587 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3589 case nir_intrinsic_shared_atomic_imin
:
3590 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3592 case nir_intrinsic_shared_atomic_umin
:
3593 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3595 case nir_intrinsic_shared_atomic_imax
:
3596 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3598 case nir_intrinsic_shared_atomic_umax
:
3599 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3601 case nir_intrinsic_shared_atomic_and
:
3602 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3604 case nir_intrinsic_shared_atomic_or
:
3605 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3607 case nir_intrinsic_shared_atomic_xor
:
3608 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3610 case nir_intrinsic_shared_atomic_exchange
:
3611 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3613 case nir_intrinsic_shared_atomic_comp_swap
:
3614 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3616 case nir_intrinsic_shared_atomic_fmin
:
3617 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3619 case nir_intrinsic_shared_atomic_fmax
:
3620 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3622 case nir_intrinsic_shared_atomic_fcomp_swap
:
3623 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3626 case nir_intrinsic_load_shared
: {
3627 assert(devinfo
->gen
>= 7);
3628 assert(stage
== MESA_SHADER_COMPUTE
);
3630 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3631 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3632 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3633 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3634 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3636 /* Make dest unsigned because that's what the temporary will be */
3637 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3639 /* Read the vector */
3640 if (nir_intrinsic_align(instr
) >= 4) {
3641 assert(nir_dest_bit_size(instr
->dest
) == 32);
3642 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3644 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3645 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3646 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3648 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3649 assert(nir_dest_num_components(instr
->dest
) == 1);
3650 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3652 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3653 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3654 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3655 bld
.MOV(dest
, read_result
);
3660 case nir_intrinsic_store_shared
: {
3661 assert(devinfo
->gen
>= 7);
3662 assert(stage
== MESA_SHADER_COMPUTE
);
3664 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3665 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3666 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3667 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3668 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3670 fs_reg data
= get_nir_src(instr
->src
[0]);
3671 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3673 assert(nir_intrinsic_write_mask(instr
) ==
3674 (1u << instr
->num_components
) - 1);
3675 if (nir_intrinsic_align(instr
) >= 4) {
3676 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3677 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3678 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3679 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3680 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3681 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3683 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3684 assert(nir_src_num_components(instr
->src
[0]) == 1);
3685 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3687 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3688 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3690 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3691 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3697 nir_emit_intrinsic(bld
, instr
);
3703 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3704 nir_op op
, brw_reg_type type
)
3706 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3707 switch (type_sz(type
)) {
3709 assert(type
!= BRW_REGISTER_TYPE_HF
);
3710 return retype(brw_imm_uw(value
.u16
), type
);
3712 return retype(brw_imm_ud(value
.u32
), type
);
3714 if (type
== BRW_REGISTER_TYPE_DF
)
3715 return setup_imm_df(bld
, value
.f64
);
3717 return retype(brw_imm_u64(value
.u64
), type
);
3719 unreachable("Invalid type size");
3724 brw_op_for_nir_reduction_op(nir_op op
)
3727 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3728 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3729 case nir_op_imul
: return BRW_OPCODE_MUL
;
3730 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3731 case nir_op_imin
: return BRW_OPCODE_SEL
;
3732 case nir_op_umin
: return BRW_OPCODE_SEL
;
3733 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3734 case nir_op_imax
: return BRW_OPCODE_SEL
;
3735 case nir_op_umax
: return BRW_OPCODE_SEL
;
3736 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3737 case nir_op_iand
: return BRW_OPCODE_AND
;
3738 case nir_op_ior
: return BRW_OPCODE_OR
;
3739 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3741 unreachable("Invalid reduction operation");
3745 static brw_conditional_mod
3746 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3749 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3750 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3751 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3752 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3753 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3754 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3755 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3756 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3757 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3758 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3759 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3760 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3761 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3763 unreachable("Invalid reduction operation");
3768 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3769 nir_intrinsic_instr
*instr
)
3771 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3773 if (stage_prog_data
->binding_table
.image_start
> 0) {
3774 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3775 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3777 bld
.ADD(image
, image
,
3778 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3782 return bld
.emit_uniformize(image
);
3786 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3787 nir_intrinsic_instr
*instr
)
3789 /* SSBO stores are weird in that their index is in src[1] */
3790 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3793 if (nir_src_is_const(instr
->src
[src
])) {
3794 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3795 nir_src_as_uint(instr
->src
[src
]);
3796 surf_index
= brw_imm_ud(index
);
3798 surf_index
= vgrf(glsl_type::uint_type
);
3799 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3800 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3803 return bld
.emit_uniformize(surf_index
);
3807 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3809 switch (nir_intrinsic_image_dim(instr
)) {
3810 case GLSL_SAMPLER_DIM_1D
:
3811 return 1 + nir_intrinsic_image_array(instr
);
3812 case GLSL_SAMPLER_DIM_2D
:
3813 case GLSL_SAMPLER_DIM_RECT
:
3814 return 2 + nir_intrinsic_image_array(instr
);
3815 case GLSL_SAMPLER_DIM_3D
:
3816 case GLSL_SAMPLER_DIM_CUBE
:
3818 case GLSL_SAMPLER_DIM_BUF
:
3820 case GLSL_SAMPLER_DIM_MS
:
3821 return 2 + nir_intrinsic_image_array(instr
);
3823 unreachable("Invalid image dimension");
3828 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3831 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3832 dest
= get_nir_dest(instr
->dest
);
3834 switch (instr
->intrinsic
) {
3835 case nir_intrinsic_image_load
:
3836 case nir_intrinsic_image_store
:
3837 case nir_intrinsic_image_atomic_add
:
3838 case nir_intrinsic_image_atomic_min
:
3839 case nir_intrinsic_image_atomic_max
:
3840 case nir_intrinsic_image_atomic_and
:
3841 case nir_intrinsic_image_atomic_or
:
3842 case nir_intrinsic_image_atomic_xor
:
3843 case nir_intrinsic_image_atomic_exchange
:
3844 case nir_intrinsic_image_atomic_comp_swap
: {
3845 if (stage
== MESA_SHADER_FRAGMENT
&&
3846 instr
->intrinsic
!= nir_intrinsic_image_load
)
3847 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3849 /* Get some metadata from the image intrinsic. */
3850 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3851 const GLenum format
= nir_intrinsic_format(instr
);
3853 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3854 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3855 get_nir_image_intrinsic_image(bld
, instr
);
3856 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3857 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
3858 brw_imm_ud(image_intrinsic_coord_components(instr
));
3860 /* Emit an image load, store or atomic op. */
3861 if (instr
->intrinsic
== nir_intrinsic_image_load
) {
3862 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3864 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
3865 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3866 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3867 } else if (instr
->intrinsic
== nir_intrinsic_image_store
) {
3868 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3869 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
3870 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
3871 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3874 unsigned num_srcs
= info
->num_srcs
;
3876 switch (instr
->intrinsic
) {
3877 case nir_intrinsic_image_atomic_add
:
3878 assert(num_srcs
== 4);
3880 op
= get_op_for_atomic_add(instr
, 3);
3882 if (op
!= BRW_AOP_ADD
)
3885 case nir_intrinsic_image_atomic_min
:
3886 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3887 op
= (format
== GL_R32I
) ? BRW_AOP_IMIN
: BRW_AOP_UMIN
;
3889 case nir_intrinsic_image_atomic_max
:
3890 assert(format
== GL_R32UI
|| format
== GL_R32I
);
3891 op
= (format
== GL_R32I
) ? BRW_AOP_IMAX
: BRW_AOP_UMAX
;
3893 case nir_intrinsic_image_atomic_and
:
3896 case nir_intrinsic_image_atomic_or
:
3899 case nir_intrinsic_image_atomic_xor
:
3902 case nir_intrinsic_image_atomic_exchange
:
3905 case nir_intrinsic_image_atomic_comp_swap
:
3909 unreachable("Not reachable.");
3912 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
3916 data
= get_nir_src(instr
->src
[3]);
3917 if (num_srcs
>= 5) {
3918 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
3919 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
3920 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
3923 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3925 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
3926 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3931 case nir_intrinsic_image_size
: {
3932 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
3933 * into will handle the binding table index for us in the geneerator.
3935 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
3936 BRW_REGISTER_TYPE_UD
);
3937 image
= bld
.emit_uniformize(image
);
3939 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3940 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
3941 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
3942 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
3943 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
3945 /* Since the image size is always uniform, we can just emit a SIMD8
3946 * query instruction and splat the result out.
3948 const fs_builder ubld
= bld
.exec_all().group(8, 0);
3950 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
3951 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
3952 tmp
, srcs
, ARRAY_SIZE(srcs
));
3953 inst
->size_written
= 4 * REG_SIZE
;
3955 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
3956 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
3957 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3958 offset(retype(dest
, tmp
.type
), bld
, c
),
3959 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
3961 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
3962 component(offset(tmp
, ubld
, c
), 0));
3968 case nir_intrinsic_image_load_raw_intel
: {
3969 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3970 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3971 get_nir_image_intrinsic_image(bld
, instr
);
3972 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3973 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3974 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3977 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3978 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3979 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3983 case nir_intrinsic_image_store_raw_intel
: {
3984 if (stage
== MESA_SHADER_FRAGMENT
)
3985 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3987 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3988 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
3989 get_nir_image_intrinsic_image(bld
, instr
);
3990 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3991 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
3992 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3993 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3995 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3996 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4000 case nir_intrinsic_group_memory_barrier
:
4001 case nir_intrinsic_memory_barrier_shared
:
4002 case nir_intrinsic_memory_barrier_atomic_counter
:
4003 case nir_intrinsic_memory_barrier_buffer
:
4004 case nir_intrinsic_memory_barrier_image
:
4005 case nir_intrinsic_memory_barrier
: {
4006 const fs_builder ubld
= bld
.group(8, 0);
4007 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4008 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
4009 ->size_written
= 2 * REG_SIZE
;
4013 case nir_intrinsic_shader_clock
: {
4014 /* We cannot do anything if there is an event, so ignore it for now */
4015 const fs_reg shader_clock
= get_timestamp(bld
);
4016 const fs_reg srcs
[] = { component(shader_clock
, 0),
4017 component(shader_clock
, 1) };
4018 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4022 case nir_intrinsic_image_samples
:
4023 /* The driver does not support multi-sampled images. */
4024 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4027 case nir_intrinsic_load_uniform
: {
4028 /* Offsets are in bytes but they should always aligned to
4031 assert(instr
->const_index
[0] % 4 == 0 ||
4032 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4034 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4036 if (nir_src_is_const(instr
->src
[0])) {
4037 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4038 assert(load_offset
% type_sz(dest
.type
) == 0);
4039 /* For 16-bit types we add the module of the const_index[0]
4040 * offset to access to not 32-bit aligned element
4042 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4044 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4045 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4048 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4049 BRW_REGISTER_TYPE_UD
);
4051 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4052 * go past the end of the uniform. In order to keep the n'th
4053 * component from running past, we subtract off the size of all but
4054 * one component of the vector.
4056 assert(instr
->const_index
[1] >=
4057 instr
->num_components
* (int) type_sz(dest
.type
));
4058 unsigned read_size
= instr
->const_index
[1] -
4059 (instr
->num_components
- 1) * type_sz(dest
.type
);
4061 bool supports_64bit_indirects
=
4062 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4064 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4065 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4066 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4067 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4068 indirect
, brw_imm_ud(read_size
));
4071 const unsigned num_mov_indirects
=
4072 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4073 /* We read a little bit less per MOV INDIRECT, as they are now
4074 * 32-bits ones instead of 64-bit. Fix read_size then.
4076 const unsigned read_size_32bit
= read_size
-
4077 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4078 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4079 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4080 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4081 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4082 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4083 indirect
, brw_imm_ud(read_size_32bit
));
4091 case nir_intrinsic_load_ubo
: {
4093 if (nir_src_is_const(instr
->src
[0])) {
4094 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4095 nir_src_as_uint(instr
->src
[0]);
4096 surf_index
= brw_imm_ud(index
);
4098 /* The block index is not a constant. Evaluate the index expression
4099 * per-channel and add the base UBO index; we have to select a value
4100 * from any live channel.
4102 surf_index
= vgrf(glsl_type::uint_type
);
4103 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4104 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4105 surf_index
= bld
.emit_uniformize(surf_index
);
4108 if (!nir_src_is_const(instr
->src
[1])) {
4109 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4110 BRW_REGISTER_TYPE_UD
);
4112 for (int i
= 0; i
< instr
->num_components
; i
++)
4113 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4114 base_offset
, i
* type_sz(dest
.type
));
4116 /* Even if we are loading doubles, a pull constant load will load
4117 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4118 * need to load a full dvec4 we will have to emit 2 loads. This is
4119 * similar to demote_pull_constants(), except that in that case we
4120 * see individual accesses to each component of the vector and then
4121 * we let CSE deal with duplicate loads. Here we see a vector access
4122 * and we have to split it if necessary.
4124 const unsigned type_size
= type_sz(dest
.type
);
4125 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4127 /* See if we've selected this as a push constant candidate */
4128 if (nir_src_is_const(instr
->src
[0])) {
4129 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4130 const unsigned offset_256b
= load_offset
/ 32;
4133 for (int i
= 0; i
< 4; i
++) {
4134 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4135 if (range
->block
== ubo_block
&&
4136 offset_256b
>= range
->start
&&
4137 offset_256b
< range
->start
+ range
->length
) {
4139 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4140 push_reg
.offset
= load_offset
- 32 * range
->start
;
4145 if (push_reg
.file
!= BAD_FILE
) {
4146 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4147 bld
.MOV(offset(dest
, bld
, i
),
4148 byte_offset(push_reg
, i
* type_size
));
4154 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4155 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4156 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4158 for (unsigned c
= 0; c
< instr
->num_components
;) {
4159 const unsigned base
= load_offset
+ c
* type_size
;
4160 /* Number of usable components in the next block-aligned load. */
4161 const unsigned count
= MIN2(instr
->num_components
- c
,
4162 (block_sz
- base
% block_sz
) / type_size
);
4164 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4165 packed_consts
, surf_index
,
4166 brw_imm_ud(base
& ~(block_sz
- 1)));
4168 const fs_reg consts
=
4169 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4172 for (unsigned d
= 0; d
< count
; d
++)
4173 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4181 case nir_intrinsic_load_global
: {
4182 assert(devinfo
->gen
>= 8);
4184 if (nir_intrinsic_align(instr
) >= 4) {
4185 assert(nir_dest_bit_size(instr
->dest
) == 32);
4186 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4188 get_nir_src(instr
->src
[0]), /* Address */
4189 fs_reg(), /* No source data */
4190 brw_imm_ud(instr
->num_components
));
4191 inst
->size_written
= instr
->num_components
*
4192 inst
->dst
.component_size(inst
->exec_size
);
4194 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4195 assert(bit_size
<= 32);
4196 assert(nir_dest_num_components(instr
->dest
) == 1);
4197 brw_reg_type data_type
=
4198 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4199 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4200 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4202 get_nir_src(instr
->src
[0]), /* Address */
4203 fs_reg(), /* No source data */
4204 brw_imm_ud(bit_size
));
4205 bld
.MOV(retype(dest
, data_type
), tmp
);
4210 case nir_intrinsic_store_global
:
4211 assert(devinfo
->gen
>= 8);
4213 if (stage
== MESA_SHADER_FRAGMENT
)
4214 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4216 if (nir_intrinsic_align(instr
) >= 4) {
4217 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4218 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4220 get_nir_src(instr
->src
[1]), /* Address */
4221 get_nir_src(instr
->src
[0]), /* Data */
4222 brw_imm_ud(instr
->num_components
));
4224 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4225 assert(bit_size
<= 32);
4226 assert(nir_src_num_components(instr
->src
[0]) == 1);
4227 brw_reg_type data_type
=
4228 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4229 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4230 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4231 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4233 get_nir_src(instr
->src
[1]), /* Address */
4235 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4239 case nir_intrinsic_global_atomic_add
:
4240 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4242 case nir_intrinsic_global_atomic_imin
:
4243 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4245 case nir_intrinsic_global_atomic_umin
:
4246 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4248 case nir_intrinsic_global_atomic_imax
:
4249 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4251 case nir_intrinsic_global_atomic_umax
:
4252 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4254 case nir_intrinsic_global_atomic_and
:
4255 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4257 case nir_intrinsic_global_atomic_or
:
4258 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4260 case nir_intrinsic_global_atomic_xor
:
4261 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4263 case nir_intrinsic_global_atomic_exchange
:
4264 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4266 case nir_intrinsic_global_atomic_comp_swap
:
4267 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4269 case nir_intrinsic_global_atomic_fmin
:
4270 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4272 case nir_intrinsic_global_atomic_fmax
:
4273 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4275 case nir_intrinsic_global_atomic_fcomp_swap
:
4276 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4279 case nir_intrinsic_load_ssbo
: {
4280 assert(devinfo
->gen
>= 7);
4282 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4283 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4284 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4285 get_nir_ssbo_intrinsic_index(bld
, instr
);
4286 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4287 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4289 /* Make dest unsigned because that's what the temporary will be */
4290 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4292 /* Read the vector */
4293 if (nir_intrinsic_align(instr
) >= 4) {
4294 assert(nir_dest_bit_size(instr
->dest
) == 32);
4295 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4297 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4298 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4299 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4301 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4302 assert(nir_dest_num_components(instr
->dest
) == 1);
4303 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4305 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4306 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4307 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4308 bld
.MOV(dest
, read_result
);
4313 case nir_intrinsic_store_ssbo
: {
4314 assert(devinfo
->gen
>= 7);
4316 if (stage
== MESA_SHADER_FRAGMENT
)
4317 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4319 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4320 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4321 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4322 get_nir_ssbo_intrinsic_index(bld
, instr
);
4323 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4324 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4326 fs_reg data
= get_nir_src(instr
->src
[0]);
4327 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4329 assert(nir_intrinsic_write_mask(instr
) ==
4330 (1u << instr
->num_components
) - 1);
4331 if (nir_intrinsic_align(instr
) >= 4) {
4332 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4333 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4334 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4335 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4336 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4337 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4339 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4340 assert(nir_src_num_components(instr
->src
[0]) == 1);
4341 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4343 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4344 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4346 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4347 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4352 case nir_intrinsic_store_output
: {
4353 fs_reg src
= get_nir_src(instr
->src
[0]);
4355 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4356 unsigned num_components
= instr
->num_components
;
4357 unsigned first_component
= nir_intrinsic_component(instr
);
4358 if (nir_src_bit_size(instr
->src
[0]) == 64) {
4359 src
= shuffle_for_32bit_write(bld
, src
, 0, num_components
);
4360 num_components
*= 2;
4363 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4364 4 * store_offset
), src
.type
);
4365 for (unsigned j
= 0; j
< num_components
; j
++) {
4366 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4367 offset(src
, bld
, j
));
4372 case nir_intrinsic_ssbo_atomic_add
:
4373 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4375 case nir_intrinsic_ssbo_atomic_imin
:
4376 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4378 case nir_intrinsic_ssbo_atomic_umin
:
4379 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4381 case nir_intrinsic_ssbo_atomic_imax
:
4382 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4384 case nir_intrinsic_ssbo_atomic_umax
:
4385 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4387 case nir_intrinsic_ssbo_atomic_and
:
4388 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4390 case nir_intrinsic_ssbo_atomic_or
:
4391 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4393 case nir_intrinsic_ssbo_atomic_xor
:
4394 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4396 case nir_intrinsic_ssbo_atomic_exchange
:
4397 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4399 case nir_intrinsic_ssbo_atomic_comp_swap
:
4400 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4402 case nir_intrinsic_ssbo_atomic_fmin
:
4403 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4405 case nir_intrinsic_ssbo_atomic_fmax
:
4406 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4408 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4409 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4412 case nir_intrinsic_get_buffer_size
: {
4413 assert(nir_src_num_components(instr
->src
[0]) == 1);
4414 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4415 nir_src_as_uint(instr
->src
[0]) : 0;
4417 /* A resinfo's sampler message is used to get the buffer size. The
4418 * SIMD8's writeback message consists of four registers and SIMD16's
4419 * writeback message consists of 8 destination registers (two per each
4420 * component). Because we are only interested on the first channel of
4421 * the first returned component, where resinfo returns the buffer size
4422 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4423 * the dispatch width.
4425 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4426 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4427 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4430 ubld
.MOV(src_payload
, brw_imm_d(0));
4432 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4433 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4434 src_payload
, brw_imm_ud(index
));
4435 inst
->header_size
= 0;
4437 inst
->size_written
= 4 * REG_SIZE
;
4439 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4441 * "Out-of-bounds checking is always performed at a DWord granularity. If
4442 * any part of the DWord is out-of-bounds then the whole DWord is
4443 * considered out-of-bounds."
4445 * This implies that types with size smaller than 4-bytes need to be
4446 * padded if they don't complete the last dword of the buffer. But as we
4447 * need to maintain the original size we need to reverse the padding
4448 * calculation to return the correct size to know the number of elements
4449 * of an unsized array. As we stored in the last two bits of the surface
4450 * size the needed padding for the buffer, we calculate here the
4451 * original buffer_size reversing the surface_size calculation:
4453 * surface_size = isl_align(buffer_size, 4) +
4454 * (isl_align(buffer_size) - buffer_size)
4456 * buffer_size = surface_size & ~3 - surface_size & 3
4459 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4460 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4461 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4463 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4464 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4465 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4467 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4471 case nir_intrinsic_load_subgroup_invocation
:
4472 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4473 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4476 case nir_intrinsic_load_subgroup_eq_mask
:
4477 case nir_intrinsic_load_subgroup_ge_mask
:
4478 case nir_intrinsic_load_subgroup_gt_mask
:
4479 case nir_intrinsic_load_subgroup_le_mask
:
4480 case nir_intrinsic_load_subgroup_lt_mask
:
4481 unreachable("not reached");
4483 case nir_intrinsic_vote_any
: {
4484 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4486 /* The any/all predicates do not consider channel enables. To prevent
4487 * dead channels from affecting the result, we initialize the flag with
4488 * with the identity value for the logical operation.
4490 if (dispatch_width
== 32) {
4491 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4492 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4495 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4497 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4499 /* For some reason, the any/all predicates don't work properly with
4500 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4501 * doesn't read the correct subset of the flag register and you end up
4502 * getting garbage in the second half. Work around this by using a pair
4503 * of 1-wide MOVs and scattering the result.
4505 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4506 ubld
.MOV(res1
, brw_imm_d(0));
4507 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4508 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4509 BRW_PREDICATE_ALIGN1_ANY32H
,
4510 ubld
.MOV(res1
, brw_imm_d(-1)));
4512 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4515 case nir_intrinsic_vote_all
: {
4516 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4518 /* The any/all predicates do not consider channel enables. To prevent
4519 * dead channels from affecting the result, we initialize the flag with
4520 * with the identity value for the logical operation.
4522 if (dispatch_width
== 32) {
4523 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4524 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4525 brw_imm_ud(0xffffffff));
4527 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4529 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4531 /* For some reason, the any/all predicates don't work properly with
4532 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4533 * doesn't read the correct subset of the flag register and you end up
4534 * getting garbage in the second half. Work around this by using a pair
4535 * of 1-wide MOVs and scattering the result.
4537 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4538 ubld
.MOV(res1
, brw_imm_d(0));
4539 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4540 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4541 BRW_PREDICATE_ALIGN1_ALL32H
,
4542 ubld
.MOV(res1
, brw_imm_d(-1)));
4544 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4547 case nir_intrinsic_vote_feq
:
4548 case nir_intrinsic_vote_ieq
: {
4549 fs_reg value
= get_nir_src(instr
->src
[0]);
4550 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4551 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4552 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4553 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4556 fs_reg uniformized
= bld
.emit_uniformize(value
);
4557 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4559 /* The any/all predicates do not consider channel enables. To prevent
4560 * dead channels from affecting the result, we initialize the flag with
4561 * with the identity value for the logical operation.
4563 if (dispatch_width
== 32) {
4564 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4565 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4566 brw_imm_ud(0xffffffff));
4568 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4570 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4572 /* For some reason, the any/all predicates don't work properly with
4573 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4574 * doesn't read the correct subset of the flag register and you end up
4575 * getting garbage in the second half. Work around this by using a pair
4576 * of 1-wide MOVs and scattering the result.
4578 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4579 ubld
.MOV(res1
, brw_imm_d(0));
4580 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4581 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4582 BRW_PREDICATE_ALIGN1_ALL32H
,
4583 ubld
.MOV(res1
, brw_imm_d(-1)));
4585 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4589 case nir_intrinsic_ballot
: {
4590 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4591 BRW_REGISTER_TYPE_UD
);
4592 struct brw_reg flag
= brw_flag_reg(0, 0);
4593 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4594 * as f0.0. This is a problem for fragment programs as we currently use
4595 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4596 * programs yet so this isn't a problem. When we do, something will
4599 if (dispatch_width
== 32)
4600 flag
.type
= BRW_REGISTER_TYPE_UD
;
4602 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4603 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4605 if (instr
->dest
.ssa
.bit_size
> 32) {
4606 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4608 dest
.type
= BRW_REGISTER_TYPE_UD
;
4610 bld
.MOV(dest
, flag
);
4614 case nir_intrinsic_read_invocation
: {
4615 const fs_reg value
= get_nir_src(instr
->src
[0]);
4616 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4617 fs_reg tmp
= bld
.vgrf(value
.type
);
4619 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4620 bld
.emit_uniformize(invocation
));
4622 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4626 case nir_intrinsic_read_first_invocation
: {
4627 const fs_reg value
= get_nir_src(instr
->src
[0]);
4628 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4632 case nir_intrinsic_shuffle
: {
4633 const fs_reg value
= get_nir_src(instr
->src
[0]);
4634 const fs_reg index
= get_nir_src(instr
->src
[1]);
4636 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4640 case nir_intrinsic_first_invocation
: {
4641 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4642 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4643 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4644 fs_reg(component(tmp
, 0)));
4648 case nir_intrinsic_quad_broadcast
: {
4649 const fs_reg value
= get_nir_src(instr
->src
[0]);
4650 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4652 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4653 value
, brw_imm_ud(index
), brw_imm_ud(4));
4657 case nir_intrinsic_quad_swap_horizontal
: {
4658 const fs_reg value
= get_nir_src(instr
->src
[0]);
4659 const fs_reg tmp
= bld
.vgrf(value
.type
);
4660 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4662 const fs_reg src_left
= horiz_stride(value
, 2);
4663 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4664 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4665 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4667 ubld
.MOV(tmp_left
, src_right
);
4668 ubld
.MOV(tmp_right
, src_left
);
4670 bld
.MOV(retype(dest
, value
.type
), tmp
);
4674 case nir_intrinsic_quad_swap_vertical
: {
4675 const fs_reg value
= get_nir_src(instr
->src
[0]);
4676 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4677 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4678 const fs_reg tmp
= bld
.vgrf(value
.type
);
4679 const fs_builder ubld
= bld
.exec_all();
4680 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4681 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4682 bld
.MOV(retype(dest
, value
.type
), tmp
);
4684 /* For larger data types, we have to either emit dispatch_width many
4685 * MOVs or else fall back to doing indirects.
4687 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4688 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4690 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4695 case nir_intrinsic_quad_swap_diagonal
: {
4696 const fs_reg value
= get_nir_src(instr
->src
[0]);
4697 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4698 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4699 const fs_reg tmp
= bld
.vgrf(value
.type
);
4700 const fs_builder ubld
= bld
.exec_all();
4701 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4702 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4703 bld
.MOV(retype(dest
, value
.type
), tmp
);
4705 /* For larger data types, we have to either emit dispatch_width many
4706 * MOVs or else fall back to doing indirects.
4708 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4709 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4711 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4716 case nir_intrinsic_reduce
: {
4717 fs_reg src
= get_nir_src(instr
->src
[0]);
4718 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4719 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4720 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4721 cluster_size
= dispatch_width
;
4723 /* Figure out the source type */
4724 src
.type
= brw_type_for_nir_type(devinfo
,
4725 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4726 nir_src_bit_size(instr
->src
[0])));
4728 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4729 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4730 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4732 /* Set up a register for all of our scratching around and initialize it
4733 * to reduction operation's identity value.
4735 fs_reg scan
= bld
.vgrf(src
.type
);
4736 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4738 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4740 dest
.type
= src
.type
;
4741 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4742 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4743 * the distance between clusters is at least 2 GRFs. In this case,
4744 * we don't need the weird striding of the CLUSTER_BROADCAST
4745 * instruction and can just do regular MOVs.
4747 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
4748 const unsigned groups
=
4749 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
4750 const unsigned group_size
= dispatch_width
/ groups
;
4751 for (unsigned i
= 0; i
< groups
; i
++) {
4752 const unsigned cluster
= (i
* group_size
) / cluster_size
;
4753 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
4754 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
4755 component(scan
, comp
));
4758 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
4759 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
4764 case nir_intrinsic_inclusive_scan
:
4765 case nir_intrinsic_exclusive_scan
: {
4766 fs_reg src
= get_nir_src(instr
->src
[0]);
4767 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4769 /* Figure out the source type */
4770 src
.type
= brw_type_for_nir_type(devinfo
,
4771 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4772 nir_src_bit_size(instr
->src
[0])));
4774 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4775 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4776 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4778 /* Set up a register for all of our scratching around and initialize it
4779 * to reduction operation's identity value.
4781 fs_reg scan
= bld
.vgrf(src
.type
);
4782 const fs_builder allbld
= bld
.exec_all();
4783 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4785 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
4786 /* Exclusive scan is a bit harder because we have to do an annoying
4787 * shift of the contents before we can begin. To make things worse,
4788 * we can't do this with a normal stride; we have to use indirects.
4790 fs_reg shifted
= bld
.vgrf(src
.type
);
4791 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4792 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4794 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
4795 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
4799 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
4801 bld
.MOV(retype(dest
, src
.type
), scan
);
4805 case nir_intrinsic_begin_invocation_interlock
: {
4806 const fs_builder ubld
= bld
.group(8, 0);
4807 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4809 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
)->size_written
= 2 *
4815 case nir_intrinsic_end_invocation_interlock
: {
4816 /* We don't need to do anything here */
4821 unreachable("unknown intrinsic");
4826 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4827 int op
, nir_intrinsic_instr
*instr
)
4829 if (stage
== MESA_SHADER_FRAGMENT
)
4830 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4833 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4834 dest
= get_nir_dest(instr
->dest
);
4836 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4837 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4838 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4839 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4840 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4843 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4844 data
= get_nir_src(instr
->src
[2]);
4846 if (op
== BRW_AOP_CMPWR
) {
4847 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4848 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4849 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4852 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4854 /* Emit the actual atomic operation */
4856 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4857 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4861 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
4862 int op
, nir_intrinsic_instr
*instr
)
4864 if (stage
== MESA_SHADER_FRAGMENT
)
4865 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4868 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4869 dest
= get_nir_dest(instr
->dest
);
4871 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4872 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
4873 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4874 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4875 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4877 fs_reg data
= get_nir_src(instr
->src
[2]);
4878 if (op
== BRW_AOP_FCMPWR
) {
4879 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4880 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
4881 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4884 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4886 /* Emit the actual atomic operation */
4888 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4889 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4893 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4894 int op
, nir_intrinsic_instr
*instr
)
4897 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4898 dest
= get_nir_dest(instr
->dest
);
4900 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4901 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4902 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4903 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4906 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4907 data
= get_nir_src(instr
->src
[1]);
4908 if (op
== BRW_AOP_CMPWR
) {
4909 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4910 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4911 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4914 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4916 /* Get the offset */
4917 if (nir_src_is_const(instr
->src
[0])) {
4918 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4919 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4921 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4922 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4923 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4924 brw_imm_ud(instr
->const_index
[0]));
4927 /* Emit the actual atomic operation operation */
4929 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
4930 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4934 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
4935 int op
, nir_intrinsic_instr
*instr
)
4938 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4939 dest
= get_nir_dest(instr
->dest
);
4941 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4942 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
4943 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4944 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4946 fs_reg data
= get_nir_src(instr
->src
[1]);
4947 if (op
== BRW_AOP_FCMPWR
) {
4948 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4949 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4950 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4953 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4955 /* Get the offset */
4956 if (nir_src_is_const(instr
->src
[0])) {
4957 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
4958 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
4960 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
4961 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
4962 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4963 brw_imm_ud(instr
->const_index
[0]));
4966 /* Emit the actual atomic operation operation */
4968 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
4969 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4973 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
4974 int op
, nir_intrinsic_instr
*instr
)
4976 if (stage
== MESA_SHADER_FRAGMENT
)
4977 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4980 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4981 dest
= get_nir_dest(instr
->dest
);
4983 fs_reg addr
= get_nir_src(instr
->src
[0]);
4986 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
4987 data
= get_nir_src(instr
->src
[1]);
4989 if (op
== BRW_AOP_CMPWR
) {
4990 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4991 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
4992 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4996 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
4997 dest
, addr
, data
, brw_imm_ud(op
));
5001 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5002 int op
, nir_intrinsic_instr
*instr
)
5004 if (stage
== MESA_SHADER_FRAGMENT
)
5005 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5007 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5008 fs_reg dest
= get_nir_dest(instr
->dest
);
5010 fs_reg addr
= get_nir_src(instr
->src
[0]);
5012 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5013 fs_reg data
= get_nir_src(instr
->src
[1]);
5015 if (op
== BRW_AOP_FCMPWR
) {
5016 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5017 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5018 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5022 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5023 dest
, addr
, data
, brw_imm_ud(op
));
5027 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5029 unsigned texture
= instr
->texture_index
;
5030 unsigned sampler
= instr
->sampler_index
;
5032 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5034 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5035 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5037 int lod_components
= 0;
5039 /* The hardware requires a LOD for buffer textures */
5040 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5041 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5043 uint32_t header_bits
= 0;
5044 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5045 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5046 switch (instr
->src
[i
].src_type
) {
5047 case nir_tex_src_bias
:
5048 srcs
[TEX_LOGICAL_SRC_LOD
] =
5049 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5051 case nir_tex_src_comparator
:
5052 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5054 case nir_tex_src_coord
:
5055 switch (instr
->op
) {
5057 case nir_texop_txf_ms
:
5058 case nir_texop_txf_ms_mcs
:
5059 case nir_texop_samples_identical
:
5060 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5063 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5067 case nir_tex_src_ddx
:
5068 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5069 lod_components
= nir_tex_instr_src_size(instr
, i
);
5071 case nir_tex_src_ddy
:
5072 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5074 case nir_tex_src_lod
:
5075 switch (instr
->op
) {
5077 srcs
[TEX_LOGICAL_SRC_LOD
] =
5078 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5081 srcs
[TEX_LOGICAL_SRC_LOD
] =
5082 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5085 srcs
[TEX_LOGICAL_SRC_LOD
] =
5086 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5090 case nir_tex_src_min_lod
:
5091 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5092 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5094 case nir_tex_src_ms_index
:
5095 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5098 case nir_tex_src_offset
: {
5099 uint32_t offset_bits
= 0;
5100 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5101 header_bits
|= offset_bits
;
5103 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5104 retype(src
, BRW_REGISTER_TYPE_D
);
5109 case nir_tex_src_projector
:
5110 unreachable("should be lowered");
5112 case nir_tex_src_texture_offset
: {
5113 /* Emit code to evaluate the actual indexing expression */
5114 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5115 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5116 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5120 case nir_tex_src_sampler_offset
: {
5121 /* Emit code to evaluate the actual indexing expression */
5122 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5123 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5124 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5128 case nir_tex_src_ms_mcs
:
5129 assert(instr
->op
== nir_texop_txf_ms
);
5130 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5133 case nir_tex_src_plane
: {
5134 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5135 const uint32_t texture_index
=
5136 instr
->texture_index
+
5137 stage_prog_data
->binding_table
.plane_start
[plane
] -
5138 stage_prog_data
->binding_table
.texture_start
;
5140 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5145 unreachable("unknown texture source");
5149 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5150 (instr
->op
== nir_texop_txf_ms
||
5151 instr
->op
== nir_texop_samples_identical
)) {
5152 if (devinfo
->gen
>= 7 &&
5153 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5154 srcs
[TEX_LOGICAL_SRC_MCS
] =
5155 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5156 instr
->coord_components
,
5157 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
5159 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5163 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5164 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5166 bool shader_supports_implicit_lod
= stage
== MESA_SHADER_FRAGMENT
||
5167 (stage
== MESA_SHADER_COMPUTE
&&
5168 nir
->info
.cs
.derivative_group
!= DERIVATIVE_GROUP_NONE
);
5171 switch (instr
->op
) {
5173 opcode
= shader_supports_implicit_lod
?
5174 SHADER_OPCODE_TEX_LOGICAL
: SHADER_OPCODE_TXL_LOGICAL
;
5177 opcode
= FS_OPCODE_TXB_LOGICAL
;
5180 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5183 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5186 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5188 case nir_texop_txf_ms
:
5189 if ((key_tex
->msaa_16
& (1 << sampler
)))
5190 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5192 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5194 case nir_texop_txf_ms_mcs
:
5195 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5197 case nir_texop_query_levels
:
5199 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5202 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5205 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5206 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5208 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5210 case nir_texop_texture_samples
:
5211 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5213 case nir_texop_samples_identical
: {
5214 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5216 /* If mcs is an immediate value, it means there is no MCS. In that case
5217 * just return false.
5219 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5220 bld
.MOV(dst
, brw_imm_ud(0u));
5221 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5222 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5223 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5224 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5225 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5227 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5228 BRW_CONDITIONAL_EQ
);
5233 unreachable("unknown texture opcode");
5236 if (instr
->op
== nir_texop_tg4
) {
5237 if (instr
->component
== 1 &&
5238 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5239 /* gather4 sampler is broken for green channel on RG32F --
5240 * we must ask for blue instead.
5242 header_bits
|= 2 << 16;
5244 header_bits
|= instr
->component
<< 16;
5248 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5249 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5250 inst
->offset
= header_bits
;
5252 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5253 if (devinfo
->gen
>= 9 &&
5254 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5255 unsigned write_mask
= instr
->dest
.is_ssa
?
5256 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5257 (1 << dest_size
) - 1;
5258 assert(write_mask
!= 0); /* dead code should have been eliminated */
5259 inst
->size_written
= util_last_bit(write_mask
) *
5260 inst
->dst
.component_size(inst
->exec_size
);
5262 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5265 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5266 inst
->shadow_compare
= true;
5268 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5269 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5272 for (unsigned i
= 0; i
< dest_size
; i
++)
5273 nir_dest
[i
] = offset(dst
, bld
, i
);
5275 if (instr
->op
== nir_texop_query_levels
) {
5276 /* # levels is in .w */
5277 nir_dest
[0] = offset(dst
, bld
, 3);
5278 } else if (instr
->op
== nir_texop_txs
&&
5279 dest_size
>= 3 && devinfo
->gen
< 7) {
5280 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5281 fs_reg depth
= offset(dst
, bld
, 2);
5282 nir_dest
[2] = vgrf(glsl_type::int_type
);
5283 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5286 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5290 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5292 switch (instr
->type
) {
5293 case nir_jump_break
:
5294 bld
.emit(BRW_OPCODE_BREAK
);
5296 case nir_jump_continue
:
5297 bld
.emit(BRW_OPCODE_CONTINUE
);
5299 case nir_jump_return
:
5301 unreachable("unknown jump");
5306 * This helper takes a source register and un/shuffles it into the destination
5309 * If source type size is smaller than destination type size the operation
5310 * needed is a component shuffle. The opposite case would be an unshuffle. If
5311 * source/destination type size is equal a shuffle is done that would be
5312 * equivalent to a simple MOV.
5314 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5315 * components .xyz 16-bit vector on SIMD8 would be.
5317 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5318 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5320 * This helper will return the following 2 32-bit components with the 16-bit
5323 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5324 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5326 * For unshuffle, the example would be the opposite, a 64-bit type source
5327 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5330 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5331 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5332 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5333 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5335 * The returned result would be the following 4 32-bit components unshuffled:
5337 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5338 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5339 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5340 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5342 * - Source and destination register must not be overlapped.
5343 * - components units are measured in terms of the smaller type between
5344 * source and destination because we are un/shuffling the smaller
5345 * components from/into the bigger ones.
5346 * - first_component parameter allows skipping source components.
5349 shuffle_src_to_dst(const fs_builder
&bld
,
5352 uint32_t first_component
,
5353 uint32_t components
)
5355 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5356 assert(!regions_overlap(dst
,
5357 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5358 offset(src
, bld
, first_component
),
5359 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5360 for (unsigned i
= 0; i
< components
; i
++) {
5361 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5362 offset(src
, bld
, i
+ first_component
));
5364 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5365 /* Source is shuffled into destination */
5366 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5367 assert(!regions_overlap(dst
,
5368 type_sz(dst
.type
) * bld
.dispatch_width() *
5369 DIV_ROUND_UP(components
, size_ratio
),
5370 offset(src
, bld
, first_component
),
5371 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5373 brw_reg_type shuffle_type
=
5374 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5375 BRW_REGISTER_TYPE_D
);
5376 for (unsigned i
= 0; i
< components
; i
++) {
5377 fs_reg shuffle_component_i
=
5378 subscript(offset(dst
, bld
, i
/ size_ratio
),
5379 shuffle_type
, i
% size_ratio
);
5380 bld
.MOV(shuffle_component_i
,
5381 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5384 /* Source is unshuffled into destination */
5385 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5386 assert(!regions_overlap(dst
,
5387 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5388 offset(src
, bld
, first_component
/ size_ratio
),
5389 type_sz(src
.type
) * bld
.dispatch_width() *
5390 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5393 brw_reg_type shuffle_type
=
5394 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5395 BRW_REGISTER_TYPE_D
);
5396 for (unsigned i
= 0; i
< components
; i
++) {
5397 fs_reg shuffle_component_i
=
5398 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5399 shuffle_type
, (first_component
+ i
) % size_ratio
);
5400 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5401 shuffle_component_i
);
5407 shuffle_from_32bit_read(const fs_builder
&bld
,
5410 uint32_t first_component
,
5411 uint32_t components
)
5413 assert(type_sz(src
.type
) == 4);
5415 /* This function takes components in units of the destination type while
5416 * shuffle_src_to_dst takes components in units of the smallest type
5418 if (type_sz(dst
.type
) > 4) {
5419 assert(type_sz(dst
.type
) == 8);
5420 first_component
*= 2;
5424 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5428 shuffle_for_32bit_write(const fs_builder
&bld
,
5430 uint32_t first_component
,
5431 uint32_t components
)
5433 fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_D
,
5434 DIV_ROUND_UP (components
* type_sz(src
.type
), 4));
5435 /* This function takes components in units of the source type while
5436 * shuffle_src_to_dst takes components in units of the smallest type
5438 if (type_sz(src
.type
) > 4) {
5439 assert(type_sz(src
.type
) == 8);
5440 first_component
*= 2;
5444 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5450 setup_imm_df(const fs_builder
&bld
, double v
)
5452 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5453 assert(devinfo
->gen
>= 7);
5455 if (devinfo
->gen
>= 8)
5456 return brw_imm_df(v
);
5458 /* gen7.5 does not support DF immediates straighforward but the DIM
5459 * instruction allows to set the 64-bit immediate value.
5461 if (devinfo
->is_haswell
) {
5462 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5463 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5464 ubld
.DIM(dst
, brw_imm_df(v
));
5465 return component(dst
, 0);
5468 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5469 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5470 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5472 * Alternatively, we could also produce a normal VGRF (without stride 0)
5473 * by writing to all the channels in the VGRF, however, that would hit the
5474 * gen7 bug where we have to split writes that span more than 1 register
5475 * into instructions with a width of 4 (otherwise the write to the second
5476 * register written runs into an execmask hardware bug) which isn't very
5489 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5490 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5491 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5492 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5494 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5498 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5500 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5501 bld
.MOV(tmp
, brw_imm_w(v
));
5506 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5508 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5509 bld
.MOV(tmp
, brw_imm_uw(v
));