2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
28 #include "nir_search_helpers.h"
29 #include "util/u_math.h"
30 #include "util/bitscan.h"
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 nir_emit_impl(nir_shader_get_entrypoint((nir_shader
*)nir
));
48 fs_visitor::nir_setup_outputs()
50 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
53 unsigned vec4s
[VARYING_SLOT_TESS_MAX
] = { 0, };
55 /* Calculate the size of output registers in a separate pass, before
56 * allocating them. With ARB_enhanced_layouts, multiple output variables
57 * may occupy the same slot, but have different type sizes.
59 nir_foreach_variable(var
, &nir
->outputs
) {
60 const int loc
= var
->data
.driver_location
;
61 const unsigned var_vec4s
=
62 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
63 : type_size_vec4(var
->type
, true);
64 vec4s
[loc
] = MAX2(vec4s
[loc
], var_vec4s
);
67 for (unsigned loc
= 0; loc
< ARRAY_SIZE(vec4s
);) {
68 if (vec4s
[loc
] == 0) {
73 unsigned reg_size
= vec4s
[loc
];
75 /* Check if there are any ranges that start within this range and extend
76 * past it. If so, include them in this allocation.
78 for (unsigned i
= 1; i
< reg_size
; i
++)
79 reg_size
= MAX2(vec4s
[i
+ loc
] + i
, reg_size
);
81 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * reg_size
);
82 for (unsigned i
= 0; i
< reg_size
; i
++)
83 outputs
[loc
+ i
] = offset(reg
, bld
, 4 * i
);
90 fs_visitor::nir_setup_uniforms()
92 /* Only the first compile gets to set up uniforms. */
93 if (push_constant_loc
) {
94 assert(pull_constant_loc
);
98 uniforms
= nir
->num_uniforms
/ 4;
100 if (stage
== MESA_SHADER_COMPUTE
) {
101 /* Add a uniform for the thread local id. It must be the last uniform
104 assert(uniforms
== prog_data
->nr_params
);
105 uint32_t *param
= brw_stage_prog_data_add_params(prog_data
, 1);
106 *param
= BRW_PARAM_BUILTIN_SUBGROUP_ID
;
107 subgroup_id
= fs_reg(UNIFORM
, uniforms
++, BRW_REGISTER_TYPE_UD
);
112 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
116 nir_foreach_instr(instr
, block
) {
117 if (instr
->type
!= nir_instr_type_intrinsic
)
120 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
121 switch (intrin
->intrinsic
) {
122 case nir_intrinsic_load_vertex_id
:
123 case nir_intrinsic_load_base_vertex
:
124 unreachable("should be lowered by nir_lower_system_values().");
126 case nir_intrinsic_load_vertex_id_zero_base
:
127 case nir_intrinsic_load_is_indexed_draw
:
128 case nir_intrinsic_load_first_vertex
:
129 case nir_intrinsic_load_instance_id
:
130 case nir_intrinsic_load_base_instance
:
131 case nir_intrinsic_load_draw_id
:
132 unreachable("should be lowered by brw_nir_lower_vs_inputs().");
134 case nir_intrinsic_load_invocation_id
:
135 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
137 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
138 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
139 if (reg
->file
== BAD_FILE
) {
140 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
141 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
142 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
143 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
148 case nir_intrinsic_load_sample_pos
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_samplepos_setup();
155 case nir_intrinsic_load_sample_id
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
158 if (reg
->file
== BAD_FILE
)
159 *reg
= *v
->emit_sampleid_setup();
162 case nir_intrinsic_load_sample_mask_in
:
163 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
164 assert(v
->devinfo
->gen
>= 7);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_samplemaskin_setup();
170 case nir_intrinsic_load_work_group_id
:
171 assert(v
->stage
== MESA_SHADER_COMPUTE
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
173 if (reg
->file
== BAD_FILE
)
174 *reg
= *v
->emit_cs_work_group_id_setup();
177 case nir_intrinsic_load_helper_invocation
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
180 if (reg
->file
== BAD_FILE
) {
181 const fs_builder abld
=
182 v
->bld
.annotate("gl_HelperInvocation", NULL
);
184 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
185 * pixel mask is in g1.7 of the thread payload.
187 * We move the per-channel pixel enable bit to the low bit of each
188 * channel by shifting the byte containing the pixel mask by the
189 * vector immediate 0x76543210UV.
191 * The region of <1,8,0> reads only 1 byte (the pixel masks for
192 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
193 * masks for 2 and 3) in SIMD16.
195 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
197 for (unsigned i
= 0; i
< DIV_ROUND_UP(v
->dispatch_width
, 16); i
++) {
198 const fs_builder hbld
= abld
.group(MIN2(16, v
->dispatch_width
), i
);
199 hbld
.SHR(offset(shifted
, hbld
, i
),
200 stride(retype(brw_vec1_grf(1 + i
, 7),
201 BRW_REGISTER_TYPE_UB
),
203 brw_imm_v(0x76543210));
206 /* A set bit in the pixel mask means the channel is enabled, but
207 * that is the opposite of gl_HelperInvocation so we need to invert
210 * The negate source-modifier bit of logical instructions on Gen8+
211 * performs 1's complement negation, so we can use that instead of
214 fs_reg inverted
= negate(shifted
);
215 if (v
->devinfo
->gen
< 8) {
216 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
217 abld
.NOT(inverted
, shifted
);
220 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
221 * with 1 and negating.
223 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
224 abld
.AND(anded
, inverted
, brw_imm_uw(1));
226 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
227 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
241 fs_visitor::nir_emit_system_values()
243 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
244 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
245 nir_system_values
[i
] = fs_reg();
248 /* Always emit SUBGROUP_INVOCATION. Dead code will clean it up if we
249 * never end up using it.
252 const fs_builder abld
= bld
.annotate("gl_SubgroupInvocation", NULL
);
253 fs_reg
®
= nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
];
254 reg
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
256 const fs_builder allbld8
= abld
.group(8, 0).exec_all();
257 allbld8
.MOV(reg
, brw_imm_v(0x76543210));
258 if (dispatch_width
> 8)
259 allbld8
.ADD(byte_offset(reg
, 16), reg
, brw_imm_uw(8u));
260 if (dispatch_width
> 16) {
261 const fs_builder allbld16
= abld
.group(16, 0).exec_all();
262 allbld16
.ADD(byte_offset(reg
, 32), reg
, brw_imm_uw(16u));
266 nir_function_impl
*impl
= nir_shader_get_entrypoint((nir_shader
*)nir
);
267 nir_foreach_block(block
, impl
)
268 emit_system_values_block(block
, this);
272 * Returns a type based on a reference_type (word, float, half-float) and a
275 * Reference BRW_REGISTER_TYPE are HF,F,DF,W,D,UW,UD.
277 * @FIXME: 64-bit return types are always DF on integer types to maintain
278 * compability with uses of DF previously to the introduction of int64
282 brw_reg_type_from_bit_size(const unsigned bit_size
,
283 const brw_reg_type reference_type
)
285 switch(reference_type
) {
286 case BRW_REGISTER_TYPE_HF
:
287 case BRW_REGISTER_TYPE_F
:
288 case BRW_REGISTER_TYPE_DF
:
291 return BRW_REGISTER_TYPE_HF
;
293 return BRW_REGISTER_TYPE_F
;
295 return BRW_REGISTER_TYPE_DF
;
297 unreachable("Invalid bit size");
299 case BRW_REGISTER_TYPE_B
:
300 case BRW_REGISTER_TYPE_W
:
301 case BRW_REGISTER_TYPE_D
:
302 case BRW_REGISTER_TYPE_Q
:
305 return BRW_REGISTER_TYPE_B
;
307 return BRW_REGISTER_TYPE_W
;
309 return BRW_REGISTER_TYPE_D
;
311 return BRW_REGISTER_TYPE_Q
;
313 unreachable("Invalid bit size");
315 case BRW_REGISTER_TYPE_UB
:
316 case BRW_REGISTER_TYPE_UW
:
317 case BRW_REGISTER_TYPE_UD
:
318 case BRW_REGISTER_TYPE_UQ
:
321 return BRW_REGISTER_TYPE_UB
;
323 return BRW_REGISTER_TYPE_UW
;
325 return BRW_REGISTER_TYPE_UD
;
327 return BRW_REGISTER_TYPE_UQ
;
329 unreachable("Invalid bit size");
332 unreachable("Unknown type");
337 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
339 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
340 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
341 nir_locals
[i
] = fs_reg();
344 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
345 unsigned array_elems
=
346 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
347 unsigned size
= array_elems
* reg
->num_components
;
348 const brw_reg_type reg_type
= reg
->bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
349 brw_reg_type_from_bit_size(reg
->bit_size
, BRW_REGISTER_TYPE_F
);
350 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
353 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
356 nir_emit_cf_list(&impl
->body
);
360 fs_visitor::nir_emit_cf_list(exec_list
*list
)
362 exec_list_validate(list
);
363 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
364 switch (node
->type
) {
366 nir_emit_if(nir_cf_node_as_if(node
));
369 case nir_cf_node_loop
:
370 nir_emit_loop(nir_cf_node_as_loop(node
));
373 case nir_cf_node_block
:
374 nir_emit_block(nir_cf_node_as_block(node
));
378 unreachable("Invalid CFG node block");
384 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
389 /* If the condition has the form !other_condition, use other_condition as
390 * the source, but invert the predicate on the if instruction.
392 nir_alu_instr
*cond
= nir_src_as_alu_instr(if_stmt
->condition
);
393 if (cond
!= NULL
&& cond
->op
== nir_op_inot
) {
394 assert(!cond
->src
[0].negate
);
395 assert(!cond
->src
[0].abs
);
398 cond_reg
= get_nir_src(cond
->src
[0].src
);
401 cond_reg
= get_nir_src(if_stmt
->condition
);
404 /* first, put the condition into f0 */
405 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
406 retype(cond_reg
, BRW_REGISTER_TYPE_D
));
407 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
409 bld
.IF(BRW_PREDICATE_NORMAL
)->predicate_inverse
= invert
;
411 nir_emit_cf_list(&if_stmt
->then_list
);
413 if (!nir_cf_list_is_empty_block(&if_stmt
->else_list
)) {
414 bld
.emit(BRW_OPCODE_ELSE
);
415 nir_emit_cf_list(&if_stmt
->else_list
);
418 bld
.emit(BRW_OPCODE_ENDIF
);
420 if (devinfo
->gen
< 7)
421 limit_dispatch_width(16, "Non-uniform control flow unsupported "
426 fs_visitor::nir_emit_loop(nir_loop
*loop
)
428 bld
.emit(BRW_OPCODE_DO
);
430 nir_emit_cf_list(&loop
->body
);
432 bld
.emit(BRW_OPCODE_WHILE
);
434 if (devinfo
->gen
< 7)
435 limit_dispatch_width(16, "Non-uniform control flow unsupported "
440 fs_visitor::nir_emit_block(nir_block
*block
)
442 nir_foreach_instr(instr
, block
) {
443 nir_emit_instr(instr
);
448 fs_visitor::nir_emit_instr(nir_instr
*instr
)
450 const fs_builder abld
= bld
.annotate(NULL
, instr
);
452 switch (instr
->type
) {
453 case nir_instr_type_alu
:
454 nir_emit_alu(abld
, nir_instr_as_alu(instr
), true);
457 case nir_instr_type_deref
:
458 unreachable("All derefs should've been lowered");
461 case nir_instr_type_intrinsic
:
463 case MESA_SHADER_VERTEX
:
464 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
466 case MESA_SHADER_TESS_CTRL
:
467 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 case MESA_SHADER_TESS_EVAL
:
470 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 case MESA_SHADER_GEOMETRY
:
473 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
475 case MESA_SHADER_FRAGMENT
:
476 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 case MESA_SHADER_COMPUTE
:
479 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
482 unreachable("unsupported shader stage");
486 case nir_instr_type_tex
:
487 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
490 case nir_instr_type_load_const
:
491 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
494 case nir_instr_type_ssa_undef
:
495 /* We create a new VGRF for undefs on every use (by handling
496 * them in get_nir_src()), rather than for each definition.
497 * This helps register coalescing eliminate MOVs from undef.
501 case nir_instr_type_jump
:
502 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
506 unreachable("unknown instruction type");
511 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
515 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
516 const fs_reg
&result
)
518 if (!instr
->src
[0].src
.is_ssa
||
519 !instr
->src
[0].src
.ssa
->parent_instr
)
522 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
525 nir_alu_instr
*src0
=
526 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
528 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
529 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
532 /* If either opcode has source modifiers, bail.
534 * TODO: We can potentially handle source modifiers if both of the opcodes
535 * we're combining are signed integers.
537 if (instr
->src
[0].abs
|| instr
->src
[0].negate
||
538 src0
->src
[0].abs
|| src0
->src
[0].negate
)
541 unsigned element
= nir_src_as_uint(src0
->src
[1].src
);
543 /* Element type to extract.*/
544 const brw_reg_type type
= brw_int_type(
545 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
546 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
548 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
549 op0
.type
= brw_type_for_nir_type(devinfo
,
550 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
551 nir_src_bit_size(src0
->src
[0].src
)));
552 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
554 set_saturate(instr
->dest
.saturate
,
555 bld
.MOV(result
, subscript(op0
, type
, element
)));
560 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
561 const fs_reg
&result
)
563 nir_intrinsic_instr
*src0
= nir_src_as_intrinsic(instr
->src
[0].src
);
564 if (src0
== NULL
|| src0
->intrinsic
!= nir_intrinsic_load_front_face
)
567 if (!nir_src_is_const(instr
->src
[1].src
) ||
568 !nir_src_is_const(instr
->src
[2].src
))
571 const float value1
= nir_src_as_float(instr
->src
[1].src
);
572 const float value2
= nir_src_as_float(instr
->src
[2].src
);
573 if (fabsf(value1
) != 1.0f
|| fabsf(value2
) != 1.0f
)
576 /* nir_opt_algebraic should have gotten rid of bcsel(b, a, a) */
577 assert(value1
== -value2
);
579 fs_reg tmp
= vgrf(glsl_type::int_type
);
581 if (devinfo
->gen
>= 6) {
582 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
583 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
585 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
587 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
588 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
590 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
592 * This negation looks like it's safe in practice, because bits 0:4 will
593 * surely be TRIANGLES
596 if (value1
== -1.0f
) {
600 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
601 g0
, brw_imm_uw(0x3f80));
603 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
604 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
606 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
608 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
609 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
611 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
613 * This negation looks like it's safe in practice, because bits 0:4 will
614 * surely be TRIANGLES
617 if (value1
== -1.0f
) {
621 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
623 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
629 emit_find_msb_using_lzd(const fs_builder
&bld
,
630 const fs_reg
&result
,
638 /* LZD of an absolute value source almost always does the right
639 * thing. There are two problem values:
641 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
642 * 0. However, findMSB(int(0x80000000)) == 30.
644 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
645 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
647 * For a value of zero or negative one, -1 will be returned.
649 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
650 * findMSB(-(1<<x)) should return x-1.
652 * For all negative number cases, including 0x80000000 and
653 * 0xffffffff, the correct value is obtained from LZD if instead of
654 * negating the (already negative) value the logical-not is used. A
655 * conditonal logical-not can be achieved in two instructions.
657 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
659 bld
.ASR(temp
, src
, brw_imm_d(31));
660 bld
.XOR(temp
, temp
, src
);
663 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
664 retype(temp
, BRW_REGISTER_TYPE_UD
));
666 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
667 * from the LSB side. Subtract the result from 31 to convert the MSB
668 * count into an LSB count. If no bits are set, LZD will return 32.
669 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
671 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
672 inst
->src
[0].negate
= true;
676 brw_rnd_mode_from_nir_op (const nir_op op
) {
678 case nir_op_f2f16_rtz
:
679 return BRW_RND_MODE_RTZ
;
680 case nir_op_f2f16_rtne
:
681 return BRW_RND_MODE_RTNE
;
683 unreachable("Operation doesn't support rounding mode");
688 fs_visitor::prepare_alu_destination_and_sources(const fs_builder
&bld
,
689 nir_alu_instr
*instr
,
694 need_dest
? get_nir_dest(instr
->dest
.dest
) : bld
.null_reg_ud();
696 result
.type
= brw_type_for_nir_type(devinfo
,
697 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
698 nir_dest_bit_size(instr
->dest
.dest
)));
700 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
701 op
[i
] = get_nir_src(instr
->src
[i
].src
);
702 op
[i
].type
= brw_type_for_nir_type(devinfo
,
703 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
704 nir_src_bit_size(instr
->src
[i
].src
)));
705 op
[i
].abs
= instr
->src
[i
].abs
;
706 op
[i
].negate
= instr
->src
[i
].negate
;
709 /* Move and vecN instrutions may still be vectored. Return the raw,
710 * vectored source and destination so that fs_visitor::nir_emit_alu can
711 * handle it. Other callers should not have to handle these kinds of
724 /* At this point, we have dealt with any instruction that operates on
725 * more than a single channel. Therefore, we can just adjust the source
726 * and destination registers for that channel and emit the instruction.
728 unsigned channel
= 0;
729 if (nir_op_infos
[instr
->op
].output_size
== 0) {
730 /* Since NIR is doing the scalarizing for us, we should only ever see
731 * vectorized operations with a single channel.
733 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
734 channel
= ffs(instr
->dest
.write_mask
) - 1;
736 result
= offset(result
, bld
, channel
);
739 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
740 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
741 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
748 fs_visitor::resolve_inot_sources(const fs_builder
&bld
, nir_alu_instr
*instr
,
751 for (unsigned i
= 0; i
< 2; i
++) {
752 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[i
].src
);
754 if (inot_instr
!= NULL
&& inot_instr
->op
== nir_op_inot
&&
755 !inot_instr
->src
[0].abs
&& !inot_instr
->src
[0].negate
) {
756 /* The source of the inot is now the source of instr. */
757 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
[i
], false);
759 assert(!op
[i
].negate
);
762 op
[i
] = resolve_source_modifiers(op
[i
]);
768 fs_visitor::try_emit_b2fi_of_inot(const fs_builder
&bld
,
770 nir_alu_instr
*instr
)
772 if (devinfo
->gen
< 6 || devinfo
->gen
>= 12)
775 nir_alu_instr
*inot_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
777 if (inot_instr
== NULL
|| inot_instr
->op
!= nir_op_inot
)
780 /* HF is also possible as a destination on BDW+. For nir_op_b2i, the set
781 * of valid size-changing combinations is a bit more complex.
783 * The source restriction is just because I was lazy about generating the
786 if (nir_dest_bit_size(instr
->dest
.dest
) != 32 ||
787 nir_src_bit_size(inot_instr
->src
[0].src
) != 32)
790 /* b2[fi](inot(a)) maps a=0 => 1, a=-1 => 0. Since a can only be 0 or -1,
791 * this is float(1 + a).
795 prepare_alu_destination_and_sources(bld
, inot_instr
, &op
, false);
797 /* Ignore the saturate modifier, if there is one. The result of the
798 * arithmetic can only be 0 or 1, so the clamping will do nothing anyway.
800 bld
.ADD(result
, op
, brw_imm_d(1));
806 * Emit code for nir_op_fsign possibly fused with a nir_op_fmul
808 * If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
809 * the source of \c instr that is a \c nir_op_fsign.
812 fs_visitor::emit_fsign(const fs_builder
&bld
, const nir_alu_instr
*instr
,
813 fs_reg result
, fs_reg
*op
, unsigned fsign_src
)
817 assert(instr
->op
== nir_op_fsign
|| instr
->op
== nir_op_fmul
);
818 assert(fsign_src
< nir_op_infos
[instr
->op
].num_inputs
);
820 if (instr
->op
!= nir_op_fsign
) {
821 const nir_alu_instr
*const fsign_instr
=
822 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
824 assert(!fsign_instr
->dest
.saturate
);
826 /* op[fsign_src] has the nominal result of the fsign, and op[1 -
827 * fsign_src] has the other multiply source. This must be rearranged so
828 * that op[0] is the source of the fsign op[1] is the other multiply
834 op
[0] = get_nir_src(fsign_instr
->src
[0].src
);
836 const nir_alu_type t
=
837 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[0] |
838 nir_src_bit_size(fsign_instr
->src
[0].src
));
840 op
[0].type
= brw_type_for_nir_type(devinfo
, t
);
841 op
[0].abs
= fsign_instr
->src
[0].abs
;
842 op
[0].negate
= fsign_instr
->src
[0].negate
;
844 unsigned channel
= 0;
845 if (nir_op_infos
[instr
->op
].output_size
== 0) {
846 /* Since NIR is doing the scalarizing for us, we should only ever see
847 * vectorized operations with a single channel.
849 assert(util_bitcount(instr
->dest
.write_mask
) == 1);
850 channel
= ffs(instr
->dest
.write_mask
) - 1;
853 op
[0] = offset(op
[0], bld
, fsign_instr
->src
[0].swizzle
[channel
]);
855 assert(!instr
->dest
.saturate
);
859 /* Straightforward since the source can be assumed to be either strictly
860 * >= 0 or strictly <= 0 depending on the setting of the negate flag.
862 set_condmod(BRW_CONDITIONAL_NZ
, bld
.MOV(result
, op
[0]));
864 if (instr
->op
== nir_op_fsign
) {
865 inst
= (op
[0].negate
)
866 ? bld
.MOV(result
, brw_imm_f(-1.0f
))
867 : bld
.MOV(result
, brw_imm_f(1.0f
));
869 op
[1].negate
= (op
[0].negate
!= op
[1].negate
);
870 inst
= bld
.MOV(result
, op
[1]);
873 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
874 } else if (type_sz(op
[0].type
) == 2) {
875 /* AND(val, 0x8000) gives the sign bit.
877 * Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
879 fs_reg zero
= retype(brw_imm_uw(0), BRW_REGISTER_TYPE_HF
);
880 bld
.CMP(bld
.null_reg_f(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
882 op
[0].type
= BRW_REGISTER_TYPE_UW
;
883 result
.type
= BRW_REGISTER_TYPE_UW
;
884 bld
.AND(result
, op
[0], brw_imm_uw(0x8000u
));
886 if (instr
->op
== nir_op_fsign
)
887 inst
= bld
.OR(result
, result
, brw_imm_uw(0x3c00u
));
889 /* Use XOR here to get the result sign correct. */
890 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UW
));
893 inst
->predicate
= BRW_PREDICATE_NORMAL
;
894 } else if (type_sz(op
[0].type
) == 4) {
895 /* AND(val, 0x80000000) gives the sign bit.
897 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
900 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
902 op
[0].type
= BRW_REGISTER_TYPE_UD
;
903 result
.type
= BRW_REGISTER_TYPE_UD
;
904 bld
.AND(result
, op
[0], brw_imm_ud(0x80000000u
));
906 if (instr
->op
== nir_op_fsign
)
907 inst
= bld
.OR(result
, result
, brw_imm_ud(0x3f800000u
));
909 /* Use XOR here to get the result sign correct. */
910 inst
= bld
.XOR(result
, result
, retype(op
[1], BRW_REGISTER_TYPE_UD
));
913 inst
->predicate
= BRW_PREDICATE_NORMAL
;
915 /* For doubles we do the same but we need to consider:
917 * - 2-src instructions can't operate with 64-bit immediates
918 * - The sign is encoded in the high 32-bit of each DF
919 * - We need to produce a DF result.
922 fs_reg zero
= vgrf(glsl_type::double_type
);
923 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
924 bld
.CMP(bld
.null_reg_df(), op
[0], zero
, BRW_CONDITIONAL_NZ
);
926 bld
.MOV(result
, zero
);
928 fs_reg r
= subscript(result
, BRW_REGISTER_TYPE_UD
, 1);
929 bld
.AND(r
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1),
930 brw_imm_ud(0x80000000u
));
932 if (instr
->op
== nir_op_fsign
) {
933 set_predicate(BRW_PREDICATE_NORMAL
,
934 bld
.OR(r
, r
, brw_imm_ud(0x3ff00000u
)));
936 /* This could be done better in some cases. If the scale is an
937 * immediate with the low 32-bits all 0, emitting a separate XOR and
938 * OR would allow an algebraic optimization to remove the OR. There
939 * are currently zero instances of fsign(double(x))*IMM in shader-db
940 * or any test suite, so it is hard to care at this time.
942 fs_reg result_int64
= retype(result
, BRW_REGISTER_TYPE_UQ
);
943 inst
= bld
.XOR(result_int64
, result_int64
,
944 retype(op
[1], BRW_REGISTER_TYPE_UQ
));
950 * Deteremine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
952 * Checks the operands of a \c nir_op_fmul to determine whether or not
953 * \c emit_fsign could fuse the multiplication with the \c sign() calculation.
955 * \param instr The multiplication instruction
957 * \param fsign_src The source of \c instr that may or may not be a
961 can_fuse_fmul_fsign(nir_alu_instr
*instr
, unsigned fsign_src
)
963 assert(instr
->op
== nir_op_fmul
);
965 nir_alu_instr
*const fsign_instr
=
966 nir_src_as_alu_instr(instr
->src
[fsign_src
].src
);
970 * 1. instr->src[fsign_src] must be a nir_op_fsign.
971 * 2. The nir_op_fsign can only be used by this multiplication.
972 * 3. The source that is the nir_op_fsign does not have source modifiers.
973 * \c emit_fsign only examines the source modifiers of the source of the
976 * The nir_op_fsign must also not have the saturate modifier, but steps
977 * have already been taken (in nir_opt_algebraic) to ensure that.
979 return fsign_instr
!= NULL
&& fsign_instr
->op
== nir_op_fsign
&&
980 is_used_once(fsign_instr
) &&
981 !instr
->src
[fsign_src
].abs
&& !instr
->src
[fsign_src
].negate
;
985 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
,
988 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
992 fs_reg result
= prepare_alu_destination_and_sources(bld
, instr
, op
, need_dest
);
999 fs_reg temp
= result
;
1000 bool need_extra_copy
= false;
1001 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1002 if (!instr
->src
[i
].src
.is_ssa
&&
1003 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
1004 need_extra_copy
= true;
1005 temp
= bld
.vgrf(result
.type
, 4);
1010 for (unsigned i
= 0; i
< 4; i
++) {
1011 if (!(instr
->dest
.write_mask
& (1 << i
)))
1014 if (instr
->op
== nir_op_mov
) {
1015 inst
= bld
.MOV(offset(temp
, bld
, i
),
1016 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
1018 inst
= bld
.MOV(offset(temp
, bld
, i
),
1019 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
1021 inst
->saturate
= instr
->dest
.saturate
;
1024 /* In this case the source and destination registers were the same,
1025 * so we need to insert an extra set of moves in order to deal with
1028 if (need_extra_copy
) {
1029 for (unsigned i
= 0; i
< 4; i
++) {
1030 if (!(instr
->dest
.write_mask
& (1 << i
)))
1033 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
1041 if (optimize_extract_to_float(instr
, result
))
1043 inst
= bld
.MOV(result
, op
[0]);
1044 inst
->saturate
= instr
->dest
.saturate
;
1047 case nir_op_f2f16_rtne
:
1048 case nir_op_f2f16_rtz
:
1049 bld
.emit(SHADER_OPCODE_RND_MODE
, bld
.null_reg_ud(),
1050 brw_imm_d(brw_rnd_mode_from_nir_op(instr
->op
)));
1053 /* In theory, it would be better to use BRW_OPCODE_F32TO16. Depending
1054 * on the HW gen, it is a special hw opcode or just a MOV, and
1055 * brw_F32TO16 (at brw_eu_emit) would do the work to chose.
1057 * But if we want to use that opcode, we need to provide support on
1058 * different optimizations and lowerings. As right now HF support is
1059 * only for gen8+, it will be better to use directly the MOV, and use
1060 * BRW_OPCODE_F32TO16 when/if we work for HF support on gen7.
1062 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1063 inst
= bld
.MOV(result
, op
[0]);
1064 inst
->saturate
= instr
->dest
.saturate
;
1074 if (try_emit_b2fi_of_inot(bld
, result
, instr
))
1076 op
[0].type
= BRW_REGISTER_TYPE_D
;
1077 op
[0].negate
= !op
[0].negate
;
1101 if (result
.type
== BRW_REGISTER_TYPE_B
||
1102 result
.type
== BRW_REGISTER_TYPE_UB
||
1103 result
.type
== BRW_REGISTER_TYPE_HF
)
1104 assert(type_sz(op
[0].type
) < 8); /* brw_nir_lower_conversions */
1106 if (op
[0].type
== BRW_REGISTER_TYPE_B
||
1107 op
[0].type
== BRW_REGISTER_TYPE_UB
||
1108 op
[0].type
== BRW_REGISTER_TYPE_HF
)
1109 assert(type_sz(result
.type
) < 8); /* brw_nir_lower_conversions */
1111 inst
= bld
.MOV(result
, op
[0]);
1112 inst
->saturate
= instr
->dest
.saturate
;
1116 inst
= bld
.MOV(result
, op
[0]);
1117 inst
->saturate
= true;
1122 op
[0].negate
= true;
1123 inst
= bld
.MOV(result
, op
[0]);
1124 if (instr
->op
== nir_op_fneg
)
1125 inst
->saturate
= instr
->dest
.saturate
;
1130 op
[0].negate
= false;
1132 inst
= bld
.MOV(result
, op
[0]);
1133 if (instr
->op
== nir_op_fabs
)
1134 inst
->saturate
= instr
->dest
.saturate
;
1138 emit_fsign(bld
, instr
, result
, op
, 0);
1142 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
1143 inst
->saturate
= instr
->dest
.saturate
;
1147 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
1148 inst
->saturate
= instr
->dest
.saturate
;
1152 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
1153 inst
->saturate
= instr
->dest
.saturate
;
1157 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
1158 inst
->saturate
= instr
->dest
.saturate
;
1162 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
1163 inst
->saturate
= instr
->dest
.saturate
;
1167 if (fs_key
->high_quality_derivatives
) {
1168 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1170 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1172 inst
->saturate
= instr
->dest
.saturate
;
1174 case nir_op_fddx_fine
:
1175 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
1176 inst
->saturate
= instr
->dest
.saturate
;
1178 case nir_op_fddx_coarse
:
1179 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
1180 inst
->saturate
= instr
->dest
.saturate
;
1183 if (fs_key
->high_quality_derivatives
) {
1184 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1186 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1188 inst
->saturate
= instr
->dest
.saturate
;
1190 case nir_op_fddy_fine
:
1191 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
1192 inst
->saturate
= instr
->dest
.saturate
;
1194 case nir_op_fddy_coarse
:
1195 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
1196 inst
->saturate
= instr
->dest
.saturate
;
1201 inst
= bld
.ADD(result
, op
[0], op
[1]);
1202 inst
->saturate
= instr
->dest
.saturate
;
1205 case nir_op_uadd_sat
:
1206 inst
= bld
.ADD(result
, op
[0], op
[1]);
1207 inst
->saturate
= true;
1211 for (unsigned i
= 0; i
< 2; i
++) {
1212 if (can_fuse_fmul_fsign(instr
, i
)) {
1213 emit_fsign(bld
, instr
, result
, op
, i
);
1218 inst
= bld
.MUL(result
, op
[0], op
[1]);
1219 inst
->saturate
= instr
->dest
.saturate
;
1222 case nir_op_imul_2x32_64
:
1223 case nir_op_umul_2x32_64
:
1224 bld
.MUL(result
, op
[0], op
[1]);
1228 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1229 bld
.MUL(result
, op
[0], op
[1]);
1232 case nir_op_imul_high
:
1233 case nir_op_umul_high
:
1234 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1235 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
1240 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1241 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
1244 case nir_op_uadd_carry
:
1245 unreachable("Should have been lowered by carry_to_arith().");
1247 case nir_op_usub_borrow
:
1248 unreachable("Should have been lowered by borrow_to_arith().");
1252 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
1253 * appears that our hardware just does the right thing for signed
1256 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1257 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1261 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
1262 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1264 /* Math instructions don't support conditional mod */
1265 inst
= bld
.MOV(bld
.null_reg_d(), result
);
1266 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1268 /* Now, we need to determine if signs of the sources are different.
1269 * When we XOR the sources, the top bit is 0 if they are the same and 1
1270 * if they are different. We can then use a conditional modifier to
1271 * turn that into a predicate. This leads us to an XOR.l instruction.
1273 * Technically, according to the PRM, you're not allowed to use .l on a
1274 * XOR instruction. However, emperical experiments and Curro's reading
1275 * of the simulator source both indicate that it's safe.
1277 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1278 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
1279 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1280 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1282 /* If the result of the initial remainder operation is non-zero and the
1283 * two sources have different signs, add in a copy of op[1] to get the
1284 * final integer modulus value.
1286 inst
= bld
.ADD(result
, result
, op
[1]);
1287 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1294 case nir_op_fne32
: {
1295 fs_reg dest
= result
;
1297 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1299 dest
= bld
.vgrf(op
[0].type
, 1);
1301 bld
.CMP(dest
, op
[0], op
[1], brw_cmod_for_nir_comparison(instr
->op
));
1303 if (bit_size
> 32) {
1304 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1305 } else if(bit_size
< 32) {
1306 /* When we convert the result to 32-bit we need to be careful and do
1307 * it as a signed conversion to get sign extension (for 32-bit true)
1309 const brw_reg_type src_type
=
1310 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1312 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1322 case nir_op_ine32
: {
1323 fs_reg dest
= result
;
1325 /* On Gen11 we have an additional issue being that src1 cannot be a byte
1326 * type. So we convert both operands for the comparison.
1329 temp_op
[0] = bld
.fix_byte_src(op
[0]);
1330 temp_op
[1] = bld
.fix_byte_src(op
[1]);
1332 const uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1334 dest
= bld
.vgrf(temp_op
[0].type
, 1);
1336 bld
.CMP(dest
, temp_op
[0], temp_op
[1],
1337 brw_cmod_for_nir_comparison(instr
->op
));
1339 if (bit_size
> 32) {
1340 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1341 } else if (bit_size
< 32) {
1342 /* When we convert the result to 32-bit we need to be careful and do
1343 * it as a signed conversion to get sign extension (for 32-bit true)
1345 const brw_reg_type src_type
=
1346 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_D
);
1348 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), retype(dest
, src_type
));
1354 if (devinfo
->gen
>= 8) {
1355 nir_alu_instr
*inot_src_instr
= nir_src_as_alu_instr(instr
->src
[0].src
);
1357 if (inot_src_instr
!= NULL
&&
1358 (inot_src_instr
->op
== nir_op_ior
||
1359 inot_src_instr
->op
== nir_op_ixor
||
1360 inot_src_instr
->op
== nir_op_iand
) &&
1361 !inot_src_instr
->src
[0].abs
&&
1362 !inot_src_instr
->src
[0].negate
&&
1363 !inot_src_instr
->src
[1].abs
&&
1364 !inot_src_instr
->src
[1].negate
) {
1365 /* The sources of the source logical instruction are now the
1366 * sources of the instruction that will be generated.
1368 prepare_alu_destination_and_sources(bld
, inot_src_instr
, op
, false);
1369 resolve_inot_sources(bld
, inot_src_instr
, op
);
1371 /* Smash all of the sources and destination to be signed. This
1372 * doesn't matter for the operation of the instruction, but cmod
1373 * propagation fails on unsigned sources with negation (due to
1374 * fs_inst::can_do_cmod returning false).
1377 brw_type_for_nir_type(devinfo
,
1378 (nir_alu_type
)(nir_type_int
|
1379 nir_dest_bit_size(instr
->dest
.dest
)));
1381 brw_type_for_nir_type(devinfo
,
1382 (nir_alu_type
)(nir_type_int
|
1383 nir_src_bit_size(inot_src_instr
->src
[0].src
)));
1385 brw_type_for_nir_type(devinfo
,
1386 (nir_alu_type
)(nir_type_int
|
1387 nir_src_bit_size(inot_src_instr
->src
[1].src
)));
1389 /* For XOR, only invert one of the sources. Arbitrarily choose
1392 op
[0].negate
= !op
[0].negate
;
1393 if (inot_src_instr
->op
!= nir_op_ixor
)
1394 op
[1].negate
= !op
[1].negate
;
1396 switch (inot_src_instr
->op
) {
1398 bld
.AND(result
, op
[0], op
[1]);
1402 bld
.OR(result
, op
[0], op
[1]);
1406 bld
.XOR(result
, op
[0], op
[1]);
1410 unreachable("impossible opcode");
1413 op
[0] = resolve_source_modifiers(op
[0]);
1415 bld
.NOT(result
, op
[0]);
1418 if (devinfo
->gen
>= 8) {
1419 resolve_inot_sources(bld
, instr
, op
);
1421 bld
.XOR(result
, op
[0], op
[1]);
1424 if (devinfo
->gen
>= 8) {
1425 resolve_inot_sources(bld
, instr
, op
);
1427 bld
.OR(result
, op
[0], op
[1]);
1430 if (devinfo
->gen
>= 8) {
1431 resolve_inot_sources(bld
, instr
, op
);
1433 bld
.AND(result
, op
[0], op
[1]);
1439 case nir_op_b32all_fequal2
:
1440 case nir_op_b32all_iequal2
:
1441 case nir_op_b32all_fequal3
:
1442 case nir_op_b32all_iequal3
:
1443 case nir_op_b32all_fequal4
:
1444 case nir_op_b32all_iequal4
:
1445 case nir_op_b32any_fnequal2
:
1446 case nir_op_b32any_inequal2
:
1447 case nir_op_b32any_fnequal3
:
1448 case nir_op_b32any_inequal3
:
1449 case nir_op_b32any_fnequal4
:
1450 case nir_op_b32any_inequal4
:
1451 unreachable("Lowered by nir_lower_alu_reductions");
1453 case nir_op_fnoise1_1
:
1454 case nir_op_fnoise1_2
:
1455 case nir_op_fnoise1_3
:
1456 case nir_op_fnoise1_4
:
1457 case nir_op_fnoise2_1
:
1458 case nir_op_fnoise2_2
:
1459 case nir_op_fnoise2_3
:
1460 case nir_op_fnoise2_4
:
1461 case nir_op_fnoise3_1
:
1462 case nir_op_fnoise3_2
:
1463 case nir_op_fnoise3_3
:
1464 case nir_op_fnoise3_4
:
1465 case nir_op_fnoise4_1
:
1466 case nir_op_fnoise4_2
:
1467 case nir_op_fnoise4_3
:
1468 case nir_op_fnoise4_4
:
1469 unreachable("not reached: should be handled by lower_noise");
1472 unreachable("not reached: should be handled by ldexp_to_arith()");
1475 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1476 inst
->saturate
= instr
->dest
.saturate
;
1480 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1481 inst
->saturate
= instr
->dest
.saturate
;
1485 case nir_op_f2b32
: {
1486 uint32_t bit_size
= nir_src_bit_size(instr
->src
[0].src
);
1487 if (bit_size
== 64) {
1488 /* two-argument instructions can't take 64-bit immediates */
1492 if (instr
->op
== nir_op_f2b32
) {
1493 zero
= vgrf(glsl_type::double_type
);
1494 tmp
= vgrf(glsl_type::double_type
);
1495 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1497 zero
= vgrf(glsl_type::int64_t_type
);
1498 tmp
= vgrf(glsl_type::int64_t_type
);
1499 bld
.MOV(zero
, brw_imm_q(0));
1502 /* A SIMD16 execution needs to be split in two instructions, so use
1503 * a vgrf instead of the flag register as dst so instruction splitting
1506 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1507 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1510 if (bit_size
== 32) {
1511 zero
= instr
->op
== nir_op_f2b32
? brw_imm_f(0.0f
) : brw_imm_d(0);
1513 assert(bit_size
== 16);
1514 zero
= instr
->op
== nir_op_f2b32
?
1515 retype(brw_imm_w(0), BRW_REGISTER_TYPE_HF
) : brw_imm_w(0);
1517 bld
.CMP(result
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1523 inst
= bld
.RNDZ(result
, op
[0]);
1524 inst
->saturate
= instr
->dest
.saturate
;
1527 case nir_op_fceil
: {
1528 op
[0].negate
= !op
[0].negate
;
1529 fs_reg temp
= vgrf(glsl_type::float_type
);
1530 bld
.RNDD(temp
, op
[0]);
1532 inst
= bld
.MOV(result
, temp
);
1533 inst
->saturate
= instr
->dest
.saturate
;
1537 inst
= bld
.RNDD(result
, op
[0]);
1538 inst
->saturate
= instr
->dest
.saturate
;
1541 inst
= bld
.FRC(result
, op
[0]);
1542 inst
->saturate
= instr
->dest
.saturate
;
1544 case nir_op_fround_even
:
1545 inst
= bld
.RNDE(result
, op
[0]);
1546 inst
->saturate
= instr
->dest
.saturate
;
1549 case nir_op_fquantize2f16
: {
1550 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1551 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1552 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1554 /* The destination stride must be at least as big as the source stride. */
1555 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1558 /* Check for denormal */
1559 fs_reg abs_src0
= op
[0];
1560 abs_src0
.abs
= true;
1561 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1563 /* Get the appropriately signed zero */
1564 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1565 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1566 brw_imm_ud(0x80000000));
1567 /* Do the actual F32 -> F16 -> F32 conversion */
1568 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1569 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1570 /* Select that or zero based on normal status */
1571 inst
= bld
.SEL(result
, zero
, tmp32
);
1572 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1573 inst
->saturate
= instr
->dest
.saturate
;
1580 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1581 inst
->saturate
= instr
->dest
.saturate
;
1587 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1588 inst
->saturate
= instr
->dest
.saturate
;
1591 case nir_op_pack_snorm_2x16
:
1592 case nir_op_pack_snorm_4x8
:
1593 case nir_op_pack_unorm_2x16
:
1594 case nir_op_pack_unorm_4x8
:
1595 case nir_op_unpack_snorm_2x16
:
1596 case nir_op_unpack_snorm_4x8
:
1597 case nir_op_unpack_unorm_2x16
:
1598 case nir_op_unpack_unorm_4x8
:
1599 case nir_op_unpack_half_2x16
:
1600 case nir_op_pack_half_2x16
:
1601 unreachable("not reached: should be handled by lower_packing_builtins");
1603 case nir_op_unpack_half_2x16_split_x
:
1604 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1605 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1606 inst
->saturate
= instr
->dest
.saturate
;
1608 case nir_op_unpack_half_2x16_split_y
:
1609 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
,
1610 subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1611 inst
->saturate
= instr
->dest
.saturate
;
1614 case nir_op_pack_64_2x32_split
:
1615 case nir_op_pack_32_2x16_split
:
1616 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1619 case nir_op_unpack_64_2x32_split_x
:
1620 case nir_op_unpack_64_2x32_split_y
: {
1621 if (instr
->op
== nir_op_unpack_64_2x32_split_x
)
1622 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1624 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1628 case nir_op_unpack_32_2x16_split_x
:
1629 case nir_op_unpack_32_2x16_split_y
: {
1630 if (instr
->op
== nir_op_unpack_32_2x16_split_x
)
1631 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 0));
1633 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UW
, 1));
1638 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1639 inst
->saturate
= instr
->dest
.saturate
;
1642 case nir_op_bitfield_reverse
:
1643 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1644 bld
.BFREV(result
, op
[0]);
1647 case nir_op_bit_count
:
1648 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1649 bld
.CBIT(result
, op
[0]);
1652 case nir_op_ufind_msb
: {
1653 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1654 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1658 case nir_op_ifind_msb
: {
1659 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1661 if (devinfo
->gen
< 7) {
1662 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1664 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1666 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1667 * count from the LSB side. If FBH didn't return an error
1668 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1669 * count into an LSB count.
1671 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1673 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1674 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1675 inst
->src
[0].negate
= true;
1680 case nir_op_find_lsb
:
1681 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1683 if (devinfo
->gen
< 7) {
1684 fs_reg temp
= vgrf(glsl_type::int_type
);
1686 /* (x & -x) generates a value that consists of only the LSB of x.
1687 * For all powers of 2, findMSB(y) == findLSB(y).
1689 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1690 fs_reg negated_src
= src
;
1692 /* One must be negated, and the other must be non-negated. It
1693 * doesn't matter which is which.
1695 negated_src
.negate
= true;
1698 bld
.AND(temp
, src
, negated_src
);
1699 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1701 bld
.FBL(result
, op
[0]);
1705 case nir_op_ubitfield_extract
:
1706 case nir_op_ibitfield_extract
:
1707 unreachable("should have been lowered");
1710 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1711 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1714 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1715 bld
.BFI1(result
, op
[0], op
[1]);
1718 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1719 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1722 case nir_op_bitfield_insert
:
1723 unreachable("not reached: should have been lowered");
1726 bld
.SHL(result
, op
[0], op
[1]);
1729 bld
.ASR(result
, op
[0], op
[1]);
1732 bld
.SHR(result
, op
[0], op
[1]);
1736 bld
.ROL(result
, op
[0], op
[1]);
1739 bld
.ROR(result
, op
[0], op
[1]);
1742 case nir_op_pack_half_2x16_split
:
1743 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1747 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1748 inst
->saturate
= instr
->dest
.saturate
;
1752 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1753 inst
->saturate
= instr
->dest
.saturate
;
1756 case nir_op_b32csel
:
1757 if (optimize_frontfacing_ternary(instr
, result
))
1760 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1761 inst
= bld
.SEL(result
, op
[1], op
[2]);
1762 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1765 case nir_op_extract_u8
:
1766 case nir_op_extract_i8
: {
1767 unsigned byte
= nir_src_as_uint(instr
->src
[1].src
);
1772 * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB.
1773 * Use two instructions and a word or DWord intermediate integer type.
1775 if (nir_dest_bit_size(instr
->dest
.dest
) == 64) {
1776 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1778 if (instr
->op
== nir_op_extract_i8
) {
1779 /* If we need to sign extend, extract to a word first */
1780 fs_reg w_temp
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
1781 bld
.MOV(w_temp
, subscript(op
[0], type
, byte
));
1782 bld
.MOV(result
, w_temp
);
1783 } else if (byte
& 1) {
1784 /* Extract the high byte from the word containing the desired byte
1788 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1791 /* Otherwise use an AND with 0xff and a word type */
1793 subscript(op
[0], BRW_REGISTER_TYPE_UW
, byte
/ 2),
1797 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1798 bld
.MOV(result
, subscript(op
[0], type
, byte
));
1803 case nir_op_extract_u16
:
1804 case nir_op_extract_i16
: {
1805 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1806 unsigned word
= nir_src_as_uint(instr
->src
[1].src
);
1807 bld
.MOV(result
, subscript(op
[0], type
, word
));
1812 unreachable("unhandled instruction");
1815 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1816 * to sign extend the low bit to 0/~0
1818 if (devinfo
->gen
<= 5 &&
1819 !result
.is_null() &&
1820 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1821 fs_reg masked
= vgrf(glsl_type::int_type
);
1822 bld
.AND(masked
, result
, brw_imm_d(1));
1823 masked
.negate
= true;
1824 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1829 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1830 nir_load_const_instr
*instr
)
1832 const brw_reg_type reg_type
=
1833 brw_reg_type_from_bit_size(instr
->def
.bit_size
, BRW_REGISTER_TYPE_D
);
1834 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1836 switch (instr
->def
.bit_size
) {
1838 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1839 bld
.MOV(offset(reg
, bld
, i
), setup_imm_b(bld
, instr
->value
[i
].i8
));
1843 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1844 bld
.MOV(offset(reg
, bld
, i
), brw_imm_w(instr
->value
[i
].i16
));
1848 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1849 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
[i
].i32
));
1853 assert(devinfo
->gen
>= 7);
1854 if (devinfo
->gen
== 7) {
1855 /* We don't get 64-bit integer types until gen8 */
1856 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++) {
1857 bld
.MOV(retype(offset(reg
, bld
, i
), BRW_REGISTER_TYPE_DF
),
1858 setup_imm_df(bld
, instr
->value
[i
].f64
));
1861 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1862 bld
.MOV(offset(reg
, bld
, i
), brw_imm_q(instr
->value
[i
].i64
));
1867 unreachable("Invalid bit size");
1870 nir_ssa_values
[instr
->def
.index
] = reg
;
1874 fs_visitor::get_nir_src(const nir_src
&src
)
1878 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1879 const brw_reg_type reg_type
=
1880 brw_reg_type_from_bit_size(src
.ssa
->bit_size
, BRW_REGISTER_TYPE_D
);
1881 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1883 reg
= nir_ssa_values
[src
.ssa
->index
];
1886 /* We don't handle indirects on locals */
1887 assert(src
.reg
.indirect
== NULL
);
1888 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1889 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1892 if (nir_src_bit_size(src
) == 64 && devinfo
->gen
== 7) {
1893 /* The only 64-bit type available on gen7 is DF, so use that. */
1894 reg
.type
= BRW_REGISTER_TYPE_DF
;
1896 /* To avoid floating-point denorm flushing problems, set the type by
1897 * default to an integer type - instructions that need floating point
1898 * semantics will set this to F if they need to
1900 reg
.type
= brw_reg_type_from_bit_size(nir_src_bit_size(src
),
1901 BRW_REGISTER_TYPE_D
);
1908 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1910 * This function should not be called on any value which may be 64 bits.
1911 * We could theoretically support 64-bit on gen8+ but we choose not to
1912 * because it wouldn't work in general (no gen7 support) and there are
1913 * enough restrictions in 64-bit immediates that you can't take the return
1914 * value and treat it the same as the result of get_nir_src().
1917 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1919 assert(nir_src_bit_size(src
) == 32);
1920 return nir_src_is_const(src
) ?
1921 fs_reg(brw_imm_d(nir_src_as_int(src
))) : get_nir_src(src
);
1925 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1928 const brw_reg_type reg_type
=
1929 brw_reg_type_from_bit_size(dest
.ssa
.bit_size
,
1930 dest
.ssa
.bit_size
== 8 ?
1931 BRW_REGISTER_TYPE_D
:
1932 BRW_REGISTER_TYPE_F
);
1933 nir_ssa_values
[dest
.ssa
.index
] =
1934 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1935 bld
.UNDEF(nir_ssa_values
[dest
.ssa
.index
]);
1936 return nir_ssa_values
[dest
.ssa
.index
];
1938 /* We don't handle indirects on locals */
1939 assert(dest
.reg
.indirect
== NULL
);
1940 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1941 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1946 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1949 for (unsigned i
= 0; i
< 4; i
++) {
1950 if (!((wr_mask
>> i
) & 1))
1953 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1954 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1955 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1956 if (new_inst
->src
[j
].file
== VGRF
)
1957 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1964 emit_pixel_interpolater_send(const fs_builder
&bld
,
1969 glsl_interp_mode interpolation
)
1971 struct brw_wm_prog_data
*wm_prog_data
=
1972 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1974 fs_inst
*inst
= bld
.emit(opcode
, dst
, src
, desc
);
1975 /* 2 floats per slot returned */
1976 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1977 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1979 wm_prog_data
->pulls_bary
= true;
1985 * Computes 1 << x, given a D/UD register containing some value x.
1988 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1990 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1992 fs_reg result
= bld
.vgrf(x
.type
, 1);
1993 fs_reg one
= bld
.vgrf(x
.type
, 1);
1995 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1996 bld
.SHL(result
, one
, x
);
2001 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
2003 assert(stage
== MESA_SHADER_GEOMETRY
);
2005 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2007 if (gs_compile
->control_data_header_size_bits
== 0)
2010 /* We can only do EndPrimitive() functionality when the control data
2011 * consists of cut bits. Fortunately, the only time it isn't is when the
2012 * output type is points, in which case EndPrimitive() is a no-op.
2014 if (gs_prog_data
->control_data_format
!=
2015 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
2019 /* Cut bits use one bit per vertex. */
2020 assert(gs_compile
->control_data_bits_per_vertex
== 1);
2022 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2023 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2025 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
2026 * vertex n, 0 otherwise. So all we need to do here is mark bit
2027 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
2028 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
2029 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
2031 * Note that if EndPrimitive() is called before emitting any vertices, this
2032 * will cause us to set bit 31 of the control_data_bits register to 1.
2033 * That's fine because:
2035 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
2036 * output, so the hardware will ignore cut bit 31.
2038 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
2039 * last vertex, so setting cut bit 31 has no effect (since the primitive
2040 * is automatically ended when the GS terminates).
2042 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
2043 * control_data_bits register to 0 when the first vertex is emitted.
2046 const fs_builder abld
= bld
.annotate("end primitive");
2048 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
2049 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2050 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2051 fs_reg mask
= intexp2(abld
, prev_count
);
2052 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2053 * attention to the lower 5 bits of its second source argument, so on this
2054 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
2055 * ((vertex_count - 1) % 32).
2057 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2061 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
2063 assert(stage
== MESA_SHADER_GEOMETRY
);
2064 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
2066 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2068 const fs_builder abld
= bld
.annotate("emit control data bits");
2069 const fs_builder fwa_bld
= bld
.exec_all();
2071 /* We use a single UD register to accumulate control data bits (32 bits
2072 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
2075 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
2076 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
2077 * use the Channel Mask phase to enable/disable which DWord within that
2078 * group to write. (Remember, different SIMD8 channels may have emitted
2079 * different numbers of vertices, so we may need per-slot offsets.)
2081 * Channel masking presents an annoying problem: we may have to replicate
2082 * the data up to 4 times:
2084 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
2086 * To avoid penalizing shaders that emit a small number of vertices, we
2087 * can avoid these sometimes: if the size of the control data header is
2088 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
2089 * land in the same 128-bit group, so we can skip per-slot offsets.
2091 * Similarly, if the control data header is <= 32 bits, there is only one
2092 * DWord, so we can skip channel masks.
2094 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
2096 fs_reg channel_mask
, per_slot_offset
;
2098 if (gs_compile
->control_data_header_size_bits
> 32) {
2099 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2100 channel_mask
= vgrf(glsl_type::uint_type
);
2103 if (gs_compile
->control_data_header_size_bits
> 128) {
2104 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
2105 per_slot_offset
= vgrf(glsl_type::uint_type
);
2108 /* Figure out which DWord we're trying to write to using the formula:
2110 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
2112 * Since bits_per_vertex is a power of two, and is known at compile
2113 * time, this can be optimized to:
2115 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
2117 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
2118 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2119 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2120 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
2121 unsigned log2_bits_per_vertex
=
2122 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
2123 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
2125 if (per_slot_offset
.file
!= BAD_FILE
) {
2126 /* Set the per-slot offset to dword_index / 4, so that we'll write to
2127 * the appropriate OWord within the control data header.
2129 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
2132 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
2133 * write to the appropriate DWORD within the OWORD.
2135 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2136 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
2137 channel_mask
= intexp2(fwa_bld
, channel
);
2138 /* Then the channel masks need to be in bits 23:16. */
2139 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
2142 /* Store the control data bits in the message payload and send it. */
2144 if (channel_mask
.file
!= BAD_FILE
)
2145 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
2146 if (per_slot_offset
.file
!= BAD_FILE
)
2149 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2150 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
2152 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
2153 if (per_slot_offset
.file
!= BAD_FILE
)
2154 sources
[i
++] = per_slot_offset
;
2155 if (channel_mask
.file
!= BAD_FILE
)
2156 sources
[i
++] = channel_mask
;
2158 sources
[i
++] = this->control_data_bits
;
2161 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
2162 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
2164 /* We need to increment Global Offset by 256-bits to make room for
2165 * Broadwell's extra "Vertex Count" payload at the beginning of the
2166 * URB entry. Since this is an OWord message, Global Offset is counted
2167 * in 128-bit units, so we must set it to 2.
2169 if (gs_prog_data
->static_vertex_count
== -1)
2174 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
2177 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
2179 /* Note: we are calling this *before* increasing vertex_count, so
2180 * this->vertex_count == vertex_count - 1 in the formula above.
2183 /* Stream mode uses 2 bits per vertex */
2184 assert(gs_compile
->control_data_bits_per_vertex
== 2);
2186 /* Must be a valid stream */
2187 assert(stream_id
< MAX_VERTEX_STREAMS
);
2189 /* Control data bits are initialized to 0 so we don't have to set any
2190 * bits when sending vertices to stream 0.
2195 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
2197 /* reg::sid = stream_id */
2198 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2199 abld
.MOV(sid
, brw_imm_ud(stream_id
));
2201 /* reg:shift_count = 2 * (vertex_count - 1) */
2202 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2203 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
2205 /* Note: we're relying on the fact that the GEN SHL instruction only pays
2206 * attention to the lower 5 bits of its second source argument, so on this
2207 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
2208 * stream_id << ((2 * (vertex_count - 1)) % 32).
2210 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2211 abld
.SHL(mask
, sid
, shift_count
);
2212 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
2216 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
2219 assert(stage
== MESA_SHADER_GEOMETRY
);
2221 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2223 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
2224 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
2226 /* Haswell and later hardware ignores the "Render Stream Select" bits
2227 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
2228 * and instead sends all primitives down the pipeline for rasterization.
2229 * If the SOL stage is enabled, "Render Stream Select" is honored and
2230 * primitives bound to non-zero streams are discarded after stream output.
2232 * Since the only purpose of primives sent to non-zero streams is to
2233 * be recorded by transform feedback, we can simply discard all geometry
2234 * bound to these streams when transform feedback is disabled.
2236 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
2239 /* If we're outputting 32 control data bits or less, then we can wait
2240 * until the shader is over to output them all. Otherwise we need to
2241 * output them as we go. Now is the time to do it, since we're about to
2242 * output the vertex_count'th vertex, so it's guaranteed that the
2243 * control data bits associated with the (vertex_count - 1)th vertex are
2246 if (gs_compile
->control_data_header_size_bits
> 32) {
2247 const fs_builder abld
=
2248 bld
.annotate("emit vertex: emit control data bits");
2250 /* Only emit control data bits if we've finished accumulating a batch
2251 * of 32 bits. This is the case when:
2253 * (vertex_count * bits_per_vertex) % 32 == 0
2255 * (in other words, when the last 5 bits of vertex_count *
2256 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
2257 * integer n (which is always the case, since bits_per_vertex is
2258 * always 1 or 2), this is equivalent to requiring that the last 5-n
2259 * bits of vertex_count are 0:
2261 * vertex_count & (2^(5-n) - 1) == 0
2263 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
2266 * vertex_count & (32 / bits_per_vertex - 1) == 0
2268 * TODO: If vertex_count is an immediate, we could do some of this math
2269 * at compile time...
2272 abld
.AND(bld
.null_reg_d(), vertex_count
,
2273 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2274 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2276 abld
.IF(BRW_PREDICATE_NORMAL
);
2277 /* If vertex_count is 0, then no control data bits have been
2278 * accumulated yet, so we can skip emitting them.
2280 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2281 BRW_CONDITIONAL_NEQ
);
2282 abld
.IF(BRW_PREDICATE_NORMAL
);
2283 emit_gs_control_data_bits(vertex_count
);
2284 abld
.emit(BRW_OPCODE_ENDIF
);
2286 /* Reset control_data_bits to 0 so we can start accumulating a new
2289 * Note: in the case where vertex_count == 0, this neutralizes the
2290 * effect of any call to EndPrimitive() that the shader may have
2291 * made before outputting its first vertex.
2293 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2294 inst
->force_writemask_all
= true;
2295 abld
.emit(BRW_OPCODE_ENDIF
);
2298 emit_urb_writes(vertex_count
);
2300 /* In stream mode we have to set control data bits for all vertices
2301 * unless we have disabled control data bits completely (which we do
2302 * do for GL_POINTS outputs that don't use streams).
2304 if (gs_compile
->control_data_header_size_bits
> 0 &&
2305 gs_prog_data
->control_data_format
==
2306 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2307 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2312 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2313 const nir_src
&vertex_src
,
2314 unsigned base_offset
,
2315 const nir_src
&offset_src
,
2316 unsigned num_components
,
2317 unsigned first_component
)
2319 assert(type_sz(dst
.type
) == 4);
2320 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2321 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2323 /* TODO: figure out push input layout for invocations == 1 */
2324 if (gs_prog_data
->invocations
== 1 &&
2325 nir_src_is_const(offset_src
) && nir_src_is_const(vertex_src
) &&
2326 4 * (base_offset
+ nir_src_as_uint(offset_src
)) < push_reg_count
) {
2327 int imm_offset
= (base_offset
+ nir_src_as_uint(offset_src
)) * 4 +
2328 nir_src_as_uint(vertex_src
) * push_reg_count
;
2329 for (unsigned i
= 0; i
< num_components
; i
++) {
2330 bld
.MOV(offset(dst
, bld
, i
),
2331 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2336 /* Resort to the pull model. Ensure the VUE handles are provided. */
2337 assert(gs_prog_data
->base
.include_vue_handles
);
2339 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2340 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2342 if (gs_prog_data
->invocations
== 1) {
2343 if (nir_src_is_const(vertex_src
)) {
2344 /* The vertex index is constant; just select the proper URB handle. */
2346 retype(brw_vec8_grf(first_icp_handle
+ nir_src_as_uint(vertex_src
), 0),
2347 BRW_REGISTER_TYPE_UD
);
2349 /* The vertex index is non-constant. We need to use indirect
2350 * addressing to fetch the proper URB handle.
2352 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2353 * indicating that channel <n> should read the handle from
2354 * DWord <n>. We convert that to bytes by multiplying by 4.
2356 * Next, we convert the vertex index to bytes by multiplying
2357 * by 32 (shifting by 5), and add the two together. This is
2358 * the final indirect byte offset.
2360 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2361 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2362 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2363 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2365 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2366 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2367 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2368 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2369 /* Convert vertex_index to bytes (multiply by 32) */
2370 bld
.SHL(vertex_offset_bytes
,
2371 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2373 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2375 /* Use first_icp_handle as the base offset. There is one register
2376 * of URB handles per vertex, so inform the register allocator that
2377 * we might read up to nir->info.gs.vertices_in registers.
2379 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2380 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2381 fs_reg(icp_offset_bytes
),
2382 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2385 assert(gs_prog_data
->invocations
> 1);
2387 if (nir_src_is_const(vertex_src
)) {
2388 unsigned vertex
= nir_src_as_uint(vertex_src
);
2389 assert(devinfo
->gen
>= 9 || vertex
<= 5);
2391 retype(brw_vec1_grf(first_icp_handle
+ vertex
/ 8, vertex
% 8),
2392 BRW_REGISTER_TYPE_UD
));
2394 /* The vertex index is non-constant. We need to use indirect
2395 * addressing to fetch the proper URB handle.
2398 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2400 /* Convert vertex_index to bytes (multiply by 4) */
2401 bld
.SHL(icp_offset_bytes
,
2402 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2405 /* Use first_icp_handle as the base offset. There is one DWord
2406 * of URB handles per vertex, so inform the register allocator that
2407 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2409 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2410 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2411 fs_reg(icp_offset_bytes
),
2412 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2418 fs_reg indirect_offset
= get_nir_src(offset_src
);
2420 if (nir_src_is_const(offset_src
)) {
2421 /* Constant indexing - use global offset. */
2422 if (first_component
!= 0) {
2423 unsigned read_components
= num_components
+ first_component
;
2424 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2425 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2426 inst
->size_written
= read_components
*
2427 tmp
.component_size(inst
->exec_size
);
2428 for (unsigned i
= 0; i
< num_components
; i
++) {
2429 bld
.MOV(offset(dst
, bld
, i
),
2430 offset(tmp
, bld
, i
+ first_component
));
2433 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2434 inst
->size_written
= num_components
*
2435 dst
.component_size(inst
->exec_size
);
2437 inst
->offset
= base_offset
+ nir_src_as_uint(offset_src
);
2440 /* Indirect indexing - use per-slot offsets as well. */
2441 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2442 unsigned read_components
= num_components
+ first_component
;
2443 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2444 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2445 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2446 if (first_component
!= 0) {
2447 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2449 inst
->size_written
= read_components
*
2450 tmp
.component_size(inst
->exec_size
);
2451 for (unsigned i
= 0; i
< num_components
; i
++) {
2452 bld
.MOV(offset(dst
, bld
, i
),
2453 offset(tmp
, bld
, i
+ first_component
));
2456 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2457 inst
->size_written
= num_components
*
2458 dst
.component_size(inst
->exec_size
);
2460 inst
->offset
= base_offset
;
2466 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2468 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2470 if (nir_src_is_const(*offset_src
)) {
2471 /* The only constant offset we should find is 0. brw_nir.c's
2472 * add_const_offset_to_base() will fold other constant offsets
2473 * into instr->const_index[0].
2475 assert(nir_src_as_uint(*offset_src
) == 0);
2479 return get_nir_src(*offset_src
);
2483 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2484 nir_intrinsic_instr
*instr
)
2486 assert(stage
== MESA_SHADER_VERTEX
);
2489 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2490 dest
= get_nir_dest(instr
->dest
);
2492 switch (instr
->intrinsic
) {
2493 case nir_intrinsic_load_vertex_id
:
2494 case nir_intrinsic_load_base_vertex
:
2495 unreachable("should be lowered by nir_lower_system_values()");
2497 case nir_intrinsic_load_input
: {
2498 assert(nir_dest_bit_size(instr
->dest
) == 32);
2499 fs_reg src
= fs_reg(ATTR
, nir_intrinsic_base(instr
) * 4, dest
.type
);
2500 src
= offset(src
, bld
, nir_intrinsic_component(instr
));
2501 src
= offset(src
, bld
, nir_src_as_uint(instr
->src
[0]));
2503 for (unsigned i
= 0; i
< instr
->num_components
; i
++)
2504 bld
.MOV(offset(dest
, bld
, i
), offset(src
, bld
, i
));
2508 case nir_intrinsic_load_vertex_id_zero_base
:
2509 case nir_intrinsic_load_instance_id
:
2510 case nir_intrinsic_load_base_instance
:
2511 case nir_intrinsic_load_draw_id
:
2512 case nir_intrinsic_load_first_vertex
:
2513 case nir_intrinsic_load_is_indexed_draw
:
2514 unreachable("lowered by brw_nir_lower_vs_inputs");
2517 nir_emit_intrinsic(bld
, instr
);
2523 fs_visitor::get_tcs_single_patch_icp_handle(const fs_builder
&bld
,
2524 nir_intrinsic_instr
*instr
)
2526 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2527 const nir_src
&vertex_src
= instr
->src
[0];
2528 nir_intrinsic_instr
*vertex_intrin
= nir_src_as_intrinsic(vertex_src
);
2531 if (nir_src_is_const(vertex_src
)) {
2532 /* Emit a MOV to resolve <0,1,0> regioning. */
2533 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2534 unsigned vertex
= nir_src_as_uint(vertex_src
);
2536 retype(brw_vec1_grf(1 + (vertex
>> 3), vertex
& 7),
2537 BRW_REGISTER_TYPE_UD
));
2538 } else if (tcs_prog_data
->instances
== 1 && vertex_intrin
&&
2539 vertex_intrin
->intrinsic
== nir_intrinsic_load_invocation_id
) {
2540 /* For the common case of only 1 instance, an array index of
2541 * gl_InvocationID means reading g1. Skip all the indirect work.
2543 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2545 /* The vertex index is non-constant. We need to use indirect
2546 * addressing to fetch the proper URB handle.
2548 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2550 /* Each ICP handle is a single DWord (4 bytes) */
2551 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2552 bld
.SHL(vertex_offset_bytes
,
2553 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2556 /* Start at g1. We might read up to 4 registers. */
2557 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2558 retype(brw_vec8_grf(1, 0), icp_handle
.type
), vertex_offset_bytes
,
2559 brw_imm_ud(4 * REG_SIZE
));
2566 fs_visitor::get_tcs_eight_patch_icp_handle(const fs_builder
&bld
,
2567 nir_intrinsic_instr
*instr
)
2569 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2570 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2571 const nir_src
&vertex_src
= instr
->src
[0];
2573 unsigned first_icp_handle
= tcs_prog_data
->include_primitive_id
? 3 : 2;
2575 if (nir_src_is_const(vertex_src
)) {
2576 return fs_reg(retype(brw_vec8_grf(first_icp_handle
+
2577 nir_src_as_uint(vertex_src
), 0),
2578 BRW_REGISTER_TYPE_UD
));
2581 /* The vertex index is non-constant. We need to use indirect
2582 * addressing to fetch the proper URB handle.
2584 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2585 * indicating that channel <n> should read the handle from
2586 * DWord <n>. We convert that to bytes by multiplying by 4.
2588 * Next, we convert the vertex index to bytes by multiplying
2589 * by 32 (shifting by 5), and add the two together. This is
2590 * the final indirect byte offset.
2592 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2593 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
2594 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2595 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2596 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2598 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2599 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2600 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2601 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2602 /* Convert vertex_index to bytes (multiply by 32) */
2603 bld
.SHL(vertex_offset_bytes
,
2604 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2606 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2608 /* Use first_icp_handle as the base offset. There is one register
2609 * of URB handles per vertex, so inform the register allocator that
2610 * we might read up to nir->info.gs.vertices_in registers.
2612 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2613 retype(brw_vec8_grf(first_icp_handle
, 0), icp_handle
.type
),
2614 icp_offset_bytes
, brw_imm_ud(tcs_key
->input_vertices
* REG_SIZE
));
2620 fs_visitor::get_tcs_output_urb_handle()
2622 struct brw_vue_prog_data
*vue_prog_data
= brw_vue_prog_data(prog_data
);
2624 if (vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_SINGLE_PATCH
) {
2625 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2627 assert(vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
);
2628 return retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2633 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2634 nir_intrinsic_instr
*instr
)
2636 assert(stage
== MESA_SHADER_TESS_CTRL
);
2637 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2638 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2639 struct brw_vue_prog_data
*vue_prog_data
= &tcs_prog_data
->base
;
2642 vue_prog_data
->dispatch_mode
== DISPATCH_MODE_TCS_8_PATCH
;
2645 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2646 dst
= get_nir_dest(instr
->dest
);
2648 switch (instr
->intrinsic
) {
2649 case nir_intrinsic_load_primitive_id
:
2650 bld
.MOV(dst
, fs_reg(eight_patch
? brw_vec8_grf(2, 0)
2651 : brw_vec1_grf(0, 1)));
2653 case nir_intrinsic_load_invocation_id
:
2654 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2656 case nir_intrinsic_load_patch_vertices_in
:
2657 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2658 brw_imm_d(tcs_key
->input_vertices
));
2661 case nir_intrinsic_barrier
: {
2662 if (tcs_prog_data
->instances
== 1)
2665 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2666 fs_reg m0_2
= component(m0
, 2);
2668 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2670 /* Zero the message header */
2671 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2673 if (devinfo
->gen
< 11) {
2674 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2675 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2676 brw_imm_ud(INTEL_MASK(16, 13)));
2678 /* Shift it up to bits 27:24. */
2679 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2681 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2682 brw_imm_ud(INTEL_MASK(30, 24)));
2685 /* Set the Barrier Count and the enable bit */
2686 if (devinfo
->gen
< 11) {
2687 chanbld
.OR(m0_2
, m0_2
,
2688 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2690 chanbld
.OR(m0_2
, m0_2
,
2691 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2694 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2698 case nir_intrinsic_load_input
:
2699 unreachable("nir_lower_io should never give us these.");
2702 case nir_intrinsic_load_per_vertex_input
: {
2703 assert(nir_dest_bit_size(instr
->dest
) == 32);
2704 fs_reg indirect_offset
= get_indirect_offset(instr
);
2705 unsigned imm_offset
= instr
->const_index
[0];
2709 eight_patch
? get_tcs_eight_patch_icp_handle(bld
, instr
)
2710 : get_tcs_single_patch_icp_handle(bld
, instr
);
2712 /* We can only read two double components with each URB read, so
2713 * we send two read messages in that case, each one loading up to
2714 * two double components.
2716 unsigned num_components
= instr
->num_components
;
2717 unsigned first_component
= nir_intrinsic_component(instr
);
2719 if (indirect_offset
.file
== BAD_FILE
) {
2720 /* Constant indexing - use global offset. */
2721 if (first_component
!= 0) {
2722 unsigned read_components
= num_components
+ first_component
;
2723 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2724 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2725 for (unsigned i
= 0; i
< num_components
; i
++) {
2726 bld
.MOV(offset(dst
, bld
, i
),
2727 offset(tmp
, bld
, i
+ first_component
));
2730 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2732 inst
->offset
= imm_offset
;
2735 /* Indirect indexing - use per-slot offsets as well. */
2736 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2737 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2738 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2739 if (first_component
!= 0) {
2740 unsigned read_components
= num_components
+ first_component
;
2741 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2742 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2744 for (unsigned i
= 0; i
< num_components
; i
++) {
2745 bld
.MOV(offset(dst
, bld
, i
),
2746 offset(tmp
, bld
, i
+ first_component
));
2749 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2752 inst
->offset
= imm_offset
;
2755 inst
->size_written
= (num_components
+ first_component
) *
2756 inst
->dst
.component_size(inst
->exec_size
);
2758 /* Copy the temporary to the destination to deal with writemasking.
2760 * Also attempt to deal with gl_PointSize being in the .w component.
2762 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2763 assert(type_sz(dst
.type
) == 4);
2764 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2765 inst
->size_written
= 4 * REG_SIZE
;
2766 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2771 case nir_intrinsic_load_output
:
2772 case nir_intrinsic_load_per_vertex_output
: {
2773 assert(nir_dest_bit_size(instr
->dest
) == 32);
2774 fs_reg indirect_offset
= get_indirect_offset(instr
);
2775 unsigned imm_offset
= instr
->const_index
[0];
2776 unsigned first_component
= nir_intrinsic_component(instr
);
2778 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2781 if (indirect_offset
.file
== BAD_FILE
) {
2782 /* This MOV replicates the output handle to all enabled channels
2783 * is SINGLE_PATCH mode.
2785 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2786 bld
.MOV(patch_handle
, output_handles
);
2789 if (first_component
!= 0) {
2790 unsigned read_components
=
2791 instr
->num_components
+ first_component
;
2792 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2793 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2795 inst
->size_written
= read_components
* REG_SIZE
;
2796 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2797 bld
.MOV(offset(dst
, bld
, i
),
2798 offset(tmp
, bld
, i
+ first_component
));
2801 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2803 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2805 inst
->offset
= imm_offset
;
2809 /* Indirect indexing - use per-slot offsets as well. */
2810 const fs_reg srcs
[] = { output_handles
, indirect_offset
};
2811 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2812 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2813 if (first_component
!= 0) {
2814 unsigned read_components
=
2815 instr
->num_components
+ first_component
;
2816 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2817 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2819 inst
->size_written
= read_components
* REG_SIZE
;
2820 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2821 bld
.MOV(offset(dst
, bld
, i
),
2822 offset(tmp
, bld
, i
+ first_component
));
2825 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2827 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2829 inst
->offset
= imm_offset
;
2835 case nir_intrinsic_store_output
:
2836 case nir_intrinsic_store_per_vertex_output
: {
2837 assert(nir_src_bit_size(instr
->src
[0]) == 32);
2838 fs_reg value
= get_nir_src(instr
->src
[0]);
2839 fs_reg indirect_offset
= get_indirect_offset(instr
);
2840 unsigned imm_offset
= instr
->const_index
[0];
2841 unsigned mask
= instr
->const_index
[1];
2842 unsigned header_regs
= 0;
2843 struct brw_reg output_handles
= get_tcs_output_urb_handle();
2846 srcs
[header_regs
++] = output_handles
;
2848 if (indirect_offset
.file
!= BAD_FILE
) {
2849 srcs
[header_regs
++] = indirect_offset
;
2855 unsigned num_components
= util_last_bit(mask
);
2858 /* We can only pack two 64-bit components in a single message, so send
2859 * 2 messages if we have more components
2861 unsigned first_component
= nir_intrinsic_component(instr
);
2862 mask
= mask
<< first_component
;
2864 if (mask
!= WRITEMASK_XYZW
) {
2865 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2866 opcode
= indirect_offset
.file
!= BAD_FILE
?
2867 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2868 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2870 opcode
= indirect_offset
.file
!= BAD_FILE
?
2871 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2872 SHADER_OPCODE_URB_WRITE_SIMD8
;
2875 for (unsigned i
= 0; i
< num_components
; i
++) {
2876 if (!(mask
& (1 << (i
+ first_component
))))
2879 srcs
[header_regs
+ i
+ first_component
] = offset(value
, bld
, i
);
2882 unsigned mlen
= header_regs
+ num_components
+ first_component
;
2884 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2885 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2887 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2888 inst
->offset
= imm_offset
;
2894 nir_emit_intrinsic(bld
, instr
);
2900 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2901 nir_intrinsic_instr
*instr
)
2903 assert(stage
== MESA_SHADER_TESS_EVAL
);
2904 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2907 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2908 dest
= get_nir_dest(instr
->dest
);
2910 switch (instr
->intrinsic
) {
2911 case nir_intrinsic_load_primitive_id
:
2912 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2914 case nir_intrinsic_load_tess_coord
:
2915 /* gl_TessCoord is part of the payload in g1-3 */
2916 for (unsigned i
= 0; i
< 3; i
++) {
2917 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2921 case nir_intrinsic_load_input
:
2922 case nir_intrinsic_load_per_vertex_input
: {
2923 assert(nir_dest_bit_size(instr
->dest
) == 32);
2924 fs_reg indirect_offset
= get_indirect_offset(instr
);
2925 unsigned imm_offset
= instr
->const_index
[0];
2926 unsigned first_component
= nir_intrinsic_component(instr
);
2929 if (indirect_offset
.file
== BAD_FILE
) {
2930 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2931 * which is 16 registers (since each holds 2 vec4 slots).
2933 const unsigned max_push_slots
= 32;
2934 if (imm_offset
< max_push_slots
) {
2935 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2936 for (int i
= 0; i
< instr
->num_components
; i
++) {
2937 unsigned comp
= 4 * (imm_offset
% 2) + i
+ first_component
;
2938 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2941 tes_prog_data
->base
.urb_read_length
=
2942 MAX2(tes_prog_data
->base
.urb_read_length
,
2943 (imm_offset
/ 2) + 1);
2945 /* Replicate the patch handle to all enabled channels */
2946 const fs_reg srcs
[] = {
2947 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2949 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2950 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2952 if (first_component
!= 0) {
2953 unsigned read_components
=
2954 instr
->num_components
+ first_component
;
2955 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2956 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2958 inst
->size_written
= read_components
* REG_SIZE
;
2959 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2960 bld
.MOV(offset(dest
, bld
, i
),
2961 offset(tmp
, bld
, i
+ first_component
));
2964 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2966 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2969 inst
->offset
= imm_offset
;
2972 /* Indirect indexing - use per-slot offsets as well. */
2974 /* We can only read two double components with each URB read, so
2975 * we send two read messages in that case, each one loading up to
2976 * two double components.
2978 unsigned num_components
= instr
->num_components
;
2979 const fs_reg srcs
[] = {
2980 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2983 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2984 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2986 if (first_component
!= 0) {
2987 unsigned read_components
=
2988 num_components
+ first_component
;
2989 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2990 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2992 for (unsigned i
= 0; i
< num_components
; i
++) {
2993 bld
.MOV(offset(dest
, bld
, i
),
2994 offset(tmp
, bld
, i
+ first_component
));
2997 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3001 inst
->offset
= imm_offset
;
3002 inst
->size_written
= (num_components
+ first_component
) *
3003 inst
->dst
.component_size(inst
->exec_size
);
3008 nir_emit_intrinsic(bld
, instr
);
3014 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3015 nir_intrinsic_instr
*instr
)
3017 assert(stage
== MESA_SHADER_GEOMETRY
);
3018 fs_reg indirect_offset
;
3021 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3022 dest
= get_nir_dest(instr
->dest
);
3024 switch (instr
->intrinsic
) {
3025 case nir_intrinsic_load_primitive_id
:
3026 assert(stage
== MESA_SHADER_GEOMETRY
);
3027 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3028 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3029 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3032 case nir_intrinsic_load_input
:
3033 unreachable("load_input intrinsics are invalid for the GS stage");
3035 case nir_intrinsic_load_per_vertex_input
:
3036 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3037 instr
->src
[1], instr
->num_components
,
3038 nir_intrinsic_component(instr
));
3041 case nir_intrinsic_emit_vertex_with_counter
:
3042 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3045 case nir_intrinsic_end_primitive_with_counter
:
3046 emit_gs_end_primitive(instr
->src
[0]);
3049 case nir_intrinsic_set_vertex_count
:
3050 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3053 case nir_intrinsic_load_invocation_id
: {
3054 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3055 assert(val
.file
!= BAD_FILE
);
3056 dest
.type
= val
.type
;
3062 nir_emit_intrinsic(bld
, instr
);
3068 * Fetch the current render target layer index.
3071 fetch_render_target_array_index(const fs_builder
&bld
)
3073 if (bld
.shader
->devinfo
->gen
>= 6) {
3074 /* The render target array index is provided in the thread payload as
3075 * bits 26:16 of r0.0.
3077 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3078 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3082 /* Pre-SNB we only ever render into the first layer of the framebuffer
3083 * since layered rendering is not implemented.
3085 return brw_imm_ud(0);
3090 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3091 * framebuffer at the current fragment coordinates and sample index.
3094 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3097 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3099 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3100 const brw_wm_prog_key
*wm_key
=
3101 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3102 assert(!wm_key
->coherent_fb_fetch
);
3103 const struct brw_wm_prog_data
*wm_prog_data
=
3104 brw_wm_prog_data(stage_prog_data
);
3106 /* Calculate the surface index relative to the start of the texture binding
3107 * table block, since that's what the texturing messages expect.
3109 const unsigned surface
= target
+
3110 wm_prog_data
->binding_table
.render_target_read_start
-
3111 wm_prog_data
->base
.binding_table
.texture_start
;
3113 /* Calculate the fragment coordinates. */
3114 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3115 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3116 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3117 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3119 /* Calculate the sample index and MCS payload when multisampling. Luckily
3120 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3121 * shouldn't be necessary to recompile based on whether the framebuffer is
3124 if (wm_key
->multisample_fbo
&&
3125 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3126 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3128 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3129 const fs_reg mcs
= wm_key
->multisample_fbo
?
3130 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
), fs_reg()) : fs_reg();
3132 /* Use either a normal or a CMS texel fetch message depending on whether
3133 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3134 * message just in case the framebuffer uses 16x multisampling, it should
3135 * be equivalent to the normal CMS fetch for lower multisampling modes.
3137 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3138 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3139 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3141 /* Emit the instruction. */
3142 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3143 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = coords
;
3144 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0);
3145 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = sample
;
3146 srcs
[TEX_LOGICAL_SRC_MCS
] = mcs
;
3147 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3148 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(0);
3149 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_ud(3);
3150 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_ud(0);
3152 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3153 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3159 * Actual coherent framebuffer read implemented using the native render target
3160 * read message. Requires SKL+.
3163 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3165 assert(bld
.shader
->devinfo
->gen
>= 9);
3166 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3167 inst
->target
= target
;
3168 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3174 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3176 if (n
&& regs
[0].file
!= BAD_FILE
) {
3180 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3182 for (unsigned i
= 0; i
< n
; i
++)
3190 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3192 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3193 const brw_wm_prog_key
*const key
=
3194 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3195 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3196 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3198 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3199 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3201 else if (l
== FRAG_RESULT_COLOR
)
3202 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3203 MAX2(key
->nr_color_regions
, 1));
3205 else if (l
== FRAG_RESULT_DEPTH
)
3206 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3208 else if (l
== FRAG_RESULT_STENCIL
)
3209 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3211 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3212 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3214 else if (l
>= FRAG_RESULT_DATA0
&&
3215 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3216 return alloc_temporary(v
->bld
, 4,
3217 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3220 unreachable("Invalid location");
3223 /* Annoyingly, we get the barycentrics into the shader in a layout that's
3224 * optimized for PLN but it doesn't work nearly as well as one would like for
3225 * manual interpolation.
3228 shuffle_from_pln_layout(const fs_builder
&bld
, fs_reg dest
, fs_reg pln_data
)
3230 dest
.type
= BRW_REGISTER_TYPE_F
;
3231 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3232 const fs_reg dest_u
= offset(dest
, bld
, 0);
3233 const fs_reg dest_v
= offset(dest
, bld
, 1);
3235 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3236 const fs_builder gbld
= bld
.group(8, g
);
3237 gbld
.MOV(horiz_offset(dest_u
, g
* 8),
3238 byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
));
3239 gbld
.MOV(horiz_offset(dest_v
, g
* 8),
3240 byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
));
3245 shuffle_to_pln_layout(const fs_builder
&bld
, fs_reg pln_data
, fs_reg src
)
3247 pln_data
.type
= BRW_REGISTER_TYPE_F
;
3248 src
.type
= BRW_REGISTER_TYPE_F
;
3249 const fs_reg src_u
= offset(src
, bld
, 0);
3250 const fs_reg src_v
= offset(src
, bld
, 1);
3252 for (unsigned g
= 0; g
< bld
.dispatch_width() / 8; g
++) {
3253 const fs_builder gbld
= bld
.group(8, g
);
3254 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 0) * REG_SIZE
),
3255 horiz_offset(src_u
, g
* 8));
3256 gbld
.MOV(byte_offset(pln_data
, (g
* 2 + 1) * REG_SIZE
),
3257 horiz_offset(src_v
, g
* 8));
3262 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3263 nir_intrinsic_instr
*instr
)
3265 assert(stage
== MESA_SHADER_FRAGMENT
);
3268 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3269 dest
= get_nir_dest(instr
->dest
);
3271 switch (instr
->intrinsic
) {
3272 case nir_intrinsic_load_front_face
:
3273 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3274 *emit_frontfacing_interpolation());
3277 case nir_intrinsic_load_sample_pos
: {
3278 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3279 assert(sample_pos
.file
!= BAD_FILE
);
3280 dest
.type
= sample_pos
.type
;
3281 bld
.MOV(dest
, sample_pos
);
3282 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3286 case nir_intrinsic_load_layer_id
:
3287 dest
.type
= BRW_REGISTER_TYPE_UD
;
3288 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3291 case nir_intrinsic_is_helper_invocation
: {
3292 /* Unlike the regular gl_HelperInvocation, that is defined at dispatch,
3293 * the helperInvocationEXT() (aka SpvOpIsHelperInvocationEXT) takes into
3294 * consideration demoted invocations. That information is stored in
3297 dest
.type
= BRW_REGISTER_TYPE_UD
;
3299 bld
.MOV(dest
, brw_imm_ud(0));
3301 fs_inst
*mov
= bld
.MOV(dest
, brw_imm_ud(~0));
3302 mov
->predicate
= BRW_PREDICATE_NORMAL
;
3303 mov
->predicate_inverse
= true;
3304 mov
->flag_subreg
= 1;
3308 case nir_intrinsic_load_helper_invocation
:
3309 case nir_intrinsic_load_sample_mask_in
:
3310 case nir_intrinsic_load_sample_id
: {
3311 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3312 fs_reg val
= nir_system_values
[sv
];
3313 assert(val
.file
!= BAD_FILE
);
3314 dest
.type
= val
.type
;
3319 case nir_intrinsic_store_output
: {
3320 const fs_reg src
= get_nir_src(instr
->src
[0]);
3321 const unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
3322 const unsigned location
= nir_intrinsic_base(instr
) +
3323 SET_FIELD(store_offset
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3324 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3327 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3328 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3329 offset(src
, bld
, j
));
3334 case nir_intrinsic_load_output
: {
3335 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3336 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3337 assert(l
>= FRAG_RESULT_DATA0
);
3338 const unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
3339 const unsigned target
= l
- FRAG_RESULT_DATA0
+ load_offset
;
3340 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3342 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3343 emit_coherent_fb_read(bld
, tmp
, target
);
3345 emit_non_coherent_fb_read(bld
, tmp
, target
);
3347 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3348 bld
.MOV(offset(dest
, bld
, j
),
3349 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3355 case nir_intrinsic_demote
:
3356 case nir_intrinsic_discard
:
3357 case nir_intrinsic_demote_if
:
3358 case nir_intrinsic_discard_if
: {
3359 /* We track our discarded pixels in f0.1. By predicating on it, we can
3360 * update just the flag bits that aren't yet discarded. If there's no
3361 * condition, we emit a CMP of g0 != g0, so all currently executing
3362 * channels will get turned off.
3364 fs_inst
*cmp
= NULL
;
3365 if (instr
->intrinsic
== nir_intrinsic_demote_if
||
3366 instr
->intrinsic
== nir_intrinsic_discard_if
) {
3367 nir_alu_instr
*alu
= nir_src_as_alu_instr(instr
->src
[0]);
3370 alu
->op
!= nir_op_bcsel
&&
3371 alu
->op
!= nir_op_inot
) {
3372 /* Re-emit the instruction that generated the Boolean value, but
3373 * do not store it. Since this instruction will be conditional,
3374 * other instructions that want to use the real Boolean value may
3375 * get garbage. This was a problem for piglit's fs-discard-exit-2
3378 * Ideally we'd detect that the instruction cannot have a
3379 * conditional modifier before emitting the instructions. Alas,
3380 * that is nigh impossible. Instead, we're going to assume the
3381 * instruction (or last instruction) generated can have a
3382 * conditional modifier. If it cannot, fallback to the old-style
3383 * compare, and hope dead code elimination will clean up the
3384 * extra instructions generated.
3386 nir_emit_alu(bld
, alu
, false);
3388 cmp
= (fs_inst
*) instructions
.get_tail();
3389 if (cmp
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
3390 if (cmp
->can_do_cmod())
3391 cmp
->conditional_mod
= BRW_CONDITIONAL_Z
;
3395 /* The old sequence that would have been generated is,
3396 * basically, bool_result == false. This is equivalent to
3397 * !bool_result, so negate the old modifier.
3399 cmp
->conditional_mod
= brw_negate_cmod(cmp
->conditional_mod
);
3404 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3405 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3408 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3409 BRW_REGISTER_TYPE_UW
));
3410 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3413 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3414 cmp
->flag_subreg
= 1;
3416 if (devinfo
->gen
>= 6) {
3417 /* Due to the way we implement discard, the jump will only happen
3418 * when the whole quad is discarded. So we can do this even for
3419 * demote as it won't break its uniformity promises.
3421 emit_discard_jump();
3424 limit_dispatch_width(16, "Fragment discard/demote not implemented in SIMD32 mode.");
3428 case nir_intrinsic_load_input
: {
3429 /* load_input is only used for flat inputs */
3430 assert(nir_dest_bit_size(instr
->dest
) == 32);
3431 unsigned base
= nir_intrinsic_base(instr
);
3432 unsigned comp
= nir_intrinsic_component(instr
);
3433 unsigned num_components
= instr
->num_components
;
3435 /* Special case fields in the VUE header */
3436 if (base
== VARYING_SLOT_LAYER
)
3438 else if (base
== VARYING_SLOT_VIEWPORT
)
3441 for (unsigned int i
= 0; i
< num_components
; i
++) {
3442 bld
.MOV(offset(dest
, bld
, i
),
3443 retype(component(interp_reg(base
, comp
+ i
), 3), dest
.type
));
3448 case nir_intrinsic_load_fs_input_interp_deltas
: {
3449 assert(stage
== MESA_SHADER_FRAGMENT
);
3450 assert(nir_src_as_uint(instr
->src
[0]) == 0);
3451 fs_reg interp
= interp_reg(nir_intrinsic_base(instr
),
3452 nir_intrinsic_component(instr
));
3453 dest
.type
= BRW_REGISTER_TYPE_F
;
3454 bld
.MOV(offset(dest
, bld
, 0), component(interp
, 3));
3455 bld
.MOV(offset(dest
, bld
, 1), component(interp
, 1));
3456 bld
.MOV(offset(dest
, bld
, 2), component(interp
, 0));
3460 case nir_intrinsic_load_barycentric_pixel
:
3461 case nir_intrinsic_load_barycentric_centroid
:
3462 case nir_intrinsic_load_barycentric_sample
: {
3463 /* Use the delta_xy values computed from the payload */
3464 const glsl_interp_mode interp_mode
=
3465 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3466 enum brw_barycentric_mode bary
=
3467 brw_barycentric_mode(interp_mode
, instr
->intrinsic
);
3469 shuffle_from_pln_layout(bld
, dest
, this->delta_xy
[bary
]);
3473 case nir_intrinsic_load_barycentric_at_sample
: {
3474 const glsl_interp_mode interpolation
=
3475 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3477 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3478 if (nir_src_is_const(instr
->src
[0])) {
3479 unsigned msg_data
= nir_src_as_uint(instr
->src
[0]) << 4;
3481 emit_pixel_interpolater_send(bld
,
3482 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3485 brw_imm_ud(msg_data
),
3488 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3489 BRW_REGISTER_TYPE_UD
);
3491 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3492 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3493 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3494 bld
.exec_all().group(1, 0)
3495 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3496 emit_pixel_interpolater_send(bld
,
3497 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3503 /* Make a loop that sends a message to the pixel interpolater
3504 * for the sample number in each live channel. If there are
3505 * multiple channels with the same sample number then these
3506 * will be handled simultaneously with a single interation of
3509 bld
.emit(BRW_OPCODE_DO
);
3511 /* Get the next live sample number into sample_id_reg */
3512 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3514 /* Set the flag register so that we can perform the send
3515 * message on all channels that have the same sample number
3517 bld
.CMP(bld
.null_reg_ud(),
3518 sample_src
, sample_id
,
3519 BRW_CONDITIONAL_EQ
);
3520 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3521 bld
.exec_all().group(1, 0)
3522 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3524 emit_pixel_interpolater_send(bld
,
3525 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3528 component(msg_data
, 0),
3530 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3532 /* Continue the loop if there are any live channels left */
3533 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3535 bld
.emit(BRW_OPCODE_WHILE
));
3538 shuffle_from_pln_layout(bld
, dest
, tmp
);
3542 case nir_intrinsic_load_barycentric_at_offset
: {
3543 const glsl_interp_mode interpolation
=
3544 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3546 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3548 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3550 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3551 unsigned off_x
= MIN2((int)(const_offset
[0].f32
* 16), 7) & 0xf;
3552 unsigned off_y
= MIN2((int)(const_offset
[1].f32
* 16), 7) & 0xf;
3554 emit_pixel_interpolater_send(bld
,
3555 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3558 brw_imm_ud(off_x
| (off_y
<< 4)),
3561 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3562 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3563 BRW_REGISTER_TYPE_F
);
3564 for (int i
= 0; i
< 2; i
++) {
3565 fs_reg temp
= vgrf(glsl_type::float_type
);
3566 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3567 fs_reg itemp
= vgrf(glsl_type::int_type
);
3569 bld
.MOV(itemp
, temp
);
3571 /* Clamp the upper end of the range to +7/16.
3572 * ARB_gpu_shader5 requires that we support a maximum offset
3573 * of +0.5, which isn't representable in a S0.4 value -- if
3574 * we didn't clamp it, we'd end up with -8/16, which is the
3575 * opposite of what the shader author wanted.
3577 * This is legal due to ARB_gpu_shader5's quantization
3580 * "Not all values of <offset> may be supported; x and y
3581 * offsets may be rounded to fixed-point values with the
3582 * number of fraction bits given by the
3583 * implementation-dependent constant
3584 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3586 set_condmod(BRW_CONDITIONAL_L
,
3587 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3590 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3591 emit_pixel_interpolater_send(bld
,
3598 shuffle_from_pln_layout(bld
, dest
, tmp
);
3602 case nir_intrinsic_load_frag_coord
:
3603 emit_fragcoord_interpolation(dest
);
3606 case nir_intrinsic_load_interpolated_input
: {
3607 assert(instr
->src
[0].ssa
&&
3608 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3609 nir_intrinsic_instr
*bary_intrinsic
=
3610 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3611 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3612 enum glsl_interp_mode interp_mode
=
3613 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3616 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3617 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3618 /* Use the result of the PI message. Because the load_barycentric
3619 * intrinsics return a regular vec2 and we need it in PLN layout, we
3620 * have to do a translation. Fortunately, copy-prop cleans this up
3623 dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
3624 shuffle_to_pln_layout(bld
, dst_xy
, get_nir_src(instr
->src
[0]));
3626 /* Use the delta_xy values computed from the payload */
3627 enum brw_barycentric_mode bary
=
3628 brw_barycentric_mode(interp_mode
, bary_intrin
);
3630 dst_xy
= this->delta_xy
[bary
];
3633 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3635 interp_reg(nir_intrinsic_base(instr
),
3636 nir_intrinsic_component(instr
) + i
);
3637 interp
.type
= BRW_REGISTER_TYPE_F
;
3638 dest
.type
= BRW_REGISTER_TYPE_F
;
3640 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3641 fs_reg tmp
= vgrf(glsl_type::float_type
);
3642 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3643 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3645 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3652 nir_emit_intrinsic(bld
, instr
);
3658 get_op_for_atomic_add(nir_intrinsic_instr
*instr
, unsigned src
)
3660 if (nir_src_is_const(instr
->src
[src
])) {
3661 int64_t add_val
= nir_src_as_int(instr
->src
[src
]);
3664 else if (add_val
== -1)
3672 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3673 nir_intrinsic_instr
*instr
)
3675 assert(stage
== MESA_SHADER_COMPUTE
);
3676 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3679 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3680 dest
= get_nir_dest(instr
->dest
);
3682 switch (instr
->intrinsic
) {
3683 case nir_intrinsic_barrier
:
3685 cs_prog_data
->uses_barrier
= true;
3688 case nir_intrinsic_load_subgroup_id
:
3689 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), subgroup_id
);
3692 case nir_intrinsic_load_local_invocation_id
:
3693 case nir_intrinsic_load_work_group_id
: {
3694 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3695 fs_reg val
= nir_system_values
[sv
];
3696 assert(val
.file
!= BAD_FILE
);
3697 dest
.type
= val
.type
;
3698 for (unsigned i
= 0; i
< 3; i
++)
3699 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3703 case nir_intrinsic_load_num_work_groups
: {
3704 const unsigned surface
=
3705 cs_prog_data
->binding_table
.work_groups_start
;
3707 cs_prog_data
->uses_num_work_groups
= true;
3709 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3710 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(surface
);
3711 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3712 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(1); /* num components */
3714 /* Read the 3 GLuint components of gl_NumWorkGroups */
3715 for (unsigned i
= 0; i
< 3; i
++) {
3716 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = brw_imm_ud(i
<< 2);
3717 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3718 offset(dest
, bld
, i
), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3723 case nir_intrinsic_shared_atomic_add
:
3724 nir_emit_shared_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
3726 case nir_intrinsic_shared_atomic_imin
:
3727 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3729 case nir_intrinsic_shared_atomic_umin
:
3730 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3732 case nir_intrinsic_shared_atomic_imax
:
3733 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3735 case nir_intrinsic_shared_atomic_umax
:
3736 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3738 case nir_intrinsic_shared_atomic_and
:
3739 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3741 case nir_intrinsic_shared_atomic_or
:
3742 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3744 case nir_intrinsic_shared_atomic_xor
:
3745 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3747 case nir_intrinsic_shared_atomic_exchange
:
3748 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3750 case nir_intrinsic_shared_atomic_comp_swap
:
3751 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3753 case nir_intrinsic_shared_atomic_fmin
:
3754 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
3756 case nir_intrinsic_shared_atomic_fmax
:
3757 nir_emit_shared_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
3759 case nir_intrinsic_shared_atomic_fcomp_swap
:
3760 nir_emit_shared_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
3763 case nir_intrinsic_load_shared
: {
3764 assert(devinfo
->gen
>= 7);
3765 assert(stage
== MESA_SHADER_COMPUTE
);
3767 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
3768 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3769 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3770 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[0]);
3771 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3773 /* Make dest unsigned because that's what the temporary will be */
3774 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3776 /* Read the vector */
3777 if (nir_intrinsic_align(instr
) >= 4) {
3778 assert(nir_dest_bit_size(instr
->dest
) == 32);
3779 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3781 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
3782 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3783 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
3785 assert(nir_dest_bit_size(instr
->dest
) <= 32);
3786 assert(nir_dest_num_components(instr
->dest
) == 1);
3787 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3789 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3790 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
3791 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3792 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
3797 case nir_intrinsic_store_shared
: {
3798 assert(devinfo
->gen
>= 7);
3799 assert(stage
== MESA_SHADER_COMPUTE
);
3801 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
3802 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
3803 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
3804 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
3805 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
3807 fs_reg data
= get_nir_src(instr
->src
[0]);
3808 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
3810 assert(nir_intrinsic_write_mask(instr
) ==
3811 (1u << instr
->num_components
) - 1);
3812 if (nir_intrinsic_align(instr
) >= 4) {
3813 assert(nir_src_bit_size(instr
->src
[0]) == 32);
3814 assert(nir_src_num_components(instr
->src
[0]) <= 4);
3815 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
3816 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
3817 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
3818 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3820 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
3821 assert(nir_src_num_components(instr
->src
[0]) == 1);
3822 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
3824 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3825 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
3827 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
3828 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
3834 nir_emit_intrinsic(bld
, instr
);
3840 brw_nir_reduction_op_identity(const fs_builder
&bld
,
3841 nir_op op
, brw_reg_type type
)
3843 nir_const_value value
= nir_alu_binop_identity(op
, type_sz(type
) * 8);
3844 switch (type_sz(type
)) {
3846 assert(type
!= BRW_REGISTER_TYPE_HF
);
3847 return retype(brw_imm_uw(value
.u16
), type
);
3849 return retype(brw_imm_ud(value
.u32
), type
);
3851 if (type
== BRW_REGISTER_TYPE_DF
)
3852 return setup_imm_df(bld
, value
.f64
);
3854 return retype(brw_imm_u64(value
.u64
), type
);
3856 unreachable("Invalid type size");
3861 brw_op_for_nir_reduction_op(nir_op op
)
3864 case nir_op_iadd
: return BRW_OPCODE_ADD
;
3865 case nir_op_fadd
: return BRW_OPCODE_ADD
;
3866 case nir_op_imul
: return BRW_OPCODE_MUL
;
3867 case nir_op_fmul
: return BRW_OPCODE_MUL
;
3868 case nir_op_imin
: return BRW_OPCODE_SEL
;
3869 case nir_op_umin
: return BRW_OPCODE_SEL
;
3870 case nir_op_fmin
: return BRW_OPCODE_SEL
;
3871 case nir_op_imax
: return BRW_OPCODE_SEL
;
3872 case nir_op_umax
: return BRW_OPCODE_SEL
;
3873 case nir_op_fmax
: return BRW_OPCODE_SEL
;
3874 case nir_op_iand
: return BRW_OPCODE_AND
;
3875 case nir_op_ior
: return BRW_OPCODE_OR
;
3876 case nir_op_ixor
: return BRW_OPCODE_XOR
;
3878 unreachable("Invalid reduction operation");
3882 static brw_conditional_mod
3883 brw_cond_mod_for_nir_reduction_op(nir_op op
)
3886 case nir_op_iadd
: return BRW_CONDITIONAL_NONE
;
3887 case nir_op_fadd
: return BRW_CONDITIONAL_NONE
;
3888 case nir_op_imul
: return BRW_CONDITIONAL_NONE
;
3889 case nir_op_fmul
: return BRW_CONDITIONAL_NONE
;
3890 case nir_op_imin
: return BRW_CONDITIONAL_L
;
3891 case nir_op_umin
: return BRW_CONDITIONAL_L
;
3892 case nir_op_fmin
: return BRW_CONDITIONAL_L
;
3893 case nir_op_imax
: return BRW_CONDITIONAL_GE
;
3894 case nir_op_umax
: return BRW_CONDITIONAL_GE
;
3895 case nir_op_fmax
: return BRW_CONDITIONAL_GE
;
3896 case nir_op_iand
: return BRW_CONDITIONAL_NONE
;
3897 case nir_op_ior
: return BRW_CONDITIONAL_NONE
;
3898 case nir_op_ixor
: return BRW_CONDITIONAL_NONE
;
3900 unreachable("Invalid reduction operation");
3905 fs_visitor::get_nir_image_intrinsic_image(const brw::fs_builder
&bld
,
3906 nir_intrinsic_instr
*instr
)
3908 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]), BRW_REGISTER_TYPE_UD
);
3910 if (stage_prog_data
->binding_table
.image_start
> 0) {
3911 if (image
.file
== BRW_IMMEDIATE_VALUE
) {
3912 image
.d
+= stage_prog_data
->binding_table
.image_start
;
3914 bld
.ADD(image
, image
,
3915 brw_imm_d(stage_prog_data
->binding_table
.image_start
));
3919 return bld
.emit_uniformize(image
);
3923 fs_visitor::get_nir_ssbo_intrinsic_index(const brw::fs_builder
&bld
,
3924 nir_intrinsic_instr
*instr
)
3926 /* SSBO stores are weird in that their index is in src[1] */
3927 const unsigned src
= instr
->intrinsic
== nir_intrinsic_store_ssbo
? 1 : 0;
3930 if (nir_src_is_const(instr
->src
[src
])) {
3931 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3932 nir_src_as_uint(instr
->src
[src
]);
3933 surf_index
= brw_imm_ud(index
);
3935 surf_index
= vgrf(glsl_type::uint_type
);
3936 bld
.ADD(surf_index
, get_nir_src(instr
->src
[src
]),
3937 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3940 return bld
.emit_uniformize(surf_index
);
3944 image_intrinsic_coord_components(nir_intrinsic_instr
*instr
)
3946 switch (nir_intrinsic_image_dim(instr
)) {
3947 case GLSL_SAMPLER_DIM_1D
:
3948 return 1 + nir_intrinsic_image_array(instr
);
3949 case GLSL_SAMPLER_DIM_2D
:
3950 case GLSL_SAMPLER_DIM_RECT
:
3951 return 2 + nir_intrinsic_image_array(instr
);
3952 case GLSL_SAMPLER_DIM_3D
:
3953 case GLSL_SAMPLER_DIM_CUBE
:
3955 case GLSL_SAMPLER_DIM_BUF
:
3957 case GLSL_SAMPLER_DIM_MS
:
3958 return 2 + nir_intrinsic_image_array(instr
);
3960 unreachable("Invalid image dimension");
3965 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3968 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3969 dest
= get_nir_dest(instr
->dest
);
3971 switch (instr
->intrinsic
) {
3972 case nir_intrinsic_image_load
:
3973 case nir_intrinsic_image_store
:
3974 case nir_intrinsic_image_atomic_add
:
3975 case nir_intrinsic_image_atomic_imin
:
3976 case nir_intrinsic_image_atomic_umin
:
3977 case nir_intrinsic_image_atomic_imax
:
3978 case nir_intrinsic_image_atomic_umax
:
3979 case nir_intrinsic_image_atomic_and
:
3980 case nir_intrinsic_image_atomic_or
:
3981 case nir_intrinsic_image_atomic_xor
:
3982 case nir_intrinsic_image_atomic_exchange
:
3983 case nir_intrinsic_image_atomic_comp_swap
:
3984 case nir_intrinsic_bindless_image_load
:
3985 case nir_intrinsic_bindless_image_store
:
3986 case nir_intrinsic_bindless_image_atomic_add
:
3987 case nir_intrinsic_bindless_image_atomic_imin
:
3988 case nir_intrinsic_bindless_image_atomic_umin
:
3989 case nir_intrinsic_bindless_image_atomic_imax
:
3990 case nir_intrinsic_bindless_image_atomic_umax
:
3991 case nir_intrinsic_bindless_image_atomic_and
:
3992 case nir_intrinsic_bindless_image_atomic_or
:
3993 case nir_intrinsic_bindless_image_atomic_xor
:
3994 case nir_intrinsic_bindless_image_atomic_exchange
:
3995 case nir_intrinsic_bindless_image_atomic_comp_swap
: {
3996 if (stage
== MESA_SHADER_FRAGMENT
&&
3997 instr
->intrinsic
!= nir_intrinsic_image_load
)
3998 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4000 /* Get some metadata from the image intrinsic. */
4001 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
4002 const GLenum format
= nir_intrinsic_format(instr
);
4004 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4006 switch (instr
->intrinsic
) {
4007 case nir_intrinsic_image_load
:
4008 case nir_intrinsic_image_store
:
4009 case nir_intrinsic_image_atomic_add
:
4010 case nir_intrinsic_image_atomic_imin
:
4011 case nir_intrinsic_image_atomic_umin
:
4012 case nir_intrinsic_image_atomic_imax
:
4013 case nir_intrinsic_image_atomic_umax
:
4014 case nir_intrinsic_image_atomic_and
:
4015 case nir_intrinsic_image_atomic_or
:
4016 case nir_intrinsic_image_atomic_xor
:
4017 case nir_intrinsic_image_atomic_exchange
:
4018 case nir_intrinsic_image_atomic_comp_swap
:
4019 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4020 get_nir_image_intrinsic_image(bld
, instr
);
4025 srcs
[SURFACE_LOGICAL_SRC_SURFACE_HANDLE
] =
4026 bld
.emit_uniformize(get_nir_src(instr
->src
[0]));
4030 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4031 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] =
4032 brw_imm_ud(image_intrinsic_coord_components(instr
));
4034 /* Emit an image load, store or atomic op. */
4035 if (instr
->intrinsic
== nir_intrinsic_image_load
||
4036 instr
->intrinsic
== nir_intrinsic_bindless_image_load
) {
4037 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4039 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
4040 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4041 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4042 } else if (instr
->intrinsic
== nir_intrinsic_image_store
||
4043 instr
->intrinsic
== nir_intrinsic_bindless_image_store
) {
4044 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4045 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[3]);
4046 bld
.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
4047 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4050 unsigned num_srcs
= info
->num_srcs
;
4052 switch (instr
->intrinsic
) {
4053 case nir_intrinsic_image_atomic_add
:
4054 case nir_intrinsic_bindless_image_atomic_add
:
4055 assert(num_srcs
== 4);
4057 op
= get_op_for_atomic_add(instr
, 3);
4059 if (op
!= BRW_AOP_ADD
)
4062 case nir_intrinsic_image_atomic_imin
:
4063 case nir_intrinsic_bindless_image_atomic_imin
:
4064 assert(format
== GL_R32I
);
4067 case nir_intrinsic_image_atomic_umin
:
4068 case nir_intrinsic_bindless_image_atomic_umin
:
4069 assert(format
== GL_R32UI
);
4072 case nir_intrinsic_image_atomic_imax
:
4073 case nir_intrinsic_bindless_image_atomic_imax
:
4074 assert(format
== GL_R32I
);
4077 case nir_intrinsic_image_atomic_umax
:
4078 case nir_intrinsic_bindless_image_atomic_umax
:
4079 assert(format
== GL_R32UI
);
4082 case nir_intrinsic_image_atomic_and
:
4083 case nir_intrinsic_bindless_image_atomic_and
:
4086 case nir_intrinsic_image_atomic_or
:
4087 case nir_intrinsic_bindless_image_atomic_or
:
4090 case nir_intrinsic_image_atomic_xor
:
4091 case nir_intrinsic_bindless_image_atomic_xor
:
4094 case nir_intrinsic_image_atomic_exchange
:
4095 case nir_intrinsic_bindless_image_atomic_exchange
:
4098 case nir_intrinsic_image_atomic_comp_swap
:
4099 case nir_intrinsic_bindless_image_atomic_comp_swap
:
4103 unreachable("Not reachable.");
4106 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
4110 data
= get_nir_src(instr
->src
[3]);
4111 if (num_srcs
>= 5) {
4112 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
4113 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[4]) };
4114 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
4117 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4119 bld
.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
4120 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4125 case nir_intrinsic_image_size
:
4126 case nir_intrinsic_bindless_image_size
: {
4127 /* Unlike the [un]typed load and store opcodes, the TXS that this turns
4128 * into will handle the binding table index for us in the geneerator.
4129 * Incidentally, this means that we can handle bindless with exactly the
4132 fs_reg image
= retype(get_nir_src_imm(instr
->src
[0]),
4133 BRW_REGISTER_TYPE_UD
);
4134 image
= bld
.emit_uniformize(image
);
4136 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4137 if (instr
->intrinsic
== nir_intrinsic_image_size
)
4138 srcs
[TEX_LOGICAL_SRC_SURFACE
] = image
;
4140 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = image
;
4141 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_d(0);
4142 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(0);
4143 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(0);
4145 /* Since the image size is always uniform, we can just emit a SIMD8
4146 * query instruction and splat the result out.
4148 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4150 fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4151 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL
,
4152 tmp
, srcs
, ARRAY_SIZE(srcs
));
4153 inst
->size_written
= 4 * REG_SIZE
;
4155 for (unsigned c
= 0; c
< instr
->dest
.ssa
.num_components
; ++c
) {
4156 if (c
== 2 && nir_intrinsic_image_dim(instr
) == GLSL_SAMPLER_DIM_CUBE
) {
4157 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
4158 offset(retype(dest
, tmp
.type
), bld
, c
),
4159 component(offset(tmp
, ubld
, c
), 0), brw_imm_ud(6));
4161 bld
.MOV(offset(retype(dest
, tmp
.type
), bld
, c
),
4162 component(offset(tmp
, ubld
, c
), 0));
4168 case nir_intrinsic_image_load_raw_intel
: {
4169 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4170 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4171 get_nir_image_intrinsic_image(bld
, instr
);
4172 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4173 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4174 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4177 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4178 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4179 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4183 case nir_intrinsic_image_store_raw_intel
: {
4184 if (stage
== MESA_SHADER_FRAGMENT
)
4185 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4187 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4188 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4189 get_nir_image_intrinsic_image(bld
, instr
);
4190 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4191 srcs
[SURFACE_LOGICAL_SRC_DATA
] = get_nir_src(instr
->src
[2]);
4192 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4193 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4195 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4196 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4200 case nir_intrinsic_group_memory_barrier
:
4201 case nir_intrinsic_memory_barrier_shared
:
4202 case nir_intrinsic_memory_barrier_atomic_counter
:
4203 case nir_intrinsic_memory_barrier_buffer
:
4204 case nir_intrinsic_memory_barrier_image
:
4205 case nir_intrinsic_memory_barrier
: {
4206 bool l3_fence
, slm_fence
;
4207 if (devinfo
->gen
>= 11) {
4208 l3_fence
= instr
->intrinsic
!= nir_intrinsic_memory_barrier_shared
;
4209 slm_fence
= instr
->intrinsic
== nir_intrinsic_group_memory_barrier
||
4210 instr
->intrinsic
== nir_intrinsic_memory_barrier
||
4211 instr
->intrinsic
== nir_intrinsic_memory_barrier_shared
;
4213 /* Prior to gen11, we only have one kind of fence. */
4218 /* Be conservative in Gen11+ and always stall in a fence. Since there
4219 * are two different fences, and shader might want to synchronize
4222 * TODO: Improve NIR so that scope and visibility information for the
4223 * barriers is available here to make a better decision.
4225 * TODO: When emitting more than one fence, it might help emit all
4226 * the fences first and then generate the stall moves.
4228 const bool stall
= devinfo
->gen
>= 11;
4230 const fs_builder ubld
= bld
.group(8, 0);
4231 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4234 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4235 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4236 /* bti */ brw_imm_ud(0))
4237 ->size_written
= 2 * REG_SIZE
;
4241 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
4242 brw_vec8_grf(0, 0), brw_imm_ud(stall
),
4243 brw_imm_ud(GEN7_BTI_SLM
))
4244 ->size_written
= 2 * REG_SIZE
;
4250 case nir_intrinsic_shader_clock
: {
4251 /* We cannot do anything if there is an event, so ignore it for now */
4252 const fs_reg shader_clock
= get_timestamp(bld
);
4253 const fs_reg srcs
[] = { component(shader_clock
, 0),
4254 component(shader_clock
, 1) };
4255 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
4259 case nir_intrinsic_image_samples
:
4260 /* The driver does not support multi-sampled images. */
4261 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
4264 case nir_intrinsic_load_uniform
: {
4265 /* Offsets are in bytes but they should always aligned to
4268 assert(instr
->const_index
[0] % 4 == 0 ||
4269 instr
->const_index
[0] % type_sz(dest
.type
) == 0);
4271 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
4273 if (nir_src_is_const(instr
->src
[0])) {
4274 unsigned load_offset
= nir_src_as_uint(instr
->src
[0]);
4275 assert(load_offset
% type_sz(dest
.type
) == 0);
4276 /* For 16-bit types we add the module of the const_index[0]
4277 * offset to access to not 32-bit aligned element
4279 src
.offset
= load_offset
+ instr
->const_index
[0] % 4;
4281 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4282 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4285 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4286 BRW_REGISTER_TYPE_UD
);
4288 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4289 * go past the end of the uniform. In order to keep the n'th
4290 * component from running past, we subtract off the size of all but
4291 * one component of the vector.
4293 assert(instr
->const_index
[1] >=
4294 instr
->num_components
* (int) type_sz(dest
.type
));
4295 unsigned read_size
= instr
->const_index
[1] -
4296 (instr
->num_components
- 1) * type_sz(dest
.type
);
4298 bool supports_64bit_indirects
=
4299 !devinfo
->is_cherryview
&& !gen_device_info_is_9lp(devinfo
);
4301 if (type_sz(dest
.type
) != 8 || supports_64bit_indirects
) {
4302 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4303 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4304 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4305 indirect
, brw_imm_ud(read_size
));
4308 const unsigned num_mov_indirects
=
4309 type_sz(dest
.type
) / type_sz(BRW_REGISTER_TYPE_UD
);
4310 /* We read a little bit less per MOV INDIRECT, as they are now
4311 * 32-bits ones instead of 64-bit. Fix read_size then.
4313 const unsigned read_size_32bit
= read_size
-
4314 (num_mov_indirects
- 1) * type_sz(BRW_REGISTER_TYPE_UD
);
4315 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4316 for (unsigned i
= 0; i
< num_mov_indirects
; i
++) {
4317 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4318 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4319 subscript(offset(src
, bld
, j
), BRW_REGISTER_TYPE_UD
, i
),
4320 indirect
, brw_imm_ud(read_size_32bit
));
4328 case nir_intrinsic_load_ubo
: {
4330 if (nir_src_is_const(instr
->src
[0])) {
4331 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4332 nir_src_as_uint(instr
->src
[0]);
4333 surf_index
= brw_imm_ud(index
);
4335 /* The block index is not a constant. Evaluate the index expression
4336 * per-channel and add the base UBO index; we have to select a value
4337 * from any live channel.
4339 surf_index
= vgrf(glsl_type::uint_type
);
4340 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4341 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4342 surf_index
= bld
.emit_uniformize(surf_index
);
4345 if (!nir_src_is_const(instr
->src
[1])) {
4346 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4347 BRW_REGISTER_TYPE_UD
);
4349 for (int i
= 0; i
< instr
->num_components
; i
++)
4350 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4351 base_offset
, i
* type_sz(dest
.type
));
4353 /* Even if we are loading doubles, a pull constant load will load
4354 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4355 * need to load a full dvec4 we will have to emit 2 loads. This is
4356 * similar to demote_pull_constants(), except that in that case we
4357 * see individual accesses to each component of the vector and then
4358 * we let CSE deal with duplicate loads. Here we see a vector access
4359 * and we have to split it if necessary.
4361 const unsigned type_size
= type_sz(dest
.type
);
4362 const unsigned load_offset
= nir_src_as_uint(instr
->src
[1]);
4364 /* See if we've selected this as a push constant candidate */
4365 if (nir_src_is_const(instr
->src
[0])) {
4366 const unsigned ubo_block
= nir_src_as_uint(instr
->src
[0]);
4367 const unsigned offset_256b
= load_offset
/ 32;
4370 for (int i
= 0; i
< 4; i
++) {
4371 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
4372 if (range
->block
== ubo_block
&&
4373 offset_256b
>= range
->start
&&
4374 offset_256b
< range
->start
+ range
->length
) {
4376 push_reg
= fs_reg(UNIFORM
, UBO_START
+ i
, dest
.type
);
4377 push_reg
.offset
= load_offset
- 32 * range
->start
;
4382 if (push_reg
.file
!= BAD_FILE
) {
4383 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
4384 bld
.MOV(offset(dest
, bld
, i
),
4385 byte_offset(push_reg
, i
* type_size
));
4391 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
4392 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
4393 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4395 for (unsigned c
= 0; c
< instr
->num_components
;) {
4396 const unsigned base
= load_offset
+ c
* type_size
;
4397 /* Number of usable components in the next block-aligned load. */
4398 const unsigned count
= MIN2(instr
->num_components
- c
,
4399 (block_sz
- base
% block_sz
) / type_size
);
4401 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4402 packed_consts
, surf_index
,
4403 brw_imm_ud(base
& ~(block_sz
- 1)));
4405 const fs_reg consts
=
4406 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
4409 for (unsigned d
= 0; d
< count
; d
++)
4410 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4418 case nir_intrinsic_load_global
: {
4419 assert(devinfo
->gen
>= 8);
4421 if (nir_intrinsic_align(instr
) >= 4) {
4422 assert(nir_dest_bit_size(instr
->dest
) == 32);
4423 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL
,
4425 get_nir_src(instr
->src
[0]), /* Address */
4426 fs_reg(), /* No source data */
4427 brw_imm_ud(instr
->num_components
));
4428 inst
->size_written
= instr
->num_components
*
4429 inst
->dst
.component_size(inst
->exec_size
);
4431 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4432 assert(bit_size
<= 32);
4433 assert(nir_dest_num_components(instr
->dest
) == 1);
4434 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4435 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL
,
4437 get_nir_src(instr
->src
[0]), /* Address */
4438 fs_reg(), /* No source data */
4439 brw_imm_ud(bit_size
));
4440 bld
.MOV(dest
, subscript(tmp
, dest
.type
, 0));
4445 case nir_intrinsic_store_global
:
4446 assert(devinfo
->gen
>= 8);
4448 if (stage
== MESA_SHADER_FRAGMENT
)
4449 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4451 if (nir_intrinsic_align(instr
) >= 4) {
4452 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4453 bld
.emit(SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL
,
4455 get_nir_src(instr
->src
[1]), /* Address */
4456 get_nir_src(instr
->src
[0]), /* Data */
4457 brw_imm_ud(instr
->num_components
));
4459 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4460 assert(bit_size
<= 32);
4461 assert(nir_src_num_components(instr
->src
[0]) == 1);
4462 brw_reg_type data_type
=
4463 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4464 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4465 bld
.MOV(tmp
, retype(get_nir_src(instr
->src
[0]), data_type
));
4466 bld
.emit(SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL
,
4468 get_nir_src(instr
->src
[1]), /* Address */
4470 brw_imm_ud(nir_src_bit_size(instr
->src
[0])));
4474 case nir_intrinsic_global_atomic_add
:
4475 nir_emit_global_atomic(bld
, get_op_for_atomic_add(instr
, 1), instr
);
4477 case nir_intrinsic_global_atomic_imin
:
4478 nir_emit_global_atomic(bld
, BRW_AOP_IMIN
, instr
);
4480 case nir_intrinsic_global_atomic_umin
:
4481 nir_emit_global_atomic(bld
, BRW_AOP_UMIN
, instr
);
4483 case nir_intrinsic_global_atomic_imax
:
4484 nir_emit_global_atomic(bld
, BRW_AOP_IMAX
, instr
);
4486 case nir_intrinsic_global_atomic_umax
:
4487 nir_emit_global_atomic(bld
, BRW_AOP_UMAX
, instr
);
4489 case nir_intrinsic_global_atomic_and
:
4490 nir_emit_global_atomic(bld
, BRW_AOP_AND
, instr
);
4492 case nir_intrinsic_global_atomic_or
:
4493 nir_emit_global_atomic(bld
, BRW_AOP_OR
, instr
);
4495 case nir_intrinsic_global_atomic_xor
:
4496 nir_emit_global_atomic(bld
, BRW_AOP_XOR
, instr
);
4498 case nir_intrinsic_global_atomic_exchange
:
4499 nir_emit_global_atomic(bld
, BRW_AOP_MOV
, instr
);
4501 case nir_intrinsic_global_atomic_comp_swap
:
4502 nir_emit_global_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4504 case nir_intrinsic_global_atomic_fmin
:
4505 nir_emit_global_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4507 case nir_intrinsic_global_atomic_fmax
:
4508 nir_emit_global_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4510 case nir_intrinsic_global_atomic_fcomp_swap
:
4511 nir_emit_global_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4514 case nir_intrinsic_load_ssbo
: {
4515 assert(devinfo
->gen
>= 7);
4517 const unsigned bit_size
= nir_dest_bit_size(instr
->dest
);
4518 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4519 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4520 get_nir_ssbo_intrinsic_index(bld
, instr
);
4521 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
4522 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4524 /* Make dest unsigned because that's what the temporary will be */
4525 dest
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4527 /* Read the vector */
4528 if (nir_intrinsic_align(instr
) >= 4) {
4529 assert(nir_dest_bit_size(instr
->dest
) == 32);
4530 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4532 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
4533 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4534 inst
->size_written
= instr
->num_components
* dispatch_width
* 4;
4536 assert(nir_dest_bit_size(instr
->dest
) <= 32);
4537 assert(nir_dest_num_components(instr
->dest
) == 1);
4538 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4540 fs_reg read_result
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4541 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL
,
4542 read_result
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4543 bld
.MOV(dest
, subscript(read_result
, dest
.type
, 0));
4548 case nir_intrinsic_store_ssbo
: {
4549 assert(devinfo
->gen
>= 7);
4551 if (stage
== MESA_SHADER_FRAGMENT
)
4552 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4554 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4555 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
4556 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] =
4557 get_nir_ssbo_intrinsic_index(bld
, instr
);
4558 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[2]);
4559 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
4561 fs_reg data
= get_nir_src(instr
->src
[0]);
4562 data
.type
= brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_UD
);
4564 assert(nir_intrinsic_write_mask(instr
) ==
4565 (1u << instr
->num_components
) - 1);
4566 if (nir_intrinsic_align(instr
) >= 4) {
4567 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4568 assert(nir_src_num_components(instr
->src
[0]) <= 4);
4569 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
4570 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(instr
->num_components
);
4571 bld
.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
4572 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4574 assert(nir_src_bit_size(instr
->src
[0]) <= 32);
4575 assert(nir_src_num_components(instr
->src
[0]) == 1);
4576 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(bit_size
);
4578 srcs
[SURFACE_LOGICAL_SRC_DATA
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4579 bld
.MOV(srcs
[SURFACE_LOGICAL_SRC_DATA
], data
);
4581 bld
.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL
,
4582 fs_reg(), srcs
, SURFACE_LOGICAL_NUM_SRCS
);
4587 case nir_intrinsic_store_output
: {
4588 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4589 fs_reg src
= get_nir_src(instr
->src
[0]);
4591 unsigned store_offset
= nir_src_as_uint(instr
->src
[1]);
4592 unsigned num_components
= instr
->num_components
;
4593 unsigned first_component
= nir_intrinsic_component(instr
);
4595 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4596 4 * store_offset
), src
.type
);
4597 for (unsigned j
= 0; j
< num_components
; j
++) {
4598 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4599 offset(src
, bld
, j
));
4604 case nir_intrinsic_ssbo_atomic_add
:
4605 nir_emit_ssbo_atomic(bld
, get_op_for_atomic_add(instr
, 2), instr
);
4607 case nir_intrinsic_ssbo_atomic_imin
:
4608 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4610 case nir_intrinsic_ssbo_atomic_umin
:
4611 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4613 case nir_intrinsic_ssbo_atomic_imax
:
4614 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4616 case nir_intrinsic_ssbo_atomic_umax
:
4617 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4619 case nir_intrinsic_ssbo_atomic_and
:
4620 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4622 case nir_intrinsic_ssbo_atomic_or
:
4623 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4625 case nir_intrinsic_ssbo_atomic_xor
:
4626 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4628 case nir_intrinsic_ssbo_atomic_exchange
:
4629 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4631 case nir_intrinsic_ssbo_atomic_comp_swap
:
4632 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4634 case nir_intrinsic_ssbo_atomic_fmin
:
4635 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMIN
, instr
);
4637 case nir_intrinsic_ssbo_atomic_fmax
:
4638 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FMAX
, instr
);
4640 case nir_intrinsic_ssbo_atomic_fcomp_swap
:
4641 nir_emit_ssbo_atomic_float(bld
, BRW_AOP_FCMPWR
, instr
);
4644 case nir_intrinsic_get_buffer_size
: {
4645 assert(nir_src_num_components(instr
->src
[0]) == 1);
4646 unsigned ssbo_index
= nir_src_is_const(instr
->src
[0]) ?
4647 nir_src_as_uint(instr
->src
[0]) : 0;
4649 /* A resinfo's sampler message is used to get the buffer size. The
4650 * SIMD8's writeback message consists of four registers and SIMD16's
4651 * writeback message consists of 8 destination registers (two per each
4652 * component). Because we are only interested on the first channel of
4653 * the first returned component, where resinfo returns the buffer size
4654 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4655 * the dispatch width.
4657 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4658 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4659 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4662 ubld
.MOV(src_payload
, brw_imm_d(0));
4664 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4665 fs_inst
*inst
= ubld
.emit(SHADER_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4666 src_payload
, brw_imm_ud(index
));
4667 inst
->header_size
= 0;
4669 inst
->size_written
= 4 * REG_SIZE
;
4671 /* SKL PRM, vol07, 3D Media GPGPU Engine, Bounds Checking and Faulting:
4673 * "Out-of-bounds checking is always performed at a DWord granularity. If
4674 * any part of the DWord is out-of-bounds then the whole DWord is
4675 * considered out-of-bounds."
4677 * This implies that types with size smaller than 4-bytes need to be
4678 * padded if they don't complete the last dword of the buffer. But as we
4679 * need to maintain the original size we need to reverse the padding
4680 * calculation to return the correct size to know the number of elements
4681 * of an unsized array. As we stored in the last two bits of the surface
4682 * size the needed padding for the buffer, we calculate here the
4683 * original buffer_size reversing the surface_size calculation:
4685 * surface_size = isl_align(buffer_size, 4) +
4686 * (isl_align(buffer_size) - buffer_size)
4688 * buffer_size = surface_size & ~3 - surface_size & 3
4691 fs_reg size_aligned4
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4692 fs_reg size_padding
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4693 fs_reg buffer_size
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4695 ubld
.AND(size_padding
, ret_payload
, brw_imm_ud(3));
4696 ubld
.AND(size_aligned4
, ret_payload
, brw_imm_ud(~3));
4697 ubld
.ADD(buffer_size
, size_aligned4
, negate(size_padding
));
4699 bld
.MOV(retype(dest
, ret_payload
.type
), component(buffer_size
, 0));
4703 case nir_intrinsic_load_subgroup_size
:
4704 /* This should only happen for fragment shaders because every other case
4705 * is lowered in NIR so we can optimize on it.
4707 assert(stage
== MESA_SHADER_FRAGMENT
);
4708 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(dispatch_width
));
4711 case nir_intrinsic_load_subgroup_invocation
:
4712 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
4713 nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
]);
4716 case nir_intrinsic_load_subgroup_eq_mask
:
4717 case nir_intrinsic_load_subgroup_ge_mask
:
4718 case nir_intrinsic_load_subgroup_gt_mask
:
4719 case nir_intrinsic_load_subgroup_le_mask
:
4720 case nir_intrinsic_load_subgroup_lt_mask
:
4721 unreachable("not reached");
4723 case nir_intrinsic_vote_any
: {
4724 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4726 /* The any/all predicates do not consider channel enables. To prevent
4727 * dead channels from affecting the result, we initialize the flag with
4728 * with the identity value for the logical operation.
4730 if (dispatch_width
== 32) {
4731 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4732 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4735 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0));
4737 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4739 /* For some reason, the any/all predicates don't work properly with
4740 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4741 * doesn't read the correct subset of the flag register and you end up
4742 * getting garbage in the second half. Work around this by using a pair
4743 * of 1-wide MOVs and scattering the result.
4745 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4746 ubld
.MOV(res1
, brw_imm_d(0));
4747 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ANY8H
:
4748 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ANY16H
:
4749 BRW_PREDICATE_ALIGN1_ANY32H
,
4750 ubld
.MOV(res1
, brw_imm_d(-1)));
4752 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4755 case nir_intrinsic_vote_all
: {
4756 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4758 /* The any/all predicates do not consider channel enables. To prevent
4759 * dead channels from affecting the result, we initialize the flag with
4760 * with the identity value for the logical operation.
4762 if (dispatch_width
== 32) {
4763 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4764 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4765 brw_imm_ud(0xffffffff));
4767 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4769 bld
.CMP(bld
.null_reg_d(), get_nir_src(instr
->src
[0]), brw_imm_d(0), BRW_CONDITIONAL_NZ
);
4771 /* For some reason, the any/all predicates don't work properly with
4772 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4773 * doesn't read the correct subset of the flag register and you end up
4774 * getting garbage in the second half. Work around this by using a pair
4775 * of 1-wide MOVs and scattering the result.
4777 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4778 ubld
.MOV(res1
, brw_imm_d(0));
4779 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4780 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4781 BRW_PREDICATE_ALIGN1_ALL32H
,
4782 ubld
.MOV(res1
, brw_imm_d(-1)));
4784 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4787 case nir_intrinsic_vote_feq
:
4788 case nir_intrinsic_vote_ieq
: {
4789 fs_reg value
= get_nir_src(instr
->src
[0]);
4790 if (instr
->intrinsic
== nir_intrinsic_vote_feq
) {
4791 const unsigned bit_size
= nir_src_bit_size(instr
->src
[0]);
4792 value
.type
= bit_size
== 8 ? BRW_REGISTER_TYPE_B
:
4793 brw_reg_type_from_bit_size(bit_size
, BRW_REGISTER_TYPE_F
);
4796 fs_reg uniformized
= bld
.emit_uniformize(value
);
4797 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4799 /* The any/all predicates do not consider channel enables. To prevent
4800 * dead channels from affecting the result, we initialize the flag with
4801 * with the identity value for the logical operation.
4803 if (dispatch_width
== 32) {
4804 /* For SIMD32, we use a UD type so we fill both f0.0 and f0.1. */
4805 ubld
.MOV(retype(brw_flag_reg(0, 0), BRW_REGISTER_TYPE_UD
),
4806 brw_imm_ud(0xffffffff));
4808 ubld
.MOV(brw_flag_reg(0, 0), brw_imm_uw(0xffff));
4810 bld
.CMP(bld
.null_reg_d(), value
, uniformized
, BRW_CONDITIONAL_Z
);
4812 /* For some reason, the any/all predicates don't work properly with
4813 * SIMD32. In particular, it appears that a SEL with a QtrCtrl of 2H
4814 * doesn't read the correct subset of the flag register and you end up
4815 * getting garbage in the second half. Work around this by using a pair
4816 * of 1-wide MOVs and scattering the result.
4818 fs_reg res1
= ubld
.vgrf(BRW_REGISTER_TYPE_D
);
4819 ubld
.MOV(res1
, brw_imm_d(0));
4820 set_predicate(dispatch_width
== 8 ? BRW_PREDICATE_ALIGN1_ALL8H
:
4821 dispatch_width
== 16 ? BRW_PREDICATE_ALIGN1_ALL16H
:
4822 BRW_PREDICATE_ALIGN1_ALL32H
,
4823 ubld
.MOV(res1
, brw_imm_d(-1)));
4825 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), component(res1
, 0));
4829 case nir_intrinsic_ballot
: {
4830 const fs_reg value
= retype(get_nir_src(instr
->src
[0]),
4831 BRW_REGISTER_TYPE_UD
);
4832 struct brw_reg flag
= brw_flag_reg(0, 0);
4833 /* FIXME: For SIMD32 programs, this causes us to stomp on f0.1 as well
4834 * as f0.0. This is a problem for fragment programs as we currently use
4835 * f0.1 for discards. Fortunately, we don't support SIMD32 fragment
4836 * programs yet so this isn't a problem. When we do, something will
4839 if (dispatch_width
== 32)
4840 flag
.type
= BRW_REGISTER_TYPE_UD
;
4842 bld
.exec_all().group(1, 0).MOV(flag
, brw_imm_ud(0u));
4843 bld
.CMP(bld
.null_reg_ud(), value
, brw_imm_ud(0u), BRW_CONDITIONAL_NZ
);
4845 if (instr
->dest
.ssa
.bit_size
> 32) {
4846 dest
.type
= BRW_REGISTER_TYPE_UQ
;
4848 dest
.type
= BRW_REGISTER_TYPE_UD
;
4850 bld
.MOV(dest
, flag
);
4854 case nir_intrinsic_read_invocation
: {
4855 const fs_reg value
= get_nir_src(instr
->src
[0]);
4856 const fs_reg invocation
= get_nir_src(instr
->src
[1]);
4857 fs_reg tmp
= bld
.vgrf(value
.type
);
4859 bld
.exec_all().emit(SHADER_OPCODE_BROADCAST
, tmp
, value
,
4860 bld
.emit_uniformize(invocation
));
4862 bld
.MOV(retype(dest
, value
.type
), fs_reg(component(tmp
, 0)));
4866 case nir_intrinsic_read_first_invocation
: {
4867 const fs_reg value
= get_nir_src(instr
->src
[0]);
4868 bld
.MOV(retype(dest
, value
.type
), bld
.emit_uniformize(value
));
4872 case nir_intrinsic_shuffle
: {
4873 const fs_reg value
= get_nir_src(instr
->src
[0]);
4874 const fs_reg index
= get_nir_src(instr
->src
[1]);
4876 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, index
);
4880 case nir_intrinsic_first_invocation
: {
4881 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4882 bld
.exec_all().emit(SHADER_OPCODE_FIND_LIVE_CHANNEL
, tmp
);
4883 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
4884 fs_reg(component(tmp
, 0)));
4888 case nir_intrinsic_quad_broadcast
: {
4889 const fs_reg value
= get_nir_src(instr
->src
[0]);
4890 const unsigned index
= nir_src_as_uint(instr
->src
[1]);
4892 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, retype(dest
, value
.type
),
4893 value
, brw_imm_ud(index
), brw_imm_ud(4));
4897 case nir_intrinsic_quad_swap_horizontal
: {
4898 const fs_reg value
= get_nir_src(instr
->src
[0]);
4899 const fs_reg tmp
= bld
.vgrf(value
.type
);
4900 if (devinfo
->gen
<= 7) {
4901 /* The hardware doesn't seem to support these crazy regions with
4902 * compressed instructions on gen7 and earlier so we fall back to
4903 * using quad swizzles. Fortunately, we don't support 64-bit
4904 * anything in Vulkan on gen7.
4906 assert(nir_src_bit_size(instr
->src
[0]) == 32);
4907 const fs_builder ubld
= bld
.exec_all();
4908 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4909 brw_imm_ud(BRW_SWIZZLE4(1,0,3,2)));
4910 bld
.MOV(retype(dest
, value
.type
), tmp
);
4912 const fs_builder ubld
= bld
.exec_all().group(dispatch_width
/ 2, 0);
4914 const fs_reg src_left
= horiz_stride(value
, 2);
4915 const fs_reg src_right
= horiz_stride(horiz_offset(value
, 1), 2);
4916 const fs_reg tmp_left
= horiz_stride(tmp
, 2);
4917 const fs_reg tmp_right
= horiz_stride(horiz_offset(tmp
, 1), 2);
4919 ubld
.MOV(tmp_left
, src_right
);
4920 ubld
.MOV(tmp_right
, src_left
);
4923 bld
.MOV(retype(dest
, value
.type
), tmp
);
4927 case nir_intrinsic_quad_swap_vertical
: {
4928 const fs_reg value
= get_nir_src(instr
->src
[0]);
4929 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4930 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4931 const fs_reg tmp
= bld
.vgrf(value
.type
);
4932 const fs_builder ubld
= bld
.exec_all();
4933 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4934 brw_imm_ud(BRW_SWIZZLE4(2,3,0,1)));
4935 bld
.MOV(retype(dest
, value
.type
), tmp
);
4937 /* For larger data types, we have to either emit dispatch_width many
4938 * MOVs or else fall back to doing indirects.
4940 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4941 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4943 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4948 case nir_intrinsic_quad_swap_diagonal
: {
4949 const fs_reg value
= get_nir_src(instr
->src
[0]);
4950 if (nir_src_bit_size(instr
->src
[0]) == 32) {
4951 /* For 32-bit, we can use a SIMD4x2 instruction to do this easily */
4952 const fs_reg tmp
= bld
.vgrf(value
.type
);
4953 const fs_builder ubld
= bld
.exec_all();
4954 ubld
.emit(SHADER_OPCODE_QUAD_SWIZZLE
, tmp
, value
,
4955 brw_imm_ud(BRW_SWIZZLE4(3,2,1,0)));
4956 bld
.MOV(retype(dest
, value
.type
), tmp
);
4958 /* For larger data types, we have to either emit dispatch_width many
4959 * MOVs or else fall back to doing indirects.
4961 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
4962 bld
.XOR(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
4964 bld
.emit(SHADER_OPCODE_SHUFFLE
, retype(dest
, value
.type
), value
, idx
);
4969 case nir_intrinsic_reduce
: {
4970 fs_reg src
= get_nir_src(instr
->src
[0]);
4971 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
4972 unsigned cluster_size
= nir_intrinsic_cluster_size(instr
);
4973 if (cluster_size
== 0 || cluster_size
> dispatch_width
)
4974 cluster_size
= dispatch_width
;
4976 /* Figure out the source type */
4977 src
.type
= brw_type_for_nir_type(devinfo
,
4978 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
4979 nir_src_bit_size(instr
->src
[0])));
4981 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
4982 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
4983 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
4985 /* Set up a register for all of our scratching around and initialize it
4986 * to reduction operation's identity value.
4988 fs_reg scan
= bld
.vgrf(src
.type
);
4989 bld
.exec_all().emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
4991 bld
.emit_scan(brw_op
, scan
, cluster_size
, cond_mod
);
4993 dest
.type
= src
.type
;
4994 if (cluster_size
* type_sz(src
.type
) >= REG_SIZE
* 2) {
4995 /* In this case, CLUSTER_BROADCAST instruction isn't needed because
4996 * the distance between clusters is at least 2 GRFs. In this case,
4997 * we don't need the weird striding of the CLUSTER_BROADCAST
4998 * instruction and can just do regular MOVs.
5000 assert((cluster_size
* type_sz(src
.type
)) % (REG_SIZE
* 2) == 0);
5001 const unsigned groups
=
5002 (dispatch_width
* type_sz(src
.type
)) / (REG_SIZE
* 2);
5003 const unsigned group_size
= dispatch_width
/ groups
;
5004 for (unsigned i
= 0; i
< groups
; i
++) {
5005 const unsigned cluster
= (i
* group_size
) / cluster_size
;
5006 const unsigned comp
= cluster
* cluster_size
+ (cluster_size
- 1);
5007 bld
.group(group_size
, i
).MOV(horiz_offset(dest
, i
* group_size
),
5008 component(scan
, comp
));
5011 bld
.emit(SHADER_OPCODE_CLUSTER_BROADCAST
, dest
, scan
,
5012 brw_imm_ud(cluster_size
- 1), brw_imm_ud(cluster_size
));
5017 case nir_intrinsic_inclusive_scan
:
5018 case nir_intrinsic_exclusive_scan
: {
5019 fs_reg src
= get_nir_src(instr
->src
[0]);
5020 nir_op redop
= (nir_op
)nir_intrinsic_reduction_op(instr
);
5022 /* Figure out the source type */
5023 src
.type
= brw_type_for_nir_type(devinfo
,
5024 (nir_alu_type
)(nir_op_infos
[redop
].input_types
[0] |
5025 nir_src_bit_size(instr
->src
[0])));
5027 fs_reg identity
= brw_nir_reduction_op_identity(bld
, redop
, src
.type
);
5028 opcode brw_op
= brw_op_for_nir_reduction_op(redop
);
5029 brw_conditional_mod cond_mod
= brw_cond_mod_for_nir_reduction_op(redop
);
5031 /* Set up a register for all of our scratching around and initialize it
5032 * to reduction operation's identity value.
5034 fs_reg scan
= bld
.vgrf(src
.type
);
5035 const fs_builder allbld
= bld
.exec_all();
5036 allbld
.emit(SHADER_OPCODE_SEL_EXEC
, scan
, src
, identity
);
5038 if (instr
->intrinsic
== nir_intrinsic_exclusive_scan
) {
5039 /* Exclusive scan is a bit harder because we have to do an annoying
5040 * shift of the contents before we can begin. To make things worse,
5041 * we can't do this with a normal stride; we have to use indirects.
5043 fs_reg shifted
= bld
.vgrf(src
.type
);
5044 fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_W
);
5045 allbld
.ADD(idx
, nir_system_values
[SYSTEM_VALUE_SUBGROUP_INVOCATION
],
5047 allbld
.emit(SHADER_OPCODE_SHUFFLE
, shifted
, scan
, idx
);
5048 allbld
.group(1, 0).MOV(component(shifted
, 0), identity
);
5052 bld
.emit_scan(brw_op
, scan
, dispatch_width
, cond_mod
);
5054 bld
.MOV(retype(dest
, src
.type
), scan
);
5058 case nir_intrinsic_begin_invocation_interlock
: {
5059 const fs_builder ubld
= bld
.group(8, 0);
5060 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5062 ubld
.emit(SHADER_OPCODE_INTERLOCK
, tmp
, brw_vec8_grf(0, 0))
5063 ->size_written
= 2 * REG_SIZE
;
5067 case nir_intrinsic_end_invocation_interlock
: {
5068 /* For endInvocationInterlock(), we need to insert a memory fence which
5069 * stalls in the shader until the memory transactions prior to that
5070 * fence are complete. This ensures that the shader does not end before
5071 * any writes from its critical section have landed. Otherwise, you can
5072 * end up with a case where the next invocation on that pixel properly
5073 * stalls for previous FS invocation on its pixel to complete but
5074 * doesn't actually wait for the dataport memory transactions from that
5075 * thread to land before submitting its own.
5077 const fs_builder ubld
= bld
.group(8, 0);
5078 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5079 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
,
5080 brw_vec8_grf(0, 0), brw_imm_ud(1), brw_imm_ud(0))
5081 ->size_written
= 2 * REG_SIZE
;
5086 unreachable("unknown intrinsic");
5091 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
5092 int op
, nir_intrinsic_instr
*instr
)
5094 if (stage
== MESA_SHADER_FRAGMENT
)
5095 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5097 /* The BTI untyped atomic messages only support 32-bit atomics. If you
5098 * just look at the big table of messages in the Vol 7 of the SKL PRM, they
5099 * appear to exist. However, if you look at Vol 2a, there are no message
5100 * descriptors provided for Qword atomic ops except for A64 messages.
5102 assert(nir_dest_bit_size(instr
->dest
) == 32);
5105 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5106 dest
= get_nir_dest(instr
->dest
);
5108 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5109 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5110 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5111 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5112 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5115 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5116 data
= get_nir_src(instr
->src
[2]);
5118 if (op
== BRW_AOP_CMPWR
) {
5119 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5120 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5121 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5124 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5126 /* Emit the actual atomic operation */
5128 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5129 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5133 fs_visitor::nir_emit_ssbo_atomic_float(const fs_builder
&bld
,
5134 int op
, nir_intrinsic_instr
*instr
)
5136 if (stage
== MESA_SHADER_FRAGMENT
)
5137 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5140 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5141 dest
= get_nir_dest(instr
->dest
);
5143 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5144 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = get_nir_ssbo_intrinsic_index(bld
, instr
);
5145 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = get_nir_src(instr
->src
[1]);
5146 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5147 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5149 fs_reg data
= get_nir_src(instr
->src
[2]);
5150 if (op
== BRW_AOP_FCMPWR
) {
5151 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5152 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[3]) };
5153 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5156 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5158 /* Emit the actual atomic operation */
5160 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5161 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5165 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
5166 int op
, nir_intrinsic_instr
*instr
)
5169 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5170 dest
= get_nir_dest(instr
->dest
);
5172 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5173 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5174 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5175 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5178 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5179 data
= get_nir_src(instr
->src
[1]);
5180 if (op
== BRW_AOP_CMPWR
) {
5181 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5182 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5183 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5186 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5188 /* Get the offset */
5189 if (nir_src_is_const(instr
->src
[0])) {
5190 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5191 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5193 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5194 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5195 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5196 brw_imm_ud(instr
->const_index
[0]));
5199 /* Emit the actual atomic operation operation */
5201 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
5202 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5206 fs_visitor::nir_emit_shared_atomic_float(const fs_builder
&bld
,
5207 int op
, nir_intrinsic_instr
*instr
)
5210 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5211 dest
= get_nir_dest(instr
->dest
);
5213 fs_reg srcs
[SURFACE_LOGICAL_NUM_SRCS
];
5214 srcs
[SURFACE_LOGICAL_SRC_SURFACE
] = brw_imm_ud(GEN7_BTI_SLM
);
5215 srcs
[SURFACE_LOGICAL_SRC_IMM_DIMS
] = brw_imm_ud(1);
5216 srcs
[SURFACE_LOGICAL_SRC_IMM_ARG
] = brw_imm_ud(op
);
5218 fs_reg data
= get_nir_src(instr
->src
[1]);
5219 if (op
== BRW_AOP_FCMPWR
) {
5220 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5221 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5222 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5225 srcs
[SURFACE_LOGICAL_SRC_DATA
] = data
;
5227 /* Get the offset */
5228 if (nir_src_is_const(instr
->src
[0])) {
5229 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] =
5230 brw_imm_ud(instr
->const_index
[0] + nir_src_as_uint(instr
->src
[0]));
5232 srcs
[SURFACE_LOGICAL_SRC_ADDRESS
] = vgrf(glsl_type::uint_type
);
5233 bld
.ADD(srcs
[SURFACE_LOGICAL_SRC_ADDRESS
],
5234 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
5235 brw_imm_ud(instr
->const_index
[0]));
5238 /* Emit the actual atomic operation operation */
5240 bld
.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL
,
5241 dest
, srcs
, SURFACE_LOGICAL_NUM_SRCS
);
5245 fs_visitor::nir_emit_global_atomic(const fs_builder
&bld
,
5246 int op
, nir_intrinsic_instr
*instr
)
5248 if (stage
== MESA_SHADER_FRAGMENT
)
5249 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5252 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
5253 dest
= get_nir_dest(instr
->dest
);
5255 fs_reg addr
= get_nir_src(instr
->src
[0]);
5258 if (op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
)
5259 data
= get_nir_src(instr
->src
[1]);
5261 if (op
== BRW_AOP_CMPWR
) {
5262 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5263 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5264 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5268 if (nir_dest_bit_size(instr
->dest
) == 64) {
5269 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_INT64_LOGICAL
,
5270 dest
, addr
, data
, brw_imm_ud(op
));
5272 assert(nir_dest_bit_size(instr
->dest
) == 32);
5273 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5274 dest
, addr
, data
, brw_imm_ud(op
));
5279 fs_visitor::nir_emit_global_atomic_float(const fs_builder
&bld
,
5280 int op
, nir_intrinsic_instr
*instr
)
5282 if (stage
== MESA_SHADER_FRAGMENT
)
5283 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
5285 assert(nir_intrinsic_infos
[instr
->intrinsic
].has_dest
);
5286 fs_reg dest
= get_nir_dest(instr
->dest
);
5288 fs_reg addr
= get_nir_src(instr
->src
[0]);
5290 assert(op
!= BRW_AOP_INC
&& op
!= BRW_AOP_DEC
&& op
!= BRW_AOP_PREDEC
);
5291 fs_reg data
= get_nir_src(instr
->src
[1]);
5293 if (op
== BRW_AOP_FCMPWR
) {
5294 fs_reg tmp
= bld
.vgrf(data
.type
, 2);
5295 fs_reg sources
[2] = { data
, get_nir_src(instr
->src
[2]) };
5296 bld
.LOAD_PAYLOAD(tmp
, sources
, 2, 0);
5300 bld
.emit(SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL
,
5301 dest
, addr
, data
, brw_imm_ud(op
));
5305 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
5307 unsigned texture
= instr
->texture_index
;
5308 unsigned sampler
= instr
->sampler_index
;
5310 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
5312 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
5313 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
5315 int lod_components
= 0;
5317 /* The hardware requires a LOD for buffer textures */
5318 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5319 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
5321 uint32_t header_bits
= 0;
5322 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
5323 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
5324 switch (instr
->src
[i
].src_type
) {
5325 case nir_tex_src_bias
:
5326 srcs
[TEX_LOGICAL_SRC_LOD
] =
5327 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5329 case nir_tex_src_comparator
:
5330 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
5332 case nir_tex_src_coord
:
5333 switch (instr
->op
) {
5335 case nir_texop_txf_ms
:
5336 case nir_texop_txf_ms_mcs
:
5337 case nir_texop_samples_identical
:
5338 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
5341 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
5345 case nir_tex_src_ddx
:
5346 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
5347 lod_components
= nir_tex_instr_src_size(instr
, i
);
5349 case nir_tex_src_ddy
:
5350 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
5352 case nir_tex_src_lod
:
5353 switch (instr
->op
) {
5355 srcs
[TEX_LOGICAL_SRC_LOD
] =
5356 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
5359 srcs
[TEX_LOGICAL_SRC_LOD
] =
5360 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
5363 srcs
[TEX_LOGICAL_SRC_LOD
] =
5364 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5368 case nir_tex_src_min_lod
:
5369 srcs
[TEX_LOGICAL_SRC_MIN_LOD
] =
5370 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
5372 case nir_tex_src_ms_index
:
5373 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
5376 case nir_tex_src_offset
: {
5377 uint32_t offset_bits
= 0;
5378 if (brw_texture_offset(instr
, i
, &offset_bits
)) {
5379 header_bits
|= offset_bits
;
5381 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
5382 retype(src
, BRW_REGISTER_TYPE_D
);
5387 case nir_tex_src_projector
:
5388 unreachable("should be lowered");
5390 case nir_tex_src_texture_offset
: {
5391 /* Emit code to evaluate the actual indexing expression */
5392 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5393 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
5394 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
5398 case nir_tex_src_sampler_offset
: {
5399 /* Emit code to evaluate the actual indexing expression */
5400 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5401 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
5402 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
5406 case nir_tex_src_texture_handle
:
5407 assert(nir_tex_instr_src_index(instr
, nir_tex_src_texture_offset
) == -1);
5408 srcs
[TEX_LOGICAL_SRC_SURFACE
] = fs_reg();
5409 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
] = bld
.emit_uniformize(src
);
5412 case nir_tex_src_sampler_handle
:
5413 assert(nir_tex_instr_src_index(instr
, nir_tex_src_sampler_offset
) == -1);
5414 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = fs_reg();
5415 srcs
[TEX_LOGICAL_SRC_SAMPLER_HANDLE
] = bld
.emit_uniformize(src
);
5418 case nir_tex_src_ms_mcs
:
5419 assert(instr
->op
== nir_texop_txf_ms
);
5420 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
5423 case nir_tex_src_plane
: {
5424 const uint32_t plane
= nir_src_as_uint(instr
->src
[i
].src
);
5425 const uint32_t texture_index
=
5426 instr
->texture_index
+
5427 stage_prog_data
->binding_table
.plane_start
[plane
] -
5428 stage_prog_data
->binding_table
.texture_start
;
5430 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
5435 unreachable("unknown texture source");
5439 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
5440 (instr
->op
== nir_texop_txf_ms
||
5441 instr
->op
== nir_texop_samples_identical
)) {
5442 if (devinfo
->gen
>= 7 &&
5443 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
5444 srcs
[TEX_LOGICAL_SRC_MCS
] =
5445 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
5446 instr
->coord_components
,
5447 srcs
[TEX_LOGICAL_SRC_SURFACE
],
5448 srcs
[TEX_LOGICAL_SRC_SURFACE_HANDLE
]);
5450 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
5454 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
5455 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
5458 switch (instr
->op
) {
5460 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
5463 opcode
= FS_OPCODE_TXB_LOGICAL
;
5466 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
5469 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
5472 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
5474 case nir_texop_txf_ms
:
5475 if ((key_tex
->msaa_16
& (1 << sampler
)))
5476 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
5478 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
5480 case nir_texop_txf_ms_mcs
:
5481 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
5483 case nir_texop_query_levels
:
5485 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
5488 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
5491 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
5492 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
5494 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
5496 case nir_texop_texture_samples
:
5497 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
5499 case nir_texop_samples_identical
: {
5500 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
5502 /* If mcs is an immediate value, it means there is no MCS. In that case
5503 * just return false.
5505 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
5506 bld
.MOV(dst
, brw_imm_ud(0u));
5507 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
5508 fs_reg tmp
= vgrf(glsl_type::uint_type
);
5509 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
5510 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
5511 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
5513 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
5514 BRW_CONDITIONAL_EQ
);
5519 unreachable("unknown texture opcode");
5522 if (instr
->op
== nir_texop_tg4
) {
5523 if (instr
->component
== 1 &&
5524 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
5525 /* gather4 sampler is broken for green channel on RG32F --
5526 * we must ask for blue instead.
5528 header_bits
|= 2 << 16;
5530 header_bits
|= instr
->component
<< 16;
5534 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(devinfo
, instr
->dest_type
), 4);
5535 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
5536 inst
->offset
= header_bits
;
5538 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
5539 if (devinfo
->gen
>= 9 &&
5540 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
5541 unsigned write_mask
= instr
->dest
.is_ssa
?
5542 nir_ssa_def_components_read(&instr
->dest
.ssa
):
5543 (1 << dest_size
) - 1;
5544 assert(write_mask
!= 0); /* dead code should have been eliminated */
5545 inst
->size_written
= util_last_bit(write_mask
) *
5546 inst
->dst
.component_size(inst
->exec_size
);
5548 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
5551 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
5552 inst
->shadow_compare
= true;
5554 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
5555 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
5558 for (unsigned i
= 0; i
< dest_size
; i
++)
5559 nir_dest
[i
] = offset(dst
, bld
, i
);
5561 if (instr
->op
== nir_texop_query_levels
) {
5562 /* # levels is in .w */
5563 nir_dest
[0] = offset(dst
, bld
, 3);
5564 } else if (instr
->op
== nir_texop_txs
&&
5565 dest_size
>= 3 && devinfo
->gen
< 7) {
5566 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
5567 fs_reg depth
= offset(dst
, bld
, 2);
5568 nir_dest
[2] = vgrf(glsl_type::int_type
);
5569 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
5572 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
5576 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
5578 switch (instr
->type
) {
5579 case nir_jump_break
:
5580 bld
.emit(BRW_OPCODE_BREAK
);
5582 case nir_jump_continue
:
5583 bld
.emit(BRW_OPCODE_CONTINUE
);
5585 case nir_jump_return
:
5587 unreachable("unknown jump");
5592 * This helper takes a source register and un/shuffles it into the destination
5595 * If source type size is smaller than destination type size the operation
5596 * needed is a component shuffle. The opposite case would be an unshuffle. If
5597 * source/destination type size is equal a shuffle is done that would be
5598 * equivalent to a simple MOV.
5600 * For example, if source is a 16-bit type and destination is 32-bit. A 3
5601 * components .xyz 16-bit vector on SIMD8 would be.
5603 * |x1|x2|x3|x4|x5|x6|x7|x8|y1|y2|y3|y4|y5|y6|y7|y8|
5604 * |z1|z2|z3|z4|z5|z6|z7|z8| | | | | | | | |
5606 * This helper will return the following 2 32-bit components with the 16-bit
5609 * |x1 y1|x2 y2|x3 y3|x4 y4|x5 y5|x6 y6|x7 y7|x8 y8|
5610 * |z1 |z2 |z3 |z4 |z5 |z6 |z7 |z8 |
5612 * For unshuffle, the example would be the opposite, a 64-bit type source
5613 * and a 32-bit destination. A 2 component .xy 64-bit vector on SIMD8
5616 * | x1l x1h | x2l x2h | x3l x3h | x4l x4h |
5617 * | x5l x5h | x6l x6h | x7l x7h | x8l x8h |
5618 * | y1l y1h | y2l y2h | y3l y3h | y4l y4h |
5619 * | y5l y5h | y6l y6h | y7l y7h | y8l y8h |
5621 * The returned result would be the following 4 32-bit components unshuffled:
5623 * | x1l | x2l | x3l | x4l | x5l | x6l | x7l | x8l |
5624 * | x1h | x2h | x3h | x4h | x5h | x6h | x7h | x8h |
5625 * | y1l | y2l | y3l | y4l | y5l | y6l | y7l | y8l |
5626 * | y1h | y2h | y3h | y4h | y5h | y6h | y7h | y8h |
5628 * - Source and destination register must not be overlapped.
5629 * - components units are measured in terms of the smaller type between
5630 * source and destination because we are un/shuffling the smaller
5631 * components from/into the bigger ones.
5632 * - first_component parameter allows skipping source components.
5635 shuffle_src_to_dst(const fs_builder
&bld
,
5638 uint32_t first_component
,
5639 uint32_t components
)
5641 if (type_sz(src
.type
) == type_sz(dst
.type
)) {
5642 assert(!regions_overlap(dst
,
5643 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5644 offset(src
, bld
, first_component
),
5645 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5646 for (unsigned i
= 0; i
< components
; i
++) {
5647 bld
.MOV(retype(offset(dst
, bld
, i
), src
.type
),
5648 offset(src
, bld
, i
+ first_component
));
5650 } else if (type_sz(src
.type
) < type_sz(dst
.type
)) {
5651 /* Source is shuffled into destination */
5652 unsigned size_ratio
= type_sz(dst
.type
) / type_sz(src
.type
);
5653 assert(!regions_overlap(dst
,
5654 type_sz(dst
.type
) * bld
.dispatch_width() *
5655 DIV_ROUND_UP(components
, size_ratio
),
5656 offset(src
, bld
, first_component
),
5657 type_sz(src
.type
) * bld
.dispatch_width() * components
));
5659 brw_reg_type shuffle_type
=
5660 brw_reg_type_from_bit_size(8 * type_sz(src
.type
),
5661 BRW_REGISTER_TYPE_D
);
5662 for (unsigned i
= 0; i
< components
; i
++) {
5663 fs_reg shuffle_component_i
=
5664 subscript(offset(dst
, bld
, i
/ size_ratio
),
5665 shuffle_type
, i
% size_ratio
);
5666 bld
.MOV(shuffle_component_i
,
5667 retype(offset(src
, bld
, i
+ first_component
), shuffle_type
));
5670 /* Source is unshuffled into destination */
5671 unsigned size_ratio
= type_sz(src
.type
) / type_sz(dst
.type
);
5672 assert(!regions_overlap(dst
,
5673 type_sz(dst
.type
) * bld
.dispatch_width() * components
,
5674 offset(src
, bld
, first_component
/ size_ratio
),
5675 type_sz(src
.type
) * bld
.dispatch_width() *
5676 DIV_ROUND_UP(components
+ (first_component
% size_ratio
),
5679 brw_reg_type shuffle_type
=
5680 brw_reg_type_from_bit_size(8 * type_sz(dst
.type
),
5681 BRW_REGISTER_TYPE_D
);
5682 for (unsigned i
= 0; i
< components
; i
++) {
5683 fs_reg shuffle_component_i
=
5684 subscript(offset(src
, bld
, (first_component
+ i
) / size_ratio
),
5685 shuffle_type
, (first_component
+ i
) % size_ratio
);
5686 bld
.MOV(retype(offset(dst
, bld
, i
), shuffle_type
),
5687 shuffle_component_i
);
5693 shuffle_from_32bit_read(const fs_builder
&bld
,
5696 uint32_t first_component
,
5697 uint32_t components
)
5699 assert(type_sz(src
.type
) == 4);
5701 /* This function takes components in units of the destination type while
5702 * shuffle_src_to_dst takes components in units of the smallest type
5704 if (type_sz(dst
.type
) > 4) {
5705 assert(type_sz(dst
.type
) == 8);
5706 first_component
*= 2;
5710 shuffle_src_to_dst(bld
, dst
, src
, first_component
, components
);
5714 setup_imm_df(const fs_builder
&bld
, double v
)
5716 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
5717 assert(devinfo
->gen
>= 7);
5719 if (devinfo
->gen
>= 8)
5720 return brw_imm_df(v
);
5722 /* gen7.5 does not support DF immediates straighforward but the DIM
5723 * instruction allows to set the 64-bit immediate value.
5725 if (devinfo
->is_haswell
) {
5726 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5727 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
5728 ubld
.DIM(dst
, brw_imm_df(v
));
5729 return component(dst
, 0);
5732 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
5733 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
5734 * the high 32-bit to suboffset 4 and then applying a stride of 0.
5736 * Alternatively, we could also produce a normal VGRF (without stride 0)
5737 * by writing to all the channels in the VGRF, however, that would hit the
5738 * gen7 bug where we have to split writes that span more than 1 register
5739 * into instructions with a width of 4 (otherwise the write to the second
5740 * register written runs into an execmask hardware bug) which isn't very
5753 const fs_builder ubld
= bld
.exec_all().group(1, 0);
5754 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
5755 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
5756 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
5758 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);
5762 setup_imm_b(const fs_builder
&bld
, int8_t v
)
5764 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_B
);
5765 bld
.MOV(tmp
, brw_imm_w(v
));
5770 setup_imm_ub(const fs_builder
&bld
, uint8_t v
)
5772 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UB
);
5773 bld
.MOV(tmp
, brw_imm_uw(v
));